K1Guitar/tools/test_amp_reg_ble.py

#!/usr/bin/env python3
"""BLE SysEx test: AD85050 CH2 EQ RAM 0xA0..0xAE read/write."""

from __future__ import annotations

import argparse
import sys
import time

from test_protocol_app_sim import Results, build, expect, hexs
from test_protocol_ble import BleMidiSim, DEFAULT_NAME


def u24_nibs(v: int) -> list[int]:
    return [(v >> s) & 0x0F for s in (20, 16, 12, 8, 4, 0)]


def nibs_u24(n) -> int:
    v = 0
    for x in n:
        v = (v << 4) | (x & 0x0F)
    return v


def reg_nibs(reg: int) -> tuple[int, int]:
    return (reg >> 4) & 0x0F, reg & 0x0F


def main() -> int:
    if hasattr(sys.stdout, "reconfigure"):
        try:
            sys.stdout.reconfigure(encoding="utf-8", errors="replace")
        except Exception:
            pass

    ap = argparse.ArgumentParser(description="K1 功放寄存器 BLE 读写测试")
    ap.add_argument("--ble-name", default=DEFAULT_NAME)
    ap.add_argument("--ble-address")
    ap.add_argument("--no-unpair", action="store_true")
    args = ap.parse_args()

    print(f"连接 BLE {args.ble_name!r} {args.ble_address or ''} ...", flush=True)
    sim = BleMidiSim(
        name=args.ble_name,
        address=args.ble_address,
        transport="midi",
        unpair=not args.no_unpair,
    )
    R = Results()
    try:
        print(
            f"已连接 {sim.info.get('name')} {sim.info.get('address')}",
            flush=True,
        )

        r = sim.query(build(0x01, 0x01), timeout=2.0)
        ok, d = expect(r, (0x60, 0x01, 0x01), 6)
        R.add("01 01 连接探测", "PASS" if ok else "FAIL", d)

        targets = (
            (0xA0, "CH2EQ16A1"),
            (0xA4, "CH2EQ16A0"),
            (0xA5, "CH2EQ17A1"),
            (0xA9, "CH2EQ17A0"),
            (0xAA, "CH2EQ18A1"),
            (0xAE, "CH2EQ18A0"),
        )
        originals: dict[int, int] = {}

        for reg, name in targets:
            rh, rl = reg_nibs(reg)
            r = sim.query(build(0x07, 0x00, rh, rl), timeout=1.5)
            ok, d = expect(r, (0x60, 0x07, 0x00, rh, rl), 13)
            if ok:
                val = nibs_u24(r[6:12])
                originals[reg] = val
                d += f"  {name}=0x{val:06X}"
            R.add(f"07 00 读 0x{reg:02X} {name}", "PASS" if ok else "FAIL", d)

        probe = 0x123456
        if 0xA4 in originals:
            rh, rl = reg_nibs(0xA4)
            r = sim.query(build(0x07, 0x01, rh, rl, *u24_nibs(probe)), timeout=1.5)
            ok, d = expect(r, (0x60, 0x07, 0x01, rh, rl), 13)
            if ok:
                got = nibs_u24(r[6:12])
                ok = got == probe
                d += f"  wrote=0x{probe:06X} echo=0x{got:06X}"
            R.add("07 01 写 0xA4=0x123456", "PASS" if ok else "FAIL", d)

            r = sim.query(build(0x07, 0x00, rh, rl), timeout=1.5)
            ok = r is not None and len(r) == 13 and nibs_u24(r[6:12]) == probe
            R.add("07 00 回读 0xA4=0x123456", "PASS" if ok else "FAIL", hexs(r))

            r = sim.query(
                build(0x07, 0x01, rh, rl, *u24_nibs(originals[0xA4])), timeout=1.5
            )
            ok = r is not None and len(r) == 13 and nibs_u24(r[6:12]) == originals[0xA4]
            R.add(
                f"07 01 恢复 0xA4=0x{originals[0xA4]:06X}",
                "PASS" if ok else "FAIL",
                hexs(r),
            )
        else:
            R.add("07 01 写 0xA4", "SKIP", "读 0xA4 失败")
            R.add("07 00 回读 0xA4", "SKIP", "读 0xA4 失败")
            R.add("07 01 恢复 0xA4", "SKIP", "读 0xA4 失败")

        rh, rl = reg_nibs(0xB0)
        r = sim.query(build(0x07, 0x00, rh, rl), timeout=1.5)
        ok = r is not None and len(r) == 8 and r[3] == 0x00 and r[6] == 0x7F
        R.add("07 00 非法地址 0xB0", "PASS" if ok else "FAIL", hexs(r))

        time.sleep(0.05)
        return R.summary()
    finally:
        sim.close()


if __name__ == "__main__":
    raise SystemExit(main())