Initial commit: YNGJ-GT1-M K1电吉他 AT32F403ARCT7 嵌入式源码
包含 IAR 工程、Bootloader、RT-Thread、应用层及外设驱动源码。 Co-authored-by: Cursor <cursoragent@cursor.com>
This commit is contained in:
yuquanjun
commit
3302c92f5a
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@ -0,0 +1,42 @@
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# IAR Embedded Workbench build outputs
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**/Obj/
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**/Exe/
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**/List/
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*.dep
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*.pbi
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*.pbi.cout
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*.o
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*.out
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*.hex
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*.bin
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*.sim
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# IAR workspace user settings (machine-specific)
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*.wsdt
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*.wspos
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*.dni
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*.dbgdt
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*.crun
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*.browse
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*.xcl
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*.cspy.bat
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# Backup and temp files
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*~
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*.bak
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*.tmp
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*.swp
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Thumbs.db
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Desktop.ini
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.DS_Store
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# IDE
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.vscode/
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.idea/
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# Secrets
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.env
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.env.*
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*.key
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*.pem
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credentials.json
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@ -0,0 +1,517 @@
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#include "includes.h"
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/* ==================== <20>ⲿ<EFBFBD><E2B2BF><EFBFBD><EFBFBD> ==================== */
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extern void SendNoteOnMidiEvent(uint8_t Key, uint8_t OnVal);
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extern void SendNoteOffMidiEvent(uint8_t Key, uint8_t OffVal);
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extern uint8_t get_note_by_channel(uint8_t ch);
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extern bool powon;
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extern bool InModeFlag;
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uint8_t get_note_by_channel(uint8_t ch)
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{
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switch(ch)
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{
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case 0: return USE_MIDI.Midi_5; // 5<><35>
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case 1: return USE_MIDI.Midi_4; // 4<><34>
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case 2: return USE_MIDI.Midi_3; // 3<><33>
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case 3: return USE_MIDI.Midi_6; // 6<><36>
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case 4: return USE_MIDI.Midi_1; // 1<><31>
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case 6: return USE_MIDI.Midi_2; // 2<><32>
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default: return 0x3C;
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}
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}
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static uint8_t string_state[7] = {0};
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/* <20><>Ƭ״̬<D7B4><CCAC> */
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typedef enum {
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PICK_STATE_IDLE,
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PICK_STATE_DOWN,
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PICK_STATE_UP
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} pick_state_t;
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typedef enum {
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PICK_FSM_STATE_IDLE,
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PICK_FSM_STATE_DOWN,
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PICK_FSM_STATE_UP,
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PICK_FSM_STATE_UP_LONG,
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} pick_fsm_state_t;
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static pick_fsm_state_t pick_fsm = PICK_FSM_STATE_IDLE;
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static pick_state_t pick_prev = PICK_STATE_IDLE;
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static pick_state_t pick_curr = PICK_STATE_IDLE;
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bool pick_hold_up = 0;
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static uint32_t pick_hold_tick = 0;
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#define PICK_LONG_PRESS_MS 200
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static uint8_t key_stable_flag[4] = {0};
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bool usb_charging_state = 0;
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bool usb_charging_laststate = 0;
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/* <20><><EFBFBD><EFBFBD> */
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static uint16_t vol_last = 0xFFFF;
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uint8_t level = 0;
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/* <20><><EFBFBD> */
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#define BAT_SAMPLE_COUNT 20
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static uint16_t bat_buffer[BAT_SAMPLE_COUNT] = {0};
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static uint8_t bat_index = 0;
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static uint32_t bat_sum = 0;
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uint8_t percentage = 0;
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//static uint32_t charge_step_tick = 0;
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#define VBAT_MIN_RAW 2520
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#define VBAT_MAX_RAW 3528
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/* ==================== ͨ<><CDA8>0~4,6<><36><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD> ==================== */
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static void app_adc_string_process(uint8_t channel)
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{
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uint16_t adc_val = ADC_ReadChannel(ADC_CHANNEL_0) >> 5;
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uint8_t vel_out = 80;
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if (adc_val >= 127) {
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/* δ<><CEB4><EFBFBD><EFBFBD> <20><> Note Off */
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if (string_state[channel]) {
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string_state[channel] = 0;
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//SendNoteOffMidiEvent(get_note_by_channel(channel), 0x00);
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}
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} else {
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/* <20><><EFBFBD><EFBFBD> <20><> <20><><EFBFBD><EFBFBD> */
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if (adc_val <= 20)
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vel_out = 127;
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else {
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uint16_t delta = adc_val - 20;
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vel_out = 127 - delta * 57 / 110;
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}
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if (!string_state[channel]) {
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string_state[channel] = 1;
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SendNoteOnMidiEvent(get_note_by_channel(channel), vel_out);
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}
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}
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}
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pick_state_t app_adc_get_pick_input(void)
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{
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uint16_t adc_val = ADC_ReadChannel(ADC_CHANNEL_0);
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pick_prev = pick_curr;
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if (adc_val <= 1000)
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pick_curr = PICK_STATE_DOWN;
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else if (adc_val >= 3800)
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pick_curr = PICK_STATE_UP;
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else
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pick_curr = PICK_STATE_IDLE;
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return pick_curr;
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}
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static void app_adc_pick_process(void)
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{
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pick_state_t curstate = app_adc_get_pick_input();
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uint32_t now = rt_tick_get();
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uint32_t hold_tick;
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switch(pick_fsm)
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{
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case PICK_FSM_STATE_IDLE:
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if(curstate == PICK_STATE_DOWN)
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{
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pick_hold_tick = now;
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pick_fsm = PICK_FSM_STATE_DOWN;
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}
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if(curstate == PICK_STATE_UP)
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{
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pick_hold_tick = now;
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pick_fsm = PICK_FSM_STATE_UP;
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}
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break;
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case PICK_FSM_STATE_DOWN:
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if(curstate != PICK_STATE_DOWN)
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{
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pick_fsm = PICK_FSM_STATE_IDLE;
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//发送下拨消息
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MainTask_Sendmsg(MSG_ID_BP_KEY,PICK_STATE_DOWN,0,0);
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}
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break;
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case PICK_FSM_STATE_UP:
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if(curstate != PICK_STATE_UP)
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{
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pick_fsm = PICK_FSM_STATE_IDLE;
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//发送上拨消息
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}else
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{
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hold_tick = now - pick_hold_tick;
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if(hold_tick > PICK_LONG_PRESS_MS && !pick_hold_up)
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{
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pick_hold_up = 1;
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pick_fsm = PICK_FSM_STATE_UP_LONG;
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//发送长按消息
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}
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}
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break;
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case PICK_FSM_STATE_UP_LONG:
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/* 长按已发过，等释放回 IDLE */
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if(curstate != PICK_STATE_UP)
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{
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pick_fsm = PICK_FSM_STATE_IDLE;
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pick_hold_up = 0;
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//发送上拨消息
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}
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break;
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}
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}
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/* ==================== ADC1 in0~3 ==================== */
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static void app_adc_key_process(uint8_t idx)
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{
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static uint8_t debounce_cnt[4] = {0}; // 每个按键独立消抖计数
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uint16_t val = ADC_ReadChannel(ADC_CHANNEL_1);
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// 按下判定：连续多次采样小于1000
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if (val < 1000)
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{
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if (!key_stable_flag[idx])
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{
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if (++debounce_cnt[idx] >= 3) // 连续3次满足，判定按下
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{
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key_stable_flag[idx] = 1;
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ADC_IN1_KEY_Handle(idx, 1);
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debounce_cnt[idx] = 0;
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}
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}
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else
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{
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debounce_cnt[idx] = 0;
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}
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}
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// 释放判定：连续多次采样大于2000
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else if (val > 2000)
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{
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if (key_stable_flag[idx])
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{
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if (++debounce_cnt[idx] >= 3) // 连续3次满足，判定释放
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{
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key_stable_flag[idx] = 0;
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debounce_cnt[idx] = 0;
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}
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}
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else
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{
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debounce_cnt[idx] = 0;
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}
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}
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// 中间迟滞区间，保持原状态，不做处理
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}
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/* ==================== ADC1 in4 ==================== */
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static void app_adc_charge_process(void)
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{
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uint16_t val = ADC_ReadChannel(ADC_CHANNEL_1) >> 5;
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/* 插入充电：阈值80，仅状态跳变时执行一次 */
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if (val > 80)
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{
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if (usb_charging_state != 1)
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{
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usb_charging_state = 1;
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if (powon)
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{
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MainTask_Sendmsg(MSG_ID_CHARG, usb_charging_state, usb_charging_laststate, 0);
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}
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usb_charging_laststate = 1;
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}
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}
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/* 拔掉充电：阈值40，迟滞防抖，仅状态跳变时执行一次 */
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else if (val < 40)
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{
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if (usb_charging_state != 0)
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{
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usb_charging_state = 0;
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// 开机场景：发送状态消息
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if (powon)
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{
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MainTask_Sendmsg(MSG_ID_CHARG, usb_charging_state, usb_charging_laststate, 0);
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}
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// 关机场景：直接切断主电源
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else
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{
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BSP_MainPowerEnable(0);
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}
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usb_charging_laststate = 0;
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}
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}
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}
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/* ==================== ADC1 in5 ==================== */
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static void app_adc_hp_process(void)
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{
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uint16_t val = ADC_ReadChannel(ADC_CHANNEL_1) >> 5;
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if (val > 50) {
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MainTask_Sendmsg(MSG_ID_HP_SPK_IN, 1, 0, 0);
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} else {
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MainTask_Sendmsg(MSG_ID_HP_SPK_IN, 1, 0, 0);
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}
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}
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/* ==================== ADC1 in6 ==================== */
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static void app_adc_volume_process(void)
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{
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uint16_t val = ADC_ReadChannel(ADC_CHANNEL_1)>>5;
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if(abs((int16_t)vol_last - (int16_t)val) > 2)
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{
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vol_last = val;
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/* <20><> 6 <20><> */
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if (val <= 5) level = 0;
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else if (val <= 35) level = 1;
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else if (val <= 65) level = 2;
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else if (val <= 95) level = 3;
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else if (val <= 115) level = 4;
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else level = 5;
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MainTask_Sendmsg(MSG_ID_EC_VOL, val, level, 0);
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}
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}
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/* ==================== ADC1 ͨ<><CDA8>7<EFBFBD><37><EFBFBD><EFBFBD><EFBFBD> ==================== */
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static bat_state_t bat_state = BAT_IDLE;
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static uint32_t bat_last_sample_tick = 0; /* 上次采样时刻 */
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static uint32_t bat_state_tick = 0; /* 进当前状态的时刻 */
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static uint8_t bat_charge_paused = 0; /* 本次是否暂停了充电 */
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static uint8_t bat_poweron_done = 0; /* 开机首采标志 */
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static uint8_t bat_sample_cnt = 0; /* SAMPLE 内已采了几个 */
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static uint32_t bat_sample_tick = 0; /* SAMPLE 内上次采样的时刻 */
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/* ==================== <20><>ʼ<EFBFBD><CABC> ==================== */
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void app_adc_init(void)
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{
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for (int i = 0; i < 7; i++) string_state[i] = 0;
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for (int i = 0; i < 4; i++) key_stable_flag[i] = 0;
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pick_prev = pick_curr = PICK_STATE_IDLE;
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pick_hold_up = 0;
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usb_charging_state = 0;
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vol_last = 0xFFFF; level = 0;
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bat_index = 0; bat_sum = 0; percentage = 0;
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for (int i = 0; i < BAT_SAMPLE_COUNT; i++) bat_buffer[i] = 0;
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/* 电池状态机复位：下次开机触发首采 */
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bat_state = BAT_IDLE;
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bat_last_sample_tick = 0;
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bat_charge_paused = 0;
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bat_poweron_done = 0;
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bat_sample_cnt = 0;
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bat_sample_tick = 0;
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}
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/* 采样：读 ADC + 滑动平均 */
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static void app_adc_battery_do_sample(void)
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{
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uint16_t adc_raw = ADC_ReadChannel(ADC_CHANNEL_1);
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bat_sum -= bat_buffer[bat_index];
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bat_buffer[bat_index] = adc_raw;
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bat_sum += bat_buffer[bat_index];
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bat_index = (bat_index + 1) % BAT_SAMPLE_COUNT;
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}
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/* 上报：映射成百分比，变化才发消息 */
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static void app_adc_battery_report(void)
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{
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uint16_t filtered = bat_sum / BAT_SAMPLE_COUNT;
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uint8_t pct;
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if (filtered < VBAT_MIN_RAW)
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pct = 0;
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else if (filtered > VBAT_MAX_RAW)
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pct = 100;
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else
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pct = 100 * (filtered - VBAT_MIN_RAW) / (VBAT_MAX_RAW - VBAT_MIN_RAW);
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pct = (pct / 10) * 10;
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|
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if (pct != percentage) { /* 变化才上报 */
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percentage = pct;
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if(usb_charging_state && !powon)
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{
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MainTask_Sendmsg(MSG_ID_POWOFF_CHARG, percentage, usb_charging_state, 0);
|
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}
|
||||
else
|
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{
|
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MainTask_Sendmsg(MSG_ID_BATTERY_VALUE, percentage, usb_charging_state, 0);
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}
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}
|
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}
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|
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/* 电池采集状态机入口（app_adc_scan 每 1ms 调用，状态推进约每 10ms 一次） */
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static void app_adc_battery_process(void)
|
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{
|
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uint32_t now = rt_tick_get();
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|
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switch (bat_state)
|
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{
|
||||
case BAT_IDLE:
|
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/* 触发：开机后首采，或距上次 ≥30s */
|
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if (/*powon && */!bat_poweron_done)
|
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{
|
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bat_poweron_done = 1;
|
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bat_state = BAT_START;
|
||||
}
|
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else if (now - bat_last_sample_tick >= BAT_SAMPLE_INTERVAL_MS)
|
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{
|
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bat_state = BAT_START;
|
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}
|
||||
break;
|
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case BAT_START:
|
||||
if (usb_charging_state) /* 充电中：先停充电，采真实电压 */
|
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{
|
||||
BSP_ChargerEnable(0);
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bat_charge_paused = 1;
|
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bat_state_tick = now;
|
||||
bat_state = BAT_WAIT_CHARGE_OFF;
|
||||
}
|
||||
else
|
||||
{
|
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bat_charge_paused = 0;
|
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bat_state = BAT_SAMPLE;
|
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}
|
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break;
|
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|
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case BAT_WAIT_CHARGE_OFF:
|
||||
if (now - bat_state_tick >= BAT_CHARGE_OFF_WAIT_MS)
|
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bat_state = BAT_SAMPLE;
|
||||
break;
|
||||
|
||||
case BAT_SAMPLE:
|
||||
/* 连续采满 BAT_SAMPLE_COUNT 次（间隔 10ms），填满滑动平均 buffer */
|
||||
if (now - bat_sample_tick >= 10)
|
||||
{
|
||||
app_adc_battery_do_sample();
|
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bat_sample_cnt++;
|
||||
bat_sample_tick = now;
|
||||
}
|
||||
if (bat_sample_cnt >= BAT_SAMPLE_COUNT)
|
||||
{
|
||||
bat_sample_cnt = 0; /* 采满，进入收尾 */
|
||||
if (bat_charge_paused)
|
||||
bat_state = BAT_RESTORE_CHARGE;
|
||||
else
|
||||
bat_state = BAT_DONE;
|
||||
}
|
||||
break;
|
||||
|
||||
case BAT_RESTORE_CHARGE:
|
||||
BSP_ChargerEnable(1); /* 恢复充电 */
|
||||
bat_charge_paused = 0;
|
||||
bat_state = BAT_DONE;
|
||||
break;
|
||||
|
||||
case BAT_DONE:
|
||||
app_adc_battery_report();
|
||||
bat_last_sample_tick = now;
|
||||
bat_state = BAT_IDLE;
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
void app_adc_scan_all(void)
|
||||
{
|
||||
static uint8_t channel = 0;
|
||||
|
||||
BSP_SelectAdcChannel(channel);
|
||||
Delay_us(10);
|
||||
|
||||
// adc_in 0
|
||||
|
||||
switch (channel)
|
||||
{
|
||||
case 0: case 1: case 2: case 3: case 4: case 6:
|
||||
if(!InModeFlag) break;
|
||||
app_adc_string_process(channel);
|
||||
break;
|
||||
case 7:
|
||||
if(!InModeFlag) break;
|
||||
app_adc_pick_process();
|
||||
break;
|
||||
}
|
||||
|
||||
|
||||
// adc_in 1
|
||||
switch (channel)
|
||||
{
|
||||
case 0: case 1: case 2: case 3:
|
||||
if(!InModeFlag) break;
|
||||
app_adc_key_process(channel);
|
||||
break;
|
||||
case 4:
|
||||
app_adc_charge_process();
|
||||
break;
|
||||
case 5:
|
||||
if(!InModeFlag) break;
|
||||
app_adc_hp_process();
|
||||
break;
|
||||
case 6:
|
||||
app_adc_volume_process();
|
||||
break;
|
||||
case 7:
|
||||
app_adc_battery_process();
|
||||
break;
|
||||
}
|
||||
if(channel < 8)
|
||||
{
|
||||
channel++;
|
||||
}else
|
||||
{
|
||||
channel = 0;
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
void app_adc_in1_scan_part(uint8_t channel)
|
||||
{
|
||||
BSP_SelectAdcChannel(channel);
|
||||
Delay_us(10);
|
||||
|
||||
// adc_in 1
|
||||
switch (channel)
|
||||
{
|
||||
case 0: case 1: case 2: case 3:
|
||||
app_adc_key_process(channel);
|
||||
break;
|
||||
case 4:
|
||||
app_adc_charge_process();
|
||||
break;
|
||||
case 5:
|
||||
app_adc_hp_process();
|
||||
break;
|
||||
case 6:
|
||||
app_adc_volume_process();
|
||||
break;
|
||||
case 7:
|
||||
app_adc_battery_process();
|
||||
break;
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
|
||||
|
|
@ -0,0 +1,27 @@
|
|||
#ifndef __APP_ADC_H__
|
||||
#define __APP_ADC_H__
|
||||
|
||||
|
||||
/* 电池采集状态机
|
||||
* 开机后首采一次 → 之后每 30s 采一次
|
||||
* 充电中：先停充电芯片 → 等稳定 → 采集 → 恢复充电
|
||||
* 电压变化才上报 MSG_ID_BATTERY_VALUE */
|
||||
#define BAT_SAMPLE_INTERVAL_MS 30000 /* 30s 采集一次 */
|
||||
#define BAT_CHARGE_OFF_WAIT_MS 50 /* 停充电后等稳定 */
|
||||
|
||||
typedef enum {
|
||||
BAT_IDLE, /* 空闲：等开机首采 / 30s 定时 */
|
||||
BAT_START, /* 开始：检查是否需停充电 */
|
||||
BAT_WAIT_CHARGE_OFF, /* 等充电芯片停止稳定 */
|
||||
BAT_SAMPLE, /* 读 ADC + 滑动平均 */
|
||||
BAT_RESTORE_CHARGE, /* 恢复充电 */
|
||||
BAT_DONE, /* 映射 + 上报，回 IDLE */
|
||||
} bat_state_t;
|
||||
|
||||
extern bool pick_hold_up;
|
||||
extern bool usb_charging_state;
|
||||
extern bool usb_charging_laststate;
|
||||
extern uint8_t percentage;
|
||||
void app_adc_scan_all(void);
|
||||
void app_adc_in1_scan_part(uint8_t channel);
|
||||
#endif
|
||||
|
|
@ -0,0 +1,85 @@
|
|||
#include "includes.h"
|
||||
|
||||
/* ==================== 氛围灯循环状态 ==================== */
|
||||
#define RGB_INTERVAL_MS 300 /* 颜色切换间隔 300ms */
|
||||
|
||||
static const uint8_t auto_rgb_seq[] = {
|
||||
COLOR_CYA, /* 青 */
|
||||
COLOR_B, /* 蓝 */
|
||||
COLOR_G, /* 绿 */
|
||||
COLOR_R, /* 红 */
|
||||
};
|
||||
#define AUTO_RGB_CNT (sizeof(auto_rgb_seq)/sizeof(auto_rgb_seq[0]))
|
||||
|
||||
static uint8_t rgb_state = 0;
|
||||
static uint32_t rgb_tick_stamp = 0;
|
||||
|
||||
static uint8_t key_last = KEY_NULL;
|
||||
|
||||
void app_tm1617_init(void)
|
||||
{
|
||||
rt_mutex_take(TM1617_Mutex, RT_WAITING_FOREVER);
|
||||
TM1617_Init(); /* 清零 + 显示模式 + 初始亮度 */
|
||||
TM1617_SetRGB(COLOR_OFF, 0); /* 确保熄灭 */
|
||||
rt_mutex_release(TM1617_Mutex);
|
||||
|
||||
rgb_state = 0;
|
||||
rgb_tick_stamp = 0;
|
||||
key_last = KEY_NULL;
|
||||
}
|
||||
|
||||
void app_tm1617_set_rgb(uint8_t color, uint8_t brightness)
|
||||
{
|
||||
if (brightness > 7)
|
||||
brightness = 7;
|
||||
|
||||
rt_mutex_take(TM1617_Mutex, RT_WAITING_FOREVER);
|
||||
TM1617_SetRGB(color, brightness);
|
||||
rt_mutex_release(TM1617_Mutex);
|
||||
}
|
||||
|
||||
void app_tm1617_off(void)
|
||||
{
|
||||
rt_mutex_take(TM1617_Mutex, RT_WAITING_FOREVER);
|
||||
TM1617_SetRGB(COLOR_OFF, 0);
|
||||
rt_mutex_release(TM1617_Mutex);
|
||||
}
|
||||
|
||||
/* 氛围灯自动循环：300ms 切换一次颜色 */
|
||||
void app_tm1617_auto_loop(void)
|
||||
{
|
||||
uint32_t now = rt_tick_get();
|
||||
|
||||
if ((now - rgb_tick_stamp) >= RGB_INTERVAL_MS)
|
||||
{
|
||||
rgb_tick_stamp = now;
|
||||
|
||||
if (rgb_state >= AUTO_RGB_CNT)
|
||||
rgb_state = 0;
|
||||
|
||||
rt_mutex_take(TM1617_Mutex, RT_WAITING_FOREVER);
|
||||
TM1617_SetRGB(auto_rgb_seq[rgb_state], 7);
|
||||
rt_mutex_release(TM1617_Mutex);
|
||||
|
||||
rgb_state++;
|
||||
if (rgb_state >= AUTO_RGB_CNT)
|
||||
rgb_state = 0;
|
||||
}
|
||||
}
|
||||
|
||||
uint8_t app_tm1617_scan_key(void)
|
||||
{
|
||||
uint8_t key;
|
||||
|
||||
rt_mutex_take(TM1617_Mutex, RT_WAITING_FOREVER);
|
||||
key = (uint8_t)TM1617_ScanFkey();
|
||||
rt_mutex_release(TM1617_Mutex);
|
||||
|
||||
if (key != key_last)
|
||||
{
|
||||
key_last = key;
|
||||
TM1617_Handle(key);
|
||||
return key;
|
||||
}
|
||||
return KEY_NULL;
|
||||
}
|
||||
|
|
@ -0,0 +1,14 @@
|
|||
#ifndef APP_TM1617_H
|
||||
#define APP_TM1617_H
|
||||
|
||||
void app_tm1617_init(void);
|
||||
|
||||
void app_tm1617_set_rgb(uint8_t color, uint8_t brightness);
|
||||
|
||||
void app_tm1617_off(void);
|
||||
|
||||
void app_tm1617_auto_loop(void);
|
||||
|
||||
uint8_t app_tm1617_scan_key(void);
|
||||
|
||||
#endif /* APP_TM1617_H */
|
||||
|
|
@ -0,0 +1,105 @@
|
|||
#include "includes.h"
|
||||
|
||||
static uint8_t key_last = KEY_NONE;
|
||||
|
||||
|
||||
/* LED 期望颜色缓存：索引 = LedNum_TypeDef（0~7），COLOR_OTHER 表示灭 */
|
||||
//static LedColor_TypeDef led_cache[8] = {
|
||||
// COLOR_OTHER, COLOR_OTHER, COLOR_OTHER, COLOR_OTHER,
|
||||
// COLOR_OTHER, COLOR_OTHER, COLOR_OTHER, COLOR_OTHER
|
||||
//};
|
||||
|
||||
void app_tm1629_init(void)
|
||||
{
|
||||
rt_mutex_take(TM1629_Mutex, RT_WAITING_FOREVER);
|
||||
TM1629D_Key_LED_Init();
|
||||
TM1629D_AllLedOff();
|
||||
TM1629D_UpdateDisplay(0);
|
||||
rt_mutex_release(TM1629_Mutex);
|
||||
}
|
||||
|
||||
uint8_t app_tm1629_Scan_Key(void)
|
||||
{
|
||||
uint8_t key = 0;
|
||||
|
||||
//static uint8_t Last_Tm1926D_Key = 0;
|
||||
|
||||
rt_mutex_take(TM1629_Mutex, RT_WAITING_FOREVER);
|
||||
key = TM1629D_GetKey();
|
||||
rt_mutex_release(TM1629_Mutex);
|
||||
|
||||
if(key != key_last)
|
||||
{
|
||||
key_last = key;
|
||||
TM1629_Handle(key);
|
||||
return key;
|
||||
}
|
||||
return KEY_NONE;
|
||||
}
|
||||
|
||||
|
||||
static void app_tm1629_led_set(LedNum_TypeDef led, LedColor_TypeDef color, uint8_t on)
|
||||
{
|
||||
if(on)
|
||||
{
|
||||
//if(led_cache[led] == color) return;
|
||||
//led_cache[led] = color;
|
||||
TM1629D_ControlLed(led, color, 1);
|
||||
}
|
||||
else
|
||||
{
|
||||
//if(led_cache[led] == color) return;
|
||||
//led_cache[led] = COLOR_OTHER;
|
||||
TM1629D_ControlLed(led, COLOR_OTHER, 1);
|
||||
}
|
||||
TM1629D_UpdateDisplay(0);
|
||||
}
|
||||
|
||||
|
||||
void app_tm1629_set_chord_led(uint8_t key_idx, LedColor_TypeDef color)
|
||||
{
|
||||
if(key_idx < 1 || key_idx > 21) return;
|
||||
|
||||
LedNum_TypeDef led = (LedNum_TypeDef)((key_idx - 1) / 3); //L1-L7
|
||||
|
||||
rt_mutex_take(TM1629_Mutex, RT_WAITING_FOREVER);
|
||||
app_tm1629_led_set(led,color,1);
|
||||
rt_mutex_release(TM1629_Mutex);
|
||||
}
|
||||
|
||||
|
||||
void app_tm1629_set_led(LedNum_TypeDef led, LedColor_TypeDef color)
|
||||
{
|
||||
rt_mutex_take(TM1629_Mutex, RT_WAITING_FOREVER);
|
||||
TM1629D_AllLedOff();
|
||||
app_tm1629_led_set(led,color,1);
|
||||
rt_mutex_release(TM1629_Mutex);
|
||||
}
|
||||
|
||||
|
||||
void app_tm1629_all_off(void)
|
||||
{
|
||||
rt_mutex_take(TM1629_Mutex, RT_WAITING_FOREVER);
|
||||
TM1629D_AllLedOff();
|
||||
TM1629D_UpdateDisplay(0);
|
||||
rt_mutex_release(TM1629_Mutex);
|
||||
|
||||
// for (int i = 0; i < 8; i++)
|
||||
// led_cache[i] = COLOR_OTHER;
|
||||
}
|
||||
|
||||
void app_tm1629_all_on(LedColor_TypeDef color)
|
||||
{
|
||||
rt_mutex_take(TM1629_Mutex, RT_WAITING_FOREVER);
|
||||
TM1629D_AllLedOff();
|
||||
TM1629D_AllLedOn(color);
|
||||
TM1629D_UpdateDisplay(0);
|
||||
rt_mutex_release(TM1629_Mutex);
|
||||
|
||||
// for (int i = 0; i < 8; i++)
|
||||
// led_cache[i] = color;
|
||||
}
|
||||
|
||||
|
||||
|
||||
|
||||
|
|
@ -0,0 +1,11 @@
|
|||
#ifndef __APP_TM1629_H__
|
||||
#define __APP_TM1629_H__
|
||||
|
||||
|
||||
void app_tm1629_init(void);
|
||||
uint8_t app_tm1629_Scan_Key(void);
|
||||
void app_tm1629_set_chord_led(uint8_t key_idx, LedColor_TypeDef color);
|
||||
void app_tm1629_set_led(LedNum_TypeDef led, LedColor_TypeDef color);
|
||||
void app_tm1629_all_off(void);
|
||||
void app_tm1629_all_on(LedColor_TypeDef color);
|
||||
#endif
|
||||
|
|
@ -0,0 +1,163 @@
|
|||
#include "includes.h"
|
||||
|
||||
/* ============================================================================
|
||||
* app_touch 实现
|
||||
*
|
||||
* 状态机（与原 Touch_Process 一致）：
|
||||
* IDLE → PRESS_WAIT_STABLE → PRESS_STABLE → SLIDING
|
||||
*
|
||||
* 时序参数：
|
||||
* 稳定判定 20ms (TOUCH_STABLE_TIME)
|
||||
* 滑动阈值 10px (TOUCH_SLIDE_THRESH)
|
||||
* 滑动步进 5px (TOUCH_SLIDE_STEP)
|
||||
* 长按触发 1000ms (TOUCH_LONG_PRESS_TIME)
|
||||
* 长按重复 120ms (TOUCH_REPEAT_INTERVAL)
|
||||
* ==========================================================================*/
|
||||
|
||||
/* ==================== 状态机枚举 ==================== */
|
||||
typedef enum {
|
||||
TOUCH_IDLE, /* 空闲 */
|
||||
TOUCH_PRESS_WAIT_STABLE, /* 按下，等待稳定判定 */
|
||||
TOUCH_PRESS_STABLE, /* 稳定按下（可长按） */
|
||||
TOUCH_SLIDING /* 滑动中 */
|
||||
} touch_state_t;
|
||||
|
||||
/* ==================== 时序参数 ==================== */
|
||||
#define TOUCH_STABLE_TIME 20 /* 按下稳定判定时间 ms */
|
||||
#define TOUCH_SLIDE_THRESH 10 /* 进入滑动的最小位移 px */
|
||||
#define TOUCH_SLIDE_STEP 5 /* 滑动事件最小步进 px */
|
||||
#define TOUCH_LONG_PRESS_TIME 1000 /* 长按触发 ms */
|
||||
#define TOUCH_REPEAT_INTERVAL 120 /* 长按重复间隔 ms */
|
||||
|
||||
/* ==================== 状态变量 ==================== */
|
||||
static touch_state_t touch_state = TOUCH_IDLE;
|
||||
static uint16_t down_x = 0;
|
||||
static uint16_t down_y = 0;
|
||||
static uint32_t touch_tick = 0;
|
||||
static uint32_t repeat_tick = 0;
|
||||
static uint8_t long_press_fired = 0;
|
||||
static uint16_t last_slide_x = 0;
|
||||
static uint16_t last_slide_y = 0;
|
||||
|
||||
/* 取绝对值（避免引入 math.h） */
|
||||
static inline uint16_t abs_diff(int16_t a, int16_t b)
|
||||
{
|
||||
int16_t d = a - b;
|
||||
return (d < 0) ? (uint16_t)(-d) : (uint16_t)d;
|
||||
}
|
||||
|
||||
/* ==================== 重置 ==================== */
|
||||
|
||||
void app_touch_reset(void)
|
||||
{
|
||||
touch_state = TOUCH_IDLE;
|
||||
down_x = down_y = 0;
|
||||
touch_tick = repeat_tick = 0;
|
||||
long_press_fired = 0;
|
||||
last_slide_x = last_slide_y = 0;
|
||||
}
|
||||
|
||||
/* ==================== 手势识别 ==================== */
|
||||
|
||||
app_touch_result_t app_touch_process(uint16_t x, uint16_t y, uint8_t pressed)
|
||||
{
|
||||
app_touch_result_t r;
|
||||
r.gesture = GESTURE_NONE;
|
||||
r.x = x; r.y = y;
|
||||
r.down_x = down_x; r.down_y = down_y;
|
||||
|
||||
uint32_t now = rt_tick_get();
|
||||
|
||||
/* ---------- 抬起处理 ---------- */
|
||||
if (!pressed) {
|
||||
/* 若曾稳定按下且未触发长按 → 释放（可当作 TAP） */
|
||||
if (touch_state == TOUCH_PRESS_STABLE && !long_press_fired) {
|
||||
r.gesture = GESTURE_RELEASE;
|
||||
r.x = down_x; r.y = down_y; /* 用按下点作为释放坐标 */
|
||||
}
|
||||
touch_state = TOUCH_IDLE;
|
||||
down_x = down_y = 0;
|
||||
last_slide_x = last_slide_y = 0;
|
||||
touch_tick = repeat_tick = 0;
|
||||
long_press_fired = 0;
|
||||
return r;
|
||||
}
|
||||
|
||||
/* ---------- 按下处理 ---------- */
|
||||
switch (touch_state)
|
||||
{
|
||||
case TOUCH_IDLE:
|
||||
down_x = x;
|
||||
down_y = y;
|
||||
touch_tick = now;
|
||||
long_press_fired = 0;
|
||||
repeat_tick = 0;
|
||||
touch_state = TOUCH_PRESS_WAIT_STABLE;
|
||||
break;
|
||||
|
||||
case TOUCH_PRESS_WAIT_STABLE:
|
||||
if ((now - touch_tick) >= TOUCH_STABLE_TIME) {
|
||||
/* 位移小 → 进入稳定 */
|
||||
if (abs_diff(x, down_x) < 8 && abs_diff(y, down_y) < 8) {
|
||||
touch_state = TOUCH_PRESS_STABLE;
|
||||
last_slide_x = down_x;
|
||||
last_slide_y = down_y;
|
||||
touch_tick = now;
|
||||
MainTask_Sendmsg(MSG_ID_TOUCH, 1, down_x, down_y);
|
||||
} else {
|
||||
/* 位移大 → 视为误触，回到空闲 */
|
||||
touch_state = TOUCH_IDLE;
|
||||
}
|
||||
}
|
||||
break;
|
||||
|
||||
case TOUCH_PRESS_STABLE:
|
||||
{
|
||||
/* ----- 长按检测 ----- */
|
||||
if (!long_press_fired && (now - touch_tick) >= TOUCH_LONG_PRESS_TIME) {
|
||||
long_press_fired = 1;
|
||||
repeat_tick = now;
|
||||
r.gesture = GESTURE_LONG_PRESS;
|
||||
MainTask_Sendmsg(MSG_ID_TOUCH_LONG_REPEAT, 1, down_x, down_y);
|
||||
return r;
|
||||
}
|
||||
/* ----- 长按重复 ----- */
|
||||
if (long_press_fired && (now - repeat_tick) >= TOUCH_REPEAT_INTERVAL) {
|
||||
repeat_tick = now;
|
||||
r.gesture = GESTURE_REPEAT;
|
||||
MainTask_Sendmsg(MSG_ID_TOUCH_LONG_REPEAT, 1, down_x, down_y);
|
||||
return r;
|
||||
}
|
||||
/* ----- 位移进入滑动 ----- */
|
||||
if (abs_diff(x, down_x) >= TOUCH_SLIDE_THRESH ||
|
||||
abs_diff(y, down_y) >= TOUCH_SLIDE_THRESH) {
|
||||
touch_state = TOUCH_SLIDING;
|
||||
last_slide_x = x;
|
||||
last_slide_y = y;
|
||||
}
|
||||
break;
|
||||
}
|
||||
|
||||
case TOUCH_SLIDING:
|
||||
{
|
||||
/* 位移超过步进 → 产生拖动事件 */
|
||||
if (abs_diff(x, last_slide_x) >= TOUCH_SLIDE_STEP ||
|
||||
abs_diff(y, last_slide_y) >= TOUCH_SLIDE_STEP) {
|
||||
r.gesture = GESTURE_DRAG;
|
||||
r.down_x = last_slide_x; /* 记录上次位置，便于消费端算增量 */
|
||||
r.down_y = last_slide_y;
|
||||
MainTask_Sendmsg(MSG_ID_TOUCH, 1, x, y);
|
||||
last_slide_x = x;
|
||||
last_slide_y = y;
|
||||
return r;
|
||||
}
|
||||
break;
|
||||
}
|
||||
|
||||
default:
|
||||
touch_state = TOUCH_IDLE;
|
||||
break;
|
||||
}
|
||||
|
||||
return r; /* 无手势 */
|
||||
}
|
||||
|
|
@ -0,0 +1,33 @@
|
|||
#ifndef APP_TOUCH_H
|
||||
#define APP_TOUCH_H
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
/* ==================== 手势类型 ==================== */
|
||||
typedef enum {
|
||||
GESTURE_NONE = 0, /* 无手势（状态机未产出） */
|
||||
GESTURE_TAP, /* 单击：稳定按下 + 释放（位移小） */
|
||||
GESTURE_LONG_PRESS, /* 长按：稳定按下超过 1000ms */
|
||||
GESTURE_REPEAT, /* 长按后的重复触发：每 120ms */
|
||||
GESTURE_DRAG, /* 拖动：按下后位移超过阈值 */
|
||||
GESTURE_RELEASE, /* 释放：从按下到抬起（无位移或未触发长按） */
|
||||
} app_touch_gesture_t;
|
||||
|
||||
/* ==================== 手势结果 ==================== */
|
||||
typedef struct {
|
||||
app_touch_gesture_t gesture; /* 产出的手势 */
|
||||
uint16_t x, y; /* 当前坐标 */
|
||||
uint16_t down_x, down_y; /* 按下起点（DRAG/RELEASE 判断用） */
|
||||
} app_touch_result_t;
|
||||
|
||||
/* ==================== 对外 API ==================== */
|
||||
|
||||
/* 重置状态机（页面切换/开机时可选调用） */
|
||||
void app_touch_reset(void);
|
||||
|
||||
/* 核心：喂一个采样点，产出手势。
|
||||
* 由 touch_task 每 20ms 调用一次。
|
||||
* 有手势返回对应 gesture，无手势返回 GESTURE_NONE。 */
|
||||
app_touch_result_t app_touch_process(uint16_t x, uint16_t y, uint8_t pressed);
|
||||
|
||||
#endif /* APP_TOUCH_H */
|
||||
|
|
@ -0,0 +1,132 @@
|
|||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<Root>
|
||||
<MCUInfo>
|
||||
<MCUSerials>AT32F403A</MCUSerials>
|
||||
<MCUName>AT32F403ARCT7</MCUName>
|
||||
<MCUPackage>LQFP64</MCUPackage>
|
||||
</MCUInfo>
|
||||
<ACC>
|
||||
<Mode>
|
||||
<ModeSub name="ACC_State" value="TRUE"/>
|
||||
</Mode>
|
||||
</ACC>
|
||||
<CRM>
|
||||
<Mode>
|
||||
<ModeSub name="HEXT" value="HEXT-External-Oscillator"/>
|
||||
</Mode>
|
||||
<Parameters>
|
||||
<ParametersSub name="HEXT" value="HEXT_CRYSTAL"/>
|
||||
</Parameters>
|
||||
</CRM>
|
||||
<DEBUG>
|
||||
<Mode>
|
||||
<ModeSub name="Debug interface" value="SWD"/>
|
||||
</Mode>
|
||||
</DEBUG>
|
||||
<SPI1>
|
||||
<Mode>
|
||||
<ModeSub name="Mode" value="Full_Duplex_Master"/>
|
||||
</Mode>
|
||||
<Parameters>
|
||||
<ParametersSub name="TransmissionMode" value="SPI_TRANSMIT_FULL_DUPLEX"/>
|
||||
<ParametersSub name="Mode" value="SPI_MODE_MASTER"/>
|
||||
<ParametersSub name="FirstBit" value="SPI_FIRST_BIT_MSB"/>
|
||||
<ParametersSub name="ClockFrequency" value="30000000"/>
|
||||
</Parameters>
|
||||
</SPI1>
|
||||
<SPI2>
|
||||
<Mode>
|
||||
<ModeSub name="Mode" value="Full_Duplex_Master"/>
|
||||
<ModeSub name="CS_Signal" value="CS_Signal_Hard_Output"/>
|
||||
</Mode>
|
||||
<Parameters>
|
||||
<ParametersSub name="TransmissionMode" value="SPI_TRANSMIT_FULL_DUPLEX"/>
|
||||
<ParametersSub name="Mode" value="SPI_MODE_MASTER"/>
|
||||
<ParametersSub name="FirstBit" value="SPI_FIRST_BIT_MSB"/>
|
||||
<ParametersSub name="ClockFrequency" value="30000000"/>
|
||||
<ParametersSub name="VirtualCS" value="SPI_CS_HARDWARE_MODE"/>
|
||||
</Parameters>
|
||||
</SPI2>
|
||||
<SYSTEM>
|
||||
<Mode>
|
||||
<ModeSub name="Time_Base" value="SysTick"/>
|
||||
</Mode>
|
||||
</SYSTEM>
|
||||
<USBFS>
|
||||
<Mode>
|
||||
<ModeSub name="Device" value="TRUE"/>
|
||||
</Mode>
|
||||
</USBFS>
|
||||
<USB_DEVICE>
|
||||
<Mode>
|
||||
<ModeSub name="FS_Device" value="MSC"/>
|
||||
</Mode>
|
||||
<Parameters>
|
||||
<ParametersSub name="DEVICE_FS1_VID" value="0x5259"/>
|
||||
<ParametersSub name="DEVICE_FS1_PID_MSC" value="0x414E"/>
|
||||
<ParametersSub name="DEVICE_FS1_Manufacturer" value="SoundWalker"/>
|
||||
<ParametersSub name="DEVICE_FS1_Product_MSC" value="SoundWalker Mass Storage"/>
|
||||
<ParametersSub name="DEVICE_FS1_Configuration_MSC" value="SoundWalker Storage Config"/>
|
||||
<ParametersSub name="DEVICE_FS1_Interface_MSC" value="SoundWalker Storage Interface"/>
|
||||
</Parameters>
|
||||
</USB_DEVICE>
|
||||
<NVIC>
|
||||
<SysTick_Handler>1;15;0;0;0</SysTick_Handler>
|
||||
<FLASH_IRQHandler>0;0;0;0;0</FLASH_IRQHandler>
|
||||
<CRM_IRQHandler>0;0;0;0;0</CRM_IRQHandler>
|
||||
<SPI1_IRQHandler>0;0;0;0;0</SPI1_IRQHandler>
|
||||
<SPI2_I2S2EXT_IRQHandler>0;0;0;0;0</SPI2_I2S2EXT_IRQHandler>
|
||||
<USBFSWakeUp_IRQHandler>0;0;0;0;0</USBFSWakeUp_IRQHandler>
|
||||
<ACC_IRQHandler>0;0;0;0;0</ACC_IRQHandler>
|
||||
<USBFS_MAPH_IRQHandler>0;0;0;0;0</USBFS_MAPH_IRQHandler>
|
||||
<USBFS_MAPL_IRQHandler>1;0;0;0;0</USBFS_MAPL_IRQHandler>
|
||||
</NVIC>
|
||||
<ClockConfiguration>
|
||||
<rtcsel>0</rtcsel>
|
||||
<hext>12.000000</hext>
|
||||
<hextdiv>2</hextdiv>
|
||||
<pllhextdiv>0</pllhextdiv>
|
||||
<pllrcs>0</pllrcs>
|
||||
<pllmult>20</pllmult>
|
||||
<sclkselect>1</sclkselect>
|
||||
<ahbdiv>1</ahbdiv>
|
||||
<apb1div>2</apb1div>
|
||||
<apb2div>2</apb2div>
|
||||
<usbdiv>4.0</usbdiv>
|
||||
<hicktousb>1</hicktousb>
|
||||
<hicktosclk>0</hicktosclk>
|
||||
<clkout>0</clkout>
|
||||
<clkoutdiv>1</clkoutdiv>
|
||||
<adcdiv>6</adcdiv>
|
||||
<systicsel>8</systicsel>
|
||||
</ClockConfiguration>
|
||||
<PINInfo>
|
||||
<PinSub pinname="PD0/HEXT_IN" signalname="CRM_HEXT_IN" signaltype="2"/>
|
||||
<PinSub pinname="PD1/HEXT_OUT" signalname="CRM_HEXT_OUT" signaltype="2"/>
|
||||
<PinSub pinname="PA5" signalname="SPI1_SCK" signaltype="2"/>
|
||||
<PinSub pinname="PA6" signalname="SPI1_MISO" signaltype="2"/>
|
||||
<PinSub pinname="PA7" signalname="SPI1_MOSI" signaltype="2"/>
|
||||
<PinSub pinname="PB12" signalname="SPI2_CS" signaltype="2"/>
|
||||
<PinSub pinname="PB13" signalname="SPI2_SCK" signaltype="2"/>
|
||||
<PinSub pinname="PB14" signalname="SPI2_MISO" signaltype="2"/>
|
||||
<PinSub pinname="PB15" signalname="SPI2_MOSI" signaltype="2"/>
|
||||
<PinSub pinname="PA11" signalname="USBFS_D-" signaltype="2"/>
|
||||
<PinSub pinname="PA12" signalname="USBFS_D+" signaltype="2"/>
|
||||
<PinSub pinname="PA13" signalname="DEBUG_JTMS_SWDIO" signaltype="2"/>
|
||||
<PinSub pinname="PA14" signalname="DEBUG_JTCK_SWCLK" signaltype="2"/>
|
||||
</PINInfo>
|
||||
<ProjectInfomation>
|
||||
<ProjectName>AT32F403ARCT7_BOOT</ProjectName>
|
||||
<ProjectLocation>C:/Users/19665/Desktop/test/YNGJ-GT1-M</ProjectLocation>
|
||||
<ToolchainIDE>IAR_V7.4</ToolchainIDE>
|
||||
<ARMCompiler>0</ARMCompiler>
|
||||
<KeepUserCode>true</KeepUserCode>
|
||||
<NotUsedPinAnalog>false</NotUsedPinAnalog>
|
||||
<CodeSplitIP>true</CodeSplitIP>
|
||||
<AddNecessaryFileFlag>true</AddNecessaryFileFlag>
|
||||
<MinHeapSize>0x200</MinHeapSize>
|
||||
<MinStackSize>0x400</MinStackSize>
|
||||
<UseFirmware>true</UseFirmware>
|
||||
<PackageVersion>V2.2.2</PackageVersion>
|
||||
</ProjectInfomation>
|
||||
</Root>
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,60 @@
|
|||
/*
|
||||
* @Author: CTW
|
||||
* @Date: 2025-11-13 16:56:59
|
||||
* @FilePath: \PhoenixSMGT_Testproject\Drivers\LCD_ILI9341\Drv_ILI9341_Lcd_App.h
|
||||
* @Description: XXX
|
||||
* @INPUT: XXX
|
||||
* @OUTPUT: XXX
|
||||
*/
|
||||
#ifndef __DRV_ILI9341_LCD_APP_H
|
||||
#define __DRV_ILI9341_LCD_APP_H
|
||||
|
||||
#include "includes.h"
|
||||
|
||||
// 对齐模式宏（复用之前定义，若已定义可省略）
|
||||
#define LCD_ALIGN_LEFT 0 // 靠左对齐（左边界贴X=0）
|
||||
#define LCD_ALIGN_CENTER 1 // 居中对齐（字符串水平居中）
|
||||
#define LCD_ALIGN_RIGHT 2 // 靠右对齐（右边界贴X=240）
|
||||
|
||||
extern uint16_t RGB(int r,int g,int b);
|
||||
|
||||
extern void LCD_FillByColor(uint16_t xsta,uint16_t ysta,uint16_t xend,uint16_t yend,uint16_t color);
|
||||
extern void LCD_DrawRect(uint16_t x1, uint16_t y1, uint16_t x2, uint16_t y2, uint16_t color, uint8_t fill);
|
||||
extern void LCD_FillRoundRect(uint16_t x0, uint16_t y0, uint16_t w, uint16_t h, uint16_t radius, uint16_t color);
|
||||
extern void LCD_FillRoundRectGradient(uint16_t x, uint16_t y, uint16_t w, uint16_t h,
|
||||
uint16_t r, uint16_t color_top, uint16_t color_bottom);
|
||||
extern void LCD_FillGradient(uint16_t xsta, uint16_t ysta, uint16_t xend, uint16_t yend,
|
||||
uint16_t color_top, uint16_t color_bottom);
|
||||
extern void LCD_WR_PIC(uint16_t x, uint16_t y, uint16_t length, uint16_t width, const uint8_t data[]);
|
||||
extern void LCD_WR_PIC_FROM_FLASH(uint16_t x, uint16_t y, uint16_t length, uint16_t width, uint32_t flash_addr);
|
||||
extern void LCD_DrawPoint(uint16_t x, uint16_t y, uint16_t color); //在指定位置画一个点
|
||||
extern void LCD_DrawLine(uint16_t x1, uint16_t y1, uint16_t x2, uint16_t y2, uint16_t color); //在指定位置画一条线
|
||||
extern void LCD_DrawRectangle(uint16_t x1, uint16_t y1, uint16_t x2, uint16_t y2, uint16_t color); //在指定位置画一个矩形
|
||||
extern void LCD_DrawCircle(uint16_t x0, uint16_t y0, uint8_t r, uint16_t color); //在指定位置画一个圆
|
||||
|
||||
extern void LCD_ShowChar(uint16_t x, uint16_t y, uint8_t num, uint16_t fc, uint16_t bc, uint8_t sizey, uint8_t mode);
|
||||
//extern void LCD_ShowChinese(uint16_t x, uint16_t y, uint8_t *str, uint16_t fc, uint16_t bc, uint8_t sizey, uint8_t mode);
|
||||
extern void LCD_ShowChinese(uint16_t x, uint16_t y, uint8_t index, uint16_t fc, uint16_t bc, uint8_t sizey, uint8_t mode);
|
||||
extern void LCD_ShowString(uint16_t x, uint16_t y, const uint8_t *p, uint16_t fc, uint16_t bc, uint8_t sizey, uint8_t mode);
|
||||
extern void LCD_ShowChineseString(uint16_t x, uint16_t y, uint8_t *str, uint16_t fc, uint16_t bc, uint8_t sizey, uint8_t mode);
|
||||
extern uint16_t LCD_ShowMixedString(uint16_t x1, uint16_t x2, uint16_t y, uint8_t *str, uint8_t align, uint16_t fc, uint16_t bc, uint8_t sizey, uint8_t mode);
|
||||
extern void LCD_ClearString(uint16_t x, uint16_t y, const uint8_t *p, uint16_t bc, uint8_t sizey, uint8_t mode);
|
||||
extern uint16_t LCD_ShowString_AutoAlign(uint16_t x1, uint16_t x2, uint16_t y, const uint8_t *p,uint8_t align, uint16_t fc, uint16_t bc, uint8_t mode, uint8_t size);
|
||||
extern void LCD_ClearString_AutoAlign(uint16_t x1, uint16_t x2, uint16_t y, const uint8_t *p,uint8_t align,uint16_t fc, uint16_t bc, uint8_t mode, uint8_t size);
|
||||
extern uint32_t LCD_ShowChinese_AutoAlign(uint16_t x1, uint16_t x2, uint16_t y, const uint8_t *p, uint8_t align, uint16_t fc, uint16_t bc, uint8_t mode, uint8_t size);
|
||||
//extern void LCD_ClearChinese_AutoAlign(uint8_t x, uint16_t y, const uint8_t *p, uint8_t align,uint16_t fc, uint16_t bc, uint8_t mode, uint8_t size);
|
||||
extern void LCD_ClearChinese_AutoAlign(uint16_t x1, uint16_t x2, uint16_t y, const uint8_t *p, uint8_t align, uint8_t fc,uint16_t bc, uint8_t mode, uint8_t size);
|
||||
|
||||
extern void LCD_DrawArrow_Left(uint16_t x, uint16_t y, uint8_t size, uint16_t color, uint16_t bg_color);
|
||||
extern void LCD_DrawArrow_Right(uint16_t x, uint16_t y, uint8_t size, uint16_t color, uint16_t bg_color);
|
||||
extern void LCD_DrawPlus_RoundBox(uint16_t x, uint16_t y, uint8_t size, uint8_t radius, uint16_t fg_color, uint16_t bg_color);
|
||||
extern void LCD_DrawMinus_RoundBox(uint16_t x, uint16_t y, uint8_t size, uint8_t radius, uint16_t fg_color, uint16_t bg_color);
|
||||
|
||||
extern void Draw_Volume_Bar(uint16_t x, uint16_t y, uint8_t volume_level,uint8_t scale,uint16_t color_on, uint16_t color_off);
|
||||
extern void Draw_Bluetooth_Icon(uint16_t x, uint16_t y, bool bt_state);
|
||||
//extern void Draw_Battery_Icon(uint16_t x, uint16_t y, uint8_t battery_percent);
|
||||
extern void Draw_Battery_Icon(uint16_t x, uint16_t y, uint8_t battery_percent,uint8_t scale, uint16_t border_color, uint16_t bg_color, uint16_t fill_color);
|
||||
extern void Draw_Charging_Icon(uint16_t x, uint16_t y, uint8_t scale, uint16_t ring_color);
|
||||
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,48 @@
|
|||
#ifndef LCD_ILI9341_DRV_ILI9341_LCD_CHINESEFONT_H_
|
||||
#define LCD_ILI9341_DRV_ILI9341_LCD_CHINESEFONT_H_
|
||||
|
||||
const char CHS12Table[][2] = {
|
||||
{0xD2,0xC6}, // 移
|
||||
};
|
||||
|
||||
const char CHS16Table[][2] = {
|
||||
{0xD2,0xC6}, // 移
|
||||
};
|
||||
|
||||
|
||||
const char CHS24Table[][2] = {
|
||||
{0xC9,0xFD}, // 升
|
||||
{0xBC,0xB6}, // 级
|
||||
{0xC4,0xA3}, // 模
|
||||
{0xCA,0xBD} // 式
|
||||
|
||||
};
|
||||
|
||||
|
||||
const unsigned char Chinese_font_12[][24] =
|
||||
{
|
||||
{0x0C,0x00,0x78,0x00,0x1B,0xF0,0x1B,0x30,0xFF,0x30,0x1B,0x30,0x3F,0x30,0x7F,0x30,0xDB,0x30,0x1B,0xF0,0x1B,0x30,0x18,0x00},/*"和",0*/
|
||||
|
||||
};
|
||||
|
||||
// 16x16 汉字 = 32字节
|
||||
const unsigned char Chinese_font_16[][32] =
|
||||
{
|
||||
{0x08,0x20,0x1C,0x20,0xF0,0x7C,0x10,0x84,0x11,0x48,0xFC,0x30,0x10,0x20,0x30,0x48,0x39,0x90,0x54,0x3E,0x54,0x42,0x91,0xA4,0x10,0x18,0x10,0x10,0x10,0x60,0x11,0x80},/*"移",0*/
|
||||
};
|
||||
|
||||
|
||||
|
||||
const unsigned char Chinese_font_24[][72] =
|
||||
{
|
||||
{0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x0C,0xC0,0x00,0x3E,0xC0,0x03,0xF0,0xC0,0x3E,0xC0,0xC0,0x00,0xC0,0xC0,0x00,0xC0,0xC0,0x00,0xC0,0xC0,0x00,0xC0,0xC0,0x00,0xC0,0xCC,0x7F,0xFF,0xFE,0x00,0xC0,0xC0,0x00,0xC0,0xC0,0x00,0xC0,0xC0,0x01,0xC0,0xC0,0x01,0xC0,0xC0,0x01,0x80,0xC0,0x03,0x80,0xC0,0x03,0x00,0xC0,0x0E,0x00,0xC0,0x18,0x00,0xC0,0x30,0x00,0xC0,0x00,0x00,0x00},/*"升",0*/
|
||||
{0x00,0x00,0x00,0x00,0x00,0x00,0x03,0x00,0x00,0x07,0x00,0x00,0x07,0x7F,0xF8,0x06,0x0E,0x38,0x0C,0x0E,0x30,0x0C,0xEE,0x70,0x18,0xCE,0x60,0x33,0xCE,0xE0,0x3F,0x8F,0xFC,0x03,0x0E,0xDC,0x06,0x0E,0x18,0x0C,0x0F,0x18,0x1C,0x0F,0x38,0x3F,0xD9,0xB0,0x3C,0x19,0xF0,0x00,0x18,0xE0,0x00,0xF0,0xE0,0x07,0xE1,0xF0,0x3C,0xC7,0x38,0x31,0x8C,0x1F,0x03,0x38,0x00,0x00,0x00,0x00},/*"级",1*/
|
||||
{0x00,0x00,0x00,0x06,0x0C,0x60,0x06,0x0E,0x60,0x06,0x0E,0x60,0x06,0xFF,0xFE,0x06,0xCE,0x60,0x7F,0xCE,0x60,0x06,0x1F,0xFC,0x0E,0x18,0x18,0x0F,0x18,0x18,0x0F,0x9F,0xF8,0x1F,0xD8,0x18,0x1E,0xD8,0x18,0x1E,0x1F,0xF8,0x36,0x1B,0x98,0x36,0x03,0x00,0x66,0xFF,0xFE,0x06,0x03,0xC0,0x06,0x07,0xC0,0x06,0x06,0x60,0x06,0x0C,0x38,0x06,0x38,0x1F,0x06,0xE0,0x00,0x00,0x00,0x00},/*"模",2*/
|
||||
{0x00,0x00,0x00,0x00,0x06,0x00,0x00,0x07,0x60,0x00,0x07,0x38,0x00,0x07,0x38,0x00,0x07,0x1C,0x3F,0xFF,0xFE,0x00,0x07,0x00,0x00,0x07,0x00,0x00,0x03,0x00,0x00,0x03,0x00,0x3F,0xFB,0x00,0x01,0x83,0x00,0x01,0x83,0x80,0x01,0x83,0x80,0x01,0x81,0x80,0x01,0x81,0xC0,0x01,0x80,0xC6,0x01,0xFC,0xE6,0x03,0xC0,0x76,0x3E,0x00,0x3E,0x38,0x00,0x1E,0x00,0x00,0x07,0x00,0x00,0x00},/*"式",3*/
|
||||
};
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,205 @@
|
|||
#ifndef __DRV_ILI9341_LCD_ENGLISHFONT_H
|
||||
#define __DRV_ILI9341_LCD_ENGLISHFONT_H
|
||||
|
||||
const unsigned char ascii_1608[][16]={
|
||||
{0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00},/*" ",0*/
|
||||
{0x00,0x00,0x00,0x08,0x08,0x08,0x08,0x08,0x08,0x08,0x00,0x00,0x08,0x08,0x00,0x00},/*"!",1*/
|
||||
{0x00,0x48,0x24,0x24,0x12,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00},/*""",2*/
|
||||
{0x00,0x00,0x00,0x48,0x48,0x48,0x7E,0x24,0x24,0x24,0x7E,0x24,0x24,0x24,0x00,0x00},/*"#",3*/
|
||||
{0x00,0x00,0x10,0x3C,0x52,0x52,0x12,0x1C,0x30,0x50,0x50,0x52,0x52,0x3C,0x10,0x10},/*"$",4*/
|
||||
{0x00,0x00,0x00,0x22,0x25,0x15,0x15,0x0D,0x2A,0x58,0x54,0x54,0x52,0x22,0x00,0x00},/*"%",5*/
|
||||
{0x00,0x00,0x00,0x0C,0x12,0x12,0x12,0x0A,0x76,0x25,0x29,0x19,0x91,0x6E,0x00,0x00},/*"&",6*/
|
||||
{0x00,0x06,0x04,0x04,0x02,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00},/*"'",7*/
|
||||
{0x00,0x40,0x20,0x10,0x10,0x08,0x08,0x08,0x08,0x08,0x08,0x10,0x10,0x20,0x40,0x00},/*"(",8*/
|
||||
{0x00,0x02,0x04,0x08,0x08,0x10,0x10,0x10,0x10,0x10,0x10,0x08,0x08,0x04,0x02,0x00},/*")",9*/
|
||||
{0x00,0x00,0x00,0x00,0x08,0x08,0x6B,0x1C,0x1C,0x6B,0x08,0x08,0x00,0x00,0x00,0x00},/*"*",10*/
|
||||
{0x00,0x00,0x00,0x00,0x00,0x10,0x10,0x10,0xFE,0x10,0x10,0x10,0x00,0x00,0x00,0x00},/*"+",11*/
|
||||
{0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x06,0x04,0x04,0x02},/*",",12*/
|
||||
{0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x7E,0x00,0x00,0x00,0x00,0x00,0x00,0x00},/*"-",13*/
|
||||
{0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x06,0x06,0x00,0x00},/*".",14*/
|
||||
{0x00,0x00,0x40,0x20,0x20,0x20,0x10,0x10,0x08,0x08,0x08,0x04,0x04,0x02,0x02,0x00},/*"/",15*/
|
||||
{0x00,0x00,0x00,0x38,0x6C,0xC6,0xC6,0xC6,0xC6,0xC6,0xC6,0xC6,0x6C,0x38,0x00,0x00},/*"0",0*/
|
||||
{0x00,0x00,0x00,0x30,0x3C,0x30,0x30,0x30,0x30,0x30,0x30,0x30,0x30,0xFC,0x00,0x00},/*"1",1*/
|
||||
{0x00,0x00,0x00,0x7C,0xC6,0xC6,0xC6,0xC0,0x60,0x30,0x18,0x0C,0xC6,0xFE,0x00,0x00},/*"2",2*/
|
||||
{0x00,0x00,0x00,0x7C,0xC6,0xC6,0xC0,0x60,0x38,0x60,0xC0,0xC6,0xC6,0x7C,0x00,0x00},/*"3",3*/
|
||||
{0x00,0x00,0x00,0x60,0x70,0x70,0x78,0x6C,0x6C,0x66,0xFE,0x60,0x60,0xF8,0x00,0x00},/*"4",4*/
|
||||
{0x00,0x00,0x00,0xFE,0x06,0x06,0x06,0x3E,0x66,0xC0,0xC0,0xC6,0x66,0x3C,0x00,0x00},/*"5",5*/
|
||||
{0x00,0x00,0x00,0x38,0x6C,0x06,0x06,0x7E,0xCE,0xC6,0xC6,0xC6,0xCC,0x78,0x00,0x00},/*"6",6*/
|
||||
{0x00,0x00,0x00,0xFE,0xC6,0x60,0x60,0x30,0x30,0x18,0x18,0x18,0x18,0x18,0x00,0x00},/*"7",7*/
|
||||
{0x00,0x00,0x00,0x7C,0xC6,0xC6,0xC6,0x6C,0x38,0x6C,0xC6,0xC6,0xC6,0x7C,0x00,0x00},/*"8",8*/
|
||||
{0x00,0x00,0x00,0x3C,0x66,0xC6,0xC6,0xC6,0xE6,0xFC,0xC0,0xC0,0x6C,0x38,0x00,0x00},/*"9",9*/
|
||||
{0x00,0x00,0x00,0x00,0x00,0x00,0x18,0x18,0x00,0x00,0x00,0x00,0x18,0x18,0x00,0x00},/*":",26*/
|
||||
{0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x08,0x00,0x00,0x00,0x00,0x00,0x08,0x08,0x08},/*";",27*/
|
||||
{0x00,0x00,0x00,0x40,0x20,0x10,0x08,0x04,0x02,0x04,0x08,0x10,0x20,0x40,0x00,0x00},/*"<",28*/
|
||||
{0x00,0x00,0x00,0x00,0x00,0x00,0x7E,0x00,0x00,0x7E,0x00,0x00,0x00,0x00,0x00,0x00},/*"=",29*/
|
||||
{0x00,0x00,0x00,0x02,0x04,0x08,0x10,0x20,0x40,0x20,0x10,0x08,0x04,0x02,0x00,0x00},/*">",30*/
|
||||
{0x00,0x00,0x00,0x3C,0x42,0x42,0x46,0x20,0x10,0x10,0x10,0x00,0x18,0x18,0x00,0x00},/*"?",31*/
|
||||
{0x00,0x00,0x00,0x1C,0x22,0x5A,0x55,0x55,0x55,0x55,0x55,0x3A,0x42,0x3C,0x00,0x00},/*"@",32*/
|
||||
{0x00,0x00,0x00,0x08,0x08,0x18,0x14,0x14,0x24,0x3C,0x22,0x42,0x42,0xE7,0x00,0x00},/*"A",33*/
|
||||
{0x00,0x00,0x00,0x1F,0x22,0x22,0x22,0x1E,0x22,0x42,0x42,0x42,0x22,0x1F,0x00,0x00},/*"B",34*/
|
||||
{0x00,0x00,0x00,0x7C,0x42,0x42,0x01,0x01,0x01,0x01,0x01,0x42,0x22,0x1C,0x00,0x00},/*"C",35*/
|
||||
{0x00,0x00,0x00,0x1F,0x22,0x42,0x42,0x42,0x42,0x42,0x42,0x42,0x22,0x1F,0x00,0x00},/*"D",36*/
|
||||
{0x00,0x00,0x00,0x3F,0x42,0x12,0x12,0x1E,0x12,0x12,0x02,0x42,0x42,0x3F,0x00,0x00},/*"E",37*/
|
||||
{0x00,0x00,0x00,0x3F,0x42,0x12,0x12,0x1E,0x12,0x12,0x02,0x02,0x02,0x07,0x00,0x00},/*"F",38*/
|
||||
{0x00,0x00,0x00,0x3C,0x22,0x22,0x01,0x01,0x01,0x71,0x21,0x22,0x22,0x1C,0x00,0x00},/*"G",39*/
|
||||
{0x00,0x00,0x00,0xE7,0x42,0x42,0x42,0x42,0x7E,0x42,0x42,0x42,0x42,0xE7,0x00,0x00},/*"H",40*/
|
||||
{0x00,0x00,0x00,0x3E,0x08,0x08,0x08,0x08,0x08,0x08,0x08,0x08,0x08,0x3E,0x00,0x00},/*"I",41*/
|
||||
{0x00,0x00,0x00,0x7C,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x11,0x0F},/*"J",42*/
|
||||
{0x00,0x00,0x00,0x77,0x22,0x12,0x0A,0x0E,0x0A,0x12,0x12,0x22,0x22,0x77,0x00,0x00},/*"K",43*/
|
||||
{0x00,0x00,0x00,0x07,0x02,0x02,0x02,0x02,0x02,0x02,0x02,0x02,0x42,0x7F,0x00,0x00},/*"L",44*/
|
||||
{0x00,0x00,0x00,0x77,0x36,0x36,0x36,0x36,0x36,0x2A,0x2A,0x2A,0x2A,0x6B,0x00,0x00},/*"M",45*/
|
||||
{0x00,0x00,0x00,0xE3,0x46,0x46,0x4A,0x4A,0x52,0x52,0x52,0x62,0x62,0x47,0x00,0x00},/*"N",46*/
|
||||
{0x00,0x00,0x00,0x1C,0x22,0x41,0x41,0x41,0x41,0x41,0x41,0x41,0x22,0x1C,0x00,0x00},/*"O",47*/
|
||||
{0x00,0x00,0x00,0x3F,0x42,0x42,0x42,0x42,0x3E,0x02,0x02,0x02,0x02,0x07,0x00,0x00},/*"P",48*/
|
||||
{0x00,0x00,0x00,0x1C,0x22,0x41,0x41,0x41,0x41,0x41,0x41,0x4D,0x32,0x1C,0x60,0x00},/*"Q",49*/
|
||||
{0x00,0x00,0x00,0x3F,0x42,0x42,0x42,0x3E,0x12,0x12,0x22,0x22,0x42,0xC7,0x00,0x00},/*"R",50*/
|
||||
{0x00,0x00,0x00,0x7C,0x42,0x42,0x02,0x04,0x18,0x20,0x40,0x42,0x42,0x3E,0x00,0x00},/*"S",51*/
|
||||
{0x00,0x00,0x00,0x7F,0x49,0x08,0x08,0x08,0x08,0x08,0x08,0x08,0x08,0x1C,0x00,0x00},/*"T",52*/
|
||||
{0x00,0x00,0x00,0xE7,0x42,0x42,0x42,0x42,0x42,0x42,0x42,0x42,0x42,0x3C,0x00,0x00},/*"U",53*/
|
||||
{0x00,0x00,0x00,0xE7,0x42,0x42,0x22,0x24,0x24,0x14,0x14,0x18,0x08,0x08,0x00,0x00},/*"V",54*/
|
||||
{0x00,0x00,0x00,0x6B,0x2A,0x2A,0x2A,0x2A,0x2A,0x36,0x14,0x14,0x14,0x14,0x00,0x00},/*"W",55*/
|
||||
{0x00,0x00,0x00,0xE7,0x42,0x24,0x24,0x18,0x18,0x18,0x24,0x24,0x42,0xE7,0x00,0x00},/*"X",56*/
|
||||
{0x00,0x00,0x00,0x77,0x22,0x22,0x14,0x14,0x08,0x08,0x08,0x08,0x08,0x1C,0x00,0x00},/*"Y",57*/
|
||||
{0x00,0x00,0x00,0x7E,0x21,0x20,0x10,0x10,0x08,0x04,0x04,0x42,0x42,0x3F,0x00,0x00},/*"Z",58*/
|
||||
{0x00,0x78,0x08,0x08,0x08,0x08,0x08,0x08,0x08,0x08,0x08,0x08,0x08,0x08,0x78,0x00},/*"[",59*/
|
||||
{0x00,0x00,0x02,0x04,0x04,0x04,0x08,0x08,0x08,0x10,0x10,0x20,0x20,0x20,0x40,0x40},/*"\",60*/
|
||||
{0x00,0x1E,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x1E,0x00},/*"]",61*/
|
||||
{0x00,0x18,0x24,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00},/*"^",62*/
|
||||
{0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xFF},/*"_",63*/
|
||||
{0x00,0x06,0x08,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00},/*"`",64*/
|
||||
{0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x1C,0x22,0x30,0x2C,0x22,0x32,0x6C,0x00,0x00},/*"a",65*/
|
||||
{0x00,0x00,0x00,0x00,0x03,0x02,0x02,0x1A,0x26,0x42,0x42,0x42,0x26,0x1A,0x00,0x00},/*"b",66*/
|
||||
{0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x38,0x44,0x02,0x02,0x02,0x44,0x38,0x00,0x00},/*"c",67*/
|
||||
{0x00,0x00,0x00,0x00,0x60,0x40,0x40,0x7C,0x42,0x42,0x42,0x42,0x62,0xDC,0x00,0x00},/*"d",68*/
|
||||
{0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x3C,0x42,0x42,0x7E,0x02,0x42,0x3C,0x00,0x00},/*"e",69*/
|
||||
{0x00,0x00,0x00,0x00,0x30,0x48,0x08,0x3E,0x08,0x08,0x08,0x08,0x08,0x3E,0x00,0x00},/*"f",70*/
|
||||
{0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x7C,0x22,0x22,0x1C,0x02,0x3C,0x42,0x42,0x3C},/*"g",71*/
|
||||
{0x00,0x00,0x00,0x00,0x03,0x02,0x02,0x3A,0x46,0x42,0x42,0x42,0x42,0xE7,0x00,0x00},/*"h",72*/
|
||||
{0x00,0x00,0x00,0x0C,0x0C,0x00,0x00,0x0E,0x08,0x08,0x08,0x08,0x08,0x3E,0x00,0x00},/*"i",73*/
|
||||
{0x00,0x00,0x00,0x30,0x30,0x00,0x00,0x38,0x20,0x20,0x20,0x20,0x20,0x20,0x22,0x1E},/*"j",74*/
|
||||
{0x00,0x00,0x00,0x00,0x03,0x02,0x02,0x72,0x12,0x0A,0x0E,0x12,0x22,0x77,0x00,0x00},/*"k",75*/
|
||||
{0x00,0x00,0x00,0x08,0x0E,0x08,0x08,0x08,0x08,0x08,0x08,0x08,0x08,0x3E,0x00,0x00},/*"l",76*/
|
||||
{0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x7F,0x92,0x92,0x92,0x92,0x92,0xB7,0x00,0x00},/*"m",77*/
|
||||
{0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x3B,0x46,0x42,0x42,0x42,0x42,0xE7,0x00,0x00},/*"n",78*/
|
||||
{0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x3C,0x42,0x42,0x42,0x42,0x42,0x3C,0x00,0x00},/*"o",79*/
|
||||
{0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x1B,0x26,0x42,0x42,0x42,0x26,0x1A,0x02,0x07},/*"p",80*/
|
||||
{0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x58,0x64,0x42,0x42,0x42,0x64,0x58,0x40,0xE0},/*"q",81*/
|
||||
{0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x77,0x4C,0x04,0x04,0x04,0x04,0x1F,0x00,0x00},/*"r",82*/
|
||||
{0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x7C,0x42,0x02,0x3C,0x40,0x42,0x3E,0x00,0x00},/*"s",83*/
|
||||
{0x00,0x00,0x00,0x00,0x00,0x08,0x08,0x3E,0x08,0x08,0x08,0x08,0x48,0x30,0x00,0x00},/*"t",84*/
|
||||
{0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x63,0x42,0x42,0x42,0x42,0x62,0xDC,0x00,0x00},/*"u",85*/
|
||||
{0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x77,0x22,0x22,0x14,0x14,0x08,0x08,0x00,0x00},/*"v",86*/
|
||||
{0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xDB,0x91,0x52,0x5A,0x2A,0x24,0x24,0x00,0x00},/*"w",87*/
|
||||
{0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x6E,0x24,0x18,0x18,0x18,0x24,0x76,0x00,0x00},/*"x",88*/
|
||||
{0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xE7,0x42,0x24,0x24,0x18,0x18,0x08,0x08,0x06},/*"y",89*/
|
||||
{0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x7E,0x22,0x10,0x08,0x08,0x44,0x7E,0x00,0x00},/*"z",90*/
|
||||
{0x00,0xC0,0x20,0x20,0x20,0x20,0x20,0x20,0x10,0x20,0x20,0x20,0x20,0x20,0xC0,0x00},/*"{",91*/
|
||||
{0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10},/*"|",92*/
|
||||
{0x00,0x03,0x04,0x04,0x04,0x04,0x04,0x04,0x08,0x04,0x04,0x04,0x04,0x04,0x03,0x00},/*"}",93*/
|
||||
{0x04,0x5A,0x20,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00},/*"~",94*/
|
||||
};
|
||||
|
||||
const unsigned char ascii_2412[][48]={
|
||||
{0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00},/*" ",0*/
|
||||
{0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x60,0x00,0x60,0x00,0x60,0x00,0x60,0x00,0x60,0x00,0x60,0x00,0x60,0x00,0x40,0x00,0x20,0x00,0x20,0x00,0x20,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x60,0x00,0x60,0x00,0x60,0x00,0x00,0x00,0x00,0x00,0x00,0x00},/*"!",1*/
|
||||
{0x00,0x00,0x00,0x00,0x60,0x06,0x60,0x06,0x30,0x03,0x98,0x01,0x88,0x00,0x44,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00},/*""",2*/
|
||||
{0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x10,0x02,0x10,0x02,0x10,0x02,0x10,0x02,0xFE,0x07,0xFE,0x07,0x08,0x02,0x08,0x01,0x08,0x01,0x08,0x01,0x08,0x01,0xFE,0x07,0xFE,0x07,0x04,0x01,0x04,0x01,0x04,0x01,0x04,0x01,0x00,0x00,0x00,0x00,0x00,0x00},/*"#",3*/
|
||||
{0x00,0x00,0x00,0x00,0x00,0x00,0x40,0x00,0x40,0x00,0xF0,0x01,0x58,0x03,0x4C,0x03,0xCC,0x03,0x4C,0x00,0x58,0x00,0x70,0x00,0xE0,0x00,0xC0,0x01,0xC0,0x01,0x40,0x03,0x4C,0x03,0x5C,0x03,0x4C,0x03,0x48,0x01,0xF0,0x00,0x40,0x00,0x40,0x00,0x00,0x00},/*"$",4*/
|
||||
{0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x0E,0x01,0x0A,0x01,0x91,0x00,0x91,0x00,0x91,0x00,0x51,0x00,0x51,0x00,0x3A,0x00,0xAE,0x03,0xA0,0x02,0x50,0x04,0x50,0x04,0x48,0x04,0x48,0x04,0x48,0x04,0x84,0x02,0x84,0x03,0x00,0x00,0x00,0x00,0x00,0x00},/*"%",5*/
|
||||
{0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x38,0x00,0x6C,0x00,0x6C,0x00,0x6C,0x00,0x6C,0x00,0x6C,0x00,0x2C,0x00,0x98,0x07,0x1C,0x01,0x1A,0x01,0x33,0x01,0x33,0x01,0x63,0x01,0xE3,0x00,0xC3,0x08,0xC6,0x09,0x3C,0x07,0x00,0x00,0x00,0x00,0x00,0x00},/*"&",6*/
|
||||
{0x00,0x00,0x00,0x00,0x0C,0x00,0x1C,0x00,0x10,0x00,0x10,0x00,0x08,0x00,0x04,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00},/*"'",7*/
|
||||
{0x00,0x00,0x00,0x00,0x00,0x04,0x00,0x02,0x00,0x01,0x80,0x00,0x80,0x00,0x40,0x00,0x40,0x00,0x20,0x00,0x20,0x00,0x20,0x00,0x20,0x00,0x20,0x00,0x20,0x00,0x20,0x00,0x40,0x00,0x40,0x00,0x80,0x00,0x80,0x00,0x00,0x01,0x00,0x02,0x00,0x04,0x00,0x00},/*"(",8*/
|
||||
{0x00,0x00,0x00,0x00,0x02,0x00,0x04,0x00,0x08,0x00,0x10,0x00,0x10,0x00,0x20,0x00,0x20,0x00,0x40,0x00,0x40,0x00,0x40,0x00,0x40,0x00,0x40,0x00,0x40,0x00,0x40,0x00,0x20,0x00,0x20,0x00,0x10,0x00,0x10,0x00,0x08,0x00,0x04,0x00,0x02,0x00,0x00,0x00},/*")",9*/
|
||||
{0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x40,0x00,0xC0,0x00,0x40,0x00,0x46,0x0C,0x4E,0x0F,0xD0,0x01,0xF0,0x01,0x5E,0x0F,0x46,0x0C,0x40,0x00,0x40,0x00,0x40,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00},/*"*",10*/
|
||||
{0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x40,0x00,0x40,0x00,0x40,0x00,0x40,0x00,0x40,0x00,0xFE,0x0F,0x40,0x00,0x40,0x00,0x40,0x00,0x40,0x00,0x40,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00},/*"+",11*/
|
||||
{0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x0C,0x00,0x1C,0x00,0x10,0x00,0x10,0x00,0x08,0x00,0x04,0x00},/*",",12*/
|
||||
{0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xFE,0x07,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00},/*"-",13*/
|
||||
{0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x1C,0x00,0x1C,0x00,0x1C,0x00,0x00,0x00,0x00,0x00,0x00,0x00},/*".",14*/
|
||||
{0x00,0x00,0x00,0x00,0x00,0x04,0x00,0x06,0x00,0x02,0x00,0x03,0x00,0x01,0x00,0x01,0x80,0x00,0x80,0x00,0x40,0x00,0x40,0x00,0x60,0x00,0x20,0x00,0x20,0x00,0x10,0x00,0x10,0x00,0x08,0x00,0x08,0x00,0x0C,0x00,0x04,0x00,0x06,0x00,0x02,0x00,0x00,0x00},/*"/",15*/
|
||||
{0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xF0,0x01,0xB8,0x03,0x1C,0x07,0x1C,0x07,0x0E,0x0E,0x0E,0x0E,0x0E,0x0E,0x0E,0x0E,0x0E,0x0E,0x0E,0x0E,0x0E,0x0E,0x0E,0x0E,0x1C,0x07,0x1C,0x07,0xB8,0x03,0xF0,0x01,0x00,0x00,0x00,0x00,0x00,0x00},/*"0",0*/
|
||||
{0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xC0,0x00,0xFC,0x00,0xE0,0x00,0xE0,0x00,0xE0,0x00,0xE0,0x00,0xE0,0x00,0xE0,0x00,0xE0,0x00,0xE0,0x00,0xE0,0x00,0xE0,0x00,0xE0,0x00,0xE0,0x00,0xE0,0x00,0xFC,0x07,0x00,0x00,0x00,0x00,0x00,0x00},/*"1",1*/
|
||||
{0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xF8,0x01,0x8C,0x03,0x06,0x07,0x0E,0x07,0x0E,0x07,0x00,0x07,0x00,0x03,0x80,0x03,0xC0,0x01,0xE0,0x00,0x60,0x00,0x30,0x00,0x18,0x06,0x0C,0x06,0x0E,0x06,0xFE,0x07,0x00,0x00,0x00,0x00,0x00,0x00},/*"2",2*/
|
||||
{0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xF8,0x00,0xCE,0x01,0x8E,0x03,0x8E,0x03,0x80,0x03,0x80,0x03,0xC0,0x01,0xF0,0x00,0x80,0x03,0x00,0x03,0x00,0x07,0x00,0x07,0x0E,0x07,0x0E,0x07,0x8E,0x03,0xF8,0x01,0x00,0x00,0x00,0x00,0x00,0x00},/*"3",3*/
|
||||
{0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x80,0x03,0x80,0x03,0xC0,0x03,0xE0,0x03,0xE0,0x03,0xB0,0x03,0x98,0x03,0x98,0x03,0x8C,0x03,0x86,0x03,0xFE,0x0F,0x80,0x03,0x80,0x03,0x80,0x03,0x80,0x03,0xE0,0x0F,0x00,0x00,0x00,0x00,0x00,0x00},/*"4",4*/
|
||||
{0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xFC,0x07,0x0C,0x00,0x0C,0x00,0x0C,0x00,0x0C,0x00,0x0C,0x00,0xFC,0x01,0x9C,0x03,0x0C,0x07,0x00,0x07,0x00,0x07,0x0E,0x07,0x0E,0x07,0x86,0x03,0x8C,0x03,0xF8,0x01,0x00,0x00,0x00,0x00,0x00,0x00},/*"5",5*/
|
||||
{0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xE0,0x03,0x38,0x07,0x1C,0x07,0x1C,0x00,0x0C,0x00,0x0E,0x00,0xEE,0x03,0x3E,0x07,0x1E,0x0E,0x0E,0x0E,0x0E,0x0E,0x0E,0x0E,0x0C,0x0E,0x1C,0x06,0x38,0x07,0xF0,0x01,0x00,0x00,0x00,0x00,0x00,0x00},/*"6",6*/
|
||||
{0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xF8,0x0F,0x1C,0x0E,0x0C,0x06,0x0C,0x03,0x00,0x03,0x00,0x03,0x80,0x01,0x80,0x01,0xC0,0x00,0xC0,0x00,0xC0,0x00,0xE0,0x00,0xE0,0x00,0xE0,0x00,0xE0,0x00,0xE0,0x00,0x00,0x00,0x00,0x00,0x00,0x00},/*"7",7*/
|
||||
{0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xF8,0x03,0x1C,0x07,0x0E,0x0E,0x0E,0x0E,0x0E,0x0E,0x1C,0x06,0x3C,0x07,0xF0,0x01,0xD8,0x03,0x1C,0x07,0x0E,0x0E,0x0E,0x0E,0x0E,0x0E,0x0E,0x0E,0x1C,0x07,0xF0,0x03,0x00,0x00,0x00,0x00,0x00,0x00},/*"8",8*/
|
||||
{0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xF0,0x01,0x1C,0x03,0x1C,0x07,0x0E,0x06,0x0E,0x0E,0x0E,0x0E,0x0E,0x0E,0x0E,0x0F,0x9C,0x0F,0xF8,0x0E,0x00,0x0E,0x00,0x07,0x00,0x07,0x1C,0x03,0x9C,0x03,0xF8,0x00,0x00,0x00,0x00,0x00,0x00,0x00},/*"9",9*/
|
||||
{0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xE0,0x00,0xE0,0x00,0xE0,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xE0,0x00,0xE0,0x00,0xE0,0x00,0x00,0x00,0x00,0x00,0x00,0x00},/*":",26*/
|
||||
{0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x60,0x00,0x60,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x60,0x00,0x60,0x00,0x40,0x00,0x20,0x00,0x20,0x00},/*";",27*/
|
||||
{0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x04,0x00,0x02,0x00,0x01,0x80,0x00,0x40,0x00,0x20,0x00,0x10,0x00,0x08,0x00,0x04,0x00,0x08,0x00,0x10,0x00,0x20,0x00,0x40,0x00,0x80,0x00,0x00,0x01,0x00,0x02,0x00,0x04,0x00,0x00,0x00,0x00,0x00,0x00},/*"<",28*/
|
||||
{0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xFE,0x07,0x00,0x00,0x00,0x00,0x00,0x00,0xFE,0x07,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00},/*"=",29*/
|
||||
{0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x04,0x00,0x08,0x00,0x10,0x00,0x20,0x00,0x40,0x00,0x80,0x00,0x00,0x01,0x00,0x02,0x00,0x04,0x00,0x02,0x00,0x01,0x80,0x00,0x40,0x00,0x20,0x00,0x10,0x00,0x08,0x00,0x04,0x00,0x00,0x00,0x00,0x00,0x00,0x00},/*">",30*/
|
||||
{0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xE0,0x03,0x18,0x06,0x04,0x0C,0x04,0x0C,0x0C,0x0C,0x0C,0x0C,0x00,0x07,0x80,0x01,0x40,0x00,0x40,0x00,0x40,0x00,0x00,0x00,0x00,0x00,0xE0,0x00,0xE0,0x00,0xE0,0x00,0x00,0x00,0x00,0x00,0x00,0x00},/*"?",31*/
|
||||
{0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xE0,0x00,0x18,0x03,0x0C,0x02,0xCC,0x05,0x64,0x05,0x66,0x05,0xA6,0x05,0xB6,0x04,0xB6,0x04,0xB6,0x04,0xB6,0x04,0xB6,0x02,0xE4,0x01,0x0C,0x04,0x0C,0x02,0x18,0x03,0xF0,0x00,0x00,0x00,0x00,0x00,0x00,0x00},/*"@",32*/
|
||||
{0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xE0,0x00,0xE0,0x00,0xF0,0x00,0xF0,0x01,0xB0,0x01,0xB0,0x01,0x98,0x01,0x98,0x03,0x18,0x03,0xF8,0x03,0x0C,0x07,0x0C,0x07,0x0C,0x06,0x06,0x06,0x06,0x0E,0x1F,0x0F,0x00,0x00,0x00,0x00,0x00,0x00},/*"A",0*/
|
||||
{0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xFE,0x01,0x9C,0x07,0x1C,0x07,0x1C,0x07,0x1C,0x07,0x1C,0x07,0x9C,0x03,0xFC,0x01,0x1C,0x07,0x1C,0x06,0x1C,0x0E,0x1C,0x0E,0x1C,0x0E,0x1C,0x0E,0x1C,0x07,0xFE,0x03,0x00,0x00,0x00,0x00,0x00,0x00},/*"B",1*/
|
||||
{0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xE0,0x07,0x38,0x07,0x1C,0x0E,0x1C,0x0C,0x0C,0x0C,0x0E,0x00,0x0E,0x00,0x0E,0x00,0x0E,0x00,0x0E,0x00,0x0E,0x00,0x0E,0x0C,0x1C,0x0C,0x1C,0x06,0x38,0x07,0xF0,0x01,0x00,0x00,0x00,0x00,0x00,0x00},/*"C",2*/
|
||||
{0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xFF,0x00,0x9C,0x03,0x1C,0x07,0x1C,0x07,0x1C,0x0E,0x1C,0x0E,0x1C,0x0E,0x1C,0x0E,0x1C,0x0E,0x1C,0x0E,0x1C,0x0E,0x1C,0x0E,0x1C,0x07,0x1C,0x07,0x9C,0x03,0xFF,0x00,0x00,0x00,0x00,0x00,0x00,0x00},/*"D",3*/
|
||||
{0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xFF,0x07,0x0E,0x07,0x0E,0x0C,0x0E,0x0C,0x0E,0x00,0x8E,0x01,0x8E,0x01,0xFE,0x01,0x8E,0x01,0x8E,0x01,0x8E,0x01,0x0E,0x00,0x0E,0x0C,0x0E,0x0C,0x0E,0x06,0xFF,0x07,0x00,0x00,0x00,0x00,0x00,0x00},/*"E",4*/
|
||||
{0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xFF,0x07,0x0E,0x07,0x0E,0x0C,0x0E,0x0C,0x0E,0x00,0x8E,0x01,0x8E,0x01,0xFE,0x01,0x8E,0x01,0x8E,0x01,0x8E,0x01,0x0E,0x00,0x0E,0x00,0x0E,0x00,0x0E,0x00,0x3F,0x00,0x00,0x00,0x00,0x00,0x00,0x00},/*"F",5*/
|
||||
{0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xF0,0x01,0x38,0x03,0x1C,0x06,0x1C,0x06,0x0C,0x06,0x0E,0x00,0x0E,0x00,0x0E,0x00,0x0E,0x00,0xCE,0x0F,0x0E,0x07,0x0E,0x07,0x1C,0x07,0x1C,0x07,0x38,0x07,0xF0,0x01,0x00,0x00,0x00,0x00,0x00,0x00},/*"G",6*/
|
||||
{0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x1F,0x0F,0x0E,0x0E,0x0E,0x0E,0x0E,0x0E,0x0E,0x0E,0x0E,0x0E,0x0E,0x0E,0xFE,0x0F,0x0E,0x0E,0x0E,0x0E,0x0E,0x0E,0x0E,0x0E,0x0E,0x0E,0x0E,0x0E,0x0E,0x0E,0x1F,0x0F,0x00,0x00,0x00,0x00,0x00,0x00},/*"H",7*/
|
||||
{0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xFC,0x07,0xE0,0x00,0xE0,0x00,0xE0,0x00,0xE0,0x00,0xE0,0x00,0xE0,0x00,0xE0,0x00,0xE0,0x00,0xE0,0x00,0xE0,0x00,0xE0,0x00,0xE0,0x00,0xE0,0x00,0xE0,0x00,0xFC,0x07,0x00,0x00,0x00,0x00,0x00,0x00},/*"I",8*/
|
||||
{0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xF8,0x0F,0xC0,0x01,0xC0,0x01,0xC0,0x01,0xC0,0x01,0xC0,0x01,0xC0,0x01,0xC0,0x01,0xC0,0x01,0xC0,0x01,0xC0,0x01,0xC0,0x01,0xC0,0x01,0xC0,0x01,0xC0,0x01,0xC0,0x01,0xCE,0x01,0xEE,0x00,0x7C,0x00},/*"J",9*/
|
||||
{0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xDF,0x07,0x8E,0x03,0xCE,0x01,0xCE,0x00,0x6E,0x00,0x3E,0x00,0x7E,0x00,0x7E,0x00,0xFE,0x00,0xCE,0x00,0xCE,0x01,0x8E,0x01,0x8E,0x03,0x0E,0x03,0x0E,0x07,0x9F,0x0F,0x00,0x00,0x00,0x00,0x00,0x00},/*"K",10*/
|
||||
{0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x3F,0x00,0x0E,0x00,0x0E,0x00,0x0E,0x00,0x0E,0x00,0x0E,0x00,0x0E,0x00,0x0E,0x00,0x0E,0x00,0x0E,0x00,0x0E,0x00,0x0E,0x00,0x0E,0x0C,0x0E,0x0C,0x0E,0x06,0xFF,0x07,0x00,0x00,0x00,0x00,0x00,0x00},/*"L",11*/
|
||||
{0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x0F,0x0F,0x8E,0x07,0x8E,0x07,0x9E,0x07,0x9E,0x07,0xDE,0x07,0xDE,0x07,0xDE,0x07,0xFE,0x07,0xFE,0x07,0x7E,0x07,0x76,0x07,0x76,0x07,0x76,0x07,0x36,0x07,0x8F,0x0F,0x00,0x00,0x00,0x00,0x00,0x00},/*"M",12*/
|
||||
{0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x9E,0x0F,0x1C,0x06,0x3C,0x06,0x3C,0x06,0x7C,0x06,0x7C,0x06,0xEC,0x06,0xEC,0x06,0xCC,0x06,0xCC,0x07,0x8C,0x07,0x8C,0x07,0x8C,0x07,0x0C,0x07,0x0C,0x07,0x3F,0x06,0x00,0x00,0x00,0x00,0x00,0x00},/*"N",13*/
|
||||
{0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xF0,0x01,0xB8,0x03,0x1C,0x07,0x1C,0x06,0x0E,0x0E,0x0E,0x0E,0x0E,0x0E,0x0E,0x0E,0x0E,0x0E,0x0E,0x0E,0x0E,0x0E,0x0E,0x0E,0x1C,0x06,0x1C,0x07,0xB8,0x03,0xF0,0x01,0x00,0x00,0x00,0x00,0x00,0x00},/*"O",14*/
|
||||
{0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xFF,0x01,0x0E,0x07,0x0E,0x0E,0x0E,0x0E,0x0E,0x0E,0x0E,0x0E,0x0E,0x0E,0x8E,0x07,0xFE,0x01,0x0E,0x00,0x0E,0x00,0x0E,0x00,0x0E,0x00,0x0E,0x00,0x0E,0x00,0x3F,0x00,0x00,0x00,0x00,0x00,0x00,0x00},/*"P",15*/
|
||||
{0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xF0,0x01,0xB8,0x03,0x1C,0x07,0x1C,0x06,0x0E,0x0E,0x0E,0x0E,0x0E,0x0E,0x0E,0x0E,0x0E,0x0E,0x0E,0x0E,0x0E,0x0E,0xFE,0x0E,0xDC,0x06,0xDC,0x07,0xB8,0x03,0xF0,0x01,0x80,0x0F,0x00,0x07,0x00,0x00},/*"Q",16*/
|
||||
{0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xFF,0x03,0x0E,0x07,0x0E,0x0E,0x0E,0x0E,0x0E,0x0E,0x0E,0x0E,0x0E,0x07,0xFE,0x01,0xCE,0x00,0xCE,0x01,0x8E,0x01,0x8E,0x03,0x0E,0x07,0x0E,0x07,0x0E,0x0E,0x1F,0x0E,0x00,0x00,0x00,0x00,0x00,0x00},/*"R",17*/
|
||||
{0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xF8,0x07,0x1C,0x07,0x0E,0x06,0x0E,0x06,0x0E,0x00,0x1E,0x00,0x7C,0x00,0xF8,0x01,0xE0,0x07,0x80,0x07,0x00,0x0F,0x06,0x0E,0x06,0x0E,0x0E,0x0E,0x1C,0x07,0xF0,0x03,0x00,0x00,0x00,0x00,0x00,0x00},/*"S",18*/
|
||||
{0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xFE,0x0F,0xE6,0x0C,0xE3,0x08,0xE3,0x08,0xE0,0x00,0xE0,0x00,0xE0,0x00,0xE0,0x00,0xE0,0x00,0xE0,0x00,0xE0,0x00,0xE0,0x00,0xE0,0x00,0xE0,0x00,0xE0,0x00,0xF8,0x03,0x00,0x00,0x00,0x00,0x00,0x00},/*"T",19*/
|
||||
{0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x3E,0x0F,0x1C,0x06,0x1C,0x06,0x1C,0x06,0x1C,0x06,0x1C,0x06,0x1C,0x06,0x1C,0x06,0x1C,0x06,0x1C,0x06,0x1C,0x06,0x1C,0x06,0x1C,0x06,0x1C,0x06,0x38,0x03,0xF0,0x01,0x00,0x00,0x00,0x00,0x00,0x00},/*"U",20*/
|
||||
{0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x1F,0x0F,0x0E,0x06,0x0C,0x03,0x0C,0x03,0x1C,0x03,0x1C,0x03,0x98,0x01,0x98,0x01,0xB8,0x01,0xB8,0x01,0xF0,0x00,0xF0,0x00,0xF0,0x00,0x70,0x00,0x60,0x00,0x60,0x00,0x00,0x00,0x00,0x00,0x00,0x00},/*"V",21*/
|
||||
{0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xFF,0x0F,0xE6,0x0C,0xC6,0x0C,0xCE,0x0C,0xCE,0x0C,0xEC,0x06,0xEC,0x06,0xEC,0x07,0xEC,0x07,0xBC,0x07,0xBC,0x03,0xB8,0x03,0xB8,0x03,0x98,0x03,0x98,0x01,0x98,0x01,0x00,0x00,0x00,0x00,0x00,0x00},/*"W",22*/
|
||||
{0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xBE,0x0F,0x1C,0x03,0x18,0x03,0x38,0x03,0xB0,0x01,0xF0,0x01,0xE0,0x00,0x60,0x00,0xE0,0x00,0xE0,0x00,0xF0,0x01,0xB0,0x01,0x98,0x03,0x18,0x03,0x0C,0x07,0x9E,0x0F,0x00,0x00,0x00,0x00,0x00,0x00},/*"X",23*/
|
||||
{0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x1F,0x0F,0x0E,0x0C,0x0C,0x06,0x1C,0x06,0x18,0x03,0x38,0x03,0xF8,0x01,0xF0,0x01,0xF0,0x00,0xE0,0x00,0xE0,0x00,0xE0,0x00,0xE0,0x00,0xE0,0x00,0xE0,0x00,0xF8,0x03,0x00,0x00,0x00,0x00,0x00,0x00},/*"Y",24*/
|
||||
{0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xFC,0x0F,0x1C,0x06,0x0E,0x07,0x06,0x03,0x80,0x03,0x80,0x01,0xC0,0x00,0xC0,0x00,0x60,0x00,0x60,0x00,0x30,0x00,0x38,0x00,0x18,0x0C,0x1C,0x0C,0x0C,0x06,0xFE,0x07,0x00,0x00,0x00,0x00,0x00,0x00},/*"Z",25*/
|
||||
{0x00,0x00,0x00,0x00,0xE0,0x03,0x20,0x00,0x20,0x00,0x20,0x00,0x20,0x00,0x20,0x00,0x20,0x00,0x20,0x00,0x20,0x00,0x20,0x00,0x20,0x00,0x20,0x00,0x20,0x00,0x20,0x00,0x20,0x00,0x20,0x00,0x20,0x00,0x20,0x00,0x20,0x00,0x20,0x00,0xE0,0x03,0x00,0x00},/*"[",59*/
|
||||
{0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x04,0x00,0x04,0x00,0x08,0x00,0x08,0x00,0x10,0x00,0x10,0x00,0x10,0x00,0x20,0x00,0x20,0x00,0x40,0x00,0x40,0x00,0xC0,0x00,0x80,0x00,0x80,0x00,0x00,0x01,0x00,0x01,0x00,0x02,0x00,0x02,0x00,0x02,0x00,0x04},/*"\",60*/
|
||||
{0x00,0x00,0x00,0x00,0x7C,0x00,0x40,0x00,0x40,0x00,0x40,0x00,0x40,0x00,0x40,0x00,0x40,0x00,0x40,0x00,0x40,0x00,0x40,0x00,0x40,0x00,0x40,0x00,0x40,0x00,0x40,0x00,0x40,0x00,0x40,0x00,0x40,0x00,0x40,0x00,0x40,0x00,0x40,0x00,0x7C,0x00,0x00,0x00},/*"]",61*/
|
||||
{0x00,0x00,0x60,0x00,0x90,0x00,0x08,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00},/*"^",62*/
|
||||
{0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xFF,0x0F},/*"_",63*/
|
||||
{0x00,0x00,0x00,0x00,0x18,0x00,0x60,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00},/*"`",64*/
|
||||
{0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xF0,0x01,0x0C,0x03,0x0C,0x03,0x00,0x03,0xE0,0x03,0x1C,0x03,0x0E,0x03,0x06,0x03,0x06,0x03,0x8E,0x0B,0x7C,0x0E,0x00,0x00,0x00,0x00,0x00,0x00},/*"a",65*/
|
||||
{0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x08,0x00,0x0E,0x00,0x0C,0x00,0x0C,0x00,0x0C,0x00,0x0C,0x00,0xCC,0x01,0x3C,0x03,0x1C,0x06,0x0C,0x06,0x0C,0x06,0x0C,0x06,0x0C,0x06,0x0C,0x06,0x0C,0x02,0x1C,0x03,0xE4,0x01,0x00,0x00,0x00,0x00,0x00,0x00},/*"b",66*/
|
||||
{0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xF0,0x00,0x8C,0x01,0x8C,0x01,0x86,0x01,0x06,0x00,0x06,0x00,0x06,0x00,0x06,0x02,0x0C,0x02,0x0C,0x01,0xF0,0x00,0x00,0x00,0x00,0x00,0x00,0x00},/*"c",67*/
|
||||
{0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x02,0xC0,0x03,0x00,0x03,0x00,0x03,0x00,0x03,0x00,0x03,0x78,0x03,0x8C,0x03,0x0C,0x03,0x06,0x03,0x06,0x03,0x06,0x03,0x06,0x03,0x06,0x03,0x04,0x03,0x8C,0x07,0x78,0x01,0x00,0x00,0x00,0x00,0x00,0x00},/*"d",68*/
|
||||
{0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xE0,0x01,0x18,0x03,0x08,0x02,0x0C,0x06,0x0C,0x06,0xFC,0x07,0x0C,0x00,0x0C,0x00,0x18,0x04,0x18,0x02,0xE0,0x01,0x00,0x00,0x00,0x00,0x00,0x00},/*"e",69*/
|
||||
{0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xC0,0x03,0x60,0x06,0x30,0x06,0x30,0x00,0x30,0x00,0xFE,0x01,0x30,0x00,0x30,0x00,0x30,0x00,0x30,0x00,0x30,0x00,0x30,0x00,0x30,0x00,0x30,0x00,0x30,0x00,0xFC,0x01,0x00,0x00,0x00,0x00,0x00,0x00},/*"f",70*/
|
||||
{0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xF0,0x07,0xD8,0x06,0x8C,0x01,0x8C,0x01,0x8C,0x01,0x98,0x01,0xF8,0x00,0x0C,0x00,0xFC,0x00,0xCC,0x03,0x06,0x03,0x06,0x03,0x8E,0x03,0xF8,0x00},/*"g",71*/
|
||||
{0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x08,0x00,0x0E,0x00,0x0C,0x00,0x0C,0x00,0x0C,0x00,0x0C,0x00,0xEC,0x01,0x1C,0x03,0x0C,0x03,0x0C,0x03,0x0C,0x03,0x0C,0x03,0x0C,0x03,0x0C,0x03,0x0C,0x03,0x0C,0x03,0x9E,0x07,0x00,0x00,0x00,0x00,0x00,0x00},/*"h",72*/
|
||||
{0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x60,0x00,0x60,0x00,0x00,0x00,0x00,0x00,0x40,0x00,0x7C,0x00,0x60,0x00,0x60,0x00,0x60,0x00,0x60,0x00,0x60,0x00,0x60,0x00,0x60,0x00,0x60,0x00,0x60,0x00,0xFC,0x03,0x00,0x00,0x00,0x00,0x00,0x00},/*"i",73*/
|
||||
{0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xC0,0x01,0xC0,0x01,0x00,0x00,0x00,0x00,0x00,0x01,0xF0,0x01,0x80,0x01,0x80,0x01,0x80,0x01,0x80,0x01,0x80,0x01,0x80,0x01,0x80,0x01,0x80,0x01,0x80,0x01,0x80,0x01,0x80,0x01,0xCC,0x00,0x7C,0x00},/*"j",74*/
|
||||
{0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x08,0x00,0x0E,0x00,0x0C,0x00,0x0C,0x00,0x0C,0x00,0x0C,0x00,0x8C,0x03,0x8C,0x00,0x8C,0x00,0x4C,0x00,0x6C,0x00,0x5C,0x00,0x8C,0x00,0x8C,0x01,0x0C,0x01,0x0C,0x03,0x9E,0x07,0x00,0x00,0x00,0x00,0x00,0x00},/*"k",75*/
|
||||
{0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x40,0x00,0x7C,0x00,0x60,0x00,0x60,0x00,0x60,0x00,0x60,0x00,0x60,0x00,0x60,0x00,0x60,0x00,0x60,0x00,0x60,0x00,0x60,0x00,0x60,0x00,0x60,0x00,0x60,0x00,0x60,0x00,0xFC,0x03,0x00,0x00,0x00,0x00,0x00,0x00},/*"l",76*/
|
||||
{0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x37,0x07,0xEE,0x06,0x66,0x06,0x66,0x06,0x66,0x06,0x66,0x06,0x66,0x06,0x66,0x06,0x66,0x06,0x66,0x06,0xFF,0x0F,0x00,0x00,0x00,0x00,0x00,0x00},/*"m",77*/
|
||||
{0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xEE,0x01,0x1C,0x03,0x0C,0x03,0x0C,0x03,0x0C,0x03,0x0C,0x03,0x0C,0x03,0x0C,0x03,0x0C,0x03,0x0C,0x03,0x9E,0x07,0x00,0x00,0x00,0x00,0x00,0x00},/*"n",78*/
|
||||
{0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xF0,0x00,0x98,0x01,0x0C,0x03,0x06,0x06,0x06,0x06,0x06,0x06,0x06,0x06,0x06,0x06,0x0C,0x03,0x0C,0x03,0xF0,0x00,0x00,0x00,0x00,0x00,0x00,0x00},/*"o",79*/
|
||||
{0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xEE,0x01,0x1C,0x03,0x0C,0x06,0x0C,0x06,0x0C,0x06,0x0C,0x06,0x0C,0x06,0x0C,0x06,0x0C,0x03,0x1C,0x03,0xEC,0x01,0x0C,0x00,0x0C,0x00,0x3E,0x00},/*"p",80*/
|
||||
{0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x78,0x02,0x8C,0x03,0x0C,0x03,0x06,0x03,0x06,0x03,0x06,0x03,0x06,0x03,0x06,0x03,0x04,0x03,0x8C,0x03,0x78,0x03,0x00,0x03,0x00,0x03,0xC0,0x07},/*"q",81*/
|
||||
{0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x9F,0x03,0x58,0x06,0x38,0x06,0x18,0x00,0x18,0x00,0x18,0x00,0x18,0x00,0x18,0x00,0x18,0x00,0x18,0x00,0xFF,0x00,0x00,0x00,0x00,0x00,0x00,0x00},/*"r",82*/
|
||||
{0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xF0,0x03,0x1C,0x03,0x0C,0x02,0x0C,0x02,0x38,0x00,0xF0,0x00,0xC0,0x03,0x04,0x03,0x04,0x03,0x8C,0x03,0xFC,0x01,0x00,0x00,0x00,0x00,0x00,0x00},/*"s",83*/
|
||||
{0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x20,0x00,0x20,0x00,0x30,0x00,0x30,0x00,0xFE,0x01,0x30,0x00,0x30,0x00,0x30,0x00,0x30,0x00,0x30,0x00,0x30,0x00,0x30,0x00,0x30,0x02,0x30,0x02,0xE0,0x01,0x00,0x00,0x00,0x00,0x00,0x00},/*"t",84*/
|
||||
{0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x08,0x02,0x8E,0x03,0x0C,0x03,0x0C,0x03,0x0C,0x03,0x0C,0x03,0x0C,0x03,0x0C,0x03,0x0C,0x03,0x0C,0x03,0x9C,0x07,0x78,0x01,0x00,0x00,0x00,0x00,0x00,0x00},/*"u",85*/
|
||||
{0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x1E,0x07,0x0C,0x02,0x08,0x01,0x08,0x01,0x18,0x01,0x90,0x00,0xB0,0x00,0xB0,0x00,0x60,0x00,0x60,0x00,0x20,0x00,0x00,0x00,0x00,0x00,0x00,0x00},/*"v",86*/
|
||||
{0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xF7,0x0E,0x62,0x04,0x46,0x04,0x64,0x02,0x64,0x02,0xEC,0x02,0x9C,0x01,0x98,0x01,0x98,0x01,0x98,0x01,0x08,0x00,0x00,0x00,0x00,0x00,0x00,0x00},/*"w",87*/
|
||||
{0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xBC,0x07,0x18,0x01,0x10,0x01,0xB0,0x00,0x60,0x00,0x60,0x00,0xE0,0x00,0x90,0x00,0x08,0x01,0x08,0x03,0x9E,0x07,0x00,0x00,0x00,0x00,0x00,0x00},/*"x",88*/
|
||||
{0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x9E,0x07,0x08,0x01,0x08,0x01,0x08,0x01,0x90,0x00,0x90,0x00,0xB0,0x00,0x60,0x00,0x60,0x00,0x60,0x00,0x20,0x00,0x20,0x00,0x24,0x00,0x1C,0x00},/*"y",89*/
|
||||
{0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xFC,0x01,0x84,0x01,0xC4,0x00,0x44,0x00,0x60,0x00,0x20,0x00,0x30,0x00,0x18,0x02,0x08,0x02,0x0C,0x03,0xFC,0x01,0x00,0x00,0x00,0x00,0x00,0x00},/*"z",90*/
|
||||
{0x00,0x00,0x00,0x00,0x00,0x03,0x80,0x00,0x80,0x00,0x80,0x00,0x80,0x00,0x80,0x00,0x80,0x00,0x80,0x00,0x80,0x00,0x40,0x00,0x20,0x00,0x40,0x00,0x80,0x00,0x80,0x00,0x80,0x00,0x80,0x00,0x80,0x00,0x80,0x00,0x80,0x00,0x80,0x00,0x00,0x03,0x00,0x00},/*"{",91*/
|
||||
{0x40,0x00,0x40,0x00,0x40,0x00,0x40,0x00,0x40,0x00,0x40,0x00,0x40,0x00,0x40,0x00,0x40,0x00,0x40,0x00,0x40,0x00,0x40,0x00,0x40,0x00,0x40,0x00,0x40,0x00,0x40,0x00,0x40,0x00,0x40,0x00,0x40,0x00,0x40,0x00,0x40,0x00,0x40,0x00,0x40,0x00,0x40,0x00},/*"|",92*/
|
||||
{0x00,0x00,0x00,0x00,0x0C,0x00,0x10,0x00,0x10,0x00,0x10,0x00,0x10,0x00,0x10,0x00,0x10,0x00,0x10,0x00,0x10,0x00,0x20,0x00,0x40,0x00,0x20,0x00,0x10,0x00,0x10,0x00,0x10,0x00,0x10,0x00,0x10,0x00,0x10,0x00,0x10,0x00,0x10,0x00,0x0C,0x00,0x00,0x00},/*"}",93*/
|
||||
{0x00,0x00,0x1C,0x00,0x22,0x04,0xC2,0x04,0x80,0x03,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00},/*"~",94*/
|
||||
|
||||
};
|
||||
//const DigitFontConfig g_digit_font_configs[] =
|
||||
//{
|
||||
// {8, 16, 16, (const unsigned char*)ascii_1608}, // 8×16
|
||||
// {12, 24, 48, (const unsigned char*)ascii_2412}, // 12×24
|
||||
//};
|
||||
#endif
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,33 @@
|
|||
#ifndef __DRV_ILI9341_LCD_IMAGE_H
|
||||
#define __DRV_ILI9341_LCD_IMAGE_H
|
||||
|
||||
#include "stdint.h"
|
||||
|
||||
//// ======== 全部改成 extern 声明 ========
|
||||
// extern const uint8_t gImage_bl[];
|
||||
// extern const uint8_t gImage_bl0[];
|
||||
// extern const uint8_t gImage_bar[];
|
||||
//
|
||||
//extern const uint8_t gImage_Return[];
|
||||
//extern const unsigned char gImage_AutoClose[];
|
||||
//extern const unsigned char gImage_FimewareVection[];
|
||||
//extern const unsigned char gImage_BlueTooth[];
|
||||
//extern const unsigned char gImage_Restore[];
|
||||
//
|
||||
//extern const unsigned char gImage_mixer[];
|
||||
//extern const unsigned char gImage_SystemSetting[];
|
||||
//
|
||||
//extern const unsigned char gImage_NormalMode_Icon_40_30[];
|
||||
//extern const unsigned char gImage_FreeMode_Icon_40_30[];
|
||||
//extern const unsigned char gImage_ExpressMode_Icon_40_30[];
|
||||
//
|
||||
//extern const uint8_t gImage_NormalMode_notSelect[];
|
||||
//extern const uint8_t gImage_NomalMode_Select[];
|
||||
//extern const uint8_t gImage_Setting_notSelect[];
|
||||
//extern const uint8_t gImage_Setting_Select[];
|
||||
//extern const uint8_t gImage_FreeMode_notSelect[];
|
||||
//extern const uint8_t gImage_FreeMode_Select[];
|
||||
//extern const uint8_t gImage_ExpressMode_notSelect[];
|
||||
//extern const uint8_t gImage_ExpressMode_Select[];
|
||||
#endif
|
||||
|
||||
|
|
@ -0,0 +1,211 @@
|
|||
#include "includes.h"
|
||||
|
||||
void LCD_GPIO_Init(void)
|
||||
{
|
||||
gpio_init_type gpio_init_struct;
|
||||
|
||||
wk_spi2_init();
|
||||
|
||||
/* 必须先用默认参数填充结构体，否则 out_type/pull 等字段是栈上随机值，
|
||||
可能导致引脚被配成开漏输出，背光和复位引脚拉不高，屏幕不亮 */
|
||||
gpio_default_para_init(&gpio_init_struct);
|
||||
|
||||
// LCD控制引脚：DC(PA8)、RESET(PA10) —— 推挽输出
|
||||
gpio_init_struct.gpio_pins = LCD_DC_PIN | LCD_RES_PIN;
|
||||
gpio_init_struct.gpio_mode = GPIO_MODE_OUTPUT;
|
||||
gpio_init_struct.gpio_out_type = GPIO_OUTPUT_PUSH_PULL;
|
||||
gpio_init_struct.gpio_pull = GPIO_PULL_NONE;
|
||||
gpio_init_struct.gpio_drive_strength = GPIO_DRIVE_STRENGTH_STRONGER;
|
||||
gpio_init(GPIOA, &gpio_init_struct);
|
||||
|
||||
// 背光引脚：BL(PC9) —— 推挽输出
|
||||
gpio_init_struct.gpio_pins = LCD_BLK_PIN;
|
||||
gpio_init_struct.gpio_mode = GPIO_MODE_OUTPUT;
|
||||
gpio_init_struct.gpio_out_type = GPIO_OUTPUT_PUSH_PULL;
|
||||
gpio_init_struct.gpio_pull = GPIO_PULL_NONE;
|
||||
gpio_init_struct.gpio_drive_strength = GPIO_DRIVE_STRENGTH_STRONGER;
|
||||
gpio_init(GPIOC, &gpio_init_struct);
|
||||
|
||||
// 初始状态
|
||||
LCD_BLK_Clr(); // 背光灯关闭
|
||||
LCD_RES_Set(); // 复位引脚高电平
|
||||
}
|
||||
|
||||
// 发送8位命令（硬件NSS自动拉低/拉高）
|
||||
void LCD_WR_REG(uint8_t reg)
|
||||
{
|
||||
LCD_DC_Clr();
|
||||
while (!(SPI2->sts & SPI_I2S_TDBE_FLAG)); /* 等待发送缓冲空，避免丢字节 */
|
||||
spi_i2s_data_transmit(SPI2, reg);
|
||||
while (SPI2->sts & SPI_I2S_BF_FLAG); /* 等待本次发送完成 */
|
||||
}
|
||||
|
||||
// 发送8位数据（硬件NSS自动拉低/拉高）
|
||||
void LCD_WR_DATA8(uint8_t data)
|
||||
{
|
||||
LCD_DC_Set();
|
||||
while (!(SPI2->sts & SPI_I2S_TDBE_FLAG));
|
||||
spi_i2s_data_transmit(SPI2, data);
|
||||
while (SPI2->sts & SPI_I2S_BF_FLAG);
|
||||
}
|
||||
|
||||
// 发送16位数据（RGB565格式，SPI为8位模式，必须分两次发：高字节在前）
|
||||
void LCD_WR_DATA16(uint16_t data)
|
||||
{
|
||||
LCD_DC_Set();
|
||||
while (!(SPI2->sts & SPI_I2S_TDBE_FLAG));
|
||||
spi_i2s_data_transmit(SPI2, (data >> 8) & 0xFF);
|
||||
while (!(SPI2->sts & SPI_I2S_TDBE_FLAG));
|
||||
spi_i2s_data_transmit(SPI2, data & 0xFF);
|
||||
while (SPI2->sts & SPI_I2S_BF_FLAG);
|
||||
}
|
||||
|
||||
/*!
|
||||
* @brief SPI2 DMA 批量发送数据（仅用于连续像素/图片数据）
|
||||
* @param data 数据缓冲区指针
|
||||
* @param len 字节数
|
||||
* @note 调用前需等待上一次DMA完成，此函数内部会等待传输完成
|
||||
*/
|
||||
void LCD_SPI_DMA_Send(const uint8_t *data, uint32_t len)
|
||||
{
|
||||
uint32_t tmp;
|
||||
|
||||
if (len == 0) return;
|
||||
tmp = len;
|
||||
while (tmp--)
|
||||
{
|
||||
// SPI 轮询发送
|
||||
while (!(SPI2->sts & SPI_I2S_TDBE_FLAG));
|
||||
SPI2->dt = *(data++);
|
||||
}
|
||||
while (SPI2->sts & SPI_I2S_BF_FLAG);
|
||||
}
|
||||
|
||||
/******************************************************************************
|
||||
函数说明：设置起始和结束地址
|
||||
入口数据：x1,x2 设置列的起始和结束地址
|
||||
y1,y2 设置行的起始和结束地址
|
||||
返回值： 无
|
||||
******************************************************************************/
|
||||
void LCD_SetWindow(uint16_t x1, uint16_t y1, uint16_t x2, uint16_t y2)
|
||||
{
|
||||
LCD_WR_REG(0x2A); // 列地址设置
|
||||
LCD_WR_DATA16(x1);
|
||||
LCD_WR_DATA16(x2);
|
||||
|
||||
LCD_WR_REG(0x2B); // 行地址设置
|
||||
LCD_WR_DATA16(y1);
|
||||
LCD_WR_DATA16(y2);
|
||||
|
||||
LCD_WR_REG(0x2C); // 开始写入GRAM
|
||||
}
|
||||
|
||||
void LCD_Init(void)
|
||||
{
|
||||
LCD_GPIO_Init();//初始化GPIO
|
||||
|
||||
// 复位LCD（ILI9341要求复位低电平≥10μs，复位高后等待≥5ms即可）
|
||||
LCD_RES_Clr();
|
||||
wk_delay_ms(10); // 10ms >> 10μs要求
|
||||
LCD_RES_Set();
|
||||
wk_delay_ms(10); // 10ms >> 5ms要求
|
||||
|
||||
//************* Start Initial Sequence **********//
|
||||
LCD_WR_REG(0x11); //Sleep out
|
||||
wk_delay_ms(120); //Delay 120ms （ILI9341要求，不可缩短）
|
||||
|
||||
//************* Start Initial Sequence **********//
|
||||
LCD_WR_REG(0xCF);
|
||||
LCD_WR_DATA8(0x00);
|
||||
LCD_WR_DATA8(0xC1);
|
||||
LCD_WR_DATA8(0X30);
|
||||
LCD_WR_REG(0xED);
|
||||
LCD_WR_DATA8(0x64);
|
||||
LCD_WR_DATA8(0x03);
|
||||
LCD_WR_DATA8(0X12);
|
||||
LCD_WR_DATA8(0X81);
|
||||
LCD_WR_REG(0xE8);
|
||||
LCD_WR_DATA8(0x85);
|
||||
LCD_WR_DATA8(0x00);
|
||||
LCD_WR_DATA8(0x79);
|
||||
LCD_WR_REG(0xCB);
|
||||
LCD_WR_DATA8(0x39);
|
||||
LCD_WR_DATA8(0x2C);
|
||||
LCD_WR_DATA8(0x00);
|
||||
LCD_WR_DATA8(0x34);
|
||||
LCD_WR_DATA8(0x02);
|
||||
LCD_WR_REG(0xF7);
|
||||
LCD_WR_DATA8(0x20);
|
||||
LCD_WR_REG(0xEA);
|
||||
LCD_WR_DATA8(0x00);
|
||||
LCD_WR_DATA8(0x00);
|
||||
LCD_WR_REG(0xC0); //Power control
|
||||
LCD_WR_DATA8(0x1D); //VRH[5:0]
|
||||
LCD_WR_REG(0xC1); //Power control
|
||||
LCD_WR_DATA8(0x12); //SAP[2:0];BT[3:0]
|
||||
LCD_WR_REG(0xC5); //VCM control
|
||||
LCD_WR_DATA8(0x33);
|
||||
LCD_WR_DATA8(0x3F);
|
||||
LCD_WR_REG(0xC7); //VCM control
|
||||
LCD_WR_DATA8(0x92);
|
||||
LCD_WR_REG(0x3A); // Memory Access Control
|
||||
LCD_WR_DATA8(0x55);
|
||||
LCD_WR_REG(0x36); // Memory Access Control
|
||||
if(USE_HORIZONTAL==0)LCD_WR_DATA8(0x08);
|
||||
else if(USE_HORIZONTAL==1)LCD_WR_DATA8(0xC8);
|
||||
else if(USE_HORIZONTAL==2)LCD_WR_DATA8(0x78);
|
||||
else LCD_WR_DATA8(0xA8);
|
||||
LCD_WR_REG(0xB1);
|
||||
LCD_WR_DATA8(0x00);
|
||||
LCD_WR_DATA8(0x12);
|
||||
LCD_WR_REG(0xB6); // Display Function Control
|
||||
LCD_WR_DATA8(0x0A);
|
||||
LCD_WR_DATA8(0xA2);
|
||||
|
||||
LCD_WR_REG(0x44);
|
||||
LCD_WR_DATA8(0x02);
|
||||
|
||||
LCD_WR_REG(0xF2); // 3Gamma Function Disable
|
||||
LCD_WR_DATA8(0x00);
|
||||
LCD_WR_REG(0x26); //Gamma curve selected
|
||||
LCD_WR_DATA8(0x01);
|
||||
LCD_WR_REG(0xE0); //Set Gamma
|
||||
LCD_WR_DATA8(0x0F);
|
||||
LCD_WR_DATA8(0x22);
|
||||
LCD_WR_DATA8(0x1C);
|
||||
LCD_WR_DATA8(0x1B);
|
||||
LCD_WR_DATA8(0x08);
|
||||
LCD_WR_DATA8(0x0F);
|
||||
LCD_WR_DATA8(0x48);
|
||||
LCD_WR_DATA8(0xB8);
|
||||
LCD_WR_DATA8(0x34);
|
||||
LCD_WR_DATA8(0x05);
|
||||
LCD_WR_DATA8(0x0C);
|
||||
LCD_WR_DATA8(0x09);
|
||||
LCD_WR_DATA8(0x0F);
|
||||
LCD_WR_DATA8(0x07);
|
||||
LCD_WR_DATA8(0x00);
|
||||
LCD_WR_REG(0XE1); //Set Gamma
|
||||
LCD_WR_DATA8(0x00);
|
||||
LCD_WR_DATA8(0x23);
|
||||
LCD_WR_DATA8(0x24);
|
||||
LCD_WR_DATA8(0x07);
|
||||
LCD_WR_DATA8(0x10);
|
||||
LCD_WR_DATA8(0x07);
|
||||
LCD_WR_DATA8(0x38);
|
||||
LCD_WR_DATA8(0x47);
|
||||
LCD_WR_DATA8(0x4B);
|
||||
LCD_WR_DATA8(0x0A);
|
||||
LCD_WR_DATA8(0x13);
|
||||
LCD_WR_DATA8(0x06);
|
||||
LCD_WR_DATA8(0x30);
|
||||
LCD_WR_DATA8(0x38);
|
||||
LCD_WR_DATA8(0x0F);
|
||||
// LCD_WR_REG(0x29); //Display on
|
||||
|
||||
LCD_FillByColor(0, 0, 240, 320, WHITE); // 初始全屏白色
|
||||
LCD_WR_REG(0x29); //Display on
|
||||
LCD_BLK_Set();
|
||||
|
||||
|
||||
}
|
||||
|
|
@ -0,0 +1,102 @@
|
|||
/*
|
||||
* @Author: CTW
|
||||
* @Date: 2025-11-07 14:37:14
|
||||
* @FilePath: \PhoenixSMGT_Testproject\Drivers\LCD_ILI9341\Drv_ILI9341_Lcd_Init.h
|
||||
*/
|
||||
#ifndef __DRV_ILI9341_LCD_INIT_H
|
||||
#define __DRV_ILI9341_LCD_INIT_H
|
||||
|
||||
#include "includes.h"
|
||||
//#include "spi.h"
|
||||
|
||||
#define USE_HORIZONTAL 0 //设置横屏或者竖屏显示 0或1为竖屏 2或3为横屏
|
||||
|
||||
#if USE_HORIZONTAL==0||USE_HORIZONTAL==1
|
||||
#define LCD_W 240
|
||||
#define LCD_H 320
|
||||
|
||||
#else
|
||||
#define LCD_W 320
|
||||
#define LCD_H 240
|
||||
#endif
|
||||
|
||||
//电阻屏芯片连接引脚
|
||||
// SPI2引脚（复用功能）
|
||||
#define LCD_SCK_PIN GPIO_PINS_13
|
||||
#define LCD_SCK_PORT GPIOB
|
||||
#define LCD_MOSI_PIN GPIO_PINS_15
|
||||
#define LCD_MOSI_PORT GPIOB
|
||||
#define LCD_MISO_PIN GPIO_PINS_14
|
||||
#define LCD_MISO_PORT GPIOB
|
||||
#define LCD_NSS_PIN GPIO_PINS_12
|
||||
#define LCD_NSS_PORT GPIOB
|
||||
|
||||
// LCD控制引脚
|
||||
#define LCD_DC_PIN GPIO_PINS_8 // TFT_RS
|
||||
#define LCD_DC_PORT GPIOA
|
||||
#define LCD_BLK_PIN GPIO_PINS_9 // TFT_BL
|
||||
#define LCD_BLK_PORT GPIOC
|
||||
#define LCD_RES_PIN GPIO_PINS_10 // TFT_RESET
|
||||
#define LCD_RES_PORT GPIOA
|
||||
|
||||
// SPI句柄（使用SPI2）
|
||||
//extern SPI_HandleTypeDef hspi2;
|
||||
|
||||
|
||||
// 引脚电平操作宏
|
||||
#define LCD_CS_Clr() HAL_GPIO_WritePin(LCD_NSS_PORT, LCD_NSS_PIN, GPIO_PIN_RESET)
|
||||
#define LCD_CS_Set() HAL_GPIO_WritePin(LCD_NSS_PORT, LCD_NSS_PIN, GPIO_PIN_SET)
|
||||
#define LCD_DC_Clr() HAL_GPIO_WritePin(LCD_DC_PORT, LCD_DC_PIN, GPIO_PIN_RESET)
|
||||
#define LCD_DC_Set() HAL_GPIO_WritePin(LCD_DC_PORT, LCD_DC_PIN, GPIO_PIN_SET)
|
||||
#define LCD_BLK_Clr() HAL_GPIO_WritePin(LCD_BLK_PORT, LCD_BLK_PIN, GPIO_PIN_RESET)
|
||||
#define LCD_BLK_Set() HAL_GPIO_WritePin(LCD_BLK_PORT, LCD_BLK_PIN, GPIO_PIN_SET)
|
||||
#define LCD_RES_Clr() HAL_GPIO_WritePin(LCD_RES_PORT, LCD_RES_PIN, GPIO_PIN_RESET)
|
||||
#define LCD_RES_Set() HAL_GPIO_WritePin(LCD_RES_PORT, LCD_RES_PIN, GPIO_PIN_SET)
|
||||
|
||||
//画笔颜色
|
||||
#define WHITE 0xFFFF
|
||||
#define BLACK 0x0000
|
||||
#define BLUE 0x001F
|
||||
#define BRED 0XF81F
|
||||
#define GRED 0XFFE0
|
||||
#define GBLUE 0X07FF
|
||||
#define RED 0xF800
|
||||
#define MAGENTA 0xF81F
|
||||
#define GREEN 0x07E0
|
||||
#define CYAN 0x7FFF
|
||||
#define YELLOW 0xFFE0
|
||||
#define BROWN 0XBC40 //棕色
|
||||
#define BRRED 0XFC07 //棕红色
|
||||
#define GRAY 0X8430 //灰色
|
||||
#define DARKBLUE 0X01CF //深蓝色
|
||||
#define LIGHTBLUE 0X7D7C //浅蓝色
|
||||
#define GRAYBLUE 0X5458 //灰蓝色
|
||||
#define LIGHTGREEN 0X841F //浅绿色
|
||||
#define LGRAY 0XC618 //浅灰色(PANNEL),窗体背景色
|
||||
#define LGRAYBLUE 0XA651 //浅灰蓝色(中间层颜色)
|
||||
#define LBBLUE 0X2B12 //浅棕蓝色(选择条目的反色)
|
||||
|
||||
|
||||
#define DARKLGRAY 0x5AEB/*0x2988*//*0x1926*//*0x252E*//*0X2B12*/
|
||||
#define BUTTON_COLOR /*0x5AEB*/BLACK
|
||||
|
||||
#define START_COLOR /*0x5AEB*/ 0x2988
|
||||
#define END_COLOR 0x2022/*0x5066*/
|
||||
extern void LCD_GPIO_Init(void); //初始化GPIO
|
||||
extern void LCD_WR_DATA8(uint8_t data); //写入一个字节
|
||||
extern void LCD_WR_DATA16(uint16_t data); //写入两个字节
|
||||
extern void LCD_WR_REG(uint8_t reg); //写入一个指令
|
||||
extern void LCD_SetWindow(uint16_t x1, uint16_t y1, uint16_t x2, uint16_t y2); //设置坐标函数
|
||||
extern void LCD_Init(void); //LCD初始化
|
||||
extern void LCD_SPI_DMA_Send(const uint8_t *data, uint32_t len); //SPI2 DMA批量发送
|
||||
extern void LCD_DrawChevron_Right(uint16_t x, uint16_t y, uint8_t size, uint8_t thick, uint16_t color); //向右空心尖括号
|
||||
|
||||
// 渐变背景文字显示（先画垂直渐变底，再叠加文字笔画）
|
||||
extern uint32_t LCD_ShowChinese_AutoAlign_Gradient(uint16_t x1, uint16_t x2, uint16_t y,
|
||||
const uint8_t *p, uint8_t align, uint16_t fc,
|
||||
uint16_t color_top, uint16_t color_bottom, uint8_t size);
|
||||
extern uint16_t LCD_ShowString_AutoAlign_Gradient(uint16_t x1, uint16_t x2, uint16_t y,
|
||||
const uint8_t *p, uint8_t align, uint16_t fc,
|
||||
uint16_t color_top, uint16_t color_bottom, uint8_t size);
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,339 @@
|
|||
#include "includes.h"
|
||||
|
||||
// 触摸初始化（含引脚配置）
|
||||
void XPT2046_Init(void)
|
||||
{
|
||||
gpio_init_type gpio_init_struct;
|
||||
|
||||
/* 必须先用默认值填充结构体，否则 out_type/drive_strength 等字段是随机值 */
|
||||
gpio_default_para_init(&gpio_init_struct);
|
||||
|
||||
/* 使能用到的 GPIO 时钟 */
|
||||
crm_periph_clock_enable(CRM_GPIOC_PERIPH_CLOCK, TRUE);
|
||||
crm_periph_clock_enable(CRM_GPIOA_PERIPH_CLOCK, TRUE);
|
||||
|
||||
// 输出引脚：CLK、DIN、CS（推挽输出）
|
||||
gpio_init_struct.gpio_mode = GPIO_MODE_OUTPUT;
|
||||
gpio_init_struct.gpio_out_type = GPIO_OUTPUT_PUSH_PULL;
|
||||
gpio_init_struct.gpio_drive_strength = GPIO_DRIVE_STRENGTH_STRONGER;
|
||||
gpio_init_struct.gpio_pull = GPIO_PULL_NONE;
|
||||
gpio_init_struct.gpio_pins = TP_CLK_PIN | TP_DIN_PIN | TP_CS_PIN;
|
||||
gpio_init(GPIOC, &gpio_init_struct);
|
||||
|
||||
// 输入引脚：OUT（上拉）、IRQ（上拉）
|
||||
gpio_init_struct.gpio_mode = GPIO_MODE_INPUT;
|
||||
gpio_init_struct.gpio_pull = GPIO_PULL_UP;
|
||||
gpio_init_struct.gpio_pins = TP_OUT_PIN;
|
||||
gpio_init(TP_OUT_PORT, &gpio_init_struct);
|
||||
|
||||
gpio_init_struct.gpio_pins = TP_IRQ_PIN;
|
||||
gpio_init_struct.gpio_pull = GPIO_PULL_UP;
|
||||
gpio_init(TP_IRQ_PORT, &gpio_init_struct);
|
||||
|
||||
// 初始状态
|
||||
TP_CS_Set();
|
||||
TP_CLK_Set();
|
||||
}
|
||||
|
||||
// 配置IRQ中断（可选，用于触摸触发）
|
||||
void XPT2046_IRQ_Init(void)
|
||||
{
|
||||
// GPIO_InitTypeDef GPIO_InitStruct = {0};
|
||||
// EXTI_HandleTypeDef EXTI_HandleStruct = {0};
|
||||
|
||||
// // 复用IRQ引脚为外部中断
|
||||
// GPIO_InitStruct.Pin = TP_IRQ_PIN;
|
||||
// GPIO_InitStruct.Mode = GPIO_MODE_IT_FALLING; // 下降沿触发（触摸时IRQ变低）
|
||||
// GPIO_InitStruct.Pull = GPIO_PULLUP;
|
||||
// HAL_GPIO_Init(TP_IRQ_PORT, &GPIO_InitStruct);
|
||||
|
||||
// // 配置EXTI中断线（PC12对应EXTI12）
|
||||
// EXTI_HandleStruct.Line = EXTI_LINE_12;
|
||||
// EXTI_HandleStruct.Mode = EXTI_MODE_INTERRUPT;
|
||||
// EXTI_HandleStruct.Pull = EXTI_PULLUP;
|
||||
// HAL_EXTI_Init(&EXTI_HandleStruct);
|
||||
|
||||
// // 使能中断并设置优先级
|
||||
// HAL_NVIC_SetPriority(EXTI15_10_IRQn, 2, 0); // EXTI12属于EXTI15_10中断线
|
||||
// HAL_NVIC_EnableIRQ(EXTI15_10_IRQn);
|
||||
}
|
||||
|
||||
//SPI写数据
|
||||
//向XPT2046写入1字节命令（MCU→DIN输出，XPT2046→DIN输入）
|
||||
//num:要写入的数据
|
||||
void TP_Write_Byte(uint8_t data)
|
||||
{
|
||||
uint8_t i;
|
||||
TP_CLK_Clr(); // 时钟拉低，准备发送数据
|
||||
Delay_us(1);
|
||||
|
||||
for (i = 0; i < 8; i++)
|
||||
{
|
||||
// MCU通过DIN输出数据位（高位先传），XPT2046通过自身DIN输入接收
|
||||
if (data & 0x80)
|
||||
{
|
||||
TP_DIN_Set(); // DIN输出高
|
||||
}
|
||||
else
|
||||
{
|
||||
TP_DIN_Clr(); // DIN输出低
|
||||
}
|
||||
data <<= 1; // 左移，准备下一位
|
||||
|
||||
// 时钟上升沿：XPT2046采样DIN引脚的输入数据（匹配XPT2046时序）
|
||||
TP_CLK_Set();
|
||||
Delay_us(1);
|
||||
TP_CLK_Clr();
|
||||
Delay_us(1);
|
||||
}
|
||||
}
|
||||
|
||||
//SPI读数据
|
||||
//从触摸屏IC读取adc值
|
||||
//CMD:指令
|
||||
//返回值:读到的数据
|
||||
uint16_t TP_Read_AD(uint8_t cmd)
|
||||
{
|
||||
uint8_t i;
|
||||
uint16_t adc_val = 0;
|
||||
|
||||
TP_CS_Clr(); // 片选拉低，选中XPT2046
|
||||
Delay_us(2); // 片选稳定时间
|
||||
|
||||
TP_Write_Byte(cmd); // MCU通过DIN发送命令（XPT2046的DIN输入接收）
|
||||
|
||||
// 等待XPT2046完成AD转换（约6us，转换期间OUT无有效数据）
|
||||
Delay_us(6);
|
||||
|
||||
// 读取16位数据（XPT2046通过自身OUT输出数据，MCU通过OUT输入读取）
|
||||
for (i = 0; i < 16; i++)
|
||||
{
|
||||
adc_val <<= 1; // 左移，准备接收下一位
|
||||
|
||||
// 时钟上升沿：XPT2046更新OUT引脚输出；下降沿：MCU读取OUT输入
|
||||
TP_CLK_Set();
|
||||
Delay_us(1);
|
||||
TP_CLK_Clr();
|
||||
Delay_us(1);
|
||||
|
||||
// MCU读取OUT引脚的输入数据（高12位有效，低4位丢弃）
|
||||
if (TP_OUT_Read())
|
||||
{
|
||||
adc_val |= 0x01;
|
||||
}
|
||||
}
|
||||
|
||||
TP_CS_Set(); // 释放片选
|
||||
return adc_val >> 4; // 取高12位有效数据
|
||||
}
|
||||
|
||||
// 简单去抖动读取（连续n次相同状态视为有效）
|
||||
uint8_t TP_CheckPressed(uint8_t n)
|
||||
{
|
||||
uint8_t count = 0;
|
||||
|
||||
for (uint8_t i = 0; i < n; i++)
|
||||
{
|
||||
if (TP_IRQ_Read() == 0)
|
||||
{ // IRQ低电平表示按下
|
||||
count++;
|
||||
}
|
||||
Delay_us(100);
|
||||
}
|
||||
|
||||
return (count >= n/2) ? 1 : 0;
|
||||
}
|
||||
|
||||
// 读取原始坐标（未校准）
|
||||
TP_Point TP_ReadRaw(void)
|
||||
{
|
||||
TP_Point p = {0, 0, 0};
|
||||
|
||||
if (!TP_CheckPressed(3))
|
||||
{ // 检查触摸状态
|
||||
return p;
|
||||
}
|
||||
|
||||
// 多次读取取平均值，减少噪声
|
||||
uint32_t x_sum = 0, y_sum = 0;
|
||||
|
||||
for (uint8_t i = 0; i < 5; i++)
|
||||
{
|
||||
x_sum += TP_Read_AD(XPT2046_READ_X);
|
||||
y_sum += TP_Read_AD(XPT2046_READ_Y);
|
||||
}
|
||||
|
||||
p.x = x_sum / 5;
|
||||
p.y = y_sum / 5;
|
||||
p.pressed = 1;
|
||||
|
||||
return p;
|
||||
}
|
||||
|
||||
// 校准参数（需实际触摸四个角后修改，示例为240x320屏）
|
||||
#define CALIB_X_MIN 200 // 最小X原始值
|
||||
#define CALIB_X_MAX 3800 // 最大X原始值
|
||||
#define CALIB_Y_MIN 200 // 最小Y原始值
|
||||
#define CALIB_Y_MAX 3800 // 最大Y原始值
|
||||
#define LCD_WIDTH 240 // LCD宽度
|
||||
#define LCD_HEIGHT 320 // LCD高度
|
||||
|
||||
// 校准后获取LCD坐标
|
||||
TP_Point TP_Read(void)
|
||||
{
|
||||
// char Info[40];
|
||||
TP_Point raw = TP_ReadRaw();
|
||||
// sprintf (Info, "(x=%03d y=%03d) ", raw.x, raw.y);
|
||||
// LCD_ShowString(2, 176+16, (const uint8_t*)Info, RED, WHITE, 16, 0);
|
||||
TP_Point calib = {0, 0, raw.pressed};
|
||||
|
||||
if (!raw.pressed) {
|
||||
return calib;
|
||||
}
|
||||
|
||||
// 线性映射：将原始ADC值转换为LCD像素坐标
|
||||
calib.x = (raw.x - CALIB_X_MIN) * LCD_WIDTH / (CALIB_X_MAX - CALIB_X_MIN);
|
||||
calib.y = (raw.y - CALIB_Y_MIN) * LCD_HEIGHT / (CALIB_Y_MAX - CALIB_Y_MIN);
|
||||
|
||||
// 边界限制
|
||||
if (calib.x > LCD_WIDTH - 1) calib.x = LCD_WIDTH - 1;
|
||||
if (calib.x == 0) calib.x = 0;
|
||||
if (calib.y > LCD_HEIGHT - 1) calib.y = LCD_HEIGHT - 1;
|
||||
if (calib.y == 0) calib.y = 0;
|
||||
|
||||
return calib;
|
||||
}
|
||||
|
||||
// EXTI15_10中断服务函数（处理TP_IRQ触发）
|
||||
//void EXTI15_10_IRQHandler(void)
|
||||
//{
|
||||
// HAL_EXTI_IRQHandler(&EXTI_HandleStruct); // 调用HAL库中断处理
|
||||
//}
|
||||
|
||||
// 中断回调函数（触摸触发时执行）
|
||||
//void HAL_EXTI_Callback(EXTI_HandleTypeDef *hexti)
|
||||
//{
|
||||
// if (hexti->Line == EXTI_LINE_12)
|
||||
// {
|
||||
// TP_Point p = TP_Read(); // 读取触摸坐标
|
||||
// if (p.pressed)
|
||||
// {
|
||||
// // 处理触摸事件（如绘图、按键响应等）
|
||||
// // LCD_DrawPixel(p.x, p.y, 0xF800); // 示例：画红点
|
||||
// }
|
||||
// }
|
||||
//}
|
||||
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
//与LCD部分有关的函数
|
||||
//画一个触摸点
|
||||
//用来校准用的
|
||||
//x,y:坐标
|
||||
//color:颜色
|
||||
void TP_Drow_Touch_Point(uint16_t x, uint16_t y, uint16_t color)
|
||||
{
|
||||
LCD_DrawLine(x - 12, y, x + 13, y, color);//横线
|
||||
LCD_DrawLine(x, y - 12, x, y + 13, color);//竖线
|
||||
LCD_DrawPoint(x + 1, y + 1, color);
|
||||
LCD_DrawPoint(x - 1, y + 1, color);
|
||||
LCD_DrawPoint(x + 1, y - 1, color);
|
||||
LCD_DrawPoint(x - 1, y - 1, color);
|
||||
LCD_DrawCircle(x, y, 6, color);//画中心圈
|
||||
}
|
||||
|
||||
//画一个大点(2*2的点)
|
||||
//x,y:坐标
|
||||
//color:颜色
|
||||
void TP_Draw_Big_Point(uint16_t x, uint16_t y, uint16_t color)
|
||||
{
|
||||
LCD_DrawPoint(x, y, color);//中心点
|
||||
LCD_DrawPoint(x + 1, y, color);
|
||||
LCD_DrawPoint(x, y + 1, color);
|
||||
LCD_DrawPoint(x + 1, y + 1, color);
|
||||
}
|
||||
|
||||
/******************************************************************************
|
||||
函数说明：画线
|
||||
入口数据：x1,y1 起始坐标
|
||||
x2,y2 终止坐标
|
||||
color 线的颜色
|
||||
返回值： 无
|
||||
******************************************************************************/
|
||||
void LCD_DrawRoughLine(uint16_t x1,uint16_t y1,uint16_t x2,uint16_t y2,uint16_t color)
|
||||
{
|
||||
uint16_t t;
|
||||
int xerr = 0, yerr = 0, delta_x, delta_y, distance;
|
||||
int incx, incy, uRow, uCol;
|
||||
|
||||
delta_x = x2 - x1; //计算坐标增量
|
||||
delta_y = y2 - y1;
|
||||
uRow = x1;//画线起点坐标
|
||||
uCol = y1;
|
||||
|
||||
if(delta_x > 0)
|
||||
{
|
||||
incx = 1; //设置单步方向
|
||||
}
|
||||
else if (delta_x == 0)
|
||||
{
|
||||
incx = 0;//垂直线
|
||||
}
|
||||
else
|
||||
{
|
||||
incx = -1;
|
||||
delta_x = -delta_x;
|
||||
}
|
||||
|
||||
if(delta_y > 0)
|
||||
{
|
||||
incy = 1;
|
||||
}
|
||||
else if (delta_y == 0)
|
||||
{
|
||||
incy = 0;//水平线
|
||||
}
|
||||
else
|
||||
{
|
||||
incy = -1;
|
||||
delta_y = -delta_y;
|
||||
}
|
||||
|
||||
if(delta_x > delta_y)
|
||||
{
|
||||
distance = delta_x; //选取基本增量坐标轴
|
||||
}
|
||||
else
|
||||
{
|
||||
distance = delta_y;
|
||||
}
|
||||
|
||||
for(t=0;t<distance+1;t++)
|
||||
{
|
||||
TP_Draw_Big_Point(uRow, uCol, color);//画点
|
||||
|
||||
xerr += delta_x;
|
||||
yerr += delta_y;
|
||||
|
||||
if(xerr > distance)
|
||||
{
|
||||
xerr -= distance;
|
||||
uRow += incx;
|
||||
}
|
||||
|
||||
if(yerr > distance)
|
||||
{
|
||||
yerr -= distance;
|
||||
uCol += incy;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
// 辅助函数：格式化坐标字符串（x,y转字符串）
|
||||
void TP_FormatCoord(char *buf, TP_Point p)
|
||||
{
|
||||
sprintf(buf, "X:%4d Y:%4d", p.x, p.y); // 格式化为"X:xxxx Y:yyyy"
|
||||
}
|
||||
|
||||
/* ------------------------END----------------------- */
|
||||
|
||||
|
||||
|
|
@ -0,0 +1,93 @@
|
|||
/*
|
||||
* @Author: CTW
|
||||
* @Date: 2025-11-14 15:36:53
|
||||
* @FilePath: \PhoenixSMGT_Testproject\Drivers\LCD_ILI9341\Drv_XPT2046_Touch.h
|
||||
* @Description: XXX
|
||||
* @INPUT: XXX
|
||||
* @OUTPUT: XXX
|
||||
*/
|
||||
#ifndef __DRV_XPT2046_TOUCH_H__
|
||||
#define __DRV_XPT2046_TOUCH_H__
|
||||
|
||||
#include "includes.h"
|
||||
|
||||
// 触摸引脚定义（MCU视角：输出=MCU→XPT2046，输入=XPT2046→MCU）
|
||||
#define TP_IRQ_PIN GPIO_PINS_12 // 输入：XPT2046触摸中断输出（低电平触发）
|
||||
#define TP_IRQ_PORT GPIOC
|
||||
#define TP_OUT_PIN GPIO_PINS_15 // 输入：XPT2046 SPI数据输出（ADC数据）
|
||||
#define TP_OUT_PORT GPIOA
|
||||
#define TP_CLK_PIN GPIO_PINS_8 // 输出：MCU SPI时钟输出
|
||||
#define TP_CLK_PORT GPIOC
|
||||
#define TP_CS_PIN GPIO_PINS_7 // 输出：MCU片选输出（选中/释放XPT2046）
|
||||
#define TP_CS_PORT GPIOC
|
||||
#define TP_DIN_PIN GPIO_PINS_6 // 输出：MCU SPI数据输出（命令/数据→XPT2046）
|
||||
#define TP_DIN_PORT GPIOC
|
||||
|
||||
// 引脚操作宏（明确方向，AT32 库）
|
||||
#define TP_IRQ_Read() gpio_input_data_bit_read(TP_IRQ_PORT, TP_IRQ_PIN) // 读中断（输入）
|
||||
#define TP_OUT_Read() gpio_input_data_bit_read(TP_OUT_PORT, TP_OUT_PIN) // 读XPT2046输出数据（输入）
|
||||
#define TP_CLK_Clr() gpio_bits_reset(TP_CLK_PORT, TP_CLK_PIN) // 时钟输出低
|
||||
#define TP_CLK_Set() gpio_bits_set(TP_CLK_PORT, TP_CLK_PIN) // 时钟输出高
|
||||
#define TP_CS_Clr() gpio_bits_reset(TP_CS_PORT, TP_CS_PIN) // 片选输出低（选中）
|
||||
#define TP_CS_Set() gpio_bits_set(TP_CS_PORT, TP_CS_PIN) // 片选输出高（释放）
|
||||
#define TP_DIN_Clr() gpio_bits_reset(TP_DIN_PORT, TP_DIN_PIN) // DIN输出低（MCU→XPT2046）
|
||||
#define TP_DIN_Set() gpio_bits_set(TP_DIN_PORT, TP_DIN_PIN) // DIN输出高（MCU→XPT2046）
|
||||
|
||||
// XPT2046命令定义
|
||||
#define XPT2046_READ_X 0xD0 // 读X坐标命令（MCU通过DIN发送给XPT2046）
|
||||
#define XPT2046_READ_Y 0x90 // 读Y坐标命令
|
||||
#define XPT2046_READ_Z1 0xB0 // 读压力Z1
|
||||
#define XPT2046_READ_Z2 0xC0 // 读压力Z2
|
||||
|
||||
// 触摸状态结构体
|
||||
typedef struct
|
||||
{
|
||||
uint16_t x; // 校准后X坐标
|
||||
uint16_t y; // 校准后Y坐标
|
||||
uint8_t pressed; // 1=按下，0=未按下
|
||||
} TP_Point;
|
||||
|
||||
|
||||
//// 琴弦结构体
|
||||
//typedef struct
|
||||
//{
|
||||
// uint16_t x; // 校准后X坐标
|
||||
// uint16_t y; // 校准后Y坐标
|
||||
// uint8_t pressed; // 1=按下，0=未按下
|
||||
//} TP_Point;
|
||||
|
||||
//电阻屏函数
|
||||
extern void XPT2046_Init(void); // 触摸初始化（含引脚配置）
|
||||
extern void XPT2046_IRQ_Init(void); // 配置IRQ中断（可选，用于触摸触发）
|
||||
extern void TP_Write_Byte(uint8_t cmd); // 向XPT2046写入1字节命令（MCU→DIN输出，XPT2046→DIN输入）
|
||||
extern uint16_t TP_Read_AD(uint8_t CMD); // 从触摸屏IC读取adc值
|
||||
extern uint8_t TP_CheckPressed(uint8_t n); // 简单去抖动读取（连续n次相同状态视为有效）
|
||||
extern TP_Point TP_ReadRaw(void); // 读取原始坐标（未校准）
|
||||
extern TP_Point TP_Read(void); // 校准后获取LCD坐标
|
||||
|
||||
extern void EXTI15_10_IRQHandler(void); // EXTI15_10中断服务函数（处理TP_IRQ触发）
|
||||
//extern void HAL_EXTI_Callback(EXTI_HandleTypeDef *hexti); // 中断回调函数（触摸触发时执行）
|
||||
|
||||
extern void TP_Drow_Touch_Point(uint16_t x, uint16_t y, uint16_t color); //画一个坐标校准点
|
||||
extern void TP_Draw_Big_Point(uint16_t x, uint16_t y, uint16_t color); //画一个大点
|
||||
extern void LCD_DrawRoughLine(uint16_t x1, uint16_t y1, uint16_t x2, uint16_t y2, uint16_t color); //画粗一点的线
|
||||
extern void TP_FormatCoord(char *buf, TP_Point p); // 辅助函数：格式化坐标字符串（x,y转字符串）
|
||||
|
||||
#endif
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
|
@ -0,0 +1,298 @@
|
|||
/*
|
||||
* @Author: CTW
|
||||
* @Date: 2025-11-07 14:37:55
|
||||
* @FilePath: \PhoenixSMGT_Testproject\Drivers\TM1617\Drv_TM1617_RGB.c
|
||||
* @note: 从 STM32 HAL 库移植到 AT32F403A，软件模拟时序（GPIO 位翻转）
|
||||
* - HAL_GPIO_WritePin/ReadPin/Init -> at32f403a_407 库 GPIO 函数
|
||||
* - Delay_us / Delay_ms / HAL_Delay -> 内置忙等延时
|
||||
*/
|
||||
#include "Drv_TM1617_RGB.h"
|
||||
|
||||
uint8_t rgb_color_seq[] = {COLOR_R, COLOR_G, COLOR_B, COLOR_YEL, COLOR_CYA, COLOR_PUR, COLOR_WHT}; // 颜色流转序列
|
||||
uint8_t color_idx = 0; // 颜色索引
|
||||
|
||||
/* ================= 底层原语（AT32 GPIO） ================= */
|
||||
|
||||
#define TM1617_DIO_H() gpio_bits_set(DIO_PORT, DIO_PIN)
|
||||
#define TM1617_DIO_L() gpio_bits_reset(DIO_PORT, DIO_PIN)
|
||||
#define TM1617_CLK_H() gpio_bits_set(CLK_PORT, CLK_PIN)
|
||||
#define TM1617_CLK_L() gpio_bits_reset(CLK_PORT, CLK_PIN)
|
||||
#define TM1617_STB_H() gpio_bits_set(STB_PORT, STB_PIN)
|
||||
#define TM1617_STB_L() gpio_bits_reset(STB_PORT, STB_PIN)
|
||||
|
||||
/* 忙等延时：约 1us（NOP 循环，不依赖 SysTick/RTOS） */
|
||||
static void TM1617_Delay1us(void)
|
||||
{
|
||||
volatile uint32_t i = 24; /* 240MHz 下约 1us，可实测微调 */
|
||||
while (i--) __NOP();
|
||||
}
|
||||
|
||||
/* 忙等延时：约 1ms（NOP 循环） */
|
||||
static void TM1617_Delay1ms(void)
|
||||
{
|
||||
volatile uint32_t i = 24000; /* 240MHz 下约 1ms */
|
||||
while (i--) __NOP();
|
||||
}
|
||||
|
||||
/* DIO 引脚切换为输出模式（推挽） */
|
||||
static void TM1617_DIO_Output(void)
|
||||
{
|
||||
gpio_init_type g;
|
||||
gpio_default_para_init(&g);
|
||||
g.gpio_mode = GPIO_MODE_OUTPUT;
|
||||
g.gpio_out_type = GPIO_OUTPUT_PUSH_PULL;
|
||||
g.gpio_pull = GPIO_PULL_NONE;
|
||||
g.gpio_pins = DIO_PIN;
|
||||
gpio_init(DIO_PORT, &g);
|
||||
}
|
||||
|
||||
/* DIO 引脚切换为输入模式（读按键） */
|
||||
static void TM1617_DIO_Input(void)
|
||||
{
|
||||
gpio_init_type g;
|
||||
gpio_default_para_init(&g);
|
||||
g.gpio_mode = GPIO_MODE_INPUT;
|
||||
g.gpio_pull = GPIO_PULL_NONE;
|
||||
g.gpio_pins = DIO_PIN;
|
||||
gpio_init(DIO_PORT, &g);
|
||||
}
|
||||
|
||||
/* GPIO初始化 */
|
||||
void TM1617_GPIO_Init(void)
|
||||
{
|
||||
gpio_init_type g;
|
||||
|
||||
/* 使能 GPIOB / GPIOC 时钟 */
|
||||
crm_periph_clock_enable(CRM_GPIOB_PERIPH_CLOCK, TRUE);
|
||||
crm_periph_clock_enable(CRM_GPIOC_PERIPH_CLOCK, TRUE);
|
||||
|
||||
/* CLK(PB0)、STB(PC15)、DIO(PC4)：推挽输出，初始拉高 */
|
||||
gpio_default_para_init(&g);
|
||||
g.gpio_mode = GPIO_MODE_OUTPUT;
|
||||
g.gpio_out_type = GPIO_OUTPUT_PUSH_PULL;
|
||||
g.gpio_pull = GPIO_PULL_NONE;
|
||||
g.gpio_drive_strength = GPIO_DRIVE_STRENGTH_MODERATE;
|
||||
|
||||
g.gpio_pins = CLK_PIN;
|
||||
gpio_init(CLK_PORT, &g);
|
||||
g.gpio_pins = STB_PIN;
|
||||
gpio_init(STB_PORT, &g);
|
||||
g.gpio_pins = DIO_PIN;
|
||||
gpio_init(DIO_PORT, &g);
|
||||
|
||||
TM1617_CLK_H();
|
||||
TM1617_STB_H();
|
||||
TM1617_DIO_H();
|
||||
}
|
||||
|
||||
/* 读取1字节数据（STB已拉低，CLK上升沿读） */
|
||||
uint8_t TM1617_ReadByte(void)
|
||||
{
|
||||
uint8_t i, data = 0;
|
||||
|
||||
TM1617_DIO_Input();
|
||||
|
||||
for (i = 0; i < 8; i++)
|
||||
{
|
||||
data >>= 1; // 低位先收，右移占位
|
||||
TM1617_CLK_L();
|
||||
TM1617_Delay1us();
|
||||
|
||||
// 时钟上升沿读数据
|
||||
TM1617_CLK_H();
|
||||
if (gpio_input_data_bit_read(DIO_PORT, DIO_PIN) == SET)
|
||||
{
|
||||
data |= 0x80; // 最高位置1
|
||||
}
|
||||
TM1617_Delay1us();
|
||||
}
|
||||
|
||||
TM1617_DIO_Output();
|
||||
|
||||
return data;
|
||||
}
|
||||
|
||||
/* TM1617写1字节数据（低位先行，CLK上升沿锁存） */
|
||||
void TM1617_WriteByte(uint8_t data)
|
||||
{
|
||||
uint8_t i;
|
||||
for (i = 0; i < 8; i++)
|
||||
{
|
||||
TM1617_CLK_L();
|
||||
TM1617_Delay1us();
|
||||
|
||||
// DIO写当前bit（低位先行）
|
||||
if (data & 0x01) TM1617_DIO_H();
|
||||
else TM1617_DIO_L();
|
||||
TM1617_Delay1us();
|
||||
|
||||
// CLK拉高，锁存数据
|
||||
TM1617_CLK_H();
|
||||
TM1617_Delay1us();
|
||||
|
||||
data >>= 1;
|
||||
}
|
||||
}
|
||||
|
||||
/* TM1617上电清零（避免显示乱码，必须执行） */
|
||||
void TM1617_Clear(void)
|
||||
{
|
||||
TM1617_STB_L();
|
||||
TM1617_Delay1us();
|
||||
|
||||
TM1617_WriteByte(0x40); // 写数据+地址自动增加
|
||||
TM1617_WriteByte(0xC0); // 起始地址 C0H
|
||||
for (uint8_t i = 0; i < 6; i++)
|
||||
{
|
||||
TM1617_WriteByte(0x00); // 6个显存地址清零
|
||||
}
|
||||
|
||||
TM1617_STB_H();
|
||||
TM1617_Delay1us();
|
||||
}
|
||||
|
||||
/* TM1617初始化（设置显示模式+初始辉度） */
|
||||
void TM1617_Init(void)
|
||||
{
|
||||
TM1617_GPIO_Init(); /* 必须先配引脚/时钟，否则 CLK/STB/DIO 浮空，灯不亮 */
|
||||
TM1617_Clear();
|
||||
TM1617_Delay1ms();
|
||||
|
||||
// 配置显示模式：3位7段（指令0x03）
|
||||
TM1617_STB_L();
|
||||
TM1617_Delay1us();
|
||||
TM1617_WriteByte(0x03);
|
||||
TM1617_STB_H();
|
||||
TM1617_Delay1us();
|
||||
|
||||
// 配置初始辉度：最高（0x8F）
|
||||
TM1617_STB_L();
|
||||
TM1617_Delay1us();
|
||||
TM1617_WriteByte(0x8F);
|
||||
TM1617_STB_H();
|
||||
TM1617_Delay1us();
|
||||
}
|
||||
|
||||
/* 设置RGB颜色+辉度（brightness：0~7，对应8级PWM） */
|
||||
void TM1617_SetRGB(uint8_t color, uint8_t brightness)
|
||||
{
|
||||
if (brightness > 7) brightness = 7;
|
||||
|
||||
// 写颜色数据（地址自动增加模式）
|
||||
TM1617_STB_L();
|
||||
TM1617_Delay1us();
|
||||
TM1617_WriteByte(0x40); // 数据命令：写数据+地址自增
|
||||
TM1617_WriteByte(0xC0); // 起始地址 C0H
|
||||
TM1617_WriteByte(color); // RGB颜色数据
|
||||
TM1617_STB_H();
|
||||
TM1617_Delay1us();
|
||||
|
||||
// 写辉度命令
|
||||
TM1617_STB_L();
|
||||
TM1617_Delay1us();
|
||||
TM1617_WriteByte(0x88 + brightness); // 辉度指令 0x88~0x8F
|
||||
TM1617_STB_H();
|
||||
TM1617_Delay1us();
|
||||
}
|
||||
|
||||
/* 按键扫描函数：返回SEG5~SEG8对应按键状态 */
|
||||
KeyStatusTypeDef TM1617_ScanFkey(void)
|
||||
{
|
||||
uint8_t keyData[5] = {0};
|
||||
KeyStatusTypeDef keyState = KEY_NULL;
|
||||
|
||||
TM1617_STB_L();
|
||||
TM1617_Delay1us();
|
||||
|
||||
TM1617_WriteByte(0x42); // 读键数据命令
|
||||
TM1617_Delay1us();
|
||||
|
||||
// 按顺序读取5字节数据
|
||||
keyData[0] = TM1617_ReadByte(); // BYTE1
|
||||
keyData[1] = TM1617_ReadByte(); // BYTE2
|
||||
keyData[2] = TM1617_ReadByte(); // BYTE3（SEG5、SEG6）
|
||||
keyData[3] = TM1617_ReadByte(); // BYTE4（SEG7、SEG8）
|
||||
keyData[4] = TM1617_ReadByte(); // BYTE5
|
||||
|
||||
TM1617_STB_H();
|
||||
TM1617_Delay1us();
|
||||
|
||||
// 解析SEG5~SEG8对应按键（按下为1）
|
||||
if (keyData[2] & 0x01)
|
||||
{
|
||||
keyState = KEY_MAIN_A;
|
||||
}
|
||||
else if (keyData[2] & 0x08)
|
||||
{
|
||||
keyState = KEY_MAIN_B;
|
||||
}
|
||||
else if (keyData[3] & 0x01)
|
||||
{
|
||||
keyState = KEY_MAIN_C;
|
||||
}
|
||||
else if (keyData[3] & 0x08)
|
||||
{
|
||||
keyState = KEY_MAIN_D;
|
||||
}
|
||||
|
||||
return keyState;
|
||||
}
|
||||
|
||||
/* RGB呼吸流转 */
|
||||
void RGB_Breath_Flow(void)
|
||||
{
|
||||
static uint8_t brightness;
|
||||
|
||||
// 吸气：暗→亮
|
||||
for (brightness = 0; brightness < 8; brightness++)
|
||||
{
|
||||
TM1617_SetRGB(rgb_color_seq[color_idx], brightness);
|
||||
TM1617_Delay1ms();
|
||||
// 近似 100ms
|
||||
for (volatile uint32_t k = 0; k < 100; k++) TM1617_Delay1ms();
|
||||
}
|
||||
|
||||
// 呼气：亮→暗
|
||||
for (brightness = 7; brightness > 0; brightness--)
|
||||
{
|
||||
TM1617_SetRGB(rgb_color_seq[color_idx], brightness);
|
||||
TM1617_Delay1ms();
|
||||
for (volatile uint32_t k = 0; k < 100; k++) TM1617_Delay1ms();
|
||||
}
|
||||
|
||||
// 切换下一种颜色
|
||||
color_idx = (color_idx + 1) % 7;
|
||||
}
|
||||
|
||||
/* 最小化测试：让RGB灯常亮（白色，最高辉度） */
|
||||
void RGB_Test_On(uint8_t u8Color)
|
||||
{
|
||||
TM1617_Clear();
|
||||
TM1617_Delay1ms();
|
||||
|
||||
// 配置显示模式
|
||||
TM1617_STB_L();
|
||||
TM1617_Delay1us();
|
||||
TM1617_WriteByte(0x03);
|
||||
TM1617_STB_H();
|
||||
TM1617_Delay1us();
|
||||
|
||||
// 写颜色数据到 C0H
|
||||
TM1617_STB_L();
|
||||
TM1617_Delay1us();
|
||||
TM1617_WriteByte(0x40);
|
||||
TM1617_WriteByte(0xC0);
|
||||
TM1617_WriteByte(u8Color);
|
||||
TM1617_STB_H();
|
||||
TM1617_Delay1us();
|
||||
|
||||
// 配置最高辉度
|
||||
TM1617_STB_L();
|
||||
TM1617_Delay1us();
|
||||
TM1617_WriteByte(0x8F);
|
||||
TM1617_STB_H();
|
||||
TM1617_Delay1us();
|
||||
|
||||
// 保持
|
||||
for (volatile uint32_t k = 0; k < 500; k++) TM1617_Delay1ms();
|
||||
}
|
||||
|
|
@ -0,0 +1,55 @@
|
|||
/*
|
||||
* @Author: CTW
|
||||
* @Date: 2025-11-07 14:37:14
|
||||
* @FilePath: \PhoenixSMGT_Testproject\Drivers\TM1617\Drv_TM1617_RGB.h
|
||||
* @note: 从 STM32 HAL 库移植到 AT32F403A，软件模拟时序（GPIO 位翻转）
|
||||
*/
|
||||
#ifndef __DRV_TM1617_RGB_H
|
||||
#define __DRV_TM1617_RGB_H
|
||||
|
||||
#include <stdint.h>
|
||||
#include "at32f403a_407.h"
|
||||
|
||||
/* TM1617 引脚（GPIO 普通推挽输出）
|
||||
DIO 需要双向（读按键时切输入），CLK/STB 推挽输出 */
|
||||
#define DIO_PORT GPIOC
|
||||
#define DIO_PIN GPIO_PINS_4
|
||||
#define CLK_PORT GPIOB
|
||||
#define CLK_PIN GPIO_PINS_0
|
||||
#define STB_PORT GPIOC
|
||||
#define STB_PIN GPIO_PINS_15
|
||||
|
||||
/* 按键状态枚举（仅关注SEG5~SEG8对应按键） */
|
||||
typedef enum {
|
||||
KEY_MAIN_D, // SEG5对应按键
|
||||
KEY_MAIN_C, // SEG6对应按键
|
||||
KEY_MAIN_B, // SEG7对应按键
|
||||
KEY_MAIN_A, // SEG8对应按键
|
||||
KEY_NULL
|
||||
} KeyStatusTypeDef;
|
||||
|
||||
/* RGB颜色宏定义（SEG9=R, SEG10=G, SEG11=B，对应bit0~bit2） */
|
||||
#define COLOR_R 0x01 // 仅R亮
|
||||
#define COLOR_G 0x02 // 仅G亮
|
||||
#define COLOR_B 0x04 // 仅B亮
|
||||
#define COLOR_YEL 0x03 // R+G（黄）
|
||||
#define COLOR_CYA 0x06 // G+B（青）
|
||||
#define COLOR_PUR 0x05 // R+B（紫）
|
||||
#define COLOR_WHT 0x07 // R+G+B（白）
|
||||
#define COLOR_OFF 0x00 // 全灭
|
||||
|
||||
|
||||
extern uint8_t rgb_color_seq[]; // 颜色流转序列
|
||||
extern uint8_t color_idx; // 颜色索引
|
||||
|
||||
/* --------------------------------------------------------------------------------------------------------- */
|
||||
void TM1617_GPIO_Init(void); // TM1617 GPIO初始化
|
||||
uint8_t TM1617_ReadByte(void); // 读1字节数据
|
||||
void TM1617_WriteByte(uint8_t data); // 写1字节数据（低位先行，CLK上升沿锁存）
|
||||
void TM1617_Clear(void); // 上电清零（避免乱码）
|
||||
void TM1617_Init(void); // TM1617 初始化
|
||||
extern void TM1617_SetRGB(uint8_t color, uint8_t brightness); // TM1617 初始化
|
||||
extern KeyStatusTypeDef TM1617_ScanFkey(void); // TM1617 按键扫描
|
||||
extern void RGB_Breath_Flow(void); // RGB呼吸流转（7色循环）
|
||||
void RGB_Test_On(uint8_t u8Color); // 最小化测试：让RGB灯常亮（白色，最高辉度）
|
||||
#endif
|
||||
|
|
@ -0,0 +1,210 @@
|
|||
// File: w25q128.c
|
||||
#include "w25q128.h"
|
||||
#include "wk_system.h"
|
||||
|
||||
/* W25Q128 挂在 SPI1 上（PA5=SCK, PA6=MISO, PA7=MOSI），CS 用 PA4 GPIO 控制 */
|
||||
#define W25Q128_SPI SPI1
|
||||
#define W25Q128_CS_PORT GPIOA
|
||||
#define W25Q128_CS_PIN GPIO_PINS_4
|
||||
|
||||
#define SPI_CS_LOW() gpio_bits_reset(W25Q128_CS_PORT, W25Q128_CS_PIN)
|
||||
#define SPI_CS_HIGH() gpio_bits_set(W25Q128_CS_PORT, W25Q128_CS_PIN)
|
||||
|
||||
// 内部私有函数声明
|
||||
static uint8_t W25Q128_ReadWriteByte(uint8_t TxData);
|
||||
static void W25Q128_WriteEnable(void);
|
||||
static void W25Q128_WaitBusy(void);
|
||||
|
||||
/**
|
||||
* @brief SPI1 读写一个字节 (AT32 阻塞式全双工)
|
||||
* 发一个字节同时收一个字节
|
||||
* @param TxData: 要发送的数据
|
||||
* @retval 接收到的数据
|
||||
*/
|
||||
uint8_t SPI1_ReadWriteByte(uint8_t TxData)
|
||||
{
|
||||
/* 等发送缓冲空（可写数据） */
|
||||
while (spi_i2s_flag_get(W25Q128_SPI, SPI_I2S_TDBE_FLAG) == RESET);
|
||||
|
||||
/* 写发送数据寄存器 */
|
||||
spi_i2s_data_transmit(W25Q128_SPI, TxData);
|
||||
|
||||
/* 等接收缓冲满（收到数据） */
|
||||
while (spi_i2s_flag_get(W25Q128_SPI, SPI_I2S_RDBF_FLAG) == RESET);
|
||||
|
||||
/* 读接收数据寄存器（自动清 RDBF） */
|
||||
return (uint8_t)spi_i2s_data_receive(W25Q128_SPI);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief 初始化W25Q128 (实质是配置 CS 引脚；SPI1 由 wk_spi1_init 初始化)
|
||||
*/
|
||||
void W25Q128_Init(void)
|
||||
{
|
||||
gpio_init_type g;
|
||||
|
||||
/* CS 引脚 PA4：推挽输出，初始拉高（释放） */
|
||||
gpio_default_para_init(&g);
|
||||
g.gpio_mode = GPIO_MODE_OUTPUT;
|
||||
g.gpio_out_type = GPIO_OUTPUT_PUSH_PULL;
|
||||
g.gpio_pull = GPIO_PULL_NONE;
|
||||
g.gpio_pins = W25Q128_CS_PIN;
|
||||
gpio_init(W25Q128_CS_PORT, &g);
|
||||
|
||||
SPI_CS_HIGH();
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief 包装SPI读写函数，方便驱动内部调用
|
||||
*/
|
||||
static uint8_t W25Q128_ReadWriteByte(uint8_t TxData)
|
||||
{
|
||||
return SPI1_ReadWriteByte(TxData);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief 发送写使能命令 (任何写/擦除操作前必须调用)
|
||||
*/
|
||||
static void W25Q128_WriteEnable(void)
|
||||
{
|
||||
SPI_CS_LOW(); // 片选选中
|
||||
W25Q128_ReadWriteByte(W25X_WriteEnable); // 发送写使能命令
|
||||
SPI_CS_HIGH(); // 释放片选
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief 等待芯片空闲 (忙时BUSY位为1)
|
||||
*/
|
||||
static void W25Q128_WaitBusy(void)
|
||||
{
|
||||
uint8_t status;
|
||||
SPI_CS_LOW();
|
||||
W25Q128_ReadWriteByte(W25X_ReadStatusReg1); // 发送读状态寄存器命令
|
||||
do {
|
||||
status = W25Q128_ReadWriteByte(0xFF); // 循环读取状态字
|
||||
} while (status & 0x01); // 等待BUSY位清零
|
||||
SPI_CS_HIGH();
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief 读取芯片ID
|
||||
* @retval 例如 W25Q128 返回 0xEF17
|
||||
*/
|
||||
uint16_t W25Q128_ReadID(void)
|
||||
{
|
||||
uint16_t id = 0;
|
||||
SPI_CS_LOW();
|
||||
W25Q128_ReadWriteByte(W25X_ManufactDeviceID); // 发送读取ID命令
|
||||
W25Q128_ReadWriteByte(0x00); // 3个空字节
|
||||
W25Q128_ReadWriteByte(0x00);
|
||||
W25Q128_ReadWriteByte(0x00);
|
||||
id |= W25Q128_ReadWriteByte(0xFF) << 8; // Manufacturer ID
|
||||
id |= W25Q128_ReadWriteByte(0xFF); // Device ID
|
||||
SPI_CS_HIGH();
|
||||
return id;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief 读取数据
|
||||
* @param pBuf: 数据存储区
|
||||
* @param ReadAddr: 读取地址 (0~16MB-1)
|
||||
* @param NumByteToRead: 读取字节数
|
||||
*/
|
||||
void W25Q128_Read(uint8_t* pBuf, uint32_t ReadAddr, uint16_t NumByteToRead)
|
||||
{
|
||||
uint16_t i;
|
||||
SPI_CS_LOW();
|
||||
W25Q128_ReadWriteByte(W25X_ReadData); // 发送读数据命令
|
||||
W25Q128_ReadWriteByte((ReadAddr >> 16) & 0xFF); // 发送24位地址
|
||||
W25Q128_ReadWriteByte((ReadAddr >> 8) & 0xFF);
|
||||
W25Q128_ReadWriteByte(ReadAddr & 0xFF);
|
||||
for (i = 0; i < NumByteToRead; i++) {
|
||||
pBuf[i] = W25Q128_ReadWriteByte(0xFF); // 循环读取
|
||||
}
|
||||
SPI_CS_HIGH();
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief 写入数据 (自动处理跨页写，但调用前需要确保目标扇区已被擦除)
|
||||
* @param pBuf: 源数据
|
||||
* @param WriteAddr: 写入地址
|
||||
* @param NumByteToWrite: 写入字节数 (不要超过扇区大小)
|
||||
*/
|
||||
void W25Q128_Write(uint8_t* pBuf, uint32_t WriteAddr, uint16_t NumByteToWrite)
|
||||
{
|
||||
uint16_t i;
|
||||
uint16_t pageSize = 256; // W25Q128 页大小
|
||||
uint16_t toWrite;
|
||||
|
||||
while (NumByteToWrite > 0) {
|
||||
// 计算当前页可以写入的字节数
|
||||
toWrite = pageSize - (WriteAddr % pageSize);
|
||||
if (toWrite > NumByteToWrite) toWrite = NumByteToWrite;
|
||||
|
||||
W25Q128_WriteEnable(); // 写使能
|
||||
|
||||
SPI_CS_LOW();
|
||||
W25Q128_ReadWriteByte(W25X_PageProgram); // 页编程命令
|
||||
W25Q128_ReadWriteByte((WriteAddr >> 16) & 0xFF);
|
||||
W25Q128_ReadWriteByte((WriteAddr >> 8) & 0xFF);
|
||||
W25Q128_ReadWriteByte(WriteAddr & 0xFF);
|
||||
|
||||
for (i = 0; i < toWrite; i++) {
|
||||
W25Q128_ReadWriteByte(pBuf[i]);
|
||||
}
|
||||
|
||||
SPI_CS_HIGH();
|
||||
W25Q128_WaitBusy(); // 等待本次页编程完成
|
||||
|
||||
// 更新指针和剩余字节数
|
||||
NumByteToWrite -= toWrite;
|
||||
WriteAddr += toWrite;
|
||||
pBuf += toWrite;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief 擦除一个扇区 (4KB)
|
||||
* @param SectorAddr: 扇区内任意地址
|
||||
*/
|
||||
void W25Q128_Erase_Sector(uint32_t SectorAddr)
|
||||
{
|
||||
W25Q128_WriteEnable(); // 写使能
|
||||
|
||||
SPI_CS_LOW();
|
||||
W25Q128_ReadWriteByte(W25X_SectorErase); // 扇区擦除命令
|
||||
W25Q128_ReadWriteByte((SectorAddr >> 16) & 0xFF);
|
||||
W25Q128_ReadWriteByte((SectorAddr >> 8) & 0xFF);
|
||||
W25Q128_ReadWriteByte(SectorAddr & 0xFF);
|
||||
SPI_CS_HIGH();
|
||||
|
||||
W25Q128_WaitBusy(); // 擦除需要时间，等待完成
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief 擦除整个芯片
|
||||
* @note 耗时较长，通常数秒至十几秒，务必确保等待完成
|
||||
*/
|
||||
void W25Q128_Erase_Chip(void)
|
||||
{
|
||||
W25Q128_WriteEnable(); // 写使能
|
||||
|
||||
SPI_CS_LOW();
|
||||
W25Q128_ReadWriteByte(W25X_ChipErase); // 全片擦除命令
|
||||
SPI_CS_HIGH();
|
||||
|
||||
W25Q128_WaitBusy(); // 等待全片擦除完成
|
||||
}
|
||||
|
||||
|
||||
void W25Q128_WriteSector_4K(uint8_t* buf, uint32_t addr,uint32_t len)
|
||||
{
|
||||
// 1. 必须 4K 对齐
|
||||
if(addr % 4096 != 0) return;
|
||||
|
||||
// 2. 擦除 1 个扇区（4KB）
|
||||
W25Q128_Erase_Sector(addr);
|
||||
|
||||
// 3. 写入 4096 字节（你的函数自动分页写，完全支持）
|
||||
W25Q128_Write(buf, addr, len);
|
||||
}
|
||||
|
|
@ -0,0 +1,42 @@
|
|||
// File: w25q128.h
|
||||
#ifndef __W25Q128_H
|
||||
#define __W25Q128_H
|
||||
|
||||
#include <stdint.h>
|
||||
#include "at32f403a_407.h"
|
||||
|
||||
// W25Q128 指令集
|
||||
#define W25X_WriteEnable 0x06
|
||||
#define W25X_WriteDisable 0x04
|
||||
#define W25X_ReadStatusReg1 0x05
|
||||
#define W25X_ReadStatusReg2 0x35
|
||||
#define W25X_WriteStatusReg 0x01
|
||||
#define W25X_PageProgram 0x02
|
||||
#define W25X_QuadPageProgram 0x32
|
||||
#define W25X_BlockErase64KB 0xD8
|
||||
#define W25X_BlockErase32KB 0x52
|
||||
#define W25X_SectorErase 0x20
|
||||
#define W25X_ChipErase 0xC7
|
||||
#define W25X_ChipErase2 0x60 // 另一种全片擦除命令
|
||||
#define W25X_ReadData 0x03
|
||||
#define W25X_FastRead 0x0B
|
||||
#define W25X_ReadManufactID 0x90
|
||||
#define W25X_ReleasePowerDown 0xAB
|
||||
#define W25X_DeviceID 0xAB
|
||||
#define W25X_ManufactDeviceID 0x90
|
||||
#define W25X_JedecDeviceID 0x9F
|
||||
#define W25X_ReadUniqueID 0x4B
|
||||
#define W25X_EnterQPI 0x38
|
||||
#define W25X_ExitQPI 0xFF
|
||||
#define W25X_EnableReset 0x66
|
||||
#define W25X_ResetDevice 0x99
|
||||
|
||||
// 函数声明
|
||||
void W25Q128_Init(void); // 初始化(调用SPI初始化)
|
||||
uint16_t W25Q128_ReadID(void); // 读取ID，用于验证通信
|
||||
void W25Q128_Read(uint8_t* pBuf, uint32_t ReadAddr, uint16_t NumByteToRead); // 读取数据
|
||||
void W25Q128_Write(uint8_t* pBuf, uint32_t WriteAddr, uint16_t NumByteToWrite); // 写入数据(自动处理页写和擦除)
|
||||
void W25Q128_Erase_Sector(uint32_t SectorAddr); // 擦除扇区(4KB)
|
||||
void W25Q128_Erase_Chip(void); // 擦除整个芯片
|
||||
void W25Q128_WriteSector_4K(uint8_t* buf, uint32_t addr,uint32_t len);
|
||||
#endif
|
||||
|
|
@ -0,0 +1,539 @@
|
|||
/* ----------------------------------------------------------------------
|
||||
* Project: CMSIS DSP Library
|
||||
* Title: arm_common_tables.h
|
||||
* Description: Extern declaration for common tables
|
||||
*
|
||||
* @version V1.10.0
|
||||
* @date 08 July 2021
|
||||
*
|
||||
* Target Processor: Cortex-M and Cortex-A cores
|
||||
* -------------------------------------------------------------------- */
|
||||
/*
|
||||
* Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
#ifndef _ARM_COMMON_TABLES_H
|
||||
#define _ARM_COMMON_TABLES_H
|
||||
|
||||
#include "arm_math_types.h"
|
||||
#include "dsp/fast_math_functions.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_FFT_ALLOW_TABLES)
|
||||
/* Double Precision Float CFFT twiddles */
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREV_1024)
|
||||
extern const uint16_t armBitRevTable[1024];
|
||||
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F64_16)
|
||||
extern const uint64_t twiddleCoefF64_16[32];
|
||||
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F64_32)
|
||||
extern const uint64_t twiddleCoefF64_32[64];
|
||||
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F64_64)
|
||||
extern const uint64_t twiddleCoefF64_64[128];
|
||||
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F64_128)
|
||||
extern const uint64_t twiddleCoefF64_128[256];
|
||||
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F64_256)
|
||||
extern const uint64_t twiddleCoefF64_256[512];
|
||||
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F64_512)
|
||||
extern const uint64_t twiddleCoefF64_512[1024];
|
||||
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F64_1024)
|
||||
extern const uint64_t twiddleCoefF64_1024[2048];
|
||||
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F64_2048)
|
||||
extern const uint64_t twiddleCoefF64_2048[4096];
|
||||
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F64_4096)
|
||||
extern const uint64_t twiddleCoefF64_4096[8192];
|
||||
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F32_16)
|
||||
extern const float32_t twiddleCoef_16[32];
|
||||
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F32_32)
|
||||
extern const float32_t twiddleCoef_32[64];
|
||||
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F32_64)
|
||||
extern const float32_t twiddleCoef_64[128];
|
||||
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F32_128)
|
||||
extern const float32_t twiddleCoef_128[256];
|
||||
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F32_256)
|
||||
extern const float32_t twiddleCoef_256[512];
|
||||
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F32_512)
|
||||
extern const float32_t twiddleCoef_512[1024];
|
||||
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F32_1024)
|
||||
extern const float32_t twiddleCoef_1024[2048];
|
||||
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F32_2048)
|
||||
extern const float32_t twiddleCoef_2048[4096];
|
||||
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F32_4096)
|
||||
extern const float32_t twiddleCoef_4096[8192];
|
||||
#define twiddleCoef twiddleCoef_4096
|
||||
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
|
||||
|
||||
/* Q31 */
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q31_16)
|
||||
extern const q31_t twiddleCoef_16_q31[24];
|
||||
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q31_32)
|
||||
extern const q31_t twiddleCoef_32_q31[48];
|
||||
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q31_64)
|
||||
extern const q31_t twiddleCoef_64_q31[96];
|
||||
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q31_128)
|
||||
extern const q31_t twiddleCoef_128_q31[192];
|
||||
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q31_256)
|
||||
extern const q31_t twiddleCoef_256_q31[384];
|
||||
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q31_512)
|
||||
extern const q31_t twiddleCoef_512_q31[768];
|
||||
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q31_1024)
|
||||
extern const q31_t twiddleCoef_1024_q31[1536];
|
||||
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q31_2048)
|
||||
extern const q31_t twiddleCoef_2048_q31[3072];
|
||||
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q31_4096)
|
||||
extern const q31_t twiddleCoef_4096_q31[6144];
|
||||
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q15_16)
|
||||
extern const q15_t twiddleCoef_16_q15[24];
|
||||
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q15_32)
|
||||
extern const q15_t twiddleCoef_32_q15[48];
|
||||
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q15_64)
|
||||
extern const q15_t twiddleCoef_64_q15[96];
|
||||
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q15_128)
|
||||
extern const q15_t twiddleCoef_128_q15[192];
|
||||
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q15_256)
|
||||
extern const q15_t twiddleCoef_256_q15[384];
|
||||
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q15_512)
|
||||
extern const q15_t twiddleCoef_512_q15[768];
|
||||
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q15_1024)
|
||||
extern const q15_t twiddleCoef_1024_q15[1536];
|
||||
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q15_2048)
|
||||
extern const q15_t twiddleCoef_2048_q15[3072];
|
||||
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q15_4096)
|
||||
extern const q15_t twiddleCoef_4096_q15[6144];
|
||||
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
|
||||
|
||||
/* Double Precision Float RFFT twiddles */
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_RFFT_F64_32)
|
||||
extern const uint64_t twiddleCoefF64_rfft_32[32];
|
||||
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_RFFT_F64_64)
|
||||
extern const uint64_t twiddleCoefF64_rfft_64[64];
|
||||
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_RFFT_F64_128)
|
||||
extern const uint64_t twiddleCoefF64_rfft_128[128];
|
||||
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_RFFT_F64_256)
|
||||
extern const uint64_t twiddleCoefF64_rfft_256[256];
|
||||
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_RFFT_F64_512)
|
||||
extern const uint64_t twiddleCoefF64_rfft_512[512];
|
||||
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_RFFT_F64_1024)
|
||||
extern const uint64_t twiddleCoefF64_rfft_1024[1024];
|
||||
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_RFFT_F64_2048)
|
||||
extern const uint64_t twiddleCoefF64_rfft_2048[2048];
|
||||
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_RFFT_F64_4096)
|
||||
extern const uint64_t twiddleCoefF64_rfft_4096[4096];
|
||||
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
|
||||
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_RFFT_F32_32)
|
||||
extern const float32_t twiddleCoef_rfft_32[32];
|
||||
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_RFFT_F32_64)
|
||||
extern const float32_t twiddleCoef_rfft_64[64];
|
||||
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_RFFT_F32_128)
|
||||
extern const float32_t twiddleCoef_rfft_128[128];
|
||||
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_RFFT_F32_256)
|
||||
extern const float32_t twiddleCoef_rfft_256[256];
|
||||
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_RFFT_F32_512)
|
||||
extern const float32_t twiddleCoef_rfft_512[512];
|
||||
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_RFFT_F32_1024)
|
||||
extern const float32_t twiddleCoef_rfft_1024[1024];
|
||||
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_RFFT_F32_2048)
|
||||
extern const float32_t twiddleCoef_rfft_2048[2048];
|
||||
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_RFFT_F32_4096)
|
||||
extern const float32_t twiddleCoef_rfft_4096[4096];
|
||||
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
|
||||
|
||||
|
||||
/* Double precision floating-point bit reversal tables */
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FLT64_16)
|
||||
#define ARMBITREVINDEXTABLEF64_16_TABLE_LENGTH ((uint16_t)12)
|
||||
extern const uint16_t armBitRevIndexTableF64_16[ARMBITREVINDEXTABLEF64_16_TABLE_LENGTH];
|
||||
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FLT64_32)
|
||||
#define ARMBITREVINDEXTABLEF64_32_TABLE_LENGTH ((uint16_t)24)
|
||||
extern const uint16_t armBitRevIndexTableF64_32[ARMBITREVINDEXTABLEF64_32_TABLE_LENGTH];
|
||||
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FLT64_64)
|
||||
#define ARMBITREVINDEXTABLEF64_64_TABLE_LENGTH ((uint16_t)56)
|
||||
extern const uint16_t armBitRevIndexTableF64_64[ARMBITREVINDEXTABLEF64_64_TABLE_LENGTH];
|
||||
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FLT64_128)
|
||||
#define ARMBITREVINDEXTABLEF64_128_TABLE_LENGTH ((uint16_t)112)
|
||||
extern const uint16_t armBitRevIndexTableF64_128[ARMBITREVINDEXTABLEF64_128_TABLE_LENGTH];
|
||||
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FLT64_256)
|
||||
#define ARMBITREVINDEXTABLEF64_256_TABLE_LENGTH ((uint16_t)240)
|
||||
extern const uint16_t armBitRevIndexTableF64_256[ARMBITREVINDEXTABLEF64_256_TABLE_LENGTH];
|
||||
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FLT64_512)
|
||||
#define ARMBITREVINDEXTABLEF64_512_TABLE_LENGTH ((uint16_t)480)
|
||||
extern const uint16_t armBitRevIndexTableF64_512[ARMBITREVINDEXTABLEF64_512_TABLE_LENGTH];
|
||||
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FLT64_1024)
|
||||
#define ARMBITREVINDEXTABLEF64_1024_TABLE_LENGTH ((uint16_t)992)
|
||||
extern const uint16_t armBitRevIndexTableF64_1024[ARMBITREVINDEXTABLEF64_1024_TABLE_LENGTH];
|
||||
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FLT64_2048)
|
||||
#define ARMBITREVINDEXTABLEF64_2048_TABLE_LENGTH ((uint16_t)1984)
|
||||
extern const uint16_t armBitRevIndexTableF64_2048[ARMBITREVINDEXTABLEF64_2048_TABLE_LENGTH];
|
||||
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FLT64_4096)
|
||||
#define ARMBITREVINDEXTABLEF64_4096_TABLE_LENGTH ((uint16_t)4032)
|
||||
extern const uint16_t armBitRevIndexTableF64_4096[ARMBITREVINDEXTABLEF64_4096_TABLE_LENGTH];
|
||||
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
|
||||
/* floating-point bit reversal tables */
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FLT_16)
|
||||
#define ARMBITREVINDEXTABLE_16_TABLE_LENGTH ((uint16_t)20)
|
||||
extern const uint16_t armBitRevIndexTable16[ARMBITREVINDEXTABLE_16_TABLE_LENGTH];
|
||||
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FLT_32)
|
||||
#define ARMBITREVINDEXTABLE_32_TABLE_LENGTH ((uint16_t)48)
|
||||
extern const uint16_t armBitRevIndexTable32[ARMBITREVINDEXTABLE_32_TABLE_LENGTH];
|
||||
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FLT_64)
|
||||
#define ARMBITREVINDEXTABLE_64_TABLE_LENGTH ((uint16_t)56)
|
||||
extern const uint16_t armBitRevIndexTable64[ARMBITREVINDEXTABLE_64_TABLE_LENGTH];
|
||||
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FLT_128)
|
||||
#define ARMBITREVINDEXTABLE_128_TABLE_LENGTH ((uint16_t)208)
|
||||
extern const uint16_t armBitRevIndexTable128[ARMBITREVINDEXTABLE_128_TABLE_LENGTH];
|
||||
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FLT_256)
|
||||
#define ARMBITREVINDEXTABLE_256_TABLE_LENGTH ((uint16_t)440)
|
||||
extern const uint16_t armBitRevIndexTable256[ARMBITREVINDEXTABLE_256_TABLE_LENGTH];
|
||||
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FLT_512)
|
||||
#define ARMBITREVINDEXTABLE_512_TABLE_LENGTH ((uint16_t)448)
|
||||
extern const uint16_t armBitRevIndexTable512[ARMBITREVINDEXTABLE_512_TABLE_LENGTH];
|
||||
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FLT_1024)
|
||||
#define ARMBITREVINDEXTABLE_1024_TABLE_LENGTH ((uint16_t)1800)
|
||||
extern const uint16_t armBitRevIndexTable1024[ARMBITREVINDEXTABLE_1024_TABLE_LENGTH];
|
||||
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FLT_2048)
|
||||
#define ARMBITREVINDEXTABLE_2048_TABLE_LENGTH ((uint16_t)3808)
|
||||
extern const uint16_t armBitRevIndexTable2048[ARMBITREVINDEXTABLE_2048_TABLE_LENGTH];
|
||||
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FLT_4096)
|
||||
#define ARMBITREVINDEXTABLE_4096_TABLE_LENGTH ((uint16_t)4032)
|
||||
extern const uint16_t armBitRevIndexTable4096[ARMBITREVINDEXTABLE_4096_TABLE_LENGTH];
|
||||
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
|
||||
|
||||
|
||||
/* fixed-point bit reversal tables */
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FXT_16)
|
||||
#define ARMBITREVINDEXTABLE_FIXED_16_TABLE_LENGTH ((uint16_t)12)
|
||||
extern const uint16_t armBitRevIndexTable_fixed_16[ARMBITREVINDEXTABLE_FIXED_16_TABLE_LENGTH];
|
||||
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FXT_32)
|
||||
#define ARMBITREVINDEXTABLE_FIXED_32_TABLE_LENGTH ((uint16_t)24)
|
||||
extern const uint16_t armBitRevIndexTable_fixed_32[ARMBITREVINDEXTABLE_FIXED_32_TABLE_LENGTH];
|
||||
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FXT_64)
|
||||
#define ARMBITREVINDEXTABLE_FIXED_64_TABLE_LENGTH ((uint16_t)56)
|
||||
extern const uint16_t armBitRevIndexTable_fixed_64[ARMBITREVINDEXTABLE_FIXED_64_TABLE_LENGTH];
|
||||
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FXT_128)
|
||||
#define ARMBITREVINDEXTABLE_FIXED_128_TABLE_LENGTH ((uint16_t)112)
|
||||
extern const uint16_t armBitRevIndexTable_fixed_128[ARMBITREVINDEXTABLE_FIXED_128_TABLE_LENGTH];
|
||||
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FXT_256)
|
||||
#define ARMBITREVINDEXTABLE_FIXED_256_TABLE_LENGTH ((uint16_t)240)
|
||||
extern const uint16_t armBitRevIndexTable_fixed_256[ARMBITREVINDEXTABLE_FIXED_256_TABLE_LENGTH];
|
||||
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FXT_512)
|
||||
#define ARMBITREVINDEXTABLE_FIXED_512_TABLE_LENGTH ((uint16_t)480)
|
||||
extern const uint16_t armBitRevIndexTable_fixed_512[ARMBITREVINDEXTABLE_FIXED_512_TABLE_LENGTH];
|
||||
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FXT_1024)
|
||||
#define ARMBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH ((uint16_t)992)
|
||||
extern const uint16_t armBitRevIndexTable_fixed_1024[ARMBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH];
|
||||
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FXT_2048)
|
||||
#define ARMBITREVINDEXTABLE_FIXED_2048_TABLE_LENGTH ((uint16_t)1984)
|
||||
extern const uint16_t armBitRevIndexTable_fixed_2048[ARMBITREVINDEXTABLE_FIXED_2048_TABLE_LENGTH];
|
||||
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_BITREVIDX_FXT_4096)
|
||||
#define ARMBITREVINDEXTABLE_FIXED_4096_TABLE_LENGTH ((uint16_t)4032)
|
||||
extern const uint16_t armBitRevIndexTable_fixed_4096[ARMBITREVINDEXTABLE_FIXED_4096_TABLE_LENGTH];
|
||||
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_REALCOEF_F32)
|
||||
extern const float32_t realCoefA[8192];
|
||||
extern const float32_t realCoefB[8192];
|
||||
#endif
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_REALCOEF_Q31)
|
||||
extern const q31_t realCoefAQ31[8192];
|
||||
extern const q31_t realCoefBQ31[8192];
|
||||
#endif
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_REALCOEF_Q15)
|
||||
extern const q15_t realCoefAQ15[8192];
|
||||
extern const q15_t realCoefBQ15[8192];
|
||||
#endif
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_DCT4_F32_128)
|
||||
extern const float32_t Weights_128[256];
|
||||
extern const float32_t cos_factors_128[128];
|
||||
#endif
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_DCT4_F32_512)
|
||||
extern const float32_t Weights_512[1024];
|
||||
extern const float32_t cos_factors_512[512];
|
||||
#endif
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_DCT4_F32_2048)
|
||||
extern const float32_t Weights_2048[4096];
|
||||
extern const float32_t cos_factors_2048[2048];
|
||||
#endif
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_DCT4_F32_8192)
|
||||
extern const float32_t Weights_8192[16384];
|
||||
extern const float32_t cos_factors_8192[8192];
|
||||
#endif
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_DCT4_Q15_128)
|
||||
extern const q15_t WeightsQ15_128[256];
|
||||
extern const q15_t cos_factorsQ15_128[128];
|
||||
#endif
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_DCT4_Q15_512)
|
||||
extern const q15_t WeightsQ15_512[1024];
|
||||
extern const q15_t cos_factorsQ15_512[512];
|
||||
#endif
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_DCT4_Q15_2048)
|
||||
extern const q15_t WeightsQ15_2048[4096];
|
||||
extern const q15_t cos_factorsQ15_2048[2048];
|
||||
#endif
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_DCT4_Q15_8192)
|
||||
extern const q15_t WeightsQ15_8192[16384];
|
||||
extern const q15_t cos_factorsQ15_8192[8192];
|
||||
#endif
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_DCT4_Q31_128)
|
||||
extern const q31_t WeightsQ31_128[256];
|
||||
extern const q31_t cos_factorsQ31_128[128];
|
||||
#endif
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_DCT4_Q31_512)
|
||||
extern const q31_t WeightsQ31_512[1024];
|
||||
extern const q31_t cos_factorsQ31_512[512];
|
||||
#endif
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_DCT4_Q31_2048)
|
||||
extern const q31_t WeightsQ31_2048[4096];
|
||||
extern const q31_t cos_factorsQ31_2048[2048];
|
||||
#endif
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_DCT4_Q31_8192)
|
||||
extern const q31_t WeightsQ31_8192[16384];
|
||||
extern const q31_t cos_factorsQ31_8192[8192];
|
||||
#endif
|
||||
|
||||
#endif /* if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_FFT_TABLES) */
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_FAST_ALLOW_TABLES)
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FAST_TABLES) || defined(ARM_TABLE_RECIP_Q15)
|
||||
extern const q15_t armRecipTableQ15[64];
|
||||
#endif /* !defined(ARM_DSP_CONFIG_TABLES) defined(ARM_ALL_FAST_TABLES) */
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FAST_TABLES) || defined(ARM_TABLE_RECIP_Q31)
|
||||
extern const q31_t armRecipTableQ31[64];
|
||||
#endif /* !defined(ARM_DSP_CONFIG_TABLES) defined(ARM_ALL_FAST_TABLES) */
|
||||
|
||||
/* Tables for Fast Math Sine and Cosine */
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FAST_TABLES) || defined(ARM_TABLE_SIN_F32)
|
||||
extern const float32_t sinTable_f32[FAST_MATH_TABLE_SIZE + 1];
|
||||
#endif /* !defined(ARM_DSP_CONFIG_TABLES) defined(ARM_ALL_FAST_TABLES) */
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FAST_TABLES) || defined(ARM_TABLE_SIN_Q31)
|
||||
extern const q31_t sinTable_q31[FAST_MATH_TABLE_SIZE + 1];
|
||||
#endif /* !defined(ARM_DSP_CONFIG_TABLES) defined(ARM_ALL_FAST_TABLES) */
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FAST_TABLES) || defined(ARM_TABLE_SIN_Q15)
|
||||
extern const q15_t sinTable_q15[FAST_MATH_TABLE_SIZE + 1];
|
||||
#endif /* !defined(ARM_DSP_CONFIG_TABLES) defined(ARM_ALL_FAST_TABLES) */
|
||||
|
||||
/* Fast vector sqrt */
|
||||
#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE)
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FAST_TABLES) || defined(ARM_TABLE_FAST_SQRT_Q31_MVE)
|
||||
extern const q31_t sqrtTable_Q31[256];
|
||||
#endif /* !defined(ARM_DSP_CONFIG_TABLES) defined(ARM_ALL_FAST_TABLES) */
|
||||
#endif
|
||||
|
||||
/* Accurate scalar sqrt */
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FAST_TABLES) || defined(ARM_TABLE_SQRT_Q31)
|
||||
extern const q31_t sqrt_initial_lut_q31[32];
|
||||
#endif
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FAST_TABLES) || defined(ARM_TABLE_SQRT_Q15)
|
||||
extern const q15_t sqrt_initial_lut_q15[16];
|
||||
#endif
|
||||
|
||||
#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE)
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FAST_TABLES) || defined(ARM_TABLE_FAST_SQRT_Q15_MVE)
|
||||
extern const q15_t sqrtTable_Q15[256];
|
||||
#endif /* !defined(ARM_DSP_CONFIG_TABLES) defined(ARM_ALL_FAST_TABLES) */
|
||||
#endif
|
||||
|
||||
#endif /* if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_FAST_TABLES) */
|
||||
|
||||
#if (defined(ARM_MATH_MVEF) || defined(ARM_MATH_HELIUM)) && !defined(ARM_MATH_AUTOVECTORIZE)
|
||||
extern const float32_t exp_tab[8];
|
||||
extern const float32_t __logf_lut_f32[8];
|
||||
#endif /* (defined(ARM_MATH_MVEF) || defined(ARM_MATH_HELIUM)) && !defined(ARM_MATH_AUTOVECTORIZE) */
|
||||
|
||||
#if (defined(ARM_MATH_MVEI) || defined(ARM_MATH_HELIUM)) && !defined(ARM_MATH_AUTOVECTORIZE)
|
||||
extern const unsigned char hwLUT[256];
|
||||
#endif /* (defined(ARM_MATH_MVEI) || defined(ARM_MATH_HELIUM)) */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* ARM_COMMON_TABLES_H */
|
||||
|
||||
|
|
@ -0,0 +1,132 @@
|
|||
/* ----------------------------------------------------------------------
|
||||
* Project: CMSIS DSP Library
|
||||
* Title: arm_common_tables_f16.h
|
||||
* Description: Extern declaration for common tables
|
||||
*
|
||||
* @version V1.10.0
|
||||
* @date 08 July 2021
|
||||
*
|
||||
* Target Processor: Cortex-M and Cortex-A cores
|
||||
* -------------------------------------------------------------------- */
|
||||
/*
|
||||
* Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
#ifndef _ARM_COMMON_TABLES_F16_H
|
||||
#define _ARM_COMMON_TABLES_F16_H
|
||||
|
||||
#include "arm_math_types_f16.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_FFT_ALLOW_TABLES)
|
||||
|
||||
/* F16 */
|
||||
#if !defined(__CC_ARM) && defined(ARM_FLOAT16_SUPPORTED)
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F16_16)
|
||||
extern const float16_t twiddleCoefF16_16[32];
|
||||
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F16_32)
|
||||
extern const float16_t twiddleCoefF16_32[64];
|
||||
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F16_64)
|
||||
extern const float16_t twiddleCoefF16_64[128];
|
||||
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F16_128)
|
||||
extern const float16_t twiddleCoefF16_128[256];
|
||||
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F16_256)
|
||||
extern const float16_t twiddleCoefF16_256[512];
|
||||
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F16_512)
|
||||
extern const float16_t twiddleCoefF16_512[1024];
|
||||
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F16_1024)
|
||||
extern const float16_t twiddleCoefF16_1024[2048];
|
||||
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F16_2048)
|
||||
extern const float16_t twiddleCoefF16_2048[4096];
|
||||
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F16_4096)
|
||||
extern const float16_t twiddleCoefF16_4096[8192];
|
||||
#define twiddleCoefF16 twiddleCoefF16_4096
|
||||
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) */
|
||||
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_RFFT_F16_32)
|
||||
extern const float16_t twiddleCoefF16_rfft_32[32];
|
||||
#endif
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_RFFT_F16_64)
|
||||
extern const float16_t twiddleCoefF16_rfft_64[64];
|
||||
#endif
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_RFFT_F16_128)
|
||||
extern const float16_t twiddleCoefF16_rfft_128[128];
|
||||
#endif
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_RFFT_F16_256)
|
||||
extern const float16_t twiddleCoefF16_rfft_256[256];
|
||||
#endif
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_RFFT_F16_512)
|
||||
extern const float16_t twiddleCoefF16_rfft_512[512];
|
||||
#endif
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_RFFT_F16_1024)
|
||||
extern const float16_t twiddleCoefF16_rfft_1024[1024];
|
||||
#endif
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_RFFT_F16_2048)
|
||||
extern const float16_t twiddleCoefF16_rfft_2048[2048];
|
||||
#endif
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_RFFT_F16_4096)
|
||||
extern const float16_t twiddleCoefF16_rfft_4096[4096];
|
||||
#endif
|
||||
|
||||
#endif /* ARMAC5 */
|
||||
|
||||
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_FFT_ALLOW_TABLES) */
|
||||
|
||||
#if !defined(__CC_ARM) && defined(ARM_FLOAT16_SUPPORTED)
|
||||
|
||||
#if (defined(ARM_MATH_MVEF) || defined(ARM_MATH_HELIUM)) && !defined(ARM_MATH_AUTOVECTORIZE)
|
||||
extern const float16_t exp_tab_f16[8];
|
||||
extern const float16_t __logf_lut_f16[8];
|
||||
#endif /* (defined(ARM_MATH_MVEF) || defined(ARM_MATH_HELIUM)) && !defined(ARM_MATH_AUTOVECTORIZE) */
|
||||
#endif
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* _ARM_COMMON_TABLES_F16_H */
|
||||
|
||||
|
||||
|
|
@ -0,0 +1,86 @@
|
|||
/* ----------------------------------------------------------------------
|
||||
* Project: CMSIS DSP Library
|
||||
* Title: arm_const_structs.h
|
||||
* Description: Constant structs that are initialized for user convenience.
|
||||
* For example, some can be given as arguments to the arm_cfft_f32() function.
|
||||
*
|
||||
* @version V1.10.0
|
||||
* @date 08 July 2021
|
||||
*
|
||||
* Target Processor: Cortex-M and Cortex-A cores
|
||||
* -------------------------------------------------------------------- */
|
||||
/*
|
||||
* Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
#ifndef _ARM_CONST_STRUCTS_H
|
||||
#define _ARM_CONST_STRUCTS_H
|
||||
|
||||
#include "arm_math_types.h"
|
||||
#include "arm_common_tables.h"
|
||||
#include "dsp/transform_functions.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
extern const arm_cfft_instance_f64 arm_cfft_sR_f64_len16;
|
||||
extern const arm_cfft_instance_f64 arm_cfft_sR_f64_len32;
|
||||
extern const arm_cfft_instance_f64 arm_cfft_sR_f64_len64;
|
||||
extern const arm_cfft_instance_f64 arm_cfft_sR_f64_len128;
|
||||
extern const arm_cfft_instance_f64 arm_cfft_sR_f64_len256;
|
||||
extern const arm_cfft_instance_f64 arm_cfft_sR_f64_len512;
|
||||
extern const arm_cfft_instance_f64 arm_cfft_sR_f64_len1024;
|
||||
extern const arm_cfft_instance_f64 arm_cfft_sR_f64_len2048;
|
||||
extern const arm_cfft_instance_f64 arm_cfft_sR_f64_len4096;
|
||||
|
||||
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len16;
|
||||
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len32;
|
||||
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len64;
|
||||
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len128;
|
||||
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len256;
|
||||
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len512;
|
||||
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len1024;
|
||||
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len2048;
|
||||
extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len4096;
|
||||
|
||||
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len16;
|
||||
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len32;
|
||||
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len64;
|
||||
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len128;
|
||||
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len256;
|
||||
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len512;
|
||||
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len1024;
|
||||
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len2048;
|
||||
extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len4096;
|
||||
|
||||
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len16;
|
||||
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len32;
|
||||
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len64;
|
||||
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len128;
|
||||
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len256;
|
||||
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len512;
|
||||
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len1024;
|
||||
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len2048;
|
||||
extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len4096;
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
||||
|
|
@ -0,0 +1,77 @@
|
|||
/* ----------------------------------------------------------------------
|
||||
* Project: CMSIS DSP Library
|
||||
* Title: arm_const_structs_f16.h
|
||||
* Description: Constant structs that are initialized for user convenience.
|
||||
* For example, some can be given as arguments to the arm_cfft_f16() function.
|
||||
*
|
||||
* @version V1.10.0
|
||||
* @date 08 July 2021
|
||||
*
|
||||
* Target Processor: Cortex-M and Cortex-A cores
|
||||
* -------------------------------------------------------------------- */
|
||||
/*
|
||||
* Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
#ifndef _ARM_CONST_STRUCTS_F16_H
|
||||
#define _ARM_CONST_STRUCTS_F16_H
|
||||
|
||||
#include "arm_math_types_f16.h"
|
||||
#include "arm_common_tables.h"
|
||||
#include "arm_common_tables_f16.h"
|
||||
#include "dsp/transform_functions_f16.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
#if !defined(__CC_ARM) && defined(ARM_FLOAT16_SUPPORTED)
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_F16_16) && defined(ARM_TABLE_BITREVIDX_FLT_16))
|
||||
extern const arm_cfft_instance_f16 arm_cfft_sR_f16_len16;
|
||||
#endif
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_F16_32) && defined(ARM_TABLE_BITREVIDX_FLT_32))
|
||||
extern const arm_cfft_instance_f16 arm_cfft_sR_f16_len32;
|
||||
#endif
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_F16_64) && defined(ARM_TABLE_BITREVIDX_FLT_64))
|
||||
extern const arm_cfft_instance_f16 arm_cfft_sR_f16_len64;
|
||||
#endif
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_F16_128) && defined(ARM_TABLE_BITREVIDX_FLT_128))
|
||||
extern const arm_cfft_instance_f16 arm_cfft_sR_f16_len128;
|
||||
#endif
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_F16_256) && defined(ARM_TABLE_BITREVIDX_FLT_256))
|
||||
extern const arm_cfft_instance_f16 arm_cfft_sR_f16_len256;
|
||||
#endif
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_F16_512) && defined(ARM_TABLE_BITREVIDX_FLT_512))
|
||||
extern const arm_cfft_instance_f16 arm_cfft_sR_f16_len512;
|
||||
#endif
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_F16_1024) && defined(ARM_TABLE_BITREVIDX_FLT_1024))
|
||||
extern const arm_cfft_instance_f16 arm_cfft_sR_f16_len1024;
|
||||
#endif
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_F16_2048) && defined(ARM_TABLE_BITREVIDX_FLT_2048))
|
||||
extern const arm_cfft_instance_f16 arm_cfft_sR_f16_len2048;
|
||||
#endif
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || (defined(ARM_TABLE_TWIDDLECOEF_F16_4096) && defined(ARM_TABLE_BITREVIDX_FLT_4096))
|
||||
extern const arm_cfft_instance_f16 arm_cfft_sR_f16_len4096;
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,753 @@
|
|||
/* ----------------------------------------------------------------------
|
||||
* Project: CMSIS DSP Library
|
||||
* Title: arm_helium_utils.h
|
||||
* Description: Utility functions for Helium development
|
||||
*
|
||||
* @version V1.10.0
|
||||
* @date 08 July 2021
|
||||
*
|
||||
* Target Processor: Cortex-M and Cortex-A cores
|
||||
* -------------------------------------------------------------------- */
|
||||
/*
|
||||
* Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
#ifndef _ARM_UTILS_HELIUM_H_
|
||||
#define _ARM_UTILS_HELIUM_H_
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
/***************************************
|
||||
|
||||
Definitions available for MVEF and MVEI
|
||||
|
||||
***************************************/
|
||||
#if (defined (ARM_MATH_HELIUM) || defined(ARM_MATH_MVEF) || defined(ARM_MATH_MVEI)) && !defined(ARM_MATH_AUTOVECTORIZE)
|
||||
|
||||
#define INACTIVELANE 0 /* inactive lane content */
|
||||
|
||||
|
||||
#endif /* defined (ARM_MATH_HELIUM) || defined(ARM_MATH_MVEF) || defined(ARM_MATH_MVEI) */
|
||||
|
||||
/***************************************
|
||||
|
||||
Definitions available for MVEF only
|
||||
|
||||
***************************************/
|
||||
#if (defined (ARM_MATH_HELIUM) || defined(ARM_MATH_MVEF)) && !defined(ARM_MATH_AUTOVECTORIZE)
|
||||
|
||||
__STATIC_FORCEINLINE float32_t vecAddAcrossF32Mve(float32x4_t in)
|
||||
{
|
||||
float32_t acc;
|
||||
|
||||
acc = vgetq_lane(in, 0) + vgetq_lane(in, 1) +
|
||||
vgetq_lane(in, 2) + vgetq_lane(in, 3);
|
||||
|
||||
return acc;
|
||||
}
|
||||
|
||||
|
||||
|
||||
|
||||
/* newton initial guess */
|
||||
#define INVSQRT_MAGIC_F32 0x5f3759df
|
||||
#define INV_NEWTON_INIT_F32 0x7EF127EA
|
||||
|
||||
|
||||
#define INVSQRT_NEWTON_MVE_F32(invSqrt, xHalf, xStart)\
|
||||
{ \
|
||||
float32x4_t tmp; \
|
||||
\
|
||||
/* tmp = xhalf * x * x */ \
|
||||
tmp = vmulq(xStart, xStart); \
|
||||
tmp = vmulq(tmp, xHalf); \
|
||||
/* (1.5f - xhalf * x * x) */ \
|
||||
tmp = vsubq(vdupq_n_f32(1.5f), tmp); \
|
||||
/* x = x*(1.5f-xhalf*x*x); */ \
|
||||
invSqrt = vmulq(tmp, xStart); \
|
||||
}
|
||||
#endif /* defined (ARM_MATH_HELIUM) || defined(ARM_MATH_MVEF) */
|
||||
|
||||
|
||||
/***************************************
|
||||
|
||||
Definitions available for f16 datatype with HW acceleration only
|
||||
|
||||
***************************************/
|
||||
#if defined(ARM_FLOAT16_SUPPORTED)
|
||||
#if defined (ARM_MATH_MVE_FLOAT16) && !defined(ARM_MATH_AUTOVECTORIZE)
|
||||
|
||||
__STATIC_FORCEINLINE float16_t vecAddAcrossF16Mve(float16x8_t in)
|
||||
{
|
||||
float16x8_t tmpVec;
|
||||
_Float16 acc;
|
||||
|
||||
tmpVec = (float16x8_t) vrev32q_s16((int16x8_t) in);
|
||||
in = vaddq_f16(tmpVec, in);
|
||||
tmpVec = (float16x8_t) vrev64q_s32((int32x4_t) in);
|
||||
in = vaddq_f16(tmpVec, in);
|
||||
acc = (_Float16)vgetq_lane_f16(in, 0) + (_Float16)vgetq_lane_f16(in, 4);
|
||||
|
||||
return acc;
|
||||
}
|
||||
|
||||
__STATIC_FORCEINLINE float16x8_t __mve_cmplx_sum_intra_vec_f16(
|
||||
float16x8_t vecIn)
|
||||
{
|
||||
float16x8_t vecTmp, vecOut;
|
||||
uint32_t tmp;
|
||||
|
||||
vecTmp = (float16x8_t) vrev64q_s32((int32x4_t) vecIn);
|
||||
// TO TRACK : using canonical addition leads to unefficient code generation for f16
|
||||
// vecTmp = vecTmp + vecAccCpx0;
|
||||
/*
|
||||
* Compute
|
||||
* re0+re1 | im0+im1 | re0+re1 | im0+im1
|
||||
* re2+re3 | im2+im3 | re2+re3 | im2+im3
|
||||
*/
|
||||
vecTmp = vaddq_f16(vecTmp, vecIn);
|
||||
vecOut = vecTmp;
|
||||
/*
|
||||
* shift left, random tmp insertion in bottom
|
||||
*/
|
||||
vecOut = vreinterpretq_f16_s32(vshlcq_s32(vreinterpretq_s32_f16(vecOut) , &tmp, 32));
|
||||
/*
|
||||
* Compute:
|
||||
* DONTCARE | DONTCARE | re0+re1+re0+re1 |im0+im1+im0+im1
|
||||
* re0+re1+re2+re3 | im0+im1+im2+im3 | re2+re3+re2+re3 |im2+im3+im2+im3
|
||||
*/
|
||||
vecOut = vaddq_f16(vecOut, vecTmp);
|
||||
/*
|
||||
* Cmplx sum is in 4rd & 5th f16 elt
|
||||
* return full vector
|
||||
*/
|
||||
return vecOut;
|
||||
}
|
||||
|
||||
|
||||
#define mve_cmplx_sum_intra_r_i_f16(vec, Re, Im) \
|
||||
{ \
|
||||
float16x8_t vecOut = __mve_cmplx_sum_intra_vec_f16(vec); \
|
||||
Re = vgetq_lane(vecOut, 4); \
|
||||
Im = vgetq_lane(vecOut, 5); \
|
||||
}
|
||||
|
||||
__STATIC_FORCEINLINE void mve_cmplx_sum_intra_vec_f16(
|
||||
float16x8_t vecIn,
|
||||
float16_t *pOut)
|
||||
{
|
||||
float16x8_t vecOut = __mve_cmplx_sum_intra_vec_f16(vecIn);
|
||||
/*
|
||||
* Cmplx sum is in 4rd & 5th f16 elt
|
||||
* use 32-bit extraction
|
||||
*/
|
||||
*(float32_t *) pOut = ((float32x4_t) vecOut)[2];
|
||||
}
|
||||
|
||||
|
||||
#define INVSQRT_MAGIC_F16 0x59ba /* ( 0x1ba = 0x3759df >> 13) */
|
||||
|
||||
/* canonical version of INVSQRT_NEWTON_MVE_F16 leads to bad performance */
|
||||
#define INVSQRT_NEWTON_MVE_F16(invSqrt, xHalf, xStart) \
|
||||
{ \
|
||||
float16x8_t tmp; \
|
||||
\
|
||||
/* tmp = xhalf * x * x */ \
|
||||
tmp = vmulq(xStart, xStart); \
|
||||
tmp = vmulq(tmp, xHalf); \
|
||||
/* (1.5f - xhalf * x * x) */ \
|
||||
tmp = vsubq(vdupq_n_f16((float16_t)1.5), tmp); \
|
||||
/* x = x*(1.5f-xhalf*x*x); */ \
|
||||
invSqrt = vmulq(tmp, xStart); \
|
||||
}
|
||||
|
||||
#endif
|
||||
#endif
|
||||
|
||||
/***************************************
|
||||
|
||||
Definitions available for MVEI and MVEF only
|
||||
|
||||
***************************************/
|
||||
#if (defined (ARM_MATH_HELIUM) || defined(ARM_MATH_MVEF) || defined(ARM_MATH_MVEI)) && !defined(ARM_MATH_AUTOVECTORIZE)
|
||||
/* Following functions are used to transpose matrix in f32 and q31 cases */
|
||||
__STATIC_INLINE arm_status arm_mat_trans_32bit_2x2_mve(
|
||||
uint32_t * pDataSrc,
|
||||
uint32_t * pDataDest)
|
||||
{
|
||||
static const uint32x4_t vecOffs = { 0, 2, 1, 3 };
|
||||
/*
|
||||
*
|
||||
* | 0 1 | => | 0 2 |
|
||||
* | 2 3 | | 1 3 |
|
||||
*
|
||||
*/
|
||||
uint32x4_t vecIn = vldrwq_u32((uint32_t const *)pDataSrc);
|
||||
vstrwq_scatter_shifted_offset_u32(pDataDest, vecOffs, vecIn);
|
||||
|
||||
return (ARM_MATH_SUCCESS);
|
||||
}
|
||||
|
||||
__STATIC_INLINE arm_status arm_mat_trans_32bit_3x3_mve(
|
||||
uint32_t * pDataSrc,
|
||||
uint32_t * pDataDest)
|
||||
{
|
||||
const uint32x4_t vecOffs1 = { 0, 3, 6, 1};
|
||||
const uint32x4_t vecOffs2 = { 4, 7, 2, 5};
|
||||
/*
|
||||
*
|
||||
* | 0 1 2 | | 0 3 6 | 4 x 32 flattened version | 0 3 6 1 |
|
||||
* | 3 4 5 | => | 1 4 7 | => | 4 7 2 5 |
|
||||
* | 6 7 8 | | 2 5 8 | (row major) | 8 . . . |
|
||||
*
|
||||
*/
|
||||
uint32x4_t vecIn1 = vldrwq_u32((uint32_t const *) pDataSrc);
|
||||
uint32x4_t vecIn2 = vldrwq_u32((uint32_t const *) &pDataSrc[4]);
|
||||
|
||||
vstrwq_scatter_shifted_offset_u32(pDataDest, vecOffs1, vecIn1);
|
||||
vstrwq_scatter_shifted_offset_u32(pDataDest, vecOffs2, vecIn2);
|
||||
|
||||
pDataDest[8] = pDataSrc[8];
|
||||
|
||||
return (ARM_MATH_SUCCESS);
|
||||
}
|
||||
|
||||
__STATIC_INLINE arm_status arm_mat_trans_32bit_4x4_mve(uint32_t * pDataSrc, uint32_t * pDataDest)
|
||||
{
|
||||
/*
|
||||
* 4x4 Matrix transposition
|
||||
* is 4 x de-interleave operation
|
||||
*
|
||||
* 0 1 2 3 0 4 8 12
|
||||
* 4 5 6 7 1 5 9 13
|
||||
* 8 9 10 11 2 6 10 14
|
||||
* 12 13 14 15 3 7 11 15
|
||||
*/
|
||||
|
||||
uint32x4x4_t vecIn;
|
||||
|
||||
vecIn = vld4q((uint32_t const *) pDataSrc);
|
||||
vstrwq(pDataDest, vecIn.val[0]);
|
||||
pDataDest += 4;
|
||||
vstrwq(pDataDest, vecIn.val[1]);
|
||||
pDataDest += 4;
|
||||
vstrwq(pDataDest, vecIn.val[2]);
|
||||
pDataDest += 4;
|
||||
vstrwq(pDataDest, vecIn.val[3]);
|
||||
|
||||
return (ARM_MATH_SUCCESS);
|
||||
}
|
||||
|
||||
|
||||
__STATIC_INLINE arm_status arm_mat_trans_32bit_generic_mve(
|
||||
uint16_t srcRows,
|
||||
uint16_t srcCols,
|
||||
uint32_t * pDataSrc,
|
||||
uint32_t * pDataDest)
|
||||
{
|
||||
uint32x4_t vecOffs;
|
||||
uint32_t i;
|
||||
uint32_t blkCnt;
|
||||
uint32_t const *pDataC;
|
||||
uint32_t *pDataDestR;
|
||||
uint32x4_t vecIn;
|
||||
|
||||
vecOffs = vidupq_u32((uint32_t)0, 1);
|
||||
vecOffs = vecOffs * srcCols;
|
||||
|
||||
i = srcCols;
|
||||
do
|
||||
{
|
||||
pDataC = (uint32_t const *) pDataSrc;
|
||||
pDataDestR = pDataDest;
|
||||
|
||||
blkCnt = srcRows >> 2;
|
||||
while (blkCnt > 0U)
|
||||
{
|
||||
vecIn = vldrwq_gather_shifted_offset_u32(pDataC, vecOffs);
|
||||
vstrwq(pDataDestR, vecIn);
|
||||
pDataDestR += 4;
|
||||
pDataC = pDataC + srcCols * 4;
|
||||
/*
|
||||
* Decrement the blockSize loop counter
|
||||
*/
|
||||
blkCnt--;
|
||||
}
|
||||
|
||||
/*
|
||||
* tail
|
||||
*/
|
||||
blkCnt = srcRows & 3;
|
||||
if (blkCnt > 0U)
|
||||
{
|
||||
mve_pred16_t p0 = vctp32q(blkCnt);
|
||||
vecIn = vldrwq_gather_shifted_offset_u32(pDataC, vecOffs);
|
||||
vstrwq_p(pDataDestR, vecIn, p0);
|
||||
}
|
||||
|
||||
pDataSrc += 1;
|
||||
pDataDest += srcRows;
|
||||
}
|
||||
while (--i);
|
||||
|
||||
return (ARM_MATH_SUCCESS);
|
||||
}
|
||||
|
||||
__STATIC_INLINE arm_status arm_mat_cmplx_trans_32bit(
|
||||
uint16_t srcRows,
|
||||
uint16_t srcCols,
|
||||
uint32_t *pDataSrc,
|
||||
uint16_t dstRows,
|
||||
uint16_t dstCols,
|
||||
uint32_t *pDataDest)
|
||||
{
|
||||
uint32_t i;
|
||||
uint32_t const *pDataC;
|
||||
uint32_t *pDataRow;
|
||||
uint32_t *pDataDestR, *pDataDestRow;
|
||||
uint32x4_t vecOffsRef, vecOffsCur;
|
||||
uint32_t blkCnt;
|
||||
uint32x4_t vecIn;
|
||||
|
||||
#ifdef ARM_MATH_MATRIX_CHECK
|
||||
/*
|
||||
* Check for matrix mismatch condition
|
||||
*/
|
||||
if ((srcRows != dstCols) || (srcCols != dstRows))
|
||||
{
|
||||
/*
|
||||
* Set status as ARM_MATH_SIZE_MISMATCH
|
||||
*/
|
||||
return ARM_MATH_SIZE_MISMATCH;
|
||||
}
|
||||
#else
|
||||
(void)dstRows;
|
||||
(void)dstCols;
|
||||
#endif
|
||||
|
||||
/* 2x2, 3x3 and 4x4 specialization to be added */
|
||||
|
||||
vecOffsRef[0] = 0;
|
||||
vecOffsRef[1] = 1;
|
||||
vecOffsRef[2] = srcCols << 1;
|
||||
vecOffsRef[3] = (srcCols << 1) + 1;
|
||||
|
||||
pDataRow = pDataSrc;
|
||||
pDataDestRow = pDataDest;
|
||||
i = srcCols;
|
||||
do
|
||||
{
|
||||
pDataC = (uint32_t const *) pDataRow;
|
||||
pDataDestR = pDataDestRow;
|
||||
vecOffsCur = vecOffsRef;
|
||||
|
||||
blkCnt = (srcRows * CMPLX_DIM) >> 2;
|
||||
while (blkCnt > 0U)
|
||||
{
|
||||
vecIn = vldrwq_gather_shifted_offset(pDataC, vecOffsCur);
|
||||
vstrwq(pDataDestR, vecIn);
|
||||
pDataDestR += 4;
|
||||
vecOffsCur = vaddq(vecOffsCur, (srcCols << 2));
|
||||
/*
|
||||
* Decrement the blockSize loop counter
|
||||
*/
|
||||
blkCnt--;
|
||||
}
|
||||
/*
|
||||
* tail
|
||||
* (will be merged thru tail predication)
|
||||
*/
|
||||
blkCnt = (srcRows * CMPLX_DIM) & 3;
|
||||
if (blkCnt > 0U)
|
||||
{
|
||||
mve_pred16_t p0 = vctp32q(blkCnt);
|
||||
vecIn = vldrwq_gather_shifted_offset(pDataC, vecOffsCur);
|
||||
vstrwq_p(pDataDestR, vecIn, p0);
|
||||
}
|
||||
|
||||
pDataRow += CMPLX_DIM;
|
||||
pDataDestRow += (srcRows * CMPLX_DIM);
|
||||
}
|
||||
while (--i);
|
||||
|
||||
return (ARM_MATH_SUCCESS);
|
||||
}
|
||||
|
||||
__STATIC_INLINE arm_status arm_mat_trans_16bit_2x2(uint16_t * pDataSrc, uint16_t * pDataDest)
|
||||
{
|
||||
pDataDest[0] = pDataSrc[0];
|
||||
pDataDest[3] = pDataSrc[3];
|
||||
pDataDest[2] = pDataSrc[1];
|
||||
pDataDest[1] = pDataSrc[2];
|
||||
|
||||
return (ARM_MATH_SUCCESS);
|
||||
}
|
||||
|
||||
__STATIC_INLINE arm_status arm_mat_trans_16bit_3x3_mve(uint16_t * pDataSrc, uint16_t * pDataDest)
|
||||
{
|
||||
static const uint16_t stridesTr33[8] = { 0, 3, 6, 1, 4, 7, 2, 5 };
|
||||
uint16x8_t vecOffs1;
|
||||
uint16x8_t vecIn1;
|
||||
/*
|
||||
*
|
||||
* | 0 1 2 | | 0 3 6 | 8 x 16 flattened version | 0 3 6 1 4 7 2 5 |
|
||||
* | 3 4 5 | => | 1 4 7 | => | 8 . . . . . . . |
|
||||
* | 6 7 8 | | 2 5 8 | (row major)
|
||||
*
|
||||
*/
|
||||
vecOffs1 = vldrhq_u16((uint16_t const *) stridesTr33);
|
||||
vecIn1 = vldrhq_u16((uint16_t const *) pDataSrc);
|
||||
|
||||
vstrhq_scatter_shifted_offset_u16(pDataDest, vecOffs1, vecIn1);
|
||||
|
||||
pDataDest[8] = pDataSrc[8];
|
||||
|
||||
return (ARM_MATH_SUCCESS);
|
||||
}
|
||||
|
||||
|
||||
__STATIC_INLINE arm_status arm_mat_trans_16bit_4x4_mve(uint16_t * pDataSrc, uint16_t * pDataDest)
|
||||
{
|
||||
static const uint16_t stridesTr44_1[8] = { 0, 4, 8, 12, 1, 5, 9, 13 };
|
||||
static const uint16_t stridesTr44_2[8] = { 2, 6, 10, 14, 3, 7, 11, 15 };
|
||||
uint16x8_t vecOffs1, vecOffs2;
|
||||
uint16x8_t vecIn1, vecIn2;
|
||||
uint16_t const * pDataSrcVec = (uint16_t const *) pDataSrc;
|
||||
|
||||
/*
|
||||
* 4x4 Matrix transposition
|
||||
*
|
||||
* | 0 1 2 3 | | 0 4 8 12 | 8 x 16 flattened version
|
||||
* | 4 5 6 7 | => | 1 5 9 13 | => [0 4 8 12 1 5 9 13]
|
||||
* | 8 9 10 11 | | 2 6 10 14 | [2 6 10 14 3 7 11 15]
|
||||
* | 12 13 14 15 | | 3 7 11 15 |
|
||||
*/
|
||||
|
||||
vecOffs1 = vldrhq_u16((uint16_t const *) stridesTr44_1);
|
||||
vecOffs2 = vldrhq_u16((uint16_t const *) stridesTr44_2);
|
||||
vecIn1 = vldrhq_u16(pDataSrcVec);
|
||||
pDataSrcVec += 8;
|
||||
vecIn2 = vldrhq_u16(pDataSrcVec);
|
||||
|
||||
vstrhq_scatter_shifted_offset_u16(pDataDest, vecOffs1, vecIn1);
|
||||
vstrhq_scatter_shifted_offset_u16(pDataDest, vecOffs2, vecIn2);
|
||||
|
||||
|
||||
return (ARM_MATH_SUCCESS);
|
||||
}
|
||||
|
||||
|
||||
|
||||
__STATIC_INLINE arm_status arm_mat_trans_16bit_generic(
|
||||
uint16_t srcRows,
|
||||
uint16_t srcCols,
|
||||
uint16_t * pDataSrc,
|
||||
uint16_t * pDataDest)
|
||||
{
|
||||
uint16x8_t vecOffs;
|
||||
uint32_t i;
|
||||
uint32_t blkCnt;
|
||||
uint16_t const *pDataC;
|
||||
uint16_t *pDataDestR;
|
||||
uint16x8_t vecIn;
|
||||
|
||||
vecOffs = vidupq_u16((uint32_t)0, 1);
|
||||
vecOffs = vecOffs * srcCols;
|
||||
|
||||
i = srcCols;
|
||||
while(i > 0U)
|
||||
{
|
||||
pDataC = (uint16_t const *) pDataSrc;
|
||||
pDataDestR = pDataDest;
|
||||
|
||||
blkCnt = srcRows >> 3;
|
||||
while (blkCnt > 0U)
|
||||
{
|
||||
vecIn = vldrhq_gather_shifted_offset_u16(pDataC, vecOffs);
|
||||
vstrhq_u16(pDataDestR, vecIn);
|
||||
pDataDestR += 8;
|
||||
pDataC = pDataC + srcCols * 8;
|
||||
/*
|
||||
* Decrement the blockSize loop counter
|
||||
*/
|
||||
blkCnt--;
|
||||
}
|
||||
|
||||
/*
|
||||
* tail
|
||||
*/
|
||||
blkCnt = srcRows & 7;
|
||||
if (blkCnt > 0U)
|
||||
{
|
||||
mve_pred16_t p0 = vctp16q(blkCnt);
|
||||
vecIn = vldrhq_gather_shifted_offset_u16(pDataC, vecOffs);
|
||||
vstrhq_p_u16(pDataDestR, vecIn, p0);
|
||||
}
|
||||
pDataSrc += 1;
|
||||
pDataDest += srcRows;
|
||||
i--;
|
||||
}
|
||||
|
||||
return (ARM_MATH_SUCCESS);
|
||||
}
|
||||
|
||||
|
||||
__STATIC_INLINE arm_status arm_mat_cmplx_trans_16bit(
|
||||
uint16_t srcRows,
|
||||
uint16_t srcCols,
|
||||
uint16_t *pDataSrc,
|
||||
uint16_t dstRows,
|
||||
uint16_t dstCols,
|
||||
uint16_t *pDataDest)
|
||||
{
|
||||
static const uint16_t loadCmplxCol[8] = { 0, 0, 1, 1, 2, 2, 3, 3 };
|
||||
int i;
|
||||
uint16x8_t vecOffsRef, vecOffsCur;
|
||||
uint16_t const *pDataC;
|
||||
uint16_t *pDataRow;
|
||||
uint16_t *pDataDestR, *pDataDestRow;
|
||||
uint32_t blkCnt;
|
||||
uint16x8_t vecIn;
|
||||
|
||||
#ifdef ARM_MATH_MATRIX_CHECK
|
||||
/*
|
||||
* Check for matrix mismatch condition
|
||||
*/
|
||||
if ((srcRows != dstCols) || (srcCols != dstRows))
|
||||
{
|
||||
/*
|
||||
* Set status as ARM_MATH_SIZE_MISMATCH
|
||||
*/
|
||||
return ARM_MATH_SIZE_MISMATCH;
|
||||
}
|
||||
#else
|
||||
(void)dstRows;
|
||||
(void)dstCols;
|
||||
#endif
|
||||
|
||||
/*
|
||||
* 2x2, 3x3 and 4x4 specialization to be added
|
||||
*/
|
||||
|
||||
|
||||
/*
|
||||
* build [0, 1, 2xcol, 2xcol+1, 4xcol, 4xcol+1, 6xcol, 6xcol+1]
|
||||
*/
|
||||
vecOffsRef = vldrhq_u16((uint16_t const *) loadCmplxCol);
|
||||
vecOffsRef = vmulq(vecOffsRef, (uint16_t) (srcCols * CMPLX_DIM))
|
||||
+ viwdupq_u16((uint32_t)0, (uint16_t) 2, 1);
|
||||
|
||||
pDataRow = pDataSrc;
|
||||
pDataDestRow = pDataDest;
|
||||
i = srcCols;
|
||||
do
|
||||
{
|
||||
pDataC = (uint16_t const *) pDataRow;
|
||||
pDataDestR = pDataDestRow;
|
||||
vecOffsCur = vecOffsRef;
|
||||
|
||||
blkCnt = (srcRows * CMPLX_DIM) >> 3;
|
||||
while (blkCnt > 0U)
|
||||
{
|
||||
vecIn = vldrhq_gather_shifted_offset(pDataC, vecOffsCur);
|
||||
vstrhq(pDataDestR, vecIn);
|
||||
pDataDestR+= 8; // VEC_LANES_U16
|
||||
vecOffsCur = vaddq(vecOffsCur, (srcCols << 3));
|
||||
/*
|
||||
* Decrement the blockSize loop counter
|
||||
*/
|
||||
blkCnt--;
|
||||
}
|
||||
/*
|
||||
* tail
|
||||
* (will be merged thru tail predication)
|
||||
*/
|
||||
blkCnt = (srcRows * CMPLX_DIM) & 0x7;
|
||||
if (blkCnt > 0U)
|
||||
{
|
||||
mve_pred16_t p0 = vctp16q(blkCnt);
|
||||
vecIn = vldrhq_gather_shifted_offset(pDataC, vecOffsCur);
|
||||
vstrhq_p(pDataDestR, vecIn, p0);
|
||||
}
|
||||
|
||||
pDataRow += CMPLX_DIM;
|
||||
pDataDestRow += (srcRows * CMPLX_DIM);
|
||||
}
|
||||
while (--i);
|
||||
|
||||
return (ARM_MATH_SUCCESS);
|
||||
}
|
||||
#endif /* MVEF and MVEI */
|
||||
|
||||
/***************************************
|
||||
|
||||
Definitions available for MVEI only
|
||||
|
||||
***************************************/
|
||||
#if (defined (ARM_MATH_HELIUM) || defined(ARM_MATH_MVEI)) && !defined(ARM_MATH_AUTOVECTORIZE)
|
||||
|
||||
#include "arm_common_tables.h"
|
||||
|
||||
#define MVE_ASRL_SAT16(acc, shift) ((sqrshrl_sat48(acc, -(32-shift)) >> 32) & 0xffffffff)
|
||||
#define MVE_ASRL_SAT32(acc, shift) ((sqrshrl(acc, -(32-shift)) >> 32) & 0xffffffff)
|
||||
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FAST_TABLES) || defined(ARM_TABLE_FAST_SQRT_Q31_MVE)
|
||||
__STATIC_INLINE q31x4_t FAST_VSQRT_Q31(q31x4_t vecIn)
|
||||
{
|
||||
q63x2_t vecTmpLL;
|
||||
q31x4_t vecTmp0, vecTmp1;
|
||||
q31_t scale;
|
||||
q63_t tmp64;
|
||||
q31x4_t vecNrm, vecDst, vecIdx, vecSignBits;
|
||||
|
||||
|
||||
vecSignBits = vclsq(vecIn);
|
||||
vecSignBits = vbicq_n_s32(vecSignBits, 1);
|
||||
/*
|
||||
* in = in << no_of_sign_bits;
|
||||
*/
|
||||
vecNrm = vshlq(vecIn, vecSignBits);
|
||||
/*
|
||||
* index = in >> 24;
|
||||
*/
|
||||
vecIdx = vecNrm >> 24;
|
||||
vecIdx = vecIdx << 1;
|
||||
|
||||
vecTmp0 = vldrwq_gather_shifted_offset_s32(sqrtTable_Q31, (uint32x4_t)vecIdx);
|
||||
|
||||
vecIdx = vecIdx + 1;
|
||||
|
||||
vecTmp1 = vldrwq_gather_shifted_offset_s32(sqrtTable_Q31, (uint32x4_t)vecIdx);
|
||||
|
||||
vecTmp1 = vqrdmulhq(vecTmp1, vecNrm);
|
||||
vecTmp0 = vecTmp0 - vecTmp1;
|
||||
vecTmp1 = vqrdmulhq(vecTmp0, vecTmp0);
|
||||
vecTmp1 = vqrdmulhq(vecNrm, vecTmp1);
|
||||
vecTmp1 = vdupq_n_s32(0x18000000) - vecTmp1;
|
||||
vecTmp0 = vqrdmulhq(vecTmp0, vecTmp1);
|
||||
vecTmpLL = vmullbq_int(vecNrm, vecTmp0);
|
||||
|
||||
/*
|
||||
* scale elements 0, 2
|
||||
*/
|
||||
scale = 26 + (vecSignBits[0] >> 1);
|
||||
tmp64 = asrl(vecTmpLL[0], scale);
|
||||
vecDst[0] = (q31_t) tmp64;
|
||||
|
||||
scale = 26 + (vecSignBits[2] >> 1);
|
||||
tmp64 = asrl(vecTmpLL[1], scale);
|
||||
vecDst[2] = (q31_t) tmp64;
|
||||
|
||||
vecTmpLL = vmulltq_int(vecNrm, vecTmp0);
|
||||
|
||||
/*
|
||||
* scale elements 1, 3
|
||||
*/
|
||||
scale = 26 + (vecSignBits[1] >> 1);
|
||||
tmp64 = asrl(vecTmpLL[0], scale);
|
||||
vecDst[1] = (q31_t) tmp64;
|
||||
|
||||
scale = 26 + (vecSignBits[3] >> 1);
|
||||
tmp64 = asrl(vecTmpLL[1], scale);
|
||||
vecDst[3] = (q31_t) tmp64;
|
||||
/*
|
||||
* set negative values to 0
|
||||
*/
|
||||
vecDst = vdupq_m(vecDst, 0, vcmpltq_n_s32(vecIn, 0));
|
||||
|
||||
return vecDst;
|
||||
}
|
||||
#endif
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FAST_TABLES) || defined(ARM_TABLE_FAST_SQRT_Q15_MVE)
|
||||
__STATIC_INLINE q15x8_t FAST_VSQRT_Q15(q15x8_t vecIn)
|
||||
{
|
||||
q31x4_t vecTmpLev, vecTmpLodd, vecSignL;
|
||||
q15x8_t vecTmp0, vecTmp1;
|
||||
q15x8_t vecNrm, vecDst, vecIdx, vecSignBits;
|
||||
|
||||
vecDst = vuninitializedq_s16();
|
||||
|
||||
vecSignBits = vclsq(vecIn);
|
||||
vecSignBits = vbicq_n_s16(vecSignBits, 1);
|
||||
/*
|
||||
* in = in << no_of_sign_bits;
|
||||
*/
|
||||
vecNrm = vshlq(vecIn, vecSignBits);
|
||||
|
||||
vecIdx = vecNrm >> 8;
|
||||
vecIdx = vecIdx << 1;
|
||||
|
||||
vecTmp0 = vldrhq_gather_shifted_offset_s16(sqrtTable_Q15, (uint16x8_t)vecIdx);
|
||||
|
||||
vecIdx = vecIdx + 1;
|
||||
|
||||
vecTmp1 = vldrhq_gather_shifted_offset_s16(sqrtTable_Q15, (uint16x8_t)vecIdx);
|
||||
|
||||
vecTmp1 = vqrdmulhq(vecTmp1, vecNrm);
|
||||
vecTmp0 = vecTmp0 - vecTmp1;
|
||||
vecTmp1 = vqrdmulhq(vecTmp0, vecTmp0);
|
||||
vecTmp1 = vqrdmulhq(vecNrm, vecTmp1);
|
||||
vecTmp1 = vdupq_n_s16(0x1800) - vecTmp1;
|
||||
vecTmp0 = vqrdmulhq(vecTmp0, vecTmp1);
|
||||
|
||||
vecSignBits = vecSignBits >> 1;
|
||||
|
||||
vecTmpLev = vmullbq_int(vecNrm, vecTmp0);
|
||||
vecTmpLodd = vmulltq_int(vecNrm, vecTmp0);
|
||||
|
||||
vecTmp0 = vecSignBits + 10;
|
||||
/*
|
||||
* negate sign to apply register based vshl
|
||||
*/
|
||||
vecTmp0 = -vecTmp0;
|
||||
|
||||
/*
|
||||
* shift even elements
|
||||
*/
|
||||
vecSignL = vmovlbq(vecTmp0);
|
||||
vecTmpLev = vshlq(vecTmpLev, vecSignL);
|
||||
/*
|
||||
* shift odd elements
|
||||
*/
|
||||
vecSignL = vmovltq(vecTmp0);
|
||||
vecTmpLodd = vshlq(vecTmpLodd, vecSignL);
|
||||
/*
|
||||
* merge and narrow odd and even parts
|
||||
*/
|
||||
vecDst = vmovnbq_s32(vecDst, vecTmpLev);
|
||||
vecDst = vmovntq_s32(vecDst, vecTmpLodd);
|
||||
/*
|
||||
* set negative values to 0
|
||||
*/
|
||||
vecDst = vdupq_m(vecDst, 0, vcmpltq_n_s16(vecIn, 0));
|
||||
|
||||
return vecDst;
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* defined (ARM_MATH_HELIUM) || defined(ARM_MATH_MVEI) */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,236 @@
|
|||
/******************************************************************************
|
||||
* @file arm_math.h
|
||||
* @brief Public header file for CMSIS DSP Library
|
||||
* @version V1.10.0
|
||||
* @date 08 July 2021
|
||||
* Target Processor: Cortex-M and Cortex-A cores
|
||||
******************************************************************************/
|
||||
/*
|
||||
* Copyright (c) 2010-2021 Arm Limited or its affiliates. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
/**
|
||||
\mainpage CMSIS DSP Software Library
|
||||
*
|
||||
* \section intro Introduction
|
||||
*
|
||||
* This user manual describes the CMSIS DSP software library,
|
||||
* a suite of common signal processing functions for use on Cortex-M and Cortex-A processor
|
||||
* based devices.
|
||||
*
|
||||
* The library is divided into a number of functions each covering a specific category:
|
||||
* - Basic math functions
|
||||
* - Fast math functions
|
||||
* - Complex math functions
|
||||
* - Filtering functions
|
||||
* - Matrix functions
|
||||
* - Transform functions
|
||||
* - Motor control functions
|
||||
* - Statistical functions
|
||||
* - Support functions
|
||||
* - Interpolation functions
|
||||
* - Support Vector Machine functions (SVM)
|
||||
* - Bayes classifier functions
|
||||
* - Distance functions
|
||||
* - Quaternion functions
|
||||
*
|
||||
* The library has generally separate functions for operating on 8-bit integers, 16-bit integers,
|
||||
* 32-bit integer and 32-bit floating-point values.
|
||||
*
|
||||
* The library is providing vectorized versions of most algorthms for Helium
|
||||
* and of most f32 algorithms for Neon.
|
||||
*
|
||||
* When using a vectorized version, provide a little bit of padding after the end of
|
||||
* a buffer (3 words) because the vectorized code may read a little bit after the end
|
||||
* of a buffer. You don't have to modify your buffers but just ensure that the
|
||||
* end of buffer + padding is not outside of a memory region.
|
||||
*
|
||||
* \section using Using the Library
|
||||
*
|
||||
* The library is released in source form. It is strongly advised to compile the library using -Ofast to
|
||||
* have the best performances.
|
||||
*
|
||||
* The library functions are declared in the public file <code>arm_math.h</code> which is placed in the <code>Include</code> folder.
|
||||
* Simply include this file. If you don't want to include everything, you can also rely
|
||||
* on headers in Include/dsp folder and use only what you need.
|
||||
*
|
||||
* \section example Examples
|
||||
*
|
||||
* The library ships with a number of examples which demonstrate how to use the library functions.
|
||||
*
|
||||
* \section toolchain Toolchain Support
|
||||
*
|
||||
* The library is now tested on Fast Models building with cmake.
|
||||
* Core M0, M4, M7, M33, M55, A32 are tested.
|
||||
*
|
||||
*
|
||||
* \section preprocessor Preprocessor Macros
|
||||
*
|
||||
* Each library project have different preprocessor macros.
|
||||
*
|
||||
* - ARM_MATH_BIG_ENDIAN:
|
||||
*
|
||||
* Define macro ARM_MATH_BIG_ENDIAN to build the library for big endian targets. By default library builds for little endian targets.
|
||||
*
|
||||
* - ARM_MATH_MATRIX_CHECK:
|
||||
*
|
||||
* Define macro ARM_MATH_MATRIX_CHECK for checking on the input and output sizes of matrices
|
||||
*
|
||||
* - ARM_MATH_ROUNDING:
|
||||
*
|
||||
* Define macro ARM_MATH_ROUNDING for rounding on support functions
|
||||
*
|
||||
* - ARM_MATH_LOOPUNROLL:
|
||||
*
|
||||
* Define macro ARM_MATH_LOOPUNROLL to enable manual loop unrolling in DSP functions
|
||||
*
|
||||
* - ARM_MATH_NEON:
|
||||
*
|
||||
* Define macro ARM_MATH_NEON to enable Neon versions of the DSP functions.
|
||||
* It is not enabled by default when Neon is available because performances are
|
||||
* dependent on the compiler and target architecture.
|
||||
*
|
||||
* - ARM_MATH_NEON_EXPERIMENTAL:
|
||||
*
|
||||
* Define macro ARM_MATH_NEON_EXPERIMENTAL to enable experimental Neon versions of
|
||||
* of some DSP functions. Experimental Neon versions currently do not have better
|
||||
* performances than the scalar versions.
|
||||
*
|
||||
* - ARM_MATH_HELIUM:
|
||||
*
|
||||
* It implies the flags ARM_MATH_MVEF and ARM_MATH_MVEI and ARM_MATH_MVE_FLOAT16.
|
||||
*
|
||||
* - ARM_MATH_HELIUM_EXPERIMENTAL:
|
||||
*
|
||||
* Only taken into account when ARM_MATH_MVEF, ARM_MATH_MVEI or ARM_MATH_MVE_FLOAT16 are defined.
|
||||
* Enable some vector versions which may have worse performance than scalar
|
||||
* depending on the core / compiler configuration.
|
||||
*
|
||||
* - ARM_MATH_MVEF:
|
||||
*
|
||||
* Select Helium versions of the f32 algorithms.
|
||||
* It implies ARM_MATH_FLOAT16 and ARM_MATH_MVEI.
|
||||
*
|
||||
* - ARM_MATH_MVEI:
|
||||
*
|
||||
* Select Helium versions of the int and fixed point algorithms.
|
||||
*
|
||||
* - ARM_MATH_MVE_FLOAT16:
|
||||
*
|
||||
* MVE Float16 implementations of some algorithms (Requires MVE extension).
|
||||
*
|
||||
* - DISABLEFLOAT16:
|
||||
*
|
||||
* Disable float16 algorithms when __fp16 is not supported for a
|
||||
* specific compiler / core configuration.
|
||||
* This is only valid for scalar. When vector architecture is
|
||||
* supporting f16 then it can't be disabled.
|
||||
*
|
||||
* - ARM_MATH_AUTOVECTORIZE:
|
||||
*
|
||||
* With Helium or Neon, disable the use of vectorized code with C intrinsics
|
||||
* and use pure C instead. The vectorization is then done by the compiler.
|
||||
*
|
||||
* <hr>
|
||||
* \section pack CMSIS-DSP in ARM::CMSIS Pack
|
||||
*
|
||||
* The following files relevant to CMSIS-DSP are present in the <b>ARM::CMSIS</b> Pack directories:
|
||||
* |File/Folder |Content |
|
||||
* |---------------------------------|------------------------------------------------------------------------|
|
||||
* |\b CMSIS\\Documentation\\DSP | This documentation |
|
||||
* |\b CMSIS\\DSP\\Examples | Example projects demonstrating the usage of the library functions |
|
||||
* |\b CMSIS\\DSP\\Include | DSP_Lib include files for using and building the lib
|
||||
* |\b CMSIS\\DSP\\PrivateInclude | DSP_Lib private include files for building the lib |
|
||||
* |\b CMSIS\\DSP\\Lib | DSP_Lib binaries |
|
||||
* |\b CMSIS\\DSP\\Source | DSP_Lib source files |
|
||||
*
|
||||
* <hr>
|
||||
* \section rev Revision History of CMSIS-DSP
|
||||
* Please refer to \ref ChangeLog_pg.
|
||||
*/
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
/**
|
||||
* @defgroup groupExamples Examples
|
||||
*/
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
#ifndef _ARM_MATH_H
|
||||
#define _ARM_MATH_H
|
||||
|
||||
|
||||
#include "arm_math_types.h"
|
||||
#include "arm_math_memory.h"
|
||||
|
||||
#include "dsp/none.h"
|
||||
#include "dsp/utils.h"
|
||||
|
||||
#include "dsp/basic_math_functions.h"
|
||||
#include "dsp/interpolation_functions.h"
|
||||
#include "dsp/bayes_functions.h"
|
||||
#include "dsp/matrix_functions.h"
|
||||
#include "dsp/complex_math_functions.h"
|
||||
#include "dsp/statistics_functions.h"
|
||||
#include "dsp/controller_functions.h"
|
||||
#include "dsp/support_functions.h"
|
||||
#include "dsp/distance_functions.h"
|
||||
#include "dsp/svm_functions.h"
|
||||
#include "dsp/fast_math_functions.h"
|
||||
#include "dsp/transform_functions.h"
|
||||
#include "dsp/filtering_functions.h"
|
||||
#include "dsp/quaternion_math_functions.h"
|
||||
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
|
||||
|
||||
|
||||
//#define TABLE_SPACING_Q31 0x400000
|
||||
//#define TABLE_SPACING_Q15 0x80
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
#endif /* _ARM_MATH_H */
|
||||
|
||||
/**
|
||||
*
|
||||
* End of file.
|
||||
*/
|
||||
|
|
@ -0,0 +1,59 @@
|
|||
/******************************************************************************
|
||||
* @file arm_math_f16.h
|
||||
* @brief Public header file for f16 function of the CMSIS DSP Library
|
||||
* @version V1.10.0
|
||||
* @date 08 July 2021
|
||||
* Target Processor: Cortex-M and Cortex-A cores
|
||||
******************************************************************************/
|
||||
/*
|
||||
* Copyright (c) 2010-2021 Arm Limited or its affiliates. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
#ifndef _ARM_MATH_F16_H
|
||||
#define _ARM_MATH_F16_H
|
||||
|
||||
#include "arm_math.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
#include "arm_math_types_f16.h"
|
||||
#include "dsp/none.h"
|
||||
#include "dsp/utils.h"
|
||||
#include "dsp/basic_math_functions_f16.h"
|
||||
#include "dsp/interpolation_functions_f16.h"
|
||||
#include "dsp/bayes_functions_f16.h"
|
||||
#include "dsp/matrix_functions_f16.h"
|
||||
#include "dsp/complex_math_functions_f16.h"
|
||||
#include "dsp/statistics_functions_f16.h"
|
||||
#include "dsp/controller_functions_f16.h"
|
||||
#include "dsp/support_functions_f16.h"
|
||||
#include "dsp/distance_functions_f16.h"
|
||||
#include "dsp/svm_functions_f16.h"
|
||||
#include "dsp/fast_math_functions_f16.h"
|
||||
#include "dsp/transform_functions_f16.h"
|
||||
#include "dsp/filtering_functions_f16.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* _ARM_MATH_F16_H */
|
||||
|
||||
|
||||
|
|
@ -0,0 +1,206 @@
|
|||
/******************************************************************************
|
||||
* @file arm_math_memory.h
|
||||
* @brief Public header file for CMSIS DSP Library
|
||||
* @version V1.10.0
|
||||
* @date 08 July 2021
|
||||
* Target Processor: Cortex-M and Cortex-A cores
|
||||
******************************************************************************/
|
||||
/*
|
||||
* Copyright (c) 2010-2021 Arm Limited or its affiliates. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
#ifndef _ARM_MATH_MEMORY_H_
|
||||
|
||||
#define _ARM_MATH_MEMORY_H_
|
||||
|
||||
#include "arm_math_types.h"
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
/**
|
||||
@brief definition to read/write two 16 bit values.
|
||||
@deprecated
|
||||
*/
|
||||
#if defined ( __CC_ARM )
|
||||
#define __SIMD32_TYPE int32_t __packed
|
||||
#elif defined ( __ARMCC_VERSION ) && ( __ARMCC_VERSION >= 6010050 )
|
||||
#define __SIMD32_TYPE int32_t
|
||||
#elif defined ( __GNUC__ )
|
||||
#define __SIMD32_TYPE int32_t
|
||||
#elif defined ( __ICCARM__ )
|
||||
#define __SIMD32_TYPE int32_t __packed
|
||||
#elif defined ( __TI_ARM__ )
|
||||
#define __SIMD32_TYPE int32_t
|
||||
#elif defined ( __CSMC__ )
|
||||
#define __SIMD32_TYPE int32_t
|
||||
#elif defined ( __TASKING__ )
|
||||
#define __SIMD32_TYPE __un(aligned) int32_t
|
||||
#elif defined(_MSC_VER )
|
||||
#define __SIMD32_TYPE int32_t
|
||||
#else
|
||||
#error Unknown compiler
|
||||
#endif
|
||||
|
||||
#define __SIMD32(addr) (*(__SIMD32_TYPE **) & (addr))
|
||||
#define __SIMD32_CONST(addr) ( (__SIMD32_TYPE * ) (addr))
|
||||
#define _SIMD32_OFFSET(addr) (*(__SIMD32_TYPE * ) (addr))
|
||||
#define __SIMD64(addr) (*( int64_t **) & (addr))
|
||||
|
||||
|
||||
/* SIMD replacement */
|
||||
|
||||
|
||||
/**
|
||||
@brief Read 2 Q15 from Q15 pointer.
|
||||
@param[in] pQ15 points to input value
|
||||
@return Q31 value
|
||||
*/
|
||||
__STATIC_FORCEINLINE q31_t read_q15x2 (
|
||||
q15_t const * pQ15)
|
||||
{
|
||||
q31_t val;
|
||||
|
||||
#ifdef __ARM_FEATURE_UNALIGNED
|
||||
memcpy (&val, pQ15, 4);
|
||||
#else
|
||||
val = (pQ15[1] << 16) | (pQ15[0] & 0x0FFFF) ;
|
||||
#endif
|
||||
|
||||
return (val);
|
||||
}
|
||||
|
||||
/**
|
||||
@brief Read 2 Q15 from Q15 pointer and increment pointer afterwards.
|
||||
@param[in] pQ15 points to input value
|
||||
@return Q31 value
|
||||
*/
|
||||
#define read_q15x2_ia(pQ15) read_q15x2((*(pQ15) += 2) - 2)
|
||||
|
||||
/**
|
||||
@brief Read 2 Q15 from Q15 pointer and decrement pointer afterwards.
|
||||
@param[in] pQ15 points to input value
|
||||
@return Q31 value
|
||||
*/
|
||||
#define read_q15x2_da(pQ15) read_q15x2((*(pQ15) -= 2) + 2)
|
||||
|
||||
/**
|
||||
@brief Write 2 Q15 to Q15 pointer and increment pointer afterwards.
|
||||
@param[in] pQ15 points to input value
|
||||
@param[in] value Q31 value
|
||||
@return none
|
||||
*/
|
||||
__STATIC_FORCEINLINE void write_q15x2_ia (
|
||||
q15_t ** pQ15,
|
||||
q31_t value)
|
||||
{
|
||||
q31_t val = value;
|
||||
#ifdef __ARM_FEATURE_UNALIGNED
|
||||
memcpy (*pQ15, &val, 4);
|
||||
#else
|
||||
(*pQ15)[0] = (q15_t)(val & 0x0FFFF);
|
||||
(*pQ15)[1] = (q15_t)((val >> 16) & 0x0FFFF);
|
||||
#endif
|
||||
|
||||
*pQ15 += 2;
|
||||
}
|
||||
|
||||
/**
|
||||
@brief Write 2 Q15 to Q15 pointer.
|
||||
@param[in] pQ15 points to input value
|
||||
@param[in] value Q31 value
|
||||
@return none
|
||||
*/
|
||||
__STATIC_FORCEINLINE void write_q15x2 (
|
||||
q15_t * pQ15,
|
||||
q31_t value)
|
||||
{
|
||||
q31_t val = value;
|
||||
|
||||
#ifdef __ARM_FEATURE_UNALIGNED
|
||||
memcpy (pQ15, &val, 4);
|
||||
#else
|
||||
pQ15[0] = (q15_t)(val & 0x0FFFF);
|
||||
pQ15[1] = (q15_t)(val >> 16);
|
||||
#endif
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
@brief Read 4 Q7 from Q7 pointer
|
||||
@param[in] pQ7 points to input value
|
||||
@return Q31 value
|
||||
*/
|
||||
__STATIC_FORCEINLINE q31_t read_q7x4 (
|
||||
q7_t const * pQ7)
|
||||
{
|
||||
q31_t val;
|
||||
|
||||
#ifdef __ARM_FEATURE_UNALIGNED
|
||||
memcpy (&val, pQ7, 4);
|
||||
#else
|
||||
val =((pQ7[3] & 0x0FF) << 24) | ((pQ7[2] & 0x0FF) << 16) | ((pQ7[1] & 0x0FF) << 8) | (pQ7[0] & 0x0FF);
|
||||
#endif
|
||||
return (val);
|
||||
}
|
||||
|
||||
/**
|
||||
@brief Read 4 Q7 from Q7 pointer and increment pointer afterwards.
|
||||
@param[in] pQ7 points to input value
|
||||
@return Q31 value
|
||||
*/
|
||||
#define read_q7x4_ia(pQ7) read_q7x4((*(pQ7) += 4) - 4)
|
||||
|
||||
/**
|
||||
@brief Read 4 Q7 from Q7 pointer and decrement pointer afterwards.
|
||||
@param[in] pQ7 points to input value
|
||||
@return Q31 value
|
||||
*/
|
||||
#define read_q7x4_da(pQ7) read_q7x4((*(pQ7) -= 4) + 4)
|
||||
|
||||
/**
|
||||
@brief Write 4 Q7 to Q7 pointer and increment pointer afterwards.
|
||||
@param[in] pQ7 points to input value
|
||||
@param[in] value Q31 value
|
||||
@return none
|
||||
*/
|
||||
__STATIC_FORCEINLINE void write_q7x4_ia (
|
||||
q7_t ** pQ7,
|
||||
q31_t value)
|
||||
{
|
||||
q31_t val = value;
|
||||
#ifdef __ARM_FEATURE_UNALIGNED
|
||||
memcpy (*pQ7, &val, 4);
|
||||
#else
|
||||
(*pQ7)[0] = (q7_t)(val & 0x0FF);
|
||||
(*pQ7)[1] = (q7_t)((val >> 8) & 0x0FF);
|
||||
(*pQ7)[2] = (q7_t)((val >> 16) & 0x0FF);
|
||||
(*pQ7)[3] = (q7_t)((val >> 24) & 0x0FF);
|
||||
|
||||
#endif
|
||||
*pQ7 += 4;
|
||||
}
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /*ifndef _ARM_MATH_MEMORY_H_ */
|
||||
|
|
@ -0,0 +1,616 @@
|
|||
/******************************************************************************
|
||||
* @file arm_math_types.h
|
||||
* @brief Public header file for CMSIS DSP Library
|
||||
* @version V1.10.0
|
||||
* @date 08 July 2021
|
||||
* Target Processor: Cortex-M and Cortex-A cores
|
||||
******************************************************************************/
|
||||
/*
|
||||
* Copyright (c) 2010-2021 Arm Limited or its affiliates. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
#ifndef _ARM_MATH_TYPES_H_
|
||||
|
||||
#define _ARM_MATH_TYPES_H_
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
/* Compiler specific diagnostic adjustment */
|
||||
#if defined ( __CC_ARM )
|
||||
|
||||
#elif defined ( __ARMCC_VERSION ) && ( __ARMCC_VERSION >= 6010050 )
|
||||
|
||||
#elif defined ( __APPLE_CC__ )
|
||||
#pragma GCC diagnostic ignored "-Wold-style-cast"
|
||||
|
||||
#elif defined ( __GNUC__ )
|
||||
#pragma GCC diagnostic push
|
||||
#pragma GCC diagnostic ignored "-Wsign-conversion"
|
||||
#pragma GCC diagnostic ignored "-Wconversion"
|
||||
#pragma GCC diagnostic ignored "-Wunused-parameter"
|
||||
|
||||
#elif defined ( __ICCARM__ )
|
||||
|
||||
#elif defined ( __TI_ARM__ )
|
||||
|
||||
#elif defined ( __CSMC__ )
|
||||
|
||||
#elif defined ( __TASKING__ )
|
||||
|
||||
#elif defined ( _MSC_VER )
|
||||
|
||||
#else
|
||||
#error Unknown compiler
|
||||
#endif
|
||||
|
||||
|
||||
/* Included for instrinsics definitions */
|
||||
#if defined (_MSC_VER )
|
||||
#include <stdint.h>
|
||||
#define __STATIC_FORCEINLINE static __forceinline
|
||||
#define __STATIC_INLINE static __inline
|
||||
#define __ALIGNED(x) __declspec(align(x))
|
||||
#elif defined ( __APPLE_CC__ )
|
||||
#include <stdint.h>
|
||||
#define __ALIGNED(x) __attribute__((aligned(x)))
|
||||
#define __STATIC_FORCEINLINE static inline __attribute__((always_inline))
|
||||
#define __STATIC_INLINE static inline
|
||||
#elif defined (__GNUC_PYTHON__)
|
||||
#include <stdint.h>
|
||||
#define __ALIGNED(x) __attribute__((aligned(x)))
|
||||
#define __STATIC_FORCEINLINE static inline __attribute__((always_inline))
|
||||
#define __STATIC_INLINE static inline
|
||||
|
||||
#else
|
||||
#include "cmsis_compiler.h"
|
||||
#endif
|
||||
|
||||
|
||||
|
||||
#include <string.h>
|
||||
#include <math.h>
|
||||
#include <float.h>
|
||||
#include <limits.h>
|
||||
|
||||
/* evaluate ARM DSP feature */
|
||||
#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1))
|
||||
#define ARM_MATH_DSP 1
|
||||
#endif
|
||||
|
||||
#if defined(ARM_MATH_NEON)
|
||||
#if defined(_MSC_VER) && defined(_M_ARM64EC)
|
||||
#include <arm64_neon.h>
|
||||
#else
|
||||
#include <arm_neon.h>
|
||||
#endif
|
||||
#if defined(__ARM_FEATURE_FP16_VECTOR_ARITHMETIC) && __ARM_FEATURE_FP16_VECTOR_ARITHMETIC
|
||||
#if !defined(ARM_MATH_NEON_FLOAT16)
|
||||
#define ARM_MATH_NEON_FLOAT16
|
||||
#endif
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#if !defined(ARM_MATH_AUTOVECTORIZE)
|
||||
|
||||
|
||||
#if defined(__ARM_FEATURE_MVE)
|
||||
#if __ARM_FEATURE_MVE
|
||||
#if !defined(ARM_MATH_MVEI)
|
||||
#define ARM_MATH_MVEI
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#if (__ARM_FEATURE_MVE & 2)
|
||||
#if !defined(ARM_MATH_MVEF)
|
||||
#define ARM_MATH_MVEF
|
||||
#endif
|
||||
#if !defined(ARM_MATH_MVE_FLOAT16)
|
||||
#define ARM_MATH_MVE_FLOAT16
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#endif /*defined(__ARM_FEATURE_MVE)*/
|
||||
#endif /*!defined(ARM_MATH_AUTOVECTORIZE)*/
|
||||
|
||||
|
||||
#if defined (ARM_MATH_HELIUM)
|
||||
#if !defined(ARM_MATH_MVEF)
|
||||
#define ARM_MATH_MVEF
|
||||
#endif
|
||||
|
||||
#if !defined(ARM_MATH_MVEI)
|
||||
#define ARM_MATH_MVEI
|
||||
#endif
|
||||
|
||||
#if !defined(ARM_MATH_MVE_FLOAT16)
|
||||
#define ARM_MATH_MVE_FLOAT16
|
||||
#endif
|
||||
#endif
|
||||
|
||||
|
||||
|
||||
#if defined ( __CC_ARM )
|
||||
/* Enter low optimization region - place directly above function definition */
|
||||
#if defined( __ARM_ARCH_7EM__ )
|
||||
#define LOW_OPTIMIZATION_ENTER \
|
||||
_Pragma ("push") \
|
||||
_Pragma ("O1")
|
||||
#else
|
||||
#define LOW_OPTIMIZATION_ENTER
|
||||
#endif
|
||||
|
||||
/* Exit low optimization region - place directly after end of function definition */
|
||||
#if defined ( __ARM_ARCH_7EM__ )
|
||||
#define LOW_OPTIMIZATION_EXIT \
|
||||
_Pragma ("pop")
|
||||
#else
|
||||
#define LOW_OPTIMIZATION_EXIT
|
||||
#endif
|
||||
|
||||
/* Enter low optimization region - place directly above function definition */
|
||||
#define IAR_ONLY_LOW_OPTIMIZATION_ENTER
|
||||
|
||||
/* Exit low optimization region - place directly after end of function definition */
|
||||
#define IAR_ONLY_LOW_OPTIMIZATION_EXIT
|
||||
|
||||
#elif defined (__ARMCC_VERSION ) && ( __ARMCC_VERSION >= 6010050 )
|
||||
#define LOW_OPTIMIZATION_ENTER
|
||||
#define LOW_OPTIMIZATION_EXIT
|
||||
#define IAR_ONLY_LOW_OPTIMIZATION_ENTER
|
||||
#define IAR_ONLY_LOW_OPTIMIZATION_EXIT
|
||||
|
||||
#elif defined ( __APPLE_CC__ )
|
||||
#define LOW_OPTIMIZATION_ENTER
|
||||
#define LOW_OPTIMIZATION_EXIT
|
||||
#define IAR_ONLY_LOW_OPTIMIZATION_ENTER
|
||||
#define IAR_ONLY_LOW_OPTIMIZATION_EXIT
|
||||
|
||||
#elif defined ( __GNUC__ )
|
||||
#define LOW_OPTIMIZATION_ENTER \
|
||||
__attribute__(( optimize("-O1") ))
|
||||
#define LOW_OPTIMIZATION_EXIT
|
||||
#define IAR_ONLY_LOW_OPTIMIZATION_ENTER
|
||||
#define IAR_ONLY_LOW_OPTIMIZATION_EXIT
|
||||
|
||||
#elif defined ( __ICCARM__ )
|
||||
/* Enter low optimization region - place directly above function definition */
|
||||
#if defined ( __ARM_ARCH_7EM__ )
|
||||
#define LOW_OPTIMIZATION_ENTER \
|
||||
_Pragma ("optimize=low")
|
||||
#else
|
||||
#define LOW_OPTIMIZATION_ENTER
|
||||
#endif
|
||||
|
||||
/* Exit low optimization region - place directly after end of function definition */
|
||||
#define LOW_OPTIMIZATION_EXIT
|
||||
|
||||
/* Enter low optimization region - place directly above function definition */
|
||||
#if defined ( __ARM_ARCH_7EM__ )
|
||||
#define IAR_ONLY_LOW_OPTIMIZATION_ENTER \
|
||||
_Pragma ("optimize=low")
|
||||
#else
|
||||
#define IAR_ONLY_LOW_OPTIMIZATION_ENTER
|
||||
#endif
|
||||
|
||||
/* Exit low optimization region - place directly after end of function definition */
|
||||
#define IAR_ONLY_LOW_OPTIMIZATION_EXIT
|
||||
|
||||
#elif defined ( __TI_ARM__ )
|
||||
#define LOW_OPTIMIZATION_ENTER
|
||||
#define LOW_OPTIMIZATION_EXIT
|
||||
#define IAR_ONLY_LOW_OPTIMIZATION_ENTER
|
||||
#define IAR_ONLY_LOW_OPTIMIZATION_EXIT
|
||||
|
||||
#elif defined ( __CSMC__ )
|
||||
#define LOW_OPTIMIZATION_ENTER
|
||||
#define LOW_OPTIMIZATION_EXIT
|
||||
#define IAR_ONLY_LOW_OPTIMIZATION_ENTER
|
||||
#define IAR_ONLY_LOW_OPTIMIZATION_EXIT
|
||||
|
||||
#elif defined ( __TASKING__ )
|
||||
#define LOW_OPTIMIZATION_ENTER
|
||||
#define LOW_OPTIMIZATION_EXIT
|
||||
#define IAR_ONLY_LOW_OPTIMIZATION_ENTER
|
||||
#define IAR_ONLY_LOW_OPTIMIZATION_EXIT
|
||||
|
||||
#elif defined ( _MSC_VER ) || defined(__GNUC_PYTHON__)
|
||||
#define LOW_OPTIMIZATION_ENTER
|
||||
#define LOW_OPTIMIZATION_EXIT
|
||||
#define IAR_ONLY_LOW_OPTIMIZATION_ENTER
|
||||
#define IAR_ONLY_LOW_OPTIMIZATION_EXIT
|
||||
#endif
|
||||
|
||||
|
||||
|
||||
/* Compiler specific diagnostic adjustment */
|
||||
#if defined ( __CC_ARM )
|
||||
|
||||
#elif defined ( __ARMCC_VERSION ) && ( __ARMCC_VERSION >= 6010050 )
|
||||
|
||||
#elif defined ( __APPLE_CC__ )
|
||||
|
||||
#elif defined ( __GNUC__ )
|
||||
#pragma GCC diagnostic pop
|
||||
|
||||
#elif defined ( __ICCARM__ )
|
||||
|
||||
#elif defined ( __TI_ARM__ )
|
||||
|
||||
#elif defined ( __CSMC__ )
|
||||
|
||||
#elif defined ( __TASKING__ )
|
||||
|
||||
#elif defined ( _MSC_VER )
|
||||
|
||||
#else
|
||||
#error Unknown compiler
|
||||
#endif
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#if defined(__ARM_FEATURE_MVE) && __ARM_FEATURE_MVE
|
||||
#include <arm_mve.h>
|
||||
#endif
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief 8-bit fractional data type in 1.7 format.
|
||||
*/
|
||||
typedef int8_t q7_t;
|
||||
|
||||
/**
|
||||
* @brief 16-bit fractional data type in 1.15 format.
|
||||
*/
|
||||
typedef int16_t q15_t;
|
||||
|
||||
/**
|
||||
* @brief 32-bit fractional data type in 1.31 format.
|
||||
*/
|
||||
typedef int32_t q31_t;
|
||||
|
||||
/**
|
||||
* @brief 64-bit fractional data type in 1.63 format.
|
||||
*/
|
||||
typedef int64_t q63_t;
|
||||
|
||||
/**
|
||||
* @brief 32-bit floating-point type definition.
|
||||
*/
|
||||
#if !defined(__ICCARM__) || !(__ARM_FEATURE_MVE & 2)
|
||||
typedef float float32_t;
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief 64-bit floating-point type definition.
|
||||
*/
|
||||
typedef double float64_t;
|
||||
|
||||
/**
|
||||
* @brief vector types
|
||||
*/
|
||||
#if defined(ARM_MATH_NEON) || (defined (ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE))
|
||||
/**
|
||||
* @brief 64-bit fractional 128-bit vector data type in 1.63 format
|
||||
*/
|
||||
typedef int64x2_t q63x2_t;
|
||||
|
||||
/**
|
||||
* @brief 32-bit fractional 128-bit vector data type in 1.31 format.
|
||||
*/
|
||||
typedef int32x4_t q31x4_t;
|
||||
|
||||
/**
|
||||
* @brief 16-bit fractional 128-bit vector data type with 16-bit alignment in 1.15 format.
|
||||
*/
|
||||
typedef __ALIGNED(2) int16x8_t q15x8_t;
|
||||
|
||||
/**
|
||||
* @brief 8-bit fractional 128-bit vector data type with 8-bit alignment in 1.7 format.
|
||||
*/
|
||||
typedef __ALIGNED(1) int8x16_t q7x16_t;
|
||||
|
||||
/**
|
||||
* @brief 32-bit fractional 128-bit vector pair data type in 1.31 format.
|
||||
*/
|
||||
typedef int32x4x2_t q31x4x2_t;
|
||||
|
||||
/**
|
||||
* @brief 32-bit fractional 128-bit vector quadruplet data type in 1.31 format.
|
||||
*/
|
||||
typedef int32x4x4_t q31x4x4_t;
|
||||
|
||||
/**
|
||||
* @brief 16-bit fractional 128-bit vector pair data type in 1.15 format.
|
||||
*/
|
||||
typedef int16x8x2_t q15x8x2_t;
|
||||
|
||||
/**
|
||||
* @brief 16-bit fractional 128-bit vector quadruplet data type in 1.15 format.
|
||||
*/
|
||||
typedef int16x8x4_t q15x8x4_t;
|
||||
|
||||
/**
|
||||
* @brief 8-bit fractional 128-bit vector pair data type in 1.7 format.
|
||||
*/
|
||||
typedef int8x16x2_t q7x16x2_t;
|
||||
|
||||
/**
|
||||
* @brief 8-bit fractional 128-bit vector quadruplet data type in 1.7 format.
|
||||
*/
|
||||
typedef int8x16x4_t q7x16x4_t;
|
||||
|
||||
/**
|
||||
* @brief 32-bit fractional data type in 9.23 format.
|
||||
*/
|
||||
typedef int32_t q23_t;
|
||||
|
||||
/**
|
||||
* @brief 32-bit fractional 128-bit vector data type in 9.23 format.
|
||||
*/
|
||||
typedef int32x4_t q23x4_t;
|
||||
|
||||
/**
|
||||
* @brief 64-bit status 128-bit vector data type.
|
||||
*/
|
||||
typedef int64x2_t status64x2_t;
|
||||
|
||||
/**
|
||||
* @brief 32-bit status 128-bit vector data type.
|
||||
*/
|
||||
typedef int32x4_t status32x4_t;
|
||||
|
||||
/**
|
||||
* @brief 16-bit status 128-bit vector data type.
|
||||
*/
|
||||
typedef int16x8_t status16x8_t;
|
||||
|
||||
/**
|
||||
* @brief 8-bit status 128-bit vector data type.
|
||||
*/
|
||||
typedef int8x16_t status8x16_t;
|
||||
|
||||
|
||||
#endif
|
||||
|
||||
#if defined(ARM_MATH_NEON) || (defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE)) /* floating point vector*/
|
||||
/**
|
||||
* @brief 32-bit floating-point 128-bit vector type
|
||||
*/
|
||||
typedef float32x4_t f32x4_t;
|
||||
|
||||
/**
|
||||
* @brief 32-bit floating-point 128-bit vector pair data type
|
||||
*/
|
||||
typedef float32x4x2_t f32x4x2_t;
|
||||
|
||||
/**
|
||||
* @brief 32-bit floating-point 128-bit vector quadruplet data type
|
||||
*/
|
||||
typedef float32x4x4_t f32x4x4_t;
|
||||
|
||||
/**
|
||||
* @brief 32-bit ubiquitous 128-bit vector data type
|
||||
*/
|
||||
typedef union _any32x4_t
|
||||
{
|
||||
float32x4_t f;
|
||||
int32x4_t i;
|
||||
} any32x4_t;
|
||||
|
||||
#endif
|
||||
|
||||
#if defined(ARM_MATH_NEON)
|
||||
/**
|
||||
* @brief 32-bit fractional 64-bit vector data type in 1.31 format.
|
||||
*/
|
||||
typedef int32x2_t q31x2_t;
|
||||
|
||||
/**
|
||||
* @brief 16-bit fractional 64-bit vector data type in 1.15 format.
|
||||
*/
|
||||
typedef __ALIGNED(2) int16x4_t q15x4_t;
|
||||
|
||||
/**
|
||||
* @brief 8-bit fractional 64-bit vector data type in 1.7 format.
|
||||
*/
|
||||
typedef __ALIGNED(1) int8x8_t q7x8_t;
|
||||
|
||||
/**
|
||||
* @brief 32-bit float 64-bit vector data type.
|
||||
*/
|
||||
typedef float32x2_t f32x2_t;
|
||||
|
||||
/**
|
||||
* @brief 32-bit floating-point 128-bit vector triplet data type
|
||||
*/
|
||||
typedef float32x4x3_t f32x4x3_t;
|
||||
|
||||
|
||||
/**
|
||||
* @brief 32-bit fractional 128-bit vector triplet data type in 1.31 format
|
||||
*/
|
||||
typedef int32x4x3_t q31x4x3_t;
|
||||
|
||||
/**
|
||||
* @brief 16-bit fractional 128-bit vector triplet data type in 1.15 format
|
||||
*/
|
||||
typedef int16x8x3_t q15x8x3_t;
|
||||
|
||||
/**
|
||||
* @brief 8-bit fractional 128-bit vector triplet data type in 1.7 format
|
||||
*/
|
||||
typedef int8x16x3_t q7x16x3_t;
|
||||
|
||||
/**
|
||||
* @brief 32-bit floating-point 64-bit vector pair data type
|
||||
*/
|
||||
typedef float32x2x2_t f32x2x2_t;
|
||||
|
||||
/**
|
||||
* @brief 32-bit floating-point 64-bit vector triplet data type
|
||||
*/
|
||||
typedef float32x2x3_t f32x2x3_t;
|
||||
|
||||
/**
|
||||
* @brief 32-bit floating-point 64-bit vector quadruplet data type
|
||||
*/
|
||||
typedef float32x2x4_t f32x2x4_t;
|
||||
|
||||
|
||||
/**
|
||||
* @brief 32-bit fractional 64-bit vector pair data type in 1.31 format
|
||||
*/
|
||||
typedef int32x2x2_t q31x2x2_t;
|
||||
|
||||
/**
|
||||
* @brief 32-bit fractional 64-bit vector triplet data type in 1.31 format
|
||||
*/
|
||||
typedef int32x2x3_t q31x2x3_t;
|
||||
|
||||
/**
|
||||
* @brief 32-bit fractional 64-bit vector quadruplet data type in 1.31 format
|
||||
*/
|
||||
typedef int32x4x3_t q31x2x4_t;
|
||||
|
||||
/**
|
||||
* @brief 16-bit fractional 64-bit vector pair data type in 1.15 format
|
||||
*/
|
||||
typedef int16x4x2_t q15x4x2_t;
|
||||
|
||||
/**
|
||||
* @brief 16-bit fractional 64-bit vector triplet data type in 1.15 format
|
||||
*/
|
||||
typedef int16x4x2_t q15x4x3_t;
|
||||
|
||||
/**
|
||||
* @brief 16-bit fractional 64-bit vector quadruplet data type in 1.15 format
|
||||
*/
|
||||
typedef int16x4x3_t q15x4x4_t;
|
||||
|
||||
/**
|
||||
* @brief 8-bit fractional 64-bit vector pair data type in 1.7 format
|
||||
*/
|
||||
typedef int8x8x2_t q7x8x2_t;
|
||||
|
||||
/**
|
||||
* @brief 8-bit fractional 64-bit vector triplet data type in 1.7 format
|
||||
*/
|
||||
typedef int8x8x3_t q7x8x3_t;
|
||||
|
||||
/**
|
||||
* @brief 8-bit fractional 64-bit vector quadruplet data type in 1.7 format
|
||||
*/
|
||||
typedef int8x8x4_t q7x8x4_t;
|
||||
|
||||
/**
|
||||
* @brief 32-bit ubiquitous 64-bit vector data type
|
||||
*/
|
||||
typedef union _any32x2_t
|
||||
{
|
||||
float32x2_t f;
|
||||
int32x2_t i;
|
||||
} any32x2_t;
|
||||
|
||||
|
||||
/**
|
||||
* @brief 32-bit status 64-bit vector data type.
|
||||
*/
|
||||
typedef int32x4_t status32x2_t;
|
||||
|
||||
/**
|
||||
* @brief 16-bit status 64-bit vector data type.
|
||||
*/
|
||||
typedef int16x8_t status16x4_t;
|
||||
|
||||
/**
|
||||
* @brief 8-bit status 64-bit vector data type.
|
||||
*/
|
||||
typedef int8x16_t status8x8_t;
|
||||
|
||||
#endif
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
#define F64_MAX ((float64_t)DBL_MAX)
|
||||
#define F32_MAX ((float32_t)FLT_MAX)
|
||||
|
||||
|
||||
|
||||
#define F64_MIN (-DBL_MAX)
|
||||
#define F32_MIN (-FLT_MAX)
|
||||
|
||||
|
||||
|
||||
#define F64_ABSMAX ((float64_t)DBL_MAX)
|
||||
#define F32_ABSMAX ((float32_t)FLT_MAX)
|
||||
|
||||
|
||||
|
||||
#define F64_ABSMIN ((float64_t)0.0)
|
||||
#define F32_ABSMIN ((float32_t)0.0)
|
||||
|
||||
|
||||
#define Q31_MAX ((q31_t)(0x7FFFFFFFL))
|
||||
#define Q15_MAX ((q15_t)(0x7FFF))
|
||||
#define Q7_MAX ((q7_t)(0x7F))
|
||||
#define Q31_MIN ((q31_t)(0x80000000L))
|
||||
#define Q15_MIN ((q15_t)(0x8000))
|
||||
#define Q7_MIN ((q7_t)(0x80))
|
||||
|
||||
#define Q31_ABSMAX ((q31_t)(0x7FFFFFFFL))
|
||||
#define Q15_ABSMAX ((q15_t)(0x7FFF))
|
||||
#define Q7_ABSMAX ((q7_t)(0x7F))
|
||||
#define Q31_ABSMIN ((q31_t)0)
|
||||
#define Q15_ABSMIN ((q15_t)0)
|
||||
#define Q7_ABSMIN ((q7_t)0)
|
||||
|
||||
/* Dimension C vector space */
|
||||
#define CMPLX_DIM 2
|
||||
|
||||
/**
|
||||
* @brief Error status returned by some functions in the library.
|
||||
*/
|
||||
|
||||
typedef enum
|
||||
{
|
||||
ARM_MATH_SUCCESS = 0, /**< No error */
|
||||
ARM_MATH_ARGUMENT_ERROR = -1, /**< One or more arguments are incorrect */
|
||||
ARM_MATH_LENGTH_ERROR = -2, /**< Length of data buffer is incorrect */
|
||||
ARM_MATH_SIZE_MISMATCH = -3, /**< Size of matrices is not compatible with the operation */
|
||||
ARM_MATH_NANINF = -4, /**< Not-a-number (NaN) or infinity is generated */
|
||||
ARM_MATH_SINGULAR = -5, /**< Input matrix is singular and cannot be inverted */
|
||||
ARM_MATH_TEST_FAILURE = -6, /**< Test Failed */
|
||||
ARM_MATH_DECOMPOSITION_FAILURE = -7 /**< Decomposition Failed */
|
||||
} arm_status;
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /*ifndef _ARM_MATH_TYPES_H_ */
|
||||
|
|
@ -0,0 +1,163 @@
|
|||
/******************************************************************************
|
||||
* @file arm_math_types_f16.h
|
||||
* @brief Public header file for f16 function of the CMSIS DSP Library
|
||||
* @version V1.10.0
|
||||
* @date 08 July 2021
|
||||
* Target Processor: Cortex-M and Cortex-A cores
|
||||
******************************************************************************/
|
||||
/*
|
||||
* Copyright (c) 2010-2021 Arm Limited or its affiliates. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
#ifndef _ARM_MATH_TYPES_F16_H
|
||||
#define _ARM_MATH_TYPES_F16_H
|
||||
|
||||
#include "arm_math_types.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
#if !defined( __CC_ARM )
|
||||
|
||||
/**
|
||||
* @brief 16-bit floating-point type definition.
|
||||
* This is already defined in arm_mve.h
|
||||
*
|
||||
* This is not fully supported on ARM AC5.
|
||||
*/
|
||||
|
||||
/*
|
||||
|
||||
Check if the type __fp16 is available.
|
||||
If it is not available, f16 version of the kernels
|
||||
won't be built.
|
||||
|
||||
*/
|
||||
#if !(__ARM_FEATURE_MVE & 2)
|
||||
#if !defined(DISABLEFLOAT16)
|
||||
#if defined(__ARM_FP16_FORMAT_IEEE) || defined(__ARM_FP16_FORMAT_ALTERNATIVE)
|
||||
typedef __fp16 float16_t;
|
||||
#define ARM_FLOAT16_SUPPORTED
|
||||
#endif
|
||||
#endif
|
||||
#else
|
||||
/* When Vector float16, this flag is always defined and can't be disabled */
|
||||
#define ARM_FLOAT16_SUPPORTED
|
||||
#endif
|
||||
|
||||
#if defined(ARM_MATH_NEON) || (defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE)) /* floating point vector*/
|
||||
|
||||
#if defined(ARM_MATH_MVE_FLOAT16) || defined(ARM_MATH_NEON_FLOAT16)
|
||||
|
||||
/**
|
||||
* @brief 16-bit floating-point 128-bit vector data type
|
||||
*/
|
||||
typedef __ALIGNED(2) float16x8_t f16x8_t;
|
||||
|
||||
/**
|
||||
* @brief 16-bit floating-point 128-bit vector pair data type
|
||||
*/
|
||||
typedef float16x8x2_t f16x8x2_t;
|
||||
|
||||
/**
|
||||
* @brief 16-bit floating-point 128-bit vector quadruplet data type
|
||||
*/
|
||||
typedef float16x8x4_t f16x8x4_t;
|
||||
|
||||
/**
|
||||
* @brief 16-bit ubiquitous 128-bit vector data type
|
||||
*/
|
||||
typedef union _any16x8_t
|
||||
{
|
||||
float16x8_t f;
|
||||
int16x8_t i;
|
||||
} any16x8_t;
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
||||
#if defined(ARM_MATH_NEON)
|
||||
|
||||
|
||||
#if defined(ARM_MATH_NEON_FLOAT16)
|
||||
/**
|
||||
* @brief 16-bit float 64-bit vector data type.
|
||||
*/
|
||||
typedef __ALIGNED(2) float16x4_t f16x4_t;
|
||||
|
||||
/**
|
||||
* @brief 16-bit floating-point 128-bit vector triplet data type
|
||||
*/
|
||||
typedef float16x8x3_t f16x8x3_t;
|
||||
|
||||
/**
|
||||
* @brief 16-bit floating-point 64-bit vector pair data type
|
||||
*/
|
||||
typedef float16x4x2_t f16x4x2_t;
|
||||
|
||||
/**
|
||||
* @brief 16-bit floating-point 64-bit vector triplet data type
|
||||
*/
|
||||
typedef float16x4x3_t f16x4x3_t;
|
||||
|
||||
/**
|
||||
* @brief 16-bit floating-point 64-bit vector quadruplet data type
|
||||
*/
|
||||
typedef float16x4x4_t f16x4x4_t;
|
||||
|
||||
/**
|
||||
* @brief 16-bit ubiquitous 64-bit vector data type
|
||||
*/
|
||||
typedef union _any16x4_t
|
||||
{
|
||||
float16x4_t f;
|
||||
int16x4_t i;
|
||||
} any16x4_t;
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
||||
|
||||
|
||||
#if defined(ARM_FLOAT16_SUPPORTED)
|
||||
|
||||
#if defined(__ICCARM__)
|
||||
|
||||
#define F16INFINITY ((float16_t) INFINITY)
|
||||
|
||||
#else
|
||||
|
||||
#define F16INFINITY ((float16_t)__builtin_inf())
|
||||
|
||||
#endif
|
||||
|
||||
#define F16_MAX ((float16_t)__FLT16_MAX__)
|
||||
#define F16_MIN (-(_Float16)__FLT16_MAX__)
|
||||
|
||||
#define F16_ABSMAX ((float16_t)__FLT16_MAX__)
|
||||
#define F16_ABSMIN ((float16_t)0.0f16)
|
||||
|
||||
#endif /* ARM_FLOAT16_SUPPORTED*/
|
||||
#endif /* !defined( __CC_ARM ) */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* _ARM_MATH_F16_H */
|
||||
|
|
@ -0,0 +1,231 @@
|
|||
/* ----------------------------------------------------------------------
|
||||
* Project: CMSIS DSP Library
|
||||
* Title: arm_mve_tables.h
|
||||
* Description: common tables like fft twiddle factors, Bitreverse, reciprocal etc
|
||||
* used for MVE implementation only
|
||||
*
|
||||
* @version V1.10.0
|
||||
* @date 04 October 2021
|
||||
*
|
||||
* Target Processor: Cortex-M and Cortex-A cores
|
||||
* -------------------------------------------------------------------- */
|
||||
/*
|
||||
* Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
#ifndef _ARM_MVE_TABLES_H
|
||||
#define _ARM_MVE_TABLES_H
|
||||
|
||||
#include "arm_math_types.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
|
||||
|
||||
|
||||
#if defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE)
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_FFT_ALLOW_TABLES)
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F32_16) || defined(ARM_TABLE_TWIDDLECOEF_F32_32)
|
||||
|
||||
extern uint32_t rearranged_twiddle_tab_stride1_arr_16_f32[2];
|
||||
extern uint32_t rearranged_twiddle_tab_stride2_arr_16_f32[2];
|
||||
extern uint32_t rearranged_twiddle_tab_stride3_arr_16_f32[2];
|
||||
extern float32_t rearranged_twiddle_stride1_16_f32[8];
|
||||
extern float32_t rearranged_twiddle_stride2_16_f32[8];
|
||||
extern float32_t rearranged_twiddle_stride3_16_f32[8];
|
||||
#endif
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F32_64) || defined(ARM_TABLE_TWIDDLECOEF_F32_128)
|
||||
|
||||
extern uint32_t rearranged_twiddle_tab_stride1_arr_64_f32[3];
|
||||
extern uint32_t rearranged_twiddle_tab_stride2_arr_64_f32[3];
|
||||
extern uint32_t rearranged_twiddle_tab_stride3_arr_64_f32[3];
|
||||
extern float32_t rearranged_twiddle_stride1_64_f32[40];
|
||||
extern float32_t rearranged_twiddle_stride2_64_f32[40];
|
||||
extern float32_t rearranged_twiddle_stride3_64_f32[40];
|
||||
#endif
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F32_256) || defined(ARM_TABLE_TWIDDLECOEF_F32_512)
|
||||
|
||||
extern uint32_t rearranged_twiddle_tab_stride1_arr_256_f32[4];
|
||||
extern uint32_t rearranged_twiddle_tab_stride2_arr_256_f32[4];
|
||||
extern uint32_t rearranged_twiddle_tab_stride3_arr_256_f32[4];
|
||||
extern float32_t rearranged_twiddle_stride1_256_f32[168];
|
||||
extern float32_t rearranged_twiddle_stride2_256_f32[168];
|
||||
extern float32_t rearranged_twiddle_stride3_256_f32[168];
|
||||
#endif
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F32_1024) || defined(ARM_TABLE_TWIDDLECOEF_F32_2048)
|
||||
|
||||
extern uint32_t rearranged_twiddle_tab_stride1_arr_1024_f32[5];
|
||||
extern uint32_t rearranged_twiddle_tab_stride2_arr_1024_f32[5];
|
||||
extern uint32_t rearranged_twiddle_tab_stride3_arr_1024_f32[5];
|
||||
extern float32_t rearranged_twiddle_stride1_1024_f32[680];
|
||||
extern float32_t rearranged_twiddle_stride2_1024_f32[680];
|
||||
extern float32_t rearranged_twiddle_stride3_1024_f32[680];
|
||||
#endif
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F32_4096) || defined(ARM_TABLE_TWIDDLECOEF_F32_8192)
|
||||
|
||||
extern uint32_t rearranged_twiddle_tab_stride1_arr_4096_f32[6];
|
||||
extern uint32_t rearranged_twiddle_tab_stride2_arr_4096_f32[6];
|
||||
extern uint32_t rearranged_twiddle_tab_stride3_arr_4096_f32[6];
|
||||
extern float32_t rearranged_twiddle_stride1_4096_f32[2728];
|
||||
extern float32_t rearranged_twiddle_stride2_4096_f32[2728];
|
||||
extern float32_t rearranged_twiddle_stride3_4096_f32[2728];
|
||||
#endif
|
||||
|
||||
|
||||
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_FFT_ALLOW_TABLES) */
|
||||
|
||||
#endif /* defined(ARM_MATH_MVEF) && !defined(ARM_MATH_AUTOVECTORIZE) */
|
||||
|
||||
|
||||
|
||||
#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE)
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_FFT_ALLOW_TABLES)
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q31_16) || defined(ARM_TABLE_TWIDDLECOEF_Q31_32)
|
||||
|
||||
extern uint32_t rearranged_twiddle_tab_stride1_arr_16_q31[2];
|
||||
extern uint32_t rearranged_twiddle_tab_stride2_arr_16_q31[2];
|
||||
extern uint32_t rearranged_twiddle_tab_stride3_arr_16_q31[2];
|
||||
extern q31_t rearranged_twiddle_stride1_16_q31[8];
|
||||
extern q31_t rearranged_twiddle_stride2_16_q31[8];
|
||||
extern q31_t rearranged_twiddle_stride3_16_q31[8];
|
||||
#endif
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q31_64) || defined(ARM_TABLE_TWIDDLECOEF_Q31_128)
|
||||
|
||||
extern uint32_t rearranged_twiddle_tab_stride1_arr_64_q31[3];
|
||||
extern uint32_t rearranged_twiddle_tab_stride2_arr_64_q31[3];
|
||||
extern uint32_t rearranged_twiddle_tab_stride3_arr_64_q31[3];
|
||||
extern q31_t rearranged_twiddle_stride1_64_q31[40];
|
||||
extern q31_t rearranged_twiddle_stride2_64_q31[40];
|
||||
extern q31_t rearranged_twiddle_stride3_64_q31[40];
|
||||
#endif
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q31_256) || defined(ARM_TABLE_TWIDDLECOEF_Q31_512)
|
||||
|
||||
extern uint32_t rearranged_twiddle_tab_stride1_arr_256_q31[4];
|
||||
extern uint32_t rearranged_twiddle_tab_stride2_arr_256_q31[4];
|
||||
extern uint32_t rearranged_twiddle_tab_stride3_arr_256_q31[4];
|
||||
extern q31_t rearranged_twiddle_stride1_256_q31[168];
|
||||
extern q31_t rearranged_twiddle_stride2_256_q31[168];
|
||||
extern q31_t rearranged_twiddle_stride3_256_q31[168];
|
||||
#endif
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q31_1024) || defined(ARM_TABLE_TWIDDLECOEF_Q31_2048)
|
||||
|
||||
extern uint32_t rearranged_twiddle_tab_stride1_arr_1024_q31[5];
|
||||
extern uint32_t rearranged_twiddle_tab_stride2_arr_1024_q31[5];
|
||||
extern uint32_t rearranged_twiddle_tab_stride3_arr_1024_q31[5];
|
||||
extern q31_t rearranged_twiddle_stride1_1024_q31[680];
|
||||
extern q31_t rearranged_twiddle_stride2_1024_q31[680];
|
||||
extern q31_t rearranged_twiddle_stride3_1024_q31[680];
|
||||
#endif
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q31_4096) || defined(ARM_TABLE_TWIDDLECOEF_Q31_8192)
|
||||
|
||||
extern uint32_t rearranged_twiddle_tab_stride1_arr_4096_q31[6];
|
||||
extern uint32_t rearranged_twiddle_tab_stride2_arr_4096_q31[6];
|
||||
extern uint32_t rearranged_twiddle_tab_stride3_arr_4096_q31[6];
|
||||
extern q31_t rearranged_twiddle_stride1_4096_q31[2728];
|
||||
extern q31_t rearranged_twiddle_stride2_4096_q31[2728];
|
||||
extern q31_t rearranged_twiddle_stride3_4096_q31[2728];
|
||||
#endif
|
||||
|
||||
|
||||
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_FFT_ALLOW_TABLES) */
|
||||
|
||||
#endif /* defined(ARM_MATH_MVEI) */
|
||||
|
||||
|
||||
|
||||
#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE)
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_FFT_ALLOW_TABLES)
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q15_16) || defined(ARM_TABLE_TWIDDLECOEF_Q15_32)
|
||||
|
||||
extern uint32_t rearranged_twiddle_tab_stride1_arr_16_q15[2];
|
||||
extern uint32_t rearranged_twiddle_tab_stride2_arr_16_q15[2];
|
||||
extern uint32_t rearranged_twiddle_tab_stride3_arr_16_q15[2];
|
||||
extern q15_t rearranged_twiddle_stride1_16_q15[8];
|
||||
extern q15_t rearranged_twiddle_stride2_16_q15[8];
|
||||
extern q15_t rearranged_twiddle_stride3_16_q15[8];
|
||||
#endif
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q15_64) || defined(ARM_TABLE_TWIDDLECOEF_Q15_128)
|
||||
|
||||
extern uint32_t rearranged_twiddle_tab_stride1_arr_64_q15[3];
|
||||
extern uint32_t rearranged_twiddle_tab_stride2_arr_64_q15[3];
|
||||
extern uint32_t rearranged_twiddle_tab_stride3_arr_64_q15[3];
|
||||
extern q15_t rearranged_twiddle_stride1_64_q15[40];
|
||||
extern q15_t rearranged_twiddle_stride2_64_q15[40];
|
||||
extern q15_t rearranged_twiddle_stride3_64_q15[40];
|
||||
#endif
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q15_256) || defined(ARM_TABLE_TWIDDLECOEF_Q15_512)
|
||||
|
||||
extern uint32_t rearranged_twiddle_tab_stride1_arr_256_q15[4];
|
||||
extern uint32_t rearranged_twiddle_tab_stride2_arr_256_q15[4];
|
||||
extern uint32_t rearranged_twiddle_tab_stride3_arr_256_q15[4];
|
||||
extern q15_t rearranged_twiddle_stride1_256_q15[168];
|
||||
extern q15_t rearranged_twiddle_stride2_256_q15[168];
|
||||
extern q15_t rearranged_twiddle_stride3_256_q15[168];
|
||||
#endif
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q15_1024) || defined(ARM_TABLE_TWIDDLECOEF_Q15_2048)
|
||||
|
||||
extern uint32_t rearranged_twiddle_tab_stride1_arr_1024_q15[5];
|
||||
extern uint32_t rearranged_twiddle_tab_stride2_arr_1024_q15[5];
|
||||
extern uint32_t rearranged_twiddle_tab_stride3_arr_1024_q15[5];
|
||||
extern q15_t rearranged_twiddle_stride1_1024_q15[680];
|
||||
extern q15_t rearranged_twiddle_stride2_1024_q15[680];
|
||||
extern q15_t rearranged_twiddle_stride3_1024_q15[680];
|
||||
#endif
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_Q15_4096) || defined(ARM_TABLE_TWIDDLECOEF_Q15_8192)
|
||||
|
||||
extern uint32_t rearranged_twiddle_tab_stride1_arr_4096_q15[6];
|
||||
extern uint32_t rearranged_twiddle_tab_stride2_arr_4096_q15[6];
|
||||
extern uint32_t rearranged_twiddle_tab_stride3_arr_4096_q15[6];
|
||||
extern q15_t rearranged_twiddle_stride1_4096_q15[2728];
|
||||
extern q15_t rearranged_twiddle_stride2_4096_q15[2728];
|
||||
extern q15_t rearranged_twiddle_stride3_4096_q15[2728];
|
||||
#endif
|
||||
|
||||
|
||||
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_FFT_ALLOW_TABLES) */
|
||||
|
||||
#endif /* defined(ARM_MATH_MVEI) */
|
||||
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /*_ARM_MVE_TABLES_H*/
|
||||
|
||||
|
|
@ -0,0 +1,109 @@
|
|||
/* ----------------------------------------------------------------------
|
||||
* Project: CMSIS DSP Library
|
||||
* Title: arm_mve_tables_f16.h
|
||||
* Description: common tables like fft twiddle factors, Bitreverse, reciprocal etc
|
||||
* used for MVE implementation only
|
||||
*
|
||||
* @version V1.10.0
|
||||
* @date 04 October 2021
|
||||
*
|
||||
* Target Processor: Cortex-M and Cortex-A cores
|
||||
* -------------------------------------------------------------------- */
|
||||
/*
|
||||
* Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
#ifndef _ARM_MVE_TABLES_F16_H
|
||||
#define _ARM_MVE_TABLES_F16_H
|
||||
|
||||
#include "arm_math_types_f16.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
|
||||
|
||||
|
||||
#if defined(ARM_MATH_MVE_FLOAT16) && !defined(ARM_MATH_AUTOVECTORIZE)
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_FFT_ALLOW_TABLES)
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F16_16) || defined(ARM_TABLE_TWIDDLECOEF_F16_32)
|
||||
|
||||
extern uint32_t rearranged_twiddle_tab_stride1_arr_16_f16[2];
|
||||
extern uint32_t rearranged_twiddle_tab_stride2_arr_16_f16[2];
|
||||
extern uint32_t rearranged_twiddle_tab_stride3_arr_16_f16[2];
|
||||
extern float16_t rearranged_twiddle_stride1_16_f16[8];
|
||||
extern float16_t rearranged_twiddle_stride2_16_f16[8];
|
||||
extern float16_t rearranged_twiddle_stride3_16_f16[8];
|
||||
#endif
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F16_64) || defined(ARM_TABLE_TWIDDLECOEF_F16_128)
|
||||
|
||||
extern uint32_t rearranged_twiddle_tab_stride1_arr_64_f16[3];
|
||||
extern uint32_t rearranged_twiddle_tab_stride2_arr_64_f16[3];
|
||||
extern uint32_t rearranged_twiddle_tab_stride3_arr_64_f16[3];
|
||||
extern float16_t rearranged_twiddle_stride1_64_f16[40];
|
||||
extern float16_t rearranged_twiddle_stride2_64_f16[40];
|
||||
extern float16_t rearranged_twiddle_stride3_64_f16[40];
|
||||
#endif
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F16_256) || defined(ARM_TABLE_TWIDDLECOEF_F16_512)
|
||||
|
||||
extern uint32_t rearranged_twiddle_tab_stride1_arr_256_f16[4];
|
||||
extern uint32_t rearranged_twiddle_tab_stride2_arr_256_f16[4];
|
||||
extern uint32_t rearranged_twiddle_tab_stride3_arr_256_f16[4];
|
||||
extern float16_t rearranged_twiddle_stride1_256_f16[168];
|
||||
extern float16_t rearranged_twiddle_stride2_256_f16[168];
|
||||
extern float16_t rearranged_twiddle_stride3_256_f16[168];
|
||||
#endif
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F16_1024) || defined(ARM_TABLE_TWIDDLECOEF_F16_2048)
|
||||
|
||||
extern uint32_t rearranged_twiddle_tab_stride1_arr_1024_f16[5];
|
||||
extern uint32_t rearranged_twiddle_tab_stride2_arr_1024_f16[5];
|
||||
extern uint32_t rearranged_twiddle_tab_stride3_arr_1024_f16[5];
|
||||
extern float16_t rearranged_twiddle_stride1_1024_f16[680];
|
||||
extern float16_t rearranged_twiddle_stride2_1024_f16[680];
|
||||
extern float16_t rearranged_twiddle_stride3_1024_f16[680];
|
||||
#endif
|
||||
|
||||
#if !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_ALL_FFT_TABLES) || defined(ARM_TABLE_TWIDDLECOEF_F16_4096) || defined(ARM_TABLE_TWIDDLECOEF_F16_8192)
|
||||
|
||||
extern uint32_t rearranged_twiddle_tab_stride1_arr_4096_f16[6];
|
||||
extern uint32_t rearranged_twiddle_tab_stride2_arr_4096_f16[6];
|
||||
extern uint32_t rearranged_twiddle_tab_stride3_arr_4096_f16[6];
|
||||
extern float16_t rearranged_twiddle_stride1_4096_f16[2728];
|
||||
extern float16_t rearranged_twiddle_stride2_4096_f16[2728];
|
||||
extern float16_t rearranged_twiddle_stride3_4096_f16[2728];
|
||||
#endif
|
||||
|
||||
|
||||
#endif /* !defined(ARM_DSP_CONFIG_TABLES) || defined(ARM_FFT_ALLOW_TABLES) */
|
||||
|
||||
#endif /* defined(ARM_MATH_MVE_FLOAT16) && !defined(ARM_MATH_AUTOVECTORIZE) */
|
||||
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /*_ARM_MVE_TABLES_F16_H*/
|
||||
|
||||
|
|
@ -0,0 +1,373 @@
|
|||
/******************************************************************************
|
||||
* @file arm_vec_math.h
|
||||
* @brief Public header file for CMSIS DSP Library
|
||||
* @version V1.10.0
|
||||
* @date 08 July 2021
|
||||
* Target Processor: Cortex-M and Cortex-A cores
|
||||
******************************************************************************/
|
||||
/*
|
||||
* Copyright (c) 2010-2021 Arm Limited or its affiliates. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
#ifndef _ARM_VEC_MATH_H
|
||||
#define _ARM_VEC_MATH_H
|
||||
|
||||
#include "arm_math_types.h"
|
||||
#include "arm_common_tables.h"
|
||||
#include "arm_helium_utils.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
#if (defined(ARM_MATH_MVEF) || defined(ARM_MATH_HELIUM)) && !defined(ARM_MATH_AUTOVECTORIZE)
|
||||
|
||||
#define INV_NEWTON_INIT_F32 0x7EF127EA
|
||||
|
||||
static const float32_t __logf_rng_f32=0.693147180f;
|
||||
|
||||
|
||||
/* fast inverse approximation (3x newton) */
|
||||
__STATIC_INLINE f32x4_t vrecip_medprec_f32(
|
||||
f32x4_t x)
|
||||
{
|
||||
q31x4_t m;
|
||||
f32x4_t b;
|
||||
any32x4_t xinv;
|
||||
f32x4_t ax = vabsq(x);
|
||||
|
||||
xinv.f = ax;
|
||||
m = 0x3F800000 - (xinv.i & 0x7F800000);
|
||||
xinv.i = xinv.i + m;
|
||||
xinv.f = 1.41176471f - 0.47058824f * xinv.f;
|
||||
xinv.i = xinv.i + m;
|
||||
|
||||
b = 2.0f - xinv.f * ax;
|
||||
xinv.f = xinv.f * b;
|
||||
|
||||
b = 2.0f - xinv.f * ax;
|
||||
xinv.f = xinv.f * b;
|
||||
|
||||
b = 2.0f - xinv.f * ax;
|
||||
xinv.f = xinv.f * b;
|
||||
|
||||
xinv.f = vdupq_m(xinv.f, INFINITY, vcmpeqq(x, 0.0f));
|
||||
/*
|
||||
* restore sign
|
||||
*/
|
||||
xinv.f = vnegq_m(xinv.f, xinv.f, vcmpltq(x, 0.0f));
|
||||
|
||||
return xinv.f;
|
||||
}
|
||||
|
||||
/* fast inverse approximation (4x newton) */
|
||||
__STATIC_INLINE f32x4_t vrecip_hiprec_f32(
|
||||
f32x4_t x)
|
||||
{
|
||||
q31x4_t m;
|
||||
f32x4_t b;
|
||||
any32x4_t xinv;
|
||||
f32x4_t ax = vabsq(x);
|
||||
|
||||
xinv.f = ax;
|
||||
|
||||
m = 0x3F800000 - (xinv.i & 0x7F800000);
|
||||
xinv.i = xinv.i + m;
|
||||
xinv.f = 1.41176471f - 0.47058824f * xinv.f;
|
||||
xinv.i = xinv.i + m;
|
||||
|
||||
b = 2.0f - xinv.f * ax;
|
||||
xinv.f = xinv.f * b;
|
||||
|
||||
b = 2.0f - xinv.f * ax;
|
||||
xinv.f = xinv.f * b;
|
||||
|
||||
b = 2.0f - xinv.f * ax;
|
||||
xinv.f = xinv.f * b;
|
||||
|
||||
b = 2.0f - xinv.f * ax;
|
||||
xinv.f = xinv.f * b;
|
||||
|
||||
xinv.f = vdupq_m(xinv.f, INFINITY, vcmpeqq(x, 0.0f));
|
||||
/*
|
||||
* restore sign
|
||||
*/
|
||||
xinv.f = vnegq_m(xinv.f, xinv.f, vcmpltq(x, 0.0f));
|
||||
|
||||
return xinv.f;
|
||||
}
|
||||
|
||||
__STATIC_INLINE f32x4_t vdiv_f32(
|
||||
f32x4_t num, f32x4_t den)
|
||||
{
|
||||
return vmulq(num, vrecip_hiprec_f32(den));
|
||||
}
|
||||
|
||||
/**
|
||||
@brief Single-precision taylor dev.
|
||||
@param[in] x f32 quad vector input
|
||||
@param[in] coeffs f32 quad vector coeffs
|
||||
@return destination f32 quad vector
|
||||
*/
|
||||
|
||||
__STATIC_INLINE f32x4_t vtaylor_polyq_f32(
|
||||
f32x4_t x,
|
||||
const float32_t * coeffs)
|
||||
{
|
||||
f32x4_t A = vfmasq(vdupq_n_f32(coeffs[4]), x, coeffs[0]);
|
||||
f32x4_t B = vfmasq(vdupq_n_f32(coeffs[6]), x, coeffs[2]);
|
||||
f32x4_t C = vfmasq(vdupq_n_f32(coeffs[5]), x, coeffs[1]);
|
||||
f32x4_t D = vfmasq(vdupq_n_f32(coeffs[7]), x, coeffs[3]);
|
||||
f32x4_t x2 = vmulq(x, x);
|
||||
f32x4_t x4 = vmulq(x2, x2);
|
||||
f32x4_t res = vfmaq(vfmaq_f32(A, B, x2), vfmaq_f32(C, D, x2), x4);
|
||||
|
||||
return res;
|
||||
}
|
||||
|
||||
__STATIC_INLINE f32x4_t vmant_exp_f32(
|
||||
f32x4_t x,
|
||||
int32x4_t * e)
|
||||
{
|
||||
any32x4_t r;
|
||||
int32x4_t n;
|
||||
|
||||
r.f = x;
|
||||
n = r.i >> 23;
|
||||
n = n - 127;
|
||||
r.i = r.i - (n << 23);
|
||||
|
||||
*e = n;
|
||||
return r.f;
|
||||
}
|
||||
|
||||
|
||||
__STATIC_INLINE f32x4_t vlogq_f32(f32x4_t vecIn)
|
||||
{
|
||||
q31x4_t vecExpUnBiased;
|
||||
f32x4_t vecTmpFlt0, vecTmpFlt1;
|
||||
f32x4_t vecAcc0, vecAcc1, vecAcc2, vecAcc3;
|
||||
f32x4_t vecExpUnBiasedFlt;
|
||||
|
||||
/*
|
||||
* extract exponent
|
||||
*/
|
||||
vecTmpFlt1 = vmant_exp_f32(vecIn, &vecExpUnBiased);
|
||||
|
||||
vecTmpFlt0 = vecTmpFlt1 * vecTmpFlt1;
|
||||
/*
|
||||
* a = (__logf_lut_f32[4] * r.f) + (__logf_lut_f32[0]);
|
||||
*/
|
||||
vecAcc0 = vdupq_n_f32(__logf_lut_f32[0]);
|
||||
vecAcc0 = vfmaq(vecAcc0, vecTmpFlt1, __logf_lut_f32[4]);
|
||||
/*
|
||||
* b = (__logf_lut_f32[6] * r.f) + (__logf_lut_f32[2]);
|
||||
*/
|
||||
vecAcc1 = vdupq_n_f32(__logf_lut_f32[2]);
|
||||
vecAcc1 = vfmaq(vecAcc1, vecTmpFlt1, __logf_lut_f32[6]);
|
||||
/*
|
||||
* c = (__logf_lut_f32[5] * r.f) + (__logf_lut_f32[1]);
|
||||
*/
|
||||
vecAcc2 = vdupq_n_f32(__logf_lut_f32[1]);
|
||||
vecAcc2 = vfmaq(vecAcc2, vecTmpFlt1, __logf_lut_f32[5]);
|
||||
/*
|
||||
* d = (__logf_lut_f32[7] * r.f) + (__logf_lut_f32[3]);
|
||||
*/
|
||||
vecAcc3 = vdupq_n_f32(__logf_lut_f32[3]);
|
||||
vecAcc3 = vfmaq(vecAcc3, vecTmpFlt1, __logf_lut_f32[7]);
|
||||
/*
|
||||
* a = a + b * xx;
|
||||
*/
|
||||
vecAcc0 = vfmaq(vecAcc0, vecAcc1, vecTmpFlt0);
|
||||
/*
|
||||
* c = c + d * xx;
|
||||
*/
|
||||
vecAcc2 = vfmaq(vecAcc2, vecAcc3, vecTmpFlt0);
|
||||
/*
|
||||
* xx = xx * xx;
|
||||
*/
|
||||
vecTmpFlt0 = vecTmpFlt0 * vecTmpFlt0;
|
||||
vecExpUnBiasedFlt = vcvtq_f32_s32(vecExpUnBiased);
|
||||
/*
|
||||
* r.f = a + c * xx;
|
||||
*/
|
||||
vecAcc0 = vfmaq(vecAcc0, vecAcc2, vecTmpFlt0);
|
||||
/*
|
||||
* add exponent
|
||||
* r.f = r.f + ((float32_t) m) * __logf_rng_f32;
|
||||
*/
|
||||
vecAcc0 = vfmaq(vecAcc0, vecExpUnBiasedFlt, __logf_rng_f32);
|
||||
// set log0 down to -inf
|
||||
vecAcc0 = vdupq_m(vecAcc0, -INFINITY, vcmpeqq(vecIn, 0.0f));
|
||||
return vecAcc0;
|
||||
}
|
||||
|
||||
__STATIC_INLINE f32x4_t vexpq_f32(
|
||||
f32x4_t x)
|
||||
{
|
||||
// Perform range reduction [-log(2),log(2)]
|
||||
int32x4_t m = vcvtq_s32_f32(vmulq_n_f32(x, 1.4426950408f));
|
||||
f32x4_t val = vfmsq_f32(x, vcvtq_f32_s32(m), vdupq_n_f32(0.6931471805f));
|
||||
|
||||
// Polynomial Approximation
|
||||
f32x4_t poly = vtaylor_polyq_f32(val, exp_tab);
|
||||
|
||||
// Reconstruct
|
||||
poly = (f32x4_t) (vqaddq_s32((q31x4_t) (poly), vqshlq_n_s32(m, 23)));
|
||||
|
||||
poly = vdupq_m(poly, 0.0f, vcmpltq_n_s32(m, -126));
|
||||
return poly;
|
||||
}
|
||||
|
||||
__STATIC_INLINE f32x4_t arm_vec_exponent_f32(f32x4_t x, int32_t nb)
|
||||
{
|
||||
f32x4_t r = x;
|
||||
nb--;
|
||||
while (nb > 0) {
|
||||
r = vmulq(r, x);
|
||||
nb--;
|
||||
}
|
||||
return (r);
|
||||
}
|
||||
|
||||
__STATIC_INLINE f32x4_t vrecip_f32(f32x4_t vecIn)
|
||||
{
|
||||
f32x4_t vecSx, vecW, vecTmp;
|
||||
any32x4_t v;
|
||||
|
||||
vecSx = vabsq(vecIn);
|
||||
|
||||
v.f = vecIn;
|
||||
v.i = vsubq(vdupq_n_s32(INV_NEWTON_INIT_F32), v.i);
|
||||
|
||||
vecW = vmulq(vecSx, v.f);
|
||||
|
||||
// v.f = v.f * (8 + w * (-28 + w * (56 + w * (-70 + w *(56 + w * (-28 + w * (8 - w)))))));
|
||||
vecTmp = vsubq(vdupq_n_f32(8.0f), vecW);
|
||||
vecTmp = vfmasq(vecW, vecTmp, -28.0f);
|
||||
vecTmp = vfmasq(vecW, vecTmp, 56.0f);
|
||||
vecTmp = vfmasq(vecW, vecTmp, -70.0f);
|
||||
vecTmp = vfmasq(vecW, vecTmp, 56.0f);
|
||||
vecTmp = vfmasq(vecW, vecTmp, -28.0f);
|
||||
vecTmp = vfmasq(vecW, vecTmp, 8.0f);
|
||||
v.f = vmulq(v.f, vecTmp);
|
||||
|
||||
v.f = vdupq_m(v.f, INFINITY, vcmpeqq(vecIn, 0.0f));
|
||||
/*
|
||||
* restore sign
|
||||
*/
|
||||
v.f = vnegq_m(v.f, v.f, vcmpltq(vecIn, 0.0f));
|
||||
return v.f;
|
||||
}
|
||||
|
||||
__STATIC_INLINE f32x4_t vtanhq_f32(
|
||||
f32x4_t val)
|
||||
{
|
||||
f32x4_t x =
|
||||
vminnmq_f32(vmaxnmq_f32(val, vdupq_n_f32(-10.f)), vdupq_n_f32(10.0f));
|
||||
f32x4_t exp2x = vexpq_f32(vmulq_n_f32(x, 2.f));
|
||||
f32x4_t num = vsubq_n_f32(exp2x, 1.f);
|
||||
f32x4_t den = vaddq_n_f32(exp2x, 1.f);
|
||||
f32x4_t tanh = vmulq_f32(num, vrecip_f32(den));
|
||||
return tanh;
|
||||
}
|
||||
|
||||
__STATIC_INLINE f32x4_t vpowq_f32(
|
||||
f32x4_t val,
|
||||
f32x4_t n)
|
||||
{
|
||||
return vexpq_f32(vmulq_f32(n, vlogq_f32(val)));
|
||||
}
|
||||
|
||||
#endif /* (defined(ARM_MATH_MVEF) || defined(ARM_MATH_HELIUM)) && !defined(ARM_MATH_AUTOVECTORIZE)*/
|
||||
|
||||
#if (defined(ARM_MATH_MVEI) || defined(ARM_MATH_HELIUM)) && !defined(ARM_MATH_AUTOVECTORIZE)
|
||||
#endif /* (defined(ARM_MATH_MVEI) || defined(ARM_MATH_HELIUM)) */
|
||||
|
||||
#if (defined(ARM_MATH_NEON) || defined(ARM_MATH_NEON_EXPERIMENTAL)) && !defined(ARM_MATH_AUTOVECTORIZE)
|
||||
|
||||
#include "NEMath.h"
|
||||
/**
|
||||
* @brief Vectorized integer exponentiation
|
||||
* @param[in] x value
|
||||
* @param[in] nb integer exponent >= 1
|
||||
* @return x^nb
|
||||
*
|
||||
*/
|
||||
__STATIC_INLINE float32x4_t arm_vec_exponent_f32(float32x4_t x, int32_t nb)
|
||||
{
|
||||
float32x4_t r = x;
|
||||
nb --;
|
||||
while(nb > 0)
|
||||
{
|
||||
r = vmulq_f32(r , x);
|
||||
nb--;
|
||||
}
|
||||
return(r);
|
||||
}
|
||||
|
||||
|
||||
__STATIC_INLINE float32x4_t __arm_vec_sqrt_f32_neon(float32x4_t x)
|
||||
{
|
||||
float32x4_t x1 = vmaxq_f32(x, vdupq_n_f32(FLT_MIN));
|
||||
float32x4_t e = vrsqrteq_f32(x1);
|
||||
e = vmulq_f32(vrsqrtsq_f32(vmulq_f32(x1, e), e), e);
|
||||
e = vmulq_f32(vrsqrtsq_f32(vmulq_f32(x1, e), e), e);
|
||||
return vmulq_f32(x, e);
|
||||
}
|
||||
|
||||
__STATIC_INLINE int16x8_t __arm_vec_sqrt_q15_neon(int16x8_t vec)
|
||||
{
|
||||
float32x4_t tempF;
|
||||
int32x4_t tempHI,tempLO;
|
||||
|
||||
tempLO = vmovl_s16(vget_low_s16(vec));
|
||||
tempF = vcvtq_n_f32_s32(tempLO,15);
|
||||
tempF = __arm_vec_sqrt_f32_neon(tempF);
|
||||
tempLO = vcvtq_n_s32_f32(tempF,15);
|
||||
|
||||
tempHI = vmovl_s16(vget_high_s16(vec));
|
||||
tempF = vcvtq_n_f32_s32(tempHI,15);
|
||||
tempF = __arm_vec_sqrt_f32_neon(tempF);
|
||||
tempHI = vcvtq_n_s32_f32(tempF,15);
|
||||
|
||||
return(vcombine_s16(vqmovn_s32(tempLO),vqmovn_s32(tempHI)));
|
||||
}
|
||||
|
||||
__STATIC_INLINE int32x4_t __arm_vec_sqrt_q31_neon(int32x4_t vec)
|
||||
{
|
||||
float32x4_t temp;
|
||||
|
||||
temp = vcvtq_n_f32_s32(vec,31);
|
||||
temp = __arm_vec_sqrt_f32_neon(temp);
|
||||
return(vcvtq_n_s32_f32(temp,31));
|
||||
}
|
||||
|
||||
#endif /* (defined(ARM_MATH_NEON) || defined(ARM_MATH_NEON_EXPERIMENTAL)) && !defined(ARM_MATH_AUTOVECTORIZE) */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
#endif /* _ARM_VEC_MATH_H */
|
||||
|
||||
/**
|
||||
*
|
||||
* End of file.
|
||||
*/
|
||||
|
|
@ -0,0 +1,312 @@
|
|||
/******************************************************************************
|
||||
* @file arm_vec_math_f16.h
|
||||
* @brief Public header file for CMSIS DSP Library
|
||||
* @version V1.10.0
|
||||
* @date 08 July 2021
|
||||
* Target Processor: Cortex-M and Cortex-A cores
|
||||
******************************************************************************/
|
||||
/*
|
||||
* Copyright (c) 2010-2021 Arm Limited or its affiliates. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
#ifndef _ARM_VEC_MATH_F16_H
|
||||
#define _ARM_VEC_MATH_F16_H
|
||||
|
||||
#include "arm_math_types_f16.h"
|
||||
#include "arm_common_tables_f16.h"
|
||||
#include "arm_helium_utils.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
#if defined(ARM_FLOAT16_SUPPORTED)
|
||||
|
||||
|
||||
#if defined(ARM_MATH_MVE_FLOAT16) && !defined(ARM_MATH_AUTOVECTORIZE)
|
||||
|
||||
|
||||
static const float16_t __logf_rng_f16=0.693147180f16;
|
||||
|
||||
/* fast inverse approximation (3x newton) */
|
||||
__STATIC_INLINE f16x8_t vrecip_medprec_f16(
|
||||
f16x8_t x)
|
||||
{
|
||||
q15x8_t m;
|
||||
f16x8_t b;
|
||||
any16x8_t xinv;
|
||||
f16x8_t ax = vabsq(x);
|
||||
|
||||
xinv.f = ax;
|
||||
|
||||
m = 0x03c00 - (xinv.i & 0x07c00);
|
||||
xinv.i = xinv.i + m;
|
||||
xinv.f = 1.41176471f16 - 0.47058824f16 * xinv.f;
|
||||
xinv.i = xinv.i + m;
|
||||
|
||||
b = 2.0f16 - xinv.f * ax;
|
||||
xinv.f = xinv.f * b;
|
||||
|
||||
b = 2.0f16 - xinv.f * ax;
|
||||
xinv.f = xinv.f * b;
|
||||
|
||||
b = 2.0f16 - xinv.f * ax;
|
||||
xinv.f = xinv.f * b;
|
||||
|
||||
xinv.f = vdupq_m_n_f16(xinv.f, F16INFINITY, vcmpeqq_n_f16(x, 0.0f));
|
||||
/*
|
||||
* restore sign
|
||||
*/
|
||||
xinv.f = vnegq_m(xinv.f, xinv.f, vcmpltq_n_f16(x, 0.0f));
|
||||
|
||||
return xinv.f;
|
||||
}
|
||||
|
||||
/* fast inverse approximation (4x newton) */
|
||||
__STATIC_INLINE f16x8_t vrecip_hiprec_f16(
|
||||
f16x8_t x)
|
||||
{
|
||||
q15x8_t m;
|
||||
f16x8_t b;
|
||||
any16x8_t xinv;
|
||||
f16x8_t ax = vabsq(x);
|
||||
|
||||
xinv.f = ax;
|
||||
|
||||
m = 0x03c00 - (xinv.i & 0x07c00);
|
||||
xinv.i = xinv.i + m;
|
||||
xinv.f = 1.41176471f16 - 0.47058824f16 * xinv.f;
|
||||
xinv.i = xinv.i + m;
|
||||
|
||||
b = 2.0f16 - xinv.f * ax;
|
||||
xinv.f = xinv.f * b;
|
||||
|
||||
b = 2.0f16 - xinv.f * ax;
|
||||
xinv.f = xinv.f * b;
|
||||
|
||||
b = 2.0f16 - xinv.f * ax;
|
||||
xinv.f = xinv.f * b;
|
||||
|
||||
b = 2.0f16 - xinv.f * ax;
|
||||
xinv.f = xinv.f * b;
|
||||
|
||||
xinv.f = vdupq_m_n_f16(xinv.f, F16INFINITY, vcmpeqq_n_f16(x, 0.0f));
|
||||
/*
|
||||
* restore sign
|
||||
*/
|
||||
xinv.f = vnegq_m(xinv.f, xinv.f, vcmpltq_n_f16(x, 0.0f));
|
||||
|
||||
return xinv.f;
|
||||
}
|
||||
|
||||
__STATIC_INLINE f16x8_t vdiv_f16(
|
||||
f16x8_t num, f16x8_t den)
|
||||
{
|
||||
return vmulq(num, vrecip_hiprec_f16(den));
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
@brief Single-precision taylor dev.
|
||||
@param[in] x f16 vector input
|
||||
@param[in] coeffs f16 vector coeffs
|
||||
@return destination f16 vector
|
||||
*/
|
||||
|
||||
__STATIC_INLINE float16x8_t vtaylor_polyq_f16(
|
||||
float16x8_t x,
|
||||
const float16_t * coeffs)
|
||||
{
|
||||
float16x8_t A = vfmasq(vdupq_n_f16(coeffs[4]), x, coeffs[0]);
|
||||
float16x8_t B = vfmasq(vdupq_n_f16(coeffs[6]), x, coeffs[2]);
|
||||
float16x8_t C = vfmasq(vdupq_n_f16(coeffs[5]), x, coeffs[1]);
|
||||
float16x8_t D = vfmasq(vdupq_n_f16(coeffs[7]), x, coeffs[3]);
|
||||
float16x8_t x2 = vmulq(x, x);
|
||||
float16x8_t x4 = vmulq(x2, x2);
|
||||
float16x8_t res = vfmaq(vfmaq_f16(A, B, x2), vfmaq_f16(C, D, x2), x4);
|
||||
|
||||
return res;
|
||||
}
|
||||
|
||||
#define VMANT_EXP_F16(x) \
|
||||
any16x8_t r; \
|
||||
int16x8_t n; \
|
||||
\
|
||||
r.f = x; \
|
||||
n = r.i >> 10; \
|
||||
n = n - 15; \
|
||||
r.i = r.i - (n << 10);\
|
||||
\
|
||||
vecExpUnBiased = n; \
|
||||
vecTmpFlt1 = r.f;
|
||||
|
||||
__STATIC_INLINE float16x8_t vlogq_f16(float16x8_t vecIn)
|
||||
{
|
||||
q15x8_t vecExpUnBiased;
|
||||
float16x8_t vecTmpFlt0, vecTmpFlt1;
|
||||
float16x8_t vecAcc0, vecAcc1, vecAcc2, vecAcc3;
|
||||
float16x8_t vecExpUnBiasedFlt;
|
||||
|
||||
/*
|
||||
* extract exponent
|
||||
*/
|
||||
VMANT_EXP_F16(vecIn);
|
||||
|
||||
vecTmpFlt0 = vecTmpFlt1 * vecTmpFlt1;
|
||||
/*
|
||||
* a = (__logf_lut_f16[4] * r.f) + (__logf_lut_f16[0]);
|
||||
*/
|
||||
vecAcc0 = vdupq_n_f16(__logf_lut_f16[0]);
|
||||
vecAcc0 = vfmaq(vecAcc0, vecTmpFlt1, __logf_lut_f16[4]);
|
||||
/*
|
||||
* b = (__logf_lut_f16[6] * r.f) + (__logf_lut_f16[2]);
|
||||
*/
|
||||
vecAcc1 = vdupq_n_f16(__logf_lut_f16[2]);
|
||||
vecAcc1 = vfmaq(vecAcc1, vecTmpFlt1, __logf_lut_f16[6]);
|
||||
/*
|
||||
* c = (__logf_lut_f16[5] * r.f) + (__logf_lut_f16[1]);
|
||||
*/
|
||||
vecAcc2 = vdupq_n_f16(__logf_lut_f16[1]);
|
||||
vecAcc2 = vfmaq(vecAcc2, vecTmpFlt1, __logf_lut_f16[5]);
|
||||
/*
|
||||
* d = (__logf_lut_f16[7] * r.f) + (__logf_lut_f16[3]);
|
||||
*/
|
||||
vecAcc3 = vdupq_n_f16(__logf_lut_f16[3]);
|
||||
vecAcc3 = vfmaq(vecAcc3, vecTmpFlt1, __logf_lut_f16[7]);
|
||||
/*
|
||||
* a = a + b * xx;
|
||||
*/
|
||||
vecAcc0 = vfmaq(vecAcc0, vecAcc1, vecTmpFlt0);
|
||||
/*
|
||||
* c = c + d * xx;
|
||||
*/
|
||||
vecAcc2 = vfmaq(vecAcc2, vecAcc3, vecTmpFlt0);
|
||||
/*
|
||||
* xx = xx * xx;
|
||||
*/
|
||||
vecTmpFlt0 = vecTmpFlt0 * vecTmpFlt0;
|
||||
vecExpUnBiasedFlt = vcvtq_f16_s16(vecExpUnBiased);
|
||||
/*
|
||||
* r.f = a + c * xx;
|
||||
*/
|
||||
vecAcc0 = vfmaq(vecAcc0, vecAcc2, vecTmpFlt0);
|
||||
/*
|
||||
* add exponent
|
||||
* r.f = r.f + ((float32_t) m) * __logf_rng_f16;
|
||||
*/
|
||||
vecAcc0 = vfmaq(vecAcc0, vecExpUnBiasedFlt, __logf_rng_f16);
|
||||
// set log0 down to -inf
|
||||
vecAcc0 = vdupq_m_n_f16(vecAcc0, -(_Float16)F16INFINITY, vcmpeqq_n_f16(vecIn, 0.0f));
|
||||
return vecAcc0;
|
||||
}
|
||||
|
||||
__STATIC_INLINE float16x8_t vexpq_f16(
|
||||
float16x8_t x)
|
||||
{
|
||||
// Perform range reduction [-log(2),log(2)]
|
||||
int16x8_t m = vcvtq_s16_f16(vmulq_n_f16(x, 1.4426950408f16));
|
||||
float16x8_t val = vfmsq_f16(x, vcvtq_f16_s16(m), vdupq_n_f16(0.6931471805f16));
|
||||
|
||||
// Polynomial Approximation
|
||||
float16x8_t poly = vtaylor_polyq_f16(val, exp_tab_f16);
|
||||
|
||||
// Reconstruct
|
||||
poly = (float16x8_t) (vqaddq_s16((int16x8_t) (poly), vqshlq_n_s16(m, 10)));
|
||||
|
||||
poly = vdupq_m_n_f16(poly, 0.0f16, vcmpltq_n_s16(m, -14));
|
||||
return poly;
|
||||
}
|
||||
|
||||
__STATIC_INLINE float16x8_t arm_vec_exponent_f16(float16x8_t x, int16_t nb)
|
||||
{
|
||||
float16x8_t r = x;
|
||||
nb--;
|
||||
while (nb > 0) {
|
||||
r = vmulq(r, x);
|
||||
nb--;
|
||||
}
|
||||
return (r);
|
||||
}
|
||||
|
||||
__STATIC_INLINE f16x8_t vpowq_f16(
|
||||
f16x8_t val,
|
||||
f16x8_t n)
|
||||
{
|
||||
return vexpq_f16(vmulq_f16(n, vlogq_f16(val)));
|
||||
}
|
||||
|
||||
#define INV_NEWTON_INIT_F16 0x7773
|
||||
|
||||
__STATIC_INLINE f16x8_t vrecip_f16(f16x8_t vecIn)
|
||||
{
|
||||
f16x8_t vecSx, vecW, vecTmp;
|
||||
any16x8_t v;
|
||||
|
||||
vecSx = vabsq(vecIn);
|
||||
|
||||
v.f = vecIn;
|
||||
v.i = vsubq(vdupq_n_s16(INV_NEWTON_INIT_F16), v.i);
|
||||
|
||||
vecW = vmulq(vecSx, v.f);
|
||||
|
||||
// v.f = v.f * (8 + w * (-28 + w * (56 + w * (-70 + w *(56 + w * (-28 + w * (8 - w)))))));
|
||||
vecTmp = vsubq(vdupq_n_f16(8.0f16), vecW);
|
||||
vecTmp = vfmasq_n_f16(vecW, vecTmp, -28.0f16);
|
||||
vecTmp = vfmasq_n_f16(vecW, vecTmp, 56.0f16);
|
||||
vecTmp = vfmasq_n_f16(vecW, vecTmp, -70.0f16);
|
||||
vecTmp = vfmasq_n_f16(vecW, vecTmp, 56.0f16);
|
||||
vecTmp = vfmasq_n_f16(vecW, vecTmp, -28.0f16);
|
||||
vecTmp = vfmasq_n_f16(vecW, vecTmp, 8.0f16);
|
||||
v.f = vmulq(v.f, vecTmp);
|
||||
|
||||
v.f = vdupq_m_n_f16(v.f, F16INFINITY, vcmpeqq_n_f16(vecIn, 0.0f));
|
||||
/*
|
||||
* restore sign
|
||||
*/
|
||||
v.f = vnegq_m(v.f, v.f, vcmpltq_n_f16(vecIn, 0.0f));
|
||||
return v.f;
|
||||
}
|
||||
|
||||
__STATIC_INLINE f16x8_t vtanhq_f16(
|
||||
f16x8_t val)
|
||||
{
|
||||
f16x8_t x =
|
||||
vminnmq_f16(vmaxnmq_f16(val, vdupq_n_f16(-10.f16)), vdupq_n_f16(10.0f16));
|
||||
f16x8_t exp2x = vexpq_f16(vmulq_n_f16(x, 2.f16));
|
||||
f16x8_t num = vsubq_n_f16(exp2x, 1.f16);
|
||||
f16x8_t den = vaddq_n_f16(exp2x, 1.f16);
|
||||
f16x8_t tanh = vmulq_f16(num, vrecip_f16(den));
|
||||
return tanh;
|
||||
}
|
||||
|
||||
#endif /* defined(ARM_MATH_MVE_FLOAT16) && !defined(ARM_MATH_AUTOVECTORIZE)*/
|
||||
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* ARM FLOAT16 SUPPORTED */
|
||||
|
||||
#endif /* _ARM_VEC_MATH_F16_H */
|
||||
|
||||
/**
|
||||
*
|
||||
* End of file.
|
||||
*/
|
||||
|
|
@ -0,0 +1,888 @@
|
|||
/**************************************************************************//**
|
||||
* @file cmsis_armcc.h
|
||||
* @brief CMSIS compiler ARMCC (Arm Compiler 5) header file
|
||||
* @version V5.3.2
|
||||
* @date 27. May 2021
|
||||
******************************************************************************/
|
||||
/*
|
||||
* Copyright (c) 2009-2021 Arm Limited. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
#ifndef __CMSIS_ARMCC_H
|
||||
#define __CMSIS_ARMCC_H
|
||||
|
||||
|
||||
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 400677)
|
||||
#error "Please use Arm Compiler Toolchain V4.0.677 or later!"
|
||||
#endif
|
||||
|
||||
/* CMSIS compiler control architecture macros */
|
||||
#if ((defined (__TARGET_ARCH_6_M ) && (__TARGET_ARCH_6_M == 1)) || \
|
||||
(defined (__TARGET_ARCH_6S_M ) && (__TARGET_ARCH_6S_M == 1)) )
|
||||
#define __ARM_ARCH_6M__ 1
|
||||
#endif
|
||||
|
||||
#if (defined (__TARGET_ARCH_7_M ) && (__TARGET_ARCH_7_M == 1))
|
||||
#define __ARM_ARCH_7M__ 1
|
||||
#endif
|
||||
|
||||
#if (defined (__TARGET_ARCH_7E_M) && (__TARGET_ARCH_7E_M == 1))
|
||||
#define __ARM_ARCH_7EM__ 1
|
||||
#endif
|
||||
|
||||
/* __ARM_ARCH_8M_BASE__ not applicable */
|
||||
/* __ARM_ARCH_8M_MAIN__ not applicable */
|
||||
/* __ARM_ARCH_8_1M_MAIN__ not applicable */
|
||||
|
||||
/* CMSIS compiler control DSP macros */
|
||||
#if ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) )
|
||||
#define __ARM_FEATURE_DSP 1
|
||||
#endif
|
||||
|
||||
/* CMSIS compiler specific defines */
|
||||
#ifndef __ASM
|
||||
#define __ASM __asm
|
||||
#endif
|
||||
#ifndef __INLINE
|
||||
#define __INLINE __inline
|
||||
#endif
|
||||
#ifndef __STATIC_INLINE
|
||||
#define __STATIC_INLINE static __inline
|
||||
#endif
|
||||
#ifndef __STATIC_FORCEINLINE
|
||||
#define __STATIC_FORCEINLINE static __forceinline
|
||||
#endif
|
||||
#ifndef __NO_RETURN
|
||||
#define __NO_RETURN __declspec(noreturn)
|
||||
#endif
|
||||
#ifndef __USED
|
||||
#define __USED __attribute__((used))
|
||||
#endif
|
||||
#ifndef __WEAK
|
||||
#define __WEAK __attribute__((weak))
|
||||
#endif
|
||||
#ifndef __PACKED
|
||||
#define __PACKED __attribute__((packed))
|
||||
#endif
|
||||
#ifndef __PACKED_STRUCT
|
||||
#define __PACKED_STRUCT __packed struct
|
||||
#endif
|
||||
#ifndef __PACKED_UNION
|
||||
#define __PACKED_UNION __packed union
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT32 /* deprecated */
|
||||
#define __UNALIGNED_UINT32(x) (*((__packed uint32_t *)(x)))
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT16_WRITE
|
||||
#define __UNALIGNED_UINT16_WRITE(addr, val) ((*((__packed uint16_t *)(addr))) = (val))
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT16_READ
|
||||
#define __UNALIGNED_UINT16_READ(addr) (*((const __packed uint16_t *)(addr)))
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT32_WRITE
|
||||
#define __UNALIGNED_UINT32_WRITE(addr, val) ((*((__packed uint32_t *)(addr))) = (val))
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT32_READ
|
||||
#define __UNALIGNED_UINT32_READ(addr) (*((const __packed uint32_t *)(addr)))
|
||||
#endif
|
||||
#ifndef __ALIGNED
|
||||
#define __ALIGNED(x) __attribute__((aligned(x)))
|
||||
#endif
|
||||
#ifndef __RESTRICT
|
||||
#define __RESTRICT __restrict
|
||||
#endif
|
||||
#ifndef __COMPILER_BARRIER
|
||||
#define __COMPILER_BARRIER() __memory_changed()
|
||||
#endif
|
||||
|
||||
/* ######################### Startup and Lowlevel Init ######################## */
|
||||
|
||||
#ifndef __PROGRAM_START
|
||||
#define __PROGRAM_START __main
|
||||
#endif
|
||||
|
||||
#ifndef __INITIAL_SP
|
||||
#define __INITIAL_SP Image$$ARM_LIB_STACK$$ZI$$Limit
|
||||
#endif
|
||||
|
||||
#ifndef __STACK_LIMIT
|
||||
#define __STACK_LIMIT Image$$ARM_LIB_STACK$$ZI$$Base
|
||||
#endif
|
||||
|
||||
#ifndef __VECTOR_TABLE
|
||||
#define __VECTOR_TABLE __Vectors
|
||||
#endif
|
||||
|
||||
#ifndef __VECTOR_TABLE_ATTRIBUTE
|
||||
#define __VECTOR_TABLE_ATTRIBUTE __attribute__((used, section("RESET")))
|
||||
#endif
|
||||
|
||||
/* ########################## Core Instruction Access ######################### */
|
||||
/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
|
||||
Access to dedicated instructions
|
||||
@{
|
||||
*/
|
||||
|
||||
/**
|
||||
\brief No Operation
|
||||
\details No Operation does nothing. This instruction can be used for code alignment purposes.
|
||||
*/
|
||||
#define __NOP __nop
|
||||
|
||||
|
||||
/**
|
||||
\brief Wait For Interrupt
|
||||
\details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs.
|
||||
*/
|
||||
#define __WFI __wfi
|
||||
|
||||
|
||||
/**
|
||||
\brief Wait For Event
|
||||
\details Wait For Event is a hint instruction that permits the processor to enter
|
||||
a low-power state until one of a number of events occurs.
|
||||
*/
|
||||
#define __WFE __wfe
|
||||
|
||||
|
||||
/**
|
||||
\brief Send Event
|
||||
\details Send Event is a hint instruction. It causes an event to be signaled to the CPU.
|
||||
*/
|
||||
#define __SEV __sev
|
||||
|
||||
|
||||
/**
|
||||
\brief Instruction Synchronization Barrier
|
||||
\details Instruction Synchronization Barrier flushes the pipeline in the processor,
|
||||
so that all instructions following the ISB are fetched from cache or memory,
|
||||
after the instruction has been completed.
|
||||
*/
|
||||
#define __ISB() __isb(0xF)
|
||||
|
||||
/**
|
||||
\brief Data Synchronization Barrier
|
||||
\details Acts as a special kind of Data Memory Barrier.
|
||||
It completes when all explicit memory accesses before this instruction complete.
|
||||
*/
|
||||
#define __DSB() __dsb(0xF)
|
||||
|
||||
/**
|
||||
\brief Data Memory Barrier
|
||||
\details Ensures the apparent order of the explicit memory operations before
|
||||
and after the instruction, without ensuring their completion.
|
||||
*/
|
||||
#define __DMB() __dmb(0xF)
|
||||
|
||||
|
||||
/**
|
||||
\brief Reverse byte order (32 bit)
|
||||
\details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412.
|
||||
\param [in] value Value to reverse
|
||||
\return Reversed value
|
||||
*/
|
||||
#define __REV __rev
|
||||
|
||||
|
||||
/**
|
||||
\brief Reverse byte order (16 bit)
|
||||
\details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856.
|
||||
\param [in] value Value to reverse
|
||||
\return Reversed value
|
||||
*/
|
||||
#ifndef __NO_EMBEDDED_ASM
|
||||
__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value)
|
||||
{
|
||||
rev16 r0, r0
|
||||
bx lr
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
/**
|
||||
\brief Reverse byte order (16 bit)
|
||||
\details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000.
|
||||
\param [in] value Value to reverse
|
||||
\return Reversed value
|
||||
*/
|
||||
#ifndef __NO_EMBEDDED_ASM
|
||||
__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int16_t __REVSH(int16_t value)
|
||||
{
|
||||
revsh r0, r0
|
||||
bx lr
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
/**
|
||||
\brief Rotate Right in unsigned value (32 bit)
|
||||
\details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
|
||||
\param [in] op1 Value to rotate
|
||||
\param [in] op2 Number of Bits to rotate
|
||||
\return Rotated value
|
||||
*/
|
||||
#define __ROR __ror
|
||||
|
||||
|
||||
/**
|
||||
\brief Breakpoint
|
||||
\details Causes the processor to enter Debug state.
|
||||
Debug tools can use this to investigate system state when the instruction at a particular address is reached.
|
||||
\param [in] value is ignored by the processor.
|
||||
If required, a debugger can use it to store additional information about the breakpoint.
|
||||
*/
|
||||
#define __BKPT(value) __breakpoint(value)
|
||||
|
||||
|
||||
/**
|
||||
\brief Reverse bit order of value
|
||||
\details Reverses the bit order of the given value.
|
||||
\param [in] value Value to reverse
|
||||
\return Reversed value
|
||||
*/
|
||||
#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
|
||||
(defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) )
|
||||
#define __RBIT __rbit
|
||||
#else
|
||||
__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
|
||||
{
|
||||
uint32_t result;
|
||||
uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */
|
||||
|
||||
result = value; /* r will be reversed bits of v; first get LSB of v */
|
||||
for (value >>= 1U; value != 0U; value >>= 1U)
|
||||
{
|
||||
result <<= 1U;
|
||||
result |= value & 1U;
|
||||
s--;
|
||||
}
|
||||
result <<= s; /* shift when v's highest bits are zero */
|
||||
return result;
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
/**
|
||||
\brief Count leading zeros
|
||||
\details Counts the number of leading zeros of a data value.
|
||||
\param [in] value Value to count the leading zeros
|
||||
\return number of leading zeros in value
|
||||
*/
|
||||
#define __CLZ __clz
|
||||
|
||||
|
||||
#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
|
||||
(defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) )
|
||||
|
||||
/**
|
||||
\brief LDR Exclusive (8 bit)
|
||||
\details Executes a exclusive LDR instruction for 8 bit value.
|
||||
\param [in] ptr Pointer to data
|
||||
\return value of type uint8_t at (*ptr)
|
||||
*/
|
||||
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
|
||||
#define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr))
|
||||
#else
|
||||
#define __LDREXB(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint8_t ) __ldrex(ptr)) _Pragma("pop")
|
||||
#endif
|
||||
|
||||
|
||||
/**
|
||||
\brief LDR Exclusive (16 bit)
|
||||
\details Executes a exclusive LDR instruction for 16 bit values.
|
||||
\param [in] ptr Pointer to data
|
||||
\return value of type uint16_t at (*ptr)
|
||||
*/
|
||||
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
|
||||
#define __LDREXH(ptr) ((uint16_t) __ldrex(ptr))
|
||||
#else
|
||||
#define __LDREXH(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint16_t) __ldrex(ptr)) _Pragma("pop")
|
||||
#endif
|
||||
|
||||
|
||||
/**
|
||||
\brief LDR Exclusive (32 bit)
|
||||
\details Executes a exclusive LDR instruction for 32 bit values.
|
||||
\param [in] ptr Pointer to data
|
||||
\return value of type uint32_t at (*ptr)
|
||||
*/
|
||||
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
|
||||
#define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr))
|
||||
#else
|
||||
#define __LDREXW(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint32_t ) __ldrex(ptr)) _Pragma("pop")
|
||||
#endif
|
||||
|
||||
|
||||
/**
|
||||
\brief STR Exclusive (8 bit)
|
||||
\details Executes a exclusive STR instruction for 8 bit values.
|
||||
\param [in] value Value to store
|
||||
\param [in] ptr Pointer to location
|
||||
\return 0 Function succeeded
|
||||
\return 1 Function failed
|
||||
*/
|
||||
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
|
||||
#define __STREXB(value, ptr) __strex(value, ptr)
|
||||
#else
|
||||
#define __STREXB(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop")
|
||||
#endif
|
||||
|
||||
|
||||
/**
|
||||
\brief STR Exclusive (16 bit)
|
||||
\details Executes a exclusive STR instruction for 16 bit values.
|
||||
\param [in] value Value to store
|
||||
\param [in] ptr Pointer to location
|
||||
\return 0 Function succeeded
|
||||
\return 1 Function failed
|
||||
*/
|
||||
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
|
||||
#define __STREXH(value, ptr) __strex(value, ptr)
|
||||
#else
|
||||
#define __STREXH(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop")
|
||||
#endif
|
||||
|
||||
|
||||
/**
|
||||
\brief STR Exclusive (32 bit)
|
||||
\details Executes a exclusive STR instruction for 32 bit values.
|
||||
\param [in] value Value to store
|
||||
\param [in] ptr Pointer to location
|
||||
\return 0 Function succeeded
|
||||
\return 1 Function failed
|
||||
*/
|
||||
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
|
||||
#define __STREXW(value, ptr) __strex(value, ptr)
|
||||
#else
|
||||
#define __STREXW(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop")
|
||||
#endif
|
||||
|
||||
|
||||
/**
|
||||
\brief Remove the exclusive lock
|
||||
\details Removes the exclusive lock which is created by LDREX.
|
||||
*/
|
||||
#define __CLREX __clrex
|
||||
|
||||
|
||||
/**
|
||||
\brief Signed Saturate
|
||||
\details Saturates a signed value.
|
||||
\param [in] value Value to be saturated
|
||||
\param [in] sat Bit position to saturate to (1..32)
|
||||
\return Saturated value
|
||||
*/
|
||||
#define __SSAT __ssat
|
||||
|
||||
|
||||
/**
|
||||
\brief Unsigned Saturate
|
||||
\details Saturates an unsigned value.
|
||||
\param [in] value Value to be saturated
|
||||
\param [in] sat Bit position to saturate to (0..31)
|
||||
\return Saturated value
|
||||
*/
|
||||
#define __USAT __usat
|
||||
|
||||
|
||||
/**
|
||||
\brief Rotate Right with Extend (32 bit)
|
||||
\details Moves each bit of a bitstring right by one bit.
|
||||
The carry input is shifted in at the left end of the bitstring.
|
||||
\param [in] value Value to rotate
|
||||
\return Rotated value
|
||||
*/
|
||||
#ifndef __NO_EMBEDDED_ASM
|
||||
__attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint32_t value)
|
||||
{
|
||||
rrx r0, r0
|
||||
bx lr
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
/**
|
||||
\brief LDRT Unprivileged (8 bit)
|
||||
\details Executes a Unprivileged LDRT instruction for 8 bit value.
|
||||
\param [in] ptr Pointer to data
|
||||
\return value of type uint8_t at (*ptr)
|
||||
*/
|
||||
#define __LDRBT(ptr) ((uint8_t ) __ldrt(ptr))
|
||||
|
||||
|
||||
/**
|
||||
\brief LDRT Unprivileged (16 bit)
|
||||
\details Executes a Unprivileged LDRT instruction for 16 bit values.
|
||||
\param [in] ptr Pointer to data
|
||||
\return value of type uint16_t at (*ptr)
|
||||
*/
|
||||
#define __LDRHT(ptr) ((uint16_t) __ldrt(ptr))
|
||||
|
||||
|
||||
/**
|
||||
\brief LDRT Unprivileged (32 bit)
|
||||
\details Executes a Unprivileged LDRT instruction for 32 bit values.
|
||||
\param [in] ptr Pointer to data
|
||||
\return value of type uint32_t at (*ptr)
|
||||
*/
|
||||
#define __LDRT(ptr) ((uint32_t ) __ldrt(ptr))
|
||||
|
||||
|
||||
/**
|
||||
\brief STRT Unprivileged (8 bit)
|
||||
\details Executes a Unprivileged STRT instruction for 8 bit values.
|
||||
\param [in] value Value to store
|
||||
\param [in] ptr Pointer to location
|
||||
*/
|
||||
#define __STRBT(value, ptr) __strt(value, ptr)
|
||||
|
||||
|
||||
/**
|
||||
\brief STRT Unprivileged (16 bit)
|
||||
\details Executes a Unprivileged STRT instruction for 16 bit values.
|
||||
\param [in] value Value to store
|
||||
\param [in] ptr Pointer to location
|
||||
*/
|
||||
#define __STRHT(value, ptr) __strt(value, ptr)
|
||||
|
||||
|
||||
/**
|
||||
\brief STRT Unprivileged (32 bit)
|
||||
\details Executes a Unprivileged STRT instruction for 32 bit values.
|
||||
\param [in] value Value to store
|
||||
\param [in] ptr Pointer to location
|
||||
*/
|
||||
#define __STRT(value, ptr) __strt(value, ptr)
|
||||
|
||||
#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
|
||||
(defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */
|
||||
|
||||
/**
|
||||
\brief Signed Saturate
|
||||
\details Saturates a signed value.
|
||||
\param [in] value Value to be saturated
|
||||
\param [in] sat Bit position to saturate to (1..32)
|
||||
\return Saturated value
|
||||
*/
|
||||
__attribute__((always_inline)) __STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat)
|
||||
{
|
||||
if ((sat >= 1U) && (sat <= 32U))
|
||||
{
|
||||
const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U);
|
||||
const int32_t min = -1 - max ;
|
||||
if (val > max)
|
||||
{
|
||||
return max;
|
||||
}
|
||||
else if (val < min)
|
||||
{
|
||||
return min;
|
||||
}
|
||||
}
|
||||
return val;
|
||||
}
|
||||
|
||||
/**
|
||||
\brief Unsigned Saturate
|
||||
\details Saturates an unsigned value.
|
||||
\param [in] value Value to be saturated
|
||||
\param [in] sat Bit position to saturate to (0..31)
|
||||
\return Saturated value
|
||||
*/
|
||||
__attribute__((always_inline)) __STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat)
|
||||
{
|
||||
if (sat <= 31U)
|
||||
{
|
||||
const uint32_t max = ((1U << sat) - 1U);
|
||||
if (val > (int32_t)max)
|
||||
{
|
||||
return max;
|
||||
}
|
||||
else if (val < 0)
|
||||
{
|
||||
return 0U;
|
||||
}
|
||||
}
|
||||
return (uint32_t)val;
|
||||
}
|
||||
|
||||
#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
|
||||
(defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */
|
||||
|
||||
/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
|
||||
|
||||
|
||||
/* ########################### Core Function Access ########################### */
|
||||
/** \ingroup CMSIS_Core_FunctionInterface
|
||||
\defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
|
||||
@{
|
||||
*/
|
||||
|
||||
/**
|
||||
\brief Enable IRQ Interrupts
|
||||
\details Enables IRQ interrupts by clearing special-purpose register PRIMASK.
|
||||
Can only be executed in Privileged modes.
|
||||
*/
|
||||
/* intrinsic void __enable_irq(); */
|
||||
|
||||
|
||||
/**
|
||||
\brief Disable IRQ Interrupts
|
||||
\details Disables IRQ interrupts by setting special-purpose register PRIMASK.
|
||||
Can only be executed in Privileged modes.
|
||||
*/
|
||||
/* intrinsic void __disable_irq(); */
|
||||
|
||||
/**
|
||||
\brief Get Control Register
|
||||
\details Returns the content of the Control Register.
|
||||
\return Control Register value
|
||||
*/
|
||||
__STATIC_INLINE uint32_t __get_CONTROL(void)
|
||||
{
|
||||
register uint32_t __regControl __ASM("control");
|
||||
return(__regControl);
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Set Control Register
|
||||
\details Writes the given value to the Control Register.
|
||||
\param [in] control Control Register value to set
|
||||
*/
|
||||
__STATIC_INLINE void __set_CONTROL(uint32_t control)
|
||||
{
|
||||
register uint32_t __regControl __ASM("control");
|
||||
__regControl = control;
|
||||
__ISB();
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Get IPSR Register
|
||||
\details Returns the content of the IPSR Register.
|
||||
\return IPSR Register value
|
||||
*/
|
||||
__STATIC_INLINE uint32_t __get_IPSR(void)
|
||||
{
|
||||
register uint32_t __regIPSR __ASM("ipsr");
|
||||
return(__regIPSR);
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Get APSR Register
|
||||
\details Returns the content of the APSR Register.
|
||||
\return APSR Register value
|
||||
*/
|
||||
__STATIC_INLINE uint32_t __get_APSR(void)
|
||||
{
|
||||
register uint32_t __regAPSR __ASM("apsr");
|
||||
return(__regAPSR);
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Get xPSR Register
|
||||
\details Returns the content of the xPSR Register.
|
||||
\return xPSR Register value
|
||||
*/
|
||||
__STATIC_INLINE uint32_t __get_xPSR(void)
|
||||
{
|
||||
register uint32_t __regXPSR __ASM("xpsr");
|
||||
return(__regXPSR);
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Get Process Stack Pointer
|
||||
\details Returns the current value of the Process Stack Pointer (PSP).
|
||||
\return PSP Register value
|
||||
*/
|
||||
__STATIC_INLINE uint32_t __get_PSP(void)
|
||||
{
|
||||
register uint32_t __regProcessStackPointer __ASM("psp");
|
||||
return(__regProcessStackPointer);
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Set Process Stack Pointer
|
||||
\details Assigns the given value to the Process Stack Pointer (PSP).
|
||||
\param [in] topOfProcStack Process Stack Pointer value to set
|
||||
*/
|
||||
__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
|
||||
{
|
||||
register uint32_t __regProcessStackPointer __ASM("psp");
|
||||
__regProcessStackPointer = topOfProcStack;
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Get Main Stack Pointer
|
||||
\details Returns the current value of the Main Stack Pointer (MSP).
|
||||
\return MSP Register value
|
||||
*/
|
||||
__STATIC_INLINE uint32_t __get_MSP(void)
|
||||
{
|
||||
register uint32_t __regMainStackPointer __ASM("msp");
|
||||
return(__regMainStackPointer);
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Set Main Stack Pointer
|
||||
\details Assigns the given value to the Main Stack Pointer (MSP).
|
||||
\param [in] topOfMainStack Main Stack Pointer value to set
|
||||
*/
|
||||
__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
|
||||
{
|
||||
register uint32_t __regMainStackPointer __ASM("msp");
|
||||
__regMainStackPointer = topOfMainStack;
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Get Priority Mask
|
||||
\details Returns the current state of the priority mask bit from the Priority Mask Register.
|
||||
\return Priority Mask value
|
||||
*/
|
||||
__STATIC_INLINE uint32_t __get_PRIMASK(void)
|
||||
{
|
||||
register uint32_t __regPriMask __ASM("primask");
|
||||
return(__regPriMask);
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Set Priority Mask
|
||||
\details Assigns the given value to the Priority Mask Register.
|
||||
\param [in] priMask Priority Mask
|
||||
*/
|
||||
__STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
|
||||
{
|
||||
register uint32_t __regPriMask __ASM("primask");
|
||||
__regPriMask = (priMask);
|
||||
}
|
||||
|
||||
|
||||
#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
|
||||
(defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) )
|
||||
|
||||
/**
|
||||
\brief Enable FIQ
|
||||
\details Enables FIQ interrupts by clearing special-purpose register FAULTMASK.
|
||||
Can only be executed in Privileged modes.
|
||||
*/
|
||||
#define __enable_fault_irq __enable_fiq
|
||||
|
||||
|
||||
/**
|
||||
\brief Disable FIQ
|
||||
\details Disables FIQ interrupts by setting special-purpose register FAULTMASK.
|
||||
Can only be executed in Privileged modes.
|
||||
*/
|
||||
#define __disable_fault_irq __disable_fiq
|
||||
|
||||
|
||||
/**
|
||||
\brief Get Base Priority
|
||||
\details Returns the current value of the Base Priority register.
|
||||
\return Base Priority register value
|
||||
*/
|
||||
__STATIC_INLINE uint32_t __get_BASEPRI(void)
|
||||
{
|
||||
register uint32_t __regBasePri __ASM("basepri");
|
||||
return(__regBasePri);
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Set Base Priority
|
||||
\details Assigns the given value to the Base Priority register.
|
||||
\param [in] basePri Base Priority value to set
|
||||
*/
|
||||
__STATIC_INLINE void __set_BASEPRI(uint32_t basePri)
|
||||
{
|
||||
register uint32_t __regBasePri __ASM("basepri");
|
||||
__regBasePri = (basePri & 0xFFU);
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Set Base Priority with condition
|
||||
\details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled,
|
||||
or the new value increases the BASEPRI priority level.
|
||||
\param [in] basePri Base Priority value to set
|
||||
*/
|
||||
__STATIC_INLINE void __set_BASEPRI_MAX(uint32_t basePri)
|
||||
{
|
||||
register uint32_t __regBasePriMax __ASM("basepri_max");
|
||||
__regBasePriMax = (basePri & 0xFFU);
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Get Fault Mask
|
||||
\details Returns the current value of the Fault Mask register.
|
||||
\return Fault Mask register value
|
||||
*/
|
||||
__STATIC_INLINE uint32_t __get_FAULTMASK(void)
|
||||
{
|
||||
register uint32_t __regFaultMask __ASM("faultmask");
|
||||
return(__regFaultMask);
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Set Fault Mask
|
||||
\details Assigns the given value to the Fault Mask register.
|
||||
\param [in] faultMask Fault Mask value to set
|
||||
*/
|
||||
__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
|
||||
{
|
||||
register uint32_t __regFaultMask __ASM("faultmask");
|
||||
__regFaultMask = (faultMask & (uint32_t)1U);
|
||||
}
|
||||
|
||||
#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
|
||||
(defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */
|
||||
|
||||
|
||||
/**
|
||||
\brief Get FPSCR
|
||||
\details Returns the current value of the Floating Point Status/Control register.
|
||||
\return Floating Point Status/Control register value
|
||||
*/
|
||||
__STATIC_INLINE uint32_t __get_FPSCR(void)
|
||||
{
|
||||
#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
|
||||
(defined (__FPU_USED ) && (__FPU_USED == 1U)) )
|
||||
register uint32_t __regfpscr __ASM("fpscr");
|
||||
return(__regfpscr);
|
||||
#else
|
||||
return(0U);
|
||||
#endif
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Set FPSCR
|
||||
\details Assigns the given value to the Floating Point Status/Control register.
|
||||
\param [in] fpscr Floating Point Status/Control value to set
|
||||
*/
|
||||
__STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
|
||||
{
|
||||
#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
|
||||
(defined (__FPU_USED ) && (__FPU_USED == 1U)) )
|
||||
register uint32_t __regfpscr __ASM("fpscr");
|
||||
__regfpscr = (fpscr);
|
||||
#else
|
||||
(void)fpscr;
|
||||
#endif
|
||||
}
|
||||
|
||||
|
||||
/*@} end of CMSIS_Core_RegAccFunctions */
|
||||
|
||||
|
||||
/* ################### Compiler specific Intrinsics ########################### */
|
||||
/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
|
||||
Access to dedicated SIMD instructions
|
||||
@{
|
||||
*/
|
||||
|
||||
#if ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) )
|
||||
|
||||
#define __SADD8 __sadd8
|
||||
#define __QADD8 __qadd8
|
||||
#define __SHADD8 __shadd8
|
||||
#define __UADD8 __uadd8
|
||||
#define __UQADD8 __uqadd8
|
||||
#define __UHADD8 __uhadd8
|
||||
#define __SSUB8 __ssub8
|
||||
#define __QSUB8 __qsub8
|
||||
#define __SHSUB8 __shsub8
|
||||
#define __USUB8 __usub8
|
||||
#define __UQSUB8 __uqsub8
|
||||
#define __UHSUB8 __uhsub8
|
||||
#define __SADD16 __sadd16
|
||||
#define __QADD16 __qadd16
|
||||
#define __SHADD16 __shadd16
|
||||
#define __UADD16 __uadd16
|
||||
#define __UQADD16 __uqadd16
|
||||
#define __UHADD16 __uhadd16
|
||||
#define __SSUB16 __ssub16
|
||||
#define __QSUB16 __qsub16
|
||||
#define __SHSUB16 __shsub16
|
||||
#define __USUB16 __usub16
|
||||
#define __UQSUB16 __uqsub16
|
||||
#define __UHSUB16 __uhsub16
|
||||
#define __SASX __sasx
|
||||
#define __QASX __qasx
|
||||
#define __SHASX __shasx
|
||||
#define __UASX __uasx
|
||||
#define __UQASX __uqasx
|
||||
#define __UHASX __uhasx
|
||||
#define __SSAX __ssax
|
||||
#define __QSAX __qsax
|
||||
#define __SHSAX __shsax
|
||||
#define __USAX __usax
|
||||
#define __UQSAX __uqsax
|
||||
#define __UHSAX __uhsax
|
||||
#define __USAD8 __usad8
|
||||
#define __USADA8 __usada8
|
||||
#define __SSAT16 __ssat16
|
||||
#define __USAT16 __usat16
|
||||
#define __UXTB16 __uxtb16
|
||||
#define __UXTAB16 __uxtab16
|
||||
#define __SXTB16 __sxtb16
|
||||
#define __SXTAB16 __sxtab16
|
||||
#define __SMUAD __smuad
|
||||
#define __SMUADX __smuadx
|
||||
#define __SMLAD __smlad
|
||||
#define __SMLADX __smladx
|
||||
#define __SMLALD __smlald
|
||||
#define __SMLALDX __smlaldx
|
||||
#define __SMUSD __smusd
|
||||
#define __SMUSDX __smusdx
|
||||
#define __SMLSD __smlsd
|
||||
#define __SMLSDX __smlsdx
|
||||
#define __SMLSLD __smlsld
|
||||
#define __SMLSLDX __smlsldx
|
||||
#define __SEL __sel
|
||||
#define __QADD __qadd
|
||||
#define __QSUB __qsub
|
||||
|
||||
#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \
|
||||
((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) )
|
||||
|
||||
#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \
|
||||
((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) )
|
||||
|
||||
#define __SMMLA(ARG1,ARG2,ARG3) ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \
|
||||
((int64_t)(ARG3) << 32U) ) >> 32U))
|
||||
|
||||
#define __SXTB16_RORn(ARG1, ARG2) __SXTB16(__ROR(ARG1, ARG2))
|
||||
|
||||
#define __SXTAB16_RORn(ARG1, ARG2, ARG3) __SXTAB16(ARG1, __ROR(ARG2, ARG3))
|
||||
|
||||
#endif /* ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */
|
||||
/*@} end of group CMSIS_SIMD_intrinsics */
|
||||
|
||||
|
||||
#endif /* __CMSIS_ARMCC_H */
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,283 @@
|
|||
/**************************************************************************//**
|
||||
* @file cmsis_compiler.h
|
||||
* @brief CMSIS compiler generic header file
|
||||
* @version V5.1.0
|
||||
* @date 09. October 2018
|
||||
******************************************************************************/
|
||||
/*
|
||||
* Copyright (c) 2009-2018 Arm Limited. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
#ifndef __CMSIS_COMPILER_H
|
||||
#define __CMSIS_COMPILER_H
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
/*
|
||||
* Arm Compiler 4/5
|
||||
*/
|
||||
#if defined ( __CC_ARM )
|
||||
#include "cmsis_armcc.h"
|
||||
|
||||
|
||||
/*
|
||||
* Arm Compiler 6.6 LTM (armclang)
|
||||
*/
|
||||
#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) && (__ARMCC_VERSION < 6100100)
|
||||
#include "cmsis_armclang_ltm.h"
|
||||
|
||||
/*
|
||||
* Arm Compiler above 6.10.1 (armclang)
|
||||
*/
|
||||
#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6100100)
|
||||
#include "cmsis_armclang.h"
|
||||
|
||||
|
||||
/*
|
||||
* GNU Compiler
|
||||
*/
|
||||
#elif defined ( __GNUC__ )
|
||||
#include "cmsis_gcc.h"
|
||||
|
||||
|
||||
/*
|
||||
* IAR Compiler
|
||||
*/
|
||||
#elif defined ( __ICCARM__ )
|
||||
#include <cmsis_iccarm.h>
|
||||
|
||||
|
||||
/*
|
||||
* TI Arm Compiler
|
||||
*/
|
||||
#elif defined ( __TI_ARM__ )
|
||||
#include <cmsis_ccs.h>
|
||||
|
||||
#ifndef __ASM
|
||||
#define __ASM __asm
|
||||
#endif
|
||||
#ifndef __INLINE
|
||||
#define __INLINE inline
|
||||
#endif
|
||||
#ifndef __STATIC_INLINE
|
||||
#define __STATIC_INLINE static inline
|
||||
#endif
|
||||
#ifndef __STATIC_FORCEINLINE
|
||||
#define __STATIC_FORCEINLINE __STATIC_INLINE
|
||||
#endif
|
||||
#ifndef __NO_RETURN
|
||||
#define __NO_RETURN __attribute__((noreturn))
|
||||
#endif
|
||||
#ifndef __USED
|
||||
#define __USED __attribute__((used))
|
||||
#endif
|
||||
#ifndef __WEAK
|
||||
#define __WEAK __attribute__((weak))
|
||||
#endif
|
||||
#ifndef __PACKED
|
||||
#define __PACKED __attribute__((packed))
|
||||
#endif
|
||||
#ifndef __PACKED_STRUCT
|
||||
#define __PACKED_STRUCT struct __attribute__((packed))
|
||||
#endif
|
||||
#ifndef __PACKED_UNION
|
||||
#define __PACKED_UNION union __attribute__((packed))
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT32 /* deprecated */
|
||||
struct __attribute__((packed)) T_UINT32 { uint32_t v; };
|
||||
#define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT16_WRITE
|
||||
__PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
|
||||
#define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void*)(addr))->v) = (val))
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT16_READ
|
||||
__PACKED_STRUCT T_UINT16_READ { uint16_t v; };
|
||||
#define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT32_WRITE
|
||||
__PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
|
||||
#define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT32_READ
|
||||
__PACKED_STRUCT T_UINT32_READ { uint32_t v; };
|
||||
#define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
|
||||
#endif
|
||||
#ifndef __ALIGNED
|
||||
#define __ALIGNED(x) __attribute__((aligned(x)))
|
||||
#endif
|
||||
#ifndef __RESTRICT
|
||||
#define __RESTRICT __restrict
|
||||
#endif
|
||||
#ifndef __COMPILER_BARRIER
|
||||
#warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored.
|
||||
#define __COMPILER_BARRIER() (void)0
|
||||
#endif
|
||||
|
||||
|
||||
/*
|
||||
* TASKING Compiler
|
||||
*/
|
||||
#elif defined ( __TASKING__ )
|
||||
/*
|
||||
* The CMSIS functions have been implemented as intrinsics in the compiler.
|
||||
* Please use "carm -?i" to get an up to date list of all intrinsics,
|
||||
* Including the CMSIS ones.
|
||||
*/
|
||||
|
||||
#ifndef __ASM
|
||||
#define __ASM __asm
|
||||
#endif
|
||||
#ifndef __INLINE
|
||||
#define __INLINE inline
|
||||
#endif
|
||||
#ifndef __STATIC_INLINE
|
||||
#define __STATIC_INLINE static inline
|
||||
#endif
|
||||
#ifndef __STATIC_FORCEINLINE
|
||||
#define __STATIC_FORCEINLINE __STATIC_INLINE
|
||||
#endif
|
||||
#ifndef __NO_RETURN
|
||||
#define __NO_RETURN __attribute__((noreturn))
|
||||
#endif
|
||||
#ifndef __USED
|
||||
#define __USED __attribute__((used))
|
||||
#endif
|
||||
#ifndef __WEAK
|
||||
#define __WEAK __attribute__((weak))
|
||||
#endif
|
||||
#ifndef __PACKED
|
||||
#define __PACKED __packed__
|
||||
#endif
|
||||
#ifndef __PACKED_STRUCT
|
||||
#define __PACKED_STRUCT struct __packed__
|
||||
#endif
|
||||
#ifndef __PACKED_UNION
|
||||
#define __PACKED_UNION union __packed__
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT32 /* deprecated */
|
||||
struct __packed__ T_UINT32 { uint32_t v; };
|
||||
#define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT16_WRITE
|
||||
__PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
|
||||
#define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT16_READ
|
||||
__PACKED_STRUCT T_UINT16_READ { uint16_t v; };
|
||||
#define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT32_WRITE
|
||||
__PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
|
||||
#define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT32_READ
|
||||
__PACKED_STRUCT T_UINT32_READ { uint32_t v; };
|
||||
#define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
|
||||
#endif
|
||||
#ifndef __ALIGNED
|
||||
#define __ALIGNED(x) __align(x)
|
||||
#endif
|
||||
#ifndef __RESTRICT
|
||||
#warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
|
||||
#define __RESTRICT
|
||||
#endif
|
||||
#ifndef __COMPILER_BARRIER
|
||||
#warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored.
|
||||
#define __COMPILER_BARRIER() (void)0
|
||||
#endif
|
||||
|
||||
|
||||
/*
|
||||
* COSMIC Compiler
|
||||
*/
|
||||
#elif defined ( __CSMC__ )
|
||||
#include <cmsis_csm.h>
|
||||
|
||||
#ifndef __ASM
|
||||
#define __ASM _asm
|
||||
#endif
|
||||
#ifndef __INLINE
|
||||
#define __INLINE inline
|
||||
#endif
|
||||
#ifndef __STATIC_INLINE
|
||||
#define __STATIC_INLINE static inline
|
||||
#endif
|
||||
#ifndef __STATIC_FORCEINLINE
|
||||
#define __STATIC_FORCEINLINE __STATIC_INLINE
|
||||
#endif
|
||||
#ifndef __NO_RETURN
|
||||
// NO RETURN is automatically detected hence no warning here
|
||||
#define __NO_RETURN
|
||||
#endif
|
||||
#ifndef __USED
|
||||
#warning No compiler specific solution for __USED. __USED is ignored.
|
||||
#define __USED
|
||||
#endif
|
||||
#ifndef __WEAK
|
||||
#define __WEAK __weak
|
||||
#endif
|
||||
#ifndef __PACKED
|
||||
#define __PACKED @packed
|
||||
#endif
|
||||
#ifndef __PACKED_STRUCT
|
||||
#define __PACKED_STRUCT @packed struct
|
||||
#endif
|
||||
#ifndef __PACKED_UNION
|
||||
#define __PACKED_UNION @packed union
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT32 /* deprecated */
|
||||
@packed struct T_UINT32 { uint32_t v; };
|
||||
#define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT16_WRITE
|
||||
__PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
|
||||
#define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT16_READ
|
||||
__PACKED_STRUCT T_UINT16_READ { uint16_t v; };
|
||||
#define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT32_WRITE
|
||||
__PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
|
||||
#define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT32_READ
|
||||
__PACKED_STRUCT T_UINT32_READ { uint32_t v; };
|
||||
#define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
|
||||
#endif
|
||||
#ifndef __ALIGNED
|
||||
#warning No compiler specific solution for __ALIGNED. __ALIGNED is ignored.
|
||||
#define __ALIGNED(x)
|
||||
#endif
|
||||
#ifndef __RESTRICT
|
||||
#warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
|
||||
#define __RESTRICT
|
||||
#endif
|
||||
#ifndef __COMPILER_BARRIER
|
||||
#warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored.
|
||||
#define __COMPILER_BARRIER() (void)0
|
||||
#endif
|
||||
|
||||
|
||||
#else
|
||||
#error Unknown compiler.
|
||||
#endif
|
||||
|
||||
|
||||
#endif /* __CMSIS_COMPILER_H */
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,39 @@
|
|||
/**************************************************************************//**
|
||||
* @file cmsis_version.h
|
||||
* @brief CMSIS Core(M) Version definitions
|
||||
* @version V5.0.5
|
||||
* @date 02. February 2022
|
||||
******************************************************************************/
|
||||
/*
|
||||
* Copyright (c) 2009-2022 ARM Limited. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
#if defined ( __ICCARM__ )
|
||||
#pragma system_include /* treat file as system include file for MISRA check */
|
||||
#elif defined (__clang__)
|
||||
#pragma clang system_header /* treat file as system include file */
|
||||
#endif
|
||||
|
||||
#ifndef __CMSIS_VERSION_H
|
||||
#define __CMSIS_VERSION_H
|
||||
|
||||
/* CMSIS Version definitions */
|
||||
#define __CM_CMSIS_VERSION_MAIN ( 5U) /*!< [31:16] CMSIS Core(M) main version */
|
||||
#define __CM_CMSIS_VERSION_SUB ( 6U) /*!< [15:0] CMSIS Core(M) sub version */
|
||||
#define __CM_CMSIS_VERSION ((__CM_CMSIS_VERSION_MAIN << 16U) | \
|
||||
__CM_CMSIS_VERSION_SUB ) /*!< CMSIS Core(M) version number */
|
||||
#endif
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,275 @@
|
|||
/******************************************************************************
|
||||
* @file mpu_armv7.h
|
||||
* @brief CMSIS MPU API for Armv7-M MPU
|
||||
* @version V5.1.2
|
||||
* @date 25. May 2020
|
||||
******************************************************************************/
|
||||
/*
|
||||
* Copyright (c) 2017-2020 Arm Limited. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
#if defined ( __ICCARM__ )
|
||||
#pragma system_include /* treat file as system include file for MISRA check */
|
||||
#elif defined (__clang__)
|
||||
#pragma clang system_header /* treat file as system include file */
|
||||
#endif
|
||||
|
||||
#ifndef ARM_MPU_ARMV7_H
|
||||
#define ARM_MPU_ARMV7_H
|
||||
|
||||
#define ARM_MPU_REGION_SIZE_32B ((uint8_t)0x04U) ///!< MPU Region Size 32 Bytes
|
||||
#define ARM_MPU_REGION_SIZE_64B ((uint8_t)0x05U) ///!< MPU Region Size 64 Bytes
|
||||
#define ARM_MPU_REGION_SIZE_128B ((uint8_t)0x06U) ///!< MPU Region Size 128 Bytes
|
||||
#define ARM_MPU_REGION_SIZE_256B ((uint8_t)0x07U) ///!< MPU Region Size 256 Bytes
|
||||
#define ARM_MPU_REGION_SIZE_512B ((uint8_t)0x08U) ///!< MPU Region Size 512 Bytes
|
||||
#define ARM_MPU_REGION_SIZE_1KB ((uint8_t)0x09U) ///!< MPU Region Size 1 KByte
|
||||
#define ARM_MPU_REGION_SIZE_2KB ((uint8_t)0x0AU) ///!< MPU Region Size 2 KBytes
|
||||
#define ARM_MPU_REGION_SIZE_4KB ((uint8_t)0x0BU) ///!< MPU Region Size 4 KBytes
|
||||
#define ARM_MPU_REGION_SIZE_8KB ((uint8_t)0x0CU) ///!< MPU Region Size 8 KBytes
|
||||
#define ARM_MPU_REGION_SIZE_16KB ((uint8_t)0x0DU) ///!< MPU Region Size 16 KBytes
|
||||
#define ARM_MPU_REGION_SIZE_32KB ((uint8_t)0x0EU) ///!< MPU Region Size 32 KBytes
|
||||
#define ARM_MPU_REGION_SIZE_64KB ((uint8_t)0x0FU) ///!< MPU Region Size 64 KBytes
|
||||
#define ARM_MPU_REGION_SIZE_128KB ((uint8_t)0x10U) ///!< MPU Region Size 128 KBytes
|
||||
#define ARM_MPU_REGION_SIZE_256KB ((uint8_t)0x11U) ///!< MPU Region Size 256 KBytes
|
||||
#define ARM_MPU_REGION_SIZE_512KB ((uint8_t)0x12U) ///!< MPU Region Size 512 KBytes
|
||||
#define ARM_MPU_REGION_SIZE_1MB ((uint8_t)0x13U) ///!< MPU Region Size 1 MByte
|
||||
#define ARM_MPU_REGION_SIZE_2MB ((uint8_t)0x14U) ///!< MPU Region Size 2 MBytes
|
||||
#define ARM_MPU_REGION_SIZE_4MB ((uint8_t)0x15U) ///!< MPU Region Size 4 MBytes
|
||||
#define ARM_MPU_REGION_SIZE_8MB ((uint8_t)0x16U) ///!< MPU Region Size 8 MBytes
|
||||
#define ARM_MPU_REGION_SIZE_16MB ((uint8_t)0x17U) ///!< MPU Region Size 16 MBytes
|
||||
#define ARM_MPU_REGION_SIZE_32MB ((uint8_t)0x18U) ///!< MPU Region Size 32 MBytes
|
||||
#define ARM_MPU_REGION_SIZE_64MB ((uint8_t)0x19U) ///!< MPU Region Size 64 MBytes
|
||||
#define ARM_MPU_REGION_SIZE_128MB ((uint8_t)0x1AU) ///!< MPU Region Size 128 MBytes
|
||||
#define ARM_MPU_REGION_SIZE_256MB ((uint8_t)0x1BU) ///!< MPU Region Size 256 MBytes
|
||||
#define ARM_MPU_REGION_SIZE_512MB ((uint8_t)0x1CU) ///!< MPU Region Size 512 MBytes
|
||||
#define ARM_MPU_REGION_SIZE_1GB ((uint8_t)0x1DU) ///!< MPU Region Size 1 GByte
|
||||
#define ARM_MPU_REGION_SIZE_2GB ((uint8_t)0x1EU) ///!< MPU Region Size 2 GBytes
|
||||
#define ARM_MPU_REGION_SIZE_4GB ((uint8_t)0x1FU) ///!< MPU Region Size 4 GBytes
|
||||
|
||||
#define ARM_MPU_AP_NONE 0U ///!< MPU Access Permission no access
|
||||
#define ARM_MPU_AP_PRIV 1U ///!< MPU Access Permission privileged access only
|
||||
#define ARM_MPU_AP_URO 2U ///!< MPU Access Permission unprivileged access read-only
|
||||
#define ARM_MPU_AP_FULL 3U ///!< MPU Access Permission full access
|
||||
#define ARM_MPU_AP_PRO 5U ///!< MPU Access Permission privileged access read-only
|
||||
#define ARM_MPU_AP_RO 6U ///!< MPU Access Permission read-only access
|
||||
|
||||
/** MPU Region Base Address Register Value
|
||||
*
|
||||
* \param Region The region to be configured, number 0 to 15.
|
||||
* \param BaseAddress The base address for the region.
|
||||
*/
|
||||
#define ARM_MPU_RBAR(Region, BaseAddress) \
|
||||
(((BaseAddress) & MPU_RBAR_ADDR_Msk) | \
|
||||
((Region) & MPU_RBAR_REGION_Msk) | \
|
||||
(MPU_RBAR_VALID_Msk))
|
||||
|
||||
/**
|
||||
* MPU Memory Access Attributes
|
||||
*
|
||||
* \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral.
|
||||
* \param IsShareable Region is shareable between multiple bus masters.
|
||||
* \param IsCacheable Region is cacheable, i.e. its value may be kept in cache.
|
||||
* \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy.
|
||||
*/
|
||||
#define ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable) \
|
||||
((((TypeExtField) << MPU_RASR_TEX_Pos) & MPU_RASR_TEX_Msk) | \
|
||||
(((IsShareable) << MPU_RASR_S_Pos) & MPU_RASR_S_Msk) | \
|
||||
(((IsCacheable) << MPU_RASR_C_Pos) & MPU_RASR_C_Msk) | \
|
||||
(((IsBufferable) << MPU_RASR_B_Pos) & MPU_RASR_B_Msk))
|
||||
|
||||
/**
|
||||
* MPU Region Attribute and Size Register Value
|
||||
*
|
||||
* \param DisableExec Instruction access disable bit, 1= disable instruction fetches.
|
||||
* \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode.
|
||||
* \param AccessAttributes Memory access attribution, see \ref ARM_MPU_ACCESS_.
|
||||
* \param SubRegionDisable Sub-region disable field.
|
||||
* \param Size Region size of the region to be configured, for example 4K, 8K.
|
||||
*/
|
||||
#define ARM_MPU_RASR_EX(DisableExec, AccessPermission, AccessAttributes, SubRegionDisable, Size) \
|
||||
((((DisableExec) << MPU_RASR_XN_Pos) & MPU_RASR_XN_Msk) | \
|
||||
(((AccessPermission) << MPU_RASR_AP_Pos) & MPU_RASR_AP_Msk) | \
|
||||
(((AccessAttributes) & (MPU_RASR_TEX_Msk | MPU_RASR_S_Msk | MPU_RASR_C_Msk | MPU_RASR_B_Msk))) | \
|
||||
(((SubRegionDisable) << MPU_RASR_SRD_Pos) & MPU_RASR_SRD_Msk) | \
|
||||
(((Size) << MPU_RASR_SIZE_Pos) & MPU_RASR_SIZE_Msk) | \
|
||||
(((MPU_RASR_ENABLE_Msk))))
|
||||
|
||||
/**
|
||||
* MPU Region Attribute and Size Register Value
|
||||
*
|
||||
* \param DisableExec Instruction access disable bit, 1= disable instruction fetches.
|
||||
* \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode.
|
||||
* \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral.
|
||||
* \param IsShareable Region is shareable between multiple bus masters.
|
||||
* \param IsCacheable Region is cacheable, i.e. its value may be kept in cache.
|
||||
* \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy.
|
||||
* \param SubRegionDisable Sub-region disable field.
|
||||
* \param Size Region size of the region to be configured, for example 4K, 8K.
|
||||
*/
|
||||
#define ARM_MPU_RASR(DisableExec, AccessPermission, TypeExtField, IsShareable, IsCacheable, IsBufferable, SubRegionDisable, Size) \
|
||||
ARM_MPU_RASR_EX(DisableExec, AccessPermission, ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable), SubRegionDisable, Size)
|
||||
|
||||
/**
|
||||
* MPU Memory Access Attribute for strongly ordered memory.
|
||||
* - TEX: 000b
|
||||
* - Shareable
|
||||
* - Non-cacheable
|
||||
* - Non-bufferable
|
||||
*/
|
||||
#define ARM_MPU_ACCESS_ORDERED ARM_MPU_ACCESS_(0U, 1U, 0U, 0U)
|
||||
|
||||
/**
|
||||
* MPU Memory Access Attribute for device memory.
|
||||
* - TEX: 000b (if shareable) or 010b (if non-shareable)
|
||||
* - Shareable or non-shareable
|
||||
* - Non-cacheable
|
||||
* - Bufferable (if shareable) or non-bufferable (if non-shareable)
|
||||
*
|
||||
* \param IsShareable Configures the device memory as shareable or non-shareable.
|
||||
*/
|
||||
#define ARM_MPU_ACCESS_DEVICE(IsShareable) ((IsShareable) ? ARM_MPU_ACCESS_(0U, 1U, 0U, 1U) : ARM_MPU_ACCESS_(2U, 0U, 0U, 0U))
|
||||
|
||||
/**
|
||||
* MPU Memory Access Attribute for normal memory.
|
||||
* - TEX: 1BBb (reflecting outer cacheability rules)
|
||||
* - Shareable or non-shareable
|
||||
* - Cacheable or non-cacheable (reflecting inner cacheability rules)
|
||||
* - Bufferable or non-bufferable (reflecting inner cacheability rules)
|
||||
*
|
||||
* \param OuterCp Configures the outer cache policy.
|
||||
* \param InnerCp Configures the inner cache policy.
|
||||
* \param IsShareable Configures the memory as shareable or non-shareable.
|
||||
*/
|
||||
#define ARM_MPU_ACCESS_NORMAL(OuterCp, InnerCp, IsShareable) ARM_MPU_ACCESS_((4U | (OuterCp)), IsShareable, ((InnerCp) >> 1U), ((InnerCp) & 1U))
|
||||
|
||||
/**
|
||||
* MPU Memory Access Attribute non-cacheable policy.
|
||||
*/
|
||||
#define ARM_MPU_CACHEP_NOCACHE 0U
|
||||
|
||||
/**
|
||||
* MPU Memory Access Attribute write-back, write and read allocate policy.
|
||||
*/
|
||||
#define ARM_MPU_CACHEP_WB_WRA 1U
|
||||
|
||||
/**
|
||||
* MPU Memory Access Attribute write-through, no write allocate policy.
|
||||
*/
|
||||
#define ARM_MPU_CACHEP_WT_NWA 2U
|
||||
|
||||
/**
|
||||
* MPU Memory Access Attribute write-back, no write allocate policy.
|
||||
*/
|
||||
#define ARM_MPU_CACHEP_WB_NWA 3U
|
||||
|
||||
|
||||
/**
|
||||
* Struct for a single MPU Region
|
||||
*/
|
||||
typedef struct {
|
||||
uint32_t RBAR; //!< The region base address register value (RBAR)
|
||||
uint32_t RASR; //!< The region attribute and size register value (RASR) \ref MPU_RASR
|
||||
} ARM_MPU_Region_t;
|
||||
|
||||
/** Enable the MPU.
|
||||
* \param MPU_Control Default access permissions for unconfigured regions.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control)
|
||||
{
|
||||
__DMB();
|
||||
MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
|
||||
#ifdef SCB_SHCSR_MEMFAULTENA_Msk
|
||||
SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
|
||||
#endif
|
||||
__DSB();
|
||||
__ISB();
|
||||
}
|
||||
|
||||
/** Disable the MPU.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_Disable(void)
|
||||
{
|
||||
__DMB();
|
||||
#ifdef SCB_SHCSR_MEMFAULTENA_Msk
|
||||
SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
|
||||
#endif
|
||||
MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk;
|
||||
__DSB();
|
||||
__ISB();
|
||||
}
|
||||
|
||||
/** Clear and disable the given MPU region.
|
||||
* \param rnr Region number to be cleared.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr)
|
||||
{
|
||||
MPU->RNR = rnr;
|
||||
MPU->RASR = 0U;
|
||||
}
|
||||
|
||||
/** Configure an MPU region.
|
||||
* \param rbar Value for RBAR register.
|
||||
* \param rasr Value for RASR register.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rbar, uint32_t rasr)
|
||||
{
|
||||
MPU->RBAR = rbar;
|
||||
MPU->RASR = rasr;
|
||||
}
|
||||
|
||||
/** Configure the given MPU region.
|
||||
* \param rnr Region number to be configured.
|
||||
* \param rbar Value for RBAR register.
|
||||
* \param rasr Value for RASR register.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_SetRegionEx(uint32_t rnr, uint32_t rbar, uint32_t rasr)
|
||||
{
|
||||
MPU->RNR = rnr;
|
||||
MPU->RBAR = rbar;
|
||||
MPU->RASR = rasr;
|
||||
}
|
||||
|
||||
/** Memcpy with strictly ordered memory access, e.g. used by code in ARM_MPU_Load().
|
||||
* \param dst Destination data is copied to.
|
||||
* \param src Source data is copied from.
|
||||
* \param len Amount of data words to be copied.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_OrderedMemcpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len)
|
||||
{
|
||||
uint32_t i;
|
||||
for (i = 0U; i < len; ++i)
|
||||
{
|
||||
dst[i] = src[i];
|
||||
}
|
||||
}
|
||||
|
||||
/** Load the given number of MPU regions from a table.
|
||||
* \param table Pointer to the MPU configuration table.
|
||||
* \param cnt Amount of regions to be configured.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_Load(ARM_MPU_Region_t const* table, uint32_t cnt)
|
||||
{
|
||||
const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U;
|
||||
while (cnt > MPU_TYPE_RALIASES) {
|
||||
ARM_MPU_OrderedMemcpy(&(MPU->RBAR), &(table->RBAR), MPU_TYPE_RALIASES*rowWordSize);
|
||||
table += MPU_TYPE_RALIASES;
|
||||
cnt -= MPU_TYPE_RALIASES;
|
||||
}
|
||||
ARM_MPU_OrderedMemcpy(&(MPU->RBAR), &(table->RBAR), cnt*rowWordSize);
|
||||
}
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,352 @@
|
|||
/******************************************************************************
|
||||
* @file mpu_armv8.h
|
||||
* @brief CMSIS MPU API for Armv8-M and Armv8.1-M MPU
|
||||
* @version V5.1.3
|
||||
* @date 03. February 2021
|
||||
******************************************************************************/
|
||||
/*
|
||||
* Copyright (c) 2017-2021 Arm Limited. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
#if defined ( __ICCARM__ )
|
||||
#pragma system_include /* treat file as system include file for MISRA check */
|
||||
#elif defined (__clang__)
|
||||
#pragma clang system_header /* treat file as system include file */
|
||||
#endif
|
||||
|
||||
#ifndef ARM_MPU_ARMV8_H
|
||||
#define ARM_MPU_ARMV8_H
|
||||
|
||||
/** \brief Attribute for device memory (outer only) */
|
||||
#define ARM_MPU_ATTR_DEVICE ( 0U )
|
||||
|
||||
/** \brief Attribute for non-cacheable, normal memory */
|
||||
#define ARM_MPU_ATTR_NON_CACHEABLE ( 4U )
|
||||
|
||||
/** \brief Attribute for normal memory (outer and inner)
|
||||
* \param NT Non-Transient: Set to 1 for non-transient data.
|
||||
* \param WB Write-Back: Set to 1 to use write-back update policy.
|
||||
* \param RA Read Allocation: Set to 1 to use cache allocation on read miss.
|
||||
* \param WA Write Allocation: Set to 1 to use cache allocation on write miss.
|
||||
*/
|
||||
#define ARM_MPU_ATTR_MEMORY_(NT, WB, RA, WA) \
|
||||
((((NT) & 1U) << 3U) | (((WB) & 1U) << 2U) | (((RA) & 1U) << 1U) | ((WA) & 1U))
|
||||
|
||||
/** \brief Device memory type non Gathering, non Re-ordering, non Early Write Acknowledgement */
|
||||
#define ARM_MPU_ATTR_DEVICE_nGnRnE (0U)
|
||||
|
||||
/** \brief Device memory type non Gathering, non Re-ordering, Early Write Acknowledgement */
|
||||
#define ARM_MPU_ATTR_DEVICE_nGnRE (1U)
|
||||
|
||||
/** \brief Device memory type non Gathering, Re-ordering, Early Write Acknowledgement */
|
||||
#define ARM_MPU_ATTR_DEVICE_nGRE (2U)
|
||||
|
||||
/** \brief Device memory type Gathering, Re-ordering, Early Write Acknowledgement */
|
||||
#define ARM_MPU_ATTR_DEVICE_GRE (3U)
|
||||
|
||||
/** \brief Memory Attribute
|
||||
* \param O Outer memory attributes
|
||||
* \param I O == ARM_MPU_ATTR_DEVICE: Device memory attributes, else: Inner memory attributes
|
||||
*/
|
||||
#define ARM_MPU_ATTR(O, I) ((((O) & 0xFU) << 4U) | ((((O) & 0xFU) != 0U) ? ((I) & 0xFU) : (((I) & 0x3U) << 2U)))
|
||||
|
||||
/** \brief Normal memory non-shareable */
|
||||
#define ARM_MPU_SH_NON (0U)
|
||||
|
||||
/** \brief Normal memory outer shareable */
|
||||
#define ARM_MPU_SH_OUTER (2U)
|
||||
|
||||
/** \brief Normal memory inner shareable */
|
||||
#define ARM_MPU_SH_INNER (3U)
|
||||
|
||||
/** \brief Memory access permissions
|
||||
* \param RO Read-Only: Set to 1 for read-only memory.
|
||||
* \param NP Non-Privileged: Set to 1 for non-privileged memory.
|
||||
*/
|
||||
#define ARM_MPU_AP_(RO, NP) ((((RO) & 1U) << 1U) | ((NP) & 1U))
|
||||
|
||||
/** \brief Region Base Address Register value
|
||||
* \param BASE The base address bits [31:5] of a memory region. The value is zero extended. Effective address gets 32 byte aligned.
|
||||
* \param SH Defines the Shareability domain for this memory region.
|
||||
* \param RO Read-Only: Set to 1 for a read-only memory region.
|
||||
* \param NP Non-Privileged: Set to 1 for a non-privileged memory region.
|
||||
* \oaram XN eXecute Never: Set to 1 for a non-executable memory region.
|
||||
*/
|
||||
#define ARM_MPU_RBAR(BASE, SH, RO, NP, XN) \
|
||||
(((BASE) & MPU_RBAR_BASE_Msk) | \
|
||||
(((SH) << MPU_RBAR_SH_Pos) & MPU_RBAR_SH_Msk) | \
|
||||
((ARM_MPU_AP_(RO, NP) << MPU_RBAR_AP_Pos) & MPU_RBAR_AP_Msk) | \
|
||||
(((XN) << MPU_RBAR_XN_Pos) & MPU_RBAR_XN_Msk))
|
||||
|
||||
/** \brief Region Limit Address Register value
|
||||
* \param LIMIT The limit address bits [31:5] for this memory region. The value is one extended.
|
||||
* \param IDX The attribute index to be associated with this memory region.
|
||||
*/
|
||||
#define ARM_MPU_RLAR(LIMIT, IDX) \
|
||||
(((LIMIT) & MPU_RLAR_LIMIT_Msk) | \
|
||||
(((IDX) << MPU_RLAR_AttrIndx_Pos) & MPU_RLAR_AttrIndx_Msk) | \
|
||||
(MPU_RLAR_EN_Msk))
|
||||
|
||||
#if defined(MPU_RLAR_PXN_Pos)
|
||||
|
||||
/** \brief Region Limit Address Register with PXN value
|
||||
* \param LIMIT The limit address bits [31:5] for this memory region. The value is one extended.
|
||||
* \param PXN Privileged execute never. Defines whether code can be executed from this privileged region.
|
||||
* \param IDX The attribute index to be associated with this memory region.
|
||||
*/
|
||||
#define ARM_MPU_RLAR_PXN(LIMIT, PXN, IDX) \
|
||||
(((LIMIT) & MPU_RLAR_LIMIT_Msk) | \
|
||||
(((PXN) << MPU_RLAR_PXN_Pos) & MPU_RLAR_PXN_Msk) | \
|
||||
(((IDX) << MPU_RLAR_AttrIndx_Pos) & MPU_RLAR_AttrIndx_Msk) | \
|
||||
(MPU_RLAR_EN_Msk))
|
||||
|
||||
#endif
|
||||
|
||||
/**
|
||||
* Struct for a single MPU Region
|
||||
*/
|
||||
typedef struct {
|
||||
uint32_t RBAR; /*!< Region Base Address Register value */
|
||||
uint32_t RLAR; /*!< Region Limit Address Register value */
|
||||
} ARM_MPU_Region_t;
|
||||
|
||||
/** Enable the MPU.
|
||||
* \param MPU_Control Default access permissions for unconfigured regions.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control)
|
||||
{
|
||||
__DMB();
|
||||
MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
|
||||
#ifdef SCB_SHCSR_MEMFAULTENA_Msk
|
||||
SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
|
||||
#endif
|
||||
__DSB();
|
||||
__ISB();
|
||||
}
|
||||
|
||||
/** Disable the MPU.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_Disable(void)
|
||||
{
|
||||
__DMB();
|
||||
#ifdef SCB_SHCSR_MEMFAULTENA_Msk
|
||||
SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
|
||||
#endif
|
||||
MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk;
|
||||
__DSB();
|
||||
__ISB();
|
||||
}
|
||||
|
||||
#ifdef MPU_NS
|
||||
/** Enable the Non-secure MPU.
|
||||
* \param MPU_Control Default access permissions for unconfigured regions.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_Enable_NS(uint32_t MPU_Control)
|
||||
{
|
||||
__DMB();
|
||||
MPU_NS->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
|
||||
#ifdef SCB_SHCSR_MEMFAULTENA_Msk
|
||||
SCB_NS->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
|
||||
#endif
|
||||
__DSB();
|
||||
__ISB();
|
||||
}
|
||||
|
||||
/** Disable the Non-secure MPU.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_Disable_NS(void)
|
||||
{
|
||||
__DMB();
|
||||
#ifdef SCB_SHCSR_MEMFAULTENA_Msk
|
||||
SCB_NS->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
|
||||
#endif
|
||||
MPU_NS->CTRL &= ~MPU_CTRL_ENABLE_Msk;
|
||||
__DSB();
|
||||
__ISB();
|
||||
}
|
||||
#endif
|
||||
|
||||
/** Set the memory attribute encoding to the given MPU.
|
||||
* \param mpu Pointer to the MPU to be configured.
|
||||
* \param idx The attribute index to be set [0-7]
|
||||
* \param attr The attribute value to be set.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_SetMemAttrEx(MPU_Type* mpu, uint8_t idx, uint8_t attr)
|
||||
{
|
||||
const uint8_t reg = idx / 4U;
|
||||
const uint32_t pos = ((idx % 4U) * 8U);
|
||||
const uint32_t mask = 0xFFU << pos;
|
||||
|
||||
if (reg >= (sizeof(mpu->MAIR) / sizeof(mpu->MAIR[0]))) {
|
||||
return; // invalid index
|
||||
}
|
||||
|
||||
mpu->MAIR[reg] = ((mpu->MAIR[reg] & ~mask) | ((attr << pos) & mask));
|
||||
}
|
||||
|
||||
/** Set the memory attribute encoding.
|
||||
* \param idx The attribute index to be set [0-7]
|
||||
* \param attr The attribute value to be set.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_SetMemAttr(uint8_t idx, uint8_t attr)
|
||||
{
|
||||
ARM_MPU_SetMemAttrEx(MPU, idx, attr);
|
||||
}
|
||||
|
||||
#ifdef MPU_NS
|
||||
/** Set the memory attribute encoding to the Non-secure MPU.
|
||||
* \param idx The attribute index to be set [0-7]
|
||||
* \param attr The attribute value to be set.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_SetMemAttr_NS(uint8_t idx, uint8_t attr)
|
||||
{
|
||||
ARM_MPU_SetMemAttrEx(MPU_NS, idx, attr);
|
||||
}
|
||||
#endif
|
||||
|
||||
/** Clear and disable the given MPU region of the given MPU.
|
||||
* \param mpu Pointer to MPU to be used.
|
||||
* \param rnr Region number to be cleared.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_ClrRegionEx(MPU_Type* mpu, uint32_t rnr)
|
||||
{
|
||||
mpu->RNR = rnr;
|
||||
mpu->RLAR = 0U;
|
||||
}
|
||||
|
||||
/** Clear and disable the given MPU region.
|
||||
* \param rnr Region number to be cleared.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr)
|
||||
{
|
||||
ARM_MPU_ClrRegionEx(MPU, rnr);
|
||||
}
|
||||
|
||||
#ifdef MPU_NS
|
||||
/** Clear and disable the given Non-secure MPU region.
|
||||
* \param rnr Region number to be cleared.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_ClrRegion_NS(uint32_t rnr)
|
||||
{
|
||||
ARM_MPU_ClrRegionEx(MPU_NS, rnr);
|
||||
}
|
||||
#endif
|
||||
|
||||
/** Configure the given MPU region of the given MPU.
|
||||
* \param mpu Pointer to MPU to be used.
|
||||
* \param rnr Region number to be configured.
|
||||
* \param rbar Value for RBAR register.
|
||||
* \param rlar Value for RLAR register.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_SetRegionEx(MPU_Type* mpu, uint32_t rnr, uint32_t rbar, uint32_t rlar)
|
||||
{
|
||||
mpu->RNR = rnr;
|
||||
mpu->RBAR = rbar;
|
||||
mpu->RLAR = rlar;
|
||||
}
|
||||
|
||||
/** Configure the given MPU region.
|
||||
* \param rnr Region number to be configured.
|
||||
* \param rbar Value for RBAR register.
|
||||
* \param rlar Value for RLAR register.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rnr, uint32_t rbar, uint32_t rlar)
|
||||
{
|
||||
ARM_MPU_SetRegionEx(MPU, rnr, rbar, rlar);
|
||||
}
|
||||
|
||||
#ifdef MPU_NS
|
||||
/** Configure the given Non-secure MPU region.
|
||||
* \param rnr Region number to be configured.
|
||||
* \param rbar Value for RBAR register.
|
||||
* \param rlar Value for RLAR register.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_SetRegion_NS(uint32_t rnr, uint32_t rbar, uint32_t rlar)
|
||||
{
|
||||
ARM_MPU_SetRegionEx(MPU_NS, rnr, rbar, rlar);
|
||||
}
|
||||
#endif
|
||||
|
||||
/** Memcpy with strictly ordered memory access, e.g. used by code in ARM_MPU_LoadEx()
|
||||
* \param dst Destination data is copied to.
|
||||
* \param src Source data is copied from.
|
||||
* \param len Amount of data words to be copied.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_OrderedMemcpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len)
|
||||
{
|
||||
uint32_t i;
|
||||
for (i = 0U; i < len; ++i)
|
||||
{
|
||||
dst[i] = src[i];
|
||||
}
|
||||
}
|
||||
|
||||
/** Load the given number of MPU regions from a table to the given MPU.
|
||||
* \param mpu Pointer to the MPU registers to be used.
|
||||
* \param rnr First region number to be configured.
|
||||
* \param table Pointer to the MPU configuration table.
|
||||
* \param cnt Amount of regions to be configured.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_LoadEx(MPU_Type* mpu, uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt)
|
||||
{
|
||||
const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U;
|
||||
if (cnt == 1U) {
|
||||
mpu->RNR = rnr;
|
||||
ARM_MPU_OrderedMemcpy(&(mpu->RBAR), &(table->RBAR), rowWordSize);
|
||||
} else {
|
||||
uint32_t rnrBase = rnr & ~(MPU_TYPE_RALIASES-1U);
|
||||
uint32_t rnrOffset = rnr % MPU_TYPE_RALIASES;
|
||||
|
||||
mpu->RNR = rnrBase;
|
||||
while ((rnrOffset + cnt) > MPU_TYPE_RALIASES) {
|
||||
uint32_t c = MPU_TYPE_RALIASES - rnrOffset;
|
||||
ARM_MPU_OrderedMemcpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), c*rowWordSize);
|
||||
table += c;
|
||||
cnt -= c;
|
||||
rnrOffset = 0U;
|
||||
rnrBase += MPU_TYPE_RALIASES;
|
||||
mpu->RNR = rnrBase;
|
||||
}
|
||||
|
||||
ARM_MPU_OrderedMemcpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), cnt*rowWordSize);
|
||||
}
|
||||
}
|
||||
|
||||
/** Load the given number of MPU regions from a table.
|
||||
* \param rnr First region number to be configured.
|
||||
* \param table Pointer to the MPU configuration table.
|
||||
* \param cnt Amount of regions to be configured.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_Load(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt)
|
||||
{
|
||||
ARM_MPU_LoadEx(MPU, rnr, table, cnt);
|
||||
}
|
||||
|
||||
#ifdef MPU_NS
|
||||
/** Load the given number of MPU regions from a table to the Non-secure MPU.
|
||||
* \param rnr First region number to be configured.
|
||||
* \param table Pointer to the MPU configuration table.
|
||||
* \param cnt Amount of regions to be configured.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_Load_NS(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt)
|
||||
{
|
||||
ARM_MPU_LoadEx(MPU_NS, rnr, table, cnt);
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
||||
|
|
@ -0,0 +1,337 @@
|
|||
/******************************************************************************
|
||||
* @file pmu_armv8.h
|
||||
* @brief CMSIS PMU API for Armv8.1-M PMU
|
||||
* @version V1.0.1
|
||||
* @date 15. April 2020
|
||||
******************************************************************************/
|
||||
/*
|
||||
* Copyright (c) 2020 Arm Limited. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
#if defined ( __ICCARM__ )
|
||||
#pragma system_include /* treat file as system include file for MISRA check */
|
||||
#elif defined (__clang__)
|
||||
#pragma clang system_header /* treat file as system include file */
|
||||
#endif
|
||||
|
||||
#ifndef ARM_PMU_ARMV8_H
|
||||
#define ARM_PMU_ARMV8_H
|
||||
|
||||
/**
|
||||
* \brief PMU Events
|
||||
* \note See the Armv8.1-M Architecture Reference Manual for full details on these PMU events.
|
||||
* */
|
||||
|
||||
#define ARM_PMU_SW_INCR 0x0000 /*!< Software update to the PMU_SWINC register, architecturally executed and condition code check pass */
|
||||
#define ARM_PMU_L1I_CACHE_REFILL 0x0001 /*!< L1 I-Cache refill */
|
||||
#define ARM_PMU_L1D_CACHE_REFILL 0x0003 /*!< L1 D-Cache refill */
|
||||
#define ARM_PMU_L1D_CACHE 0x0004 /*!< L1 D-Cache access */
|
||||
#define ARM_PMU_LD_RETIRED 0x0006 /*!< Memory-reading instruction architecturally executed and condition code check pass */
|
||||
#define ARM_PMU_ST_RETIRED 0x0007 /*!< Memory-writing instruction architecturally executed and condition code check pass */
|
||||
#define ARM_PMU_INST_RETIRED 0x0008 /*!< Instruction architecturally executed */
|
||||
#define ARM_PMU_EXC_TAKEN 0x0009 /*!< Exception entry */
|
||||
#define ARM_PMU_EXC_RETURN 0x000A /*!< Exception return instruction architecturally executed and the condition code check pass */
|
||||
#define ARM_PMU_PC_WRITE_RETIRED 0x000C /*!< Software change to the Program Counter (PC). Instruction is architecturally executed and condition code check pass */
|
||||
#define ARM_PMU_BR_IMMED_RETIRED 0x000D /*!< Immediate branch architecturally executed */
|
||||
#define ARM_PMU_BR_RETURN_RETIRED 0x000E /*!< Function return instruction architecturally executed and the condition code check pass */
|
||||
#define ARM_PMU_UNALIGNED_LDST_RETIRED 0x000F /*!< Unaligned memory memory-reading or memory-writing instruction architecturally executed and condition code check pass */
|
||||
#define ARM_PMU_BR_MIS_PRED 0x0010 /*!< Mispredicted or not predicted branch speculatively executed */
|
||||
#define ARM_PMU_CPU_CYCLES 0x0011 /*!< Cycle */
|
||||
#define ARM_PMU_BR_PRED 0x0012 /*!< Predictable branch speculatively executed */
|
||||
#define ARM_PMU_MEM_ACCESS 0x0013 /*!< Data memory access */
|
||||
#define ARM_PMU_L1I_CACHE 0x0014 /*!< Level 1 instruction cache access */
|
||||
#define ARM_PMU_L1D_CACHE_WB 0x0015 /*!< Level 1 data cache write-back */
|
||||
#define ARM_PMU_L2D_CACHE 0x0016 /*!< Level 2 data cache access */
|
||||
#define ARM_PMU_L2D_CACHE_REFILL 0x0017 /*!< Level 2 data cache refill */
|
||||
#define ARM_PMU_L2D_CACHE_WB 0x0018 /*!< Level 2 data cache write-back */
|
||||
#define ARM_PMU_BUS_ACCESS 0x0019 /*!< Bus access */
|
||||
#define ARM_PMU_MEMORY_ERROR 0x001A /*!< Local memory error */
|
||||
#define ARM_PMU_INST_SPEC 0x001B /*!< Instruction speculatively executed */
|
||||
#define ARM_PMU_BUS_CYCLES 0x001D /*!< Bus cycles */
|
||||
#define ARM_PMU_CHAIN 0x001E /*!< For an odd numbered counter, increment when an overflow occurs on the preceding even-numbered counter on the same PE */
|
||||
#define ARM_PMU_L1D_CACHE_ALLOCATE 0x001F /*!< Level 1 data cache allocation without refill */
|
||||
#define ARM_PMU_L2D_CACHE_ALLOCATE 0x0020 /*!< Level 2 data cache allocation without refill */
|
||||
#define ARM_PMU_BR_RETIRED 0x0021 /*!< Branch instruction architecturally executed */
|
||||
#define ARM_PMU_BR_MIS_PRED_RETIRED 0x0022 /*!< Mispredicted branch instruction architecturally executed */
|
||||
#define ARM_PMU_STALL_FRONTEND 0x0023 /*!< No operation issued because of the frontend */
|
||||
#define ARM_PMU_STALL_BACKEND 0x0024 /*!< No operation issued because of the backend */
|
||||
#define ARM_PMU_L2I_CACHE 0x0027 /*!< Level 2 instruction cache access */
|
||||
#define ARM_PMU_L2I_CACHE_REFILL 0x0028 /*!< Level 2 instruction cache refill */
|
||||
#define ARM_PMU_L3D_CACHE_ALLOCATE 0x0029 /*!< Level 3 data cache allocation without refill */
|
||||
#define ARM_PMU_L3D_CACHE_REFILL 0x002A /*!< Level 3 data cache refill */
|
||||
#define ARM_PMU_L3D_CACHE 0x002B /*!< Level 3 data cache access */
|
||||
#define ARM_PMU_L3D_CACHE_WB 0x002C /*!< Level 3 data cache write-back */
|
||||
#define ARM_PMU_LL_CACHE_RD 0x0036 /*!< Last level data cache read */
|
||||
#define ARM_PMU_LL_CACHE_MISS_RD 0x0037 /*!< Last level data cache read miss */
|
||||
#define ARM_PMU_L1D_CACHE_MISS_RD 0x0039 /*!< Level 1 data cache read miss */
|
||||
#define ARM_PMU_OP_COMPLETE 0x003A /*!< Operation retired */
|
||||
#define ARM_PMU_OP_SPEC 0x003B /*!< Operation speculatively executed */
|
||||
#define ARM_PMU_STALL 0x003C /*!< Stall cycle for instruction or operation not sent for execution */
|
||||
#define ARM_PMU_STALL_OP_BACKEND 0x003D /*!< Stall cycle for instruction or operation not sent for execution due to pipeline backend */
|
||||
#define ARM_PMU_STALL_OP_FRONTEND 0x003E /*!< Stall cycle for instruction or operation not sent for execution due to pipeline frontend */
|
||||
#define ARM_PMU_STALL_OP 0x003F /*!< Instruction or operation slots not occupied each cycle */
|
||||
#define ARM_PMU_L1D_CACHE_RD 0x0040 /*!< Level 1 data cache read */
|
||||
#define ARM_PMU_LE_RETIRED 0x0100 /*!< Loop end instruction executed */
|
||||
#define ARM_PMU_LE_SPEC 0x0101 /*!< Loop end instruction speculatively executed */
|
||||
#define ARM_PMU_BF_RETIRED 0x0104 /*!< Branch future instruction architecturally executed and condition code check pass */
|
||||
#define ARM_PMU_BF_SPEC 0x0105 /*!< Branch future instruction speculatively executed and condition code check pass */
|
||||
#define ARM_PMU_LE_CANCEL 0x0108 /*!< Loop end instruction not taken */
|
||||
#define ARM_PMU_BF_CANCEL 0x0109 /*!< Branch future instruction not taken */
|
||||
#define ARM_PMU_SE_CALL_S 0x0114 /*!< Call to secure function, resulting in Security state change */
|
||||
#define ARM_PMU_SE_CALL_NS 0x0115 /*!< Call to non-secure function, resulting in Security state change */
|
||||
#define ARM_PMU_DWT_CMPMATCH0 0x0118 /*!< DWT comparator 0 match */
|
||||
#define ARM_PMU_DWT_CMPMATCH1 0x0119 /*!< DWT comparator 1 match */
|
||||
#define ARM_PMU_DWT_CMPMATCH2 0x011A /*!< DWT comparator 2 match */
|
||||
#define ARM_PMU_DWT_CMPMATCH3 0x011B /*!< DWT comparator 3 match */
|
||||
#define ARM_PMU_MVE_INST_RETIRED 0x0200 /*!< MVE instruction architecturally executed */
|
||||
#define ARM_PMU_MVE_INST_SPEC 0x0201 /*!< MVE instruction speculatively executed */
|
||||
#define ARM_PMU_MVE_FP_RETIRED 0x0204 /*!< MVE floating-point instruction architecturally executed */
|
||||
#define ARM_PMU_MVE_FP_SPEC 0x0205 /*!< MVE floating-point instruction speculatively executed */
|
||||
#define ARM_PMU_MVE_FP_HP_RETIRED 0x0208 /*!< MVE half-precision floating-point instruction architecturally executed */
|
||||
#define ARM_PMU_MVE_FP_HP_SPEC 0x0209 /*!< MVE half-precision floating-point instruction speculatively executed */
|
||||
#define ARM_PMU_MVE_FP_SP_RETIRED 0x020C /*!< MVE single-precision floating-point instruction architecturally executed */
|
||||
#define ARM_PMU_MVE_FP_SP_SPEC 0x020D /*!< MVE single-precision floating-point instruction speculatively executed */
|
||||
#define ARM_PMU_MVE_FP_MAC_RETIRED 0x0214 /*!< MVE floating-point multiply or multiply-accumulate instruction architecturally executed */
|
||||
#define ARM_PMU_MVE_FP_MAC_SPEC 0x0215 /*!< MVE floating-point multiply or multiply-accumulate instruction speculatively executed */
|
||||
#define ARM_PMU_MVE_INT_RETIRED 0x0224 /*!< MVE integer instruction architecturally executed */
|
||||
#define ARM_PMU_MVE_INT_SPEC 0x0225 /*!< MVE integer instruction speculatively executed */
|
||||
#define ARM_PMU_MVE_INT_MAC_RETIRED 0x0228 /*!< MVE multiply or multiply-accumulate instruction architecturally executed */
|
||||
#define ARM_PMU_MVE_INT_MAC_SPEC 0x0229 /*!< MVE multiply or multiply-accumulate instruction speculatively executed */
|
||||
#define ARM_PMU_MVE_LDST_RETIRED 0x0238 /*!< MVE load or store instruction architecturally executed */
|
||||
#define ARM_PMU_MVE_LDST_SPEC 0x0239 /*!< MVE load or store instruction speculatively executed */
|
||||
#define ARM_PMU_MVE_LD_RETIRED 0x023C /*!< MVE load instruction architecturally executed */
|
||||
#define ARM_PMU_MVE_LD_SPEC 0x023D /*!< MVE load instruction speculatively executed */
|
||||
#define ARM_PMU_MVE_ST_RETIRED 0x0240 /*!< MVE store instruction architecturally executed */
|
||||
#define ARM_PMU_MVE_ST_SPEC 0x0241 /*!< MVE store instruction speculatively executed */
|
||||
#define ARM_PMU_MVE_LDST_CONTIG_RETIRED 0x0244 /*!< MVE contiguous load or store instruction architecturally executed */
|
||||
#define ARM_PMU_MVE_LDST_CONTIG_SPEC 0x0245 /*!< MVE contiguous load or store instruction speculatively executed */
|
||||
#define ARM_PMU_MVE_LD_CONTIG_RETIRED 0x0248 /*!< MVE contiguous load instruction architecturally executed */
|
||||
#define ARM_PMU_MVE_LD_CONTIG_SPEC 0x0249 /*!< MVE contiguous load instruction speculatively executed */
|
||||
#define ARM_PMU_MVE_ST_CONTIG_RETIRED 0x024C /*!< MVE contiguous store instruction architecturally executed */
|
||||
#define ARM_PMU_MVE_ST_CONTIG_SPEC 0x024D /*!< MVE contiguous store instruction speculatively executed */
|
||||
#define ARM_PMU_MVE_LDST_NONCONTIG_RETIRED 0x0250 /*!< MVE non-contiguous load or store instruction architecturally executed */
|
||||
#define ARM_PMU_MVE_LDST_NONCONTIG_SPEC 0x0251 /*!< MVE non-contiguous load or store instruction speculatively executed */
|
||||
#define ARM_PMU_MVE_LD_NONCONTIG_RETIRED 0x0254 /*!< MVE non-contiguous load instruction architecturally executed */
|
||||
#define ARM_PMU_MVE_LD_NONCONTIG_SPEC 0x0255 /*!< MVE non-contiguous load instruction speculatively executed */
|
||||
#define ARM_PMU_MVE_ST_NONCONTIG_RETIRED 0x0258 /*!< MVE non-contiguous store instruction architecturally executed */
|
||||
#define ARM_PMU_MVE_ST_NONCONTIG_SPEC 0x0259 /*!< MVE non-contiguous store instruction speculatively executed */
|
||||
#define ARM_PMU_MVE_LDST_MULTI_RETIRED 0x025C /*!< MVE memory instruction targeting multiple registers architecturally executed */
|
||||
#define ARM_PMU_MVE_LDST_MULTI_SPEC 0x025D /*!< MVE memory instruction targeting multiple registers speculatively executed */
|
||||
#define ARM_PMU_MVE_LD_MULTI_RETIRED 0x0260 /*!< MVE memory load instruction targeting multiple registers architecturally executed */
|
||||
#define ARM_PMU_MVE_LD_MULTI_SPEC 0x0261 /*!< MVE memory load instruction targeting multiple registers speculatively executed */
|
||||
#define ARM_PMU_MVE_ST_MULTI_RETIRED 0x0261 /*!< MVE memory store instruction targeting multiple registers architecturally executed */
|
||||
#define ARM_PMU_MVE_ST_MULTI_SPEC 0x0265 /*!< MVE memory store instruction targeting multiple registers speculatively executed */
|
||||
#define ARM_PMU_MVE_LDST_UNALIGNED_RETIRED 0x028C /*!< MVE unaligned memory load or store instruction architecturally executed */
|
||||
#define ARM_PMU_MVE_LDST_UNALIGNED_SPEC 0x028D /*!< MVE unaligned memory load or store instruction speculatively executed */
|
||||
#define ARM_PMU_MVE_LD_UNALIGNED_RETIRED 0x0290 /*!< MVE unaligned load instruction architecturally executed */
|
||||
#define ARM_PMU_MVE_LD_UNALIGNED_SPEC 0x0291 /*!< MVE unaligned load instruction speculatively executed */
|
||||
#define ARM_PMU_MVE_ST_UNALIGNED_RETIRED 0x0294 /*!< MVE unaligned store instruction architecturally executed */
|
||||
#define ARM_PMU_MVE_ST_UNALIGNED_SPEC 0x0295 /*!< MVE unaligned store instruction speculatively executed */
|
||||
#define ARM_PMU_MVE_LDST_UNALIGNED_NONCONTIG_RETIRED 0x0298 /*!< MVE unaligned noncontiguous load or store instruction architecturally executed */
|
||||
#define ARM_PMU_MVE_LDST_UNALIGNED_NONCONTIG_SPEC 0x0299 /*!< MVE unaligned noncontiguous load or store instruction speculatively executed */
|
||||
#define ARM_PMU_MVE_VREDUCE_RETIRED 0x02A0 /*!< MVE vector reduction instruction architecturally executed */
|
||||
#define ARM_PMU_MVE_VREDUCE_SPEC 0x02A1 /*!< MVE vector reduction instruction speculatively executed */
|
||||
#define ARM_PMU_MVE_VREDUCE_FP_RETIRED 0x02A4 /*!< MVE floating-point vector reduction instruction architecturally executed */
|
||||
#define ARM_PMU_MVE_VREDUCE_FP_SPEC 0x02A5 /*!< MVE floating-point vector reduction instruction speculatively executed */
|
||||
#define ARM_PMU_MVE_VREDUCE_INT_RETIRED 0x02A8 /*!< MVE integer vector reduction instruction architecturally executed */
|
||||
#define ARM_PMU_MVE_VREDUCE_INT_SPEC 0x02A9 /*!< MVE integer vector reduction instruction speculatively executed */
|
||||
#define ARM_PMU_MVE_PRED 0x02B8 /*!< Cycles where one or more predicated beats architecturally executed */
|
||||
#define ARM_PMU_MVE_STALL 0x02CC /*!< Stall cycles caused by an MVE instruction */
|
||||
#define ARM_PMU_MVE_STALL_RESOURCE 0x02CD /*!< Stall cycles caused by an MVE instruction because of resource conflicts */
|
||||
#define ARM_PMU_MVE_STALL_RESOURCE_MEM 0x02CE /*!< Stall cycles caused by an MVE instruction because of memory resource conflicts */
|
||||
#define ARM_PMU_MVE_STALL_RESOURCE_FP 0x02CF /*!< Stall cycles caused by an MVE instruction because of floating-point resource conflicts */
|
||||
#define ARM_PMU_MVE_STALL_RESOURCE_INT 0x02D0 /*!< Stall cycles caused by an MVE instruction because of integer resource conflicts */
|
||||
#define ARM_PMU_MVE_STALL_BREAK 0x02D3 /*!< Stall cycles caused by an MVE chain break */
|
||||
#define ARM_PMU_MVE_STALL_DEPENDENCY 0x02D4 /*!< Stall cycles caused by MVE register dependency */
|
||||
#define ARM_PMU_ITCM_ACCESS 0x4007 /*!< Instruction TCM access */
|
||||
#define ARM_PMU_DTCM_ACCESS 0x4008 /*!< Data TCM access */
|
||||
#define ARM_PMU_TRCEXTOUT0 0x4010 /*!< ETM external output 0 */
|
||||
#define ARM_PMU_TRCEXTOUT1 0x4011 /*!< ETM external output 1 */
|
||||
#define ARM_PMU_TRCEXTOUT2 0x4012 /*!< ETM external output 2 */
|
||||
#define ARM_PMU_TRCEXTOUT3 0x4013 /*!< ETM external output 3 */
|
||||
#define ARM_PMU_CTI_TRIGOUT4 0x4018 /*!< Cross-trigger Interface output trigger 4 */
|
||||
#define ARM_PMU_CTI_TRIGOUT5 0x4019 /*!< Cross-trigger Interface output trigger 5 */
|
||||
#define ARM_PMU_CTI_TRIGOUT6 0x401A /*!< Cross-trigger Interface output trigger 6 */
|
||||
#define ARM_PMU_CTI_TRIGOUT7 0x401B /*!< Cross-trigger Interface output trigger 7 */
|
||||
|
||||
/** \brief PMU Functions */
|
||||
|
||||
__STATIC_INLINE void ARM_PMU_Enable(void);
|
||||
__STATIC_INLINE void ARM_PMU_Disable(void);
|
||||
|
||||
__STATIC_INLINE void ARM_PMU_Set_EVTYPER(uint32_t num, uint32_t type);
|
||||
|
||||
__STATIC_INLINE void ARM_PMU_CYCCNT_Reset(void);
|
||||
__STATIC_INLINE void ARM_PMU_EVCNTR_ALL_Reset(void);
|
||||
|
||||
__STATIC_INLINE void ARM_PMU_CNTR_Enable(uint32_t mask);
|
||||
__STATIC_INLINE void ARM_PMU_CNTR_Disable(uint32_t mask);
|
||||
|
||||
__STATIC_INLINE uint32_t ARM_PMU_Get_CCNTR(void);
|
||||
__STATIC_INLINE uint32_t ARM_PMU_Get_EVCNTR(uint32_t num);
|
||||
|
||||
__STATIC_INLINE uint32_t ARM_PMU_Get_CNTR_OVS(void);
|
||||
__STATIC_INLINE void ARM_PMU_Set_CNTR_OVS(uint32_t mask);
|
||||
|
||||
__STATIC_INLINE void ARM_PMU_Set_CNTR_IRQ_Enable(uint32_t mask);
|
||||
__STATIC_INLINE void ARM_PMU_Set_CNTR_IRQ_Disable(uint32_t mask);
|
||||
|
||||
__STATIC_INLINE void ARM_PMU_CNTR_Increment(uint32_t mask);
|
||||
|
||||
/**
|
||||
\brief Enable the PMU
|
||||
*/
|
||||
__STATIC_INLINE void ARM_PMU_Enable(void)
|
||||
{
|
||||
PMU->CTRL |= PMU_CTRL_ENABLE_Msk;
|
||||
}
|
||||
|
||||
/**
|
||||
\brief Disable the PMU
|
||||
*/
|
||||
__STATIC_INLINE void ARM_PMU_Disable(void)
|
||||
{
|
||||
PMU->CTRL &= ~PMU_CTRL_ENABLE_Msk;
|
||||
}
|
||||
|
||||
/**
|
||||
\brief Set event to count for PMU eventer counter
|
||||
\param [in] num Event counter (0-30) to configure
|
||||
\param [in] type Event to count
|
||||
*/
|
||||
__STATIC_INLINE void ARM_PMU_Set_EVTYPER(uint32_t num, uint32_t type)
|
||||
{
|
||||
PMU->EVTYPER[num] = type;
|
||||
}
|
||||
|
||||
/**
|
||||
\brief Reset cycle counter
|
||||
*/
|
||||
__STATIC_INLINE void ARM_PMU_CYCCNT_Reset(void)
|
||||
{
|
||||
PMU->CTRL |= PMU_CTRL_CYCCNT_RESET_Msk;
|
||||
}
|
||||
|
||||
/**
|
||||
\brief Reset all event counters
|
||||
*/
|
||||
__STATIC_INLINE void ARM_PMU_EVCNTR_ALL_Reset(void)
|
||||
{
|
||||
PMU->CTRL |= PMU_CTRL_EVENTCNT_RESET_Msk;
|
||||
}
|
||||
|
||||
/**
|
||||
\brief Enable counters
|
||||
\param [in] mask Counters to enable
|
||||
\note Enables one or more of the following:
|
||||
- event counters (0-30)
|
||||
- cycle counter
|
||||
*/
|
||||
__STATIC_INLINE void ARM_PMU_CNTR_Enable(uint32_t mask)
|
||||
{
|
||||
PMU->CNTENSET = mask;
|
||||
}
|
||||
|
||||
/**
|
||||
\brief Disable counters
|
||||
\param [in] mask Counters to enable
|
||||
\note Disables one or more of the following:
|
||||
- event counters (0-30)
|
||||
- cycle counter
|
||||
*/
|
||||
__STATIC_INLINE void ARM_PMU_CNTR_Disable(uint32_t mask)
|
||||
{
|
||||
PMU->CNTENCLR = mask;
|
||||
}
|
||||
|
||||
/**
|
||||
\brief Read cycle counter
|
||||
\return Cycle count
|
||||
*/
|
||||
__STATIC_INLINE uint32_t ARM_PMU_Get_CCNTR(void)
|
||||
{
|
||||
return PMU->CCNTR;
|
||||
}
|
||||
|
||||
/**
|
||||
\brief Read event counter
|
||||
\param [in] num Event counter (0-30) to read
|
||||
\return Event count
|
||||
*/
|
||||
__STATIC_INLINE uint32_t ARM_PMU_Get_EVCNTR(uint32_t num)
|
||||
{
|
||||
return PMU_EVCNTR_CNT_Msk & PMU->EVCNTR[num];
|
||||
}
|
||||
|
||||
/**
|
||||
\brief Read counter overflow status
|
||||
\return Counter overflow status bits for the following:
|
||||
- event counters (0-30)
|
||||
- cycle counter
|
||||
*/
|
||||
__STATIC_INLINE uint32_t ARM_PMU_Get_CNTR_OVS(void)
|
||||
{
|
||||
return PMU->OVSSET;
|
||||
}
|
||||
|
||||
/**
|
||||
\brief Clear counter overflow status
|
||||
\param [in] mask Counter overflow status bits to clear
|
||||
\note Clears overflow status bits for one or more of the following:
|
||||
- event counters (0-30)
|
||||
- cycle counter
|
||||
*/
|
||||
__STATIC_INLINE void ARM_PMU_Set_CNTR_OVS(uint32_t mask)
|
||||
{
|
||||
PMU->OVSCLR = mask;
|
||||
}
|
||||
|
||||
/**
|
||||
\brief Enable counter overflow interrupt request
|
||||
\param [in] mask Counter overflow interrupt request bits to set
|
||||
\note Sets overflow interrupt request bits for one or more of the following:
|
||||
- event counters (0-30)
|
||||
- cycle counter
|
||||
*/
|
||||
__STATIC_INLINE void ARM_PMU_Set_CNTR_IRQ_Enable(uint32_t mask)
|
||||
{
|
||||
PMU->INTENSET = mask;
|
||||
}
|
||||
|
||||
/**
|
||||
\brief Disable counter overflow interrupt request
|
||||
\param [in] mask Counter overflow interrupt request bits to clear
|
||||
\note Clears overflow interrupt request bits for one or more of the following:
|
||||
- event counters (0-30)
|
||||
- cycle counter
|
||||
*/
|
||||
__STATIC_INLINE void ARM_PMU_Set_CNTR_IRQ_Disable(uint32_t mask)
|
||||
{
|
||||
PMU->INTENCLR = mask;
|
||||
}
|
||||
|
||||
/**
|
||||
\brief Software increment event counter
|
||||
\param [in] mask Counters to increment
|
||||
\note Software increment bits for one or more event counters (0-30)
|
||||
*/
|
||||
__STATIC_INLINE void ARM_PMU_CNTR_Increment(uint32_t mask)
|
||||
{
|
||||
PMU->SWINC = mask;
|
||||
}
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,641 @@
|
|||
/**
|
||||
**************************************************************************
|
||||
* @file at32f403a_407.h
|
||||
* @brief at32f403a_407 header file
|
||||
**************************************************************************
|
||||
*
|
||||
* Copyright (c) 2025, Artery Technology, All rights reserved.
|
||||
*
|
||||
* The software Board Support Package (BSP) that is made available to
|
||||
* download from Artery official website is the copyrighted work of Artery.
|
||||
* Artery authorizes customers to use, copy, and distribute the BSP
|
||||
* software and its related documentation for the purpose of design and
|
||||
* development in conjunction with Artery microcontrollers. Use of the
|
||||
* software is governed by this copyright notice and the following disclaimer.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
|
||||
* GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
|
||||
* TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
|
||||
* STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
|
||||
* INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
|
||||
*
|
||||
**************************************************************************
|
||||
*/
|
||||
|
||||
#ifndef __AT32F403A_407_H
|
||||
#define __AT32F403A_407_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#if defined (__CC_ARM)
|
||||
#pragma anon_unions
|
||||
#endif
|
||||
|
||||
/** @addtogroup CMSIS
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup AT32F403A_407
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup Library_configuration_section
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* tip: to avoid modifying this file each time you need to switch between these
|
||||
* devices, you can define the device in your toolchain compiler preprocessor.
|
||||
*/
|
||||
|
||||
#if !defined (AT32F403AVCT7) && !defined (AT32F403ARCT7) && !defined (AT32F403ACCT7) && \
|
||||
!defined (AT32F403ACCU7) && !defined (AT32F403AVGT7) && !defined (AT32F403ACGT7) && \
|
||||
!defined (AT32F403ARGT7) && !defined (AT32F403ACGU7) && !defined (AT32F403AVET7) && \
|
||||
!defined (AT32F403ARET7) && !defined (AT32F403ACET7) && !defined (AT32F403ACEU7) && \
|
||||
!defined (AT32F407RGT7) && !defined (AT32F407VGT7) && !defined (AT32F407RCT7) && \
|
||||
!defined (AT32F407VCT7) && !defined (AT32F407RET7) && !defined (AT32F407VET7) && \
|
||||
!defined (AT32F407AVCT7) && !defined (AT32F407AVGT7)
|
||||
|
||||
#error "Please select first the target device used in your application (in at32f403a_407.h file)"
|
||||
#endif
|
||||
|
||||
#if defined (AT32F403AVCT7) || defined (AT32F403ARCT7) || defined (AT32F403ACCT7) || \
|
||||
defined (AT32F403ACCU7) || defined (AT32F403AVGT7) || defined (AT32F403ACGT7) || \
|
||||
defined (AT32F403ARGT7) || defined (AT32F403ACGU7) || defined (AT32F403AVET7) || \
|
||||
defined (AT32F403ACET7) || defined (AT32F403ARET7) || defined (AT32F403ACEU7)
|
||||
|
||||
#define AT32F403Axx
|
||||
#endif
|
||||
|
||||
#if defined (AT32F407RGT7) || defined (AT32F407VGT7) || defined (AT32F407RCT7) || \
|
||||
defined (AT32F407VCT7) || defined (AT32F407VET7) || defined (AT32F407RET7) || \
|
||||
defined (AT32F407AVCT7) || defined (AT32F407AVGT7)
|
||||
|
||||
#define AT32F407xx
|
||||
#endif
|
||||
|
||||
/**
|
||||
* define with package
|
||||
*/
|
||||
#if defined (AT32F403AVCT7) || defined (AT32F403AVET7) || defined (AT32F403AVGT7)
|
||||
|
||||
#define AT32F403AVx
|
||||
#endif
|
||||
|
||||
#if defined (AT32F403ARCT7) || defined (AT32F403ARET7) || defined (AT32F403ARGT7)
|
||||
|
||||
#define AT32F403ARx
|
||||
#endif
|
||||
|
||||
#if defined (AT32F403ACCT7) || defined (AT32F403ACCU7) || defined (AT32F403ACET7) || \
|
||||
defined (AT32F403ACEU7) || defined (AT32F403ACGT7) || defined (AT32F403ACGU7)
|
||||
|
||||
#define AT32F403ACx
|
||||
#endif
|
||||
|
||||
#if defined (AT32F407RCT7) || defined (AT32F407RET7) || defined (AT32F407RGT7)
|
||||
|
||||
#define AT32F407Rx
|
||||
#endif
|
||||
|
||||
#if defined (AT32F407VCT7) || defined (AT32F407VET7) || defined (AT32F407VGT7) || \
|
||||
defined (AT32F407AVCT7) || defined (AT32F407AVGT7)
|
||||
|
||||
#define AT32F407Vx
|
||||
#endif
|
||||
|
||||
/**
|
||||
* define with memory density
|
||||
*/
|
||||
#if defined (AT32F403AVCT7) || defined (AT32F403ARCT7) || defined (AT32F403ACCT7) || \
|
||||
defined (AT32F403ACCU7)
|
||||
|
||||
#define AT32F403AxC
|
||||
#endif
|
||||
|
||||
#if defined (AT32F403AVET7) || defined (AT32F403ACET7) || defined (AT32F403ARET7) || \
|
||||
defined (AT32F403ACEU7)
|
||||
|
||||
#define AT32F403AxE
|
||||
#endif
|
||||
|
||||
#if defined (AT32F403AVGT7) || defined (AT32F403ACGT7) || defined (AT32F403ARGT7) || \
|
||||
defined (AT32F403ACGU7)
|
||||
|
||||
#define AT32F403AxG
|
||||
#endif
|
||||
|
||||
#if defined (AT32F407RCT7) || defined (AT32F407VCT7) || defined (AT32F407AVCT7)
|
||||
|
||||
#define AT32F407xC
|
||||
#endif
|
||||
|
||||
#if defined (AT32F407VET7) || defined (AT32F407RET7)
|
||||
|
||||
#define AT32F407xE
|
||||
#endif
|
||||
|
||||
#if defined (AT32F407RGT7) || defined (AT32F407VGT7) || defined (AT32F407AVGT7)
|
||||
|
||||
#define AT32F407xG
|
||||
#endif
|
||||
|
||||
#ifndef USE_STDPERIPH_DRIVER
|
||||
/**
|
||||
* @brief comment the line below if you will not use the peripherals drivers.
|
||||
* in this case, these drivers will not be included and the application code will
|
||||
* be based on direct access to peripherals registers
|
||||
*/
|
||||
#ifdef _RTE_
|
||||
#include "RTE_Components.h"
|
||||
#ifdef RTE_DEVICE_STDPERIPH_FRAMEWORK
|
||||
#define USE_STDPERIPH_DRIVER
|
||||
#endif
|
||||
#endif
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief at32f403a_407 standard peripheral library version number
|
||||
*/
|
||||
#define __AT32F403A_407_LIBRARY_VERSION_MAJOR (0x02) /*!< [31:24] major version */
|
||||
#define __AT32F403A_407_LIBRARY_VERSION_MIDDLE (0x02) /*!< [23:16] middle version */
|
||||
#define __AT32F403A_407_LIBRARY_VERSION_MINOR (0x02) /*!< [15:8] minor version */
|
||||
#define __AT32F403A_407_LIBRARY_VERSION_RC (0x00) /*!< [7:0] release candidate */
|
||||
#define __AT32F403A_407_LIBRARY_VERSION ((__AT32F403A_407_LIBRARY_VERSION_MAJOR << 24) | \
|
||||
(__AT32F403A_407_LIBRARY_VERSION_MIDDLE << 16) | \
|
||||
(__AT32F403A_407_LIBRARY_VERSION_MINOR << 8) | \
|
||||
(__AT32F403A_407_LIBRARY_VERSION_RC))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup Configuration_section_for_CMSIS
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief configuration of the cortex-m4 processor and core peripherals
|
||||
*/
|
||||
#define __CM4_REV 0x0001U /*!< core revision r0p1 */
|
||||
#define __MPU_PRESENT 1 /*!< mpu present */
|
||||
#define __NVIC_PRIO_BITS 4 /*!< at32 uses 4 bits for the priority levels */
|
||||
#define __Vendor_SysTickConfig 0 /*!< set to 1 if different systick config is used */
|
||||
#define __FPU_PRESENT 1U /*!< fpu present */
|
||||
|
||||
/**
|
||||
* @brief at32f403a_407 interrupt number definition, according to the selected device
|
||||
* in @ref Library_configuration_section
|
||||
*/
|
||||
typedef enum IRQn
|
||||
{
|
||||
/****** cortex-m4 processor exceptions numbers ***************************************************/
|
||||
Reset_IRQn = -15, /*!< 1 reset vector, invoked on power up and warm reset */
|
||||
NonMaskableInt_IRQn = -14, /*!< 2 non maskable interrupt */
|
||||
HardFault_IRQn = -13, /*!< 3 hard fault, all classes of fault */
|
||||
MemoryManagement_IRQn = -12, /*!< 4 cortex-m4 memory management interrupt */
|
||||
BusFault_IRQn = -11, /*!< 5 cortex-m4 bus fault interrupt */
|
||||
UsageFault_IRQn = -10, /*!< 6 cortex-m4 usage fault interrupt */
|
||||
SVCall_IRQn = -5, /*!< 11 cortex-m4 sv call interrupt */
|
||||
DebugMonitor_IRQn = -4, /*!< 12 cortex-m4 debug monitor interrupt */
|
||||
PendSV_IRQn = -2, /*!< 14 cortex-m4 pend sv interrupt */
|
||||
SysTick_IRQn = -1, /*!< 15 cortex-m4 system tick interrupt */
|
||||
|
||||
/****** at32 specific interrupt numbers *********************************************************/
|
||||
WWDT_IRQn = 0, /*!< window watchdog timer interrupt */
|
||||
PVM_IRQn = 1, /*!< pvm through exint line detection interrupt */
|
||||
TAMPER_IRQn = 2, /*!< tamper interrupt */
|
||||
RTC_IRQn = 3, /*!< rtc global interrupt */
|
||||
FLASH_IRQn = 4, /*!< flash global interrupt */
|
||||
CRM_IRQn = 5, /*!< crm global interrupt */
|
||||
EXINT0_IRQn = 6, /*!< external line0 interrupt */
|
||||
EXINT1_IRQn = 7, /*!< external line1 interrupt */
|
||||
EXINT2_IRQn = 8, /*!< external line2 interrupt */
|
||||
EXINT3_IRQn = 9, /*!< external line3 interrupt */
|
||||
EXINT4_IRQn = 10, /*!< external line4 interrupt */
|
||||
DMA1_Channel1_IRQn = 11, /*!< dma1 channel 1 global interrupt */
|
||||
DMA1_Channel2_IRQn = 12, /*!< dma1 channel 2 global interrupt */
|
||||
DMA1_Channel3_IRQn = 13, /*!< dma1 channel 3 global interrupt */
|
||||
DMA1_Channel4_IRQn = 14, /*!< dma1 channel 4 global interrupt */
|
||||
DMA1_Channel5_IRQn = 15, /*!< dma1 channel 5 global interrupt */
|
||||
DMA1_Channel6_IRQn = 16, /*!< dma1 channel 6 global interrupt */
|
||||
DMA1_Channel7_IRQn = 17, /*!< dma1 channel 7 global interrupt */
|
||||
|
||||
#if defined (AT32F403Axx)
|
||||
ADC1_2_IRQn = 18, /*!< adc1 and adc2 global interrupt */
|
||||
USBFS_H_CAN1_TX_IRQn = 19, /*!< usb device high priority or can1 tx interrupts */
|
||||
USBFS_L_CAN1_RX0_IRQn = 20, /*!< usb device low priority or can1 rx0 interrupts */
|
||||
CAN1_RX1_IRQn = 21, /*!< can1 rx1 interrupt */
|
||||
CAN1_SE_IRQn = 22, /*!< can1 se interrupt */
|
||||
EXINT9_5_IRQn = 23, /*!< external line[9:5] interrupts */
|
||||
TMR1_BRK_TMR9_IRQn = 24, /*!< tmr1 brake interrupt */
|
||||
TMR1_OVF_TMR10_IRQn = 25, /*!< tmr1 overflow interrupt */
|
||||
TMR1_TRG_HALL_TMR11_IRQn = 26, /*!< tmr1 trigger and hall interrupt */
|
||||
TMR1_CH_IRQn = 27, /*!< tmr1 channel interrupt */
|
||||
TMR2_GLOBAL_IRQn = 28, /*!< tmr2 global interrupt */
|
||||
TMR3_GLOBAL_IRQn = 29, /*!< tmr3 global interrupt */
|
||||
TMR4_GLOBAL_IRQn = 30, /*!< tmr4 global interrupt */
|
||||
I2C1_EVT_IRQn = 31, /*!< i2c1 event interrupt */
|
||||
I2C1_ERR_IRQn = 32, /*!< i2c1 error interrupt */
|
||||
I2C2_EVT_IRQn = 33, /*!< i2c2 event interrupt */
|
||||
I2C2_ERR_IRQn = 34, /*!< i2c2 error interrupt */
|
||||
SPI1_IRQn = 35, /*!< spi1 global interrupt */
|
||||
SPI2_I2S2EXT_IRQn = 36, /*!< spi2 global interrupt */
|
||||
USART1_IRQn = 37, /*!< usart1 global interrupt */
|
||||
USART2_IRQn = 38, /*!< usart2 global interrupt */
|
||||
USART3_IRQn = 39, /*!< usart3 global interrupt */
|
||||
EXINT15_10_IRQn = 40, /*!< external line[15:10] interrupts */
|
||||
RTCAlarm_IRQn = 41, /*!< rtc alarm through exint line interrupt */
|
||||
USBFSWakeUp_IRQn = 42, /*!< usb device wakeup from suspend through exint line interrupt */
|
||||
TMR8_BRK_TMR12_IRQn = 43, /*!< tmr8 brake interrupt */
|
||||
TMR8_OVF_TMR13_IRQn = 44, /*!< tmr8 overflow interrupt */
|
||||
TMR8_TRG_HALL_TMR14_IRQn = 45, /*!< tmr8 trigger and hall interrupt */
|
||||
TMR8_CH_IRQn = 46, /*!< tmr8 channel interrupt */
|
||||
ADC3_IRQn = 47, /*!< adc3 global interrupt */
|
||||
XMC_IRQn = 48, /*!< xmc global interrupt */
|
||||
SDIO1_IRQn = 49, /*!< sdio1 global interrupt */
|
||||
TMR5_GLOBAL_IRQn = 50, /*!< tmr5 global interrupt */
|
||||
SPI3_I2S3EXT_IRQn = 51, /*!< spi3 global interrupt */
|
||||
UART4_IRQn = 52, /*!< uart4 global interrupt */
|
||||
UART5_IRQn = 53, /*!< uart5 global interrupt */
|
||||
TMR6_GLOBAL_IRQn = 54, /*!< tmr6 global interrupt */
|
||||
TMR7_GLOBAL_IRQn = 55, /*!< tmr7 global interrupt */
|
||||
DMA2_Channel1_IRQn = 56, /*!< dma2 channel 1 global interrupt */
|
||||
DMA2_Channel2_IRQn = 57, /*!< dma2 channel 2 global interrupt */
|
||||
DMA2_Channel3_IRQn = 58, /*!< dma2 channel 3 global interrupt */
|
||||
DMA2_Channel4_5_IRQn = 59, /*!< dma2 channel 4 and channel 5 global interrupt */
|
||||
SDIO2_IRQn = 60, /*!< sdio2 global interrupt */
|
||||
I2C3_EVT_IRQn = 61, /*!< i2c3 event interrupt */
|
||||
I2C3_ERR_IRQn = 62, /*!< i2c3 error interrupt */
|
||||
SPI4_IRQn = 63, /*!< spi4 global interrupt */
|
||||
CAN2_TX_IRQn = 68, /*!< can2 tx interrupt */
|
||||
CAN2_RX0_IRQn = 69, /*!< can2 rx0 interrupt */
|
||||
CAN2_RX1_IRQn = 70, /*!< can2 rx1 interrupt */
|
||||
CAN2_SE_IRQn = 71, /*!< can2 se interrupt */
|
||||
ACC_IRQn = 72, /*!< acc interrupt */
|
||||
USBFS_MAPH_IRQn = 73, /*!< usb map hp interrupt */
|
||||
USBFS_MAPL_IRQn = 74, /*!< usb map lp interrupt */
|
||||
DMA2_Channel6_7_IRQn = 75, /*!< dma2 channel 6 and channel 7 global interrupt */
|
||||
USART6_IRQn = 76, /*!< usart6 interrupt */
|
||||
UART7_IRQn = 77, /*!< uart7 interrupt */
|
||||
UART8_IRQn = 78 /*!< uart8 interrupt */
|
||||
#endif
|
||||
|
||||
#if defined (AT32F407xx)
|
||||
ADC1_2_IRQn = 18, /*!< adc1 and adc2 global interrupt */
|
||||
USBFS_H_CAN1_TX_IRQn = 19, /*!< usb device high priority or can1 tx interrupts */
|
||||
USBFS_L_CAN1_RX0_IRQn = 20, /*!< usb device low priority or can1 rx0 interrupts */
|
||||
CAN1_RX1_IRQn = 21, /*!< can1 rx1 interrupt */
|
||||
CAN1_SE_IRQn = 22, /*!< can1 se interrupt */
|
||||
EXINT9_5_IRQn = 23, /*!< external line[9:5] interrupts */
|
||||
TMR1_BRK_TMR9_IRQn = 24, /*!< tmr1 brake interrupt */
|
||||
TMR1_OVF_TMR10_IRQn = 25, /*!< tmr1 overflow interrupt */
|
||||
TMR1_TRG_HALL_TMR11_IRQn = 26, /*!< tmr1 trigger and hall interrupt */
|
||||
TMR1_CH_IRQn = 27, /*!< tmr1 channel interrupt */
|
||||
TMR2_GLOBAL_IRQn = 28, /*!< tmr2 global interrupt */
|
||||
TMR3_GLOBAL_IRQn = 29, /*!< tmr3 global interrupt */
|
||||
TMR4_GLOBAL_IRQn = 30, /*!< tmr4 global interrupt */
|
||||
I2C1_EVT_IRQn = 31, /*!< i2c1 event interrupt */
|
||||
I2C1_ERR_IRQn = 32, /*!< i2c1 error interrupt */
|
||||
I2C2_EVT_IRQn = 33, /*!< i2c2 event interrupt */
|
||||
I2C2_ERR_IRQn = 34, /*!< i2c2 error interrupt */
|
||||
SPI1_IRQn = 35, /*!< spi1 global interrupt */
|
||||
SPI2_I2S2EXT_IRQn = 36, /*!< spi2 global interrupt */
|
||||
USART1_IRQn = 37, /*!< usart1 global interrupt */
|
||||
USART2_IRQn = 38, /*!< usart2 global interrupt */
|
||||
USART3_IRQn = 39, /*!< usart3 global interrupt */
|
||||
EXINT15_10_IRQn = 40, /*!< external line[15:10] interrupts */
|
||||
RTCAlarm_IRQn = 41, /*!< rtc alarm through exint line interrupt */
|
||||
USBFSWakeUp_IRQn = 42, /*!< usb device wakeup from suspend through exint line interrupt */
|
||||
TMR8_BRK_TMR12_IRQn = 43, /*!< tmr8 brake interrupt */
|
||||
TMR8_OVF_TMR13_IRQn = 44, /*!< tmr8 overflow interrupt */
|
||||
TMR8_TRG_HALL_TMR14_IRQn = 45, /*!< tmr8 trigger and hall interrupt */
|
||||
TMR8_CH_IRQn = 46, /*!< tmr8 channel interrupt */
|
||||
ADC3_IRQn = 47, /*!< adc3 global interrupt */
|
||||
XMC_IRQn = 48, /*!< xmc global interrupt */
|
||||
SDIO1_IRQn = 49, /*!< sdio1 global interrupt */
|
||||
TMR5_GLOBAL_IRQn = 50, /*!< tmr5 global interrupt */
|
||||
SPI3_I2S3EXT_IRQn = 51, /*!< spi3 global interrupt */
|
||||
UART4_IRQn = 52, /*!< uart4 global interrupt */
|
||||
UART5_IRQn = 53, /*!< uart5 global interrupt */
|
||||
TMR6_GLOBAL_IRQn = 54, /*!< tmr6 global interrupt */
|
||||
TMR7_GLOBAL_IRQn = 55, /*!< tmr7 global interrupt */
|
||||
DMA2_Channel1_IRQn = 56, /*!< dma2 channel 1 global interrupt */
|
||||
DMA2_Channel2_IRQn = 57, /*!< dma2 channel 2 global interrupt */
|
||||
DMA2_Channel3_IRQn = 58, /*!< dma2 channel 3 global interrupt */
|
||||
DMA2_Channel4_5_IRQn = 59, /*!< dma2 channel 4 and channel 5 global interrupt */
|
||||
SDIO2_IRQn = 60, /*!< sdio2 global interrupt */
|
||||
I2C3_EVT_IRQn = 61, /*!< i2c3 event interrupt */
|
||||
I2C3_ERR_IRQn = 62, /*!< i2c3 error interrupt */
|
||||
SPI4_IRQn = 63, /*!< spi4 global interrupt */
|
||||
CAN2_TX_IRQn = 68, /*!< can2 tx interrupt */
|
||||
CAN2_RX0_IRQn = 69, /*!< can2 rx0 interrupt */
|
||||
CAN2_RX1_IRQn = 70, /*!< can2 rx1 interrupt */
|
||||
CAN2_SE_IRQn = 71, /*!< can2 se interrupt */
|
||||
ACC_IRQn = 72, /*!< acc interrupt */
|
||||
USBFS_MAPH_IRQn = 73, /*!< usb map hp interrupt */
|
||||
USBFS_MAPL_IRQn = 74, /*!< usb map lp interrupt */
|
||||
DMA2_Channel6_7_IRQn = 75, /*!< dma2 channel 6 and channel 7 global interrupt */
|
||||
USART6_IRQn = 76, /*!< usart6 interrupt */
|
||||
UART7_IRQn = 77, /*!< uart7 interrupt */
|
||||
UART8_IRQn = 78, /*!< uart8 interrupt */
|
||||
EMAC_IRQn = 79, /*!< emac interrupt */
|
||||
EMAC_WKUP_IRQn = 80 /*!< emac wakeup interrupt */
|
||||
#endif
|
||||
|
||||
} IRQn_Type;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#include "core_cm4.h"
|
||||
#include "system_at32f403a_407.h"
|
||||
#include <stdint.h>
|
||||
|
||||
/** @addtogroup Exported_types
|
||||
* @{
|
||||
*/
|
||||
|
||||
typedef int32_t INT32;
|
||||
typedef int16_t INT16;
|
||||
typedef int8_t INT8;
|
||||
typedef uint32_t UINT32;
|
||||
typedef uint16_t UINT16;
|
||||
typedef uint8_t UINT8;
|
||||
|
||||
typedef int32_t s32;
|
||||
typedef int16_t s16;
|
||||
typedef int8_t s8;
|
||||
|
||||
typedef const int32_t sc32; /*!< read only */
|
||||
typedef const int16_t sc16; /*!< read only */
|
||||
typedef const int8_t sc8; /*!< read only */
|
||||
|
||||
typedef __IO int32_t vs32;
|
||||
typedef __IO int16_t vs16;
|
||||
typedef __IO int8_t vs8;
|
||||
|
||||
typedef __I int32_t vsc32; /*!< read only */
|
||||
typedef __I int16_t vsc16; /*!< read only */
|
||||
typedef __I int8_t vsc8; /*!< read only */
|
||||
|
||||
typedef uint32_t u32;
|
||||
typedef uint16_t u16;
|
||||
typedef uint8_t u8;
|
||||
|
||||
typedef const uint32_t uc32; /*!< read only */
|
||||
typedef const uint16_t uc16; /*!< read only */
|
||||
typedef const uint8_t uc8; /*!< read only */
|
||||
|
||||
typedef __IO uint32_t vu32;
|
||||
typedef __IO uint16_t vu16;
|
||||
typedef __IO uint8_t vu8;
|
||||
|
||||
typedef __I uint32_t vuc32; /*!< read only */
|
||||
typedef __I uint16_t vuc16; /*!< read only */
|
||||
typedef __I uint8_t vuc8; /*!< read only */
|
||||
|
||||
/**
|
||||
* @brief flag status
|
||||
*/
|
||||
typedef enum {RESET = 0, SET = !RESET} flag_status;
|
||||
|
||||
/**
|
||||
* @brief confirm state
|
||||
*/
|
||||
typedef enum {FALSE = 0, TRUE = !FALSE} confirm_state;
|
||||
|
||||
/**
|
||||
* @brief error status
|
||||
*/
|
||||
typedef enum {ERROR = 0, SUCCESS = !ERROR} error_status;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup Exported_macro
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define REG8(addr) *(volatile uint8_t *)(addr)
|
||||
#define REG16(addr) *(volatile uint16_t *)(addr)
|
||||
#define REG32(addr) *(volatile uint32_t *)(addr)
|
||||
|
||||
#define MAKE_VALUE(reg_offset, bit_num) (uint32_t)(((reg_offset) << 16) | (bit_num & 0x1F))
|
||||
|
||||
#define PERIPH_REG(periph_base, value) REG32((periph_base + (value >> 16)))
|
||||
#define PERIPH_REG_BIT(value) (0x1U << (value & 0x1F))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup Peripheral_memory_map
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define FLASH_BASE ((uint32_t)0x08000000)
|
||||
#define SPIM_FLASH_BASE ((uint32_t)0x08400000)
|
||||
#define USD_BASE ((uint32_t)0x1FFFF800)
|
||||
#define SRAM_BASE ((uint32_t)0x20000000)
|
||||
#define PERIPH_BASE ((uint32_t)0x40000000)
|
||||
#define XMC_REG_BASE ((uint32_t)0xA0000000)
|
||||
#define DEBUG_BASE ((uint32_t)0xE0042000)
|
||||
|
||||
#define APB1PERIPH_BASE (PERIPH_BASE + 0x00000)
|
||||
#define APB2PERIPH_BASE (PERIPH_BASE + 0x10000)
|
||||
#define AHBPERIPH_BASE (PERIPH_BASE + 0x20000)
|
||||
|
||||
#if defined (AT32F403Axx)
|
||||
/* apb1 bus base address */
|
||||
#define TMR2_BASE (APB1PERIPH_BASE + 0x0000)
|
||||
#define TMR3_BASE (APB1PERIPH_BASE + 0x0400)
|
||||
#define TMR4_BASE (APB1PERIPH_BASE + 0x0800)
|
||||
#define TMR5_BASE (APB1PERIPH_BASE + 0x0C00)
|
||||
#define TMR6_BASE (APB1PERIPH_BASE + 0x1000)
|
||||
#define TMR7_BASE (APB1PERIPH_BASE + 0x1400)
|
||||
#define TMR12_BASE (APB1PERIPH_BASE + 0x1800)
|
||||
#define TMR13_BASE (APB1PERIPH_BASE + 0x1C00)
|
||||
#define TMR14_BASE (APB1PERIPH_BASE + 0x2000)
|
||||
#define RTC_BASE (APB1PERIPH_BASE + 0x2800)
|
||||
#define WWDT_BASE (APB1PERIPH_BASE + 0x2C00)
|
||||
#define WDT_BASE (APB1PERIPH_BASE + 0x3000)
|
||||
#define SPI2_BASE (APB1PERIPH_BASE + 0x3800)
|
||||
#define SPI3_BASE (APB1PERIPH_BASE + 0x3C00)
|
||||
#define SPI4_BASE (APB1PERIPH_BASE + 0x4000)
|
||||
#define USART2_BASE (APB1PERIPH_BASE + 0x4400)
|
||||
#define USART3_BASE (APB1PERIPH_BASE + 0x4800)
|
||||
#define UART4_BASE (APB1PERIPH_BASE + 0x4C00)
|
||||
#define UART5_BASE (APB1PERIPH_BASE + 0x5000)
|
||||
#define I2C1_BASE (APB1PERIPH_BASE + 0x5400)
|
||||
#define I2C2_BASE (APB1PERIPH_BASE + 0x5800)
|
||||
#define USBFS_BASE (APB1PERIPH_BASE + 0x5C00)
|
||||
#define CAN1_BASE (APB1PERIPH_BASE + 0x6400)
|
||||
#define CAN2_BASE (APB1PERIPH_BASE + 0x6800)
|
||||
#define BPR_BASE (APB1PERIPH_BASE + 0x6C00)
|
||||
#define PWC_BASE (APB1PERIPH_BASE + 0x7000)
|
||||
#define DAC_BASE (APB1PERIPH_BASE + 0x7400)
|
||||
/* apb2 bus base address */
|
||||
#define IOMUX_BASE (APB2PERIPH_BASE + 0x0000)
|
||||
#define EXINT_BASE (APB2PERIPH_BASE + 0x0400)
|
||||
#define GPIOA_BASE (APB2PERIPH_BASE + 0x0800)
|
||||
#define GPIOB_BASE (APB2PERIPH_BASE + 0x0C00)
|
||||
#define GPIOC_BASE (APB2PERIPH_BASE + 0x1000)
|
||||
#define GPIOD_BASE (APB2PERIPH_BASE + 0x1400)
|
||||
#define GPIOE_BASE (APB2PERIPH_BASE + 0x1800)
|
||||
#define ADC1_BASE (APB2PERIPH_BASE + 0x2400)
|
||||
#define ADC2_BASE (APB2PERIPH_BASE + 0x2800)
|
||||
#define TMR1_BASE (APB2PERIPH_BASE + 0x2C00)
|
||||
#define SPI1_BASE (APB2PERIPH_BASE + 0x3000)
|
||||
#define TMR8_BASE (APB2PERIPH_BASE + 0x3400)
|
||||
#define USART1_BASE (APB2PERIPH_BASE + 0x3800)
|
||||
#define ADC3_BASE (APB2PERIPH_BASE + 0x3C00)
|
||||
#define TMR9_BASE (APB2PERIPH_BASE + 0x4C00)
|
||||
#define TMR10_BASE (APB2PERIPH_BASE + 0x5000)
|
||||
#define TMR11_BASE (APB2PERIPH_BASE + 0x5400)
|
||||
#define ACC_BASE (APB2PERIPH_BASE + 0x5800)
|
||||
#define I2C3_BASE (APB2PERIPH_BASE + 0x5C00)
|
||||
#define USART6_BASE (APB2PERIPH_BASE + 0x6000)
|
||||
#define UART7_BASE (APB2PERIPH_BASE + 0x6400)
|
||||
#define UART8_BASE (APB2PERIPH_BASE + 0x6800)
|
||||
#define I2S2EXT_BASE (APB2PERIPH_BASE + 0x6C00)
|
||||
#define I2S3EXT_BASE (APB2PERIPH_BASE + 0x7000)
|
||||
#define SDIO1_BASE (APB2PERIPH_BASE + 0x8000)
|
||||
/* ahb bus base address */
|
||||
#define DMA1_BASE (AHBPERIPH_BASE + 0x0000)
|
||||
#define DMA1_CHANNEL1_BASE (AHBPERIPH_BASE + 0x0008)
|
||||
#define DMA1_CHANNEL2_BASE (AHBPERIPH_BASE + 0x001C)
|
||||
#define DMA1_CHANNEL3_BASE (AHBPERIPH_BASE + 0x0030)
|
||||
#define DMA1_CHANNEL4_BASE (AHBPERIPH_BASE + 0x0044)
|
||||
#define DMA1_CHANNEL5_BASE (AHBPERIPH_BASE + 0x0058)
|
||||
#define DMA1_CHANNEL6_BASE (AHBPERIPH_BASE + 0x006C)
|
||||
#define DMA1_CHANNEL7_BASE (AHBPERIPH_BASE + 0x0080)
|
||||
#define DMA2_BASE (AHBPERIPH_BASE + 0x0400)
|
||||
#define DMA2_CHANNEL1_BASE (AHBPERIPH_BASE + 0x0408)
|
||||
#define DMA2_CHANNEL2_BASE (AHBPERIPH_BASE + 0x041C)
|
||||
#define DMA2_CHANNEL3_BASE (AHBPERIPH_BASE + 0x0430)
|
||||
#define DMA2_CHANNEL4_BASE (AHBPERIPH_BASE + 0x0444)
|
||||
#define DMA2_CHANNEL5_BASE (AHBPERIPH_BASE + 0x0458)
|
||||
#define DMA2_CHANNEL6_BASE (AHBPERIPH_BASE + 0x046C)
|
||||
#define DMA2_CHANNEL7_BASE (AHBPERIPH_BASE + 0x0480)
|
||||
#define CRM_BASE (AHBPERIPH_BASE + 0x1000)
|
||||
#define FLASH_REG_BASE (AHBPERIPH_BASE + 0x2000)
|
||||
#define CRC_BASE (AHBPERIPH_BASE + 0x3000)
|
||||
#define SDIO2_BASE (AHBPERIPH_BASE + 0x3400)
|
||||
#define XMC_BANK1_REG_BASE (XMC_REG_BASE + 0x0000)
|
||||
#define XMC_BANK1E_REG_BASE (XMC_REG_BASE + 0x0104)
|
||||
#define XMC_BANK1E_H_BASE (XMC_REG_BASE + 0x0220)
|
||||
#define XMC_BANK2_REG_BASE (XMC_REG_BASE + 0x0060)
|
||||
#define XMC_BANK3_REG_BASE (XMC_REG_BASE + 0x0080)
|
||||
#define XMC_BANK4_REG_BASE (XMC_REG_BASE + 0x00A0)
|
||||
#endif
|
||||
|
||||
#if defined (AT32F407xx)
|
||||
/* apb1 bus base address */
|
||||
#define TMR2_BASE (APB1PERIPH_BASE + 0x0000)
|
||||
#define TMR3_BASE (APB1PERIPH_BASE + 0x0400)
|
||||
#define TMR4_BASE (APB1PERIPH_BASE + 0x0800)
|
||||
#define TMR5_BASE (APB1PERIPH_BASE + 0x0C00)
|
||||
#define TMR6_BASE (APB1PERIPH_BASE + 0x1000)
|
||||
#define TMR7_BASE (APB1PERIPH_BASE + 0x1400)
|
||||
#define TMR12_BASE (APB1PERIPH_BASE + 0x1800)
|
||||
#define TMR13_BASE (APB1PERIPH_BASE + 0x1C00)
|
||||
#define TMR14_BASE (APB1PERIPH_BASE + 0x2000)
|
||||
#define RTC_BASE (APB1PERIPH_BASE + 0x2800)
|
||||
#define WWDT_BASE (APB1PERIPH_BASE + 0x2C00)
|
||||
#define WDT_BASE (APB1PERIPH_BASE + 0x3000)
|
||||
#define SPI2_BASE (APB1PERIPH_BASE + 0x3800)
|
||||
#define SPI3_BASE (APB1PERIPH_BASE + 0x3C00)
|
||||
#define SPI4_BASE (APB1PERIPH_BASE + 0x4000)
|
||||
#define USART2_BASE (APB1PERIPH_BASE + 0x4400)
|
||||
#define USART3_BASE (APB1PERIPH_BASE + 0x4800)
|
||||
#define UART4_BASE (APB1PERIPH_BASE + 0x4C00)
|
||||
#define UART5_BASE (APB1PERIPH_BASE + 0x5000)
|
||||
#define I2C1_BASE (APB1PERIPH_BASE + 0x5400)
|
||||
#define I2C2_BASE (APB1PERIPH_BASE + 0x5800)
|
||||
#define USBFS_BASE (APB1PERIPH_BASE + 0x5C00)
|
||||
#define CAN1_BASE (APB1PERIPH_BASE + 0x6400)
|
||||
#define CAN2_BASE (APB1PERIPH_BASE + 0x6800)
|
||||
#define BPR_BASE (APB1PERIPH_BASE + 0x6C00)
|
||||
#define PWC_BASE (APB1PERIPH_BASE + 0x7000)
|
||||
#define DAC_BASE (APB1PERIPH_BASE + 0x7400)
|
||||
/* apb2 bus base address */
|
||||
#define IOMUX_BASE (APB2PERIPH_BASE + 0x0000)
|
||||
#define EXINT_BASE (APB2PERIPH_BASE + 0x0400)
|
||||
#define GPIOA_BASE (APB2PERIPH_BASE + 0x0800)
|
||||
#define GPIOB_BASE (APB2PERIPH_BASE + 0x0C00)
|
||||
#define GPIOC_BASE (APB2PERIPH_BASE + 0x1000)
|
||||
#define GPIOD_BASE (APB2PERIPH_BASE + 0x1400)
|
||||
#define GPIOE_BASE (APB2PERIPH_BASE + 0x1800)
|
||||
#define ADC1_BASE (APB2PERIPH_BASE + 0x2400)
|
||||
#define ADC2_BASE (APB2PERIPH_BASE + 0x2800)
|
||||
#define TMR1_BASE (APB2PERIPH_BASE + 0x2C00)
|
||||
#define SPI1_BASE (APB2PERIPH_BASE + 0x3000)
|
||||
#define TMR8_BASE (APB2PERIPH_BASE + 0x3400)
|
||||
#define USART1_BASE (APB2PERIPH_BASE + 0x3800)
|
||||
#define ADC3_BASE (APB2PERIPH_BASE + 0x3C00)
|
||||
#define TMR9_BASE (APB2PERIPH_BASE + 0x4C00)
|
||||
#define TMR10_BASE (APB2PERIPH_BASE + 0x5000)
|
||||
#define TMR11_BASE (APB2PERIPH_BASE + 0x5400)
|
||||
#define ACC_BASE (APB2PERIPH_BASE + 0x5800)
|
||||
#define I2C3_BASE (APB2PERIPH_BASE + 0x5C00)
|
||||
#define USART6_BASE (APB2PERIPH_BASE + 0x6000)
|
||||
#define UART7_BASE (APB2PERIPH_BASE + 0x6400)
|
||||
#define UART8_BASE (APB2PERIPH_BASE + 0x6800)
|
||||
#define I2S2EXT_BASE (APB2PERIPH_BASE + 0x6C00)
|
||||
#define I2S3EXT_BASE (APB2PERIPH_BASE + 0x7000)
|
||||
#define SDIO1_BASE (APB2PERIPH_BASE + 0x8000)
|
||||
/* ahb bus base address */
|
||||
#define DMA1_BASE (AHBPERIPH_BASE + 0x0000)
|
||||
#define DMA1_CHANNEL1_BASE (AHBPERIPH_BASE + 0x0008)
|
||||
#define DMA1_CHANNEL2_BASE (AHBPERIPH_BASE + 0x001C)
|
||||
#define DMA1_CHANNEL3_BASE (AHBPERIPH_BASE + 0x0030)
|
||||
#define DMA1_CHANNEL4_BASE (AHBPERIPH_BASE + 0x0044)
|
||||
#define DMA1_CHANNEL5_BASE (AHBPERIPH_BASE + 0x0058)
|
||||
#define DMA1_CHANNEL6_BASE (AHBPERIPH_BASE + 0x006C)
|
||||
#define DMA1_CHANNEL7_BASE (AHBPERIPH_BASE + 0x0080)
|
||||
#define DMA2_BASE (AHBPERIPH_BASE + 0x0400)
|
||||
#define DMA2_CHANNEL1_BASE (AHBPERIPH_BASE + 0x0408)
|
||||
#define DMA2_CHANNEL2_BASE (AHBPERIPH_BASE + 0x041C)
|
||||
#define DMA2_CHANNEL3_BASE (AHBPERIPH_BASE + 0x0430)
|
||||
#define DMA2_CHANNEL4_BASE (AHBPERIPH_BASE + 0x0444)
|
||||
#define DMA2_CHANNEL5_BASE (AHBPERIPH_BASE + 0x0458)
|
||||
#define DMA2_CHANNEL6_BASE (AHBPERIPH_BASE + 0x046C)
|
||||
#define DMA2_CHANNEL7_BASE (AHBPERIPH_BASE + 0x0480)
|
||||
#define CRM_BASE (AHBPERIPH_BASE + 0x1000)
|
||||
#define FLASH_REG_BASE (AHBPERIPH_BASE + 0x2000)
|
||||
#define CRC_BASE (AHBPERIPH_BASE + 0x3000)
|
||||
#define SDIO2_BASE (AHBPERIPH_BASE + 0x3400)
|
||||
#define EMAC_BASE (AHBPERIPH_BASE + 0x8000)
|
||||
#define XMC_BANK1_REG_BASE (XMC_REG_BASE + 0x0000)
|
||||
#define XMC_BANK2_REG_BASE (XMC_REG_BASE + 0x0060)
|
||||
#define EMAC_MMC_BASE (EMAC_BASE + 0x0100)
|
||||
#define EMAC_PTP_BASE (EMAC_BASE + 0x0700)
|
||||
#define EMAC_DMA_BASE (EMAC_BASE + 0x1000)
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#include "at32f403a_407_def.h"
|
||||
#include "at32f403a_407_conf.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,163 @@
|
|||
/**
|
||||
**************************************************************************
|
||||
* @file at32f403a_407_conf.h
|
||||
* @brief at32f403a_407 config header file
|
||||
**************************************************************************
|
||||
*
|
||||
* Copyright (c) 2025, Artery Technology, All rights reserved.
|
||||
*
|
||||
* The software Board Support Package (BSP) that is made available to
|
||||
* download from Artery official website is the copyrighted work of Artery.
|
||||
* Artery authorizes customers to use, copy, and distribute the BSP
|
||||
* software and its related documentation for the purpose of design and
|
||||
* development in conjunction with Artery microcontrollers. Use of the
|
||||
* software is governed by this copyright notice and the following disclaimer.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
|
||||
* GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
|
||||
* TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
|
||||
* STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
|
||||
* INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
|
||||
*
|
||||
**************************************************************************
|
||||
*/
|
||||
|
||||
/* define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __AT32F403A_407_CONF_H
|
||||
#define __AT32F403A_407_CONF_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
|
||||
/**
|
||||
* @brief in the following line adjust the value of high speed external crystal (hext)
|
||||
* used in your application
|
||||
* tip: to avoid modifying this file each time you need to use different hext, you
|
||||
* can define the hext value in your toolchain compiler preprocessor.
|
||||
*/
|
||||
#if !defined HEXT_VALUE
|
||||
#define HEXT_VALUE ((uint32_t)8000000) /*!< value of the high speed external crystal in hz */
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief in the following line adjust the high speed external crystal (hext) startup
|
||||
* timeout value
|
||||
*/
|
||||
#define HEXT_STARTUP_TIMEOUT ((uint16_t)0x3000) /*!< time out for hext start up */
|
||||
#define HICK_VALUE ((uint32_t)8000000) /*!< value of the high speed internal clock in hz */
|
||||
#define LEXT_VALUE ((uint32_t)32768) /*!< value of the low speed external clock in hz */
|
||||
|
||||
/* module define -------------------------------------------------------------*/
|
||||
#define CRM_MODULE_ENABLED
|
||||
#define TMR_MODULE_ENABLED
|
||||
#define RTC_MODULE_ENABLED
|
||||
#define BPR_MODULE_ENABLED
|
||||
#define GPIO_MODULE_ENABLED
|
||||
#define I2C_MODULE_ENABLED
|
||||
#define USART_MODULE_ENABLED
|
||||
#define PWC_MODULE_ENABLED
|
||||
#define CAN_MODULE_ENABLED
|
||||
#define ADC_MODULE_ENABLED
|
||||
#define DAC_MODULE_ENABLED
|
||||
#define SPI_MODULE_ENABLED
|
||||
#define DMA_MODULE_ENABLED
|
||||
#define DEBUG_MODULE_ENABLED
|
||||
#define FLASH_MODULE_ENABLED
|
||||
#define CRC_MODULE_ENABLED
|
||||
#define WWDT_MODULE_ENABLED
|
||||
#define WDT_MODULE_ENABLED
|
||||
#define EXINT_MODULE_ENABLED
|
||||
#define SDIO_MODULE_ENABLED
|
||||
#define XMC_MODULE_ENABLED
|
||||
#define USB_MODULE_ENABLED
|
||||
#define ACC_MODULE_ENABLED
|
||||
#define MISC_MODULE_ENABLED
|
||||
#define EMAC_MODULE_ENABLED
|
||||
|
||||
/* includes ------------------------------------------------------------------*/
|
||||
#ifdef CRM_MODULE_ENABLED
|
||||
#include "at32f403a_407_crm.h"
|
||||
#endif
|
||||
#ifdef TMR_MODULE_ENABLED
|
||||
#include "at32f403a_407_tmr.h"
|
||||
#endif
|
||||
#ifdef RTC_MODULE_ENABLED
|
||||
#include "at32f403a_407_rtc.h"
|
||||
#endif
|
||||
#ifdef BPR_MODULE_ENABLED
|
||||
#include "at32f403a_407_bpr.h"
|
||||
#endif
|
||||
#ifdef GPIO_MODULE_ENABLED
|
||||
#include "at32f403a_407_gpio.h"
|
||||
#endif
|
||||
#ifdef I2C_MODULE_ENABLED
|
||||
#include "at32f403a_407_i2c.h"
|
||||
#endif
|
||||
#ifdef USART_MODULE_ENABLED
|
||||
#include "at32f403a_407_usart.h"
|
||||
#endif
|
||||
#ifdef PWC_MODULE_ENABLED
|
||||
#include "at32f403a_407_pwc.h"
|
||||
#endif
|
||||
#ifdef CAN_MODULE_ENABLED
|
||||
#include "at32f403a_407_can.h"
|
||||
#endif
|
||||
#ifdef ADC_MODULE_ENABLED
|
||||
#include "at32f403a_407_adc.h"
|
||||
#endif
|
||||
#ifdef DAC_MODULE_ENABLED
|
||||
#include "at32f403a_407_dac.h"
|
||||
#endif
|
||||
#ifdef SPI_MODULE_ENABLED
|
||||
#include "at32f403a_407_spi.h"
|
||||
#endif
|
||||
#ifdef DMA_MODULE_ENABLED
|
||||
#include "at32f403a_407_dma.h"
|
||||
#endif
|
||||
#ifdef DEBUG_MODULE_ENABLED
|
||||
#include "at32f403a_407_debug.h"
|
||||
#endif
|
||||
#ifdef FLASH_MODULE_ENABLED
|
||||
#include "at32f403a_407_flash.h"
|
||||
#endif
|
||||
#ifdef CRC_MODULE_ENABLED
|
||||
#include "at32f403a_407_crc.h"
|
||||
#endif
|
||||
#ifdef WWDT_MODULE_ENABLED
|
||||
#include "at32f403a_407_wwdt.h"
|
||||
#endif
|
||||
#ifdef WDT_MODULE_ENABLED
|
||||
#include "at32f403a_407_wdt.h"
|
||||
#endif
|
||||
#ifdef EXINT_MODULE_ENABLED
|
||||
#include "at32f403a_407_exint.h"
|
||||
#endif
|
||||
#ifdef SDIO_MODULE_ENABLED
|
||||
#include "at32f403a_407_sdio.h"
|
||||
#endif
|
||||
#ifdef XMC_MODULE_ENABLED
|
||||
#include "at32f403a_407_xmc.h"
|
||||
#endif
|
||||
#ifdef ACC_MODULE_ENABLED
|
||||
#include "at32f403a_407_acc.h"
|
||||
#endif
|
||||
#ifdef MISC_MODULE_ENABLED
|
||||
#include "at32f403a_407_misc.h"
|
||||
#endif
|
||||
#ifdef USB_MODULE_ENABLED
|
||||
#include "at32f403a_407_usb.h"
|
||||
#endif
|
||||
#ifdef EMAC_MODULE_ENABLED
|
||||
#include "at32f403a_407_emac.h"
|
||||
#endif
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __AT32F403A_407_CONF_H */
|
||||
|
||||
|
||||
|
|
@ -0,0 +1,168 @@
|
|||
/*
|
||||
*****************************************************************************
|
||||
**
|
||||
** File : AT32F403AxC_FLASH.ld
|
||||
**
|
||||
** Abstract : Linker script for AT32F403AxC Device with
|
||||
** 256KByte FLASH, 96KByte RAM
|
||||
**
|
||||
** Set heap size, stack size and stack location according
|
||||
** to application requirements.
|
||||
**
|
||||
** Set memory bank area and size if external memory is used.
|
||||
**
|
||||
** Target : Artery Tek AT32
|
||||
**
|
||||
** Environment : Arm gcc toolchain
|
||||
**
|
||||
*****************************************************************************
|
||||
*/
|
||||
|
||||
/* Entry Point */
|
||||
ENTRY(Reset_Handler)
|
||||
|
||||
/* Highest address of the user mode stack */
|
||||
_estack = 0x20018000; /* end of RAM */
|
||||
|
||||
/* Generate a link error if heap and stack don't fit into RAM */
|
||||
_Min_Heap_Size = 0x200; /* required amount of heap */
|
||||
_Min_Stack_Size = 0x400; /* required amount of stack */
|
||||
|
||||
/* Specify the memory areas */
|
||||
MEMORY
|
||||
{
|
||||
FLASH (rx) : ORIGIN = 0x08000000, LENGTH = 256K
|
||||
RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 96K
|
||||
SPIM (rx) : ORIGIN = 0x08400000, LENGTH = 16384K
|
||||
}
|
||||
|
||||
/* Define output sections */
|
||||
SECTIONS
|
||||
{
|
||||
/* The startup code goes first into FLASH */
|
||||
.isr_vector :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
KEEP(*(.isr_vector)) /* Startup code */
|
||||
. = ALIGN(4);
|
||||
} >FLASH
|
||||
|
||||
/* The program code and other data goes into FLASH */
|
||||
.text :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
*(.text) /* .text sections (code) */
|
||||
*(.text*) /* .text* sections (code) */
|
||||
*(.glue_7) /* glue arm to thumb code */
|
||||
*(.glue_7t) /* glue thumb to arm code */
|
||||
*(.eh_frame)
|
||||
|
||||
KEEP (*(.init))
|
||||
KEEP (*(.fini))
|
||||
|
||||
. = ALIGN(4);
|
||||
_etext = .; /* define a global symbols at end of code */
|
||||
} >FLASH
|
||||
|
||||
/* Constant data goes into FLASH */
|
||||
.rodata :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
*(.rodata) /* .rodata sections (constants, strings, etc.) */
|
||||
*(.rodata*) /* .rodata* sections (constants, strings, etc.) */
|
||||
. = ALIGN(4);
|
||||
} >FLASH
|
||||
|
||||
.ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH
|
||||
.ARM : {
|
||||
__exidx_start = .;
|
||||
*(.ARM.exidx*)
|
||||
__exidx_end = .;
|
||||
} >FLASH
|
||||
|
||||
.preinit_array :
|
||||
{
|
||||
PROVIDE_HIDDEN (__preinit_array_start = .);
|
||||
KEEP (*(.preinit_array*))
|
||||
PROVIDE_HIDDEN (__preinit_array_end = .);
|
||||
} >FLASH
|
||||
.init_array :
|
||||
{
|
||||
PROVIDE_HIDDEN (__init_array_start = .);
|
||||
KEEP (*(SORT(.init_array.*)))
|
||||
KEEP (*(.init_array*))
|
||||
PROVIDE_HIDDEN (__init_array_end = .);
|
||||
} >FLASH
|
||||
.fini_array :
|
||||
{
|
||||
PROVIDE_HIDDEN (__fini_array_start = .);
|
||||
KEEP (*(SORT(.fini_array.*)))
|
||||
KEEP (*(.fini_array*))
|
||||
PROVIDE_HIDDEN (__fini_array_end = .);
|
||||
} >FLASH
|
||||
|
||||
/* used by the startup to initialize data */
|
||||
_sidata = LOADADDR(.data);
|
||||
|
||||
/* Initialized data sections goes into RAM, load LMA copy after code */
|
||||
.data :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
_sdata = .; /* create a global symbol at data start */
|
||||
*(.data) /* .data sections */
|
||||
*(.data*) /* .data* sections */
|
||||
|
||||
. = ALIGN(4);
|
||||
_edata = .; /* define a global symbol at data end */
|
||||
} >RAM AT> FLASH
|
||||
|
||||
_spim_init_base = LOADADDR(.spim);
|
||||
_spim_init_length = SIZEOF(.spim);
|
||||
|
||||
.spim :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
_spim_start = .; /* create a global symbol at spim start */
|
||||
*(.spim) /* .spim sections */
|
||||
*(.spim*) /* .spim* sections */
|
||||
. = ALIGN(4);
|
||||
_spim_end = .; /* define a global symbols at end of spim */
|
||||
} >SPIM
|
||||
|
||||
/* Uninitialized data section */
|
||||
. = ALIGN(4);
|
||||
.bss :
|
||||
{
|
||||
/* This is used by the startup in order to initialize the .bss secion */
|
||||
_sbss = .; /* define a global symbol at bss start */
|
||||
__bss_start__ = _sbss;
|
||||
*(.bss)
|
||||
*(.bss*)
|
||||
*(COMMON)
|
||||
|
||||
. = ALIGN(4);
|
||||
_ebss = .; /* define a global symbol at bss end */
|
||||
__bss_end__ = _ebss;
|
||||
} >RAM
|
||||
|
||||
/* User_heap_stack section, used to check that there is enough RAM left */
|
||||
._user_heap_stack :
|
||||
{
|
||||
. = ALIGN(8);
|
||||
PROVIDE ( end = . );
|
||||
PROVIDE ( _end = . );
|
||||
. = . + _Min_Heap_Size;
|
||||
. = . + _Min_Stack_Size;
|
||||
. = ALIGN(8);
|
||||
} >RAM
|
||||
|
||||
/* Remove information from the standard libraries */
|
||||
/DISCARD/ :
|
||||
{
|
||||
libc.a ( * )
|
||||
libm.a ( * )
|
||||
libgcc.a ( * )
|
||||
}
|
||||
|
||||
.ARM.attributes 0 : { *(.ARM.attributes) }
|
||||
}
|
||||
|
|
@ -0,0 +1,168 @@
|
|||
/*
|
||||
*****************************************************************************
|
||||
**
|
||||
** File : AT32F403AxE_FLASH.ld
|
||||
**
|
||||
** Abstract : Linker script for AT32F403AxE Device with
|
||||
** 512KByte FLASH, 96KByte RAM
|
||||
**
|
||||
** Set heap size, stack size and stack location according
|
||||
** to application requirements.
|
||||
**
|
||||
** Set memory bank area and size if external memory is used.
|
||||
**
|
||||
** Target : Artery Tek AT32
|
||||
**
|
||||
** Environment : Arm gcc toolchain
|
||||
**
|
||||
*****************************************************************************
|
||||
*/
|
||||
|
||||
/* Entry Point */
|
||||
ENTRY(Reset_Handler)
|
||||
|
||||
/* Highest address of the user mode stack */
|
||||
_estack = 0x20018000; /* end of RAM */
|
||||
|
||||
/* Generate a link error if heap and stack don't fit into RAM */
|
||||
_Min_Heap_Size = 0x200; /* required amount of heap */
|
||||
_Min_Stack_Size = 0x400; /* required amount of stack */
|
||||
|
||||
/* Specify the memory areas */
|
||||
MEMORY
|
||||
{
|
||||
FLASH (rx) : ORIGIN = 0x08000000, LENGTH = 512K
|
||||
RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 96K
|
||||
SPIM (rx) : ORIGIN = 0x08400000, LENGTH = 16384K
|
||||
}
|
||||
|
||||
/* Define output sections */
|
||||
SECTIONS
|
||||
{
|
||||
/* The startup code goes first into FLASH */
|
||||
.isr_vector :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
KEEP(*(.isr_vector)) /* Startup code */
|
||||
. = ALIGN(4);
|
||||
} >FLASH
|
||||
|
||||
/* The program code and other data goes into FLASH */
|
||||
.text :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
*(.text) /* .text sections (code) */
|
||||
*(.text*) /* .text* sections (code) */
|
||||
*(.glue_7) /* glue arm to thumb code */
|
||||
*(.glue_7t) /* glue thumb to arm code */
|
||||
*(.eh_frame)
|
||||
|
||||
KEEP (*(.init))
|
||||
KEEP (*(.fini))
|
||||
|
||||
. = ALIGN(4);
|
||||
_etext = .; /* define a global symbols at end of code */
|
||||
} >FLASH
|
||||
|
||||
/* Constant data goes into FLASH */
|
||||
.rodata :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
*(.rodata) /* .rodata sections (constants, strings, etc.) */
|
||||
*(.rodata*) /* .rodata* sections (constants, strings, etc.) */
|
||||
. = ALIGN(4);
|
||||
} >FLASH
|
||||
|
||||
.ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH
|
||||
.ARM : {
|
||||
__exidx_start = .;
|
||||
*(.ARM.exidx*)
|
||||
__exidx_end = .;
|
||||
} >FLASH
|
||||
|
||||
.preinit_array :
|
||||
{
|
||||
PROVIDE_HIDDEN (__preinit_array_start = .);
|
||||
KEEP (*(.preinit_array*))
|
||||
PROVIDE_HIDDEN (__preinit_array_end = .);
|
||||
} >FLASH
|
||||
.init_array :
|
||||
{
|
||||
PROVIDE_HIDDEN (__init_array_start = .);
|
||||
KEEP (*(SORT(.init_array.*)))
|
||||
KEEP (*(.init_array*))
|
||||
PROVIDE_HIDDEN (__init_array_end = .);
|
||||
} >FLASH
|
||||
.fini_array :
|
||||
{
|
||||
PROVIDE_HIDDEN (__fini_array_start = .);
|
||||
KEEP (*(SORT(.fini_array.*)))
|
||||
KEEP (*(.fini_array*))
|
||||
PROVIDE_HIDDEN (__fini_array_end = .);
|
||||
} >FLASH
|
||||
|
||||
/* used by the startup to initialize data */
|
||||
_sidata = LOADADDR(.data);
|
||||
|
||||
/* Initialized data sections goes into RAM, load LMA copy after code */
|
||||
.data :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
_sdata = .; /* create a global symbol at data start */
|
||||
*(.data) /* .data sections */
|
||||
*(.data*) /* .data* sections */
|
||||
|
||||
. = ALIGN(4);
|
||||
_edata = .; /* define a global symbol at data end */
|
||||
} >RAM AT> FLASH
|
||||
|
||||
_spim_init_base = LOADADDR(.spim);
|
||||
_spim_init_length = SIZEOF(.spim);
|
||||
|
||||
.spim :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
_spim_start = .; /* create a global symbol at spim start */
|
||||
*(.spim) /* .spim sections */
|
||||
*(.spim*) /* .spim* sections */
|
||||
. = ALIGN(4);
|
||||
_spim_end = .; /* define a global symbols at end of spim */
|
||||
} >SPIM
|
||||
|
||||
/* Uninitialized data section */
|
||||
. = ALIGN(4);
|
||||
.bss :
|
||||
{
|
||||
/* This is used by the startup in order to initialize the .bss secion */
|
||||
_sbss = .; /* define a global symbol at bss start */
|
||||
__bss_start__ = _sbss;
|
||||
*(.bss)
|
||||
*(.bss*)
|
||||
*(COMMON)
|
||||
|
||||
. = ALIGN(4);
|
||||
_ebss = .; /* define a global symbol at bss end */
|
||||
__bss_end__ = _ebss;
|
||||
} >RAM
|
||||
|
||||
/* User_heap_stack section, used to check that there is enough RAM left */
|
||||
._user_heap_stack :
|
||||
{
|
||||
. = ALIGN(8);
|
||||
PROVIDE ( end = . );
|
||||
PROVIDE ( _end = . );
|
||||
. = . + _Min_Heap_Size;
|
||||
. = . + _Min_Stack_Size;
|
||||
. = ALIGN(8);
|
||||
} >RAM
|
||||
|
||||
/* Remove information from the standard libraries */
|
||||
/DISCARD/ :
|
||||
{
|
||||
libc.a ( * )
|
||||
libm.a ( * )
|
||||
libgcc.a ( * )
|
||||
}
|
||||
|
||||
.ARM.attributes 0 : { *(.ARM.attributes) }
|
||||
}
|
||||
|
|
@ -0,0 +1,168 @@
|
|||
/*
|
||||
*****************************************************************************
|
||||
**
|
||||
** File : AT32F403AxG_FLASH.ld
|
||||
**
|
||||
** Abstract : Linker script for AT32F403AxG Device with
|
||||
** 1000KByte FLASH, 96KByte RAM
|
||||
**
|
||||
** Set heap size, stack size and stack location according
|
||||
** to application requirements.
|
||||
**
|
||||
** Set memory bank area and size if external memory is used.
|
||||
**
|
||||
** Target : Artery Tek AT32
|
||||
**
|
||||
** Environment : Arm gcc toolchain
|
||||
**
|
||||
*****************************************************************************
|
||||
*/
|
||||
|
||||
/* Entry Point */
|
||||
ENTRY(Reset_Handler)
|
||||
|
||||
/* Highest address of the user mode stack */
|
||||
_estack = 0x20018000; /* end of RAM */
|
||||
|
||||
/* Generate a link error if heap and stack don't fit into RAM */
|
||||
_Min_Heap_Size = 0x200; /* required amount of heap */
|
||||
_Min_Stack_Size = 0x400; /* required amount of stack */
|
||||
|
||||
/* Specify the memory areas */
|
||||
MEMORY
|
||||
{
|
||||
FLASH (rx) : ORIGIN = 0x08000000, LENGTH = 1024K
|
||||
RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 96K
|
||||
SPIM (rx) : ORIGIN = 0x08400000, LENGTH = 16384K
|
||||
}
|
||||
|
||||
/* Define output sections */
|
||||
SECTIONS
|
||||
{
|
||||
/* The startup code goes first into FLASH */
|
||||
.isr_vector :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
KEEP(*(.isr_vector)) /* Startup code */
|
||||
. = ALIGN(4);
|
||||
} >FLASH
|
||||
|
||||
/* The program code and other data goes into FLASH */
|
||||
.text :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
*(.text) /* .text sections (code) */
|
||||
*(.text*) /* .text* sections (code) */
|
||||
*(.glue_7) /* glue arm to thumb code */
|
||||
*(.glue_7t) /* glue thumb to arm code */
|
||||
*(.eh_frame)
|
||||
|
||||
KEEP (*(.init))
|
||||
KEEP (*(.fini))
|
||||
|
||||
. = ALIGN(4);
|
||||
_etext = .; /* define a global symbols at end of code */
|
||||
} >FLASH
|
||||
|
||||
/* Constant data goes into FLASH */
|
||||
.rodata :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
*(.rodata) /* .rodata sections (constants, strings, etc.) */
|
||||
*(.rodata*) /* .rodata* sections (constants, strings, etc.) */
|
||||
. = ALIGN(4);
|
||||
} >FLASH
|
||||
|
||||
.ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH
|
||||
.ARM : {
|
||||
__exidx_start = .;
|
||||
*(.ARM.exidx*)
|
||||
__exidx_end = .;
|
||||
} >FLASH
|
||||
|
||||
.preinit_array :
|
||||
{
|
||||
PROVIDE_HIDDEN (__preinit_array_start = .);
|
||||
KEEP (*(.preinit_array*))
|
||||
PROVIDE_HIDDEN (__preinit_array_end = .);
|
||||
} >FLASH
|
||||
.init_array :
|
||||
{
|
||||
PROVIDE_HIDDEN (__init_array_start = .);
|
||||
KEEP (*(SORT(.init_array.*)))
|
||||
KEEP (*(.init_array*))
|
||||
PROVIDE_HIDDEN (__init_array_end = .);
|
||||
} >FLASH
|
||||
.fini_array :
|
||||
{
|
||||
PROVIDE_HIDDEN (__fini_array_start = .);
|
||||
KEEP (*(SORT(.fini_array.*)))
|
||||
KEEP (*(.fini_array*))
|
||||
PROVIDE_HIDDEN (__fini_array_end = .);
|
||||
} >FLASH
|
||||
|
||||
/* used by the startup to initialize data */
|
||||
_sidata = LOADADDR(.data);
|
||||
|
||||
/* Initialized data sections goes into RAM, load LMA copy after code */
|
||||
.data :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
_sdata = .; /* create a global symbol at data start */
|
||||
*(.data) /* .data sections */
|
||||
*(.data*) /* .data* sections */
|
||||
|
||||
. = ALIGN(4);
|
||||
_edata = .; /* define a global symbol at data end */
|
||||
} >RAM AT> FLASH
|
||||
|
||||
_spim_init_base = LOADADDR(.spim);
|
||||
_spim_init_length = SIZEOF(.spim);
|
||||
|
||||
.spim :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
_spim_start = .; /* create a global symbol at spim start */
|
||||
*(.spim) /* .spim sections */
|
||||
*(.spim*) /* .spim* sections */
|
||||
. = ALIGN(4);
|
||||
_spim_end = .; /* define a global symbols at end of spim */
|
||||
} >SPIM
|
||||
|
||||
/* Uninitialized data section */
|
||||
. = ALIGN(4);
|
||||
.bss :
|
||||
{
|
||||
/* This is used by the startup in order to initialize the .bss secion */
|
||||
_sbss = .; /* define a global symbol at bss start */
|
||||
__bss_start__ = _sbss;
|
||||
*(.bss)
|
||||
*(.bss*)
|
||||
*(COMMON)
|
||||
|
||||
. = ALIGN(4);
|
||||
_ebss = .; /* define a global symbol at bss end */
|
||||
__bss_end__ = _ebss;
|
||||
} >RAM
|
||||
|
||||
/* User_heap_stack section, used to check that there is enough RAM left */
|
||||
._user_heap_stack :
|
||||
{
|
||||
. = ALIGN(8);
|
||||
PROVIDE ( end = . );
|
||||
PROVIDE ( _end = . );
|
||||
. = . + _Min_Heap_Size;
|
||||
. = . + _Min_Stack_Size;
|
||||
. = ALIGN(8);
|
||||
} >RAM
|
||||
|
||||
/* Remove information from the standard libraries */
|
||||
/DISCARD/ :
|
||||
{
|
||||
libc.a ( * )
|
||||
libm.a ( * )
|
||||
libgcc.a ( * )
|
||||
}
|
||||
|
||||
.ARM.attributes 0 : { *(.ARM.attributes) }
|
||||
}
|
||||
|
|
@ -0,0 +1,168 @@
|
|||
/*
|
||||
*****************************************************************************
|
||||
**
|
||||
** File : AT32F407xC_FLASH.ld
|
||||
**
|
||||
** Abstract : Linker script for AT32F407xC Device with
|
||||
** 256KByte FLASH, 96KByte RAM
|
||||
**
|
||||
** Set heap size, stack size and stack location according
|
||||
** to application requirements.
|
||||
**
|
||||
** Set memory bank area and size if external memory is used.
|
||||
**
|
||||
** Target : Artery Tek AT32
|
||||
**
|
||||
** Environment : Arm gcc toolchain
|
||||
**
|
||||
*****************************************************************************
|
||||
*/
|
||||
|
||||
/* Entry Point */
|
||||
ENTRY(Reset_Handler)
|
||||
|
||||
/* Highest address of the user mode stack */
|
||||
_estack = 0x20018000; /* end of RAM */
|
||||
|
||||
/* Generate a link error if heap and stack don't fit into RAM */
|
||||
_Min_Heap_Size = 0x200; /* required amount of heap */
|
||||
_Min_Stack_Size = 0x400; /* required amount of stack */
|
||||
|
||||
/* Specify the memory areas */
|
||||
MEMORY
|
||||
{
|
||||
FLASH (rx) : ORIGIN = 0x08000000, LENGTH = 256K
|
||||
RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 96K
|
||||
SPIM (rx) : ORIGIN = 0x08400000, LENGTH = 16384K
|
||||
}
|
||||
|
||||
/* Define output sections */
|
||||
SECTIONS
|
||||
{
|
||||
/* The startup code goes first into FLASH */
|
||||
.isr_vector :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
KEEP(*(.isr_vector)) /* Startup code */
|
||||
. = ALIGN(4);
|
||||
} >FLASH
|
||||
|
||||
/* The program code and other data goes into FLASH */
|
||||
.text :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
*(.text) /* .text sections (code) */
|
||||
*(.text*) /* .text* sections (code) */
|
||||
*(.glue_7) /* glue arm to thumb code */
|
||||
*(.glue_7t) /* glue thumb to arm code */
|
||||
*(.eh_frame)
|
||||
|
||||
KEEP (*(.init))
|
||||
KEEP (*(.fini))
|
||||
|
||||
. = ALIGN(4);
|
||||
_etext = .; /* define a global symbols at end of code */
|
||||
} >FLASH
|
||||
|
||||
/* Constant data goes into FLASH */
|
||||
.rodata :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
*(.rodata) /* .rodata sections (constants, strings, etc.) */
|
||||
*(.rodata*) /* .rodata* sections (constants, strings, etc.) */
|
||||
. = ALIGN(4);
|
||||
} >FLASH
|
||||
|
||||
.ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH
|
||||
.ARM : {
|
||||
__exidx_start = .;
|
||||
*(.ARM.exidx*)
|
||||
__exidx_end = .;
|
||||
} >FLASH
|
||||
|
||||
.preinit_array :
|
||||
{
|
||||
PROVIDE_HIDDEN (__preinit_array_start = .);
|
||||
KEEP (*(.preinit_array*))
|
||||
PROVIDE_HIDDEN (__preinit_array_end = .);
|
||||
} >FLASH
|
||||
.init_array :
|
||||
{
|
||||
PROVIDE_HIDDEN (__init_array_start = .);
|
||||
KEEP (*(SORT(.init_array.*)))
|
||||
KEEP (*(.init_array*))
|
||||
PROVIDE_HIDDEN (__init_array_end = .);
|
||||
} >FLASH
|
||||
.fini_array :
|
||||
{
|
||||
PROVIDE_HIDDEN (__fini_array_start = .);
|
||||
KEEP (*(SORT(.fini_array.*)))
|
||||
KEEP (*(.fini_array*))
|
||||
PROVIDE_HIDDEN (__fini_array_end = .);
|
||||
} >FLASH
|
||||
|
||||
/* used by the startup to initialize data */
|
||||
_sidata = LOADADDR(.data);
|
||||
|
||||
/* Initialized data sections goes into RAM, load LMA copy after code */
|
||||
.data :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
_sdata = .; /* create a global symbol at data start */
|
||||
*(.data) /* .data sections */
|
||||
*(.data*) /* .data* sections */
|
||||
|
||||
. = ALIGN(4);
|
||||
_edata = .; /* define a global symbol at data end */
|
||||
} >RAM AT> FLASH
|
||||
|
||||
_spim_init_base = LOADADDR(.spim);
|
||||
_spim_init_length = SIZEOF(.spim);
|
||||
|
||||
.spim :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
_spim_start = .; /* create a global symbol at spim start */
|
||||
*(.spim) /* .spim sections */
|
||||
*(.spim*) /* .spim* sections */
|
||||
. = ALIGN(4);
|
||||
_spim_end = .; /* define a global symbols at end of spim */
|
||||
} >SPIM
|
||||
|
||||
/* Uninitialized data section */
|
||||
. = ALIGN(4);
|
||||
.bss :
|
||||
{
|
||||
/* This is used by the startup in order to initialize the .bss secion */
|
||||
_sbss = .; /* define a global symbol at bss start */
|
||||
__bss_start__ = _sbss;
|
||||
*(.bss)
|
||||
*(.bss*)
|
||||
*(COMMON)
|
||||
|
||||
. = ALIGN(4);
|
||||
_ebss = .; /* define a global symbol at bss end */
|
||||
__bss_end__ = _ebss;
|
||||
} >RAM
|
||||
|
||||
/* User_heap_stack section, used to check that there is enough RAM left */
|
||||
._user_heap_stack :
|
||||
{
|
||||
. = ALIGN(8);
|
||||
PROVIDE ( end = . );
|
||||
PROVIDE ( _end = . );
|
||||
. = . + _Min_Heap_Size;
|
||||
. = . + _Min_Stack_Size;
|
||||
. = ALIGN(8);
|
||||
} >RAM
|
||||
|
||||
/* Remove information from the standard libraries */
|
||||
/DISCARD/ :
|
||||
{
|
||||
libc.a ( * )
|
||||
libm.a ( * )
|
||||
libgcc.a ( * )
|
||||
}
|
||||
|
||||
.ARM.attributes 0 : { *(.ARM.attributes) }
|
||||
}
|
||||
|
|
@ -0,0 +1,168 @@
|
|||
/*
|
||||
*****************************************************************************
|
||||
**
|
||||
** File : AT32F407xE_FLASH.ld
|
||||
**
|
||||
** Abstract : Linker script for AT32F407xE Device with
|
||||
** 512KByte FLASH, 96KByte RAM
|
||||
**
|
||||
** Set heap size, stack size and stack location according
|
||||
** to application requirements.
|
||||
**
|
||||
** Set memory bank area and size if external memory is used.
|
||||
**
|
||||
** Target : Artery Tek AT32
|
||||
**
|
||||
** Environment : Arm gcc toolchain
|
||||
**
|
||||
*****************************************************************************
|
||||
*/
|
||||
|
||||
/* Entry Point */
|
||||
ENTRY(Reset_Handler)
|
||||
|
||||
/* Highest address of the user mode stack */
|
||||
_estack = 0x20018000; /* end of RAM */
|
||||
|
||||
/* Generate a link error if heap and stack don't fit into RAM */
|
||||
_Min_Heap_Size = 0x200; /* required amount of heap */
|
||||
_Min_Stack_Size = 0x400; /* required amount of stack */
|
||||
|
||||
/* Specify the memory areas */
|
||||
MEMORY
|
||||
{
|
||||
FLASH (rx) : ORIGIN = 0x08000000, LENGTH = 512K
|
||||
RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 96K
|
||||
SPIM (rx) : ORIGIN = 0x08400000, LENGTH = 16384K
|
||||
}
|
||||
|
||||
/* Define output sections */
|
||||
SECTIONS
|
||||
{
|
||||
/* The startup code goes first into FLASH */
|
||||
.isr_vector :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
KEEP(*(.isr_vector)) /* Startup code */
|
||||
. = ALIGN(4);
|
||||
} >FLASH
|
||||
|
||||
/* The program code and other data goes into FLASH */
|
||||
.text :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
*(.text) /* .text sections (code) */
|
||||
*(.text*) /* .text* sections (code) */
|
||||
*(.glue_7) /* glue arm to thumb code */
|
||||
*(.glue_7t) /* glue thumb to arm code */
|
||||
*(.eh_frame)
|
||||
|
||||
KEEP (*(.init))
|
||||
KEEP (*(.fini))
|
||||
|
||||
. = ALIGN(4);
|
||||
_etext = .; /* define a global symbols at end of code */
|
||||
} >FLASH
|
||||
|
||||
/* Constant data goes into FLASH */
|
||||
.rodata :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
*(.rodata) /* .rodata sections (constants, strings, etc.) */
|
||||
*(.rodata*) /* .rodata* sections (constants, strings, etc.) */
|
||||
. = ALIGN(4);
|
||||
} >FLASH
|
||||
|
||||
.ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH
|
||||
.ARM : {
|
||||
__exidx_start = .;
|
||||
*(.ARM.exidx*)
|
||||
__exidx_end = .;
|
||||
} >FLASH
|
||||
|
||||
.preinit_array :
|
||||
{
|
||||
PROVIDE_HIDDEN (__preinit_array_start = .);
|
||||
KEEP (*(.preinit_array*))
|
||||
PROVIDE_HIDDEN (__preinit_array_end = .);
|
||||
} >FLASH
|
||||
.init_array :
|
||||
{
|
||||
PROVIDE_HIDDEN (__init_array_start = .);
|
||||
KEEP (*(SORT(.init_array.*)))
|
||||
KEEP (*(.init_array*))
|
||||
PROVIDE_HIDDEN (__init_array_end = .);
|
||||
} >FLASH
|
||||
.fini_array :
|
||||
{
|
||||
PROVIDE_HIDDEN (__fini_array_start = .);
|
||||
KEEP (*(SORT(.fini_array.*)))
|
||||
KEEP (*(.fini_array*))
|
||||
PROVIDE_HIDDEN (__fini_array_end = .);
|
||||
} >FLASH
|
||||
|
||||
/* used by the startup to initialize data */
|
||||
_sidata = LOADADDR(.data);
|
||||
|
||||
/* Initialized data sections goes into RAM, load LMA copy after code */
|
||||
.data :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
_sdata = .; /* create a global symbol at data start */
|
||||
*(.data) /* .data sections */
|
||||
*(.data*) /* .data* sections */
|
||||
|
||||
. = ALIGN(4);
|
||||
_edata = .; /* define a global symbol at data end */
|
||||
} >RAM AT> FLASH
|
||||
|
||||
_spim_init_base = LOADADDR(.spim);
|
||||
_spim_init_length = SIZEOF(.spim);
|
||||
|
||||
.spim :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
_spim_start = .; /* create a global symbol at spim start */
|
||||
*(.spim) /* .spim sections */
|
||||
*(.spim*) /* .spim* sections */
|
||||
. = ALIGN(4);
|
||||
_spim_end = .; /* define a global symbols at end of spim */
|
||||
} >SPIM
|
||||
|
||||
/* Uninitialized data section */
|
||||
. = ALIGN(4);
|
||||
.bss :
|
||||
{
|
||||
/* This is used by the startup in order to initialize the .bss secion */
|
||||
_sbss = .; /* define a global symbol at bss start */
|
||||
__bss_start__ = _sbss;
|
||||
*(.bss)
|
||||
*(.bss*)
|
||||
*(COMMON)
|
||||
|
||||
. = ALIGN(4);
|
||||
_ebss = .; /* define a global symbol at bss end */
|
||||
__bss_end__ = _ebss;
|
||||
} >RAM
|
||||
|
||||
/* User_heap_stack section, used to check that there is enough RAM left */
|
||||
._user_heap_stack :
|
||||
{
|
||||
. = ALIGN(8);
|
||||
PROVIDE ( end = . );
|
||||
PROVIDE ( _end = . );
|
||||
. = . + _Min_Heap_Size;
|
||||
. = . + _Min_Stack_Size;
|
||||
. = ALIGN(8);
|
||||
} >RAM
|
||||
|
||||
/* Remove information from the standard libraries */
|
||||
/DISCARD/ :
|
||||
{
|
||||
libc.a ( * )
|
||||
libm.a ( * )
|
||||
libgcc.a ( * )
|
||||
}
|
||||
|
||||
.ARM.attributes 0 : { *(.ARM.attributes) }
|
||||
}
|
||||
|
|
@ -0,0 +1,168 @@
|
|||
/*
|
||||
*****************************************************************************
|
||||
**
|
||||
** File : AT32F407xG_FLASH.ld
|
||||
**
|
||||
** Abstract : Linker script for AT32F407xG Device with
|
||||
** 1000KByte FLASH, 96KByte RAM
|
||||
**
|
||||
** Set heap size, stack size and stack location according
|
||||
** to application requirements.
|
||||
**
|
||||
** Set memory bank area and size if external memory is used.
|
||||
**
|
||||
** Target : Artery Tek AT32
|
||||
**
|
||||
** Environment : Arm gcc toolchain
|
||||
**
|
||||
*****************************************************************************
|
||||
*/
|
||||
|
||||
/* Entry Point */
|
||||
ENTRY(Reset_Handler)
|
||||
|
||||
/* Highest address of the user mode stack */
|
||||
_estack = 0x20018000; /* end of RAM */
|
||||
|
||||
/* Generate a link error if heap and stack don't fit into RAM */
|
||||
_Min_Heap_Size = 0x200; /* required amount of heap */
|
||||
_Min_Stack_Size = 0x400; /* required amount of stack */
|
||||
|
||||
/* Specify the memory areas */
|
||||
MEMORY
|
||||
{
|
||||
FLASH (rx) : ORIGIN = 0x08000000, LENGTH = 1024K
|
||||
RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 96K
|
||||
SPIM (rx) : ORIGIN = 0x08400000, LENGTH = 16384K
|
||||
}
|
||||
|
||||
/* Define output sections */
|
||||
SECTIONS
|
||||
{
|
||||
/* The startup code goes first into FLASH */
|
||||
.isr_vector :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
KEEP(*(.isr_vector)) /* Startup code */
|
||||
. = ALIGN(4);
|
||||
} >FLASH
|
||||
|
||||
/* The program code and other data goes into FLASH */
|
||||
.text :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
*(.text) /* .text sections (code) */
|
||||
*(.text*) /* .text* sections (code) */
|
||||
*(.glue_7) /* glue arm to thumb code */
|
||||
*(.glue_7t) /* glue thumb to arm code */
|
||||
*(.eh_frame)
|
||||
|
||||
KEEP (*(.init))
|
||||
KEEP (*(.fini))
|
||||
|
||||
. = ALIGN(4);
|
||||
_etext = .; /* define a global symbols at end of code */
|
||||
} >FLASH
|
||||
|
||||
/* Constant data goes into FLASH */
|
||||
.rodata :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
*(.rodata) /* .rodata sections (constants, strings, etc.) */
|
||||
*(.rodata*) /* .rodata* sections (constants, strings, etc.) */
|
||||
. = ALIGN(4);
|
||||
} >FLASH
|
||||
|
||||
.ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) } >FLASH
|
||||
.ARM : {
|
||||
__exidx_start = .;
|
||||
*(.ARM.exidx*)
|
||||
__exidx_end = .;
|
||||
} >FLASH
|
||||
|
||||
.preinit_array :
|
||||
{
|
||||
PROVIDE_HIDDEN (__preinit_array_start = .);
|
||||
KEEP (*(.preinit_array*))
|
||||
PROVIDE_HIDDEN (__preinit_array_end = .);
|
||||
} >FLASH
|
||||
.init_array :
|
||||
{
|
||||
PROVIDE_HIDDEN (__init_array_start = .);
|
||||
KEEP (*(SORT(.init_array.*)))
|
||||
KEEP (*(.init_array*))
|
||||
PROVIDE_HIDDEN (__init_array_end = .);
|
||||
} >FLASH
|
||||
.fini_array :
|
||||
{
|
||||
PROVIDE_HIDDEN (__fini_array_start = .);
|
||||
KEEP (*(SORT(.fini_array.*)))
|
||||
KEEP (*(.fini_array*))
|
||||
PROVIDE_HIDDEN (__fini_array_end = .);
|
||||
} >FLASH
|
||||
|
||||
/* used by the startup to initialize data */
|
||||
_sidata = LOADADDR(.data);
|
||||
|
||||
/* Initialized data sections goes into RAM, load LMA copy after code */
|
||||
.data :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
_sdata = .; /* create a global symbol at data start */
|
||||
*(.data) /* .data sections */
|
||||
*(.data*) /* .data* sections */
|
||||
|
||||
. = ALIGN(4);
|
||||
_edata = .; /* define a global symbol at data end */
|
||||
} >RAM AT> FLASH
|
||||
|
||||
_spim_init_base = LOADADDR(.spim);
|
||||
_spim_init_length = SIZEOF(.spim);
|
||||
|
||||
.spim :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
_spim_start = .; /* create a global symbol at spim start */
|
||||
*(.spim) /* .spim sections */
|
||||
*(.spim*) /* .spim* sections */
|
||||
. = ALIGN(4);
|
||||
_spim_end = .; /* define a global symbols at end of spim */
|
||||
} >SPIM
|
||||
|
||||
/* Uninitialized data section */
|
||||
. = ALIGN(4);
|
||||
.bss :
|
||||
{
|
||||
/* This is used by the startup in order to initialize the .bss secion */
|
||||
_sbss = .; /* define a global symbol at bss start */
|
||||
__bss_start__ = _sbss;
|
||||
*(.bss)
|
||||
*(.bss*)
|
||||
*(COMMON)
|
||||
|
||||
. = ALIGN(4);
|
||||
_ebss = .; /* define a global symbol at bss end */
|
||||
__bss_end__ = _ebss;
|
||||
} >RAM
|
||||
|
||||
/* User_heap_stack section, used to check that there is enough RAM left */
|
||||
._user_heap_stack :
|
||||
{
|
||||
. = ALIGN(8);
|
||||
PROVIDE ( end = . );
|
||||
PROVIDE ( _end = . );
|
||||
. = . + _Min_Heap_Size;
|
||||
. = . + _Min_Stack_Size;
|
||||
. = ALIGN(8);
|
||||
} >RAM
|
||||
|
||||
/* Remove information from the standard libraries */
|
||||
/DISCARD/ :
|
||||
{
|
||||
libc.a ( * )
|
||||
libm.a ( * )
|
||||
libgcc.a ( * )
|
||||
}
|
||||
|
||||
.ARM.attributes 0 : { *(.ARM.attributes) }
|
||||
}
|
||||
|
|
@ -0,0 +1,478 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file startup_at32f403a_407.s
|
||||
* @brief at32f403a_407xx devices vector table for gcc toolchain.
|
||||
* this module performs:
|
||||
* - set the initial sp
|
||||
* - set the initial pc == reset_handler,
|
||||
* - set the vector table entries with the exceptions isr address
|
||||
* - configure the clock system and the external sram to
|
||||
* be used as data memory (optional, to be enabled by user)
|
||||
* - branches to main in the c library (which eventually
|
||||
* calls main()).
|
||||
* after reset the cortex-m4 processor is in thread mode,
|
||||
* priority is privileged, and the stack is set to main.
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
.syntax unified
|
||||
.cpu cortex-m4
|
||||
.fpu softvfp
|
||||
.thumb
|
||||
|
||||
.global g_pfnVectors
|
||||
.global Default_Handler
|
||||
|
||||
/* start address for the initialization values of the .data section.
|
||||
defined in linker script */
|
||||
.word _sidata
|
||||
/* start address for the .data section. defined in linker script */
|
||||
.word _sdata
|
||||
/* end address for the .data section. defined in linker script */
|
||||
.word _edata
|
||||
/* start address for the .bss section. defined in linker script */
|
||||
.word _sbss
|
||||
/* end address for the .bss section. defined in linker script */
|
||||
.word _ebss
|
||||
/* stack used for SystemInit_ExtMemCtl; always internal RAM used */
|
||||
|
||||
/**
|
||||
* @brief This is the code that gets called when the processor first
|
||||
* starts execution following a reset event. Only the absolutely
|
||||
* necessary set is performed, after which the application
|
||||
* supplied main() routine is called.
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
|
||||
.section .text.Reset_Handler
|
||||
.weak Reset_Handler
|
||||
.type Reset_Handler, %function
|
||||
Reset_Handler:
|
||||
|
||||
/* Copy the data segment initializers from flash to SRAM */
|
||||
movs r1, #0
|
||||
b LoopCopyDataInit
|
||||
|
||||
CopyDataInit:
|
||||
ldr r3, =_sidata
|
||||
ldr r3, [r3, r1]
|
||||
str r3, [r0, r1]
|
||||
adds r1, r1, #4
|
||||
|
||||
LoopCopyDataInit:
|
||||
ldr r0, =_sdata
|
||||
ldr r3, =_edata
|
||||
adds r2, r0, r1
|
||||
cmp r2, r3
|
||||
bcc CopyDataInit
|
||||
ldr r2, =_sbss
|
||||
b LoopFillZerobss
|
||||
/* Zero fill the bss segment. */
|
||||
FillZerobss:
|
||||
movs r3, #0
|
||||
str r3, [r2], #4
|
||||
|
||||
LoopFillZerobss:
|
||||
ldr r3, = _ebss
|
||||
cmp r2, r3
|
||||
bcc FillZerobss
|
||||
|
||||
/* Call the clock system intitialization function.*/
|
||||
bl SystemInit
|
||||
/* Call static constructors */
|
||||
bl __libc_init_array
|
||||
/* Call the application's entry point.*/
|
||||
bl main
|
||||
bx lr
|
||||
.size Reset_Handler, .-Reset_Handler
|
||||
|
||||
/**
|
||||
* @brief This is the code that gets called when the processor receives an
|
||||
* unexpected interrupt. This simply enters an infinite loop, preserving
|
||||
* the system state for examination by a debugger.
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
.section .text.Default_Handler,"ax",%progbits
|
||||
Default_Handler:
|
||||
Infinite_Loop:
|
||||
b Infinite_Loop
|
||||
.size Default_Handler, .-Default_Handler
|
||||
/******************************************************************************
|
||||
*
|
||||
* The minimal vector table for a Cortex M3. Note that the proper constructs
|
||||
* must be placed on this to ensure that it ends up at physical address
|
||||
* 0x0000.0000.
|
||||
*
|
||||
*******************************************************************************/
|
||||
.section .isr_vector,"a",%progbits
|
||||
.type g_pfnVectors, %object
|
||||
.size g_pfnVectors, .-g_pfnVectors
|
||||
|
||||
|
||||
g_pfnVectors:
|
||||
.word _estack
|
||||
.word Reset_Handler
|
||||
.word NMI_Handler
|
||||
.word HardFault_Handler
|
||||
.word MemManage_Handler
|
||||
.word BusFault_Handler
|
||||
.word UsageFault_Handler
|
||||
.word 0
|
||||
.word 0
|
||||
.word 0
|
||||
.word 0
|
||||
.word SVC_Handler
|
||||
.word DebugMon_Handler
|
||||
.word 0
|
||||
.word PendSV_Handler
|
||||
.word SysTick_Handler
|
||||
|
||||
/* External Interrupts */
|
||||
.word WWDT_IRQHandler /* Window Watchdog Timer */
|
||||
.word PVM_IRQHandler /* PVM through EXINT Line detect */
|
||||
.word TAMPER_IRQHandler /* Tamper */
|
||||
.word RTC_IRQHandler /* RTC */
|
||||
.word FLASH_IRQHandler /* Flash */
|
||||
.word CRM_IRQHandler /* CRM */
|
||||
.word EXINT0_IRQHandler /* EXINT Line 0 */
|
||||
.word EXINT1_IRQHandler /* EXINT Line 1 */
|
||||
.word EXINT2_IRQHandler /* EXINT Line 2 */
|
||||
.word EXINT3_IRQHandler /* EXINT Line 3 */
|
||||
.word EXINT4_IRQHandler /* EXINT Line 4 */
|
||||
.word DMA1_Channel1_IRQHandler /* DMA1 Channel 1 */
|
||||
.word DMA1_Channel2_IRQHandler /* DMA1 Channel 2 */
|
||||
.word DMA1_Channel3_IRQHandler /* DMA1 Channel 3 */
|
||||
.word DMA1_Channel4_IRQHandler /* DMA1 Channel 4 */
|
||||
.word DMA1_Channel5_IRQHandler /* DMA1 Channel 5 */
|
||||
.word DMA1_Channel6_IRQHandler /* DMA1 Channel 6 */
|
||||
.word DMA1_Channel7_IRQHandler /* DMA1 Channel 7 */
|
||||
.word ADC1_2_IRQHandler /* ADC1 & ADC2 */
|
||||
.word USBFS_H_CAN1_TX_IRQHandler /* USB High Priority or CAN1 TX */
|
||||
.word USBFS_L_CAN1_RX0_IRQHandler /* USB Low Priority or CAN1 RX0 */
|
||||
.word CAN1_RX1_IRQHandler /* CAN1 RX1 */
|
||||
.word CAN1_SE_IRQHandler /* CAN1 SE */
|
||||
.word EXINT9_5_IRQHandler /* EXINT Line [9:5] */
|
||||
.word TMR1_BRK_TMR9_IRQHandler /* TMR1 Brake and TMR9 */
|
||||
.word TMR1_OVF_TMR10_IRQHandler /* TMR1 Overflow and TMR10 */
|
||||
.word TMR1_TRG_HALL_TMR11_IRQHandler /* TMR1 Trigger and hall and TMR11 */
|
||||
.word TMR1_CH_IRQHandler /* TMR1 Channel */
|
||||
.word TMR2_GLOBAL_IRQHandler /* TMR2 */
|
||||
.word TMR3_GLOBAL_IRQHandler /* TMR3 */
|
||||
.word TMR4_GLOBAL_IRQHandler /* TMR4 */
|
||||
.word I2C1_EVT_IRQHandler /* I2C1 Event */
|
||||
.word I2C1_ERR_IRQHandler /* I2C1 Error */
|
||||
.word I2C2_EVT_IRQHandler /* I2C2 Event */
|
||||
.word I2C2_ERR_IRQHandler /* I2C2 Error */
|
||||
.word SPI1_IRQHandler /* SPI1 */
|
||||
.word SPI2_I2S2EXT_IRQHandler /* SPI2 & I2S2EXT */
|
||||
.word USART1_IRQHandler /* USART1 */
|
||||
.word USART2_IRQHandler /* USART2 */
|
||||
.word USART3_IRQHandler /* USART3 */
|
||||
.word EXINT15_10_IRQHandler /* EXINT Line [15:10] */
|
||||
.word RTCAlarm_IRQHandler /* RTC Alarm through EXINT Line */
|
||||
.word USBFSWakeUp_IRQHandler /* USB Wakeup from suspend */
|
||||
.word TMR8_BRK_TMR12_IRQHandler /* TMR8 Brake and TMR12 */
|
||||
.word TMR8_OVF_TMR13_IRQHandler /* TMR8 Overflow and TMR13 */
|
||||
.word TMR8_TRG_HALL_TMR14_IRQHandler /* TMR8 Trigger and hall and TMR14 */
|
||||
.word TMR8_CH_IRQHandler /* TMR8 Channel */
|
||||
.word ADC3_IRQHandler /* ADC3 */
|
||||
.word XMC_IRQHandler /* XMC */
|
||||
.word SDIO1_IRQHandler /* SDIO1 */
|
||||
.word TMR5_GLOBAL_IRQHandler /* TMR5 */
|
||||
.word SPI3_I2S3EXT_IRQHandler /* SPI3 & I2S3EXT */
|
||||
.word UART4_IRQHandler /* UART4 */
|
||||
.word UART5_IRQHandler /* UART5 */
|
||||
.word TMR6_GLOBAL_IRQHandler /* TMR6 */
|
||||
.word TMR7_GLOBAL_IRQHandler /* TMR7 */
|
||||
.word DMA2_Channel1_IRQHandler /* DMA2 Channel1 */
|
||||
.word DMA2_Channel2_IRQHandler /* DMA2 Channel2 */
|
||||
.word DMA2_Channel3_IRQHandler /* DMA2 Channel3 */
|
||||
.word DMA2_Channel4_5_IRQHandler /* DMA2 Channel4 & Channel5 */
|
||||
.word SDIO2_IRQHandler /* SDIO2 */
|
||||
.word I2C3_EVT_IRQHandler /* I2C3 Event */
|
||||
.word I2C3_ERR_IRQHandler /* I2C3 Error */
|
||||
.word SPI4_IRQHandler /* SPI4 */
|
||||
.word 0 /* Reserved */
|
||||
.word 0 /* Reserved */
|
||||
.word 0 /* Reserved */
|
||||
.word 0 /* Reserved */
|
||||
.word CAN2_TX_IRQHandler /* CAN2 TX */
|
||||
.word CAN2_RX0_IRQHandler /* CAN2 RX0 */
|
||||
.word CAN2_RX1_IRQHandler /* CAN2 RX1 */
|
||||
.word CAN2_SE_IRQHandler /* CAN2 SE */
|
||||
.word ACC_IRQHandler /* ACC */
|
||||
.word USBFS_MAPH_IRQHandler /* USB Map HP */
|
||||
.word USBFS_MAPL_IRQHandler /* USB Map LP */
|
||||
.word DMA2_Channel6_7_IRQHandler /* DMA2 Channel6 & Channel7 */
|
||||
.word USART6_IRQHandler /* USART6 */
|
||||
.word UART7_IRQHandler /* UART7 */
|
||||
.word UART8_IRQHandler /* UART8 */
|
||||
.word EMAC_IRQHandler /* EMAC */
|
||||
.word EMAC_WKUP_IRQHandler /* EMAC Wakeup */
|
||||
|
||||
/*******************************************************************************
|
||||
*
|
||||
* Provide weak aliases for each Exception handler to the Default_Handler.
|
||||
* As they are weak aliases, any function with the same name will override
|
||||
* this definition.
|
||||
*
|
||||
*******************************************************************************/
|
||||
.weak NMI_Handler
|
||||
.thumb_set NMI_Handler,Default_Handler
|
||||
|
||||
.weak HardFault_Handler
|
||||
.thumb_set HardFault_Handler,Default_Handler
|
||||
|
||||
.weak MemManage_Handler
|
||||
.thumb_set MemManage_Handler,Default_Handler
|
||||
|
||||
.weak BusFault_Handler
|
||||
.thumb_set BusFault_Handler,Default_Handler
|
||||
|
||||
.weak UsageFault_Handler
|
||||
.thumb_set UsageFault_Handler,Default_Handler
|
||||
|
||||
.weak SVC_Handler
|
||||
.thumb_set SVC_Handler,Default_Handler
|
||||
|
||||
.weak DebugMon_Handler
|
||||
.thumb_set DebugMon_Handler,Default_Handler
|
||||
|
||||
.weak PendSV_Handler
|
||||
.thumb_set PendSV_Handler,Default_Handler
|
||||
|
||||
.weak SysTick_Handler
|
||||
.thumb_set SysTick_Handler,Default_Handler
|
||||
|
||||
.weak WWDT_IRQHandler
|
||||
.thumb_set WWDT_IRQHandler,Default_Handler
|
||||
|
||||
.weak PVM_IRQHandler
|
||||
.thumb_set PVM_IRQHandler,Default_Handler
|
||||
|
||||
.weak TAMPER_IRQHandler
|
||||
.thumb_set TAMPER_IRQHandler,Default_Handler
|
||||
|
||||
.weak RTC_IRQHandler
|
||||
.thumb_set RTC_IRQHandler,Default_Handler
|
||||
|
||||
.weak FLASH_IRQHandler
|
||||
.thumb_set FLASH_IRQHandler,Default_Handler
|
||||
|
||||
.weak CRM_IRQHandler
|
||||
.thumb_set CRM_IRQHandler,Default_Handler
|
||||
|
||||
.weak EXINT0_IRQHandler
|
||||
.thumb_set EXINT0_IRQHandler,Default_Handler
|
||||
|
||||
.weak EXINT1_IRQHandler
|
||||
.thumb_set EXINT1_IRQHandler,Default_Handler
|
||||
|
||||
.weak EXINT2_IRQHandler
|
||||
.thumb_set EXINT2_IRQHandler,Default_Handler
|
||||
|
||||
.weak EXINT3_IRQHandler
|
||||
.thumb_set EXINT3_IRQHandler,Default_Handler
|
||||
|
||||
.weak EXINT4_IRQHandler
|
||||
.thumb_set EXINT4_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA1_Channel1_IRQHandler
|
||||
.thumb_set DMA1_Channel1_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA1_Channel2_IRQHandler
|
||||
.thumb_set DMA1_Channel2_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA1_Channel3_IRQHandler
|
||||
.thumb_set DMA1_Channel3_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA1_Channel4_IRQHandler
|
||||
.thumb_set DMA1_Channel4_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA1_Channel5_IRQHandler
|
||||
.thumb_set DMA1_Channel5_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA1_Channel6_IRQHandler
|
||||
.thumb_set DMA1_Channel6_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA1_Channel7_IRQHandler
|
||||
.thumb_set DMA1_Channel7_IRQHandler,Default_Handler
|
||||
|
||||
.weak ADC1_2_IRQHandler
|
||||
.thumb_set ADC1_2_IRQHandler,Default_Handler
|
||||
|
||||
.weak USBFS_H_CAN1_TX_IRQHandler
|
||||
.thumb_set USBFS_H_CAN1_TX_IRQHandler,Default_Handler
|
||||
|
||||
.weak USBFS_L_CAN1_RX0_IRQHandler
|
||||
.thumb_set USBFS_L_CAN1_RX0_IRQHandler,Default_Handler
|
||||
|
||||
.weak CAN1_RX1_IRQHandler
|
||||
.thumb_set CAN1_RX1_IRQHandler,Default_Handler
|
||||
|
||||
.weak CAN1_SE_IRQHandler
|
||||
.thumb_set CAN1_SE_IRQHandler,Default_Handler
|
||||
|
||||
.weak EXINT9_5_IRQHandler
|
||||
.thumb_set EXINT9_5_IRQHandler,Default_Handler
|
||||
|
||||
.weak TMR1_BRK_TMR9_IRQHandler
|
||||
.thumb_set TMR1_BRK_TMR9_IRQHandler,Default_Handler
|
||||
|
||||
.weak TMR1_OVF_TMR10_IRQHandler
|
||||
.thumb_set TMR1_OVF_TMR10_IRQHandler,Default_Handler
|
||||
|
||||
.weak TMR1_TRG_HALL_TMR11_IRQHandler
|
||||
.thumb_set TMR1_TRG_HALL_TMR11_IRQHandler,Default_Handler
|
||||
|
||||
.weak TMR1_CH_IRQHandler
|
||||
.thumb_set TMR1_CH_IRQHandler,Default_Handler
|
||||
|
||||
.weak TMR2_GLOBAL_IRQHandler
|
||||
.thumb_set TMR2_GLOBAL_IRQHandler,Default_Handler
|
||||
|
||||
.weak TMR3_GLOBAL_IRQHandler
|
||||
.thumb_set TMR3_GLOBAL_IRQHandler,Default_Handler
|
||||
|
||||
.weak TMR4_GLOBAL_IRQHandler
|
||||
.thumb_set TMR4_GLOBAL_IRQHandler,Default_Handler
|
||||
|
||||
.weak I2C1_EVT_IRQHandler
|
||||
.thumb_set I2C1_EVT_IRQHandler,Default_Handler
|
||||
|
||||
.weak I2C1_ERR_IRQHandler
|
||||
.thumb_set I2C1_ERR_IRQHandler,Default_Handler
|
||||
|
||||
.weak I2C2_EVT_IRQHandler
|
||||
.thumb_set I2C2_EVT_IRQHandler,Default_Handler
|
||||
|
||||
.weak I2C2_ERR_IRQHandler
|
||||
.thumb_set I2C2_ERR_IRQHandler,Default_Handler
|
||||
|
||||
.weak SPI1_IRQHandler
|
||||
.thumb_set SPI1_IRQHandler,Default_Handler
|
||||
|
||||
.weak SPI2_I2S2EXT_IRQHandler
|
||||
.thumb_set SPI2_I2S2EXT_IRQHandler,Default_Handler
|
||||
|
||||
.weak USART1_IRQHandler
|
||||
.thumb_set USART1_IRQHandler,Default_Handler
|
||||
|
||||
.weak USART2_IRQHandler
|
||||
.thumb_set USART2_IRQHandler,Default_Handler
|
||||
|
||||
.weak USART3_IRQHandler
|
||||
.thumb_set USART3_IRQHandler,Default_Handler
|
||||
|
||||
.weak EXINT15_10_IRQHandler
|
||||
.thumb_set EXINT15_10_IRQHandler,Default_Handler
|
||||
|
||||
.weak RTCAlarm_IRQHandler
|
||||
.thumb_set RTCAlarm_IRQHandler,Default_Handler
|
||||
|
||||
.weak USBFSWakeUp_IRQHandler
|
||||
.thumb_set USBFSWakeUp_IRQHandler,Default_Handler
|
||||
|
||||
.weak TMR8_BRK_TMR12_IRQHandler
|
||||
.thumb_set TMR8_BRK_TMR12_IRQHandler,Default_Handler
|
||||
|
||||
.weak TMR8_OVF_TMR13_IRQHandler
|
||||
.thumb_set TMR8_OVF_TMR13_IRQHandler,Default_Handler
|
||||
|
||||
.weak TMR8_TRG_HALL_TMR14_IRQHandler
|
||||
.thumb_set TMR8_TRG_HALL_TMR14_IRQHandler,Default_Handler
|
||||
|
||||
.weak TMR8_CH_IRQHandler
|
||||
.thumb_set TMR8_CH_IRQHandler,Default_Handler
|
||||
|
||||
.weak ADC3_IRQHandler
|
||||
.thumb_set ADC3_IRQHandler,Default_Handler
|
||||
|
||||
.weak XMC_IRQHandler
|
||||
.thumb_set XMC_IRQHandler,Default_Handler
|
||||
|
||||
.weak SDIO1_IRQHandler
|
||||
.thumb_set SDIO1_IRQHandler,Default_Handler
|
||||
|
||||
.weak TMR5_GLOBAL_IRQHandler
|
||||
.thumb_set TMR5_GLOBAL_IRQHandler,Default_Handler
|
||||
|
||||
.weak SPI3_I2S3EXT_IRQHandler
|
||||
.thumb_set SPI3_I2S3EXT_IRQHandler,Default_Handler
|
||||
|
||||
.weak UART4_IRQHandler
|
||||
.thumb_set UART4_IRQHandler,Default_Handler
|
||||
|
||||
.weak UART5_IRQHandler
|
||||
.thumb_set UART5_IRQHandler,Default_Handler
|
||||
|
||||
.weak TMR6_GLOBAL_IRQHandler
|
||||
.thumb_set TMR6_GLOBAL_IRQHandler,Default_Handler
|
||||
|
||||
.weak TMR7_GLOBAL_IRQHandler
|
||||
.thumb_set TMR7_GLOBAL_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA2_Channel1_IRQHandler
|
||||
.thumb_set DMA2_Channel1_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA2_Channel2_IRQHandler
|
||||
.thumb_set DMA2_Channel2_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA2_Channel3_IRQHandler
|
||||
.thumb_set DMA2_Channel3_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA2_Channel4_5_IRQHandler
|
||||
.thumb_set DMA2_Channel4_5_IRQHandler,Default_Handler
|
||||
|
||||
.weak SDIO2_IRQHandler
|
||||
.thumb_set SDIO2_IRQHandler,Default_Handler
|
||||
|
||||
.weak I2C3_EVT_IRQHandler
|
||||
.thumb_set I2C3_EVT_IRQHandler,Default_Handler
|
||||
|
||||
.weak I2C3_ERR_IRQHandler
|
||||
.thumb_set I2C3_ERR_IRQHandler,Default_Handler
|
||||
|
||||
.weak SPI4_IRQHandler
|
||||
.thumb_set SPI4_IRQHandler,Default_Handler
|
||||
|
||||
.weak CAN2_TX_IRQHandler
|
||||
.thumb_set CAN2_TX_IRQHandler,Default_Handler
|
||||
|
||||
.weak CAN2_RX0_IRQHandler
|
||||
.thumb_set CAN2_RX0_IRQHandler ,Default_Handler
|
||||
|
||||
.weak CAN2_RX1_IRQHandler
|
||||
.thumb_set CAN2_RX1_IRQHandler ,Default_Handler
|
||||
|
||||
.weak CAN2_SE_IRQHandler
|
||||
.thumb_set CAN2_SE_IRQHandler,Default_Handler
|
||||
|
||||
.weak ACC_IRQHandler
|
||||
.thumb_set ACC_IRQHandler,Default_Handler
|
||||
|
||||
.weak USBFS_MAPH_IRQHandler
|
||||
.thumb_set USBFS_MAPH_IRQHandler,Default_Handler
|
||||
|
||||
.weak USBFS_MAPL_IRQHandler
|
||||
.thumb_set USBFS_MAPL_IRQHandler,Default_Handler
|
||||
|
||||
.weak DMA2_Channel6_7_IRQHandler
|
||||
.thumb_set DMA2_Channel6_7_IRQHandler,Default_Handler
|
||||
|
||||
.weak USART6_IRQHandler
|
||||
.thumb_set USART6_IRQHandler,Default_Handler
|
||||
|
||||
.weak UART7_IRQHandler
|
||||
.thumb_set UART7_IRQHandler,Default_Handler
|
||||
|
||||
.weak UART8_IRQHandler
|
||||
.thumb_set UART8_IRQHandler,Default_Handler
|
||||
|
||||
.weak EMAC_IRQHandler
|
||||
.thumb_set EMAC_IRQHandler,Default_Handler
|
||||
|
||||
.weak EMAC_WKUP_IRQHandler
|
||||
.thumb_set EMAC_WKUP_IRQHandler,Default_Handler
|
||||
|
|
@ -0,0 +1,30 @@
|
|||
/*###ICF### Section handled by ICF editor, don't touch! ****/
|
||||
/*-Editor annotation file-*/
|
||||
/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
|
||||
/*-Specials-*/
|
||||
define symbol __ICFEDIT_intvec_start__ = 0x08000000;
|
||||
/*-Memory Regions-*/
|
||||
define symbol __ICFEDIT_region_ROM_start__ = 0x08000000;
|
||||
define symbol __ICFEDIT_region_ROM_end__ = 0x0803FFFF;
|
||||
define symbol __ICFEDIT_region_RAM_start__ = 0x20000000;
|
||||
define symbol __ICFEDIT_region_RAM_end__ = 0x20037FFF;
|
||||
/*-Sizes-*/
|
||||
define symbol __ICFEDIT_size_cstack__ = 0x1000;
|
||||
define symbol __ICFEDIT_size_heap__ = 0x1000;
|
||||
/**** End of ICF editor section. ###ICF###*/
|
||||
|
||||
define memory mem with size = 4G;
|
||||
define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
|
||||
define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
|
||||
|
||||
define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
|
||||
define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
|
||||
|
||||
initialize by copy { readwrite };
|
||||
do not initialize { section .noinit };
|
||||
|
||||
place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
|
||||
|
||||
place in ROM_region { readonly };
|
||||
place in RAM_region { readwrite,
|
||||
block CSTACK, block HEAP };
|
||||
|
|
@ -0,0 +1,30 @@
|
|||
/*###ICF### Section handled by ICF editor, don't touch! ****/
|
||||
/*-Editor annotation file-*/
|
||||
/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
|
||||
/*-Specials-*/
|
||||
define symbol __ICFEDIT_intvec_start__ = 0x08000000;
|
||||
/*-Memory Regions-*/
|
||||
define symbol __ICFEDIT_region_ROM_start__ = 0x08000000;
|
||||
define symbol __ICFEDIT_region_ROM_end__ = 0x0807FFFF;
|
||||
define symbol __ICFEDIT_region_RAM_start__ = 0x20000000;
|
||||
define symbol __ICFEDIT_region_RAM_end__ = 0x20037FFF;
|
||||
/*-Sizes-*/
|
||||
define symbol __ICFEDIT_size_cstack__ = 0x1000;
|
||||
define symbol __ICFEDIT_size_heap__ = 0x1000;
|
||||
/**** End of ICF editor section. ###ICF###*/
|
||||
|
||||
define memory mem with size = 4G;
|
||||
define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
|
||||
define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
|
||||
|
||||
define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
|
||||
define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
|
||||
|
||||
initialize by copy { readwrite };
|
||||
do not initialize { section .noinit };
|
||||
|
||||
place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
|
||||
|
||||
place in ROM_region { readonly };
|
||||
place in RAM_region { readwrite,
|
||||
block CSTACK, block HEAP };
|
||||
|
|
@ -0,0 +1,30 @@
|
|||
/*###ICF### Section handled by ICF editor, don't touch! ****/
|
||||
/*-Editor annotation file-*/
|
||||
/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
|
||||
/*-Specials-*/
|
||||
define symbol __ICFEDIT_intvec_start__ = 0x08000000;
|
||||
/*-Memory Regions-*/
|
||||
define symbol __ICFEDIT_region_ROM_start__ = 0x08000000;
|
||||
define symbol __ICFEDIT_region_ROM_end__ = 0x080FFFFF;
|
||||
define symbol __ICFEDIT_region_RAM_start__ = 0x20000000;
|
||||
define symbol __ICFEDIT_region_RAM_end__ = 0x20037FFF;
|
||||
/*-Sizes-*/
|
||||
define symbol __ICFEDIT_size_cstack__ = 0x1000;
|
||||
define symbol __ICFEDIT_size_heap__ = 0x1000;
|
||||
/**** End of ICF editor section. ###ICF###*/
|
||||
|
||||
define memory mem with size = 4G;
|
||||
define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
|
||||
define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
|
||||
|
||||
define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
|
||||
define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
|
||||
|
||||
initialize by copy { readwrite };
|
||||
do not initialize { section .noinit };
|
||||
|
||||
place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
|
||||
|
||||
place in ROM_region { readonly };
|
||||
place in RAM_region { readwrite,
|
||||
block CSTACK, block HEAP };
|
||||
|
|
@ -0,0 +1,30 @@
|
|||
/*###ICF### Section handled by ICF editor, don't touch! ****/
|
||||
/*-Editor annotation file-*/
|
||||
/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
|
||||
/*-Specials-*/
|
||||
define symbol __ICFEDIT_intvec_start__ = 0x08000000;
|
||||
/*-Memory Regions-*/
|
||||
define symbol __ICFEDIT_region_ROM_start__ = 0x08000000;
|
||||
define symbol __ICFEDIT_region_ROM_end__ = 0x0803FFFF;
|
||||
define symbol __ICFEDIT_region_RAM_start__ = 0x20000000;
|
||||
define symbol __ICFEDIT_region_RAM_end__ = 0x20037FFF;
|
||||
/*-Sizes-*/
|
||||
define symbol __ICFEDIT_size_cstack__ = 0x1000;
|
||||
define symbol __ICFEDIT_size_heap__ = 0x1000;
|
||||
/**** End of ICF editor section. ###ICF###*/
|
||||
|
||||
define memory mem with size = 4G;
|
||||
define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
|
||||
define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
|
||||
|
||||
define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
|
||||
define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
|
||||
|
||||
initialize by copy { readwrite };
|
||||
do not initialize { section .noinit };
|
||||
|
||||
place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
|
||||
|
||||
place in ROM_region { readonly };
|
||||
place in RAM_region { readwrite,
|
||||
block CSTACK, block HEAP };
|
||||
|
|
@ -0,0 +1,30 @@
|
|||
/*###ICF### Section handled by ICF editor, don't touch! ****/
|
||||
/*-Editor annotation file-*/
|
||||
/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
|
||||
/*-Specials-*/
|
||||
define symbol __ICFEDIT_intvec_start__ = 0x08000000;
|
||||
/*-Memory Regions-*/
|
||||
define symbol __ICFEDIT_region_ROM_start__ = 0x08000000;
|
||||
define symbol __ICFEDIT_region_ROM_end__ = 0x0807FFFF;
|
||||
define symbol __ICFEDIT_region_RAM_start__ = 0x20000000;
|
||||
define symbol __ICFEDIT_region_RAM_end__ = 0x20037FFF;
|
||||
/*-Sizes-*/
|
||||
define symbol __ICFEDIT_size_cstack__ = 0x1000;
|
||||
define symbol __ICFEDIT_size_heap__ = 0x1000;
|
||||
/**** End of ICF editor section. ###ICF###*/
|
||||
|
||||
define memory mem with size = 4G;
|
||||
define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
|
||||
define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
|
||||
|
||||
define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
|
||||
define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
|
||||
|
||||
initialize by copy { readwrite };
|
||||
do not initialize { section .noinit };
|
||||
|
||||
place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
|
||||
|
||||
place in ROM_region { readonly };
|
||||
place in RAM_region { readwrite,
|
||||
block CSTACK, block HEAP };
|
||||
|
|
@ -0,0 +1,30 @@
|
|||
/*###ICF### Section handled by ICF editor, don't touch! ****/
|
||||
/*-Editor annotation file-*/
|
||||
/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
|
||||
/*-Specials-*/
|
||||
define symbol __ICFEDIT_intvec_start__ = 0x08000000;
|
||||
/*-Memory Regions-*/
|
||||
define symbol __ICFEDIT_region_ROM_start__ = 0x08000000;
|
||||
define symbol __ICFEDIT_region_ROM_end__ = 0x080FFFFF;
|
||||
define symbol __ICFEDIT_region_RAM_start__ = 0x20000000;
|
||||
define symbol __ICFEDIT_region_RAM_end__ = 0x20037FFF;
|
||||
/*-Sizes-*/
|
||||
define symbol __ICFEDIT_size_cstack__ = 0x1000;
|
||||
define symbol __ICFEDIT_size_heap__ = 0x1000;
|
||||
/**** End of ICF editor section. ###ICF###*/
|
||||
|
||||
define memory mem with size = 4G;
|
||||
define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
|
||||
define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
|
||||
|
||||
define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
|
||||
define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
|
||||
|
||||
initialize by copy { readwrite };
|
||||
do not initialize { section .noinit };
|
||||
|
||||
place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
|
||||
|
||||
place in ROM_region { readonly };
|
||||
place in RAM_region { readwrite,
|
||||
block CSTACK, block HEAP };
|
||||
|
|
@ -0,0 +1,571 @@
|
|||
;**************************************************************************
|
||||
;* @file startup_at32f403a_407.s
|
||||
;* @brief at32f403a_407 startup file for IAR Systems
|
||||
;**************************************************************************
|
||||
;
|
||||
|
||||
; Amount of memory (in bytes) allocated for Stack
|
||||
; Tailor this value to your application needs
|
||||
; <h> Stack Configuration
|
||||
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
|
||||
; </h>
|
||||
;
|
||||
|
||||
MODULE ?cstartup
|
||||
|
||||
;; Forward declaration of sections.
|
||||
SECTION CSTACK:DATA:NOROOT(3)
|
||||
|
||||
SECTION .intvec:CODE:NOROOT(2)
|
||||
|
||||
EXTERN __iar_program_start
|
||||
EXTERN SystemInit
|
||||
PUBLIC __vector_table
|
||||
|
||||
DATA
|
||||
__vector_table
|
||||
DCD sfe(CSTACK)
|
||||
DCD Reset_Handler ; Reset Handler
|
||||
DCD NMI_Handler ; NMI Handler
|
||||
DCD HardFault_Handler ; Hard Fault Handler
|
||||
DCD MemManage_Handler ; MPU Fault Handler
|
||||
DCD BusFault_Handler ; Bus Fault Handler
|
||||
DCD UsageFault_Handler ; Usage Fault Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD SVC_Handler ; SVCall Handler
|
||||
DCD DebugMon_Handler ; Debug Monitor Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD PendSV_Handler ; PendSV Handler
|
||||
DCD SysTick_Handler ; SysTick Handler
|
||||
|
||||
; External Interrupts
|
||||
DCD WWDT_IRQHandler ; Window Watchdog Timer
|
||||
DCD PVM_IRQHandler ; PVM through EXINT Line detect
|
||||
DCD TAMPER_IRQHandler ; Tamper
|
||||
DCD RTC_IRQHandler ; RTC
|
||||
DCD FLASH_IRQHandler ; Flash
|
||||
DCD CRM_IRQHandler ; CRM
|
||||
DCD EXINT0_IRQHandler ; EXINT Line 0
|
||||
DCD EXINT1_IRQHandler ; EXINT Line 1
|
||||
DCD EXINT2_IRQHandler ; EXINT Line 2
|
||||
DCD EXINT3_IRQHandler ; EXINT Line 3
|
||||
DCD EXINT4_IRQHandler ; EXINT Line 4
|
||||
DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
|
||||
DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2
|
||||
DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3
|
||||
DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4
|
||||
DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5
|
||||
DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6
|
||||
DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7
|
||||
DCD ADC1_2_IRQHandler ; ADC1 & ADC2
|
||||
DCD USBFS_H_CAN1_TX_IRQHandler ; USB High Priority or CAN1 TX
|
||||
DCD USBFS_L_CAN1_RX0_IRQHandler ; USB Low Priority or CAN1 RX0
|
||||
DCD CAN1_RX1_IRQHandler ; CAN1 RX1
|
||||
DCD CAN1_SE_IRQHandler ; CAN1 SE
|
||||
DCD EXINT9_5_IRQHandler ; EXINT Line [9:5]
|
||||
DCD TMR1_BRK_TMR9_IRQHandler ; TMR1 Brake and TMR9
|
||||
DCD TMR1_OVF_TMR10_IRQHandler ; TMR1 Overflow and TMR10
|
||||
DCD TMR1_TRG_HALL_TMR11_IRQHandler ; TMR1 Trigger and hall and TMR11
|
||||
DCD TMR1_CH_IRQHandler ; TMR1 Channel
|
||||
DCD TMR2_GLOBAL_IRQHandler ; TMR2
|
||||
DCD TMR3_GLOBAL_IRQHandler ; TMR3
|
||||
DCD TMR4_GLOBAL_IRQHandler ; TMR4
|
||||
DCD I2C1_EVT_IRQHandler ; I2C1 Event
|
||||
DCD I2C1_ERR_IRQHandler ; I2C1 Error
|
||||
DCD I2C2_EVT_IRQHandler ; I2C2 Event
|
||||
DCD I2C2_ERR_IRQHandler ; I2C2 Error
|
||||
DCD SPI1_IRQHandler ; SPI1
|
||||
DCD SPI2_I2S2EXT_IRQHandler ; SPI2 & I2S2EXT
|
||||
DCD USART1_IRQHandler ; USART1
|
||||
DCD USART2_IRQHandler ; USART2
|
||||
DCD USART3_IRQHandler ; USART3
|
||||
DCD EXINT15_10_IRQHandler ; EXINT Line [15:10]
|
||||
DCD RTCAlarm_IRQHandler ; RTC Alarm through EXINT Line
|
||||
DCD USBFSWakeUp_IRQHandler ; USB Wakeup from suspend
|
||||
DCD TMR8_BRK_TMR12_IRQHandler ; TMR8 Brake and TMR12
|
||||
DCD TMR8_OVF_TMR13_IRQHandler ; TMR8 Overflow and TMR13
|
||||
DCD TMR8_TRG_HALL_TMR14_IRQHandler ; TMR8 Trigger and hall and TMR14
|
||||
DCD TMR8_CH_IRQHandler ; TMR8 Channel
|
||||
DCD ADC3_IRQHandler ; ADC3
|
||||
DCD XMC_IRQHandler ; XMC
|
||||
DCD SDIO1_IRQHandler ; SDIO1
|
||||
DCD TMR5_GLOBAL_IRQHandler ; TMR5
|
||||
DCD SPI3_I2S3EXT_IRQHandler ; SPI3 & I2S3EXT
|
||||
DCD UART4_IRQHandler ; UART4
|
||||
DCD UART5_IRQHandler ; UART5
|
||||
DCD TMR6_GLOBAL_IRQHandler ; TMR6
|
||||
DCD TMR7_GLOBAL_IRQHandler ; TMR7
|
||||
DCD DMA2_Channel1_IRQHandler ; DMA2 Channel1
|
||||
DCD DMA2_Channel2_IRQHandler ; DMA2 Channel2
|
||||
DCD DMA2_Channel3_IRQHandler ; DMA2 Channel3
|
||||
DCD DMA2_Channel4_5_IRQHandler ; DMA2 Channel4 & Channel5
|
||||
DCD SDIO2_IRQHandler ; SDIO2
|
||||
DCD I2C3_EVT_IRQHandler ; I2C3 Event
|
||||
DCD I2C3_ERR_IRQHandler ; I2C3 Error
|
||||
DCD SPI4_IRQHandler ; SPI4
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD CAN2_TX_IRQHandler ; CAN2 TX
|
||||
DCD CAN2_RX0_IRQHandler ; CAN2 RX0
|
||||
DCD CAN2_RX1_IRQHandler ; CAN2 RX1
|
||||
DCD CAN2_SE_IRQHandler ; CAN2 SE
|
||||
DCD ACC_IRQHandler ; ACC
|
||||
DCD USBFS_MAPH_IRQHandler ; USB Map HP
|
||||
DCD USBFS_MAPL_IRQHandler ; USB Map LP
|
||||
DCD DMA2_Channel6_7_IRQHandler ; DMA2 Channel6 & Channel7
|
||||
DCD USART6_IRQHandler ; USART6
|
||||
DCD UART7_IRQHandler ; UART7
|
||||
DCD UART8_IRQHandler ; UART8
|
||||
DCD EMAC_IRQHandler ; EMAC
|
||||
DCD EMAC_WKUP_IRQHandler ; EMAC_WKUP
|
||||
|
||||
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
||||
;;
|
||||
;; Default interrupt handlers.
|
||||
;;
|
||||
THUMB
|
||||
|
||||
PUBWEAK Reset_Handler
|
||||
SECTION .text:CODE:REORDER:NOROOT(2)
|
||||
Reset_Handler
|
||||
LDR R0, =SystemInit
|
||||
BLX R0
|
||||
LDR R0, =__iar_program_start
|
||||
BX R0
|
||||
|
||||
PUBWEAK NMI_Handler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
NMI_Handler
|
||||
B NMI_Handler
|
||||
|
||||
PUBWEAK HardFault_Handler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
HardFault_Handler
|
||||
B HardFault_Handler
|
||||
|
||||
PUBWEAK MemManage_Handler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
MemManage_Handler
|
||||
B MemManage_Handler
|
||||
|
||||
PUBWEAK BusFault_Handler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
BusFault_Handler
|
||||
B BusFault_Handler
|
||||
|
||||
PUBWEAK UsageFault_Handler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
UsageFault_Handler
|
||||
B UsageFault_Handler
|
||||
|
||||
PUBWEAK SVC_Handler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
SVC_Handler
|
||||
B SVC_Handler
|
||||
|
||||
PUBWEAK DebugMon_Handler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
DebugMon_Handler
|
||||
B DebugMon_Handler
|
||||
|
||||
PUBWEAK PendSV_Handler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
PendSV_Handler
|
||||
B PendSV_Handler
|
||||
|
||||
PUBWEAK SysTick_Handler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
SysTick_Handler
|
||||
B SysTick_Handler
|
||||
|
||||
PUBWEAK WWDT_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
WWDT_IRQHandler
|
||||
B WWDT_IRQHandler
|
||||
|
||||
PUBWEAK PVM_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
PVM_IRQHandler
|
||||
B PVM_IRQHandler
|
||||
|
||||
PUBWEAK TAMPER_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
TAMPER_IRQHandler
|
||||
B TAMPER_IRQHandler
|
||||
|
||||
PUBWEAK RTC_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
RTC_IRQHandler
|
||||
B RTC_IRQHandler
|
||||
|
||||
PUBWEAK FLASH_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
FLASH_IRQHandler
|
||||
B FLASH_IRQHandler
|
||||
|
||||
PUBWEAK CRM_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
CRM_IRQHandler
|
||||
B CRM_IRQHandler
|
||||
|
||||
PUBWEAK EXINT0_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
EXINT0_IRQHandler
|
||||
B EXINT0_IRQHandler
|
||||
|
||||
PUBWEAK EXINT1_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
EXINT1_IRQHandler
|
||||
B EXINT1_IRQHandler
|
||||
|
||||
PUBWEAK EXINT2_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
EXINT2_IRQHandler
|
||||
B EXINT2_IRQHandler
|
||||
|
||||
PUBWEAK EXINT3_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
EXINT3_IRQHandler
|
||||
B EXINT3_IRQHandler
|
||||
|
||||
PUBWEAK EXINT4_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
EXINT4_IRQHandler
|
||||
B EXINT4_IRQHandler
|
||||
|
||||
PUBWEAK DMA1_Channel1_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
DMA1_Channel1_IRQHandler
|
||||
B DMA1_Channel1_IRQHandler
|
||||
|
||||
PUBWEAK DMA1_Channel2_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
DMA1_Channel2_IRQHandler
|
||||
B DMA1_Channel2_IRQHandler
|
||||
|
||||
PUBWEAK DMA1_Channel3_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
DMA1_Channel3_IRQHandler
|
||||
B DMA1_Channel3_IRQHandler
|
||||
|
||||
PUBWEAK DMA1_Channel4_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
DMA1_Channel4_IRQHandler
|
||||
B DMA1_Channel4_IRQHandler
|
||||
|
||||
PUBWEAK DMA1_Channel5_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
DMA1_Channel5_IRQHandler
|
||||
B DMA1_Channel5_IRQHandler
|
||||
|
||||
PUBWEAK DMA1_Channel6_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
DMA1_Channel6_IRQHandler
|
||||
B DMA1_Channel6_IRQHandler
|
||||
|
||||
PUBWEAK DMA1_Channel7_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
DMA1_Channel7_IRQHandler
|
||||
B DMA1_Channel7_IRQHandler
|
||||
|
||||
PUBWEAK ADC1_2_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
ADC1_2_IRQHandler
|
||||
B ADC1_2_IRQHandler
|
||||
|
||||
PUBWEAK USBFS_H_CAN1_TX_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
USBFS_H_CAN1_TX_IRQHandler
|
||||
B USBFS_H_CAN1_TX_IRQHandler
|
||||
|
||||
PUBWEAK USBFS_L_CAN1_RX0_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
USBFS_L_CAN1_RX0_IRQHandler
|
||||
B USBFS_L_CAN1_RX0_IRQHandler
|
||||
|
||||
PUBWEAK CAN1_RX1_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
CAN1_RX1_IRQHandler
|
||||
B CAN1_RX1_IRQHandler
|
||||
|
||||
PUBWEAK CAN1_SE_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
CAN1_SE_IRQHandler
|
||||
B CAN1_SE_IRQHandler
|
||||
|
||||
PUBWEAK EXINT9_5_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
EXINT9_5_IRQHandler
|
||||
B EXINT9_5_IRQHandler
|
||||
|
||||
PUBWEAK TMR1_BRK_TMR9_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
TMR1_BRK_TMR9_IRQHandler
|
||||
B TMR1_BRK_TMR9_IRQHandler
|
||||
|
||||
PUBWEAK TMR1_OVF_TMR10_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
TMR1_OVF_TMR10_IRQHandler
|
||||
B TMR1_OVF_TMR10_IRQHandler
|
||||
|
||||
PUBWEAK TMR1_TRG_HALL_TMR11_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
TMR1_TRG_HALL_TMR11_IRQHandler
|
||||
B TMR1_TRG_HALL_TMR11_IRQHandler
|
||||
|
||||
PUBWEAK TMR1_CH_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
TMR1_CH_IRQHandler
|
||||
B TMR1_CH_IRQHandler
|
||||
|
||||
PUBWEAK TMR2_GLOBAL_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
TMR2_GLOBAL_IRQHandler
|
||||
B TMR2_GLOBAL_IRQHandler
|
||||
|
||||
PUBWEAK TMR3_GLOBAL_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
TMR3_GLOBAL_IRQHandler
|
||||
B TMR3_GLOBAL_IRQHandler
|
||||
|
||||
PUBWEAK TMR4_GLOBAL_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
TMR4_GLOBAL_IRQHandler
|
||||
B TMR4_GLOBAL_IRQHandler
|
||||
|
||||
PUBWEAK I2C1_EVT_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
I2C1_EVT_IRQHandler
|
||||
B I2C1_EVT_IRQHandler
|
||||
|
||||
PUBWEAK I2C1_ERR_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
I2C1_ERR_IRQHandler
|
||||
B I2C1_ERR_IRQHandler
|
||||
|
||||
PUBWEAK I2C2_EVT_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
I2C2_EVT_IRQHandler
|
||||
B I2C2_EVT_IRQHandler
|
||||
|
||||
PUBWEAK I2C2_ERR_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
I2C2_ERR_IRQHandler
|
||||
B I2C2_ERR_IRQHandler
|
||||
|
||||
PUBWEAK SPI1_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
SPI1_IRQHandler
|
||||
B SPI1_IRQHandler
|
||||
|
||||
PUBWEAK SPI2_I2S2EXT_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
SPI2_I2S2EXT_IRQHandler
|
||||
B SPI2_I2S2EXT_IRQHandler
|
||||
|
||||
PUBWEAK USART1_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
USART1_IRQHandler
|
||||
B USART1_IRQHandler
|
||||
|
||||
PUBWEAK USART2_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
USART2_IRQHandler
|
||||
B USART2_IRQHandler
|
||||
|
||||
PUBWEAK USART3_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
USART3_IRQHandler
|
||||
B USART3_IRQHandler
|
||||
|
||||
PUBWEAK EXINT15_10_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
EXINT15_10_IRQHandler
|
||||
B EXINT15_10_IRQHandler
|
||||
|
||||
PUBWEAK RTCAlarm_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
RTCAlarm_IRQHandler
|
||||
B RTCAlarm_IRQHandler
|
||||
|
||||
PUBWEAK USBFSWakeUp_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
USBFSWakeUp_IRQHandler
|
||||
B USBFSWakeUp_IRQHandler
|
||||
|
||||
PUBWEAK TMR8_BRK_TMR12_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
TMR8_BRK_TMR12_IRQHandler
|
||||
B TMR8_BRK_TMR12_IRQHandler
|
||||
|
||||
PUBWEAK TMR8_OVF_TMR13_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
TMR8_OVF_TMR13_IRQHandler
|
||||
B TMR8_OVF_TMR13_IRQHandler
|
||||
|
||||
PUBWEAK TMR8_TRG_HALL_TMR14_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
TMR8_TRG_HALL_TMR14_IRQHandler
|
||||
B TMR8_TRG_HALL_TMR14_IRQHandler
|
||||
|
||||
PUBWEAK TMR8_CH_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
TMR8_CH_IRQHandler
|
||||
B TMR8_CH_IRQHandler
|
||||
|
||||
PUBWEAK ADC3_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
ADC3_IRQHandler
|
||||
B ADC3_IRQHandler
|
||||
|
||||
PUBWEAK XMC_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
XMC_IRQHandler
|
||||
B XMC_IRQHandler
|
||||
|
||||
PUBWEAK SDIO1_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
SDIO1_IRQHandler
|
||||
B SDIO1_IRQHandler
|
||||
|
||||
PUBWEAK TMR5_GLOBAL_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
TMR5_GLOBAL_IRQHandler
|
||||
B TMR5_GLOBAL_IRQHandler
|
||||
|
||||
PUBWEAK SPI3_I2S3EXT_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
SPI3_I2S3EXT_IRQHandler
|
||||
B SPI3_I2S3EXT_IRQHandler
|
||||
|
||||
PUBWEAK UART4_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
UART4_IRQHandler
|
||||
B UART4_IRQHandler
|
||||
|
||||
PUBWEAK UART5_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
UART5_IRQHandler
|
||||
B UART5_IRQHandler
|
||||
|
||||
PUBWEAK TMR6_GLOBAL_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
TMR6_GLOBAL_IRQHandler
|
||||
B TMR6_GLOBAL_IRQHandler
|
||||
|
||||
PUBWEAK TMR7_GLOBAL_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
TMR7_GLOBAL_IRQHandler
|
||||
B TMR7_GLOBAL_IRQHandler
|
||||
|
||||
PUBWEAK DMA2_Channel1_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
DMA2_Channel1_IRQHandler
|
||||
B DMA2_Channel1_IRQHandler
|
||||
|
||||
PUBWEAK DMA2_Channel2_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
DMA2_Channel2_IRQHandler
|
||||
B DMA2_Channel2_IRQHandler
|
||||
|
||||
PUBWEAK DMA2_Channel3_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
DMA2_Channel3_IRQHandler
|
||||
B DMA2_Channel3_IRQHandler
|
||||
|
||||
PUBWEAK DMA2_Channel4_5_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
DMA2_Channel4_5_IRQHandler
|
||||
B DMA2_Channel4_5_IRQHandler
|
||||
|
||||
PUBWEAK SDIO2_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
SDIO2_IRQHandler
|
||||
B SDIO2_IRQHandler
|
||||
|
||||
PUBWEAK I2C3_EVT_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
I2C3_EVT_IRQHandler
|
||||
B I2C3_EVT_IRQHandler
|
||||
|
||||
PUBWEAK I2C3_ERR_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
I2C3_ERR_IRQHandler
|
||||
B I2C3_ERR_IRQHandler
|
||||
|
||||
PUBWEAK SPI4_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
SPI4_IRQHandler
|
||||
B SPI4_IRQHandler
|
||||
|
||||
PUBWEAK CAN2_TX_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
CAN2_TX_IRQHandler
|
||||
B CAN2_TX_IRQHandler
|
||||
|
||||
PUBWEAK CAN2_RX0_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
CAN2_RX0_IRQHandler
|
||||
B CAN2_RX0_IRQHandler
|
||||
|
||||
PUBWEAK CAN2_RX1_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
CAN2_RX1_IRQHandler
|
||||
B CAN2_RX1_IRQHandler
|
||||
|
||||
PUBWEAK CAN2_SE_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
CAN2_SE_IRQHandler
|
||||
B CAN2_SE_IRQHandler
|
||||
|
||||
PUBWEAK ACC_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
ACC_IRQHandler
|
||||
B ACC_IRQHandler
|
||||
|
||||
PUBWEAK USBFS_MAPH_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
USBFS_MAPH_IRQHandler
|
||||
B USBFS_MAPH_IRQHandler
|
||||
|
||||
PUBWEAK USBFS_MAPL_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
USBFS_MAPL_IRQHandler
|
||||
B USBFS_MAPL_IRQHandler
|
||||
|
||||
PUBWEAK DMA2_Channel6_7_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
DMA2_Channel6_7_IRQHandler
|
||||
B DMA2_Channel6_7_IRQHandler
|
||||
|
||||
PUBWEAK USART6_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
USART6_IRQHandler
|
||||
B USART6_IRQHandler
|
||||
|
||||
PUBWEAK UART7_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
UART7_IRQHandler
|
||||
B UART7_IRQHandler
|
||||
|
||||
PUBWEAK UART8_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
UART8_IRQHandler
|
||||
B UART8_IRQHandler
|
||||
|
||||
PUBWEAK EMAC_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
EMAC_IRQHandler
|
||||
B EMAC_IRQHandler
|
||||
|
||||
PUBWEAK EMAC_WKUP_IRQHandler
|
||||
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||
EMAC_WKUP_IRQHandler
|
||||
B EMAC_WKUP_IRQHandler
|
||||
|
||||
END
|
||||
|
|
@ -0,0 +1,390 @@
|
|||
;**************************************************************************
|
||||
;* @file startup_at32f403a_407.s
|
||||
;* @brief at32f403a_407 startup file for keil
|
||||
;* <<< Use Configuration Wizard in Context Menu >>>
|
||||
;**************************************************************************
|
||||
;
|
||||
|
||||
; Amount of memory (in bytes) allocated for Stack
|
||||
; Tailor this value to your application needs
|
||||
; <h> Stack Configuration
|
||||
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
|
||||
; </h>
|
||||
|
||||
Stack_Size EQU 0x00000400
|
||||
|
||||
AREA STACK, NOINIT, READWRITE, ALIGN=3
|
||||
Stack_Mem SPACE Stack_Size
|
||||
__initial_sp
|
||||
|
||||
; <h> Heap Configuration
|
||||
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
|
||||
; </h>
|
||||
|
||||
Heap_Size EQU 0x00000200
|
||||
|
||||
AREA HEAP, NOINIT, READWRITE, ALIGN=3
|
||||
__heap_base
|
||||
Heap_Mem SPACE Heap_Size
|
||||
__heap_limit
|
||||
|
||||
PRESERVE8
|
||||
THUMB
|
||||
|
||||
|
||||
; Vector Table Mapped to Address 0 at Reset
|
||||
AREA RESET, DATA, READONLY
|
||||
EXPORT __Vectors
|
||||
EXPORT __Vectors_End
|
||||
EXPORT __Vectors_Size
|
||||
|
||||
__Vectors DCD __initial_sp ; Top of Stack
|
||||
DCD Reset_Handler ; Reset Handler
|
||||
DCD NMI_Handler ; NMI Handler
|
||||
DCD HardFault_Handler ; Hard Fault Handler
|
||||
DCD MemManage_Handler ; MPU Fault Handler
|
||||
DCD BusFault_Handler ; Bus Fault Handler
|
||||
DCD UsageFault_Handler ; Usage Fault Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD SVC_Handler ; SVCall Handler
|
||||
DCD DebugMon_Handler ; Debug Monitor Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD PendSV_Handler ; PendSV Handler
|
||||
DCD SysTick_Handler ; SysTick Handler
|
||||
|
||||
; External Interrupts
|
||||
DCD WWDT_IRQHandler ; Window Watchdog Timer
|
||||
DCD PVM_IRQHandler ; PVM through EXINT Line detect
|
||||
DCD TAMPER_IRQHandler ; Tamper
|
||||
DCD RTC_IRQHandler ; RTC
|
||||
DCD FLASH_IRQHandler ; Flash
|
||||
DCD CRM_IRQHandler ; CRM
|
||||
DCD EXINT0_IRQHandler ; EXINT Line 0
|
||||
DCD EXINT1_IRQHandler ; EXINT Line 1
|
||||
DCD EXINT2_IRQHandler ; EXINT Line 2
|
||||
DCD EXINT3_IRQHandler ; EXINT Line 3
|
||||
DCD EXINT4_IRQHandler ; EXINT Line 4
|
||||
DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
|
||||
DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2
|
||||
DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3
|
||||
DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4
|
||||
DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5
|
||||
DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6
|
||||
DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7
|
||||
DCD ADC1_2_IRQHandler ; ADC1 & ADC2
|
||||
DCD USBFS_H_CAN1_TX_IRQHandler ; USB High Priority or CAN1 TX
|
||||
DCD USBFS_L_CAN1_RX0_IRQHandler ; USB Low Priority or CAN1 RX0
|
||||
DCD CAN1_RX1_IRQHandler ; CAN1 RX1
|
||||
DCD CAN1_SE_IRQHandler ; CAN1 SE
|
||||
DCD EXINT9_5_IRQHandler ; EXINT Line [9:5]
|
||||
DCD TMR1_BRK_TMR9_IRQHandler ; TMR1 Brake and TMR9
|
||||
DCD TMR1_OVF_TMR10_IRQHandler ; TMR1 overflow and TMR10
|
||||
DCD TMR1_TRG_HALL_TMR11_IRQHandler ; TMR1 Trigger and hall and TMR11
|
||||
DCD TMR1_CH_IRQHandler ; TMR1 channel
|
||||
DCD TMR2_GLOBAL_IRQHandler ; TMR2
|
||||
DCD TMR3_GLOBAL_IRQHandler ; TMR3
|
||||
DCD TMR4_GLOBAL_IRQHandler ; TMR4
|
||||
DCD I2C1_EVT_IRQHandler ; I2C1 Event
|
||||
DCD I2C1_ERR_IRQHandler ; I2C1 Error
|
||||
DCD I2C2_EVT_IRQHandler ; I2C2 Event
|
||||
DCD I2C2_ERR_IRQHandler ; I2C2 Error
|
||||
DCD SPI1_IRQHandler ; SPI1
|
||||
DCD SPI2_I2S2EXT_IRQHandler ; SPI2 & I2S2EXT
|
||||
DCD USART1_IRQHandler ; USART1
|
||||
DCD USART2_IRQHandler ; USART2
|
||||
DCD USART3_IRQHandler ; USART3
|
||||
DCD EXINT15_10_IRQHandler ; EXINT Line [15:10]
|
||||
DCD RTCAlarm_IRQHandler ; RTC Alarm through EXINT Line
|
||||
DCD USBFSWakeUp_IRQHandler ; USB Wakeup from suspend
|
||||
DCD TMR8_BRK_TMR12_IRQHandler ; TMR8 Brake and TMR12
|
||||
DCD TMR8_OVF_TMR13_IRQHandler ; TMR8 overflow and TMR13
|
||||
DCD TMR8_TRG_HALL_TMR14_IRQHandler ; TMR8 Trigger and hall and TMR14
|
||||
DCD TMR8_CH_IRQHandler ; TMR8 channel
|
||||
DCD ADC3_IRQHandler ; ADC3
|
||||
DCD XMC_IRQHandler ; XMC
|
||||
DCD SDIO1_IRQHandler ; SDIO1
|
||||
DCD TMR5_GLOBAL_IRQHandler ; TMR5
|
||||
DCD SPI3_I2S3EXT_IRQHandler ; SPI3 & I2S3EXT
|
||||
DCD UART4_IRQHandler ; UART4
|
||||
DCD UART5_IRQHandler ; UART5
|
||||
DCD TMR6_GLOBAL_IRQHandler ; TMR6
|
||||
DCD TMR7_GLOBAL_IRQHandler ; TMR7
|
||||
DCD DMA2_Channel1_IRQHandler ; DMA2 Channel1
|
||||
DCD DMA2_Channel2_IRQHandler ; DMA2 Channel2
|
||||
DCD DMA2_Channel3_IRQHandler ; DMA2 Channel3
|
||||
DCD DMA2_Channel4_5_IRQHandler ; DMA2 Channel4 & Channel5
|
||||
DCD SDIO2_IRQHandler ; SDIO2
|
||||
DCD I2C3_EVT_IRQHandler ; I2C3 Event
|
||||
DCD I2C3_ERR_IRQHandler ; I2C3 Error
|
||||
DCD SPI4_IRQHandler ; SPI4
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD CAN2_TX_IRQHandler ; CAN2 TX
|
||||
DCD CAN2_RX0_IRQHandler ; CAN2 RX0
|
||||
DCD CAN2_RX1_IRQHandler ; CAN2 RX1
|
||||
DCD CAN2_SE_IRQHandler ; CAN2 SE
|
||||
DCD ACC_IRQHandler ; ACC
|
||||
DCD USBFS_MAPH_IRQHandler ; USB Map High
|
||||
DCD USBFS_MAPL_IRQHandler ; USB Map Low
|
||||
DCD DMA2_Channel6_7_IRQHandler ; DMA2 Channel6 & Channel7
|
||||
DCD USART6_IRQHandler ; USART6
|
||||
DCD UART7_IRQHandler ; UART7
|
||||
DCD UART8_IRQHandler ; UART8
|
||||
DCD EMAC_IRQHandler ; EMAC
|
||||
DCD EMAC_WKUP_IRQHandler ; EMAC_WKUP
|
||||
__Vectors_End
|
||||
|
||||
__Vectors_Size EQU __Vectors_End - __Vectors
|
||||
|
||||
AREA |.text|, CODE, READONLY
|
||||
|
||||
; Reset handler
|
||||
Reset_Handler PROC
|
||||
EXPORT Reset_Handler [WEAK]
|
||||
IMPORT __main
|
||||
IMPORT SystemInit
|
||||
LDR R0, =SystemInit
|
||||
BLX R0
|
||||
LDR R0, =__main
|
||||
BX R0
|
||||
ENDP
|
||||
|
||||
; Dummy Exception Handlers (infinite loops which can be modified)
|
||||
|
||||
NMI_Handler PROC
|
||||
EXPORT NMI_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
HardFault_Handler\
|
||||
PROC
|
||||
EXPORT HardFault_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
MemManage_Handler\
|
||||
PROC
|
||||
EXPORT MemManage_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
BusFault_Handler\
|
||||
PROC
|
||||
EXPORT BusFault_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
UsageFault_Handler\
|
||||
PROC
|
||||
EXPORT UsageFault_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
SVC_Handler PROC
|
||||
EXPORT SVC_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
DebugMon_Handler\
|
||||
PROC
|
||||
EXPORT DebugMon_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
PendSV_Handler PROC
|
||||
EXPORT PendSV_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
SysTick_Handler PROC
|
||||
EXPORT SysTick_Handler [WEAK]
|
||||
B .
|
||||
ENDP
|
||||
|
||||
Default_Handler PROC
|
||||
|
||||
EXPORT WWDT_IRQHandler [WEAK]
|
||||
EXPORT PVM_IRQHandler [WEAK]
|
||||
EXPORT TAMPER_IRQHandler [WEAK]
|
||||
EXPORT RTC_IRQHandler [WEAK]
|
||||
EXPORT FLASH_IRQHandler [WEAK]
|
||||
EXPORT CRM_IRQHandler [WEAK]
|
||||
EXPORT EXINT0_IRQHandler [WEAK]
|
||||
EXPORT EXINT1_IRQHandler [WEAK]
|
||||
EXPORT EXINT2_IRQHandler [WEAK]
|
||||
EXPORT EXINT3_IRQHandler [WEAK]
|
||||
EXPORT EXINT4_IRQHandler [WEAK]
|
||||
EXPORT DMA1_Channel1_IRQHandler [WEAK]
|
||||
EXPORT DMA1_Channel2_IRQHandler [WEAK]
|
||||
EXPORT DMA1_Channel3_IRQHandler [WEAK]
|
||||
EXPORT DMA1_Channel4_IRQHandler [WEAK]
|
||||
EXPORT DMA1_Channel5_IRQHandler [WEAK]
|
||||
EXPORT DMA1_Channel6_IRQHandler [WEAK]
|
||||
EXPORT DMA1_Channel7_IRQHandler [WEAK]
|
||||
EXPORT ADC1_2_IRQHandler [WEAK]
|
||||
EXPORT USBFS_H_CAN1_TX_IRQHandler [WEAK]
|
||||
EXPORT USBFS_L_CAN1_RX0_IRQHandler [WEAK]
|
||||
EXPORT CAN1_RX1_IRQHandler [WEAK]
|
||||
EXPORT CAN1_SE_IRQHandler [WEAK]
|
||||
EXPORT EXINT9_5_IRQHandler [WEAK]
|
||||
EXPORT TMR1_BRK_TMR9_IRQHandler [WEAK]
|
||||
EXPORT TMR1_OVF_TMR10_IRQHandler [WEAK]
|
||||
EXPORT TMR1_TRG_HALL_TMR11_IRQHandler [WEAK]
|
||||
EXPORT TMR1_CH_IRQHandler [WEAK]
|
||||
EXPORT TMR2_GLOBAL_IRQHandler [WEAK]
|
||||
EXPORT TMR3_GLOBAL_IRQHandler [WEAK]
|
||||
EXPORT TMR4_GLOBAL_IRQHandler [WEAK]
|
||||
EXPORT I2C1_EVT_IRQHandler [WEAK]
|
||||
EXPORT I2C1_ERR_IRQHandler [WEAK]
|
||||
EXPORT I2C2_EVT_IRQHandler [WEAK]
|
||||
EXPORT I2C2_ERR_IRQHandler [WEAK]
|
||||
EXPORT SPI1_IRQHandler [WEAK]
|
||||
EXPORT SPI2_I2S2EXT_IRQHandler [WEAK]
|
||||
EXPORT USART1_IRQHandler [WEAK]
|
||||
EXPORT USART2_IRQHandler [WEAK]
|
||||
EXPORT USART3_IRQHandler [WEAK]
|
||||
EXPORT EXINT15_10_IRQHandler [WEAK]
|
||||
EXPORT RTCAlarm_IRQHandler [WEAK]
|
||||
EXPORT USBFSWakeUp_IRQHandler [WEAK]
|
||||
EXPORT TMR8_BRK_TMR12_IRQHandler [WEAK]
|
||||
EXPORT TMR8_OVF_TMR13_IRQHandler [WEAK]
|
||||
EXPORT TMR8_TRG_HALL_TMR14_IRQHandler [WEAK]
|
||||
EXPORT TMR8_CH_IRQHandler [WEAK]
|
||||
EXPORT ADC3_IRQHandler [WEAK]
|
||||
EXPORT XMC_IRQHandler [WEAK]
|
||||
EXPORT SDIO1_IRQHandler [WEAK]
|
||||
EXPORT TMR5_GLOBAL_IRQHandler [WEAK]
|
||||
EXPORT SPI3_I2S3EXT_IRQHandler [WEAK]
|
||||
EXPORT UART4_IRQHandler [WEAK]
|
||||
EXPORT UART5_IRQHandler [WEAK]
|
||||
EXPORT TMR6_GLOBAL_IRQHandler [WEAK]
|
||||
EXPORT TMR7_GLOBAL_IRQHandler [WEAK]
|
||||
EXPORT DMA2_Channel1_IRQHandler [WEAK]
|
||||
EXPORT DMA2_Channel2_IRQHandler [WEAK]
|
||||
EXPORT DMA2_Channel3_IRQHandler [WEAK]
|
||||
EXPORT DMA2_Channel4_5_IRQHandler [WEAK]
|
||||
EXPORT SDIO2_IRQHandler [WEAK]
|
||||
EXPORT I2C3_EVT_IRQHandler [WEAK]
|
||||
EXPORT I2C3_ERR_IRQHandler [WEAK]
|
||||
EXPORT SPI4_IRQHandler [WEAK]
|
||||
EXPORT CAN2_TX_IRQHandler [WEAK]
|
||||
EXPORT CAN2_RX0_IRQHandler [WEAK]
|
||||
EXPORT CAN2_RX1_IRQHandler [WEAK]
|
||||
EXPORT CAN2_SE_IRQHandler [WEAK]
|
||||
EXPORT ACC_IRQHandler [WEAK]
|
||||
EXPORT USBFS_MAPH_IRQHandler [WEAK]
|
||||
EXPORT USBFS_MAPL_IRQHandler [WEAK]
|
||||
EXPORT DMA2_Channel6_7_IRQHandler [WEAK]
|
||||
EXPORT USART6_IRQHandler [WEAK]
|
||||
EXPORT UART7_IRQHandler [WEAK]
|
||||
EXPORT UART8_IRQHandler [WEAK]
|
||||
EXPORT EMAC_IRQHandler [WEAK]
|
||||
EXPORT EMAC_WKUP_IRQHandler [WEAK]
|
||||
|
||||
WWDT_IRQHandler
|
||||
PVM_IRQHandler
|
||||
TAMPER_IRQHandler
|
||||
RTC_IRQHandler
|
||||
FLASH_IRQHandler
|
||||
CRM_IRQHandler
|
||||
EXINT0_IRQHandler
|
||||
EXINT1_IRQHandler
|
||||
EXINT2_IRQHandler
|
||||
EXINT3_IRQHandler
|
||||
EXINT4_IRQHandler
|
||||
DMA1_Channel1_IRQHandler
|
||||
DMA1_Channel2_IRQHandler
|
||||
DMA1_Channel3_IRQHandler
|
||||
DMA1_Channel4_IRQHandler
|
||||
DMA1_Channel5_IRQHandler
|
||||
DMA1_Channel6_IRQHandler
|
||||
DMA1_Channel7_IRQHandler
|
||||
ADC1_2_IRQHandler
|
||||
USBFS_H_CAN1_TX_IRQHandler
|
||||
USBFS_L_CAN1_RX0_IRQHandler
|
||||
CAN1_RX1_IRQHandler
|
||||
CAN1_SE_IRQHandler
|
||||
EXINT9_5_IRQHandler
|
||||
TMR1_BRK_TMR9_IRQHandler
|
||||
TMR1_OVF_TMR10_IRQHandler
|
||||
TMR1_TRG_HALL_TMR11_IRQHandler
|
||||
TMR1_CH_IRQHandler
|
||||
TMR2_GLOBAL_IRQHandler
|
||||
TMR3_GLOBAL_IRQHandler
|
||||
TMR4_GLOBAL_IRQHandler
|
||||
I2C1_EVT_IRQHandler
|
||||
I2C1_ERR_IRQHandler
|
||||
I2C2_EVT_IRQHandler
|
||||
I2C2_ERR_IRQHandler
|
||||
SPI1_IRQHandler
|
||||
SPI2_I2S2EXT_IRQHandler
|
||||
USART1_IRQHandler
|
||||
USART2_IRQHandler
|
||||
USART3_IRQHandler
|
||||
EXINT15_10_IRQHandler
|
||||
RTCAlarm_IRQHandler
|
||||
USBFSWakeUp_IRQHandler
|
||||
TMR8_BRK_TMR12_IRQHandler
|
||||
TMR8_OVF_TMR13_IRQHandler
|
||||
TMR8_TRG_HALL_TMR14_IRQHandler
|
||||
TMR8_CH_IRQHandler
|
||||
ADC3_IRQHandler
|
||||
XMC_IRQHandler
|
||||
SDIO1_IRQHandler
|
||||
TMR5_GLOBAL_IRQHandler
|
||||
SPI3_I2S3EXT_IRQHandler
|
||||
UART4_IRQHandler
|
||||
UART5_IRQHandler
|
||||
TMR6_GLOBAL_IRQHandler
|
||||
TMR7_GLOBAL_IRQHandler
|
||||
DMA2_Channel1_IRQHandler
|
||||
DMA2_Channel2_IRQHandler
|
||||
DMA2_Channel3_IRQHandler
|
||||
DMA2_Channel4_5_IRQHandler
|
||||
SDIO2_IRQHandler
|
||||
I2C3_EVT_IRQHandler
|
||||
I2C3_ERR_IRQHandler
|
||||
SPI4_IRQHandler
|
||||
CAN2_TX_IRQHandler
|
||||
CAN2_RX0_IRQHandler
|
||||
CAN2_RX1_IRQHandler
|
||||
CAN2_SE_IRQHandler
|
||||
ACC_IRQHandler
|
||||
USBFS_MAPH_IRQHandler
|
||||
USBFS_MAPL_IRQHandler
|
||||
DMA2_Channel6_7_IRQHandler
|
||||
USART6_IRQHandler
|
||||
UART7_IRQHandler
|
||||
UART8_IRQHandler
|
||||
EMAC_IRQHandler
|
||||
EMAC_WKUP_IRQHandler
|
||||
B .
|
||||
|
||||
ENDP
|
||||
|
||||
ALIGN
|
||||
|
||||
;*******************************************************************************
|
||||
; User Stack and Heap initialization
|
||||
;*******************************************************************************
|
||||
IF :DEF:__MICROLIB
|
||||
|
||||
EXPORT __initial_sp
|
||||
EXPORT __heap_base
|
||||
EXPORT __heap_limit
|
||||
|
||||
ELSE
|
||||
|
||||
IMPORT __use_two_region_memory
|
||||
EXPORT __user_initial_stackheap
|
||||
|
||||
__user_initial_stackheap
|
||||
|
||||
LDR R0, = Heap_Mem
|
||||
LDR R1, = (Stack_Mem + Stack_Size)
|
||||
LDR R2, = (Heap_Mem + Heap_Size)
|
||||
LDR R3, = Stack_Mem
|
||||
BX LR
|
||||
|
||||
ALIGN
|
||||
|
||||
ENDIF
|
||||
|
||||
END
|
||||
|
|
@ -0,0 +1,192 @@
|
|||
/**
|
||||
**************************************************************************
|
||||
* @file system_at32f403a_407.c
|
||||
* @brief contains all the functions for cmsis cortex-m4 system source file
|
||||
**************************************************************************
|
||||
*
|
||||
* Copyright (c) 2025, Artery Technology, All rights reserved.
|
||||
*
|
||||
* The software Board Support Package (BSP) that is made available to
|
||||
* download from Artery official website is the copyrighted work of Artery.
|
||||
* Artery authorizes customers to use, copy, and distribute the BSP
|
||||
* software and its related documentation for the purpose of design and
|
||||
* development in conjunction with Artery microcontrollers. Use of the
|
||||
* software is governed by this copyright notice and the following disclaimer.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
|
||||
* GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
|
||||
* TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
|
||||
* STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
|
||||
* INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
|
||||
*
|
||||
**************************************************************************
|
||||
*/
|
||||
|
||||
/** @addtogroup CMSIS
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup AT32F403A_407_system
|
||||
* @{
|
||||
*/
|
||||
|
||||
#include "at32f403a_407.h"
|
||||
|
||||
/** @addtogroup AT32F403A_407_system_private_defines
|
||||
* @{
|
||||
*/
|
||||
#define VECT_TAB_OFFSET 0x0 /*!< vector table base offset field. this value must be a multiple of 0x200. */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup AT32F403A_407_system_private_variables
|
||||
* @{
|
||||
*/
|
||||
unsigned int system_core_clock = HICK_VALUE; /*!< system clock frequency (core clock) */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup AT32F403A_407_system_private_functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief setup the microcontroller system
|
||||
* initialize the flash interface.
|
||||
* @note this function should be used only after reset.
|
||||
* @param none
|
||||
* @retval none
|
||||
*/
|
||||
void SystemInit (void)
|
||||
{
|
||||
#if defined (__FPU_USED) && (__FPU_USED == 1U)
|
||||
SCB->CPACR |= ((3U << 10U * 2U) | /* set cp10 full access */
|
||||
(3U << 11U * 2U) ); /* set cp11 full access */
|
||||
#endif
|
||||
|
||||
/* reset the crm clock configuration to the default reset state(for debug purpose) */
|
||||
/* set hicken bit */
|
||||
CRM->ctrl_bit.hicken = TRUE;
|
||||
|
||||
/* wait hick stable */
|
||||
while(CRM->ctrl_bit.hickstbl != SET);
|
||||
|
||||
/* hick used as system clock */
|
||||
CRM->cfg_bit.sclksel = CRM_SCLK_HICK;
|
||||
|
||||
/* wait sclk switch status */
|
||||
while(CRM->cfg_bit.sclksts != CRM_SCLK_HICK);
|
||||
|
||||
/* reset hexten, hextbyps, cfden and pllen bits */
|
||||
CRM->ctrl &= ~(0x010D0000U);
|
||||
|
||||
/* reset cfg register, include sclk switch, ahbdiv, apb1div, apb2div, adcdiv,
|
||||
clkout pllrcs, pllhextdiv, pllmult, usbdiv and pllrange bits */
|
||||
CRM->cfg = 0;
|
||||
|
||||
/* reset clkout[3], usbbufs, hickdiv, clkoutdiv */
|
||||
CRM->misc1 = 0;
|
||||
|
||||
/* disable all interrupts enable and clear pending bits */
|
||||
CRM->clkint = 0x009F0000;
|
||||
|
||||
#ifdef VECT_TAB_SRAM
|
||||
SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* vector table relocation in internal sram. */
|
||||
#else
|
||||
SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* vector table relocation in internal flash. */
|
||||
#endif
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief update system_core_clock variable according to clock register values.
|
||||
* the system_core_clock variable contains the core clock (hclk), it can
|
||||
* be used by the user application to setup the systick timer or configure
|
||||
* other parameters.
|
||||
* @param none
|
||||
* @retval none
|
||||
*/
|
||||
void system_core_clock_update(void)
|
||||
{
|
||||
uint32_t hext_prediv = 0, pll_mult = 0, pll_mult_h = 0, pll_clock_source = 0, temp = 0, div_value = 0;
|
||||
crm_sclk_type sclk_source;
|
||||
|
||||
static const uint8_t sys_ahb_div_table[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
|
||||
|
||||
/* get sclk source */
|
||||
sclk_source = crm_sysclk_switch_status_get();
|
||||
|
||||
switch(sclk_source)
|
||||
{
|
||||
case CRM_SCLK_HICK:
|
||||
if(((CRM->misc3_bit.hick_to_sclk) != RESET) && ((CRM->misc1_bit.hickdiv) != RESET))
|
||||
system_core_clock = HICK_VALUE * 6;
|
||||
else
|
||||
system_core_clock = HICK_VALUE;
|
||||
break;
|
||||
case CRM_SCLK_HEXT:
|
||||
system_core_clock = HEXT_VALUE;
|
||||
break;
|
||||
case CRM_SCLK_PLL:
|
||||
pll_clock_source = CRM->cfg_bit.pllrcs;
|
||||
{
|
||||
/* get multiplication factor */
|
||||
pll_mult = CRM->cfg_bit.pllmult_l;
|
||||
pll_mult_h = CRM->cfg_bit.pllmult_h;
|
||||
/* process high bits */
|
||||
if((pll_mult_h != 0U) || (pll_mult == 15U)){
|
||||
pll_mult += ((16U * pll_mult_h) + 1U);
|
||||
}
|
||||
else
|
||||
{
|
||||
pll_mult += 2U;
|
||||
}
|
||||
|
||||
if(pll_clock_source == 0x00)
|
||||
{
|
||||
/* hick divided by 2 selected as pll clock entry */
|
||||
system_core_clock = (HICK_VALUE >> 1) * pll_mult;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* hext selected as pll clock entry */
|
||||
if(CRM->cfg_bit.pllhextdiv != RESET)
|
||||
{
|
||||
hext_prediv = CRM->misc3_bit.hextdiv;
|
||||
|
||||
/* hext clock divided by 2 */
|
||||
system_core_clock = (HEXT_VALUE / (hext_prediv + 2)) * pll_mult;
|
||||
}
|
||||
else
|
||||
{
|
||||
system_core_clock = HEXT_VALUE * pll_mult;
|
||||
}
|
||||
}
|
||||
}
|
||||
break;
|
||||
default:
|
||||
system_core_clock = HICK_VALUE;
|
||||
break;
|
||||
}
|
||||
|
||||
/* compute sclk, ahbclk frequency */
|
||||
/* get ahb division */
|
||||
temp = CRM->cfg_bit.ahbdiv;
|
||||
div_value = sys_ahb_div_table[temp];
|
||||
/* ahbclk frequency */
|
||||
system_core_clock = system_core_clock >> div_value;
|
||||
}
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
|
@ -0,0 +1,90 @@
|
|||
/**
|
||||
**************************************************************************
|
||||
* @file system_at32f403a_407.h
|
||||
* @brief cmsis cortex-m4 system header file.
|
||||
**************************************************************************
|
||||
*
|
||||
* Copyright (c) 2025, Artery Technology, All rights reserved.
|
||||
*
|
||||
* The software Board Support Package (BSP) that is made available to
|
||||
* download from Artery official website is the copyrighted work of Artery.
|
||||
* Artery authorizes customers to use, copy, and distribute the BSP
|
||||
* software and its related documentation for the purpose of design and
|
||||
* development in conjunction with Artery microcontrollers. Use of the
|
||||
* software is governed by this copyright notice and the following disclaimer.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
|
||||
* GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
|
||||
* TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
|
||||
* STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
|
||||
* INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
|
||||
*
|
||||
**************************************************************************
|
||||
*/
|
||||
|
||||
#ifndef __SYSTEM_AT32F403A_407_H
|
||||
#define __SYSTEM_AT32F403A_407_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/** @addtogroup CMSIS
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup AT32F403A_407_system
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup AT32F403A_407_system_clock_stable_definition
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define HEXT_STABLE_DELAY (5000u)
|
||||
#define PLL_STABLE_DELAY (500u)
|
||||
#define SystemCoreClock system_core_clock
|
||||
#define DUMMY_NOP() {__NOP();__NOP();__NOP();__NOP();__NOP(); \
|
||||
__NOP();__NOP();__NOP();__NOP();__NOP(); \
|
||||
__NOP();__NOP();__NOP();__NOP();__NOP(); \
|
||||
__NOP();__NOP();__NOP();__NOP();__NOP();}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup AT32F403A_407_system_exported_variables
|
||||
* @{
|
||||
*/
|
||||
|
||||
extern unsigned int system_core_clock; /*!< system clock frequency (core clock) */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup AT32F403A_407_system_exported_functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
extern void SystemInit(void);
|
||||
extern void system_core_clock_update(void);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,298 @@
|
|||
<html>
|
||||
|
||||
<head>
|
||||
<meta http-equiv=Content-Type content="text/html; charset=gb2312">
|
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<meta name=Generator content="Microsoft Word 15 (filtered)">
|
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|
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|
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|
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@page WordSection1
|
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{size:595.3pt 841.9pt;
|
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|
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|
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div.WordSection1
|
||||
{page:WordSection1;}
|
||||
/* List Definitions */
|
||||
ol
|
||||
{margin-bottom:0cm;}
|
||||
ul
|
||||
{margin-bottom:0cm;}
|
||||
-->
|
||||
</style>
|
||||
|
||||
</head>
|
||||
|
||||
<body lang=ZH-CN style='text-justify-trim:punctuation'>
|
||||
|
||||
<div class=WordSection1 style='layout-grid:15.6pt'>
|
||||
|
||||
<p class=MsoNormal align=center style='text-align:center;word-break:break-all'><b><i><span
|
||||
lang=EN-US style='font-size:16.0pt;font-family:"Arial",sans-serif;color:#0070C0'>Release
|
||||
Notes for </span></i></b></p>
|
||||
|
||||
<p class=MsoNormal align=center style='text-align:center;word-break:break-all'><b><i><span
|
||||
lang=EN-US style='font-size:16.0pt;font-family:"Arial",sans-serif;color:#0070C0'>AT32F403A_407
|
||||
Firmware Library Drivers</span></i></b></p>
|
||||
|
||||
<p class=MsoNormal style='word-break:break-all'><b><span lang=EN-US
|
||||
style='font-family:"Arial",sans-serif;color:#7030A0'>V2.0.8-2025/11/24</span></b></p>
|
||||
|
||||
<p class=MsoListParagraph style='margin-left:21.0pt;text-indent:-21.0pt;
|
||||
word-break:break-all'><span lang=EN-US>1.<span style='font:7.0pt "Times New Roman"'>
|
||||
</span></span><span lang=EN-US>GPIO</span></p>
|
||||
|
||||
<p class=MsoListParagraph style='margin-left:42.0pt;text-indent:-21.0pt;
|
||||
word-break:break-all'><span lang=EN-US style='font-family:Wingdings'>l<span
|
||||
style='font:7.0pt "Times New Roman"'> </span></span><span
|
||||
style='font-family:宋体'>更新</span><span lang=EN-US>gpio_bits_toggle()</span><span
|
||||
style='font-family:宋体'>函数，操作流程更严谨。</span></p>
|
||||
|
||||
<p class=MsoListParagraph style='margin-left:21.0pt;text-indent:-21.0pt;
|
||||
word-break:break-all'><span lang=EN-US>2.<span style='font:7.0pt "Times New Roman"'>
|
||||
</span></span><span lang=EN-US>USB</span></p>
|
||||
|
||||
<p class=MsoListParagraph style='margin-left:42.0pt;text-indent:-21.0pt;
|
||||
word-break:break-all'><span lang=EN-US style='font-family:Wingdings'>l<span
|
||||
style='font:7.0pt "Times New Roman"'> </span></span><span
|
||||
style='font-family:宋体'>更新</span><span lang=EN-US>usb_ept_open()</span><span
|
||||
style='font-family:宋体'>函数，当设置同步</span><span lang=EN-US>IN</span><span
|
||||
style='font-family:宋体'>传输端点时，默认将端点状态由</span><span lang=EN-US>NAK</span><span
|
||||
style='font-family:宋体'>改为</span><span lang=EN-US>DISABLE</span><span
|
||||
style='font-family:宋体'>，解决同步端点在错误的</span><span lang=EN-US>NAK</span><span
|
||||
style='font-family:宋体'>状态下引起错误。</span></p>
|
||||
|
||||
<p class=MsoListParagraph style='margin-left:21.0pt;text-indent:-21.0pt;
|
||||
word-break:break-all'><span lang=EN-US>3.<span style='font:7.0pt "Times New Roman"'>
|
||||
</span></span><span lang=EN-US>TMR</span></p>
|
||||
|
||||
<p class=MsoListParagraph style='margin-left:42.0pt;text-indent:-21.0pt;
|
||||
word-break:break-all'><span lang=EN-US style='font-family:Wingdings'>l<span
|
||||
style='font:7.0pt "Times New Roman"'> </span></span><span
|
||||
style='font-family:宋体'>更新</span><span lang=EN-US>tmr_pwm_input_config()</span><span
|
||||
style='font-family:宋体'>、</span><span lang=EN-US>tmr_encoder_mode_config()</span><span
|
||||
style='font-family:宋体'>和</span><span lang=EN-US>tmr_output_channel_config()</span><span
|
||||
style='font-family:宋体'>函数。通道模式配置前关闭通道使能，否则通道模式无法切换。</span></p>
|
||||
|
||||
<p class=MsoListParagraph style='margin-left:21.0pt;text-indent:-21.0pt;
|
||||
word-break:break-all'><span lang=EN-US>4.<span style='font:7.0pt "Times New Roman"'>
|
||||
</span></span><span style='font-family:宋体'>更新部分注释。</span></p>
|
||||
|
||||
<p class=MsoNormal style='word-break:break-all'><b><span lang=EN-US
|
||||
style='font-family:"Arial",sans-serif;color:#7030A0'> </span></b></p>
|
||||
|
||||
<p class=MsoNormal style='word-break:break-all'><b><span lang=EN-US
|
||||
style='font-family:"Arial",sans-serif;color:#7030A0'>V2.0.7-2025/04/25</span></b></p>
|
||||
|
||||
<p class=MsoListParagraph style='margin-left:21.0pt;text-indent:-21.0pt'><span
|
||||
lang=EN-US>1.<span style='font:7.0pt "Times New Roman"'>
|
||||
</span></span><span style='font-family:宋体'>更新</span><span lang=EN-US>RTC</span><span
|
||||
style='font-family:宋体'>计数值读取流程。</span></p>
|
||||
|
||||
<p class=MsoListParagraph style='margin-left:21.0pt;text-indent:-21.0pt'><span
|
||||
lang=EN-US>2.<span style='font:7.0pt "Times New Roman"'>
|
||||
</span></span><span style='font-family:宋体'>更新</span><span lang=EN-US>Flash</span><span
|
||||
style='font-family:宋体'>驱动，优化部分流程。</span></p>
|
||||
|
||||
<p class=MsoListParagraph style='margin-left:21.0pt;text-indent:-21.0pt'><span
|
||||
lang=EN-US>3.<span style='font:7.0pt "Times New Roman"'>
|
||||
</span></span><span style='font-family:宋体'>新增</span><span lang=EN-US>gpio_bits_toggle</span><span
|
||||
style='font-family:宋体'>函数。</span></p>
|
||||
|
||||
<p class=MsoNormal><span lang=EN-US> </span></p>
|
||||
|
||||
<p class=MsoNormal style='word-break:break-all'><b><span lang=EN-US
|
||||
style='font-family:"Arial",sans-serif;color:#7030A0'>V2.0.6-2024/12/13</span></b></p>
|
||||
|
||||
<p class=MsoListParagraph style='margin-left:21.0pt;text-indent:-21.0pt'><span
|
||||
lang=EN-US>1.<span style='font:7.0pt "Times New Roman"'>
|
||||
</span></span><span style='font-family:宋体'>更新</span><span lang=EN-US>CAN</span><span
|
||||
style='font-family:宋体'>驱动。</span></p>
|
||||
|
||||
<p class=MsoListParagraph style='margin-left:21.0pt;text-indent:-21.0pt'><span
|
||||
lang=EN-US>2.<span style='font:7.0pt "Times New Roman"'>
|
||||
</span></span><span style='font-family:宋体'>更新</span><span lang=EN-US>Flash</span><span
|
||||
style='font-family:宋体'>驱动。</span></p>
|
||||
|
||||
<p class=MsoListParagraph style='margin-left:21.0pt;text-indent:-21.0pt'><span
|
||||
lang=EN-US>3.<span style='font:7.0pt "Times New Roman"'>
|
||||
</span></span><span style='font-family:宋体'>更新部分注释。</span></p>
|
||||
|
||||
<p class=MsoNormal><span lang=EN-US> </span></p>
|
||||
|
||||
<p class=MsoNormal style='word-break:break-all'><b><span lang=EN-US
|
||||
style='font-family:"Arial",sans-serif;color:#7030A0'>V2.0.5-2024/08/08</span></b></p>
|
||||
|
||||
<p class=MsoListParagraph style='margin-left:21.0pt;text-indent:-21.0pt'><span
|
||||
lang=EN-US>1.<span style='font:7.0pt "Times New Roman"'>
|
||||
</span></span><span style='font-family:宋体'>更新</span><span lang=EN-US>i2c_flag_clear</span><span
|
||||
style='font-family:宋体'>和</span><span lang=EN-US>i2c_init</span><span
|
||||
style='font-family:宋体'>函数。</span></p>
|
||||
|
||||
<p class=MsoListParagraph style='margin-left:21.0pt;text-indent:-21.0pt'><span
|
||||
lang=EN-US>2.<span style='font:7.0pt "Times New Roman"'>
|
||||
</span></span><span style='font-family:宋体'>更新部分注释。</span></p>
|
||||
|
||||
<p class=MsoNormal><span lang=EN-US> </span></p>
|
||||
|
||||
<p class=MsoNormal style='word-break:break-all'><b><span lang=EN-US
|
||||
style='font-family:"Arial",sans-serif;color:#7030A0'>V2.0.4-2024/01/05</span></b></p>
|
||||
|
||||
<p class=MsoListParagraph style='margin-left:21.0pt;text-indent:-21.0pt'><span
|
||||
lang=EN-US>1.<span style='font:7.0pt "Times New Roman"'>
|
||||
</span></span><span style='font-family:宋体'>完善部分驱动流程在</span><span lang=EN-US>IAR7.4</span><span
|
||||
style='font-family:宋体'>下的编译警告。</span></p>
|
||||
|
||||
<p class=MsoListParagraph style='margin-left:21.0pt;text-indent:-21.0pt'><span
|
||||
lang=EN-US>2.<span style='font:7.0pt "Times New Roman"'>
|
||||
</span></span><span style='font-family:宋体'>完善</span><span lang=EN-US>EMAC</span><span
|
||||
style='font-family:宋体'>的</span><span lang=EN-US>PTP</span><span
|
||||
style='font-family:宋体'>驱动。</span></p>
|
||||
|
||||
<p class=MsoNormal><span lang=EN-US> </span></p>
|
||||
|
||||
<p class=MsoNormal style='word-break:break-all'><b><span lang=EN-US
|
||||
style='font-family:"Arial",sans-serif;color:#7030A0'>V2.0.3-2023/10/26</span></b></p>
|
||||
|
||||
<p class=MsoListParagraph style='margin-left:21.0pt;text-indent:-21.0pt'><span
|
||||
lang=EN-US>1.<span style='font:7.0pt "Times New Roman"'>
|
||||
</span></span><span style='font-family:宋体'>各</span><span lang=EN-US>IP</span><span
|
||||
style='font-family:宋体'>驱动新增</span><span lang=EN-US>interrupt_flag_get</span><span
|
||||
style='font-family:宋体'>函数。</span></p>
|
||||
|
||||
<p class=MsoListParagraph style='margin-left:21.0pt;text-indent:-21.0pt'><span
|
||||
lang=EN-US>2.<span style='font:7.0pt "Times New Roman"'>
|
||||
</span></span><span style='font-family:宋体'>优化系统时钟切换流程。</span></p>
|
||||
|
||||
<p class=MsoNormal><span lang=EN-US> </span></p>
|
||||
|
||||
<p class=MsoNormal style='word-break:break-all'><b><span lang=EN-US
|
||||
style='font-family:"Arial",sans-serif;color:#7030A0'>V2.0.2-2023/08/04</span></b></p>
|
||||
|
||||
<p class=MsoListParagraph style='margin-left:21.0pt;text-indent:-21.0pt'><span
|
||||
lang=EN-US>1.<span style='font:7.0pt "Times New Roman"'>
|
||||
</span></span><span lang=EN-US>CRC</span><span style='font-family:宋体'>驱动新增多项式及多项式宽度可修改的支持。</span></p>
|
||||
|
||||
<p class=MsoListParagraph style='margin-left:21.0pt;text-indent:-21.0pt'><span
|
||||
lang=EN-US>2.<span style='font:7.0pt "Times New Roman"'>
|
||||
</span></span><span lang=EN-US>FLASH</span><span style='font-family:宋体'>中新增</span><span
|
||||
lang=EN-US>flash_spim_dummy_read</span><span style='font-family:宋体'>和</span><span
|
||||
lang=EN-US>flash_spim_mass_program</span><span style='font-family:宋体'>函数。</span></p>
|
||||
|
||||
<p class=MsoListParagraph style='margin-left:21.0pt;text-indent:-21.0pt'><span
|
||||
lang=EN-US>3.<span style='font:7.0pt "Times New Roman"'>
|
||||
</span></span><span style='font-family:宋体'>更新了</span><span lang=EN-US>adc_ordinary_channel_set</span><span
|
||||
style='font-family:宋体'>和</span><span lang=EN-US>adc_preempt_channel_set</span><span
|
||||
style='font-family:宋体'>函数流程。</span></p>
|
||||
|
||||
<p class=MsoListParagraph style='margin-left:21.0pt;text-indent:-21.0pt'><span
|
||||
lang=EN-US>4.<span style='font:7.0pt "Times New Roman"'>
|
||||
</span></span><span style='font-family:宋体'>更新部分注释。</span></p>
|
||||
|
||||
<p class=MsoNormal><span lang=EN-US> </span></p>
|
||||
|
||||
<p class=MsoNormal style='word-break:break-all'><b><span lang=EN-US
|
||||
style='font-family:"Arial",sans-serif;color:#7030A0'>V2.0.1-2023/02/16</span></b></p>
|
||||
|
||||
<p class=MsoListParagraph style='margin-left:21.0pt;text-indent:-21.0pt'><span
|
||||
lang=EN-US>1.<span style='font:7.0pt "Times New Roman"'>
|
||||
</span></span><span style='font-family:宋体'>更新</span><span lang=EN-US>EMAC</span><span
|
||||
style='font-family:宋体'>最大包长宏定义</span><span lang=EN-US>EMAC_MAX_PACKET_LENGTH</span><span
|
||||
style='font-family:宋体'>值为</span><span lang=EN-US>1524</span><span
|
||||
style='font-family:宋体'>。</span></p>
|
||||
|
||||
<p class=MsoNormal><span lang=EN-US> </span></p>
|
||||
|
||||
<p class=MsoNormal style='word-break:break-all'><b><span lang=EN-US
|
||||
style='font-family:"Arial",sans-serif;color:#7030A0'>V2.0.0-2022/11/18</span></b></p>
|
||||
|
||||
<p class=MsoListParagraph style='margin-left:21.0pt;text-indent:-21.0pt'><span
|
||||
lang=EN-US>1.<span style='font:7.0pt "Times New Roman"'>
|
||||
</span></span><span style='font-family:宋体'>更新了</span><span lang=EN-US>xmc_ext_timing_config</span><span
|
||||
style='font-family:宋体'>函数。</span></p>
|
||||
|
||||
<p class=MsoListParagraph style='margin-left:21.0pt;text-indent:-21.0pt'><span
|
||||
lang=EN-US>2.<span style='font:7.0pt "Times New Roman"'>
|
||||
</span></span><span style='font-family:宋体'>更新当</span><span lang=EN-US>HICK</span><span
|
||||
style='font-family:宋体'>作为</span><span lang=EN-US>PLL</span><span
|
||||
style='font-family:宋体'>时钟源时</span><span lang=EN-US>CRM_HICK48_NODIV</span><span
|
||||
style='font-family:宋体'>作为默认设置。</span></p>
|
||||
|
||||
</div>
|
||||
|
||||
</body>
|
||||
|
||||
</html>
|
||||
|
|
@ -0,0 +1,202 @@
|
|||
/**
|
||||
**************************************************************************
|
||||
* @file at32f403a_407_acc.h
|
||||
* @brief at32f403a_407 acc header file
|
||||
**************************************************************************
|
||||
*
|
||||
* Copyright (c) 2025, Artery Technology, All rights reserved.
|
||||
*
|
||||
* The software Board Support Package (BSP) that is made available to
|
||||
* download from Artery official website is the copyrighted work of Artery.
|
||||
* Artery authorizes customers to use, copy, and distribute the BSP
|
||||
* software and its related documentation for the purpose of design and
|
||||
* development in conjunction with Artery microcontrollers. Use of the
|
||||
* software is governed by this copyright notice and the following disclaimer.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
|
||||
* GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
|
||||
* TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
|
||||
* STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
|
||||
* INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
|
||||
*
|
||||
**************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __AT32F403A_407_ACC_H
|
||||
#define __AT32F403A_407_ACC_H
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "at32f403a_407.h"
|
||||
|
||||
/** @addtogroup AT32F403A_407_periph_driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup ACC
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup ACC_exported_constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define ACC_CAL_HICKCAL ((uint16_t)0x0000) /*!< acc hick calibration */
|
||||
#define ACC_CAL_HICKTRIM ((uint16_t)0x0002) /*!< acc hick trim */
|
||||
|
||||
#define ACC_RSLOST_FLAG ((uint16_t)0x0002) /*!< acc reference signal lost error flag */
|
||||
#define ACC_CALRDY_FLAG ((uint16_t)0x0001) /*!< acc internal high-speed clock calibration ready error flag */
|
||||
|
||||
#define ACC_CALRDYIEN_INT ((uint16_t)0x0020) /*!< acc internal high-speed clock calibration ready interrupt enable */
|
||||
#define ACC_EIEN_INT ((uint16_t)0x0010) /*!< acc reference signal lost interrupt enable */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup ACC_exported_types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief type define acc register all
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
|
||||
/**
|
||||
* @brief acc sts register, offset:0x00
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t sts;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t calrdy : 1; /* [0] */
|
||||
__IO uint32_t rslost : 1; /* [1] */
|
||||
__IO uint32_t reserved1 : 30;/* [31:2] */
|
||||
} sts_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief acc ctrl1 register, offset:0x04
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t ctrl1;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t calon : 1; /* [0] */
|
||||
__IO uint32_t entrim : 1; /* [1] */
|
||||
__IO uint32_t reserved1 : 2; /* [3:2] */
|
||||
__IO uint32_t eien : 1; /* [4] */
|
||||
__IO uint32_t calrdyien : 1; /* [5] */
|
||||
__IO uint32_t reserved2 : 2; /* [7:6] */
|
||||
__IO uint32_t step : 4; /* [11:8] */
|
||||
__IO uint32_t reserved3 : 20;/* [31:12] */
|
||||
} ctrl1_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief acc ctrl2 register, offset:0x08
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t ctrl2;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t hickcal : 8; /* [7:0] */
|
||||
__IO uint32_t hicktrim : 6; /* [13:8] */
|
||||
__IO uint32_t reserved1 : 18;/* [31:14] */
|
||||
} ctrl2_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief acc acc_c1 register, offset:0x0C
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t c1;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t c1 : 16;/* [15:0] */
|
||||
__IO uint32_t reserved1 : 16;/* [31:16] */
|
||||
} c1_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief acc acc_c2 register, offset:0x10
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t c2;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t c2 : 16;/* [15:0] */
|
||||
__IO uint32_t reserved1 : 16;/* [31:16] */
|
||||
} c2_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief acc acc_c3 register, offset:0x14
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t c3;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t c3 : 16;/* [15:0] */
|
||||
__IO uint32_t reserved1 : 16;/* [31:16] */
|
||||
} c3_bit;
|
||||
};
|
||||
} acc_type;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#define ACC ((acc_type *) ACC_BASE)
|
||||
|
||||
/** @defgroup ACC_exported_functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
void acc_calibration_mode_enable(uint16_t acc_trim, confirm_state new_state);
|
||||
void acc_step_set(uint8_t step_value);
|
||||
void acc_interrupt_enable(uint16_t acc_int, confirm_state new_state);
|
||||
uint8_t acc_hicktrim_get(void);
|
||||
uint8_t acc_hickcal_get(void);
|
||||
void acc_write_c1(uint16_t acc_c1_value);
|
||||
void acc_write_c2(uint16_t acc_c2_value);
|
||||
void acc_write_c3(uint16_t acc_c3_value);
|
||||
uint16_t acc_read_c1(void);
|
||||
uint16_t acc_read_c2(void);
|
||||
uint16_t acc_read_c3(void);
|
||||
flag_status acc_flag_get(uint16_t acc_flag);
|
||||
flag_status acc_interrupt_flag_get(uint16_t acc_flag);
|
||||
void acc_flag_clear(uint16_t acc_flag);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,642 @@
|
|||
/**
|
||||
**************************************************************************
|
||||
* @file at32f403a_407_adc.h
|
||||
* @brief at32f403a_407 adc header file
|
||||
**************************************************************************
|
||||
*
|
||||
* Copyright (c) 2025, Artery Technology, All rights reserved.
|
||||
*
|
||||
* The software Board Support Package (BSP) that is made available to
|
||||
* download from Artery official website is the copyrighted work of Artery.
|
||||
* Artery authorizes customers to use, copy, and distribute the BSP
|
||||
* software and its related documentation for the purpose of design and
|
||||
* development in conjunction with Artery microcontrollers. Use of the
|
||||
* software is governed by this copyright notice and the following disclaimer.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
|
||||
* GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
|
||||
* TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
|
||||
* STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
|
||||
* INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
|
||||
*
|
||||
**************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __AT32F403A_407_ADC_H
|
||||
#define __AT32F403A_407_ADC_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "at32f403a_407.h"
|
||||
|
||||
/** @addtogroup AT32F403A_407_periph_driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup ADC
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup ADC_interrupts_definition
|
||||
* @brief adc interrupt
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define ADC_CCE_INT ((uint32_t)0x00000020) /*!< channels conversion end interrupt */
|
||||
#define ADC_VMOR_INT ((uint32_t)0x00000040) /*!< voltage monitoring out of range interrupt */
|
||||
#define ADC_PCCE_INT ((uint32_t)0x00000080) /*!< preempt channels conversion end interrupt */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup ADC_flags_definition
|
||||
* @brief adc flag
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define ADC_VMOR_FLAG ((uint8_t)0x01) /*!< voltage monitoring out of range flag */
|
||||
#define ADC_CCE_FLAG ((uint8_t)0x02) /*!< channels conversion end flag */
|
||||
#define ADC_PCCE_FLAG ((uint8_t)0x04) /*!< preempt channels conversion end flag */
|
||||
#define ADC_PCCS_FLAG ((uint8_t)0x08) /*!< preempt channel conversion start flag */
|
||||
#define ADC_OCCS_FLAG ((uint8_t)0x10) /*!< ordinary channel conversion start flag */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup ADC_exported_types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief adc combine mode type(these options are reserved in adc2 and adc3)
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
ADC_INDEPENDENT_MODE = 0x00, /*!< independent mode */
|
||||
ADC_ORDINARY_SMLT_PREEMPT_SMLT_MODE = 0x01, /*!< combined ordinary simultaneous + preempt simultaneous mode */
|
||||
ADC_ORDINARY_SMLT_PREEMPT_INTERLTRIG_MODE = 0x02, /*!< combined ordinary simultaneous + preempt interleaved trigger mode */
|
||||
ADC_ORDINARY_SHORTSHIFT_PREEMPT_SMLT_MODE = 0x03, /*!< combined ordinary short shifting + preempt simultaneous mode */
|
||||
ADC_ORDINARY_LONGSHIFT_PREEMPT_SMLT_MODE = 0x04, /*!< combined ordinary long shifting + preempt simultaneous mode */
|
||||
ADC_PREEMPT_SMLT_ONLY_MODE = 0x05, /*!< preempt simultaneous mode only */
|
||||
ADC_ORDINARY_SMLT_ONLY_MODE = 0x06, /*!< ordinary simultaneous mode only */
|
||||
ADC_ORDINARY_SHORTSHIFT_ONLY_MODE = 0x07, /*!< ordinary short shifting mode only */
|
||||
ADC_ORDINARY_LONGSHIFT_ONLY_MODE = 0x08, /*!< slow interleaved mode only */
|
||||
ADC_PREEMPT_INTERLTRIG_ONLY_MODE = 0x09 /*!< alternate trigger mode only */
|
||||
} adc_combine_mode_type;
|
||||
|
||||
/**
|
||||
* @brief adc data align type
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
ADC_RIGHT_ALIGNMENT = 0x00, /*!< data right alignment */
|
||||
ADC_LEFT_ALIGNMENT = 0x01 /*!< data left alignment */
|
||||
} adc_data_align_type;
|
||||
|
||||
/**
|
||||
* @brief adc channel select type
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
ADC_CHANNEL_0 = 0x00, /*!< adc channel 0 */
|
||||
ADC_CHANNEL_1 = 0x01, /*!< adc channel 1 */
|
||||
ADC_CHANNEL_2 = 0x02, /*!< adc channel 2 */
|
||||
ADC_CHANNEL_3 = 0x03, /*!< adc channel 3 */
|
||||
ADC_CHANNEL_4 = 0x04, /*!< adc channel 4 */
|
||||
ADC_CHANNEL_5 = 0x05, /*!< adc channel 5 */
|
||||
ADC_CHANNEL_6 = 0x06, /*!< adc channel 6 */
|
||||
ADC_CHANNEL_7 = 0x07, /*!< adc channel 7 */
|
||||
ADC_CHANNEL_8 = 0x08, /*!< adc channel 8 */
|
||||
ADC_CHANNEL_9 = 0x09, /*!< adc channel 9 */
|
||||
ADC_CHANNEL_10 = 0x0A, /*!< adc channel 10 */
|
||||
ADC_CHANNEL_11 = 0x0B, /*!< adc channel 11 */
|
||||
ADC_CHANNEL_12 = 0x0C, /*!< adc channel 12 */
|
||||
ADC_CHANNEL_13 = 0x0D, /*!< adc channel 13 */
|
||||
ADC_CHANNEL_14 = 0x0E, /*!< adc channel 14 */
|
||||
ADC_CHANNEL_15 = 0x0F, /*!< adc channel 15 */
|
||||
ADC_CHANNEL_16 = 0x10, /*!< adc channel 16 */
|
||||
ADC_CHANNEL_17 = 0x11 /*!< adc channel 17 */
|
||||
} adc_channel_select_type;
|
||||
|
||||
/**
|
||||
* @brief adc sampletime select type
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
ADC_SAMPLETIME_1_5 = 0x00, /*!< adc sample time 1.5 cycle */
|
||||
ADC_SAMPLETIME_7_5 = 0x01, /*!< adc sample time 7.5 cycle */
|
||||
ADC_SAMPLETIME_13_5 = 0x02, /*!< adc sample time 13.5 cycle */
|
||||
ADC_SAMPLETIME_28_5 = 0x03, /*!< adc sample time 28.5 cycle */
|
||||
ADC_SAMPLETIME_41_5 = 0x04, /*!< adc sample time 41.5 cycle */
|
||||
ADC_SAMPLETIME_55_5 = 0x05, /*!< adc sample time 55.5 cycle */
|
||||
ADC_SAMPLETIME_71_5 = 0x06, /*!< adc sample time 71.5 cycle */
|
||||
ADC_SAMPLETIME_239_5 = 0x07 /*!< adc sample time 239.5 cycle */
|
||||
} adc_sampletime_select_type;
|
||||
|
||||
/**
|
||||
* @brief adc ordinary group trigger event select type
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
/*adc1 and adc2 ordinary trigger event*/
|
||||
ADC12_ORDINARY_TRIG_TMR1CH1 = 0x00, /*!< timer1 ch1 event as trigger source of adc1/adc2 ordinary sequence */
|
||||
ADC12_ORDINARY_TRIG_TMR1CH2 = 0x01, /*!< timer1 ch2 event as trigger source of adc1/adc2 ordinary sequence */
|
||||
ADC12_ORDINARY_TRIG_TMR1CH3 = 0x02, /*!< timer1 ch3 event as trigger source of adc1/adc2 ordinary sequence */
|
||||
ADC12_ORDINARY_TRIG_TMR2CH2 = 0x03, /*!< timer2 ch2 event as trigger source of adc1/adc2 ordinary sequence */
|
||||
ADC12_ORDINARY_TRIG_TMR3TRGOUT = 0x04, /*!< timer3 trgout event as trigger source of adc1/adc2 ordinary sequence */
|
||||
ADC12_ORDINARY_TRIG_TMR4CH4 = 0x05, /*!< timer4 ch4 event as trigger source of adc1/adc2 ordinary sequence */
|
||||
ADC12_ORDINARY_TRIG_EXINT11_TMR8TRGOUT = 0x06, /*!< exint line11/timer8 trgout event as trigger source of adc1/adc2 ordinary sequence */
|
||||
ADC12_ORDINARY_TRIG_SOFTWARE = 0x07, /*!< software(OCSWTRG) control bit as trigger source of adc1/adc2 ordinary sequence */
|
||||
ADC12_ORDINARY_TRIG_TMR1TRGOUT = 0x0D, /*!< timer1 trgout event as trigger source of adc1/adc2 ordinary sequence */
|
||||
ADC12_ORDINARY_TRIG_TMR8CH1 = 0x0E, /*!< timer8 ch1 event as trigger source of adc1/adc2 ordinary sequence */
|
||||
ADC12_ORDINARY_TRIG_TMR8CH2 = 0x0F, /*!< timer8 ch2 event as trigger source of adc1/adc2 ordinary sequence */
|
||||
/*adc3 ordinary trigger event*/
|
||||
ADC3_ORDINARY_TRIG_TMR3CH1 = 0x00, /*!< timer3 ch1 event as trigger source of adc3 ordinary sequence */
|
||||
ADC3_ORDINARY_TRIG_TMR2CH3 = 0x01, /*!< timer2 ch3 event as trigger source of adc3 ordinary sequence */
|
||||
ADC3_ORDINARY_TRIG_TMR1CH3 = 0x02, /*!< timer1 ch3 event as trigger source of adc3 ordinary sequence */
|
||||
ADC3_ORDINARY_TRIG_TMR8CH1 = 0x03, /*!< timer8 ch1 event as trigger source of adc3 ordinary sequence */
|
||||
ADC3_ORDINARY_TRIG_TMR8TRGOUT = 0x04, /*!< timer8 trgout event as trigger source of adc3 ordinary sequence */
|
||||
ADC3_ORDINARY_TRIG_TMR5CH1 = 0x05, /*!< timer5 ch1 event as trigger source of adc3 ordinary sequence */
|
||||
ADC3_ORDINARY_TRIG_TMR5CH3 = 0x06, /*!< timer5 ch3 event as trigger source of adc3 ordinary sequence */
|
||||
ADC3_ORDINARY_TRIG_SOFTWARE = 0x07, /*!< software(OCSWTRG) control bit as trigger source of adc3 ordinary sequence */
|
||||
ADC3_ORDINARY_TRIG_TMR1TRGOUT = 0x0D, /*!< timer1 trgout event as trigger source of adc3 ordinary sequence */
|
||||
ADC3_ORDINARY_TRIG_TMR1CH1 = 0x0E, /*!< timer1 ch1 event as trigger source of adc3 ordinary sequence */
|
||||
ADC3_ORDINARY_TRIG_TMR8CH3 = 0x0F /*!< timer8 ch3 event as trigger source of adc3 ordinary sequence */
|
||||
} adc_ordinary_trig_select_type;
|
||||
|
||||
/**
|
||||
* @brief adc preempt group trigger event select type
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
/*adc1 and adc2 preempt trigger event*/
|
||||
ADC12_PREEMPT_TRIG_TMR1TRGOUT = 0x00, /*!< timer1 trgout event as trigger source of adc1/adc2 preempt sequence */
|
||||
ADC12_PREEMPT_TRIG_TMR1CH4 = 0x01, /*!< timer1 ch4 event as trigger source of adc1/adc2 preempt sequence */
|
||||
ADC12_PREEMPT_TRIG_TMR2TRGOUT = 0x02, /*!< timer2 trgout event as trigger source of adc1/adc2 preempt sequence */
|
||||
ADC12_PREEMPT_TRIG_TMR2CH1 = 0x03, /*!< timer2 ch1 event as trigger source of adc1/adc2 preempt sequence */
|
||||
ADC12_PREEMPT_TRIG_TMR3CH4 = 0x04, /*!< timer3 ch4 event as trigger source of adc1/adc2 preempt sequence */
|
||||
ADC12_PREEMPT_TRIG_TMR4TRGOUT = 0x05, /*!< timer4 trgout event as trigger source of adc1/adc2 preempt sequence */
|
||||
ADC12_PREEMPT_TRIG_EXINT15_TMR8CH4 = 0x06, /*!< exint line15/timer8 ch4 event as trigger source of adc1/adc2 preempt sequence */
|
||||
ADC12_PREEMPT_TRIG_SOFTWARE = 0x07, /*!< software(PCSWTRG) control bit as trigger source of adc1/adc2 preempt sequence */
|
||||
ADC12_PREEMPT_TRIG_TMR1CH1 = 0x0D, /*!< timer1 ch1 event as trigger source of adc1/adc2 preempt sequence */
|
||||
ADC12_PREEMPT_TRIG_TMR8CH1 = 0x0E, /*!< timer8 ch1 event as trigger source of adc1/adc2 preempt sequence */
|
||||
ADC12_PREEMPT_TRIG_TMR8TRGOUT = 0x0F, /*!< timer8 trgout event as trigger source of adc1/adc2 preempt sequence */
|
||||
/*adc3 preempt trigger event*/
|
||||
ADC3_PREEMPT_TRIG_TMR1TRGOUT = 0x00, /*!< timer1 trgout event as trigger source of adc3 preempt sequence */
|
||||
ADC3_PREEMPT_TRIG_TMR1CH4 = 0x01, /*!< timer1 ch4 event as trigger source of adc3 preempt sequence */
|
||||
ADC3_PREEMPT_TRIG_TMR4CH3 = 0x02, /*!< timer4 ch3 event as trigger source of adc3 preempt sequence */
|
||||
ADC3_PREEMPT_TRIG_TMR8CH2 = 0x03, /*!< timer8 ch2 event as trigger source of adc3 preempt sequence */
|
||||
ADC3_PREEMPT_TRIG_TMR8CH4 = 0x04, /*!< timer8 ch4 event as trigger source of adc3 preempt sequence */
|
||||
ADC3_PREEMPT_TRIG_TMR5TRGOUT = 0x05, /*!< timer5 trgout event as trigger source of adc3 preempt sequence */
|
||||
ADC3_PREEMPT_TRIG_TMR5CH4 = 0x06, /*!< timer5 ch4 event as trigger source of adc3 preempt sequence */
|
||||
ADC3_PREEMPT_TRIG_SOFTWARE = 0x07, /*!< software(PCSWTRG) control bit as trigger source of adc3 preempt sequence */
|
||||
ADC3_PREEMPT_TRIG_TMR1CH1 = 0x0D, /*!< timer1 ch1 event as trigger source of adc3 preempt sequence */
|
||||
ADC3_PREEMPT_TRIG_TMR1CH2 = 0x0E, /*!< timer1 ch2 event as trigger source of adc3 preempt sequence */
|
||||
ADC3_PREEMPT_TRIG_TMR8TRGOUT = 0x0F /*!< timer8 trgout event as trigger source of adc3 preempt sequence */
|
||||
} adc_preempt_trig_select_type;
|
||||
|
||||
/**
|
||||
* @brief adc preempt channel type
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
ADC_PREEMPT_CHANNEL_1 = 0x00, /*!< adc preempt channel 1 */
|
||||
ADC_PREEMPT_CHANNEL_2 = 0x01, /*!< adc preempt channel 2 */
|
||||
ADC_PREEMPT_CHANNEL_3 = 0x02, /*!< adc preempt channel 3 */
|
||||
ADC_PREEMPT_CHANNEL_4 = 0x03 /*!< adc preempt channel 4 */
|
||||
} adc_preempt_channel_type;
|
||||
|
||||
/**
|
||||
* @brief adc voltage_monitoring type
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
ADC_VMONITOR_SINGLE_ORDINARY = 0x00800200, /*!< voltage_monitoring on a single ordinary channel */
|
||||
ADC_VMONITOR_SINGLE_PREEMPT = 0x00400200, /*!< voltage_monitoring on a single preempt channel */
|
||||
ADC_VMONITOR_SINGLE_ORDINARY_PREEMPT = 0x00C00200, /*!< voltage_monitoring on a single ordinary or preempt channel */
|
||||
ADC_VMONITOR_ALL_ORDINARY = 0x00800000, /*!< voltage_monitoring on all ordinary channel */
|
||||
ADC_VMONITOR_ALL_PREEMPT = 0x00400000, /*!< voltage_monitoring on all preempt channel */
|
||||
ADC_VMONITOR_ALL_ORDINARY_PREEMPT = 0x00C00000, /*!< voltage_monitoring on all ordinary and preempt channel */
|
||||
ADC_VMONITOR_NONE = 0x00000000 /*!< no channel guarded by the voltage_monitoring */
|
||||
} adc_voltage_monitoring_type;
|
||||
|
||||
/**
|
||||
* @brief adc base config type
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
confirm_state sequence_mode; /*!< adc sequence mode */
|
||||
confirm_state repeat_mode; /*!< adc repeat mode */
|
||||
adc_data_align_type data_align; /*!< adc data alignment */
|
||||
uint8_t ordinary_channel_length; /*!< adc ordinary channel sequence length*/
|
||||
} adc_base_config_type;
|
||||
|
||||
/**
|
||||
* @brief type define adc register all
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
|
||||
/**
|
||||
* @brief adc sts register, offset:0x00
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t sts;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t vmor : 1; /* [0] */
|
||||
__IO uint32_t cce : 1; /* [1] */
|
||||
__IO uint32_t pcce : 1; /* [2] */
|
||||
__IO uint32_t pccs : 1; /* [3] */
|
||||
__IO uint32_t occs : 1; /* [4] */
|
||||
__IO uint32_t reserved1 : 27;/* [31:5] */
|
||||
} sts_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief adc ctrl1 register, offset:0x04
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t ctrl1;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t vmcsel : 5; /* [4:0] */
|
||||
__IO uint32_t cceien : 1; /* [5] */
|
||||
__IO uint32_t vmorien : 1; /* [6] */
|
||||
__IO uint32_t pcceien : 1; /* [7] */
|
||||
__IO uint32_t sqen : 1; /* [8] */
|
||||
__IO uint32_t vmsgen : 1; /* [9] */
|
||||
__IO uint32_t pcautoen : 1; /* [10] */
|
||||
__IO uint32_t ocpen : 1; /* [11] */
|
||||
__IO uint32_t pcpen : 1; /* [12] */
|
||||
__IO uint32_t ocpcnt : 3; /* [15:13] */
|
||||
__IO uint32_t mssel : 4; /* [19:16] */
|
||||
__IO uint32_t reserved1 : 2; /* [21:20] */
|
||||
__IO uint32_t pcvmen : 1; /* [22] */
|
||||
__IO uint32_t ocvmen : 1; /* [23] */
|
||||
__IO uint32_t reserved2 : 8; /* [31:24] */
|
||||
} ctrl1_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief adc ctrl2 register, offset:0x08
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t ctrl2;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t adcen : 1; /* [0] */
|
||||
__IO uint32_t rpen : 1; /* [1] */
|
||||
__IO uint32_t adcal : 1; /* [2] */
|
||||
__IO uint32_t adcalinit : 1; /* [3] */
|
||||
__IO uint32_t reserved1 : 4; /* [7:4] */
|
||||
__IO uint32_t ocdmaen : 1; /* [8] */
|
||||
__IO uint32_t reserved2 : 2; /* [10:9] */
|
||||
__IO uint32_t dtalign : 1; /* [11] */
|
||||
__IO uint32_t pctesel_l : 3; /* [14:12] */
|
||||
__IO uint32_t pcten : 1; /* [15] */
|
||||
__IO uint32_t reserved3 : 1; /* [16] */
|
||||
__IO uint32_t octesel_l : 3; /* [19:17] */
|
||||
__IO uint32_t octen : 1; /* [20] */
|
||||
__IO uint32_t pcswtrg : 1; /* [21] */
|
||||
__IO uint32_t ocswtrg : 1; /* [22] */
|
||||
__IO uint32_t itsrven : 1; /* [23] */
|
||||
__IO uint32_t pctesel_h : 1; /* [24] */
|
||||
__IO uint32_t octesel_h : 1; /* [25] */
|
||||
__IO uint32_t reserved4 : 6; /* [31:26] */
|
||||
} ctrl2_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief adc spt1 register, offset:0x0C
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t spt1;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t cspt10 : 3; /* [2:0] */
|
||||
__IO uint32_t cspt11 : 3; /* [5:3] */
|
||||
__IO uint32_t cspt12 : 3; /* [8:6] */
|
||||
__IO uint32_t cspt13 : 3; /* [11:9] */
|
||||
__IO uint32_t cspt14 : 3; /* [14:12] */
|
||||
__IO uint32_t cspt15 : 3; /* [17:15] */
|
||||
__IO uint32_t cspt16 : 3; /* [20:18] */
|
||||
__IO uint32_t cspt17 : 3; /* [23:21] */
|
||||
__IO uint32_t reserved1 : 8;/* [31:24] */
|
||||
} spt1_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief adc spt2 register, offset:0x10
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t spt2;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t cspt0 : 3;/* [2:0] */
|
||||
__IO uint32_t cspt1 : 3;/* [5:3] */
|
||||
__IO uint32_t cspt2 : 3;/* [8:6] */
|
||||
__IO uint32_t cspt3 : 3;/* [11:9] */
|
||||
__IO uint32_t cspt4 : 3;/* [14:12] */
|
||||
__IO uint32_t cspt5 : 3;/* [17:15] */
|
||||
__IO uint32_t cspt6 : 3;/* [20:18] */
|
||||
__IO uint32_t cspt7 : 3;/* [23:21] */
|
||||
__IO uint32_t cspt8 : 3;/* [26:24] */
|
||||
__IO uint32_t cspt9 : 3;/* [29:27] */
|
||||
__IO uint32_t reserved1 : 2;/* [31:30] */
|
||||
} spt2_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief adc pcdto1 register, offset:0x14
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t pcdto1;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t pcdto1 : 12; /* [11:0] */
|
||||
__IO uint32_t reserved1 : 20; /* [31:12] */
|
||||
} pcdto1_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief adc pcdto2 register, offset:0x18
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t pcdto2;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t pcdto2 : 12; /* [11:0] */
|
||||
__IO uint32_t reserved1 : 20; /* [31:12] */
|
||||
} pcdto2_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief adc pcdto3 register, offset:0x1C
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t pcdto3;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t pcdto3 : 12; /* [11:0] */
|
||||
__IO uint32_t reserved1 : 20; /* [31:12] */
|
||||
} pcdto3_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief adc pcdto4 register, offset:0x20
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t pcdto4;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t pcdto4 : 12; /* [11:0] */
|
||||
__IO uint32_t reserved1 : 20; /* [31:12] */
|
||||
} pcdto4_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief adc vmhb register, offset:0x24
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t vmhb;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t vmhb : 12; /* [11:0] */
|
||||
__IO uint32_t reserved1 : 20; /* [31:12] */
|
||||
} vmhb_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief adc vmlb register, offset:0x28
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t vmlb;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t vmlb : 12; /* [11:0] */
|
||||
__IO uint32_t reserved1 : 20; /* [31:12] */
|
||||
} vmlb_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief adc osq1 register, offset:0x2C
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t osq1;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t osn13 : 5; /* [4:0] */
|
||||
__IO uint32_t osn14 : 5; /* [9:5] */
|
||||
__IO uint32_t osn15 : 5; /* [14:10] */
|
||||
__IO uint32_t osn16 : 5; /* [19:15] */
|
||||
__IO uint32_t oclen : 4; /* [23:20] */
|
||||
__IO uint32_t reserved1 : 8; /* [31:24] */
|
||||
} osq1_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief adc osq2 register, offset:0x30
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t osq2;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t osn7 : 5; /* [4:0] */
|
||||
__IO uint32_t osn8 : 5; /* [9:5] */
|
||||
__IO uint32_t osn9 : 5; /* [14:10] */
|
||||
__IO uint32_t osn10 : 5; /* [19:15] */
|
||||
__IO uint32_t osn11 : 5; /* [24:20] */
|
||||
__IO uint32_t osn12 : 5; /* [29:25] */
|
||||
__IO uint32_t reserved1 : 2; /* [31:30] */
|
||||
} osq2_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief adc osq3 register, offset:0x34
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t osq3;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t osn1 : 5; /* [4:0] */
|
||||
__IO uint32_t osn2 : 5; /* [9:5] */
|
||||
__IO uint32_t osn3 : 5; /* [14:10] */
|
||||
__IO uint32_t osn4 : 5; /* [19:15] */
|
||||
__IO uint32_t osn5 : 5; /* [24:20] */
|
||||
__IO uint32_t osn6 : 5; /* [29:25] */
|
||||
__IO uint32_t reserved1 : 2; /* [31:30] */
|
||||
} osq3_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief adc psq register, offset:0x38
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t psq;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t psn1 : 5; /* [4:0] */
|
||||
__IO uint32_t psn2 : 5; /* [9:5] */
|
||||
__IO uint32_t psn3 : 5; /* [14:10] */
|
||||
__IO uint32_t psn4 : 5; /* [19:15] */
|
||||
__IO uint32_t pclen : 2; /* [21:20] */
|
||||
__IO uint32_t reserved1 : 10;/* [31:22] */
|
||||
} psq_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief adc pdt1 register, offset:0x3C
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t pdt1;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t pdt1 : 16; /* [15:0] */
|
||||
__IO uint32_t reserved1 : 16; /* [31:16] */
|
||||
} pdt1_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief adc pdt2 register, offset:0x40
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t pdt2;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t pdt2 : 16; /* [15:0] */
|
||||
__IO uint32_t reserved1 : 16; /* [31:16] */
|
||||
} pdt2_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief adc pdt3 register, offset:0x44
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t pdt3;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t pdt3 : 16; /* [15:0] */
|
||||
__IO uint32_t reserved1 : 16; /* [31:16] */
|
||||
} pdt3_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief adc pdt4 register, offset:0x48
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t pdt4;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t pdt4 : 16; /* [15:0] */
|
||||
__IO uint32_t reserved1 : 16; /* [31:16] */
|
||||
} pdt4_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief adc odt register, offset:0x4C
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t odt;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t odt : 16; /* [15:0] */
|
||||
__IO uint32_t adc2odt : 16; /* [31:16] */
|
||||
} odt_bit;
|
||||
};
|
||||
|
||||
} adc_type;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#define ADC1 ((adc_type *) ADC1_BASE)
|
||||
#define ADC2 ((adc_type *) ADC2_BASE)
|
||||
#define ADC3 ((adc_type *) ADC3_BASE)
|
||||
|
||||
/** @defgroup ADC_exported_functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
void adc_reset(adc_type *adc_x);
|
||||
void adc_enable(adc_type *adc_x, confirm_state new_state);
|
||||
void adc_combine_mode_select(adc_combine_mode_type combine_mode);
|
||||
void adc_base_default_para_init(adc_base_config_type *adc_base_struct);
|
||||
void adc_base_config(adc_type *adc_x, adc_base_config_type *adc_base_struct);
|
||||
void adc_dma_mode_enable(adc_type *adc_x, confirm_state new_state);
|
||||
void adc_interrupt_enable(adc_type *adc_x, uint32_t adc_int, confirm_state new_state);
|
||||
void adc_calibration_init(adc_type *adc_x);
|
||||
flag_status adc_calibration_init_status_get(adc_type *adc_x);
|
||||
void adc_calibration_start(adc_type *adc_x);
|
||||
flag_status adc_calibration_status_get(adc_type *adc_x);
|
||||
void adc_voltage_monitor_enable(adc_type *adc_x, adc_voltage_monitoring_type adc_voltage_monitoring);
|
||||
void adc_voltage_monitor_threshold_value_set(adc_type *adc_x, uint16_t adc_high_threshold, uint16_t adc_low_threshold);
|
||||
void adc_voltage_monitor_single_channel_select(adc_type *adc_x, adc_channel_select_type adc_channel);
|
||||
void adc_ordinary_channel_set(adc_type *adc_x, adc_channel_select_type adc_channel, uint8_t adc_sequence, adc_sampletime_select_type adc_sampletime);
|
||||
void adc_preempt_channel_length_set(adc_type *adc_x, uint8_t adc_channel_lenght);
|
||||
void adc_preempt_channel_set(adc_type *adc_x, adc_channel_select_type adc_channel, uint8_t adc_sequence, adc_sampletime_select_type adc_sampletime);
|
||||
void adc_ordinary_conversion_trigger_set(adc_type *adc_x, adc_ordinary_trig_select_type adc_ordinary_trig, confirm_state new_state);
|
||||
void adc_preempt_conversion_trigger_set(adc_type *adc_x, adc_preempt_trig_select_type adc_preempt_trig, confirm_state new_state);
|
||||
void adc_preempt_offset_value_set(adc_type *adc_x, adc_preempt_channel_type adc_preempt_channel, uint16_t adc_offset_value);
|
||||
void adc_ordinary_part_count_set(adc_type *adc_x, uint8_t adc_channel_count);
|
||||
void adc_ordinary_part_mode_enable(adc_type *adc_x, confirm_state new_state);
|
||||
void adc_preempt_part_mode_enable(adc_type *adc_x, confirm_state new_state);
|
||||
void adc_preempt_auto_mode_enable(adc_type *adc_x, confirm_state new_state);
|
||||
void adc_tempersensor_vintrv_enable(confirm_state new_state);
|
||||
void adc_ordinary_software_trigger_enable(adc_type *adc_x, confirm_state new_state);
|
||||
flag_status adc_ordinary_software_trigger_status_get(adc_type *adc_x);
|
||||
void adc_preempt_software_trigger_enable(adc_type *adc_x, confirm_state new_state);
|
||||
flag_status adc_preempt_software_trigger_status_get(adc_type *adc_x);
|
||||
uint16_t adc_ordinary_conversion_data_get(adc_type *adc_x);
|
||||
uint32_t adc_combine_ordinary_conversion_data_get(void);
|
||||
uint16_t adc_preempt_conversion_data_get(adc_type *adc_x, adc_preempt_channel_type adc_preempt_channel);
|
||||
flag_status adc_flag_get(adc_type *adc_x, uint8_t adc_flag);
|
||||
flag_status adc_interrupt_flag_get(adc_type *adc_x, uint8_t adc_flag);
|
||||
void adc_flag_clear(adc_type *adc_x, uint32_t adc_flag);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,789 @@
|
|||
/**
|
||||
**************************************************************************
|
||||
* @file at32f403a_407_bpr.h
|
||||
* @brief at32f403a_407 bpr header file
|
||||
**************************************************************************
|
||||
*
|
||||
* Copyright (c) 2025, Artery Technology, All rights reserved.
|
||||
*
|
||||
* The software Board Support Package (BSP) that is made available to
|
||||
* download from Artery official website is the copyrighted work of Artery.
|
||||
* Artery authorizes customers to use, copy, and distribute the BSP
|
||||
* software and its related documentation for the purpose of design and
|
||||
* development in conjunction with Artery microcontrollers. Use of the
|
||||
* software is governed by this copyright notice and the following disclaimer.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
|
||||
* GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
|
||||
* TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
|
||||
* STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
|
||||
* INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
|
||||
*
|
||||
**************************************************************************
|
||||
*/
|
||||
|
||||
/* define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __AT32F403A_407_BPR_H
|
||||
#define __AT32F403A_407_BPR_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "at32f403a_407.h"
|
||||
|
||||
/** @addtogroup AT32F403A_407_periph_driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup BPR
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup BPR_flags_definition
|
||||
* @brief bpr flag
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define BPR_TAMPER_INTERRUPT_FLAG ((uint32_t)0x00000001) /*!< bpr tamper interrupt flag */
|
||||
#define BPR_TAMPER_EVENT_FLAG ((uint32_t)0x00000002) /*!< bpr tamper event flag */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup BPR_exported_types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief battery powered register data type
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
BPR_DATA1 = 0x04, /*!< bpr data register 1 */
|
||||
BPR_DATA2 = 0x08, /*!< bpr data register 2 */
|
||||
BPR_DATA3 = 0x0C, /*!< bpr data register 3 */
|
||||
BPR_DATA4 = 0x10, /*!< bpr data register 4 */
|
||||
BPR_DATA5 = 0x14, /*!< bpr data register 5 */
|
||||
BPR_DATA6 = 0x18, /*!< bpr data register 6 */
|
||||
BPR_DATA7 = 0x1C, /*!< bpr data register 7 */
|
||||
BPR_DATA8 = 0x20, /*!< bpr data register 8 */
|
||||
BPR_DATA9 = 0x24, /*!< bpr data register 9 */
|
||||
BPR_DATA10 = 0x28, /*!< bpr data register 10 */
|
||||
BPR_DATA11 = 0x40, /*!< bpr data register 11 */
|
||||
BPR_DATA12 = 0x44, /*!< bpr data register 12 */
|
||||
BPR_DATA13 = 0x48, /*!< bpr data register 13 */
|
||||
BPR_DATA14 = 0x4C, /*!< bpr data register 14 */
|
||||
BPR_DATA15 = 0x50, /*!< bpr data register 15 */
|
||||
BPR_DATA16 = 0x54, /*!< bpr data register 16 */
|
||||
BPR_DATA17 = 0x58, /*!< bpr data register 17 */
|
||||
BPR_DATA18 = 0x5C, /*!< bpr data register 18 */
|
||||
BPR_DATA19 = 0x60, /*!< bpr data register 19 */
|
||||
BPR_DATA20 = 0x64, /*!< bpr data register 20 */
|
||||
BPR_DATA21 = 0x68, /*!< bpr data register 21 */
|
||||
BPR_DATA22 = 0x6C, /*!< bpr data register 22 */
|
||||
BPR_DATA23 = 0x70, /*!< bpr data register 23 */
|
||||
BPR_DATA24 = 0x74, /*!< bpr data register 24 */
|
||||
BPR_DATA25 = 0x78, /*!< bpr data register 25 */
|
||||
BPR_DATA26 = 0x7C, /*!< bpr data register 26 */
|
||||
BPR_DATA27 = 0x80, /*!< bpr data register 27 */
|
||||
BPR_DATA28 = 0x84, /*!< bpr data register 28 */
|
||||
BPR_DATA29 = 0x88, /*!< bpr data register 29 */
|
||||
BPR_DATA30 = 0x8C, /*!< bpr data register 30 */
|
||||
BPR_DATA31 = 0x90, /*!< bpr data register 31 */
|
||||
BPR_DATA32 = 0x94, /*!< bpr data register 32 */
|
||||
BPR_DATA33 = 0x98, /*!< bpr data register 33 */
|
||||
BPR_DATA34 = 0x9C, /*!< bpr data register 34 */
|
||||
BPR_DATA35 = 0xA0, /*!< bpr data register 35 */
|
||||
BPR_DATA36 = 0xA4, /*!< bpr data register 36 */
|
||||
BPR_DATA37 = 0xA8, /*!< bpr data register 37 */
|
||||
BPR_DATA38 = 0xAC, /*!< bpr data register 38 */
|
||||
BPR_DATA39 = 0xB0, /*!< bpr data register 39 */
|
||||
BPR_DATA40 = 0xB4, /*!< bpr data register 40 */
|
||||
BPR_DATA41 = 0xB8, /*!< bpr data register 41 */
|
||||
BPR_DATA42 = 0xBC /*!< bpr data register 42 */
|
||||
} bpr_data_type;
|
||||
|
||||
/**
|
||||
* @brief bpr rtc output type
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
BPR_RTC_OUTPUT_NONE = 0x000, /*!< output disable */
|
||||
BPR_RTC_OUTPUT_CLOCK_CAL_BEFORE = 0x080, /*!< output clock before calibration */
|
||||
BPR_RTC_OUTPUT_ALARM = 0x100, /*!< output alarm event with pluse mode */
|
||||
BPR_RTC_OUTPUT_SECOND = 0x300, /*!< output second event with pluse mode */
|
||||
BPR_RTC_OUTPUT_CLOCK_CAL_AFTER = 0x480, /*!< output clock after calibration */
|
||||
BPR_RTC_OUTPUT_ALARM_TOGGLE = 0x900, /*!< output alarm event with toggle mode */
|
||||
BPR_RTC_OUTPUT_SECOND_TOGGLE = 0xB00 /*!< output second event with toggle mode */
|
||||
} bpr_rtc_output_type;
|
||||
|
||||
/**
|
||||
* @brief tamper pin active level type
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
BPR_TAMPER_PIN_ACTIVE_HIGH = 0x00, /*!< tamper pin input active level is high */
|
||||
BPR_TAMPER_PIN_ACTIVE_LOW = 0x01 /*!< tamper pin input active level is low */
|
||||
} bpr_tamper_pin_active_level_type;
|
||||
|
||||
/**
|
||||
* @brief type define bpr register all
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
/**
|
||||
* @brief reserved, offset:0x00
|
||||
*/
|
||||
__IO uint32_t reserved1;
|
||||
|
||||
/**
|
||||
* @brief bpr dt1 register, offset:0x04
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t dt1;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t dt : 16;/* [15:0] */
|
||||
__IO uint32_t reserved1 : 16;/* [31:15] */
|
||||
} dt1_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief bpr dt2 register, offset:0x08
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t dt2;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t dt : 16;/* [15:0] */
|
||||
__IO uint32_t reserved1 : 16;/* [31:15] */
|
||||
} dt2_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief bpr dt3 register, offset:0x0C
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t dt3;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t dt : 16;/* [15:0] */
|
||||
__IO uint32_t reserved1 : 16;/* [31:15] */
|
||||
} dt3_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief bpr dt4 register, offset:0x10
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t dt4;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t dt : 16;/* [15:0] */
|
||||
__IO uint32_t reserved1 : 16;/* [31:15] */
|
||||
} dt4_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief bpr dt5 register, offset:0x14
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t dt5;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t dt : 16;/* [15:0] */
|
||||
__IO uint32_t reserved1 : 16;/* [31:15] */
|
||||
} dt5_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief bpr dt6 register, offset:0x18
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t dt6;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t dt : 16;/* [15:0] */
|
||||
__IO uint32_t reserved1 : 16;/* [31:15] */
|
||||
} dt6_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief bpr dt7 register, offset:0x1C
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t dt7;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t dt : 16;/* [15:0] */
|
||||
__IO uint32_t reserved1 : 16;/* [31:15] */
|
||||
} dt7_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief bpr dt8 register, offset:0x20
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t dt8;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t dt : 16;/* [15:0] */
|
||||
__IO uint32_t reserved1 : 16;/* [31:15] */
|
||||
} dt8_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief bpr dt9 register, offset:0x24
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t dt9;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t dt : 16;/* [15:0] */
|
||||
__IO uint32_t reserved1 : 16;/* [31:15] */
|
||||
} dt9_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief bpr dt10 register, offset:0x28
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t dt10;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t dt : 16;/* [15:0] */
|
||||
__IO uint32_t reserved1 : 16;/* [31:15] */
|
||||
} dt10_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief bpr rtccal register, offset:0x2C
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t rtccal;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t calval : 7; /* [6:0] */
|
||||
__IO uint32_t calout : 1; /* [7] */
|
||||
__IO uint32_t outen : 1; /* [8] */
|
||||
__IO uint32_t outsel : 1; /* [9] */
|
||||
__IO uint32_t ccos : 1; /* [10] */
|
||||
__IO uint32_t outm : 1; /* [11] */
|
||||
__IO uint32_t reserved1 : 20;/* [31:12] */
|
||||
} rtccal_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief bpr ctrl register, offset:0x30
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t ctrl;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t tpen : 1; /* [0] */
|
||||
__IO uint32_t tpp : 1; /* [1] */
|
||||
__IO uint32_t reserved1 : 30;/* [31:2] */
|
||||
} ctrl_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief bpr ctrlsts register, offset:0x34
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t ctrlsts;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t tpefclr : 1;/* [0] */
|
||||
__IO uint32_t tpifclr : 1;/* [1] */
|
||||
__IO uint32_t tpien : 1;/* [2] */
|
||||
__IO uint32_t reserved1 : 5;/* [7:3] */
|
||||
__IO uint32_t tpef : 1;/* [8] */
|
||||
__IO uint32_t tpif : 1;/* [9] */
|
||||
__IO uint32_t reserved2 : 22;/* [31:10] */
|
||||
} ctrlsts_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief reserved, offset:0x38
|
||||
*/
|
||||
__IO uint32_t reserved2;
|
||||
|
||||
/**
|
||||
* @brief reserved, offset:0x3C
|
||||
*/
|
||||
__IO uint32_t reserved3;
|
||||
|
||||
/**
|
||||
* @brief bpr dt11 register, offset:0x40
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t dt11;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t dt : 16;/* [15:0] */
|
||||
__IO uint32_t reserved1 : 16;/* [31:15] */
|
||||
} dt11_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief bpr dt12 register, offset:0x44
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t dt12;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t dt : 16;/* [15:0] */
|
||||
__IO uint32_t reserved1 : 16;/* [31:15] */
|
||||
} dt12_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief bpr dt13 register, offset:0x48
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t dt13;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t dt : 16;/* [15:0] */
|
||||
__IO uint32_t reserved1 : 16;/* [31:15] */
|
||||
} dt13_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief bpr dt14 register, offset:0x4C
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t dt14;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t dt : 16;/* [15:0] */
|
||||
__IO uint32_t reserved1 : 16;/* [31:15] */
|
||||
} dt14_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief bpr dt15 register, offset:0x50
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t dt15;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t dt : 16;/* [15:0] */
|
||||
__IO uint32_t reserved1 : 16;/* [31:15] */
|
||||
} dt15_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief bpr dt16 register, offset:0x54
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t dt16;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t dt : 16;/* [15:0] */
|
||||
__IO uint32_t reserved1 : 16;/* [31:15] */
|
||||
} dt16_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief bpr dt17 register, offset:0x58
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t dt17;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t dt : 16;/* [15:0] */
|
||||
__IO uint32_t reserved1 : 16;/* [31:15] */
|
||||
} dt17_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief bpr dt18 register, offset:0x5C
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t dt18;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t dt : 16;/* [15:0] */
|
||||
__IO uint32_t reserved1 : 16;/* [31:15] */
|
||||
} dt18_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief bpr dt19 register, offset:0x60
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t dt19;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t dt : 16;/* [15:0] */
|
||||
__IO uint32_t reserved1 : 16;/* [31:15] */
|
||||
} dt19_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief bpr dt20 register, offset:0x64
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t dt20;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t dt : 16;/* [15:0] */
|
||||
__IO uint32_t reserved1 : 16;/* [31:15] */
|
||||
} dt20_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief bpr dt21 register, offset:0x68
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t dt21;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t dt : 16;/* [15:0] */
|
||||
__IO uint32_t reserved1 : 16;/* [31:15] */
|
||||
} dt21_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief bpr dt22 register, offset:6C
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t dt22;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t dt : 16;/* [15:0] */
|
||||
__IO uint32_t reserved1 : 16;/* [31:15] */
|
||||
} dt22_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief bpr dt23 register, offset:0x70
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t dt23;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t dt : 16;/* [15:0] */
|
||||
__IO uint32_t reserved1 : 16;/* [31:15] */
|
||||
} dt23_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief bpr dt24 register, offset:0x74
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t dt24;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t dt : 16;/* [15:0] */
|
||||
__IO uint32_t reserved1 : 16;/* [31:15] */
|
||||
} dt24_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief bpr dt25 register, offset:0x78
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t dt25;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t dt : 16;/* [15:0] */
|
||||
__IO uint32_t reserved1 : 16;/* [31:15] */
|
||||
} dt25_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief bpr dt26 register, offset:0x7C
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t dt26;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t dt : 16;/* [15:0] */
|
||||
__IO uint32_t reserved1 : 16;/* [31:15] */
|
||||
} dt26_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief bpr dt27 register, offset:0x80
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t dt27;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t dt : 16;/* [15:0] */
|
||||
__IO uint32_t reserved1 : 16;/* [31:15] */
|
||||
} dt27_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief bpr dt28 register, offset:0x84
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t dt28;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t dt : 16;/* [15:0] */
|
||||
__IO uint32_t reserved1 : 16;/* [31:15] */
|
||||
} dt28_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief bpr dt29 register, offset:0x88
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t dt29;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t dt : 16;/* [15:0] */
|
||||
__IO uint32_t reserved1 : 16;/* [31:15] */
|
||||
} dt29_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief bpr dt30 register, offset:0x8C
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t dt30;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t dt : 16;/* [15:0] */
|
||||
__IO uint32_t reserved1 : 16;/* [31:15] */
|
||||
} dt30_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief bpr dt31 register, offset:0x90
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t dt31;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t dt : 16;/* [15:0] */
|
||||
__IO uint32_t reserved1 : 16;/* [31:15] */
|
||||
} dt31_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief bpr dt32 register, offset:0x94
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t dt32;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t dt : 16;/* [15:0] */
|
||||
__IO uint32_t reserved1 : 16;/* [31:15] */
|
||||
} dt32_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief bpr dt33 register, offset:0x98
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t dt33;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t dt : 16;/* [15:0] */
|
||||
__IO uint32_t reserved1 : 16;/* [31:15] */
|
||||
} dt33_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief bpr dt34 register, offset:0x9C
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t dt34;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t dt : 16;/* [15:0] */
|
||||
__IO uint32_t reserved1 : 16;/* [31:15] */
|
||||
} dt34_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief bpr dt35 register, offset:0xA0
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t dt35;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t dt : 16;/* [15:0] */
|
||||
__IO uint32_t reserved1 : 16;/* [31:15] */
|
||||
} dt35_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief bpr dt36 register, offset:0xA4
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t dt36;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t dt : 16;/* [15:0] */
|
||||
__IO uint32_t reserved1 : 16;/* [31:15] */
|
||||
} dt36_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief bpr dt37 register, offset:0xA8
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t dt37;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t dt : 16;/* [15:0] */
|
||||
__IO uint32_t reserved1 : 16;/* [31:15] */
|
||||
} dt37_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief bpr dt38 register, offset:0xAC
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t dt38;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t dt : 16;/* [15:0] */
|
||||
__IO uint32_t reserved1 : 16;/* [31:15] */
|
||||
} dt38_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief bpr dt39 register, offset:0xB0
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t dt39;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t dt : 16;/* [15:0] */
|
||||
__IO uint32_t reserved1 : 16;/* [31:15] */
|
||||
} dt39_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief bpr dt40 register, offset:0xB4
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t dt40;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t dt : 16;/* [15:0] */
|
||||
__IO uint32_t reserved1 : 16;/* [31:15] */
|
||||
} dt40_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief bpr dt41 register, offset:0xB8
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t dt41;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t dt : 16;/* [15:0] */
|
||||
__IO uint32_t reserved1 : 16;/* [31:15] */
|
||||
} dt41_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief bpr dt42 register, offset:0xBC
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t dt42;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t dt : 16;/* [15:0] */
|
||||
__IO uint32_t reserved1 : 16;/* [31:15] */
|
||||
} dt42_bit;
|
||||
};
|
||||
} bpr_type;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#define BPR ((bpr_type *) BPR_BASE)
|
||||
|
||||
/** @defgroup BPR_exported_functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
void bpr_reset(void);
|
||||
flag_status bpr_flag_get(uint32_t flag);
|
||||
flag_status bpr_interrupt_flag_get(uint32_t flag);
|
||||
void bpr_flag_clear(uint32_t flag);
|
||||
void bpr_interrupt_enable(confirm_state new_state);
|
||||
uint16_t bpr_data_read(bpr_data_type bpr_data);
|
||||
void bpr_data_write(bpr_data_type bpr_data, uint16_t data_value);
|
||||
void bpr_rtc_output_select(bpr_rtc_output_type output_source);
|
||||
void bpr_rtc_clock_calibration_value_set(uint8_t calibration_value);
|
||||
void bpr_tamper_pin_enable(confirm_state new_state);
|
||||
void bpr_tamper_pin_active_level_set(bpr_tamper_pin_active_level_type active_level);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,986 @@
|
|||
/**
|
||||
**************************************************************************
|
||||
* @file at32f403a_407_can.h
|
||||
* @brief at32f403a_407 can header file
|
||||
**************************************************************************
|
||||
*
|
||||
* Copyright (c) 2025, Artery Technology, All rights reserved.
|
||||
*
|
||||
* The software Board Support Package (BSP) that is made available to
|
||||
* download from Artery official website is the copyrighted work of Artery.
|
||||
* Artery authorizes customers to use, copy, and distribute the BSP
|
||||
* software and its related documentation for the purpose of design and
|
||||
* development in conjunction with Artery microcontrollers. Use of the
|
||||
* software is governed by this copyright notice and the following disclaimer.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
|
||||
* GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
|
||||
* TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
|
||||
* STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
|
||||
* INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
|
||||
*
|
||||
**************************************************************************
|
||||
*/
|
||||
|
||||
/* define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __AT32F403A_407_CAN_H
|
||||
#define __AT32F403A_407_CAN_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
|
||||
/* includes ------------------------------------------------------------------*/
|
||||
#include "at32f403a_407.h"
|
||||
|
||||
/** @addtogroup AT32F403A_407_periph_driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup CAN
|
||||
* @{
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup CAN_timeout_count
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define FZC_TIMEOUT ((uint32_t)0x0000FFFF) /*!< time out for fzc bit */
|
||||
#define DZC_TIMEOUT ((uint32_t)0x0000FFFF) /*!< time out for dzc bit */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CAN_flags_definition
|
||||
* @brief can flag
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define CAN_EAF_FLAG ((uint32_t)0x01) /*!< error active flag */
|
||||
#define CAN_EPF_FLAG ((uint32_t)0x02) /*!< error passive flag */
|
||||
#define CAN_BOF_FLAG ((uint32_t)0x03) /*!< bus-off flag */
|
||||
#define CAN_ETR_FLAG ((uint32_t)0x04) /*!< error type record flag */
|
||||
#define CAN_EOIF_FLAG ((uint32_t)0x05) /*!< error occur interrupt flag */
|
||||
#define CAN_TM0TCF_FLAG ((uint32_t)0x06) /*!< transmit mailbox 0 transmission completed flag */
|
||||
#define CAN_TM1TCF_FLAG ((uint32_t)0x07) /*!< transmit mailbox 1 transmission completed flag */
|
||||
#define CAN_TM2TCF_FLAG ((uint32_t)0x08) /*!< transmit mailbox 2 transmission completed flag */
|
||||
#define CAN_RF0MN_FLAG ((uint32_t)0x09) /*!< receive fifo 0 message num flag */
|
||||
#define CAN_RF0FF_FLAG ((uint32_t)0x0A) /*!< receive fifo 0 full flag */
|
||||
#define CAN_RF0OF_FLAG ((uint32_t)0x0B) /*!< receive fifo 0 overflow flag */
|
||||
#define CAN_RF1MN_FLAG ((uint32_t)0x0C) /*!< receive fifo 1 message num flag */
|
||||
#define CAN_RF1FF_FLAG ((uint32_t)0x0D) /*!< receive fifo 1 full flag */
|
||||
#define CAN_RF1OF_FLAG ((uint32_t)0x0E) /*!< receive fifo 1 overflow flag */
|
||||
#define CAN_QDZIF_FLAG ((uint32_t)0x0F) /*!< quit doze mode interrupt flag */
|
||||
#define CAN_EDZC_FLAG ((uint32_t)0x10) /*!< enter doze mode confirm flag */
|
||||
#define CAN_TMEF_FLAG ((uint32_t)0x11) /*!< transmit mailbox empty flag */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CAN_interrupts_definition
|
||||
* @brief can interrupt
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define CAN_TCIEN_INT ((uint32_t)0x00000001) /*!< transmission complete interrupt */
|
||||
#define CAN_RF0MIEN_INT ((uint32_t)0x00000002) /*!< receive fifo 0 message interrupt */
|
||||
#define CAN_RF0FIEN_INT ((uint32_t)0x00000004) /*!< receive fifo 0 full interrupt */
|
||||
#define CAN_RF0OIEN_INT ((uint32_t)0x00000008) /*!< receive fifo 0 overflow interrupt */
|
||||
#define CAN_RF1MIEN_INT ((uint32_t)0x00000010) /*!< receive fifo 1 message interrupt */
|
||||
#define CAN_RF1FIEN_INT ((uint32_t)0x00000020) /*!< receive fifo 1 full interrupt */
|
||||
#define CAN_RF1OIEN_INT ((uint32_t)0x00000040) /*!< receive fifo 1 overflow interrupt */
|
||||
#define CAN_EAIEN_INT ((uint32_t)0x00000100) /*!< error active interrupt */
|
||||
#define CAN_EPIEN_INT ((uint32_t)0x00000200) /*!< error passive interrupt */
|
||||
#define CAN_BOIEN_INT ((uint32_t)0x00000400) /*!< bus-off interrupt */
|
||||
#define CAN_ETRIEN_INT ((uint32_t)0x00000800) /*!< error type record interrupt */
|
||||
#define CAN_EOIEN_INT ((uint32_t)0x00008000) /*!< error occur interrupt */
|
||||
#define CAN_QDZIEN_INT ((uint32_t)0x00010000) /*!< quit doze mode interrupt */
|
||||
#define CAN_EDZIEN_INT ((uint32_t)0x00020000) /*!< enter doze mode confirm interrupt */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief can flag clear operation macro definition val
|
||||
*/
|
||||
#define CAN_MSTS_EOIF_VAL ((uint32_t)0x00000004) /*!< eoif bit value, it clear by writing 1 */
|
||||
#define CAN_MSTS_QDZIF_VAL ((uint32_t)0x00000008) /*!< qdzif bit value, it clear by writing 1 */
|
||||
#define CAN_MSTS_EDZIF_VAL ((uint32_t)0x00000010) /*!< edzif bit value, it clear by writing 1 */
|
||||
#define CAN_TSTS_TM0TCF_VAL ((uint32_t)0x00000001) /*!< tm0tcf bit value, it clear by writing 1 */
|
||||
#define CAN_TSTS_TM1TCF_VAL ((uint32_t)0x00000100) /*!< tm1tcf bit value, it clear by writing 1 */
|
||||
#define CAN_TSTS_TM2TCF_VAL ((uint32_t)0x00010000) /*!< tm2tcf bit value, it clear by writing 1 */
|
||||
#define CAN_TSTS_TM0CT_VAL ((uint32_t)0x00000080) /*!< tm0ct bit value, it clear by writing 1 */
|
||||
#define CAN_TSTS_TM1CT_VAL ((uint32_t)0x00008000) /*!< tm1ct bit value, it clear by writing 1 */
|
||||
#define CAN_TSTS_TM2CT_VAL ((uint32_t)0x00800000) /*!< tm2ct bit value, it clear by writing 1 */
|
||||
#define CAN_RF0_RF0FF_VAL ((uint32_t)0x00000008) /*!< rf0ff bit value, it clear by writing 1 */
|
||||
#define CAN_RF0_RF0OF_VAL ((uint32_t)0x00000010) /*!< rf0of bit value, it clear by writing 1 */
|
||||
#define CAN_RF0_RF0R_VAL ((uint32_t)0x00000020) /*!< rf0r bit value, it clear by writing 1 */
|
||||
#define CAN_RF1_RF1FF_VAL ((uint32_t)0x00000008) /*!< rf1ff bit value, it clear by writing 1 */
|
||||
#define CAN_RF1_RF1OF_VAL ((uint32_t)0x00000010) /*!< rf1of bit value, it clear by writing 1 */
|
||||
#define CAN_RF1_RF1R_VAL ((uint32_t)0x00000020) /*!< rf1r bit value, it clear by writing 1 */
|
||||
|
||||
/** @defgroup CAN_exported_types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief can filter fifo
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
CAN_FILTER_FIFO0 = 0x00, /*!< filter fifo 0 assignment for filter x */
|
||||
CAN_FILTER_FIFO1 = 0x01 /*!< filter fifo 1 assignment for filter x */
|
||||
} can_filter_fifo_type;
|
||||
|
||||
/**
|
||||
* @brief can filter mode
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
CAN_FILTER_MODE_ID_MASK = 0x00, /*!< identifier mask mode */
|
||||
CAN_FILTER_MODE_ID_LIST = 0x01 /*!< identifier list mode */
|
||||
} can_filter_mode_type;
|
||||
|
||||
/**
|
||||
* @brief can filter bit width select
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
CAN_FILTER_16BIT = 0x00, /*!< two 16-bit filters */
|
||||
CAN_FILTER_32BIT = 0x01 /*!< one 32-bit filter */
|
||||
} can_filter_bit_width_type;
|
||||
|
||||
/**
|
||||
* @brief can mode
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
CAN_MODE_COMMUNICATE = 0x00, /*!< communication mode */
|
||||
CAN_MODE_LOOPBACK = 0x01, /*!< loopback mode */
|
||||
CAN_MODE_LISTENONLY = 0x02, /*!< listen-only mode */
|
||||
CAN_MODE_LISTENONLY_LOOPBACK = 0x03 /*!< loopback combined with listen-only mode */
|
||||
} can_mode_type;
|
||||
|
||||
/**
|
||||
* @brief can operating mode
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
CAN_OPERATINGMODE_FREEZE = 0x00, /*!< freeze mode */
|
||||
CAN_OPERATINGMODE_DOZE = 0x01, /*!< doze mode */
|
||||
CAN_OPERATINGMODE_COMMUNICATE = 0x02 /*!< communication mode */
|
||||
} can_operating_mode_type;
|
||||
|
||||
/**
|
||||
* @brief can resynchronization adjust width
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
CAN_RSAW_1TQ = 0x00, /*!< 1 time quantum */
|
||||
CAN_RSAW_2TQ = 0x01, /*!< 2 time quantum */
|
||||
CAN_RSAW_3TQ = 0x02, /*!< 3 time quantum */
|
||||
CAN_RSAW_4TQ = 0x03 /*!< 4 time quantum */
|
||||
} can_rsaw_type;
|
||||
|
||||
/**
|
||||
* @brief can bit time segment 1
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
CAN_BTS1_1TQ = 0x00, /*!< 1 time quantum */
|
||||
CAN_BTS1_2TQ = 0x01, /*!< 2 time quantum */
|
||||
CAN_BTS1_3TQ = 0x02, /*!< 3 time quantum */
|
||||
CAN_BTS1_4TQ = 0x03, /*!< 4 time quantum */
|
||||
CAN_BTS1_5TQ = 0x04, /*!< 5 time quantum */
|
||||
CAN_BTS1_6TQ = 0x05, /*!< 6 time quantum */
|
||||
CAN_BTS1_7TQ = 0x06, /*!< 7 time quantum */
|
||||
CAN_BTS1_8TQ = 0x07, /*!< 8 time quantum */
|
||||
CAN_BTS1_9TQ = 0x08, /*!< 9 time quantum */
|
||||
CAN_BTS1_10TQ = 0x09, /*!< 10 time quantum */
|
||||
CAN_BTS1_11TQ = 0x0A, /*!< 11 time quantum */
|
||||
CAN_BTS1_12TQ = 0x0B, /*!< 12 time quantum */
|
||||
CAN_BTS1_13TQ = 0x0C, /*!< 13 time quantum */
|
||||
CAN_BTS1_14TQ = 0x0D, /*!< 14 time quantum */
|
||||
CAN_BTS1_15TQ = 0x0E, /*!< 15 time quantum */
|
||||
CAN_BTS1_16TQ = 0x0F /*!< 16 time quantum */
|
||||
} can_bts1_type;
|
||||
|
||||
/**
|
||||
* @brief can bit time segment 2
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
CAN_BTS2_1TQ = 0x00, /*!< 1 time quantum */
|
||||
CAN_BTS2_2TQ = 0x01, /*!< 2 time quantum */
|
||||
CAN_BTS2_3TQ = 0x02, /*!< 3 time quantum */
|
||||
CAN_BTS2_4TQ = 0x03, /*!< 4 time quantum */
|
||||
CAN_BTS2_5TQ = 0x04, /*!< 5 time quantum */
|
||||
CAN_BTS2_6TQ = 0x05, /*!< 6 time quantum */
|
||||
CAN_BTS2_7TQ = 0x06, /*!< 7 time quantum */
|
||||
CAN_BTS2_8TQ = 0x07 /*!< 8 time quantum */
|
||||
} can_bts2_type;
|
||||
|
||||
/**
|
||||
* @brief can identifier type
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
CAN_ID_STANDARD = 0x00, /*!< standard Id */
|
||||
CAN_ID_EXTENDED = 0x01 /*!< extended Id */
|
||||
} can_identifier_type;
|
||||
|
||||
/**
|
||||
* @brief can transmission frame type
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
CAN_TFT_DATA = 0x00, /*!< data frame */
|
||||
CAN_TFT_REMOTE = 0x01 /*!< remote frame */
|
||||
} can_trans_frame_type;
|
||||
|
||||
/**
|
||||
* @brief can tx mailboxes
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
CAN_TX_MAILBOX0 = 0x00, /*!< can tx mailbox 0 */
|
||||
CAN_TX_MAILBOX1 = 0x01, /*!< can tx mailbox 1 */
|
||||
CAN_TX_MAILBOX2 = 0x02 /*!< can tx mailbox 2 */
|
||||
} can_tx_mailbox_num_type;
|
||||
|
||||
/**
|
||||
* @brief can receive fifo
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
CAN_RX_FIFO0 = 0x00, /*!< can fifo 0 used to receive */
|
||||
CAN_RX_FIFO1 = 0x01 /*!< can fifo 1 used to receive */
|
||||
} can_rx_fifo_num_type;
|
||||
|
||||
/**
|
||||
* @brief can transmit status
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
CAN_TX_STATUS_FAILED = 0x00, /*!< can transmission failed */
|
||||
CAN_TX_STATUS_SUCCESSFUL = 0x01, /*!< can transmission successful */
|
||||
CAN_TX_STATUS_PENDING = 0x02, /*!< can transmission pending */
|
||||
CAN_TX_STATUS_NO_EMPTY = 0x04 /*!< can transmission no empty mailbox */
|
||||
} can_transmit_status_type;
|
||||
|
||||
/**
|
||||
* @brief can enter doze mode status
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
CAN_ENTER_DOZE_FAILED = 0x00, /*!< can enter the doze mode failed */
|
||||
CAN_ENTER_DOZE_SUCCESSFUL = 0x01 /*!< can enter the doze mode successful */
|
||||
} can_enter_doze_status_type;
|
||||
|
||||
/**
|
||||
* @brief can quit doze mode status
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
CAN_QUIT_DOZE_FAILED = 0x00, /*!< can quit doze mode failed */
|
||||
CAN_QUIT_DOZE_SUCCESSFUL = 0x01 /*!< can quit doze mode successful */
|
||||
} can_quit_doze_status_type;
|
||||
|
||||
/**
|
||||
* @brief can message discarding rule select when overflow
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
CAN_DISCARDING_FIRST_RECEIVED = 0x00, /*!< can discarding the first received message */
|
||||
CAN_DISCARDING_LAST_RECEIVED = 0x01 /*!< can discarding the last received message */
|
||||
} can_msg_discarding_rule_type;
|
||||
|
||||
/**
|
||||
* @brief can multiple message sending sequence rule
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
CAN_SENDING_BY_ID = 0x00, /*!< can sending the minimum id message first*/
|
||||
CAN_SENDING_BY_REQUEST = 0x01 /*!< can sending the first request message first */
|
||||
} can_msg_sending_rule_type;
|
||||
|
||||
/**
|
||||
* @brief can error type record
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
CAN_ERRORRECORD_NOERR = 0x00, /*!< no error */
|
||||
CAN_ERRORRECORD_STUFFERR = 0x01, /*!< stuff error */
|
||||
CAN_ERRORRECORD_FORMERR = 0x02, /*!< form error */
|
||||
CAN_ERRORRECORD_ACKERR = 0x03, /*!< acknowledgment error */
|
||||
CAN_ERRORRECORD_BITRECESSIVEERR = 0x04, /*!< bit recessive error */
|
||||
CAN_ERRORRECORD_BITDOMINANTERR = 0x05, /*!< bit dominant error */
|
||||
CAN_ERRORRECORD_CRCERR = 0x06, /*!< crc error */
|
||||
CAN_ERRORRECORD_SOFTWARESETERR = 0x07 /*!< software set error */
|
||||
} can_error_record_type;
|
||||
|
||||
/**
|
||||
* @brief can init structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
can_mode_type mode_selection; /*!< specifies the can mode.*/
|
||||
|
||||
confirm_state ttc_enable; /*!< time triggered communication mode enable */
|
||||
|
||||
confirm_state aebo_enable; /*!< automatic exit bus-off enable */
|
||||
|
||||
confirm_state aed_enable; /*!< automatic exit doze mode enable */
|
||||
|
||||
confirm_state prsf_enable; /*!< prohibit retransmission when sending fails enable */
|
||||
|
||||
can_msg_discarding_rule_type mdrsel_selection; /*!< message discarding rule select when overflow */
|
||||
|
||||
can_msg_sending_rule_type mmssr_selection; /*!< multiple message sending sequence rule */
|
||||
|
||||
} can_base_type;
|
||||
|
||||
/**
|
||||
* @brief can baudrate structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint16_t baudrate_div; /*!< baudrate division,this parameter can be 0x001~0x1000.*/
|
||||
|
||||
can_rsaw_type rsaw_size; /*!< resynchronization adjust width */
|
||||
|
||||
can_bts1_type bts1_size; /*!< bit time segment 1 */
|
||||
|
||||
can_bts2_type bts2_size; /*!< bit time segment 2 */
|
||||
|
||||
} can_baudrate_type;
|
||||
|
||||
/**
|
||||
* @brief can filter init structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
confirm_state filter_activate_enable; /*!< enable or disable the filter activate.*/
|
||||
|
||||
can_filter_mode_type filter_mode; /*!< config the filter mode mask or list.*/
|
||||
|
||||
can_filter_fifo_type filter_fifo; /*!< config the fifo which will be assigned to the filter. */
|
||||
|
||||
uint8_t filter_number; /*!< config the filter number, parameter ranges from 0 to 13. */
|
||||
|
||||
can_filter_bit_width_type filter_bit; /*!< config the filter bit width 16bit or 32bit.*/
|
||||
|
||||
uint16_t filter_id_high; /*!< config the filter identification, for 32-bit configuration
|
||||
it's high 16 bits, for 16-bit configuration it's first. */
|
||||
|
||||
uint16_t filter_id_low; /*!< config the filter identification, for 32-bit configuration
|
||||
it's low 16 bits, for 16-bit configuration it's second. */
|
||||
|
||||
uint16_t filter_mask_high; /*!< config the filter mask or identification, according to the filtering mode,
|
||||
for 32-bit configuration it's high 16 bits, for 16-bit configuration it's first. */
|
||||
|
||||
uint16_t filter_mask_low; /*!< config the filter mask or identification, according to the filtering mode,
|
||||
for 32-bit configuration it's low 16 bits, for 16-bit configuration it's second. */
|
||||
} can_filter_init_type;
|
||||
|
||||
/**
|
||||
* @brief can tx message structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t standard_id; /*!< specifies the 11 bits standard identifier.
|
||||
this parameter can be a value between 0 to 0x7FF. */
|
||||
|
||||
uint32_t extended_id; /*!< specifies the 29 bits extended identifier.
|
||||
this parameter can be a value between 0 to 0x1FFFFFFF. */
|
||||
|
||||
can_identifier_type id_type; /*!< specifies identifier type for the transmit message.*/
|
||||
|
||||
can_trans_frame_type frame_type; /*!< specifies frame type for the transmit message.*/
|
||||
|
||||
uint8_t dlc; /*!< specifies frame data length that will be transmitted.
|
||||
this parameter can be a value between 0 to 8 */
|
||||
|
||||
uint8_t data[8]; /*!< contains the transmit data. it ranges from 0 to 0xFF. */
|
||||
|
||||
} can_tx_message_type;
|
||||
|
||||
/**
|
||||
* @brief can rx message structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t standard_id; /*!< specifies the 11 bits standard identifier
|
||||
this parameter can be a value between 0 to 0x7FF. */
|
||||
|
||||
uint32_t extended_id; /*!< specifies the 29 bits extended identifier.
|
||||
this parameter can be a value between 0 to 0x1FFFFFFF. */
|
||||
|
||||
can_identifier_type id_type; /*!< specifies identifier type for the receive message.*/
|
||||
|
||||
can_trans_frame_type frame_type; /*!< specifies frame type for the receive message.*/
|
||||
|
||||
uint8_t dlc; /*!< specifies the frame data length that will be received.
|
||||
this parameter can be a value between 0 to 8 */
|
||||
|
||||
uint8_t data[8]; /*!< contains the receive data. it ranges from 0 to 0xFF.*/
|
||||
|
||||
uint8_t filter_index; /*!< specifies the message stored in which filter
|
||||
this parameter can be a value between 0 to 0xFF */
|
||||
} can_rx_message_type;
|
||||
|
||||
/**
|
||||
* @brief can controller area network tx mailbox
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
/**
|
||||
* @brief can tmi register
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t tmi;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t tmsr : 1; /* [0] */
|
||||
__IO uint32_t tmfrsel : 1; /* [1] */
|
||||
__IO uint32_t tmidsel : 1; /* [2] */
|
||||
__IO uint32_t tmeid : 18;/* [20:3] */
|
||||
__IO uint32_t tmsid : 11;/* [31:21] */
|
||||
} tmi_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief can tmc register
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t tmc;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t tmdtbl : 4; /* [3:0] */
|
||||
__IO uint32_t reserved1 : 4; /* [7:4] */
|
||||
__IO uint32_t tmtsten : 1; /* [8] */
|
||||
__IO uint32_t reserved2 : 7; /* [15:9] */
|
||||
__IO uint32_t tmts : 16;/* [31:16] */
|
||||
} tmc_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief can tmdtl register
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t tmdtl;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t tmdt0 : 8; /* [7:0] */
|
||||
__IO uint32_t tmdt1 : 8; /* [15:8] */
|
||||
__IO uint32_t tmdt2 : 8; /* [23:16] */
|
||||
__IO uint32_t tmdt3 : 8; /* [31:24] */
|
||||
} tmdtl_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief can tmdth register
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t tmdth;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t tmdt4 : 8; /* [7:0] */
|
||||
__IO uint32_t tmdt5 : 8; /* [15:8] */
|
||||
__IO uint32_t tmdt6 : 8; /* [23:16] */
|
||||
__IO uint32_t tmdt7 : 8; /* [31:24] */
|
||||
} tmdth_bit;
|
||||
};
|
||||
} can_tx_mailbox_type;
|
||||
|
||||
/**
|
||||
* @brief can controller area network fifo mailbox
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
/**
|
||||
* @brief can rfi register
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t rfi;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t reserved1 : 1; /* [0] */
|
||||
__IO uint32_t rffri : 1; /* [1] */
|
||||
__IO uint32_t rfidi : 1; /* [2] */
|
||||
__IO uint32_t rfeid : 18;/* [20:3] */
|
||||
__IO uint32_t rfsid : 11;/* [31:21] */
|
||||
} rfi_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief can rfc register
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t rfc;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t rfdtl : 4; /* [3:0] */
|
||||
__IO uint32_t reserved1 : 4; /* [7:4] */
|
||||
__IO uint32_t rffmn : 8; /* [15:8] */
|
||||
__IO uint32_t rfts : 16;/* [31:16] */
|
||||
} rfc_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief can rfdtl register
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t rfdtl;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t rfdt0 : 8; /* [7:0] */
|
||||
__IO uint32_t rfdt1 : 8; /* [15:8] */
|
||||
__IO uint32_t rfdt2 : 8; /* [23:16] */
|
||||
__IO uint32_t rfdt3 : 8; /* [31:24] */
|
||||
} rfdtl_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief can rfdth register
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t rfdth;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t rfdt4 : 8; /* [7:0] */
|
||||
__IO uint32_t rfdt5 : 8; /* [15:8] */
|
||||
__IO uint32_t rfdt6 : 8; /* [23:16] */
|
||||
__IO uint32_t rfdt7 : 8; /* [31:24] */
|
||||
} rfdth_bit;
|
||||
};
|
||||
} can_fifo_mailbox_type;
|
||||
|
||||
/**
|
||||
* @brief can controller area network filter bit register
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
__IO uint32_t ffdb1;
|
||||
__IO uint32_t ffdb2;
|
||||
} can_filter_register_type;
|
||||
|
||||
/**
|
||||
* @brief type define can register all
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
|
||||
/**
|
||||
* @brief can mctrl register, offset:0x00
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t mctrl;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t fzen : 1; /* [0] */
|
||||
__IO uint32_t dzen : 1; /* [1] */
|
||||
__IO uint32_t mmssr : 1; /* [2] */
|
||||
__IO uint32_t mdrsel : 1; /* [3] */
|
||||
__IO uint32_t prsfen : 1; /* [4] */
|
||||
__IO uint32_t aeden : 1; /* [5] */
|
||||
__IO uint32_t aeboen : 1; /* [6] */
|
||||
__IO uint32_t ttcen : 1; /* [7] */
|
||||
__IO uint32_t reserved1 : 7; /* [14:8] */
|
||||
__IO uint32_t sprst : 1; /* [15] */
|
||||
__IO uint32_t ptd : 1; /* [16] */
|
||||
__IO uint32_t reserved2 : 15;/*[31:17] */
|
||||
} mctrl_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief can msts register, offset:0x04
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t msts;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t fzc : 1; /* [0] */
|
||||
__IO uint32_t dzc : 1; /* [1] */
|
||||
__IO uint32_t eoif : 1; /* [2] */
|
||||
__IO uint32_t qdzif : 1; /* [3] */
|
||||
__IO uint32_t edzif : 1; /* [4] */
|
||||
__IO uint32_t reserved1 : 3; /* [7:5] */
|
||||
__IO uint32_t cuss : 1; /* [8] */
|
||||
__IO uint32_t curs : 1; /* [9] */
|
||||
__IO uint32_t lsamprx : 1; /* [10] */
|
||||
__IO uint32_t realrx : 1; /* [11] */
|
||||
__IO uint32_t reserved2 : 20;/*[31:12] */
|
||||
} msts_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief can tsts register, offset:0x08
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t tsts;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t tm0tcf : 1; /* [0] */
|
||||
__IO uint32_t tm0tsf : 1; /* [1] */
|
||||
__IO uint32_t tm0alf : 1; /* [2] */
|
||||
__IO uint32_t tm0tef : 1; /* [3] */
|
||||
__IO uint32_t reserved1 : 3; /* [6:4] */
|
||||
__IO uint32_t tm0ct : 1; /* [7] */
|
||||
__IO uint32_t tm1tcf : 1; /* [8] */
|
||||
__IO uint32_t tm1tsf : 1; /* [9] */
|
||||
__IO uint32_t tm1alf : 1; /* [10] */
|
||||
__IO uint32_t tm1tef : 1; /* [11] */
|
||||
__IO uint32_t reserved2 : 3; /* [14:12] */
|
||||
__IO uint32_t tm1ct : 1; /* [15] */
|
||||
__IO uint32_t tm2tcf : 1; /* [16] */
|
||||
__IO uint32_t tm2tsf : 1; /* [17] */
|
||||
__IO uint32_t tm2alf : 1; /* [18] */
|
||||
__IO uint32_t tm2tef : 1; /* [19] */
|
||||
__IO uint32_t reserved3 : 3; /* [22:20] */
|
||||
__IO uint32_t tm2ct : 1; /* [23] */
|
||||
__IO uint32_t tmnr : 2; /* [25:24] */
|
||||
__IO uint32_t tm0ef : 1; /* [26] */
|
||||
__IO uint32_t tm1ef : 1; /* [27] */
|
||||
__IO uint32_t tm2ef : 1; /* [28] */
|
||||
__IO uint32_t tm0lpf : 1; /* [29] */
|
||||
__IO uint32_t tm1lpf : 1; /* [30] */
|
||||
__IO uint32_t tm2lpf : 1; /* [31] */
|
||||
} tsts_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief can rf0 register, offset:0x0C
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t rf0;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t rf0mn : 2; /* [1:0] */
|
||||
__IO uint32_t reserved1 : 1; /* [2] */
|
||||
__IO uint32_t rf0ff : 1; /* [3] */
|
||||
__IO uint32_t rf0of : 1; /* [4] */
|
||||
__IO uint32_t rf0r : 1; /* [5] */
|
||||
__IO uint32_t reserved2 : 26;/* [31:6] */
|
||||
} rf0_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief can rf1 register, offset:0x10
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t rf1;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t rf1mn : 2; /* [1:0] */
|
||||
__IO uint32_t reserved1 : 1; /* [2] */
|
||||
__IO uint32_t rf1ff : 1; /* [3] */
|
||||
__IO uint32_t rf1of : 1; /* [4] */
|
||||
__IO uint32_t rf1r : 1; /* [5] */
|
||||
__IO uint32_t reserved2 : 26;/* [31:6] */
|
||||
} rf1_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief can inten register, offset:0x14
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t inten;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t tcien : 1; /* [0] */
|
||||
__IO uint32_t rf0mien : 1; /* [1] */
|
||||
__IO uint32_t rf0fien : 1; /* [2] */
|
||||
__IO uint32_t rf0oien : 1; /* [3] */
|
||||
__IO uint32_t rf1mien : 1; /* [4] */
|
||||
__IO uint32_t rf1fien : 1; /* [5] */
|
||||
__IO uint32_t rf1oien : 1; /* [6] */
|
||||
__IO uint32_t reserved1 : 1; /* [7] */
|
||||
__IO uint32_t eaien : 1; /* [8] */
|
||||
__IO uint32_t epien : 1; /* [9] */
|
||||
__IO uint32_t boien : 1; /* [10] */
|
||||
__IO uint32_t etrien : 1; /* [11] */
|
||||
__IO uint32_t reserved2 : 3; /* [14:12] */
|
||||
__IO uint32_t eoien : 1; /* [15] */
|
||||
__IO uint32_t qdzien : 1; /* [16] */
|
||||
__IO uint32_t edzien : 1; /* [17] */
|
||||
__IO uint32_t reserved3 : 14;/* [31:18] */
|
||||
} inten_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief can ests register, offset:0x18
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t ests;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t eaf : 1; /* [0] */
|
||||
__IO uint32_t epf : 1; /* [1] */
|
||||
__IO uint32_t bof : 1; /* [2] */
|
||||
__IO uint32_t reserved1 : 1; /* [3] */
|
||||
__IO uint32_t etr : 3; /* [6:4] */
|
||||
__IO uint32_t reserved2 : 9; /* [15:7] */
|
||||
__IO uint32_t tec : 8; /* [23:16] */
|
||||
__IO uint32_t rec : 8; /* [31:24] */
|
||||
} ests_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief can btmg register, offset:0x1C
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t btmg;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t brdiv : 12;/* [11:0] */
|
||||
__IO uint32_t reserved1 : 4; /* [15:12] */
|
||||
__IO uint32_t bts1 : 4; /* [19:16] */
|
||||
__IO uint32_t bts2 : 3; /* [22:20] */
|
||||
__IO uint32_t reserved2 : 1; /* [23] */
|
||||
__IO uint32_t rsaw : 2; /* [25:24] */
|
||||
__IO uint32_t reserved3 : 4; /* [29:26] */
|
||||
__IO uint32_t lben : 1; /* [30] */
|
||||
__IO uint32_t loen : 1; /* [31] */
|
||||
} btmg_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief can reserved register, offset:0x20~0x17C
|
||||
*/
|
||||
__IO uint32_t reserved1[88];
|
||||
|
||||
/**
|
||||
* @brief can controller area network tx mailbox register, offset:0x180~0x1AC
|
||||
*/
|
||||
can_tx_mailbox_type tx_mailbox[3];
|
||||
|
||||
/**
|
||||
* @brief can controller area network fifo mailbox register, offset:0x1B0~0x1CC
|
||||
*/
|
||||
can_fifo_mailbox_type fifo_mailbox[2];
|
||||
|
||||
/**
|
||||
* @brief can reserved register, offset:0x1D0~0x1FC
|
||||
*/
|
||||
__IO uint32_t reserved2[12];
|
||||
|
||||
/**
|
||||
* @brief can fctrl register, offset:0x200
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t fctrl;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t fcs : 1; /* [0] */
|
||||
__IO uint32_t reserved1 : 31;/* [31:1] */
|
||||
} fctrl_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief can fmcfg register, offset:0x204
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t fmcfg;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t fmsel0 : 1; /* [0] */
|
||||
__IO uint32_t fmsel1 : 1; /* [1] */
|
||||
__IO uint32_t fmsel2 : 1; /* [2] */
|
||||
__IO uint32_t fmsel3 : 1; /* [3] */
|
||||
__IO uint32_t fmsel4 : 1; /* [4] */
|
||||
__IO uint32_t fmsel5 : 1; /* [5] */
|
||||
__IO uint32_t fmsel6 : 1; /* [6] */
|
||||
__IO uint32_t fmsel7 : 1; /* [7] */
|
||||
__IO uint32_t fmsel8 : 1; /* [8] */
|
||||
__IO uint32_t fmsel9 : 1; /* [9] */
|
||||
__IO uint32_t fmsel10 : 1; /* [10] */
|
||||
__IO uint32_t fmsel11 : 1; /* [11] */
|
||||
__IO uint32_t fmsel12 : 1; /* [12] */
|
||||
__IO uint32_t fmsel13 : 1; /* [13] */
|
||||
__IO uint32_t reserved1 : 18;/* [31:14] */
|
||||
} fmcfg_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief can reserved register, offset:0x208
|
||||
*/
|
||||
__IO uint32_t reserved3;
|
||||
|
||||
/**
|
||||
* @brief can fbwcfg register, offset:0x20C
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t fbwcfg;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t fbwsel0 : 1; /* [0] */
|
||||
__IO uint32_t fbwsel1 : 1; /* [1] */
|
||||
__IO uint32_t fbwsel2 : 1; /* [2] */
|
||||
__IO uint32_t fbwsel3 : 1; /* [3] */
|
||||
__IO uint32_t fbwsel4 : 1; /* [4] */
|
||||
__IO uint32_t fbwsel5 : 1; /* [5] */
|
||||
__IO uint32_t fbwsel6 : 1; /* [6] */
|
||||
__IO uint32_t fbwsel7 : 1; /* [7] */
|
||||
__IO uint32_t fbwsel8 : 1; /* [8] */
|
||||
__IO uint32_t fbwsel9 : 1; /* [9] */
|
||||
__IO uint32_t fbwsel10 : 1; /* [10] */
|
||||
__IO uint32_t fbwsel11 : 1; /* [11] */
|
||||
__IO uint32_t fbwsel12 : 1; /* [12] */
|
||||
__IO uint32_t fbwsel13 : 1; /* [13] */
|
||||
__IO uint32_t reserved1 : 18;/* [31:14] */
|
||||
} fbwcfg_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief can reserved register, offset:0x210
|
||||
*/
|
||||
__IO uint32_t reserved4;
|
||||
|
||||
/**
|
||||
* @brief can frf register, offset:0x214
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t frf;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t frfsel0 : 1; /* [0] */
|
||||
__IO uint32_t frfsel1 : 1; /* [1] */
|
||||
__IO uint32_t frfsel2 : 1; /* [2] */
|
||||
__IO uint32_t frfsel3 : 1; /* [3] */
|
||||
__IO uint32_t frfsel4 : 1; /* [4] */
|
||||
__IO uint32_t frfsel5 : 1; /* [5] */
|
||||
__IO uint32_t frfsel6 : 1; /* [6] */
|
||||
__IO uint32_t frfsel7 : 1; /* [7] */
|
||||
__IO uint32_t frfsel8 : 1; /* [8] */
|
||||
__IO uint32_t frfsel9 : 1; /* [9] */
|
||||
__IO uint32_t frfsel10 : 1; /* [10] */
|
||||
__IO uint32_t frfsel11 : 1; /* [11] */
|
||||
__IO uint32_t frfsel12 : 1; /* [12] */
|
||||
__IO uint32_t frfsel13 : 1; /* [13] */
|
||||
__IO uint32_t reserved1 : 18;/* [31:14] */
|
||||
} frf_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief can reserved register, offset:0x218
|
||||
*/
|
||||
__IO uint32_t reserved5;
|
||||
|
||||
/**
|
||||
* @brief can facfg register, offset:0x21C
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t facfg;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t faen0 : 1; /* [0] */
|
||||
__IO uint32_t faen1 : 1; /* [1] */
|
||||
__IO uint32_t faen2 : 1; /* [2] */
|
||||
__IO uint32_t faen3 : 1; /* [3] */
|
||||
__IO uint32_t faen4 : 1; /* [4] */
|
||||
__IO uint32_t faen5 : 1; /* [5] */
|
||||
__IO uint32_t faen6 : 1; /* [6] */
|
||||
__IO uint32_t faen7 : 1; /* [7] */
|
||||
__IO uint32_t faen8 : 1; /* [8] */
|
||||
__IO uint32_t faen9 : 1; /* [9] */
|
||||
__IO uint32_t faen10 : 1; /* [10] */
|
||||
__IO uint32_t faen11 : 1; /* [11] */
|
||||
__IO uint32_t faen12 : 1; /* [12] */
|
||||
__IO uint32_t faen13 : 1; /* [13] */
|
||||
__IO uint32_t reserved1 : 18;/* [31:14] */
|
||||
} facfg_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief can reserved register, offset:0x220~0x23C
|
||||
*/
|
||||
__IO uint32_t reserved6[8];
|
||||
|
||||
/**
|
||||
* @brief can ffb register, offset:0x240~0x2AC
|
||||
*/
|
||||
can_filter_register_type ffb[14];
|
||||
} can_type;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#define CAN1 ((can_type *) CAN1_BASE)
|
||||
#define CAN2 ((can_type *) CAN2_BASE)
|
||||
|
||||
/** @defgroup CAN_exported_functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
void can_reset(can_type* can_x);
|
||||
void can_baudrate_default_para_init(can_baudrate_type* can_baudrate_struct);
|
||||
error_status can_baudrate_set(can_type* can_x, can_baudrate_type* can_baudrate_struct);
|
||||
void can_default_para_init(can_base_type* can_base_struct);
|
||||
error_status can_base_init(can_type* can_x, can_base_type* can_base_struct);
|
||||
void can_filter_default_para_init(can_filter_init_type* can_filter_init_struct);
|
||||
void can_filter_init(can_type* can_x, can_filter_init_type* can_filter_init_struct);
|
||||
void can_debug_transmission_prohibit(can_type* can_x, confirm_state new_state);
|
||||
void can_ttc_mode_enable(can_type* can_x, confirm_state new_state);
|
||||
uint8_t can_message_transmit(can_type* can_x, can_tx_message_type* tx_message_struct);
|
||||
can_transmit_status_type can_transmit_status_get(can_type* can_x, can_tx_mailbox_num_type transmit_mailbox);
|
||||
void can_transmit_cancel(can_type* can_x, can_tx_mailbox_num_type transmit_mailbox);
|
||||
void can_message_receive(can_type* can_x, can_rx_fifo_num_type fifo_number, can_rx_message_type* rx_message_struct);
|
||||
void can_receive_fifo_release(can_type* can_x, can_rx_fifo_num_type fifo_number);
|
||||
uint8_t can_receive_message_pending_get(can_type* can_x, can_rx_fifo_num_type fifo_number);
|
||||
error_status can_operating_mode_set(can_type* can_x, can_operating_mode_type can_operating_mode);
|
||||
can_enter_doze_status_type can_doze_mode_enter(can_type* can_x);
|
||||
can_quit_doze_status_type can_doze_mode_exit(can_type* can_x);
|
||||
can_error_record_type can_error_type_record_get(can_type* can_x);
|
||||
uint8_t can_receive_error_counter_get(can_type* can_x);
|
||||
uint8_t can_transmit_error_counter_get(can_type* can_x);
|
||||
void can_interrupt_enable(can_type* can_x, uint32_t can_int, confirm_state new_state);
|
||||
flag_status can_interrupt_flag_get(can_type* can_x, uint32_t can_flag);
|
||||
flag_status can_flag_get(can_type* can_x, uint32_t can_flag);
|
||||
void can_flag_clear(can_type* can_x, uint32_t can_flag);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,199 @@
|
|||
/**
|
||||
**************************************************************************
|
||||
* @file at32f403a_407_crc.h
|
||||
* @brief at32f403a_407 crc header file
|
||||
**************************************************************************
|
||||
*
|
||||
* Copyright (c) 2025, Artery Technology, All rights reserved.
|
||||
*
|
||||
* The software Board Support Package (BSP) that is made available to
|
||||
* download from Artery official website is the copyrighted work of Artery.
|
||||
* Artery authorizes customers to use, copy, and distribute the BSP
|
||||
* software and its related documentation for the purpose of design and
|
||||
* development in conjunction with Artery microcontrollers. Use of the
|
||||
* software is governed by this copyright notice and the following disclaimer.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
|
||||
* GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
|
||||
* TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
|
||||
* STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
|
||||
* INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
|
||||
*
|
||||
**************************************************************************
|
||||
*/
|
||||
|
||||
/* define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __AT32F403A_407_CRC_H
|
||||
#define __AT32F403A_407_CRC_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
|
||||
/* includes ------------------------------------------------------------------*/
|
||||
#include "at32f403a_407.h"
|
||||
|
||||
/** @addtogroup AT32F403A_407_periph_driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup CRC
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup CRC_exported_types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief crc reverse input data
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
CRC_REVERSE_INPUT_NO_AFFECTE = 0x00, /*!< input data no reverse */
|
||||
CRC_REVERSE_INPUT_BY_BYTE = 0x01, /*!< input data reverse by byte */
|
||||
CRC_REVERSE_INPUT_BY_HALFWORD = 0x02, /*!< input data reverse by half word */
|
||||
CRC_REVERSE_INPUT_BY_WORD = 0x03 /*!< input data reverse by word */
|
||||
} crc_reverse_input_type;
|
||||
|
||||
/**
|
||||
* @brief crc reverse output data
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
CRC_REVERSE_OUTPUT_NO_AFFECTE = 0x00, /*!< output data no reverse */
|
||||
CRC_REVERSE_OUTPUT_DATA = 0x01 /*!< output data reverse by word */
|
||||
} crc_reverse_output_type;
|
||||
|
||||
/**
|
||||
* @brief crc polynomial size
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
CRC_POLY_SIZE_32B = 0x00, /*!< polynomial size 32 bits */
|
||||
CRC_POLY_SIZE_16B = 0x01, /*!< polynomial size 16 bits */
|
||||
CRC_POLY_SIZE_8B = 0x02, /*!< polynomial size 8 bits */
|
||||
CRC_POLY_SIZE_7B = 0x03 /*!< polynomial size 7 bits */
|
||||
} crc_poly_size_type;
|
||||
|
||||
/**
|
||||
* @brief type define crc register all
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
/**
|
||||
* @brief crc dt register, offset:0x00
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t dt;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t dt : 32; /* [31:0] */
|
||||
} dt_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief crc cdt register, offset:0x04
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t cdt;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t cdt : 8 ; /* [7:0] */
|
||||
__IO uint32_t reserved1 : 24 ;/* [31:8] */
|
||||
} cdt_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief crc ctrl register, offset:0x08
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t ctrl;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t rst : 1 ; /* [0] */
|
||||
__IO uint32_t reserved1 : 2 ; /* [2:1] */
|
||||
__IO uint32_t poly_size : 2 ; /* [4:3] */
|
||||
__IO uint32_t revid : 2 ; /* [6:5] */
|
||||
__IO uint32_t revod : 1 ; /* [7] */
|
||||
__IO uint32_t reserved2 : 24 ;/* [31:8] */
|
||||
} ctrl_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief crm reserved1 register, offset:0x0C
|
||||
*/
|
||||
__IO uint32_t reserved1;
|
||||
|
||||
/**
|
||||
* @brief crc idt register, offset:0x10
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t idt;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t idt : 32; /* [31:0] */
|
||||
} idt_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief crc polynomial register, offset:0x14
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t poly;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t poly : 32; /* [31:0] */
|
||||
} poly_bit;
|
||||
};
|
||||
|
||||
} crc_type;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#define CRC ((crc_type *) CRC_BASE)
|
||||
|
||||
/** @defgroup CRC_exported_functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
void crc_data_reset(void);
|
||||
uint32_t crc_one_word_calculate(uint32_t data);
|
||||
uint32_t crc_block_calculate(uint32_t *pbuffer, uint32_t length);
|
||||
uint32_t crc_data_get(void);
|
||||
void crc_common_data_set(uint8_t cdt_value);
|
||||
uint8_t crc_common_data_get(void);
|
||||
void crc_init_data_set(uint32_t value);
|
||||
void crc_reverse_input_data_set(crc_reverse_input_type value);
|
||||
void crc_reverse_output_data_set(crc_reverse_output_type value);
|
||||
void crc_poly_value_set(uint32_t value);
|
||||
uint32_t crc_poly_value_get(void);
|
||||
void crc_poly_size_set(crc_poly_size_type size);
|
||||
crc_poly_size_type crc_poly_size_get(void);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,373 @@
|
|||
/**
|
||||
**************************************************************************
|
||||
* @file at32f403a_407_dac.h
|
||||
* @brief at32f403a_407 dac header file
|
||||
**************************************************************************
|
||||
*
|
||||
* Copyright (c) 2025, Artery Technology, All rights reserved.
|
||||
*
|
||||
* The software Board Support Package (BSP) that is made available to
|
||||
* download from Artery official website is the copyrighted work of Artery.
|
||||
* Artery authorizes customers to use, copy, and distribute the BSP
|
||||
* software and its related documentation for the purpose of design and
|
||||
* development in conjunction with Artery microcontrollers. Use of the
|
||||
* software is governed by this copyright notice and the following disclaimer.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
|
||||
* GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
|
||||
* TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
|
||||
* STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
|
||||
* INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
|
||||
*
|
||||
**************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __AT32F403A_407_DAC_H
|
||||
#define __AT32F403A_407_DAC_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "at32f403a_407.h"
|
||||
|
||||
/** @addtogroup AT32F403A_407_periph_driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup DAC
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define DAC1_D1DMAUDRF ((uint32_t)(0x00002000))
|
||||
#define DAC2_D2DMAUDRF ((uint32_t)(0x20000000))
|
||||
|
||||
/** @defgroup DAC_exported_types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief dac select type
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
DAC1_SELECT = 0x01, /*!< dac1 select */
|
||||
DAC2_SELECT = 0x02 /*!< dac2 select */
|
||||
} dac_select_type;
|
||||
|
||||
/**
|
||||
* @brief dac trigger type
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
DAC_TMR6_TRGOUT_EVENT = 0x00, /*!< dac trigger selection:timer6 trgout event */
|
||||
DAC_TMR8_TRGOUT_EVENT = 0x01, /*!< dac trigger selection:timer8 trgout event */
|
||||
DAC_TMR7_TRGOUT_EVENT = 0x02, /*!< dac trigger selection:timer7 trgout event */
|
||||
DAC_TMR5_TRGOUT_EVENT = 0x03, /*!< dac trigger selection:timer5 trgout event */
|
||||
DAC_TMR2_TRGOUT_EVENT = 0x04, /*!< dac trigger selection:timer2 trgout event */
|
||||
DAC_TMR4_TRGOUT_EVENT = 0x05, /*!< dac trigger selection:timer4 trgout event */
|
||||
DAC_EXTERNAL_INTERRUPT_LINE_9 = 0x06, /*!< dac trigger selection:external line9 */
|
||||
DAC_SOFTWARE_TRIGGER = 0x07 /*!< dac trigger selection:software trigger */
|
||||
} dac_trigger_type;
|
||||
|
||||
/**
|
||||
* @brief dac wave type
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
DAC_WAVE_GENERATE_NONE = 0x00, /*!< dac wave generation disabled */
|
||||
DAC_WAVE_GENERATE_NOISE = 0x01, /*!< dac noise wave generation enabled */
|
||||
DAC_WAVE_GENERATE_TRIANGLE = 0x02 /*!< dac triangle wave generation enabled */
|
||||
} dac_wave_type;
|
||||
|
||||
/**
|
||||
* @brief dac mask amplitude type
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
DAC_LSFR_BIT0_AMPLITUDE_1 = 0x00, /*!< unmask bit0/ triangle amplitude equal to 1 */
|
||||
DAC_LSFR_BIT10_AMPLITUDE_3 = 0x01, /*!< unmask bit[1:0]/ triangle amplitude equal to 3 */
|
||||
DAC_LSFR_BIT20_AMPLITUDE_7 = 0x02, /*!< unmask bit[2:0]/ triangle amplitude equal to 7 */
|
||||
DAC_LSFR_BIT30_AMPLITUDE_15 = 0x03, /*!< unmask bit[3:0]/ triangle amplitude equal to 15 */
|
||||
DAC_LSFR_BIT40_AMPLITUDE_31 = 0x04, /*!< unmask bit[4:0]/ triangle amplitude equal to 31 */
|
||||
DAC_LSFR_BIT50_AMPLITUDE_63 = 0x05, /*!< unmask bit[5:0]/ triangle amplitude equal to 63 */
|
||||
DAC_LSFR_BIT60_AMPLITUDE_127 = 0x06, /*!< unmask bit[6:0]/ triangle amplitude equal to 127 */
|
||||
DAC_LSFR_BIT70_AMPLITUDE_255 = 0x07, /*!< unmask bit[7:0]/ triangle amplitude equal to 255 */
|
||||
DAC_LSFR_BIT80_AMPLITUDE_511 = 0x08, /*!< unmask bit[8:0]/ triangle amplitude equal to 511 */
|
||||
DAC_LSFR_BIT90_AMPLITUDE_1023 = 0x09, /*!< unmask bit[9:0]/ triangle amplitude equal to 1023 */
|
||||
DAC_LSFR_BITA0_AMPLITUDE_2047 = 0x0A, /*!< unmask bit[10:0]/ triangle amplitude equal to 2047 */
|
||||
DAC_LSFR_BITB0_AMPLITUDE_4095 = 0x0B /*!< unmask bit[11:0]/ triangle amplitude equal to 4095 */
|
||||
} dac_mask_amplitude_type;
|
||||
|
||||
/**
|
||||
* @brief dac1 aligned data type
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
DAC1_12BIT_RIGHT = 0x40007408, /*!< dac1 12-bit data right-aligned */
|
||||
DAC1_12BIT_LEFT = 0x4000740C, /*!< dac1 12-bit data left-aligned */
|
||||
DAC1_8BIT_RIGHT = 0x40007410 /*!< dac1 8-bit data right-aligned */
|
||||
} dac1_aligned_data_type;
|
||||
|
||||
/**
|
||||
* @brief dac2 aligned data type
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
DAC2_12BIT_RIGHT = 0x40007414, /*!< dac2 12-bit data right-aligned */
|
||||
DAC2_12BIT_LEFT = 0x40007418, /*!< dac2 12-bit data left-aligned */
|
||||
DAC2_8BIT_RIGHT = 0x4000741C /*!< dac2 8-bit data right-aligned */
|
||||
} dac2_aligned_data_type;
|
||||
|
||||
/**
|
||||
* @brief dac dual data type
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
DAC_DUAL_12BIT_RIGHT = 0x40007420, /*!<double dac 12-bit data right-aligned */
|
||||
DAC_DUAL_12BIT_LEFT = 0x40007424, /*!<double dac 12-bit data left-aligned */
|
||||
DAC_DUAL_8BIT_RIGHT = 0x40007428 /*!<double dac 8-bit data right-aligned */
|
||||
} dac_dual_data_type;
|
||||
|
||||
/**
|
||||
* @brief type define dac register all
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
|
||||
/**
|
||||
* @brief dac ctrl register, offset:0x00
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t ctrl;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t d1en : 1; /* [0] */
|
||||
__IO uint32_t d1obdis : 1; /* [1] */
|
||||
__IO uint32_t d1trgen : 1; /* [2] */
|
||||
__IO uint32_t d1trgsel : 3; /* [5:3] */
|
||||
__IO uint32_t d1nm : 2; /* [7:6] */
|
||||
__IO uint32_t d1nbsel : 4; /* [11:8] */
|
||||
__IO uint32_t d1dmaen : 1; /* [12] */
|
||||
__IO uint32_t reserved1 : 3; /* [15:13] */
|
||||
__IO uint32_t d2en : 1; /* [16] */
|
||||
__IO uint32_t d2obdis : 1; /* [17] */
|
||||
__IO uint32_t d2trgen : 1; /* [18] */
|
||||
__IO uint32_t d2trgsel : 3; /* [21:19] */
|
||||
__IO uint32_t d2nm : 2; /* [23:22] */
|
||||
__IO uint32_t d2nbsel : 4; /* [27:24] */
|
||||
__IO uint32_t d2dmaen : 1; /* [28] */
|
||||
__IO uint32_t reserved2 : 3; /* [31:29] */
|
||||
} ctrl_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief dac swtrg register, offset:0x04
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t swtrg;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t d1swtrg : 1; /* [0] */
|
||||
__IO uint32_t d2swtrg : 1; /* [1] */
|
||||
__IO uint32_t reserved1 : 30;/* [31:2] */
|
||||
} swtrg_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief dac d1dth12r register, offset:0x08
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t d1dth12r;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t d1dt12r : 12;/* [11:0] */
|
||||
__IO uint32_t reserved1 : 20;/* [31:2] */
|
||||
} d1dth12r_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief dac d1dth12l register, offset:0x0C
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t d1dth12l;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t d1dt12l : 12;/* [11:0] */
|
||||
__IO uint32_t reserved1 : 20;/* [31:2] */
|
||||
} d1dth12l_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief dac d1dth8r register, offset:0x10
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t d1dth8r;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t d1dt8r : 8; /* [7:0] */
|
||||
__IO uint32_t reserved1 : 24;/* [31:8] */
|
||||
} d1dth8r_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief dac d2dth12r register, offset:0x14
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t d2dth12r;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t d2dt12r : 12;/* [11:0] */
|
||||
__IO uint32_t reserved1 : 20;/* [31:2] */
|
||||
} d2dth12r_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief dac d2dth12l register, offset:0x18
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t d2dth12l;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t d2dt12l : 12;/* [11:0] */
|
||||
__IO uint32_t reserved1 : 20;/* [31:2] */
|
||||
} d2dth12l_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief dac d2dth8r register, offset:0x1C
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t d2dth8r;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t d2dt8r : 8; /* [7:0] */
|
||||
__IO uint32_t reserved1 : 24;/* [31:8] */
|
||||
} d2dth8r_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief dac ddth12r register, offset:0x20
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t ddth12r;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t dd1dt12r : 12;/* [11:0] */
|
||||
__IO uint32_t reserved1 : 4; /* [15:12] */
|
||||
__IO uint32_t dd2dt12r : 12;/* [27:16] */
|
||||
__IO uint32_t reserved2 : 4; /* [31:28] */
|
||||
} ddth12r_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief dac ddth12l register, offset:0x24
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t ddth12l;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t reserved1 : 4; /* [3:0] */
|
||||
__IO uint32_t dd1dt12l : 12;/* [15:4] */
|
||||
__IO uint32_t reserved2 : 4; /* [19:16] */
|
||||
__IO uint32_t dd2dt12l : 12;/* [31:20] */
|
||||
} ddth12l_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief dac ddth8r register, offset:0x28
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t ddth8r;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t dd1dt8r : 8; /* [7:0] */
|
||||
__IO uint32_t dd2dt8r : 8; /* [15:8] */
|
||||
__IO uint32_t reserved1 : 16;/* [31:16] */
|
||||
} ddth8r_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief dac d1odt register, offset:0x2c
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t d1odt;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t d1odt : 12;/* [11:0] */
|
||||
__IO uint32_t reserved1 : 20;/* [31:12] */
|
||||
} d1odt_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief dac d2odt register, offset:0x30
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t d2odt;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t d2odt : 12;/* [11:0] */
|
||||
__IO uint32_t reserved1 : 20;/* [31:12] */
|
||||
} d2odt_bit;
|
||||
};
|
||||
} dac_type;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#define DAC ((dac_type *) DAC_BASE)
|
||||
|
||||
/** @defgroup DAC_exported_functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
void dac_reset(void);
|
||||
void dac_enable(dac_select_type dac_select, confirm_state new_state);
|
||||
void dac_output_buffer_enable(dac_select_type dac_select, confirm_state new_state);
|
||||
void dac_trigger_enable(dac_select_type dac_select, confirm_state new_state);
|
||||
void dac_trigger_select(dac_select_type dac_select, dac_trigger_type dac_trigger_source);
|
||||
void dac_software_trigger_generate(dac_select_type dac_select);
|
||||
void dac_dual_software_trigger_generate(void);
|
||||
void dac_wave_generate(dac_select_type dac_select, dac_wave_type dac_wave);
|
||||
void dac_mask_amplitude_select(dac_select_type dac_select, dac_mask_amplitude_type dac_mask_amplitude);
|
||||
void dac_dma_enable(dac_select_type dac_select, confirm_state new_state);
|
||||
uint16_t dac_data_output_get(dac_select_type dac_select);
|
||||
void dac_1_data_set(dac1_aligned_data_type dac1_aligned, uint16_t dac1_data);
|
||||
void dac_2_data_set(dac2_aligned_data_type dac2_aligned, uint16_t dac2_data);
|
||||
void dac_dual_data_set(dac_dual_data_type dac_dual, uint16_t data1, uint16_t data2);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,170 @@
|
|||
/**
|
||||
**************************************************************************
|
||||
* @file at32f403a_407_debug.h
|
||||
* @brief at32f403a_407 debug header file
|
||||
**************************************************************************
|
||||
*
|
||||
* Copyright (c) 2025, Artery Technology, All rights reserved.
|
||||
*
|
||||
* The software Board Support Package (BSP) that is made available to
|
||||
* download from Artery official website is the copyrighted work of Artery.
|
||||
* Artery authorizes customers to use, copy, and distribute the BSP
|
||||
* software and its related documentation for the purpose of design and
|
||||
* development in conjunction with Artery microcontrollers. Use of the
|
||||
* software is governed by this copyright notice and the following disclaimer.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
|
||||
* GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
|
||||
* TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
|
||||
* STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
|
||||
* INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
|
||||
*
|
||||
**************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __AT32F403A_407_DEBUG_H
|
||||
#define __AT32F403A_407_DEBUG_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "at32f403a_407.h"
|
||||
|
||||
/** @addtogroup AT32F403A_407_periph_driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup DEBUG
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup DEBUG_mode_definition
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define DEBUG_SLEEP 0x00000001 /*!< debug sleep mode */
|
||||
#define DEBUG_DEEPSLEEP 0x00000002 /*!< debug deepsleep mode */
|
||||
#define DEBUG_STANDBY 0x00000004 /*!< debug standby mode */
|
||||
#define DEBUG_WDT_PAUSE 0x00000100 /*!< debug watchdog timer pause */
|
||||
#define DEBUG_WWDT_PAUSE 0x00000200 /*!< debug window watchdog timer pause */
|
||||
#define DEBUG_TMR1_PAUSE 0x00000400 /*!< debug timer1 pause */
|
||||
#define DEBUG_TMR3_PAUSE 0x00001000 /*!< debug timer3 pause */
|
||||
#define DEBUG_I2C1_SMBUS_TIMEOUT 0x00008000 /*!< debug i2c1 smbus timeout */
|
||||
#define DEBUG_I2C2_SMBUS_TIMEOUT 0x00010000 /*!< debug i2c2 smbus timeout */
|
||||
#define DEBUG_I2C3_SMBUS_TIMEOUT 0x80000000 /*!< debug i2c3 smbus timeout */
|
||||
#define DEBUG_TMR2_PAUSE 0x00000800 /*!< debug timer2 pause */
|
||||
#define DEBUG_TMR4_PAUSE 0x00002000 /*!< debug timer4 pause */
|
||||
#define DEBUG_CAN1_PAUSE 0x00004000 /*!< debug can1 pause */
|
||||
#define DEBUG_TMR8_PAUSE 0x00020000 /*!< debug timer8 pause */
|
||||
#define DEBUG_TMR5_PAUSE 0x00040000 /*!< debug timer5 pause */
|
||||
#define DEBUG_TMR6_PAUSE 0x00080000 /*!< debug timer6 pause */
|
||||
#define DEBUG_TMR7_PAUSE 0x00100000 /*!< debug timer7 pause */
|
||||
#define DEBUG_CAN2_PAUSE 0x00200000 /*!< debug can2 pause */
|
||||
#define DEBUG_TMR12_PAUSE 0x02000000 /*!< debug timer12 pause */
|
||||
#define DEBUG_TMR13_PAUSE 0x04000000 /*!< debug timer13 pause */
|
||||
#define DEBUG_TMR14_PAUSE 0x08000000 /*!< debug timer14 pause */
|
||||
#define DEBUG_TMR9_PAUSE 0x10000000 /*!< debug timer9 pause */
|
||||
#define DEBUG_TMR10_PAUSE 0x20000000 /*!< debug timer10 pause */
|
||||
#define DEBUG_TMR11_PAUSE 0x40000000 /*!< debug timer11 pause */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DEBUG_exported_types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief type define debug register all
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
/**
|
||||
* @brief debug idcode register, offset:0x00
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t pid;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t pid : 32;/* [31:0] */
|
||||
} idcode_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief debug ctrl register, offset:0x04
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t ctrl;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t sleep_debug : 1;/* [0] */
|
||||
__IO uint32_t deepsleep_debug : 1;/* [1] */
|
||||
__IO uint32_t standby_debug : 1;/* [2] */
|
||||
__IO uint32_t reserved1 : 2;/* [4:3] */
|
||||
__IO uint32_t trace_ioen : 1;/* [5] */
|
||||
__IO uint32_t trace_mode : 2;/* [7:6] */
|
||||
__IO uint32_t wdt_pause : 1;/* [8] */
|
||||
__IO uint32_t wwdt_pause : 1;/* [9] */
|
||||
__IO uint32_t tmr1_pause : 1;/* [10] */
|
||||
__IO uint32_t tmr2_pause : 1;/* [11] */
|
||||
__IO uint32_t tmr3_pause : 1;/* [12] */
|
||||
__IO uint32_t tmr4_pause : 1;/* [13] */
|
||||
__IO uint32_t can1_pause : 1;/* [14] */
|
||||
__IO uint32_t i2c1_smbus_timeout : 1;/* [15] */
|
||||
__IO uint32_t i2c2_smbus_timeout : 1;/* [16] */
|
||||
__IO uint32_t tmr8_pause : 1;/* [17] */
|
||||
__IO uint32_t tmr5_pause : 1;/* [18] */
|
||||
__IO uint32_t tmr6_pause : 1;/* [19] */
|
||||
__IO uint32_t tmr7_pause : 1;/* [20] */
|
||||
__IO uint32_t can2_pause : 1;/* [21] */
|
||||
__IO uint32_t reserved2 : 3;/* [24:22] */
|
||||
__IO uint32_t tmr12_pause : 1;/* [25] */
|
||||
__IO uint32_t tmr13_pause : 1;/* [26] */
|
||||
__IO uint32_t tmr14_pause : 1;/* [27] */
|
||||
__IO uint32_t tmr9_pause : 1;/* [28] */
|
||||
__IO uint32_t tmr10_pause : 1;/* [29] */
|
||||
__IO uint32_t tmr11_pause : 1;/* [30] */
|
||||
__IO uint32_t i2c3_smbus_timeout : 1;/* [31] */
|
||||
} ctrl_bit;
|
||||
};
|
||||
|
||||
} debug_type;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#define DEBUGMCU ((debug_type *) DEBUG_BASE)
|
||||
|
||||
/** @defgroup DEBUG_exported_functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
uint32_t debug_device_id_get(void);
|
||||
void debug_periph_mode_set(uint32_t periph_debug_mode, confirm_state new_state);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,70 @@
|
|||
/**
|
||||
**************************************************************************
|
||||
* @file at32f403a_407_def.h
|
||||
* @brief at32f403a_407 macros header file
|
||||
**************************************************************************
|
||||
*
|
||||
* Copyright (c) 2025, Artery Technology, All rights reserved.
|
||||
*
|
||||
* The software Board Support Package (BSP) that is made available to
|
||||
* download from Artery official website is the copyrighted work of Artery.
|
||||
* Artery authorizes customers to use, copy, and distribute the BSP
|
||||
* software and its related documentation for the purpose of design and
|
||||
* development in conjunction with Artery microcontrollers. Use of the
|
||||
* software is governed by this copyright notice and the following disclaimer.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
|
||||
* GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
|
||||
* TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
|
||||
* STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
|
||||
* INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
|
||||
*
|
||||
**************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __AT32F403A_407_DEF_H
|
||||
#define __AT32F403A_407_DEF_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* gnu compiler */
|
||||
#if defined (__GNUC__)
|
||||
#ifndef ALIGNED_HEAD
|
||||
#define ALIGNED_HEAD
|
||||
#endif
|
||||
#ifndef ALIGNED_TAIL
|
||||
#define ALIGNED_TAIL __attribute__ ((aligned (4)))
|
||||
#endif
|
||||
#endif
|
||||
|
||||
/* arm compiler */
|
||||
#if defined (__CC_ARM)
|
||||
#ifndef ALIGNED_HEAD
|
||||
#define ALIGNED_HEAD __align(4)
|
||||
#endif
|
||||
#ifndef ALIGNED_TAIL
|
||||
#define ALIGNED_TAIL
|
||||
#endif
|
||||
#endif
|
||||
|
||||
/* iar compiler */
|
||||
#if defined (__ICCARM__)
|
||||
#ifndef ALIGNED_HEAD
|
||||
#define ALIGNED_HEAD
|
||||
#endif
|
||||
#ifndef ALIGNED_TAIL
|
||||
#define ALIGNED_TAIL
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#define UNUSED(x) (void)x /* to avoid gcc/g++ warnings */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,551 @@
|
|||
/**
|
||||
**************************************************************************
|
||||
* @file at32f403a_407_dma.h
|
||||
* @brief at32f403a_407 dma header file
|
||||
**************************************************************************
|
||||
*
|
||||
* Copyright (c) 2025, Artery Technology, All rights reserved.
|
||||
*
|
||||
* The software Board Support Package (BSP) that is made available to
|
||||
* download from Artery official website is the copyrighted work of Artery.
|
||||
* Artery authorizes customers to use, copy, and distribute the BSP
|
||||
* software and its related documentation for the purpose of design and
|
||||
* development in conjunction with Artery microcontrollers. Use of the
|
||||
* software is governed by this copyright notice and the following disclaimer.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
|
||||
* GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
|
||||
* TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
|
||||
* STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
|
||||
* INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
|
||||
*
|
||||
**************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __AT32F403A_407_DMA_H
|
||||
#define __AT32F403A_407_DMA_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "at32f403a_407.h"
|
||||
|
||||
/** @addtogroup AT32F403A_407_periph_driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup DMA
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup DMA_interrupts_definition
|
||||
* @brief dma interrupt
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define DMA_FDT_INT ((uint32_t)0x00000002) /*!< dma full data transfer interrupt */
|
||||
#define DMA_HDT_INT ((uint32_t)0x00000004) /*!< dma half data transfer interrupt */
|
||||
#define DMA_DTERR_INT ((uint32_t)0x00000008) /*!< dma errorr interrupt */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DMA_flexible_channel
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define FLEX_CHANNEL1 ((uint8_t)0x01) /*!< dma flexible channel1 */
|
||||
#define FLEX_CHANNEL2 ((uint8_t)0x02) /*!< dma flexible channel2 */
|
||||
#define FLEX_CHANNEL3 ((uint8_t)0x03) /*!< dma flexible channel3 */
|
||||
#define FLEX_CHANNEL4 ((uint8_t)0x04) /*!< dma flexible channel4 */
|
||||
#define FLEX_CHANNEL5 ((uint8_t)0x05) /*!< dma flexible channel5 */
|
||||
#define FLEX_CHANNEL6 ((uint8_t)0x06) /*!< dma flexible channel6 */
|
||||
#define FLEX_CHANNEL7 ((uint8_t)0x07) /*!< dma flexible channel7 */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DMA_flags_definition
|
||||
* @brief dma flag
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define DMA1_GL1_FLAG ((uint32_t)0x00000001) /*!< dma1 channel1 global flag */
|
||||
#define DMA1_FDT1_FLAG ((uint32_t)0x00000002) /*!< dma1 channel1 full data transfer flag */
|
||||
#define DMA1_HDT1_FLAG ((uint32_t)0x00000004) /*!< dma1 channel1 half data transfer flag */
|
||||
#define DMA1_DTERR1_FLAG ((uint32_t)0x00000008) /*!< dma1 channel1 error flag */
|
||||
#define DMA1_GL2_FLAG ((uint32_t)0x00000010) /*!< dma1 channel2 global flag */
|
||||
#define DMA1_FDT2_FLAG ((uint32_t)0x00000020) /*!< dma1 channel2 full data transfer flag */
|
||||
#define DMA1_HDT2_FLAG ((uint32_t)0x00000040) /*!< dma1 channel2 half data transfer flag */
|
||||
#define DMA1_DTERR2_FLAG ((uint32_t)0x00000080) /*!< dma1 channel2 error flag */
|
||||
#define DMA1_GL3_FLAG ((uint32_t)0x00000100) /*!< dma1 channel3 global flag */
|
||||
#define DMA1_FDT3_FLAG ((uint32_t)0x00000200) /*!< dma1 channel3 full data transfer flag */
|
||||
#define DMA1_HDT3_FLAG ((uint32_t)0x00000400) /*!< dma1 channel3 half data transfer flag */
|
||||
#define DMA1_DTERR3_FLAG ((uint32_t)0x00000800) /*!< dma1 channel3 error flag */
|
||||
#define DMA1_GL4_FLAG ((uint32_t)0x00001000) /*!< dma1 channel4 global flag */
|
||||
#define DMA1_FDT4_FLAG ((uint32_t)0x00002000) /*!< dma1 channel4 full data transfer flag */
|
||||
#define DMA1_HDT4_FLAG ((uint32_t)0x00004000) /*!< dma1 channel4 half data transfer flag */
|
||||
#define DMA1_DTERR4_FLAG ((uint32_t)0x00008000) /*!< dma1 channel4 error flag */
|
||||
#define DMA1_GL5_FLAG ((uint32_t)0x00010000) /*!< dma1 channel5 global flag */
|
||||
#define DMA1_FDT5_FLAG ((uint32_t)0x00020000) /*!< dma1 channel5 full data transfer flag */
|
||||
#define DMA1_HDT5_FLAG ((uint32_t)0x00040000) /*!< dma1 channel5 half data transfer flag */
|
||||
#define DMA1_DTERR5_FLAG ((uint32_t)0x00080000) /*!< dma1 channel5 error flag */
|
||||
#define DMA1_GL6_FLAG ((uint32_t)0x00100000) /*!< dma1 channel6 global flag */
|
||||
#define DMA1_FDT6_FLAG ((uint32_t)0x00200000) /*!< dma1 channel6 full data transfer flag */
|
||||
#define DMA1_HDT6_FLAG ((uint32_t)0x00400000) /*!< dma1 channel6 half data transfer flag */
|
||||
#define DMA1_DTERR6_FLAG ((uint32_t)0x00800000) /*!< dma1 channel6 error flag */
|
||||
#define DMA1_GL7_FLAG ((uint32_t)0x01000000) /*!< dma1 channel7 global flag */
|
||||
#define DMA1_FDT7_FLAG ((uint32_t)0x02000000) /*!< dma1 channel7 full data transfer flag */
|
||||
#define DMA1_HDT7_FLAG ((uint32_t)0x04000000) /*!< dma1 channel7 half data transfer flag */
|
||||
#define DMA1_DTERR7_FLAG ((uint32_t)0x08000000) /*!< dma1 channel7 error flag */
|
||||
|
||||
#define DMA2_GL1_FLAG ((uint32_t)0x10000001) /*!< dma2 channel1 global flag */
|
||||
#define DMA2_FDT1_FLAG ((uint32_t)0x10000002) /*!< dma2 channel1 full data transfer flag */
|
||||
#define DMA2_HDT1_FLAG ((uint32_t)0x10000004) /*!< dma2 channel1 half data transfer flag */
|
||||
#define DMA2_DTERR1_FLAG ((uint32_t)0x10000008) /*!< dma2 channel1 error flag */
|
||||
#define DMA2_GL2_FLAG ((uint32_t)0x10000010) /*!< dma2 channel2 global flag */
|
||||
#define DMA2_FDT2_FLAG ((uint32_t)0x10000020) /*!< dma2 channel2 full data transfer flag */
|
||||
#define DMA2_HDT2_FLAG ((uint32_t)0x10000040) /*!< dma2 channel2 half data transfer flag */
|
||||
#define DMA2_DTERR2_FLAG ((uint32_t)0x10000080) /*!< dma2 channel2 error flag */
|
||||
#define DMA2_GL3_FLAG ((uint32_t)0x10000100) /*!< dma2 channel3 global flag */
|
||||
#define DMA2_FDT3_FLAG ((uint32_t)0x10000200) /*!< dma2 channel3 full data transfer flag */
|
||||
#define DMA2_HDT3_FLAG ((uint32_t)0x10000400) /*!< dma2 channel3 half data transfer flag */
|
||||
#define DMA2_DTERR3_FLAG ((uint32_t)0x10000800) /*!< dma2 channel3 error flag */
|
||||
#define DMA2_GL4_FLAG ((uint32_t)0x10001000) /*!< dma2 channel4 global flag */
|
||||
#define DMA2_FDT4_FLAG ((uint32_t)0x10002000) /*!< dma2 channel4 full data transfer flag */
|
||||
#define DMA2_HDT4_FLAG ((uint32_t)0x10004000) /*!< dma2 channel4 half data transfer flag */
|
||||
#define DMA2_DTERR4_FLAG ((uint32_t)0x10008000) /*!< dma2 channel4 error flag */
|
||||
#define DMA2_GL5_FLAG ((uint32_t)0x10010000) /*!< dma2 channel5 global flag */
|
||||
#define DMA2_FDT5_FLAG ((uint32_t)0x10020000) /*!< dma2 channel5 full data transfer flag */
|
||||
#define DMA2_HDT5_FLAG ((uint32_t)0x10040000) /*!< dma2 channel5 half data transfer flag */
|
||||
#define DMA2_DTERR5_FLAG ((uint32_t)0x10080000) /*!< dma2 channel5 error flag */
|
||||
#define DMA2_GL6_FLAG ((uint32_t)0x10100000) /*!< dma2 channel6 global flag */
|
||||
#define DMA2_FDT6_FLAG ((uint32_t)0x10200000) /*!< dma2 channel6 full data transfer flag */
|
||||
#define DMA2_HDT6_FLAG ((uint32_t)0x10400000) /*!< dma2 channel6 half data transfer flag */
|
||||
#define DMA2_DTERR6_FLAG ((uint32_t)0x10800000) /*!< dma2 channel6 error flag */
|
||||
#define DMA2_GL7_FLAG ((uint32_t)0x11000000) /*!< dma2 channel7 global flag */
|
||||
#define DMA2_FDT7_FLAG ((uint32_t)0x12000000) /*!< dma2 channel7 full data transfer flag */
|
||||
#define DMA2_HDT7_FLAG ((uint32_t)0x14000000) /*!< dma2 channel7 half data transfer flag */
|
||||
#define DMA2_DTERR7_FLAG ((uint32_t)0x18000000) /*!< dma2 channel7 error flag */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DMA_exported_types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief dma flexible request type
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
DMA_FLEXIBLE_ADC1 = 0x01, /*!< adc1 flexible request id */
|
||||
DMA_FLEXIBLE_ADC3 = 0x03, /*!< adc3 flexible request id */
|
||||
DMA_FLEXIBLE_DAC1 = 0x05, /*!< dac1 flexible request id */
|
||||
DMA_FLEXIBLE_DAC2 = 0x06, /*!< dac2 flexible request id */
|
||||
DMA_FLEXIBLE_SPI1_RX = 0x09, /*!< spi1_rx flexible request id */
|
||||
DMA_FLEXIBLE_SPI1_TX = 0x0A, /*!< spi1_tx flexible request id */
|
||||
DMA_FLEXIBLE_SPI2_RX = 0x0B, /*!< spi2_rx flexible request id */
|
||||
DMA_FLEXIBLE_SPI2_TX = 0x0C, /*!< spi2_tx flexible request id */
|
||||
DMA_FLEXIBLE_SPI3_RX = 0x0D, /*!< spi3_rx flexible request id */
|
||||
DMA_FLEXIBLE_SPI3_TX = 0x0E, /*!< spi3_tx flexible request id */
|
||||
DMA_FLEXIBLE_SPI4_RX = 0x0F, /*!< spi4_rx flexible request id */
|
||||
DMA_FLEXIBLE_SPI4_TX = 0x10, /*!< spi4_tx flexible request id */
|
||||
DMA_FLEXIBLE_I2S2EXT_RX = 0x11, /*!< i2s2ext_rx flexible request id */
|
||||
DMA_FLEXIBLE_I2S2EXT_TX = 0x12, /*!< i2s2ext_tx flexible request id */
|
||||
DMA_FLEXIBLE_I2S3EXT_RX = 0x13, /*!< i2s3ext_rx flexible request id */
|
||||
DMA_FLEXIBLE_I2S3EXT_TX = 0x14, /*!< i2s3ext_tx flexible request id */
|
||||
DMA_FLEXIBLE_UART1_RX = 0x19, /*!< uart1_rx flexible request id */
|
||||
DMA_FLEXIBLE_UART1_TX = 0x1A, /*!< uart1_tx flexible request id */
|
||||
DMA_FLEXIBLE_UART2_RX = 0x1B, /*!< uart2_rx flexible request id */
|
||||
DMA_FLEXIBLE_UART2_TX = 0x1C, /*!< uart2_tx flexible request id */
|
||||
DMA_FLEXIBLE_UART3_RX = 0x1D, /*!< uart3_rx flexible request id */
|
||||
DMA_FLEXIBLE_UART3_TX = 0x1E, /*!< uart3_tx flexible request id */
|
||||
DMA_FLEXIBLE_UART4_RX = 0x1F, /*!< uart4_rx flexible request id */
|
||||
DMA_FLEXIBLE_UART4_TX = 0x20, /*!< uart4_tx flexible request id */
|
||||
DMA_FLEXIBLE_UART5_RX = 0x21, /*!< uart5_rx flexible request id */
|
||||
DMA_FLEXIBLE_UART5_TX = 0x22, /*!< uart5_tx flexible request id */
|
||||
DMA_FLEXIBLE_UART6_RX = 0x23, /*!< uart6_rx flexible request id */
|
||||
DMA_FLEXIBLE_UART6_TX = 0x24, /*!< uart6_tx flexible request id */
|
||||
DMA_FLEXIBLE_UART7_RX = 0x25, /*!< uart7_rx flexible request id */
|
||||
DMA_FLEXIBLE_UART7_TX = 0x26, /*!< uart7_tx flexible request id */
|
||||
DMA_FLEXIBLE_UART8_RX = 0x27, /*!< uart8_rx flexible request id */
|
||||
DMA_FLEXIBLE_UART8_TX = 0x28, /*!< uart8_tx flexible request id */
|
||||
DMA_FLEXIBLE_I2C1_RX = 0x29, /*!< i2c1_rx flexible request id */
|
||||
DMA_FLEXIBLE_I2C1_TX = 0x2A, /*!< i2c1_tx flexible request id */
|
||||
DMA_FLEXIBLE_I2C2_RX = 0x2B, /*!< i2c2_rx flexible request id */
|
||||
DMA_FLEXIBLE_I2C2_TX = 0x2C, /*!< i2c2_tx flexible request id */
|
||||
DMA_FLEXIBLE_I2C3_RX = 0x2D, /*!< i2c3_rx flexible request id */
|
||||
DMA_FLEXIBLE_I2C3_TX = 0x2E, /*!< i2c3_tx flexible request id */
|
||||
DMA_FLEXIBLE_SDIO1 = 0x31, /*!< sdio1 flexible request id */
|
||||
DMA_FLEXIBLE_SDIO2 = 0x32, /*!< sdio2 flexible request id */
|
||||
DMA_FLEXIBLE_TMR1_TRIG = 0x35, /*!< tmr1_trig flexible request id */
|
||||
DMA_FLEXIBLE_TMR1_HALL = 0x36, /*!< tmr1_hall flexible request id */
|
||||
DMA_FLEXIBLE_TMR1_OVERFLOW = 0x37, /*!< tmr1_overflow flexible request id */
|
||||
DMA_FLEXIBLE_TMR1_CH1 = 0x38, /*!< tmr1_ch1 flexible request id */
|
||||
DMA_FLEXIBLE_TMR1_CH2 = 0x39, /*!< tmr1_ch2 flexible request id */
|
||||
DMA_FLEXIBLE_TMR1_CH3 = 0x3A, /*!< tmr1_ch3 flexible request id */
|
||||
DMA_FLEXIBLE_TMR1_CH4 = 0x3B, /*!< tmr1_ch4 flexible request id */
|
||||
DMA_FLEXIBLE_TMR2_TRIG = 0x3D, /*!< tmr2_trig flexible request id */
|
||||
DMA_FLEXIBLE_TMR2_OVERFLOW = 0x3F, /*!< tmr2_overflow flexible request id */
|
||||
DMA_FLEXIBLE_TMR2_CH1 = 0x40, /*!< tmr2_ch1 flexible request id */
|
||||
DMA_FLEXIBLE_TMR2_CH2 = 0x41, /*!< tmr2_ch2 flexible request id */
|
||||
DMA_FLEXIBLE_TMR2_CH3 = 0x42, /*!< tmr2_ch3 flexible request id */
|
||||
DMA_FLEXIBLE_TMR2_CH4 = 0x43, /*!< tmr2_ch4 flexible request id */
|
||||
DMA_FLEXIBLE_TMR3_TRIG = 0x45, /*!< tmr3_trig flexible request id */
|
||||
DMA_FLEXIBLE_TMR3_OVERFLOW = 0x47, /*!< tmr3_overflow flexible request id */
|
||||
DMA_FLEXIBLE_TMR3_CH1 = 0x48, /*!< tmr3_ch1 flexible request id */
|
||||
DMA_FLEXIBLE_TMR3_CH2 = 0x49, /*!< tmr3_ch2 flexible request id */
|
||||
DMA_FLEXIBLE_TMR3_CH3 = 0x4A, /*!< tmr3_ch3 flexible request id */
|
||||
DMA_FLEXIBLE_TMR3_CH4 = 0x4B, /*!< tmr3_ch4 flexible request id */
|
||||
DMA_FLEXIBLE_TMR4_TRIG = 0x4D, /*!< tmr4_trig flexible request id */
|
||||
DMA_FLEXIBLE_TMR4_OVERFLOW = 0x4F, /*!< tmr4_overflow flexible request id */
|
||||
DMA_FLEXIBLE_TMR4_CH1 = 0x50, /*!< tmr4_ch1 flexible request id */
|
||||
DMA_FLEXIBLE_TMR4_CH2 = 0x51, /*!< tmr4_ch2 flexible request id */
|
||||
DMA_FLEXIBLE_TMR4_CH3 = 0x52, /*!< tmr4_ch3 flexible request id */
|
||||
DMA_FLEXIBLE_TMR4_CH4 = 0x53, /*!< tmr4_ch4 flexible request id */
|
||||
DMA_FLEXIBLE_TMR5_TRIG = 0x55, /*!< tmr5_trig flexible request id */
|
||||
DMA_FLEXIBLE_TMR5_OVERFLOW = 0x57, /*!< tmr5_overflow flexible request id */
|
||||
DMA_FLEXIBLE_TMR5_CH1 = 0x58, /*!< tmr5_ch1 flexible request id */
|
||||
DMA_FLEXIBLE_TMR5_CH2 = 0x59, /*!< tmr5_ch2 flexible request id */
|
||||
DMA_FLEXIBLE_TMR5_CH3 = 0x5A, /*!< tmr5_ch3 flexible request id */
|
||||
DMA_FLEXIBLE_TMR5_CH4 = 0x5B, /*!< tmr5_ch4 flexible request id */
|
||||
DMA_FLEXIBLE_TMR6_OVERFLOW = 0x5F, /*!< tmr6_overflow flexible request id */
|
||||
DMA_FLEXIBLE_TMR7_OVERFLOW = 0x67, /*!< tmr7_overflow flexible request id */
|
||||
DMA_FLEXIBLE_TMR8_TRIG = 0x6D, /*!< tmr8_trig flexible request id */
|
||||
DMA_FLEXIBLE_TMR8_HALL = 0x6E, /*!< tmr8_hall flexible request id */
|
||||
DMA_FLEXIBLE_TMR8_OVERFLOW = 0x6F, /*!< tmr8_overflow flexible request id */
|
||||
DMA_FLEXIBLE_TMR8_CH1 = 0x70, /*!< tmr8_ch1 flexible request id */
|
||||
DMA_FLEXIBLE_TMR8_CH2 = 0x71, /*!< tmr8_ch2 flexible request id */
|
||||
DMA_FLEXIBLE_TMR8_CH3 = 0x72, /*!< tmr8_ch3 flexible request id */
|
||||
DMA_FLEXIBLE_TMR8_CH4 = 0x73 /*!< tmr8_ch4 flexible request id */
|
||||
} dma_flexible_request_type;
|
||||
|
||||
/**
|
||||
* @brief dma direction type
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
DMA_DIR_PERIPHERAL_TO_MEMORY = 0x0000, /*!< dma data transfer direction:peripheral to memory */
|
||||
DMA_DIR_MEMORY_TO_PERIPHERAL = 0x0010, /*!< dma data transfer direction:memory to peripheral */
|
||||
DMA_DIR_MEMORY_TO_MEMORY = 0x4000 /*!< dma data transfer direction:memory to memory,
|
||||
note:if the direction is memory to memory,peripheral_base_addr as source and memory_base_addr as destnation */
|
||||
} dma_dir_type;
|
||||
|
||||
/**
|
||||
* @brief dma peripheral incremented type
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
DMA_PERIPHERAL_INC_DISABLE = 0x00, /*!< dma peripheral increment mode disable */
|
||||
DMA_PERIPHERAL_INC_ENABLE = 0x01 /*!< dma peripheral increment mode enable */
|
||||
} dma_peripheral_inc_type;
|
||||
|
||||
/**
|
||||
* @brief dma memory incremented type
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
DMA_MEMORY_INC_DISABLE = 0x00, /*!< dma memory increment mode disable */
|
||||
DMA_MEMORY_INC_ENABLE = 0x01 /*!< dma memory increment mode enable */
|
||||
} dma_memory_inc_type;
|
||||
|
||||
/**
|
||||
* @brief dma peripheral data size type
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
DMA_PERIPHERAL_DATA_WIDTH_BYTE = 0x00, /*!< dma peripheral databus width 8bit */
|
||||
DMA_PERIPHERAL_DATA_WIDTH_HALFWORD = 0x01, /*!< dma peripheral databus width 16bit */
|
||||
DMA_PERIPHERAL_DATA_WIDTH_WORD = 0x02 /*!< dma peripheral databus width 32bit */
|
||||
} dma_peripheral_data_size_type;
|
||||
|
||||
/**
|
||||
* @brief dma memory data size type
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
DMA_MEMORY_DATA_WIDTH_BYTE = 0x00, /*!< dma memory databus width 8bit */
|
||||
DMA_MEMORY_DATA_WIDTH_HALFWORD = 0x01, /*!< dma memory databus width 16bit */
|
||||
DMA_MEMORY_DATA_WIDTH_WORD = 0x02 /*!< dma memory databus width 32bit */
|
||||
} dma_memory_data_size_type;
|
||||
|
||||
/**
|
||||
* @brief dma priority level type
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
DMA_PRIORITY_LOW = 0x00, /*!< dma channel priority: low */
|
||||
DMA_PRIORITY_MEDIUM = 0x01, /*!< dma channel priority: mediue */
|
||||
DMA_PRIORITY_HIGH = 0x02, /*!< dma channel priority: high */
|
||||
DMA_PRIORITY_VERY_HIGH = 0x03 /*!< dma channel priority: very high */
|
||||
} dma_priority_level_type;
|
||||
|
||||
/**
|
||||
* @brief dma init type
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t peripheral_base_addr; /*!< base addrress for peripheral */
|
||||
uint32_t memory_base_addr; /*!< base addrress for memory */
|
||||
dma_dir_type direction; /*!< dma transmit direction, peripheral as source or as destnation */
|
||||
uint16_t buffer_size; /*!< counter to transfer */
|
||||
confirm_state peripheral_inc_enable; /*!< periphera address increment after one transmit */
|
||||
confirm_state memory_inc_enable; /*!< memory address increment after one transmit */
|
||||
dma_peripheral_data_size_type peripheral_data_width; /*!< peripheral data width for transmit */
|
||||
dma_memory_data_size_type memory_data_width; /*!< memory data width for transmit */
|
||||
confirm_state loop_mode_enable; /*!< when circular mode enable, buffer size will reload if count to 0 */
|
||||
dma_priority_level_type priority; /*!< dma priority can choose from very high, high, dedium or low */
|
||||
} dma_init_type;
|
||||
|
||||
/**
|
||||
* @brief type define dma register
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
/**
|
||||
* @brief dma sts register, offset:0x00
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t sts;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t gf1 : 1; /* [0] */
|
||||
__IO uint32_t fdtf1 : 1; /* [1] */
|
||||
__IO uint32_t hdtf1 : 1; /* [2] */
|
||||
__IO uint32_t dterrf1 : 1; /* [3] */
|
||||
__IO uint32_t gf2 : 1; /* [4] */
|
||||
__IO uint32_t fdtf2 : 1; /* [5] */
|
||||
__IO uint32_t hdtf2 : 1; /* [6] */
|
||||
__IO uint32_t dterrf2 : 1; /* [7] */
|
||||
__IO uint32_t gf3 : 1; /* [8] */
|
||||
__IO uint32_t fdtf3 : 1; /* [9] */
|
||||
__IO uint32_t hdtf3 : 1; /* [10] */
|
||||
__IO uint32_t dterrf3 : 1; /* [11] */
|
||||
__IO uint32_t gf4 : 1; /* [12] */
|
||||
__IO uint32_t fdtf4 : 1; /* [13] */
|
||||
__IO uint32_t hdtf4 : 1; /* [14] */
|
||||
__IO uint32_t dterrf4 : 1; /* [15] */
|
||||
__IO uint32_t gf5 : 1; /* [16] */
|
||||
__IO uint32_t fdtf5 : 1; /* [17] */
|
||||
__IO uint32_t hdtf5 : 1; /* [18] */
|
||||
__IO uint32_t dterrf5 : 1; /* [19] */
|
||||
__IO uint32_t gf6 : 1; /* [20] */
|
||||
__IO uint32_t fdtf6 : 1; /* [21] */
|
||||
__IO uint32_t hdtf6 : 1; /* [22] */
|
||||
__IO uint32_t dterrf6 : 1; /* [23] */
|
||||
__IO uint32_t gf7 : 1; /* [24] */
|
||||
__IO uint32_t fdtf7 : 1; /* [25] */
|
||||
__IO uint32_t hdtf7 : 1; /* [26] */
|
||||
__IO uint32_t dterrf7 : 1; /* [27] */
|
||||
__IO uint32_t reserved1 : 4; /* [31:28] */
|
||||
} sts_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief dma clr register, offset:0x04
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t clr;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t gfc1 : 1; /* [0] */
|
||||
__IO uint32_t fdtfc1 : 1; /* [1] */
|
||||
__IO uint32_t hdtfc1 : 1; /* [2] */
|
||||
__IO uint32_t dterrfc1 : 1; /* [3] */
|
||||
__IO uint32_t gfc2 : 1; /* [4] */
|
||||
__IO uint32_t fdtfc2 : 1; /* [5] */
|
||||
__IO uint32_t hdtfc2 : 1; /* [6] */
|
||||
__IO uint32_t dterrfc2 : 1; /* [7] */
|
||||
__IO uint32_t gfc3 : 1; /* [8] */
|
||||
__IO uint32_t fdtfc3 : 1; /* [9] */
|
||||
__IO uint32_t hdtfc3 : 1; /* [10] */
|
||||
__IO uint32_t dterrfc3 : 1; /* [11] */
|
||||
__IO uint32_t gfc4 : 1; /* [12] */
|
||||
__IO uint32_t fdtfc4 : 1; /* [13] */
|
||||
__IO uint32_t hdtfc4 : 1; /* [14] */
|
||||
__IO uint32_t dterrfc4 : 1; /* [15] */
|
||||
__IO uint32_t gfc5 : 1; /* [16] */
|
||||
__IO uint32_t fdtfc5 : 1; /* [17] */
|
||||
__IO uint32_t hdtfc5 : 1; /* [18] */
|
||||
__IO uint32_t dterrfc5 : 1; /* [19] */
|
||||
__IO uint32_t gfc6 : 1; /* [20] */
|
||||
__IO uint32_t fdtfc6 : 1; /* [21] */
|
||||
__IO uint32_t hdtfc6 : 1; /* [22] */
|
||||
__IO uint32_t dterrfc6 : 1; /* [23] */
|
||||
__IO uint32_t gfc7 : 1; /* [24] */
|
||||
__IO uint32_t fdtfc7 : 1; /* [25] */
|
||||
__IO uint32_t hdtfc7 : 1; /* [26] */
|
||||
__IO uint32_t dterrfc7 : 1; /* [27] */
|
||||
__IO uint32_t reserved1 : 4; /* [31:28] */
|
||||
} clr_bit;
|
||||
};
|
||||
/**
|
||||
* @brief reserved, offset:0x08~0x9C
|
||||
*/
|
||||
__IO uint32_t reserved1[38];
|
||||
/**
|
||||
* @brief dma src_sel0 register, offset:0xA0
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t src_sel0;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t ch1_src : 8; /* [7:0] */
|
||||
__IO uint32_t ch2_src : 8; /* [15:8] */
|
||||
__IO uint32_t ch3_src : 8; /* [23:16] */
|
||||
__IO uint32_t ch4_src : 8; /* [31:24] */
|
||||
} src_sel0_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief dma src_sel1 register, offset:0xA4
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t src_sel1;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t ch5_src : 8; /* [7:0] */
|
||||
__IO uint32_t ch6_src : 8; /* [15:8] */
|
||||
__IO uint32_t ch7_src : 8; /* [23:16] */
|
||||
__IO uint32_t dma_flex_en : 1; /* [24] */
|
||||
__IO uint32_t reserved1 : 7; /* [31:25] */
|
||||
} src_sel1_bit;
|
||||
};
|
||||
} dma_type;
|
||||
|
||||
/**
|
||||
* @brief type define dma channel register all
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
/**
|
||||
* @brief dma ctrl register, offset:0x08+20*(x-1) x=1...7
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t ctrl;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t chen : 1; /* [0] */
|
||||
__IO uint32_t fdtien : 1; /* [1] */
|
||||
__IO uint32_t hdtien : 1; /* [2] */
|
||||
__IO uint32_t dterrien : 1; /* [3] */
|
||||
__IO uint32_t dtd : 1; /* [4] */
|
||||
__IO uint32_t lm : 1; /* [5] */
|
||||
__IO uint32_t pincm : 1; /* [6] */
|
||||
__IO uint32_t mincm : 1; /* [7] */
|
||||
__IO uint32_t pwidth : 2; /* [9:8] */
|
||||
__IO uint32_t mwidth : 2; /* [11:10] */
|
||||
__IO uint32_t chpl : 2; /* [13:12] */
|
||||
__IO uint32_t m2m : 1; /* [14] */
|
||||
__IO uint32_t reserved1 : 17;/* [31:15] */
|
||||
} ctrl_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief dma dtcnt register, offset:0x0C+20*(x-1) x=1...7
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t dtcnt;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t cnt : 16;/* [15:0] */
|
||||
__IO uint32_t reserved1 : 16;/* [31:16] */
|
||||
} dtcnt_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief dma cpba register, offset:0x10+20*(x-1) x=1...7
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t paddr;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t paddr : 32;/* [31:0] */
|
||||
} paddr_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief dma cmba register, offset:0x14+20*(x-1) x=1...7
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t maddr;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t maddr : 32;/* [31:0] */
|
||||
} maddr_bit;
|
||||
};
|
||||
} dma_channel_type;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#define DMA1 ((dma_type *) DMA1_BASE)
|
||||
#define DMA1_CHANNEL1 ((dma_channel_type *) DMA1_CHANNEL1_BASE)
|
||||
#define DMA1_CHANNEL2 ((dma_channel_type *) DMA1_CHANNEL2_BASE)
|
||||
#define DMA1_CHANNEL3 ((dma_channel_type *) DMA1_CHANNEL3_BASE)
|
||||
#define DMA1_CHANNEL4 ((dma_channel_type *) DMA1_CHANNEL4_BASE)
|
||||
#define DMA1_CHANNEL5 ((dma_channel_type *) DMA1_CHANNEL5_BASE)
|
||||
#define DMA1_CHANNEL6 ((dma_channel_type *) DMA1_CHANNEL6_BASE)
|
||||
#define DMA1_CHANNEL7 ((dma_channel_type *) DMA1_CHANNEL7_BASE)
|
||||
|
||||
#define DMA2 ((dma_type *) DMA2_BASE)
|
||||
#define DMA2_CHANNEL1 ((dma_channel_type *) DMA2_CHANNEL1_BASE)
|
||||
#define DMA2_CHANNEL2 ((dma_channel_type *) DMA2_CHANNEL2_BASE)
|
||||
#define DMA2_CHANNEL3 ((dma_channel_type *) DMA2_CHANNEL3_BASE)
|
||||
#define DMA2_CHANNEL4 ((dma_channel_type *) DMA2_CHANNEL4_BASE)
|
||||
#define DMA2_CHANNEL5 ((dma_channel_type *) DMA2_CHANNEL5_BASE)
|
||||
#define DMA2_CHANNEL6 ((dma_channel_type *) DMA2_CHANNEL6_BASE)
|
||||
#define DMA2_CHANNEL7 ((dma_channel_type *) DMA2_CHANNEL7_BASE)
|
||||
|
||||
/** @defgroup DMA_exported_functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
void dma_reset(dma_channel_type* dmax_channely);
|
||||
void dma_data_number_set(dma_channel_type* dmax_channely, uint16_t data_number);
|
||||
uint16_t dma_data_number_get(dma_channel_type* dmax_channely);
|
||||
void dma_interrupt_enable(dma_channel_type* dmax_channely, uint32_t dma_int, confirm_state new_state);
|
||||
void dma_channel_enable(dma_channel_type* dmax_channely, confirm_state new_state);
|
||||
void dma_flexible_config(dma_type* dma_x, uint8_t flex_channelx, dma_flexible_request_type flexible_request);
|
||||
flag_status dma_flag_get(uint32_t dmax_flag);
|
||||
flag_status dma_interrupt_flag_get(uint32_t dmax_flag);
|
||||
void dma_flag_clear(uint32_t dmax_flag);
|
||||
void dma_default_para_init(dma_init_type* dma_init_struct);
|
||||
void dma_init(dma_channel_type* dmax_channely, dma_init_type* dma_init_struct);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,232 @@
|
|||
/**
|
||||
**************************************************************************
|
||||
* @file at32f403a_407_exint.h
|
||||
* @brief at32f403a_407 exint header file
|
||||
**************************************************************************
|
||||
*
|
||||
* Copyright (c) 2025, Artery Technology, All rights reserved.
|
||||
*
|
||||
* The software Board Support Package (BSP) that is made available to
|
||||
* download from Artery official website is the copyrighted work of Artery.
|
||||
* Artery authorizes customers to use, copy, and distribute the BSP
|
||||
* software and its related documentation for the purpose of design and
|
||||
* development in conjunction with Artery microcontrollers. Use of the
|
||||
* software is governed by this copyright notice and the following disclaimer.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
|
||||
* GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
|
||||
* TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
|
||||
* STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
|
||||
* INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
|
||||
*
|
||||
**************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __AT32F403A_407_EXINT_H
|
||||
#define __AT32F403A_407_EXINT_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "at32f403a_407.h"
|
||||
|
||||
/** @addtogroup AT32F403A_407_periph_driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup EXINT
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup EXINT_lines
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define EXINT_LINE_NONE ((uint32_t)0x000000)
|
||||
#define EXINT_LINE_0 ((uint32_t)0x000001) /*!< external interrupt line 0 */
|
||||
#define EXINT_LINE_1 ((uint32_t)0x000002) /*!< external interrupt line 1 */
|
||||
#define EXINT_LINE_2 ((uint32_t)0x000004) /*!< external interrupt line 2 */
|
||||
#define EXINT_LINE_3 ((uint32_t)0x000008) /*!< external interrupt line 3 */
|
||||
#define EXINT_LINE_4 ((uint32_t)0x000010) /*!< external interrupt line 4 */
|
||||
#define EXINT_LINE_5 ((uint32_t)0x000020) /*!< external interrupt line 5 */
|
||||
#define EXINT_LINE_6 ((uint32_t)0x000040) /*!< external interrupt line 6 */
|
||||
#define EXINT_LINE_7 ((uint32_t)0x000080) /*!< external interrupt line 7 */
|
||||
#define EXINT_LINE_8 ((uint32_t)0x000100) /*!< external interrupt line 8 */
|
||||
#define EXINT_LINE_9 ((uint32_t)0x000200) /*!< external interrupt line 9 */
|
||||
#define EXINT_LINE_10 ((uint32_t)0x000400) /*!< external interrupt line 10 */
|
||||
#define EXINT_LINE_11 ((uint32_t)0x000800) /*!< external interrupt line 11 */
|
||||
#define EXINT_LINE_12 ((uint32_t)0x001000) /*!< external interrupt line 12 */
|
||||
#define EXINT_LINE_13 ((uint32_t)0x002000) /*!< external interrupt line 13 */
|
||||
#define EXINT_LINE_14 ((uint32_t)0x004000) /*!< external interrupt line 14 */
|
||||
#define EXINT_LINE_15 ((uint32_t)0x008000) /*!< external interrupt line 15 */
|
||||
#define EXINT_LINE_16 ((uint32_t)0x010000) /*!< external interrupt line 16 connected to the pvm output */
|
||||
#define EXINT_LINE_17 ((uint32_t)0x020000) /*!< external interrupt line 17 connected to the rtc alarm event */
|
||||
#define EXINT_LINE_18 ((uint32_t)0x040000) /*!< external interrupt line 18 connected to the usb device fs wakeup from suspend event */
|
||||
#define EXINT_LINE_19 ((uint32_t)0x080000) /*!< external interrupt line 19 connected to the comp1*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup EXINT_exported_types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief exint line mode type
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
EXINT_LINE_INTERRUPUT = 0x00, /*!< external interrupt line interrupt mode */
|
||||
EXINT_LINE_INTERRUPT = 0x00, /*!< same as EXINT_LINE_INTERRUPUT, fixed spelling error */
|
||||
EXINT_LINE_EVENT = 0x01 /*!< external interrupt line event mode */
|
||||
} exint_line_mode_type;
|
||||
|
||||
/**
|
||||
* @brief exint polarity configuration type
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
EXINT_TRIGGER_RISING_EDGE = 0x00, /*!< external interrupt line rising trigger mode */
|
||||
EXINT_TRIGGER_FALLING_EDGE = 0x01, /*!< external interrupt line falling trigger mode */
|
||||
EXINT_TRIGGER_BOTH_EDGE = 0x02 /*!< external interrupt line both rising and falling trigger mode */
|
||||
} exint_polarity_config_type;
|
||||
|
||||
/**
|
||||
* @brief exint init type
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
exint_line_mode_type line_mode; /*!< choose mode event or interrupt mode */
|
||||
uint32_t line_select; /*!< select the exint line, availiable for single line or multiple lines */
|
||||
exint_polarity_config_type line_polarity; /*!< select the tregger polarity, with rising edge, falling edge or both edge */
|
||||
confirm_state line_enable; /*!< enable or disable exint */
|
||||
} exint_init_type;
|
||||
|
||||
/**
|
||||
* @brief type define exint register all
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
|
||||
/**
|
||||
* @brief exint inten register, offset:0x00
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t inten;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t intenx : 20;/* [19:0] */
|
||||
__IO uint32_t reserved1 : 12;/* [31:20] */
|
||||
} inten_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief exint evten register, offset:0x04
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t evten;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t evtenx : 20;/* [19:0] */
|
||||
__IO uint32_t reserved1 : 12;/* [31:20] */
|
||||
} evten_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief exint polcfg1 register, offset:0x08
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t polcfg1;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t rpx : 20;/* [19:0] */
|
||||
__IO uint32_t reserved1 : 12;/* [31:20] */
|
||||
} polcfg1_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief exint polcfg2 register, offset:0x0C
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t polcfg2;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t fpx : 20;/* [19:0] */
|
||||
__IO uint32_t reserved1 : 12;/* [31:20] */
|
||||
} polcfg2_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief exint swtrg register, offset:0x10
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t swtrg;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t swtx : 20;/* [19:0] */
|
||||
__IO uint32_t reserved1 : 12;/* [31:20] */
|
||||
} swtrg_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief exint intsts register, offset:0x14
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t intsts;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t linex : 20;/* [19:0] */
|
||||
__IO uint32_t reserved1 : 12;/* [31:20] */
|
||||
} intsts_bit;
|
||||
};
|
||||
} exint_type;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#define EXINT ((exint_type *) EXINT_BASE)
|
||||
|
||||
/** @defgroup EXINT_exported_functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
void exint_reset(void);
|
||||
void exint_default_para_init(exint_init_type *exint_struct);
|
||||
void exint_init(exint_init_type *exint_struct);
|
||||
void exint_flag_clear(uint32_t exint_line);
|
||||
flag_status exint_flag_get(uint32_t exint_line);
|
||||
flag_status exint_interrupt_flag_get(uint32_t exint_line);
|
||||
void exint_software_interrupt_event_generate(uint32_t exint_line);
|
||||
void exint_interrupt_enable(uint32_t exint_line, confirm_state new_state);
|
||||
void exint_event_enable(uint32_t exint_line, confirm_state new_state);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,729 @@
|
|||
/**
|
||||
**************************************************************************
|
||||
* @file at32f403a_407_flash.h
|
||||
* @brief at32f403a_407 flash header file
|
||||
**************************************************************************
|
||||
*
|
||||
* Copyright (c) 2025, Artery Technology, All rights reserved.
|
||||
*
|
||||
* The software Board Support Package (BSP) that is made available to
|
||||
* download from Artery official website is the copyrighted work of Artery.
|
||||
* Artery authorizes customers to use, copy, and distribute the BSP
|
||||
* software and its related documentation for the purpose of design and
|
||||
* development in conjunction with Artery microcontrollers. Use of the
|
||||
* software is governed by this copyright notice and the following disclaimer.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
|
||||
* GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
|
||||
* TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
|
||||
* STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
|
||||
* INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
|
||||
*
|
||||
**************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __AT32F403A_407_FLASH_H
|
||||
#define __AT32F403A_407_FLASH_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "at32f403a_407.h"
|
||||
|
||||
|
||||
/** @addtogroup AT32F403A_407_periph_driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup FLASH
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup FLASH_unlock_keys
|
||||
* @brief flash unlock keys
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define FLASH_UNLOCK_KEY1 ((uint32_t)0x45670123) /*!< flash operation unlock order key1 */
|
||||
#define FLASH_UNLOCK_KEY2 ((uint32_t)0xCDEF89AB) /*!< flash operation unlock order key2 */
|
||||
#define FAP_RELIEVE_KEY ((uint16_t)0x00A5) /*!< flash fap relieve key val */
|
||||
#define SLIB_UNLOCK_KEY ((uint32_t)0xA35F6D24) /*!< flash slib operation unlock order key */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FLASH_bank_address
|
||||
* @brief flash bank address
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define FLASH_BANK1_START_ADDR ((uint32_t)0x08000000) /*!< flash start address of bank1 */
|
||||
#define FLASH_BANK1_END_ADDR ((uint32_t)0x0807FFFF) /*!< flash end address of bank1 */
|
||||
#define FLASH_BANK2_START_ADDR ((uint32_t)0x08080000) /*!< flash start address of bank2 */
|
||||
#define FLASH_BANK2_END_ADDR ((uint32_t)0x080FFFFF) /*!< flash end address of bank2 */
|
||||
#define FLASH_SPIM_START_ADDR ((uint32_t)0x08400000) /*!< flash start address of spim */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FLASH_flags
|
||||
* @brief flash flag
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define FLASH_OBF_FLAG FLASH_BANK1_OBF_FLAG /*!< flash operate busy flag */
|
||||
#define FLASH_ODF_FLAG FLASH_BANK1_ODF_FLAG /*!< flash operate done flag */
|
||||
#define FLASH_PRGMERR_FLAG FLASH_BANK1_PRGMERR_FLAG /*!< flash program error flag */
|
||||
#define FLASH_EPPERR_FLAG FLASH_BANK1_EPPERR_FLAG /*!< flash erase/program protection error flag */
|
||||
#define FLASH_BANK1_OBF_FLAG ((uint32_t)0x00000001) /*!< flash bank1 operate busy flag */
|
||||
#define FLASH_BANK1_ODF_FLAG ((uint32_t)0x00000020) /*!< flash bank1 operate done flag */
|
||||
#define FLASH_BANK1_PRGMERR_FLAG ((uint32_t)0x00000004) /*!< flash bank1 program error flag */
|
||||
#define FLASH_BANK1_EPPERR_FLAG ((uint32_t)0x00000010) /*!< flash bank1 erase/program protection error flag */
|
||||
#define FLASH_BANK2_OBF_FLAG ((uint32_t)0x10000001) /*!< flash bank2 operate busy flag */
|
||||
#define FLASH_BANK2_ODF_FLAG ((uint32_t)0x10000020) /*!< flash bank2 operate done flag */
|
||||
#define FLASH_BANK2_PRGMERR_FLAG ((uint32_t)0x10000004) /*!< flash bank2 program error flag */
|
||||
#define FLASH_BANK2_EPPERR_FLAG ((uint32_t)0x10000010) /*!< flash bank2 erase/program protection error flag */
|
||||
#define FLASH_SPIM_OBF_FLAG ((uint32_t)0x20000001) /*!< flash spim operate busy flag */
|
||||
#define FLASH_SPIM_ODF_FLAG ((uint32_t)0x20000020) /*!< flash spim operate done flag */
|
||||
#define FLASH_SPIM_PRGMERR_FLAG ((uint32_t)0x20000004) /*!< flash spim program error flag */
|
||||
#define FLASH_SPIM_EPPERR_FLAG ((uint32_t)0x20000010) /*!< flash spim erase/program protection error flag */
|
||||
#define FLASH_USDERR_FLAG ((uint32_t)0x40000001) /*!< flash user system data error flag */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FLASH_interrupts
|
||||
* @brief flash interrupts
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define FLASH_ERR_INT FLASH_BANK1_ERR_INT /*!< flash error interrupt */
|
||||
#define FLASH_ODF_INT FLASH_BANK1_ODF_INT /*!< flash operate done interrupt */
|
||||
#define FLASH_BANK1_ERR_INT ((uint32_t)0x00000001) /*!< flash bank1 error interrupt */
|
||||
#define FLASH_BANK1_ODF_INT ((uint32_t)0x00000002) /*!< flash bank1 operate done interrupt */
|
||||
#define FLASH_BANK2_ERR_INT ((uint32_t)0x00000004) /*!< flash bank2 error interrupt */
|
||||
#define FLASH_BANK2_ODF_INT ((uint32_t)0x00000008) /*!< flash bank2 operate done interrupt */
|
||||
#define FLASH_SPIM_ERR_INT ((uint32_t)0x00000010) /*!< flash spim error interrupt */
|
||||
#define FLASH_SPIM_ODF_INT ((uint32_t)0x00000020) /*!< flash spim operate done interrupt */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FLASH_slib_mask
|
||||
* @brief flash slib mask
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define FLASH_SLIB_START_SECTOR ((uint32_t)0x000007FF) /*!< flash slib start sector */
|
||||
#define FLASH_SLIB_DATA_START_SECTOR ((uint32_t)0x003FF800) /*!< flash slib d-bus area start sector */
|
||||
#define FLASH_SLIB_END_SECTOR ((uint32_t)0xFFC00000) /*!< flash slib end sector */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FLASH_user_system_data
|
||||
* @brief flash user system data
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define USD_WDT_ATO_DISABLE ((uint16_t)0x0001) /*!< wdt auto start disabled */
|
||||
#define USD_WDT_ATO_ENABLE ((uint16_t)0x0000) /*!< wdt auto start enabled */
|
||||
|
||||
#define USD_DEPSLP_NO_RST ((uint16_t)0x0002) /*!< no reset generated when entering in deepsleep */
|
||||
#define USD_DEPSLP_RST ((uint16_t)0x0000) /*!< reset generated when entering in deepsleep */
|
||||
|
||||
#define USD_STDBY_NO_RST ((uint16_t)0x0004) /*!< no reset generated when entering in standby */
|
||||
#define USD_STDBY_RST ((uint16_t)0x0000) /*!< reset generated when entering in standby */
|
||||
|
||||
#define FLASH_BOOT_FROM_BANK1 ((uint16_t)0x0008) /*!< boot from bank1 */
|
||||
#define FLASH_BOOT_FROM_BANK2 ((uint16_t)0x0000) /*!< boot from bank 2 or bank 1,depending on the activation of the bank */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FLASH_timeout_definition
|
||||
* @brief flash timeout definition
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define ERASE_TIMEOUT ((uint32_t)0x40000000) /*!< internal flash erase operation timeout */
|
||||
#define PROGRAMMING_TIMEOUT ((uint32_t)0x00100000) /*!< internal flash program operation timeout */
|
||||
#define SPIM_ERASE_TIMEOUT ((uint32_t)0xFFFFFFFF) /*!< spim erase operation timeout */
|
||||
#define SPIM_PROGRAMMING_TIMEOUT ((uint32_t)0x00100000) /*!< spim program operation timeout */
|
||||
#define OPERATION_TIMEOUT ((uint32_t)0x10000000) /*!< flash common operation timeout */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FLASH_exported_types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief flash status type
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
FLASH_OPERATE_BUSY = 0x00, /*!< flash status is operate busy */
|
||||
FLASH_PROGRAM_ERROR = 0x01, /*!< flash status is program error */
|
||||
FLASH_EPP_ERROR = 0x02, /*!< flash status is epp error */
|
||||
FLASH_OPERATE_DONE = 0x03, /*!< flash status is operate done */
|
||||
FLASH_OPERATE_TIMEOUT = 0x04 /*!< flash status is operate timeout */
|
||||
} flash_status_type;
|
||||
|
||||
/**
|
||||
* @brief flash spim model type
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
FLASH_SPIM_MODEL1 = 0x01, /*!< spim model 1 */
|
||||
FLASH_SPIM_MODEL2 = 0x02 /*!< spim model 2 */
|
||||
} flash_spim_model_type;
|
||||
|
||||
/**
|
||||
* @brief type define flash register all
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
/**
|
||||
* @brief flash psr register, offset:0x00
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t psr;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t reserved1 : 32; /* [31:0] */
|
||||
} psr_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief flash unlock register, offset:0x04
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t unlock;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t ukval : 32;/* [31:0] */
|
||||
} unlock_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief flash usd unlock register, offset:0x08
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t usd_unlock;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t usd_ukval : 32;/* [31:0] */
|
||||
} usd_unlock_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief flash sts register, offset:0x0C
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t sts;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t obf : 1; /* [0] */
|
||||
__IO uint32_t reserved1 : 1; /* [1] */
|
||||
__IO uint32_t prgmerr : 1; /* [2] */
|
||||
__IO uint32_t reserved2 : 1; /* [3] */
|
||||
__IO uint32_t epperr : 1; /* [4] */
|
||||
__IO uint32_t odf : 1; /* [5] */
|
||||
__IO uint32_t reserved3 : 26;/* [31:6] */
|
||||
} sts_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief flash ctrl register, offset:0x10
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t ctrl;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t fprgm : 1; /* [0] */
|
||||
__IO uint32_t secers : 1; /* [1] */
|
||||
__IO uint32_t bankers : 1; /* [2] */
|
||||
__IO uint32_t reserved1 : 1; /* [3] */
|
||||
__IO uint32_t usdprgm : 1; /* [4] */
|
||||
__IO uint32_t usders : 1; /* [5] */
|
||||
__IO uint32_t erstr : 1; /* [6] */
|
||||
__IO uint32_t oplk : 1; /* [7] */
|
||||
__IO uint32_t reserved2 : 1; /* [8] */
|
||||
__IO uint32_t usdulks : 1; /* [9] */
|
||||
__IO uint32_t errie : 1; /* [10] */
|
||||
__IO uint32_t reserved3 : 1; /* [11] */
|
||||
__IO uint32_t odfie : 1; /* [12] */
|
||||
__IO uint32_t reserved4 : 19;/* [31:13] */
|
||||
} ctrl_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief flash addr register, offset:0x14
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t addr;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t fa : 32;/* [31:0] */
|
||||
} addr_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief flash reserved1 register, offset:0x18
|
||||
*/
|
||||
__IO uint32_t reserved1;
|
||||
|
||||
/**
|
||||
* @brief flash usd register, offset:0x1C
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t usd;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t usderr : 1; /* [0] */
|
||||
__IO uint32_t fap : 1; /* [1] */
|
||||
__IO uint32_t wdt_ato_en : 1; /* [2] */
|
||||
__IO uint32_t depslp_rst : 1; /* [3] */
|
||||
__IO uint32_t stdby_rst : 1; /* [4] */
|
||||
__IO uint32_t btopt : 1; /* [5] */
|
||||
__IO uint32_t reserved1 : 4; /* [9:6] */
|
||||
__IO uint32_t user_d0 : 8; /* [17:10] */
|
||||
__IO uint32_t user_d1 : 8; /* [25:18] */
|
||||
__IO uint32_t reserved2 : 6; /* [31:26] */
|
||||
} usd_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief flash epps register, offset:0x20
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t epps;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t epps : 32;/* [31:0] */
|
||||
} epps_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief flash reserved2 register, offset:0x40~0x24
|
||||
*/
|
||||
__IO uint32_t reserved2[8];
|
||||
|
||||
/**
|
||||
* @brief flash unlock2 register, offset:0x44
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t unlock2;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t ukval : 32;/* [31:0] */
|
||||
} unlock2_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief flash reserved3 register, offset:0x48
|
||||
*/
|
||||
__IO uint32_t reserved3;
|
||||
|
||||
/**
|
||||
* @brief flash sts2 register, offset:0x4C
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t sts2;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t obf : 1; /* [0] */
|
||||
__IO uint32_t reserved1 : 1; /* [1] */
|
||||
__IO uint32_t prgmerr : 1; /* [2] */
|
||||
__IO uint32_t reserved2 : 1; /* [3] */
|
||||
__IO uint32_t epperr : 1; /* [4] */
|
||||
__IO uint32_t odf : 1; /* [5] */
|
||||
__IO uint32_t reserved3 : 26;/* [31:6] */
|
||||
} sts2_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief flash ctrl2 register, offset:0x50
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t ctrl2;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t fprgm : 1; /* [0] */
|
||||
__IO uint32_t secers : 1; /* [1] */
|
||||
__IO uint32_t bankers : 1; /* [2] */
|
||||
__IO uint32_t reserved1 : 3; /* [5:3] */
|
||||
__IO uint32_t erstr : 1; /* [6] */
|
||||
__IO uint32_t oplk : 1; /* [7] */
|
||||
__IO uint32_t reserved2 : 2; /* [9:8] */
|
||||
__IO uint32_t errie : 1; /* [10] */
|
||||
__IO uint32_t reserved3 : 1; /* [11] */
|
||||
__IO uint32_t odfie : 1; /* [12] */
|
||||
__IO uint32_t reserved4 : 19;/* [31:13] */
|
||||
} ctrl2_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief flash addr2 register, offset:0x54
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t addr2;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t fa : 32;/* [31:0] */
|
||||
} addr2_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief flash reserved4 register, offset:0x80~0x58
|
||||
*/
|
||||
__IO uint32_t reserved4[11];
|
||||
|
||||
/**
|
||||
* @brief flash unlock3 register, offset:0x84
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t unlock3;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t ukval : 32;/* [31:0] */
|
||||
} unlock3_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief flash select register, offset:0x88
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t select;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t select : 32;/* [31:0] */
|
||||
} select_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief flash sts3 register, offset:0x8C
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t sts3;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t obf : 1; /* [0] */
|
||||
__IO uint32_t reserved1 : 1; /* [1] */
|
||||
__IO uint32_t prgmerr : 1; /* [2] */
|
||||
__IO uint32_t reserved2 : 1; /* [3] */
|
||||
__IO uint32_t epperr : 1; /* [4] */
|
||||
__IO uint32_t odf : 1; /* [5] */
|
||||
__IO uint32_t reserved3 : 26;/* [31:6] */
|
||||
} sts3_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief flash ctrl3 register, offset:0x90
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t ctrl3;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t fprgm : 1; /* [0] */
|
||||
__IO uint32_t secers : 1; /* [1] */
|
||||
__IO uint32_t chpers : 1; /* [2] */
|
||||
__IO uint32_t reserved1 : 3; /* [5:3] */
|
||||
__IO uint32_t erstr : 1; /* [6] */
|
||||
__IO uint32_t oplk : 1; /* [7] */
|
||||
__IO uint32_t reserved2 : 2; /* [9:8] */
|
||||
__IO uint32_t errie : 1; /* [10] */
|
||||
__IO uint32_t reserved3 : 1; /* [11] */
|
||||
__IO uint32_t odfie : 1; /* [12] */
|
||||
__IO uint32_t reserved4 : 19;/* [31:13] */
|
||||
} ctrl3_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief flash addr3 register, offset:0x94
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t addr3;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t fa : 32;/* [31:0] */
|
||||
} addr3_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief flash da register, offset:0x98
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t da;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t fda : 32;/* [31:0] */
|
||||
} da_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief flash reserved5 register, offset:0xC8~0x9C
|
||||
*/
|
||||
__IO uint32_t reserved5[12];
|
||||
|
||||
/**
|
||||
* @brief flash slib_sts0 register, offset:0xCC
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t slib_sts0;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t reserved1 : 3; /* [2:0] */
|
||||
__IO uint32_t slib_enf : 1; /* [3] */
|
||||
__IO uint32_t reserved2 : 28;/* [31:4] */
|
||||
} slib_sts0_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief flash slib_sts1 register, offset:0xD0
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t slib_sts1;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t slib_ss : 11;/* [10:0] */
|
||||
__IO uint32_t slib_dat_ss : 11;/* [21:11] */
|
||||
__IO uint32_t slib_es : 10;/* [31:22] */
|
||||
} slib_sts1_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief flash slib_pwd_clr register, offset:0xD4
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t slib_pwd_clr;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t slib_pclr_val : 32;/* [31:0] */
|
||||
} slib_pwd_clr_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief flash slib_misc_sts register, offset:0xD8
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t slib_misc_sts;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t slib_pwd_err : 1; /* [0] */
|
||||
__IO uint32_t slib_pwd_ok : 1; /* [1] */
|
||||
__IO uint32_t slib_ulkf : 1; /* [2] */
|
||||
__IO uint32_t reserved1 : 13;/* [15:3] */
|
||||
__IO uint32_t slib_rcnt : 9; /* [24:16] */
|
||||
__IO uint32_t reserved2 : 7; /* [31:25] */
|
||||
} slib_misc_sts_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief flash slib_set_pwd register, offset:0xDC
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t slib_set_pwd;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t slib_pset_val : 32;/* [31:0] */
|
||||
} slib_set_pwd_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief flash slib_set_range register, offset:0xE0
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t slib_set_range;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t slib_ss_set : 11;/* [10:0] */
|
||||
__IO uint32_t slib_dss_set : 11;/* [21:11] */
|
||||
__IO uint32_t slib_es_set : 10;/* [31:22] */
|
||||
} slib_set_range_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief flash reserved6 register, offset:0xEC~0xE4
|
||||
*/
|
||||
__IO uint32_t reserved6[3];
|
||||
|
||||
/**
|
||||
* @brief flash slib_unlock register, offset:0xF0
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t slib_unlock;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t slib_ukval : 32;/* [31:0] */
|
||||
} slib_unlock_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief flash crc_ctrl register, offset:0xF4
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t crc_ctrl;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t crc_ss : 12;/* [11:0] */
|
||||
__IO uint32_t crc_sn : 12;/* [23:12] */
|
||||
__IO uint32_t reserved1 : 7; /* [30:24] */
|
||||
__IO uint32_t crc_strt : 1; /* [31] */
|
||||
} crc_ctrl_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief flash crc_chkr register, offset:0xF8
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t crc_chkr;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t crc_chkr : 32;/* [31:0] */
|
||||
} crc_chkr_bit;
|
||||
};
|
||||
|
||||
} flash_type;
|
||||
|
||||
/**
|
||||
* @brief user system data
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
__IO uint16_t fap;
|
||||
__IO uint16_t ssb;
|
||||
__IO uint16_t data0;
|
||||
__IO uint16_t data1;
|
||||
__IO uint16_t epp0;
|
||||
__IO uint16_t epp1;
|
||||
__IO uint16_t epp2;
|
||||
__IO uint16_t epp3;
|
||||
__IO uint16_t eopb0;
|
||||
__IO uint16_t reserved;
|
||||
__IO uint16_t data2;
|
||||
__IO uint16_t data3;
|
||||
__IO uint16_t data4;
|
||||
__IO uint16_t data5;
|
||||
__IO uint16_t data6;
|
||||
__IO uint16_t data7;
|
||||
__IO uint16_t ext_flash_key[8];
|
||||
} usd_type;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#define FLASH ((flash_type *) FLASH_REG_BASE)
|
||||
#define USD ((usd_type *) USD_BASE)
|
||||
|
||||
/** @defgroup FLASH_exported_functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
flag_status flash_flag_get(uint32_t flash_flag);
|
||||
void flash_flag_clear(uint32_t flash_flag);
|
||||
flash_status_type flash_operation_status_get(void);
|
||||
flash_status_type flash_bank1_operation_status_get(void);
|
||||
flash_status_type flash_bank2_operation_status_get(void);
|
||||
flash_status_type flash_spim_operation_status_get(void);
|
||||
flash_status_type flash_operation_wait_for(uint32_t time_out);
|
||||
flash_status_type flash_bank1_operation_wait_for(uint32_t time_out);
|
||||
flash_status_type flash_bank2_operation_wait_for(uint32_t time_out);
|
||||
flash_status_type flash_spim_operation_wait_for(uint32_t time_out);
|
||||
void flash_unlock(void);
|
||||
void flash_bank1_unlock(void);
|
||||
void flash_bank2_unlock(void);
|
||||
void flash_spim_unlock(void);
|
||||
void flash_lock(void);
|
||||
void flash_bank1_lock(void);
|
||||
void flash_bank2_lock(void);
|
||||
void flash_spim_lock(void);
|
||||
flash_status_type flash_sector_erase(uint32_t sector_address);
|
||||
flash_status_type flash_internal_all_erase(void);
|
||||
flash_status_type flash_bank1_erase(void);
|
||||
flash_status_type flash_bank2_erase(void);
|
||||
flash_status_type flash_spim_all_erase(void);
|
||||
flash_status_type flash_user_system_data_erase(void);
|
||||
flash_status_type flash_word_program(uint32_t address, uint32_t data);
|
||||
flash_status_type flash_halfword_program(uint32_t address, uint16_t data);
|
||||
flash_status_type flash_byte_program(uint32_t address, uint8_t data);
|
||||
flash_status_type flash_user_system_data_program(uint32_t address, uint8_t data);
|
||||
flash_status_type flash_epp_set(uint32_t *sector_bits);
|
||||
void flash_epp_status_get(uint32_t *sector_bits);
|
||||
flash_status_type flash_fap_enable(confirm_state new_state);
|
||||
flag_status flash_fap_status_get(void);
|
||||
flash_status_type flash_ssb_set(uint8_t usd_ssb);
|
||||
uint8_t flash_ssb_status_get(void);
|
||||
void flash_interrupt_enable(uint32_t flash_int, confirm_state new_state);
|
||||
void flash_spim_model_select(flash_spim_model_type mode);
|
||||
void flash_spim_encryption_range_set(uint32_t decode_address);
|
||||
void flash_spim_dummy_read(void);
|
||||
flash_status_type flash_spim_mass_program(uint32_t address, uint8_t *buf, uint32_t cnt);
|
||||
flash_status_type flash_slib_enable(uint32_t pwd, uint16_t start_sector, uint16_t data_start_sector, uint16_t end_sector);
|
||||
error_status flash_slib_disable(uint32_t pwd);
|
||||
uint32_t flash_slib_remaining_count_get(void);
|
||||
flag_status flash_slib_state_get(void);
|
||||
uint16_t flash_slib_start_sector_get(void);
|
||||
uint16_t flash_slib_datastart_sector_get(void);
|
||||
uint16_t flash_slib_end_sector_get(void);
|
||||
uint32_t flash_crc_calibrate(uint32_t start_sector, uint32_t sector_cnt);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,941 @@
|
|||
/**
|
||||
**************************************************************************
|
||||
* @file at32f403a_407_gpio.h
|
||||
* @brief at32f403a_407 gpio header file
|
||||
**************************************************************************
|
||||
*
|
||||
* Copyright (c) 2025, Artery Technology, All rights reserved.
|
||||
*
|
||||
* The software Board Support Package (BSP) that is made available to
|
||||
* download from Artery official website is the copyrighted work of Artery.
|
||||
* Artery authorizes customers to use, copy, and distribute the BSP
|
||||
* software and its related documentation for the purpose of design and
|
||||
* development in conjunction with Artery microcontrollers. Use of the
|
||||
* software is governed by this copyright notice and the following disclaimer.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
|
||||
* GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
|
||||
* TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
|
||||
* STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
|
||||
* INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
|
||||
*
|
||||
**************************************************************************
|
||||
*/
|
||||
|
||||
/* define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __AT32F403A_407_GPIO_H
|
||||
#define __AT32F403A_407_GPIO_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
|
||||
/* includes ------------------------------------------------------------------*/
|
||||
#include "at32f403a_407.h"
|
||||
|
||||
/** @addtogroup AT32F403A_407_periph_driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup GPIO
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup GPIO_pins_number_definition
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define GPIO_PINS_0 0x0001 /*!< gpio pins number 0 */
|
||||
#define GPIO_PINS_1 0x0002 /*!< gpio pins number 1 */
|
||||
#define GPIO_PINS_2 0x0004 /*!< gpio pins number 2 */
|
||||
#define GPIO_PINS_3 0x0008 /*!< gpio pins number 3 */
|
||||
#define GPIO_PINS_4 0x0010 /*!< gpio pins number 4 */
|
||||
#define GPIO_PINS_5 0x0020 /*!< gpio pins number 5 */
|
||||
#define GPIO_PINS_6 0x0040 /*!< gpio pins number 6 */
|
||||
#define GPIO_PINS_7 0x0080 /*!< gpio pins number 7 */
|
||||
#define GPIO_PINS_8 0x0100 /*!< gpio pins number 8 */
|
||||
#define GPIO_PINS_9 0x0200 /*!< gpio pins number 9 */
|
||||
#define GPIO_PINS_10 0x0400 /*!< gpio pins number 10 */
|
||||
#define GPIO_PINS_11 0x0800 /*!< gpio pins number 11 */
|
||||
#define GPIO_PINS_12 0x1000 /*!< gpio pins number 12 */
|
||||
#define GPIO_PINS_13 0x2000 /*!< gpio pins number 13 */
|
||||
#define GPIO_PINS_14 0x4000 /*!< gpio pins number 14 */
|
||||
#define GPIO_PINS_15 0x8000 /*!< gpio pins number 15 */
|
||||
#define GPIO_PINS_ALL 0xFFFF /*!< gpio all pins */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#define IOMUX_MAKE_VALUE(reg_offset, bit_addr ,bit_num, bit_val) \
|
||||
(uint32_t)(((reg_offset) << 24) | ((bit_addr) << 16) | ((bit_num) << 8) | (bit_val))
|
||||
|
||||
/** @defgroup IOMUX_map_definition
|
||||
* @brief iomux map definitions
|
||||
* @{
|
||||
*/
|
||||
|
||||
#if defined (AT32F403Axx)
|
||||
#define SPI1_MUX_01 SPI1_GMUX_0001 /*!< spi1_cs/i2s1_ws(pa15), spi1_sck/i2s1_ck(pb3), spi1_miso(pb4), spi1_mosi/i2s1_sd(pb5), i2s1_mck(pb0) */
|
||||
#define SPI1_MUX_10 SPI1_GMUX_0010 /*!< spi1_cs/i2s1_ws(pa4), spi1_sck/i2s1_ck(pa5), spi1_miso(pa6), spi1_mosi/i2s1_sd(pa7), i2s1_mck(pb6) */
|
||||
#define SPI1_MUX_11 SPI1_GMUX_0011 /*!< spi1_cs/i2s1_ws(pa15), spi1_sck/i2s1_ck(pb3), spi1_miso(pb4), spi1_mosi/i2s1_sd(pb5), i2s1_mck(pb6) */
|
||||
#define I2C1_MUX I2C1_GMUX_0001 /*!< i2c1_scl(pb8), i2c1_sda(pb9) */
|
||||
#define USART1_MUX USART1_GMUX_0001 /*!< usart1_tx(pb6), usart1_rx(pb7) */
|
||||
#define USART2_MUX USART2_GMUX_0001 /*!< usart2_tx(pd5), usart2_rx(pd6), usart2_ck(pd7), usart2_cts(pd3), usart2_rts(pd4) */
|
||||
#define USART3_MUX_01 USART3_GMUX_0001 /*!< usart3_tx(pc10), usart3_rx(pc11), usart3_ck(pc12), usart3_cts(pb13), usart3_rts(pb14) */
|
||||
#define USART3_MUX_11 USART3_GMUX_0011 /*!< usart3_tx(pd8), usart3_rx(pd9), usart3_ck(pd10), usart3_cts(pd11), usart3_rts(pd12) */
|
||||
#define TMR1_MUX_01 TMR1_GMUX_0001 /*!< tmr1_ext(pa12), tmr1_ch1(pa8), tmr1_ch2(pa9), tmr1_ch3(pa10), tmr1_ch4(pa11), tmr1_brkin(pa6), tmr1_ch1c(pa7), tmr1_ch2c(pb0), tmr1_ch3c(pb1) */
|
||||
#define TMR1_MUX_11 TMR1_GMUX_0011 /*!< tmr1_ext(pe7), tmr1_ch1(pe9), tmr1_ch2(pe11), tmr1_ch3(pe13), tmr1_ch4(pe14), tmr1_brkin(pe15), tmr1_ch1c(pe8), tmr1_ch2c(pe10), tmr1_ch3c(pe12) */
|
||||
#define TMR2_MUX_01 TMR2_GMUX_01 /*!< tmr2_ch1_ext(pa15), tmr2_ch2(pb3), tmr2_ch3(pa2), tmr2_ch4(pa3) */
|
||||
#define TMR2_MUX_10 TMR2_GMUX_10 /*!< tmr2_ch1_ext(pa0), tmr2_ch2(pa1), tmr2_ch3(pb10), tmr2_ch4(pb11) */
|
||||
#define TMR2_MUX_11 TMR2_GMUX_11 /*!< tmr2_ch1_ext(pa15), tmr2_ch2(pb3), tmr2_ch3(pb10), tmr2_ch4(pb11) */
|
||||
#define TMR3_MUX_10 TMR3_GMUX_0010 /*!< tmr3_ch1(pb4), tmr3_ch2(pb5), tmr3_ch3(pb0), tmr3_ch4(pb1) */
|
||||
#define TMR3_MUX_11 TMR3_GMUX_0011 /*!< tmr3_ch1(pc6), tmr3_ch2(pc7), tmr3_ch3(pc8), tmr3_ch4(pc9) */
|
||||
#define TMR4_MUX TMR4_GMUX_0001 /*!< tmr4_ch1(pd12), tmr4_ch2(pd13), tmr4_ch3(pd14), tmr4_ch4(pd15) */
|
||||
#define CAN_MUX_10 CAN1_GMUX_0010 /*!< can_rx(pb8), can_tx(pb9) */
|
||||
#define CAN_MUX_11 CAN1_GMUX_0011 /*!< can_rx(pd0), can_tx(pd1) */
|
||||
#define PD01_MUX PD01_GMUX /*!< pd0/pd1 mapping on osc_in/osc_out */
|
||||
#define TMR5CH4_MUX TMR5CH4_GMUX /*!< lick connected to tmr5_ch4 input capture for calibration */
|
||||
#define ADC1_ETP_MUX ADC1_ETP_GMUX /*!< adc1 external trigger preempted conversion muxing */
|
||||
#define ADC1_ETO_MUX ADC1_ETO_GMUX /*!< adc1 external trigger ordinary conversion muxing */
|
||||
#define ADC2_ETP_MUX ADC2_ETP_GMUX /*!< adc2 external trigger preempted conversion muxing */
|
||||
#define ADC2_ETO_MUX ADC2_ETO_GMUX /*!< adc2 external trigger ordinary conversion muxing */
|
||||
#define SWJTAG_MUX_001 SWJTAG_GMUX_001 /*!< full swj enabled (jtag-dp + sw-dp) but without jtrst */
|
||||
#define SWJTAG_MUX_010 SWJTAG_GMUX_010 /*!< jtag-dp disabled and sw-dp enabled */
|
||||
#define SWJTAG_MUX_100 SWJTAG_GMUX_100 /*!< full swj disabled (jtag-dp + sw-dp) */
|
||||
#endif
|
||||
#if defined (AT32F407xx)
|
||||
#define SPI1_MUX_01 SPI1_GMUX_0001 /*!< spi1_cs/i2s1_ws(pa15), spi1_sck/i2s1_ck(pb3), spi1_miso(pb4), spi1_mosi/i2s1_sd(pb5), i2s1_mck(pb0) */
|
||||
#define SPI1_MUX_10 SPI1_GMUX_0010 /*!< spi1_cs/i2s1_ws(pa4), spi1_sck/i2s1_ck(pa5), spi1_miso(pa6), spi1_mosi/i2s1_sd(pa7), i2s1_mck(pb6) */
|
||||
#define SPI1_MUX_11 SPI1_GMUX_0011 /*!< spi1_cs/i2s1_ws(pa15), spi1_sck/i2s1_ck(pb3), spi1_miso(pb4), spi1_mosi/i2s1_sd(pb5), i2s1_mck(pb6) */
|
||||
#define I2C1_MUX I2C1_GMUX_0001 /*!< i2c1_scl(pb8), i2c1_sda(pb9) */
|
||||
#define USART1_MUX USART1_GMUX_0001 /*!< usart1_tx(pb6), usart1_rx(pb7) */
|
||||
#define USART2_MUX USART2_GMUX_0001 /*!< usart2_tx(pd5), usart2_rx(pd6), usart2_ck(pd7), usart2_cts(pd3), usart2_rts(pd4) */
|
||||
#define USART3_MUX_01 USART3_GMUX_0001 /*!< usart3_tx(pc10), usart3_rx(pc11), usart3_ck(pc12), usart3_cts(pb13), usart3_rts(pb14) */
|
||||
#define USART3_MUX_11 USART3_GMUX_0011 /*!< usart3_tx(pd8), usart3_rx(pd9), usart3_ck(pd10), usart3_cts(pd11), usart3_rts(pd12) */
|
||||
#define TMR1_MUX_01 TMR1_GMUX_0001 /*!< tmr1_ext(pa12), tmr1_ch1(pa8), tmr1_ch2(pa9), tmr1_ch3(pa10), tmr1_ch4(pa11), tmr1_brkin(pa6), tmr1_ch1c(pa7), tmr1_ch2c(pb0), tmr1_ch3c(pb1) */
|
||||
#define TMR1_MUX_11 TMR1_GMUX_0011 /*!< tmr1_ext(pe7), tmr1_ch1(pe9), tmr1_ch2(pe11), tmr1_ch3(pe13), tmr1_ch4(pe14), tmr1_brkin(pe15), tmr1_ch1c(pe8), tmr1_ch2c(pe10), tmr1_ch3c(pe12) */
|
||||
#define TMR2_MUX_01 TMR2_GMUX_01 /*!< tmr2_ch1_ext(pa15), tmr2_ch2(pb3), tmr2_ch3(pa2), tmr2_ch4(pa3) */
|
||||
#define TMR2_MUX_10 TMR2_GMUX_10 /*!< tmr2_ch1_ext(pa0), tmr2_ch2(pa1), tmr2_ch3(pb10), tmr2_ch4(pb11) */
|
||||
#define TMR2_MUX_11 TMR2_GMUX_11 /*!< tmr2_ch1_ext(pa15), tmr2_ch2(pb3), tmr2_ch3(pb10), tmr2_ch4(pb11) */
|
||||
#define TMR3_MUX_10 TMR3_GMUX_0010 /*!< tmr3_ch1(pb4), tmr3_ch2(pb5), tmr3_ch3(pb0), tmr3_ch4(pb1) */
|
||||
#define TMR3_MUX_11 TMR3_GMUX_0011 /*!< tmr3_ch1(pc6), tmr3_ch2(pc7), tmr3_ch3(pc8), tmr3_ch4(pc9) */
|
||||
#define TMR4_MUX TMR4_GMUX_0001 /*!< tmr4_ch1(pd12), tmr4_ch2(pd13), tmr4_ch3(pd14), tmr4_ch4(pd15) */
|
||||
#define CAN_MUX_00 CAN1_GMUX_0000 /*!< can_rx(pa11), can_tx(pa12) */
|
||||
#define CAN_MUX_10 CAN1_GMUX_0010 /*!< can_rx(pb8), can_tx(pb9) */
|
||||
#define CAN_MUX_11 CAN1_GMUX_0011 /*!< can_rx(pd0), can_tx(pd1) */
|
||||
#define PD01_MUX PD01_GMUX /*!< pd0/pd1 mapping on osc_in/osc_out */
|
||||
#define TMR5CH4_MUX TMR5CH4_GMUX /*!< lick connected to tmr5_ch4 input capture for calibration */
|
||||
#define ADC1_ETP_MUX ADC1_ETP_GMUX /*!< adc1 external trigger preempted conversion muxing */
|
||||
#define ADC1_ETO_MUX ADC1_ETO_GMUX /*!< adc1 external trigger ordinary conversion muxing */
|
||||
#define ADC2_ETP_MUX ADC2_ETP_GMUX /*!< adc2 external trigger preempted conversion muxing */
|
||||
#define ADC2_ETO_MUX ADC2_ETO_GMUX /*!< adc2 external trigger ordinary conversion muxing */
|
||||
#define EMAC_MUX EMAC_GMUX_01 /*!< rx_dv/crs_dv(pd8), rxd0(pd9), rxd1(pd10), rxd2(pd11), rxd3(pd12) */
|
||||
#define CAN2_MUX CAN2_GMUX_0001 /*!< can2_rx(pb5), can2_tx(pb6) */
|
||||
#define MII_RMII_SEL_MUX MII_RMII_SEL_GMUX /*!< mii or rmii selection */
|
||||
#define SWJTAG_MUX_001 SWJTAG_GMUX_001 /*!< full swj enabled (jtag-dp + sw-dp) but without jtrst */
|
||||
#define SWJTAG_MUX_010 SWJTAG_GMUX_010 /*!< jtag-dp disabled and sw-dp enabled */
|
||||
#define SWJTAG_MUX_100 SWJTAG_GMUX_100 /*!< full swj disabled (jtag-dp + sw-dp) */
|
||||
#define SPI3_MUX SPI3_GMUX_0001 /*!< spi3_cs/i2s3_ws(pa4), spi3_sck/i2s3_ck(pc10), spi3_miso(pc11), spi3_mosi/i2s3_sd(pc12), i2s3_mck(pc7) */
|
||||
#define TMR2ITR1_MUX TMR2ITR1_GMAP_10 /*!< tmr2 internal trigger 1 mux remapping */
|
||||
#define PTP_PPS_MUX PTP_PPS_GMUX /*!< ethernet ptp pps mux function remapping */
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup IOMUX_map2_definition
|
||||
* @brief iomux map2 definitions
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define TMR9_MUX TMR9_GMUX /*!< tmr9_ch1(pe5), tmr9_ch2(pe6) */
|
||||
#define XMC_NADV_MUX XMC_NADV_GMUX /*!< xmc_nadv not used */
|
||||
#define SPI4_MUX SPI4_GMUX_0001 /*!< spi4_cs/i2s4_ws(pe12), spi4_sck/i2s4_ck(pe11), spi4_miso(pe13), spi4_mosi/i2s4_sd(pe14), i2s4_mck(pc8) */
|
||||
#define I2C3_MUX I2C3_GMUX_0001 /*!< i2c3_scl(pa8), i2c3_sda(pb4) */
|
||||
#define SDIO2_MUX01 SDIO2_GMUX_0001 /*!< sdio2_ck(pc4), sdio2_cmd(pc5), sdio2_d0(pa4), sdio2_d1(pa5), sdio2_d2(pa6), sdio2_d3(pa7) */
|
||||
#define SDIO2_MUX10 SDIO2_GMUX_0010 /*!< sdio2_ck(pa2), sdio2_cmd(pa3), sdio2_d0(pc0), sdio2_d1(pc1), sdio2_d2(pc2), sdio2_d3(pc3), sdio2_d4(pa4), sdio2_d5(pa5), sdio2_d6(pa6), sdio2_d7(pa7) */
|
||||
#define SDIO2_MUX11 SDIO2_GMUX_0011 /*!< sdio2_ck(pa2), sdio2_cmd(pa3), sdio2_d0(pa4), sdio2_d1(pa5), sdio2_d2(pa6), sdio2_d3(pa7) */
|
||||
#define EXT_SPIM_EN_MUX EXT_SPIM_GMUX_1000 /*!< enable external spi-flash interface */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup IOMUX_map3_definition
|
||||
* @brief iomux map3 definitions
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define TMR9_GMUX IOMUX_MAKE_VALUE(0x20, 0, 4, 0x01) /*!< tmr9_ch1(pe5), tmr9_ch2(pe6) */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup IOMUX_map4_definition
|
||||
* @brief iomux map4 definitions
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define TMR1_GMUX_0001 IOMUX_MAKE_VALUE(0x24, 0, 4, 0x01) /*!< tmr1_ext(pa12), tmr1_ch1(pa8), tmr1_ch2(pa9), tmr1_ch3(pa10), tmr1_ch4(pa11), tmr1_brkin(pa6), tmr1_ch1c(pa7), tmr1_ch2c(pb0), tmr1_ch3c(pb1) */
|
||||
#define TMR1_GMUX_0011 IOMUX_MAKE_VALUE(0x24, 0, 4, 0x03) /*!< tmr1_ext(pe7), tmr1_ch1(pe9), tmr1_ch2(pe11), tmr1_ch3(pe13), tmr1_ch4(pe14), tmr1_brkin(pe15), tmr1_ch1c(pe8), tmr1_ch2c(pe10), tmr1_ch3c(pe12) */
|
||||
#define TMR2_GMUX_01 IOMUX_MAKE_VALUE(0x24, 4, 2, 0x01) /*!< tmr2_ch1_ext(pa15), tmr2_ch2(pb3), tmr2_ch3(pa2), tmr2_ch4(pa3) */
|
||||
#define TMR2_GMUX_10 IOMUX_MAKE_VALUE(0x24, 4, 2, 0x02) /*!< tmr2_ch1_ext(pa0), tmr2_ch2(pa1), tmr2_ch3(pb10), tmr2_ch4(pb11) */
|
||||
#define TMR2_GMUX_11 IOMUX_MAKE_VALUE(0x24, 4, 2, 0x03) /*!< tmr2_ch1_ext(pa15), tmr2_ch2(pb3), tmr2_ch3(pb10), tmr2_ch4(pb11) */
|
||||
#define TMR2ITR1_GMUX_10 IOMUX_MAKE_VALUE(0x24, 6, 2, 0x02) /*!< ethernet ptp as input to tmr2_int.1 */
|
||||
#define TMR2ITR1_GMUX_11 IOMUX_MAKE_VALUE(0x24, 6, 2, 0x03) /*!< usbdev sof as input to tmr2_int.1 */
|
||||
#define TMR3_GMUX_0010 IOMUX_MAKE_VALUE(0x24, 8, 4, 0x02) /*!< tmr3_ch1(pb4), tmr3_ch2(pb5), tmr3_ch3(pb0), tmr3_ch4(pb1) */
|
||||
#define TMR3_GMUX_0011 IOMUX_MAKE_VALUE(0x24, 8, 4, 0x03) /*!< tmr3_ch1(pc6), tmr3_ch2(pc7), tmr3_ch3(pc8), tmr3_ch4(pc9) */
|
||||
#define TMR4_GMUX_0001 IOMUX_MAKE_VALUE(0x24, 12, 4, 0x01) /*!< tmr4_ch1(pd12), tmr4_ch2(pd13), tmr4_ch3(pd14), tmr4_ch4(pd15) */
|
||||
#define TMR5CH4_GMUX IOMUX_MAKE_VALUE(0x24, 19, 1, 0x01) /*!< lick connected to tmr5_ch4 input capture for calibration */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup IOMUX_map5_definition
|
||||
* @brief iomux map5 definitions
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define UART5_GMUX_0001 IOMUX_MAKE_VALUE(0x28, 0, 4, 0x01) /*!< uart5_tx(pb9), uart5_rx(pb8) */
|
||||
#define I2C1_GMUX_0001 IOMUX_MAKE_VALUE(0x28, 4, 4, 0x01) /*!< i2c1_scl(pb8), i2c1_sda(pb9) */
|
||||
#define I2C3_GMUX_0001 IOMUX_MAKE_VALUE(0x28, 12, 4, 0x01) /*!< i2c3_scl(pa8), i2c3_sda(pb4) */
|
||||
#define SPI1_GMUX_0001 IOMUX_MAKE_VALUE(0x28, 16, 4, 0x01) /*!< spi1_cs/i2s1_ws(pa15), spi1_sck/i2s1_ck(pb3), spi1_miso(pb4), spi1_mosi/i2s1_sd(pb5), i2s1_mck(pb0) */
|
||||
#define SPI1_GMUX_0010 IOMUX_MAKE_VALUE(0x28, 16, 4, 0x02) /*!< spi1_cs/i2s1_ws(pa4), spi1_sck/i2s1_ck(pa5), spi1_miso(pa6), spi1_mosi/i2s1_sd(pa7), i2s1_mck(pb6) */
|
||||
#define SPI1_GMUX_0011 IOMUX_MAKE_VALUE(0x28, 16, 4, 0x03) /*!< spi1_cs/i2s1_ws(pa15), spi1_sck/i2s1_ck(pb3), spi1_miso(pb4), spi1_mosi/i2s1_sd(pb5), i2s1_mck(pb6) */
|
||||
#define SPI2_GMUX_0001 IOMUX_MAKE_VALUE(0x28, 20, 4, 0x01) /*!< i2s2_mck(pa3) */
|
||||
#define SPI2_GMUX_0010 IOMUX_MAKE_VALUE(0x28, 20, 4, 0x02) /*!< i2s2_mck(pa6) */
|
||||
#define SPI3_GMUX_0001 IOMUX_MAKE_VALUE(0x28, 24, 4, 0x01) /*!< spi3_cs/i2s3_ws(pa4), spi3_sck/i2s3_ck(pc10), spi3_miso(pc11), spi3_mosi/i2s3_sd(pc12), i2s3_mck(pc7) */
|
||||
#define SPI3_GMUX_0010 IOMUX_MAKE_VALUE(0x28, 24, 4, 0x02) /*!< spi3_cs/i2s3_ws(pa15), spi3_sck/i2s3_ck(pb3), spi3_miso(pb4), spi3_mosi/i2s3_sd(pb5), i2s3_mck(pb10) */
|
||||
#define SPI3_GMUX_0011 IOMUX_MAKE_VALUE(0x28, 24, 4, 0x03) /*!< spi3_cs/i2s3_ws(pa4), spi3_sck/i2s3_ck(pc10), spi3_miso(pc11), spi3_mosi/i2s3_sd(pc12), i2s3_mck(pb10) */
|
||||
#define SPI4_GMUX_0001 IOMUX_MAKE_VALUE(0x28, 28, 4, 0x01) /*!< spi4_cs/i2s4_ws(pe12), spi4_sck/i2s4_ck(pe11), spi4_miso(pe13), spi4_mosi/i2s4_sd(pe14), i2s4_mck(pc8) */
|
||||
#define SPI4_GMUX_0010 IOMUX_MAKE_VALUE(0x28, 28, 4, 0x02) /*!< spi4_cs/i2s4_ws(pb6), spi4_sck/i2s4_ck(pb7), spi4_miso(pb8), spi4_mosi/i2s4_sd(pb9), i2s4_mck(pc8) */
|
||||
#define SPI4_GMUX_0011 IOMUX_MAKE_VALUE(0x28, 28, 4, 0x03) /*!< spi4_cs/i2s4_ws(pb6), spi4_sck/i2s4_ck(pb7), spi4_miso(pb8), spi4_mosi/i2s4_sd(pb9), i2s4_mck(pa10) */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup IOMUX_map6_definition
|
||||
* @brief iomux map6 definitions
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define CAN1_GMUX_0010 IOMUX_MAKE_VALUE(0x2C, 0, 4, 0x02) /*!< can_rx(pb8), can_tx(pb9) */
|
||||
#define CAN1_GMUX_0011 IOMUX_MAKE_VALUE(0x2C, 0, 4, 0x03) /*!< can_rx(pd0), can_tx(pd1) */
|
||||
#define CAN2_GMUX_0001 IOMUX_MAKE_VALUE(0x2C, 4, 4, 0x01) /*!< can2_rx(pb5), can2_tx(pb6) */
|
||||
#define SDIO2_GMUX_0001 IOMUX_MAKE_VALUE(0x2C, 12, 4, 0x01) /*!< sdio2_ck(pc4), sdio2_cmd(pc5), sdio2_d0(pa4), sdio2_d1(pa5), sdio2_d2(pa6), sdio2_d3(pa7) */
|
||||
#define SDIO2_GMUX_0010 IOMUX_MAKE_VALUE(0x2C, 12, 4, 0x02) /*!< sdio2_ck(pa2), sdio2_cmd(pa3), sdio2_d0(pc0), sdio2_d1(pc1), sdio2_d2(pc2), sdio2_d3(pc3), sdio2_d4(pa4), sdio2_d5(pa5), sdio2_d6(pa6), sdio2_d7(pa7) */
|
||||
#define SDIO2_GMUX_0011 IOMUX_MAKE_VALUE(0x2C, 12, 4, 0x03) /*!< sdio2_ck(pa2), sdio2_cmd(pa3), sdio2_d0(pa4), sdio2_d1(pa5), sdio2_d2(pa6), sdio2_d3(pa7) */
|
||||
#define USART1_GMUX_0001 IOMUX_MAKE_VALUE(0x2C, 16, 4, 0x01) /*!< usart1_tx(pb6), usart1_rx(pb7) */
|
||||
#define USART2_GMUX_0001 IOMUX_MAKE_VALUE(0x2C, 20, 4, 0x01) /*!< usart2_tx(pd5), usart2_rx(pd6), usart2_ck(pd7), usart2_cts(pd3), usart2_rts(pd4) */
|
||||
#define USART3_GMUX_0001 IOMUX_MAKE_VALUE(0x2C, 24, 4, 0x01) /*!< usart3_tx(pc10), usart3_rx(pc11), usart3_ck(pc12), usart3_cts(pb13), usart3_rts(pb14) */
|
||||
#define USART3_GMUX_0011 IOMUX_MAKE_VALUE(0x2C, 24, 4, 0x03) /*!< usart3_tx(pd8), usart3_rx(pd9), usart3_ck(pd10), usart3_cts(pd11), usart3_rts(pd12) */
|
||||
#define UART4_GMUX_0010 IOMUX_MAKE_VALUE(0x2C, 28, 4, 0x02) /*!< uart4_tx(pa0), uart4_rx(pa1) */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup IOMUX_map7_definition
|
||||
* @brief iomux map7 definitions
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define EXT_SPIM_GMUX_1000 IOMUX_MAKE_VALUE(0x30, 0, 4, 0x08) /*!< spim_sck(pb1), spim_cs(pa8), spim_io0(pa11), spim_io1(pa12), spim_io2(pb7), spim_sio3(pb6) */
|
||||
#define EXT_SPIM_GMUX_1001 IOMUX_MAKE_VALUE(0x30, 0, 4, 0x09) /*!< spim_sck(pb1), spim_cs(pa8), spim_io0(pb10), spim_io1(pb11), spim_io2(pb7), spim_sio3(pb6) */
|
||||
#define ADC1_ETP_GMUX IOMUX_MAKE_VALUE(0x30, 4, 1, 0x01) /*!< adc1 external trigger preempted conversion muxing */
|
||||
#define ADC1_ETO_GMUX IOMUX_MAKE_VALUE(0x30, 5, 1, 0x01) /*!< adc1 external trigger ordinary conversion muxing */
|
||||
#define ADC2_ETP_GMUX IOMUX_MAKE_VALUE(0x30, 8, 1, 0x01) /*!< adc2 external trigger preempted conversion muxing */
|
||||
#define ADC2_ETO_GMUX IOMUX_MAKE_VALUE(0x30, 9, 1, 0x01) /*!< adc2 external trigger ordinary conversion muxing */
|
||||
#define SWJTAG_GMUX_001 IOMUX_MAKE_VALUE(0x30, 16, 3, 0x01) /*!< full swj enabled (jtag-dp + sw-dp) but without jtrst */
|
||||
#define SWJTAG_GMUX_010 IOMUX_MAKE_VALUE(0x30, 16, 3, 0x02) /*!< jtag-dp disabled and sw-dp enabled */
|
||||
#define SWJTAG_GMUX_100 IOMUX_MAKE_VALUE(0x30, 16, 3, 0x04) /*!< full swj disabled (jtag-dp + sw-dp) */
|
||||
#define PD01_GMUX IOMUX_MAKE_VALUE(0x30, 20, 1, 0x01) /*!< pd0/pd1 mapping on osc_in/osc_out */
|
||||
#define XMC_GMUX_001 IOMUX_MAKE_VALUE(0x30, 24, 3, 0x01) /*!< xmc_nwe(pd2), xmc_d0(pb14), xmc_d1(pc6), xmc_d2(pc11), xmc_d3(pc12), xmc_d4(pa2), xmc_d5(pa3), xmc_d6(pa4), xmc_d7(pa5), xmc_d13(pb12), xmc_noe(pc5) */
|
||||
#define XMC_GMUX_010 IOMUX_MAKE_VALUE(0x30, 24, 3, 0x02) /*!< xmc_nwe(pc2), xmc_d0(pb14), xmc_d1(pc6), xmc_d2(pc11), xmc_d3(pc12), xmc_d4(pa2), xmc_d5(pa3), xmc_d6(pa4), xmc_d7(pa5), xmc_d13(pb12), xmc_noe(pc5) */
|
||||
#define XMC_NADV_GMUX IOMUX_MAKE_VALUE(0x30, 27, 1, 0x01) /*!< xmc_nadv not used */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup IOMUX_map8_definition
|
||||
* @brief iomux map8 definitions
|
||||
* @{
|
||||
*/
|
||||
|
||||
#if defined (AT32F407xx)
|
||||
#define EMAC_GMUX_01 IOMUX_MAKE_VALUE(0x34, 16, 2, 0x01) /*!< rx_dv/crs_dv(pd8), rxd0(pd9), rxd1(pd10), rxd2(pd11), rxd3(pd12) */
|
||||
#define MII_RMII_SEL_GMUX IOMUX_MAKE_VALUE(0x34, 18, 1, 0x01) /*!< mii or rmii selection */
|
||||
#define PTP_PPS_GMUX IOMUX_MAKE_VALUE(0x34, 19, 1, 0x01) /*!< ethernet ptp pps mux function remapping */
|
||||
#endif
|
||||
#define USART6_GMUX IOMUX_MAKE_VALUE(0x34, 20, 4, 0x01) /*!< usart6_tx(pa4), usart6_rx(pa5) */
|
||||
#define UART7_GMUX IOMUX_MAKE_VALUE(0x34, 24, 4, 0x01) /*!< uart7_tx(pb4), uart7_rx(pb3) */
|
||||
#define UART8_GMUX IOMUX_MAKE_VALUE(0x34, 28, 4, 0x01) /*!< uart8_tx(pc2), uart8_rx(pc3) */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup GPIO_exported_types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief gpio mode select
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
GPIO_MODE_INPUT = 0x00, /*!< gpio input mode */
|
||||
GPIO_MODE_OUTPUT = 0x10, /*!< gpio output mode */
|
||||
GPIO_MODE_MUX = 0x08, /*!< gpio mux function mode */
|
||||
GPIO_MODE_ANALOG = 0x03 /*!< gpio analog in/out mode */
|
||||
} gpio_mode_type;
|
||||
|
||||
/**
|
||||
* @brief gpio output drive strength select
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
GPIO_DRIVE_STRENGTH_STRONGER = 0x01, /*!< stronger sourcing/sinking strength */
|
||||
GPIO_DRIVE_STRENGTH_MODERATE = 0x02 /*!< moderate sourcing/sinking strength */
|
||||
} gpio_drive_type;
|
||||
|
||||
/**
|
||||
* @brief gpio output type
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
GPIO_OUTPUT_PUSH_PULL = 0x00, /*!< output push-pull */
|
||||
GPIO_OUTPUT_OPEN_DRAIN = 0x04 /*!< output open-drain */
|
||||
} gpio_output_type;
|
||||
|
||||
/**
|
||||
* @brief gpio pull type
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
GPIO_PULL_NONE = 0x0004, /*!< floating for input, no pull for output */
|
||||
GPIO_PULL_UP = 0x0018, /*!< pull-up */
|
||||
GPIO_PULL_DOWN = 0x0028 /*!< pull-down */
|
||||
} gpio_pull_type;
|
||||
|
||||
/**
|
||||
* @brief gpio pins source type
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
GPIO_PINS_SOURCE0 = 0x00, /*!< gpio pins source number 0 */
|
||||
GPIO_PINS_SOURCE1 = 0x01, /*!< gpio pins source number 1 */
|
||||
GPIO_PINS_SOURCE2 = 0x02, /*!< gpio pins source number 2 */
|
||||
GPIO_PINS_SOURCE3 = 0x03, /*!< gpio pins source number 3 */
|
||||
GPIO_PINS_SOURCE4 = 0x04, /*!< gpio pins source number 4 */
|
||||
GPIO_PINS_SOURCE5 = 0x05, /*!< gpio pins source number 5 */
|
||||
GPIO_PINS_SOURCE6 = 0x06, /*!< gpio pins source number 6 */
|
||||
GPIO_PINS_SOURCE7 = 0x07, /*!< gpio pins source number 7 */
|
||||
GPIO_PINS_SOURCE8 = 0x08, /*!< gpio pins source number 8 */
|
||||
GPIO_PINS_SOURCE9 = 0x09, /*!< gpio pins source number 9 */
|
||||
GPIO_PINS_SOURCE10 = 0x0A, /*!< gpio pins source number 10 */
|
||||
GPIO_PINS_SOURCE11 = 0x0B, /*!< gpio pins source number 11 */
|
||||
GPIO_PINS_SOURCE12 = 0x0C, /*!< gpio pins source number 12 */
|
||||
GPIO_PINS_SOURCE13 = 0x0D, /*!< gpio pins source number 13 */
|
||||
GPIO_PINS_SOURCE14 = 0x0E, /*!< gpio pins source number 14 */
|
||||
GPIO_PINS_SOURCE15 = 0x0F /*!< gpio pins source number 15 */
|
||||
} gpio_pins_source_type;
|
||||
|
||||
/**
|
||||
* @brief gpio port source type
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
GPIO_PORT_SOURCE_GPIOA = 0x00, /*!< gpio port source gpioa */
|
||||
GPIO_PORT_SOURCE_GPIOB = 0x01, /*!< gpio port source gpiob */
|
||||
GPIO_PORT_SOURCE_GPIOC = 0x02, /*!< gpio port source gpioc */
|
||||
GPIO_PORT_SOURCE_GPIOD = 0x03, /*!< gpio port source gpiod */
|
||||
GPIO_PORT_SOURCE_GPIOE = 0x04, /*!< gpio port source gpioe */
|
||||
} gpio_port_source_type;
|
||||
|
||||
/**
|
||||
* @brief gpio init type
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t gpio_pins; /*!< pins number selection */
|
||||
gpio_output_type gpio_out_type; /*!< output type selection */
|
||||
gpio_pull_type gpio_pull; /*!< pull type selection */
|
||||
gpio_mode_type gpio_mode; /*!< mode selection */
|
||||
gpio_drive_type gpio_drive_strength; /*!< drive strength selection */
|
||||
} gpio_init_type;
|
||||
|
||||
/**
|
||||
* @brief type define gpio register all
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
/**
|
||||
* @brief gpio cfglr register, offset:0x00
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t cfglr;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t iomc0 : 2; /* [1:0] */
|
||||
__IO uint32_t iofc0 : 2; /* [3:2] */
|
||||
__IO uint32_t iomc1 : 2; /* [5:4] */
|
||||
__IO uint32_t iofc1 : 2; /* [7:6] */
|
||||
__IO uint32_t iomc2 : 2; /* [9:8] */
|
||||
__IO uint32_t iofc2 : 2; /* [11:10] */
|
||||
__IO uint32_t iomc3 : 2; /* [13:12] */
|
||||
__IO uint32_t iofc3 : 2; /* [15:14] */
|
||||
__IO uint32_t iomc4 : 2; /* [17:16] */
|
||||
__IO uint32_t iofc4 : 2; /* [19:18] */
|
||||
__IO uint32_t iomc5 : 2; /* [21:20] */
|
||||
__IO uint32_t iofc5 : 2; /* [23:22] */
|
||||
__IO uint32_t iomc6 : 2; /* [25:24] */
|
||||
__IO uint32_t iofc6 : 2; /* [27:26] */
|
||||
__IO uint32_t iomc7 : 2; /* [29:28] */
|
||||
__IO uint32_t iofc7 : 2; /* [31:30] */
|
||||
} cfglr_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief gpio cfghr register, offset:0x04
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t cfghr;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t iomc8 : 2; /* [1:0] */
|
||||
__IO uint32_t iofc8 : 2; /* [3:2] */
|
||||
__IO uint32_t iomc9 : 2; /* [5:4] */
|
||||
__IO uint32_t iofc9 : 2; /* [7:6] */
|
||||
__IO uint32_t iomc10 : 2; /* [9:8] */
|
||||
__IO uint32_t iofc10 : 2; /* [11:10] */
|
||||
__IO uint32_t iomc11 : 2; /* [13:12] */
|
||||
__IO uint32_t iofc11 : 2; /* [15:14] */
|
||||
__IO uint32_t iomc12 : 2; /* [17:16] */
|
||||
__IO uint32_t iofc12 : 2; /* [19:18] */
|
||||
__IO uint32_t iomc13 : 2; /* [21:20] */
|
||||
__IO uint32_t iofc13 : 2; /* [23:22] */
|
||||
__IO uint32_t iomc14 : 2; /* [25:24] */
|
||||
__IO uint32_t iofc14 : 2; /* [27:26] */
|
||||
__IO uint32_t iomc15 : 2; /* [29:28] */
|
||||
__IO uint32_t iofc15 : 2; /* [31:30] */
|
||||
} cfghr_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief gpio idt register, offset:0x08
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t idt;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t idt0 : 1; /* [0] */
|
||||
__IO uint32_t idt1 : 1; /* [1] */
|
||||
__IO uint32_t idt2 : 1; /* [2] */
|
||||
__IO uint32_t idt3 : 1; /* [3] */
|
||||
__IO uint32_t idt4 : 1; /* [4] */
|
||||
__IO uint32_t idt5 : 1; /* [5] */
|
||||
__IO uint32_t idt6 : 1; /* [6] */
|
||||
__IO uint32_t idt7 : 1; /* [7] */
|
||||
__IO uint32_t idt8 : 1; /* [8] */
|
||||
__IO uint32_t idt9 : 1; /* [9] */
|
||||
__IO uint32_t idt10 : 1; /* [10] */
|
||||
__IO uint32_t idt11 : 1; /* [11] */
|
||||
__IO uint32_t idt12 : 1; /* [12] */
|
||||
__IO uint32_t idt13 : 1; /* [13] */
|
||||
__IO uint32_t idt14 : 1; /* [14] */
|
||||
__IO uint32_t idt15 : 1; /* [15] */
|
||||
__IO uint32_t reserved1 : 16;/* [31:16] */
|
||||
} idt_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief gpio odt register, offset:0x0C
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t odt;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t odt0 : 1; /* [0] */
|
||||
__IO uint32_t odt1 : 1; /* [1] */
|
||||
__IO uint32_t odt2 : 1; /* [2] */
|
||||
__IO uint32_t odt3 : 1; /* [3] */
|
||||
__IO uint32_t odt4 : 1; /* [4] */
|
||||
__IO uint32_t odt5 : 1; /* [5] */
|
||||
__IO uint32_t odt6 : 1; /* [6] */
|
||||
__IO uint32_t odt7 : 1; /* [7] */
|
||||
__IO uint32_t odt8 : 1; /* [8] */
|
||||
__IO uint32_t odt9 : 1; /* [9] */
|
||||
__IO uint32_t odt10 : 1; /* [10] */
|
||||
__IO uint32_t odt11 : 1; /* [11] */
|
||||
__IO uint32_t odt12 : 1; /* [12] */
|
||||
__IO uint32_t odt13 : 1; /* [13] */
|
||||
__IO uint32_t odt14 : 1; /* [14] */
|
||||
__IO uint32_t odt15 : 1; /* [15] */
|
||||
__IO uint32_t reserved1 : 16;/* [31:16] */
|
||||
} odt_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief gpio scr register, offset:0x10
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t scr;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t iosb0 : 1; /* [0] */
|
||||
__IO uint32_t iosb1 : 1; /* [1] */
|
||||
__IO uint32_t iosb2 : 1; /* [2] */
|
||||
__IO uint32_t iosb3 : 1; /* [3] */
|
||||
__IO uint32_t iosb4 : 1; /* [4] */
|
||||
__IO uint32_t iosb5 : 1; /* [5] */
|
||||
__IO uint32_t iosb6 : 1; /* [6] */
|
||||
__IO uint32_t iosb7 : 1; /* [7] */
|
||||
__IO uint32_t iosb8 : 1; /* [8] */
|
||||
__IO uint32_t iosb9 : 1; /* [9] */
|
||||
__IO uint32_t iosb10 : 1; /* [10] */
|
||||
__IO uint32_t iosb11 : 1; /* [11] */
|
||||
__IO uint32_t iosb12 : 1; /* [12] */
|
||||
__IO uint32_t iosb13 : 1; /* [13] */
|
||||
__IO uint32_t iosb14 : 1; /* [14] */
|
||||
__IO uint32_t iosb15 : 1; /* [15] */
|
||||
__IO uint32_t iocb0 : 1; /* [16] */
|
||||
__IO uint32_t iocb1 : 1; /* [17] */
|
||||
__IO uint32_t iocb2 : 1; /* [18] */
|
||||
__IO uint32_t iocb3 : 1; /* [19] */
|
||||
__IO uint32_t iocb4 : 1; /* [20] */
|
||||
__IO uint32_t iocb5 : 1; /* [21] */
|
||||
__IO uint32_t iocb6 : 1; /* [22] */
|
||||
__IO uint32_t iocb7 : 1; /* [23] */
|
||||
__IO uint32_t iocb8 : 1; /* [24] */
|
||||
__IO uint32_t iocb9 : 1; /* [25] */
|
||||
__IO uint32_t iocb10 : 1; /* [26] */
|
||||
__IO uint32_t iocb11 : 1; /* [27] */
|
||||
__IO uint32_t iocb12 : 1; /* [28] */
|
||||
__IO uint32_t iocb13 : 1; /* [29] */
|
||||
__IO uint32_t iocb14 : 1; /* [30] */
|
||||
__IO uint32_t iocb15 : 1; /* [31] */
|
||||
} scr_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief gpio clr register, offset:0x14
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t clr;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t iocb0 : 1; /* [0] */
|
||||
__IO uint32_t iocb1 : 1; /* [1] */
|
||||
__IO uint32_t iocb2 : 1; /* [2] */
|
||||
__IO uint32_t iocb3 : 1; /* [3] */
|
||||
__IO uint32_t iocb4 : 1; /* [4] */
|
||||
__IO uint32_t iocb5 : 1; /* [5] */
|
||||
__IO uint32_t iocb6 : 1; /* [6] */
|
||||
__IO uint32_t iocb7 : 1; /* [7] */
|
||||
__IO uint32_t iocb8 : 1; /* [8] */
|
||||
__IO uint32_t iocb9 : 1; /* [9] */
|
||||
__IO uint32_t iocb10 : 1; /* [10] */
|
||||
__IO uint32_t iocb11 : 1; /* [11] */
|
||||
__IO uint32_t iocb12 : 1; /* [12] */
|
||||
__IO uint32_t iocb13 : 1; /* [13] */
|
||||
__IO uint32_t iocb14 : 1; /* [14] */
|
||||
__IO uint32_t iocb15 : 1; /* [15] */
|
||||
__IO uint32_t reserved1 : 16;/* [31:16] */
|
||||
} clr_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief gpio wpr register, offset:0x18
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t wpr;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t wpen0 : 1; /* [0] */
|
||||
__IO uint32_t wpen1 : 1; /* [1] */
|
||||
__IO uint32_t wpen2 : 1; /* [2] */
|
||||
__IO uint32_t wpen3 : 1; /* [3] */
|
||||
__IO uint32_t wpen4 : 1; /* [4] */
|
||||
__IO uint32_t wpen5 : 1; /* [5] */
|
||||
__IO uint32_t wpen6 : 1; /* [6] */
|
||||
__IO uint32_t wpen7 : 1; /* [7] */
|
||||
__IO uint32_t wpen8 : 1; /* [8] */
|
||||
__IO uint32_t wpen9 : 1; /* [9] */
|
||||
__IO uint32_t wpen10 : 1; /* [10] */
|
||||
__IO uint32_t wpen11 : 1; /* [11] */
|
||||
__IO uint32_t wpen12 : 1; /* [12] */
|
||||
__IO uint32_t wpen13 : 1; /* [13] */
|
||||
__IO uint32_t wpen14 : 1; /* [14] */
|
||||
__IO uint32_t wpen15 : 1; /* [15] */
|
||||
__IO uint32_t wpseq : 1; /* [16] */
|
||||
__IO uint32_t reserved1 : 15;/* [31:17] */
|
||||
} wpr_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief gpio reserved1 register, offset:0x1C~0x38
|
||||
*/
|
||||
__IO uint32_t reserved1[8];
|
||||
|
||||
/**
|
||||
* @brief gpio hdrv register, offset:0x3C
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t hdrv;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t hdrv0 : 1; /* [0] */
|
||||
__IO uint32_t hdrv1 : 1; /* [1] */
|
||||
__IO uint32_t hdrv2 : 1; /* [2] */
|
||||
__IO uint32_t hdrv3 : 1; /* [3] */
|
||||
__IO uint32_t hdrv4 : 1; /* [4] */
|
||||
__IO uint32_t hdrv5 : 1; /* [5] */
|
||||
__IO uint32_t hdrv6 : 1; /* [6] */
|
||||
__IO uint32_t hdrv7 : 1; /* [7] */
|
||||
__IO uint32_t hdrv8 : 1; /* [8] */
|
||||
__IO uint32_t hdrv9 : 1; /* [9] */
|
||||
__IO uint32_t hdrv10 : 1; /* [10] */
|
||||
__IO uint32_t hdrv11 : 1; /* [11] */
|
||||
__IO uint32_t hdrv12 : 1; /* [12] */
|
||||
__IO uint32_t hdrv13 : 1; /* [13] */
|
||||
__IO uint32_t hdrv14 : 1; /* [14] */
|
||||
__IO uint32_t hdrv15 : 1; /* [15] */
|
||||
__IO uint32_t reserved1 : 16;/* [31:16] */
|
||||
} hdrv_bit;
|
||||
};
|
||||
} gpio_type;
|
||||
|
||||
/**
|
||||
* @brief type define iomux register all
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
/**
|
||||
* @brief mux event control register, offset:0x00
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t evtout;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t selpin : 4; /* [3:0] */
|
||||
__IO uint32_t selport : 3; /* [6:4] */
|
||||
__IO uint32_t evoen : 1; /* [7] */
|
||||
__IO uint32_t reserved1 : 24;/* [31:8] */
|
||||
} evtout_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief iomux remap register, offset:0x04
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t remap;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t spi1_mux_l : 1; /* [0] */
|
||||
__IO uint32_t i2c1_mux : 1; /* [1] */
|
||||
__IO uint32_t usart1_mux : 1; /* [2] */
|
||||
__IO uint32_t usart2_mux : 1; /* [3] */
|
||||
__IO uint32_t usart3_mux : 2; /* [5:4] */
|
||||
__IO uint32_t tmr1_mux : 2; /* [7:6] */
|
||||
__IO uint32_t tmr2_mux : 2; /* [9:8] */
|
||||
__IO uint32_t tmr3_mux : 2; /* [11:10] */
|
||||
__IO uint32_t tmr4_mux : 1; /* [12] */
|
||||
__IO uint32_t can_mux : 2; /* [14:13] */
|
||||
__IO uint32_t pd01_mux : 1; /* [15] */
|
||||
__IO uint32_t tmr5ch4_mux : 1; /* [16] */
|
||||
__IO uint32_t adc1_extrgpre_mux : 1; /* [17] */
|
||||
__IO uint32_t adc1_extrgord_mux : 1; /* [18] */
|
||||
__IO uint32_t adc2_extrgpre_mux : 1; /* [19] */
|
||||
__IO uint32_t adc2_extrgord_mux : 1; /* [20] */
|
||||
__IO uint32_t emac_mux : 1; /* [21] */
|
||||
__IO uint32_t can2_mux : 1; /* [22] */
|
||||
__IO uint32_t mii_rmii_sel_mux : 1; /* [23] */
|
||||
__IO uint32_t swjtag_mux : 3; /* [26:24] */
|
||||
__IO uint32_t reserved1 : 1; /* [27] */
|
||||
__IO uint32_t spi3_mux : 1; /* [28] */
|
||||
__IO uint32_t tim2itr1_mux : 1; /* [29] */
|
||||
__IO uint32_t ptp_pps_mux : 1; /* [30] */
|
||||
__IO uint32_t spi1_mux_h : 1; /* [31] */
|
||||
} remap_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief mux external interrupt configuration register 1, offset:0x08
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t exintc1;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t exint0 : 4; /* [3:0] */
|
||||
__IO uint32_t exint1 : 4; /* [7:4] */
|
||||
__IO uint32_t exint2 : 4; /* [11:8] */
|
||||
__IO uint32_t exint3 : 4; /* [15:12] */
|
||||
__IO uint32_t reserved1 : 16;/* [31:16] */
|
||||
} exintc1_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief mux external interrupt configuration register 2, offset:0x0c
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t exintc2;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t exint4 : 4; /* [3:0] */
|
||||
__IO uint32_t exint5 : 4; /* [7:4] */
|
||||
__IO uint32_t exint6 : 4; /* [11:8] */
|
||||
__IO uint32_t exint7 : 4; /* [15:12] */
|
||||
__IO uint32_t reserved1 : 16;/* [31:16] */
|
||||
} exintc2_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief mux external interrupt configuration register 3, offset:0x10
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t exintc3;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t exint8 : 4; /* [3:0] */
|
||||
__IO uint32_t exint9 : 4; /* [7:4] */
|
||||
__IO uint32_t exint10 : 4; /* [11:8] */
|
||||
__IO uint32_t exint11 : 4; /* [15:12] */
|
||||
__IO uint32_t reserved1 : 16;/* [31:16] */
|
||||
} exintc3_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief mux external interrupt configuration register 4, offset:0x14
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t exintc4;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t exint12 : 4; /* [3:0] */
|
||||
__IO uint32_t exint13 : 4; /* [7:4] */
|
||||
__IO uint32_t exint14 : 4; /* [11:8] */
|
||||
__IO uint32_t exint15 : 4; /* [15:12] */
|
||||
__IO uint32_t reserved1 : 16;/* [31:16] */
|
||||
} exintc4_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief iomux reserved1 register, offset:0x18
|
||||
*/
|
||||
__IO uint32_t reserved1;
|
||||
|
||||
/**
|
||||
* @brief iomux remap register 2, offset:0x1C
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t remap2;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t tmr15_mux : 1; /* [0] */
|
||||
__IO uint32_t reserved1 : 4; /* [4:1] */
|
||||
__IO uint32_t tmr9_mux : 1; /* [5] */
|
||||
__IO uint32_t tmr10_mux : 1; /* [6] */
|
||||
__IO uint32_t tmr11_mux : 1; /* [7] */
|
||||
__IO uint32_t tmr13_mux : 1; /* [8] */
|
||||
__IO uint32_t tmr14_mux : 1; /* [9] */
|
||||
__IO uint32_t xmc_nadv_mux : 1; /* [10] */
|
||||
__IO uint32_t reserved2 : 6; /* [16:11] */
|
||||
__IO uint32_t spi4_mux : 1; /* [17] */
|
||||
__IO uint32_t i2c3_mux : 1; /* [18] */
|
||||
__IO uint32_t sdio2_mux : 2; /* [20:19] */
|
||||
__IO uint32_t ext_spim_en_mux : 1; /* [21] */
|
||||
__IO uint32_t reserved3 : 10;/* [31:22] */
|
||||
} remap2_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief iomux remap register 3, offset:0x20
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t remap3;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t tmr9_gmux : 4; /* [3:0] */
|
||||
__IO uint32_t reserved1 : 28;/* [31:4] */
|
||||
} remap3_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief iomux remap register 4, offset:0x24
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t remap4;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t tmr1_gmux : 4; /* [3:0] */
|
||||
__IO uint32_t tmr2_gmux : 2; /* [5:4] */
|
||||
__IO uint32_t tmr2itr1_gmux : 2; /* [7:6] */
|
||||
__IO uint32_t tmr3_gmux : 4; /* [11:8] */
|
||||
__IO uint32_t tmr4_gmux : 4; /* [15:12] */
|
||||
__IO uint32_t reserved1 : 3; /* [18:16] */
|
||||
__IO uint32_t tmr5ch4_gmux : 1; /* [19] */
|
||||
__IO uint32_t reserved2 : 12; /* [31:20] */
|
||||
} remap4_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief iomux remap register 5, offset:0x28
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t remap5;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t usart5_gmux : 4; /* [3:0] */
|
||||
__IO uint32_t i2c1_gmux : 4; /* [7:4] */
|
||||
__IO uint32_t reserved1 : 4; /* [11:8] */
|
||||
__IO uint32_t i2c3_gmux : 4; /* [15:12] */
|
||||
__IO uint32_t spi1_gmux : 4; /* [19:16] */
|
||||
__IO uint32_t spi2_gmux : 4; /* [23:20] */
|
||||
__IO uint32_t spi3_gmux : 4; /* [27:24] */
|
||||
__IO uint32_t spi4_gmux : 4; /* [31:28] */
|
||||
} remap5_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief iomux remap register 6, offset:0x2C
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t remap6;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t can1_gmux : 4; /* [3:0] */
|
||||
__IO uint32_t can2_gmux : 4; /* [7:4] */
|
||||
__IO uint32_t reserved1 : 4; /* [11:8] */
|
||||
__IO uint32_t sdio2_gmux : 4; /* [15:12] */
|
||||
__IO uint32_t usart1_gmux : 4; /* [19:16] */
|
||||
__IO uint32_t usart2_gmux : 4; /* [23:20] */
|
||||
__IO uint32_t usart3_gmux : 4; /* [27:24] */
|
||||
__IO uint32_t uart4_gmux : 4; /* [31:28] */
|
||||
} remap6_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief iomux remap register 7, offset:0x30
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t remap7;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t ext_spim_gmux : 3; /* [2:0] */
|
||||
__IO uint32_t ext_spim_gen : 1; /* [3] */
|
||||
__IO uint32_t adc1_etp_gmux : 1; /* [4] */
|
||||
__IO uint32_t adc1_eto_gmux : 1; /* [5] */
|
||||
__IO uint32_t reserved1 : 2; /* [7:6] */
|
||||
__IO uint32_t adc2_etp_gmux : 1; /* [8] */
|
||||
__IO uint32_t adc2_eto_gmux : 1; /* [9] */
|
||||
__IO uint32_t reserved2 : 6; /* [15:10] */
|
||||
__IO uint32_t swjtag_gmux : 3; /* [18:16] */
|
||||
__IO uint32_t reserved3 : 1; /* [19] */
|
||||
__IO uint32_t pd01_gmux : 1; /* [20] */
|
||||
__IO uint32_t reserved4 : 3; /* [23:21] */
|
||||
__IO uint32_t xmc_gmux : 3; /* [26:24] */
|
||||
__IO uint32_t xmc_nadv_gmux : 1; /* [27] */
|
||||
__IO uint32_t reserved5 : 4; /* [31:28] */
|
||||
} remap7_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief iomux remap register 8, offset:0x34
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t remap8;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t reserved1 : 16; /* [15:0] */
|
||||
__IO uint32_t emac_gmux : 2; /* [17:16] */
|
||||
__IO uint32_t mii_rmii_sel_gmux : 1; /* [18] */
|
||||
__IO uint32_t ptp_pps_gmux : 1; /* [19] */
|
||||
__IO uint32_t usart6_gmux : 4; /* [23:20] */
|
||||
__IO uint32_t uart7_gmux : 4; /* [27:24] */
|
||||
__IO uint32_t uart8_gmux : 4; /* [31:28] */
|
||||
} remap8_bit;
|
||||
};
|
||||
} iomux_type;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#define GPIOA ((gpio_type *) GPIOA_BASE)
|
||||
#define GPIOB ((gpio_type *) GPIOB_BASE)
|
||||
#define GPIOC ((gpio_type *) GPIOC_BASE)
|
||||
#define GPIOD ((gpio_type *) GPIOD_BASE)
|
||||
#define GPIOE ((gpio_type *) GPIOE_BASE)
|
||||
#define IOMUX ((iomux_type *) IOMUX_BASE)
|
||||
|
||||
/** @defgroup GPIO_exported_functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
void gpio_reset(gpio_type *gpio_x);
|
||||
void gpio_iomux_reset(void);
|
||||
void gpio_init(gpio_type *gpio_x, gpio_init_type *gpio_init_struct);
|
||||
void gpio_default_para_init(gpio_init_type *gpio_init_struct);
|
||||
flag_status gpio_input_data_bit_read(gpio_type *gpio_x, uint16_t pins);
|
||||
uint16_t gpio_input_data_read(gpio_type *gpio_x);
|
||||
flag_status gpio_output_data_bit_read(gpio_type *gpio_x, uint16_t pins);
|
||||
uint16_t gpio_output_data_read(gpio_type *gpio_x);
|
||||
void gpio_bits_set(gpio_type *gpio_x, uint16_t pins);
|
||||
void gpio_bits_reset(gpio_type *gpio_x, uint16_t pins);
|
||||
void gpio_bits_toggle(gpio_type *gpio_x, uint16_t pins);
|
||||
void gpio_bits_write(gpio_type *gpio_x, uint16_t pins, confirm_state bit_state);
|
||||
void gpio_port_write(gpio_type *gpio_x, uint16_t port_value);
|
||||
void gpio_pin_wp_config(gpio_type *gpio_x, uint16_t pins);
|
||||
void gpio_pins_huge_driven_config(gpio_type *gpio_x, uint16_t pins, confirm_state new_state);
|
||||
void gpio_event_output_config(gpio_port_source_type gpio_port_source, gpio_pins_source_type gpio_pin_source);
|
||||
void gpio_event_output_enable(confirm_state new_state);
|
||||
void gpio_pin_remap_config(uint32_t gpio_remap, confirm_state new_state);
|
||||
void gpio_exint_line_config(gpio_port_source_type gpio_port_source, gpio_pins_source_type gpio_pin_source);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,402 @@
|
|||
/**
|
||||
**************************************************************************
|
||||
* @file at32f403a_407_i2c.h
|
||||
* @brief at32f403a_407 i2c header file
|
||||
**************************************************************************
|
||||
*
|
||||
* Copyright (c) 2025, Artery Technology, All rights reserved.
|
||||
*
|
||||
* The software Board Support Package (BSP) that is made available to
|
||||
* download from Artery official website is the copyrighted work of Artery.
|
||||
* Artery authorizes customers to use, copy, and distribute the BSP
|
||||
* software and its related documentation for the purpose of design and
|
||||
* development in conjunction with Artery microcontrollers. Use of the
|
||||
* software is governed by this copyright notice and the following disclaimer.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
|
||||
* GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
|
||||
* TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
|
||||
* STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
|
||||
* INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
|
||||
*
|
||||
**************************************************************************
|
||||
*/
|
||||
|
||||
/* define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __AT32F403A_407_I2C_H
|
||||
#define __AT32F403A_407_I2C_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
|
||||
/* includes ------------------------------------------------------------------*/
|
||||
#include "at32f403a_407.h"
|
||||
|
||||
/** @addtogroup AT32F403A_407_periph_driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup I2C
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup I2C_sts1_flags_definition
|
||||
* @brief i2c sts1 flag
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define I2C_STARTF_FLAG ((uint32_t)0x00000001) /*!< i2c start condition generation complete flag */
|
||||
#define I2C_ADDR7F_FLAG ((uint32_t)0x00000002) /*!< i2c 0~7 bit address match flag */
|
||||
#define I2C_TDC_FLAG ((uint32_t)0x00000004) /*!< i2c transmit data complete flag */
|
||||
#define I2C_ADDRHF_FLAG ((uint32_t)0x00000008) /*!< i2c master 9~8 bit address header match flag */
|
||||
#define I2C_STOPF_FLAG ((uint32_t)0x00000010) /*!< i2c stop condition generation complete flag */
|
||||
#define I2C_RDBF_FLAG ((uint32_t)0x00000040) /*!< i2c receive data buffer full flag */
|
||||
#define I2C_TDBE_FLAG ((uint32_t)0x00000080) /*!< i2c transmit data buffer empty flag */
|
||||
#define I2C_BUSERR_FLAG ((uint32_t)0x00000100) /*!< i2c bus error flag */
|
||||
#define I2C_ARLOST_FLAG ((uint32_t)0x00000200) /*!< i2c arbitration lost flag */
|
||||
#define I2C_ACKFAIL_FLAG ((uint32_t)0x00000400) /*!< i2c acknowledge failure flag */
|
||||
#define I2C_OUF_FLAG ((uint32_t)0x00000800) /*!< i2c overflow or underflow flag */
|
||||
#define I2C_PECERR_FLAG ((uint32_t)0x00001000) /*!< i2c pec receive error flag */
|
||||
#define I2C_TMOUT_FLAG ((uint32_t)0x00004000) /*!< i2c smbus timeout flag */
|
||||
#define I2C_ALERTF_FLAG ((uint32_t)0x00008000) /*!< i2c smbus alert flag */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup I2C_sts2_flags_definition
|
||||
* @brief i2c sts2 flag
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define I2C_TRMODE_FLAG ((uint32_t)0x10010000) /*!< i2c transmission mode */
|
||||
#define I2C_BUSYF_FLAG ((uint32_t)0x10020000) /*!< i2c bus busy flag transmission mode */
|
||||
#define I2C_DIRF_FLAG ((uint32_t)0x10040000) /*!< i2c transmission direction flag */
|
||||
#define I2C_GCADDRF_FLAG ((uint32_t)0x10100000) /*!< i2c general call address received flag */
|
||||
#define I2C_DEVADDRF_FLAG ((uint32_t)0x10200000) /*!< i2c smbus device address received flag */
|
||||
#define I2C_HOSTADDRF_FLAG ((uint32_t)0x10400000) /*!< i2c smbus host address received flag */
|
||||
#define I2C_ADDR2_FLAG ((uint32_t)0x10800000) /*!< i2c own address 2 received flag */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup I2C_interrupts_definition
|
||||
* @brief i2c interrupt
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define I2C_DATA_INT ((uint16_t)0x0400) /*!< i2c data transmission interrupt */
|
||||
#define I2C_EVT_INT ((uint16_t)0x0200) /*!< i2c event interrupt */
|
||||
#define I2C_ERR_INT ((uint16_t)0x0100) /*!< i2c error interrupt */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup I2C_exported_types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief i2c master receiving mode acknowledge control
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
I2C_MASTER_ACK_CURRENT = 0x00, /*!< acken bit acts on the current byte */
|
||||
I2C_MASTER_ACK_NEXT = 0x01 /*!< acken bit acts on the next byte */
|
||||
} i2c_master_ack_type;
|
||||
|
||||
/**
|
||||
* @brief i2c pec position set
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
I2C_PEC_POSITION_CURRENT = 0x00, /*!< the current byte is pec */
|
||||
I2C_PEC_POSITION_NEXT = 0x01 /*!< the next byte is pec */
|
||||
} i2c_pec_position_type;
|
||||
|
||||
|
||||
/**
|
||||
* @brief i2c smbus alert pin set
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
I2C_SMBUS_ALERT_HIGH = 0x00, /*!< smbus alert pin set high */
|
||||
I2C_SMBUS_ALERT_LOW = 0x01 /*!< smbus alert pin set low */
|
||||
} i2c_smbus_alert_set_type;
|
||||
|
||||
/**
|
||||
* @brief i2c smbus mode set
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
I2C_SMBUS_MODE_DEVICE = 0x00, /*!< smbus device mode */
|
||||
I2C_SMBUS_MODE_HOST = 0x01 /*!< smbus host mode */
|
||||
} i2c_smbus_mode_set_type;
|
||||
|
||||
|
||||
/**
|
||||
* @brief i2c fast mode duty cycle
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
I2C_FSMODE_DUTY_2_1 = 0x00, /*!< duty cycle is 2:1 in fast mode */
|
||||
I2C_FSMODE_DUTY_16_9 = 0x01 /*!< duty cycle is 16:9 in fast mode */
|
||||
} i2c_fsmode_duty_cycle_type;
|
||||
|
||||
/**
|
||||
* @brief i2c address mode
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
I2C_ADDRESS_MODE_7BIT = 0x00, /*!< 7bit address mode */
|
||||
I2C_ADDRESS_MODE_10BIT = 0x01 /*!< 10bit address mode */
|
||||
} i2c_address_mode_type;
|
||||
|
||||
/**
|
||||
* @brief i2c address direction
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
I2C_DIRECTION_TRANSMIT = 0x00, /*!< transmit mode */
|
||||
I2C_DIRECTION_RECEIVE = 0x01 /*!< receive mode */
|
||||
} i2c_direction_type;
|
||||
|
||||
/**
|
||||
* @brief type define i2c register all
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
/**
|
||||
* @brief i2c ctrl1 register, offset:0x00
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t ctrl1;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t i2cen : 1; /* [0] */
|
||||
__IO uint32_t permode : 1; /* [1] */
|
||||
__IO uint32_t reserved1 : 1; /* [2] */
|
||||
__IO uint32_t smbmode : 1; /* [3] */
|
||||
__IO uint32_t arpen : 1; /* [4] */
|
||||
__IO uint32_t pecen : 1; /* [5] */
|
||||
__IO uint32_t gcaen : 1; /* [6] */
|
||||
__IO uint32_t stretch : 1; /* [7] */
|
||||
__IO uint32_t genstart : 1; /* [8] */
|
||||
__IO uint32_t genstop : 1; /* [9] */
|
||||
__IO uint32_t acken : 1; /* [10] */
|
||||
__IO uint32_t mackctrl : 1; /* [11] */
|
||||
__IO uint32_t pecten : 1; /* [12] */
|
||||
__IO uint32_t smbalert : 1; /* [13] */
|
||||
__IO uint32_t reserved2 : 1; /* [14] */
|
||||
__IO uint32_t reset : 1; /* [15] */
|
||||
__IO uint32_t reserved3 : 16;/* [31:16] */
|
||||
} ctrl1_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief i2c ctrl2 register, offset:0x04
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t ctrl2;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t clkfreq : 8; /* [7:0] */
|
||||
__IO uint32_t errien : 1; /* [8] */
|
||||
__IO uint32_t evtien : 1; /* [9] */
|
||||
__IO uint32_t dataien : 1; /* [10] */
|
||||
__IO uint32_t dmaen : 1; /* [11] */
|
||||
__IO uint32_t dmaend : 1; /* [12] */
|
||||
__IO uint32_t reserved1 : 19;/* [31:13] */
|
||||
} ctrl2_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief i2c oaddr1 register, offset:0x08
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t oaddr1;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t addr1 : 10;/* [9:0] */
|
||||
__IO uint32_t reserved1 : 5; /* [14:10] */
|
||||
__IO uint32_t addr1mode : 1; /* [15] */
|
||||
__IO uint32_t reserved2 : 16;/* [31:16] */
|
||||
} oaddr1_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief i2c oaddr2 register, offset:0x0C
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t oaddr2;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t addr2en : 1; /* [0] */
|
||||
__IO uint32_t addr2 : 7; /* [7:1] */
|
||||
__IO uint32_t reserved1 : 24;/* [31:8] */
|
||||
} oaddr2_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief i2c dt register, offset:0x10
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t dt;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t dt : 8; /* [7:0] */
|
||||
__IO uint32_t reserved1 : 24;/* [31:8] */
|
||||
} dt_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief i2c sts1 register, offset:0x14
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t sts1;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t startf : 1; /* [0] */
|
||||
__IO uint32_t addr7f : 1; /* [1] */
|
||||
__IO uint32_t tdc : 1; /* [2] */
|
||||
__IO uint32_t addrhf : 1; /* [3] */
|
||||
__IO uint32_t stopf : 1; /* [4] */
|
||||
__IO uint32_t reserved1 : 1; /* [5] */
|
||||
__IO uint32_t rdbf : 1; /* [6] */
|
||||
__IO uint32_t tdbe : 1; /* [7] */
|
||||
__IO uint32_t buserr : 1; /* [8] */
|
||||
__IO uint32_t arlost : 1; /* [9] */
|
||||
__IO uint32_t ackfail : 1; /* [10] */
|
||||
__IO uint32_t ouf : 1; /* [11] */
|
||||
__IO uint32_t pecerr : 1; /* [12] */
|
||||
__IO uint32_t reserved2 : 1; /* [13] */
|
||||
__IO uint32_t tmout : 1; /* [14] */
|
||||
__IO uint32_t alertf : 1; /* [15] */
|
||||
__IO uint32_t reserved3 : 16; /* [31:16] */
|
||||
} sts1_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief i2c sts2 register, offset:0x18
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t sts2;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t trmode : 1; /* [0] */
|
||||
__IO uint32_t busyf : 1; /* [1] */
|
||||
__IO uint32_t dirf : 1; /* [2] */
|
||||
__IO uint32_t reserved1 : 1; /* [3] */
|
||||
__IO uint32_t gcaddrf : 1; /* [4] */
|
||||
__IO uint32_t devaddrf : 1; /* [5] */
|
||||
__IO uint32_t hostaddrf : 1; /* [6] */
|
||||
__IO uint32_t addr2 : 1; /* [7] */
|
||||
__IO uint32_t pecval : 8; /* [15:8] */
|
||||
__IO uint32_t reserved2 : 16;/* [31:16] */
|
||||
} sts2_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief i2c clkctrl register, offset:0x1C
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t clkctrl;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t speed : 12;/* [11:0] */
|
||||
__IO uint32_t reserved1 : 2; /* [13:12] */
|
||||
__IO uint32_t dutymode : 1; /* [14] */
|
||||
__IO uint32_t speedmode : 1; /* [15] */
|
||||
__IO uint32_t reserved2 : 16;/* [31:16] */
|
||||
} clkctrl_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief i2c tmrise register, offset:0x20
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t tmrise;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t risetime : 6; /* [5:0] */
|
||||
__IO uint32_t reserved1 : 26;/* [31:6] */
|
||||
} tmrise_bit;
|
||||
};
|
||||
|
||||
} i2c_type;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#define I2C1 ((i2c_type *) I2C1_BASE)
|
||||
#define I2C2 ((i2c_type *) I2C2_BASE)
|
||||
#define I2C3 ((i2c_type *) I2C3_BASE)
|
||||
|
||||
/** @defgroup I2C_exported_functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
void i2c_reset(i2c_type *i2c_x);
|
||||
void i2c_software_reset(i2c_type *i2c_x, confirm_state new_state);
|
||||
void i2c_init(i2c_type *i2c_x, i2c_fsmode_duty_cycle_type duty, uint32_t speed);
|
||||
void i2c_own_address1_set(i2c_type *i2c_x, i2c_address_mode_type mode, uint16_t address);
|
||||
void i2c_own_address2_set(i2c_type *i2c_x, uint8_t address);
|
||||
void i2c_own_address2_enable(i2c_type *i2c_x, confirm_state new_state);
|
||||
void i2c_smbus_enable(i2c_type *i2c_x, confirm_state new_state);
|
||||
void i2c_enable(i2c_type *i2c_x, confirm_state new_state);
|
||||
void i2c_fast_mode_duty_set(i2c_type *i2c_x, i2c_fsmode_duty_cycle_type duty);
|
||||
void i2c_clock_stretch_enable(i2c_type *i2c_x, confirm_state new_state);
|
||||
void i2c_ack_enable(i2c_type *i2c_x, confirm_state new_state);
|
||||
void i2c_master_receive_ack_set(i2c_type *i2c_x, i2c_master_ack_type pos);
|
||||
void i2c_pec_position_set(i2c_type *i2c_x, i2c_pec_position_type pos);
|
||||
void i2c_general_call_enable(i2c_type *i2c_x, confirm_state new_state);
|
||||
void i2c_arp_mode_enable(i2c_type *i2c_x, confirm_state new_state);
|
||||
void i2c_smbus_mode_set(i2c_type *i2c_x, i2c_smbus_mode_set_type mode);
|
||||
void i2c_smbus_alert_set(i2c_type *i2c_x, i2c_smbus_alert_set_type level);
|
||||
void i2c_pec_transmit_enable(i2c_type *i2c_x, confirm_state new_state);
|
||||
void i2c_pec_calculate_enable(i2c_type *i2c_x, confirm_state new_state);
|
||||
uint8_t i2c_pec_value_get(i2c_type *i2c_x);
|
||||
void i2c_dma_end_transfer_set(i2c_type *i2c_x, confirm_state new_state);
|
||||
void i2c_dma_enable(i2c_type *i2c_x, confirm_state new_state);
|
||||
void i2c_interrupt_enable(i2c_type *i2c_x, uint16_t source, confirm_state new_state);
|
||||
void i2c_start_generate(i2c_type *i2c_x);
|
||||
void i2c_stop_generate(i2c_type *i2c_x);
|
||||
void i2c_7bit_address_send(i2c_type *i2c_x, uint8_t address, i2c_direction_type direction);
|
||||
void i2c_data_send(i2c_type *i2c_x, uint8_t data);
|
||||
uint8_t i2c_data_receive(i2c_type *i2c_x);
|
||||
flag_status i2c_flag_get(i2c_type *i2c_x, uint32_t flag);
|
||||
flag_status i2c_interrupt_flag_get(i2c_type *i2c_x, uint32_t flag);
|
||||
void i2c_flag_clear(i2c_type *i2c_x, uint32_t flag);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,124 @@
|
|||
/**
|
||||
**************************************************************************
|
||||
* @file at32f403a_407_misc.h
|
||||
* @brief at32f403a_407 misc header file
|
||||
**************************************************************************
|
||||
*
|
||||
* Copyright (c) 2025, Artery Technology, All rights reserved.
|
||||
*
|
||||
* The software Board Support Package (BSP) that is made available to
|
||||
* download from Artery official website is the copyrighted work of Artery.
|
||||
* Artery authorizes customers to use, copy, and distribute the BSP
|
||||
* software and its related documentation for the purpose of design and
|
||||
* development in conjunction with Artery microcontrollers. Use of the
|
||||
* software is governed by this copyright notice and the following disclaimer.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
|
||||
* GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
|
||||
* TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
|
||||
* STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
|
||||
* INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
|
||||
*
|
||||
**************************************************************************
|
||||
*/
|
||||
|
||||
/* define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __AT32F403A_407_MISC_H
|
||||
#define __AT32F403A_407_MISC_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
|
||||
/* includes ------------------------------------------------------------------*/
|
||||
#include "at32f403a_407.h"
|
||||
|
||||
/** @addtogroup AT32F403A_407_periph_driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup MISC
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup MISC_vector_table_base_address
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define NVIC_VECTTAB_RAM ((uint32_t)0x20000000) /*!< nvic vector table based ram address */
|
||||
#define NVIC_VECTTAB_FLASH ((uint32_t)0x08000000) /*!< nvic vector table based flash address */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup MISC_exported_types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief nvic interrupt priority group
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
NVIC_PRIORITY_GROUP_0 = ((uint32_t)0x7), /*!< 0 bits for preemption priority, 4 bits for subpriority */
|
||||
NVIC_PRIORITY_GROUP_1 = ((uint32_t)0x6), /*!< 1 bits for preemption priority, 3 bits for subpriority */
|
||||
NVIC_PRIORITY_GROUP_2 = ((uint32_t)0x5), /*!< 2 bits for preemption priority, 2 bits for subpriority */
|
||||
NVIC_PRIORITY_GROUP_3 = ((uint32_t)0x4), /*!< 3 bits for preemption priority, 1 bits for subpriority */
|
||||
NVIC_PRIORITY_GROUP_4 = ((uint32_t)0x3) /*!< 4 bits for preemption priority, 0 bits for subpriority */
|
||||
} nvic_priority_group_type;
|
||||
|
||||
/**
|
||||
* @brief nvic low power mode
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
NVIC_LP_SLEEPONEXIT = 0x02, /*!< enable sleep-on-exit feature */
|
||||
NVIC_LP_SLEEPDEEP = 0x04, /*!< enable sleep-deep output signal when entering sleep mode */
|
||||
NVIC_LP_SEVONPEND = 0x10 /*!< send event on pending */
|
||||
} nvic_lowpower_mode_type;
|
||||
|
||||
/**
|
||||
* @brief systick clock source
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
SYSTICK_CLOCK_SOURCE_AHBCLK_DIV8 = ((uint32_t)0x00000000), /*!< systick clock source from core clock div8 */
|
||||
SYSTICK_CLOCK_SOURCE_AHBCLK_NODIV = ((uint32_t)0x00000004) /*!< systick clock source from core clock */
|
||||
} systick_clock_source_type;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup MISC_exported_functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
void nvic_system_reset(void);
|
||||
void nvic_irq_enable(IRQn_Type irqn, uint32_t preempt_priority, uint32_t sub_priority);
|
||||
void nvic_irq_disable(IRQn_Type irqn);
|
||||
void nvic_priority_group_config(nvic_priority_group_type priority_group);
|
||||
void nvic_vector_table_set(uint32_t base, uint32_t offset);
|
||||
void nvic_lowpower_mode_config(nvic_lowpower_mode_type lp_mode, confirm_state new_state);
|
||||
void systick_clock_source_config(systick_clock_source_type source);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,190 @@
|
|||
/**
|
||||
**************************************************************************
|
||||
* @file at32f403a_407_pwc.h
|
||||
* @brief at32f403a_407 pwc header file
|
||||
**************************************************************************
|
||||
*
|
||||
* Copyright (c) 2025, Artery Technology, All rights reserved.
|
||||
*
|
||||
* The software Board Support Package (BSP) that is made available to
|
||||
* download from Artery official website is the copyrighted work of Artery.
|
||||
* Artery authorizes customers to use, copy, and distribute the BSP
|
||||
* software and its related documentation for the purpose of design and
|
||||
* development in conjunction with Artery microcontrollers. Use of the
|
||||
* software is governed by this copyright notice and the following disclaimer.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
|
||||
* GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
|
||||
* TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
|
||||
* STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
|
||||
* INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
|
||||
*
|
||||
**************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __AT32F403A_407_PWC_H
|
||||
#define __AT32F403A_407_PWC_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "at32f403a_407.h"
|
||||
|
||||
/** @addtogroup AT32F403A_407_periph_driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup PWC
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup PWC_flags_definition
|
||||
* @brief pwc flag
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define PWC_WAKEUP_FLAG ((uint32_t)0x00000001) /*!< wakeup flag */
|
||||
#define PWC_STANDBY_FLAG ((uint32_t)0x00000002) /*!< standby flag */
|
||||
#define PWC_PVM_OUTPUT_FLAG ((uint32_t)0x00000004) /*!< pvm output flag */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief pwc wakeup pin num definition
|
||||
*/
|
||||
#define PWC_WAKEUP_PIN_1 ((uint32_t)0x00000100) /*!< standby wake-up pin1(pa0) */
|
||||
|
||||
/** @defgroup PWC_exported_types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief pwc pvm voltage type
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
PWC_PVM_VOLTAGE_2V3 = 0x01, /*!< power voltage monitoring boundary 2.3v */
|
||||
PWC_PVM_VOLTAGE_2V4 = 0x02, /*!< power voltage monitoring boundary 2.4v */
|
||||
PWC_PVM_VOLTAGE_2V5 = 0x03, /*!< power voltage monitoring boundary 2.5v */
|
||||
PWC_PVM_VOLTAGE_2V6 = 0x04, /*!< power voltage monitoring boundary 2.6v */
|
||||
PWC_PVM_VOLTAGE_2V7 = 0x05, /*!< power voltage monitoring boundary 2.7v */
|
||||
PWC_PVM_VOLTAGE_2V8 = 0x06, /*!< power voltage monitoring boundary 2.8v */
|
||||
PWC_PVM_VOLTAGE_2V9 = 0x07 /*!< power voltage monitoring boundary 2.9v */
|
||||
} pwc_pvm_voltage_type;
|
||||
|
||||
/**
|
||||
* @brief pwc sleep enter type
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
PWC_SLEEP_ENTER_WFI = 0x00, /*!< use wfi enter sleep mode */
|
||||
PWC_SLEEP_ENTER_WFE = 0x01 /*!< use wfe enter sleep mode */
|
||||
} pwc_sleep_enter_type;
|
||||
|
||||
/**
|
||||
* @brief pwc deep sleep enter type
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
PWC_DEEP_SLEEP_ENTER_WFI = 0x00, /*!< use wfi enter deepsleep mode */
|
||||
PWC_DEEP_SLEEP_ENTER_WFE = 0x01 /*!< use wfe enter deepsleep mode */
|
||||
} pwc_deep_sleep_enter_type;
|
||||
|
||||
/**
|
||||
* @brief pwc regulator type
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
PWC_REGULATOR_ON = 0x00, /*!< voltage regulator state on when deepsleep mode */
|
||||
PWC_REGULATOR_LOW_POWER = 0x01 /*!< voltage regulator state low power when deepsleep mode */
|
||||
} pwc_regulator_type;
|
||||
|
||||
/**
|
||||
* @brief type define pwc register all
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
/**
|
||||
* @brief pwc ctrl register, offset:0x00
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t ctrl;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t vrsel : 1; /* [0] */
|
||||
__IO uint32_t lpsel : 1; /* [1] */
|
||||
__IO uint32_t clswef : 1; /* [2] */
|
||||
__IO uint32_t clsef : 1; /* [3] */
|
||||
__IO uint32_t pvmen : 1; /* [4] */
|
||||
__IO uint32_t pvmsel : 3; /* [7:5] */
|
||||
__IO uint32_t bpwen : 1; /* [8] */
|
||||
__IO uint32_t reserved1 : 23;/* [31:9] */
|
||||
} ctrl_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief pwc ctrlsts register, offset:0x04
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t ctrlsts;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t swef : 1; /* [0] */
|
||||
__IO uint32_t sef : 1; /* [1] */
|
||||
__IO uint32_t pvmof : 1; /* [2] */
|
||||
__IO uint32_t reserved1 : 5; /* [7:3] */
|
||||
__IO uint32_t swpen : 1; /* [8] */
|
||||
__IO uint32_t reserved2 : 23;/* [31:9] */
|
||||
} ctrlsts_bit;
|
||||
};
|
||||
|
||||
} pwc_type;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#define PWC ((pwc_type *) PWC_BASE)
|
||||
|
||||
/** @defgroup PWC_exported_functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
void pwc_reset(void);
|
||||
void pwc_battery_powered_domain_access(confirm_state new_state);
|
||||
void pwc_pvm_level_select(pwc_pvm_voltage_type pvm_voltage);
|
||||
void pwc_power_voltage_monitor_enable(confirm_state new_state);
|
||||
void pwc_wakeup_pin_enable(uint32_t pin_num, confirm_state new_state);
|
||||
void pwc_flag_clear(uint32_t pwc_flag);
|
||||
flag_status pwc_flag_get(uint32_t pwc_flag);
|
||||
void pwc_sleep_mode_enter(pwc_sleep_enter_type pwc_sleep_enter);
|
||||
void pwc_deep_sleep_mode_enter(pwc_deep_sleep_enter_type pwc_deep_sleep_enter);
|
||||
void pwc_voltage_regulate_set(pwc_regulator_type pwc_regulator);
|
||||
void pwc_standby_mode_enter(void);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,261 @@
|
|||
/**
|
||||
**************************************************************************
|
||||
* @file at32f403a_407_rtc.h
|
||||
* @brief at32f403a_407 rtc header file
|
||||
**************************************************************************
|
||||
*
|
||||
* Copyright (c) 2025, Artery Technology, All rights reserved.
|
||||
*
|
||||
* The software Board Support Package (BSP) that is made available to
|
||||
* download from Artery official website is the copyrighted work of Artery.
|
||||
* Artery authorizes customers to use, copy, and distribute the BSP
|
||||
* software and its related documentation for the purpose of design and
|
||||
* development in conjunction with Artery microcontrollers. Use of the
|
||||
* software is governed by this copyright notice and the following disclaimer.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
|
||||
* GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
|
||||
* TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
|
||||
* STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
|
||||
* INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
|
||||
*
|
||||
**************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __AT32F403A_407_RTC_H
|
||||
#define __AT32F403A_407_RTC_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "at32f403a_407.h"
|
||||
|
||||
/** @addtogroup AT32F403A_407_periph_driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup RTC
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup RTC_interrupts_definition
|
||||
* @brief rtc interrupt
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define RTC_TS_INT ((uint16_t)0x0001) /*!< rtc time second interrupt */
|
||||
#define RTC_TA_INT ((uint16_t)0x0002) /*!< rtc time alarm interrupt */
|
||||
#define RTC_OVF_INT ((uint16_t)0x0004) /*!< rtc overflow interrupt */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RTC_flags_definition
|
||||
* @brief rtc flag
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define RTC_TS_FLAG ((uint16_t)0x0001) /*!< rtc time second flag */
|
||||
#define RTC_TA_FLAG ((uint16_t)0x0002) /*!< rtc time alarm flag */
|
||||
#define RTC_OVF_FLAG ((uint16_t)0x0004) /*!< rtc overflow flag */
|
||||
#define RTC_UPDF_FLAG ((uint16_t)0x0008) /*!< rtc update finish flag */
|
||||
#define RTC_CFGF_FLAG ((uint16_t)0x0020) /*!< rtc configuration finish flag */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RTC_exported_types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief type define rtc register all
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
|
||||
/**
|
||||
* @brief rtc ctrlh register, offset:0x00
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t ctrlh;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t tsien : 1; /* [0] */
|
||||
__IO uint32_t taien : 1; /* [1] */
|
||||
__IO uint32_t ovfien : 1; /* [2] */
|
||||
__IO uint32_t reserved1 : 29;/* [31:3] */
|
||||
} ctrlh_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief rtc ctrll register, offset:0x04
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t ctrll;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t tsf : 1; /* [0] */
|
||||
__IO uint32_t taf : 1; /* [1] */
|
||||
__IO uint32_t ovff : 1; /* [2] */
|
||||
__IO uint32_t updf : 1; /* [3] */
|
||||
__IO uint32_t cfgen : 1; /* [4] */
|
||||
__IO uint32_t cfgf : 1; /* [5] */
|
||||
__IO uint32_t reserved1 : 26;/* [31:6] */
|
||||
} ctrll_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief rtc divh register, offset:0x08
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t divh;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t div : 4; /* [3:0] */
|
||||
__IO uint32_t reserved1 : 28;/* [31:4] */
|
||||
} divh_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief rtc divl register, offset:0x0C
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t divl;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t div : 16;/* [15:0] */
|
||||
__IO uint32_t reserved1 : 16;/* [31:15] */
|
||||
} divl_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief rtc divcnth register, offset:0x10
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t divcnth;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t divcnt : 4; /* [3:0] */
|
||||
__IO uint32_t reserved1 : 28;/* [31:15] */
|
||||
} divcnth_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief rtc divcntl register, offset:0x14
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t divcntl;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t divcnt : 16;/* [15:0] */
|
||||
__IO uint32_t reserved1 : 16;/* [31:15] */
|
||||
} divcntl_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief rtc cnth register, offset:0x18
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t cnth;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t cnt : 16;/* [15:0] */
|
||||
__IO uint32_t reserved1 : 16;/* [31:15] */
|
||||
} cnth_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief rtc cntl register, offset:0x1C
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t cntl;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t cnt : 16;/* [15:0] */
|
||||
__IO uint32_t reserved1 : 16;/* [31:15] */
|
||||
} cntl_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief rtc tah register, offset:0x20
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t tah;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t ta : 16;/* [15:0] */
|
||||
__IO uint32_t reserved1 : 16;/* [31:15] */
|
||||
} tah_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief rtc tal register, offset:0x24
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t tal;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t ta : 16;/* [15:0] */
|
||||
__IO uint32_t reserved1 : 16;/* [31:15] */
|
||||
} tal_bit;
|
||||
};
|
||||
|
||||
} rtc_type;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#define RTC ((rtc_type *) RTC_BASE)
|
||||
|
||||
/** @defgroup RTC_exported_functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
void rtc_counter_set(uint32_t counter_value);
|
||||
uint32_t rtc_counter_get(void);
|
||||
void rtc_divider_set(uint32_t div_value);
|
||||
uint32_t rtc_divider_get(void);
|
||||
void rtc_alarm_set(uint32_t alarm_value);
|
||||
void rtc_interrupt_enable(uint16_t source, confirm_state new_state);
|
||||
flag_status rtc_flag_get(uint16_t flag);
|
||||
flag_status rtc_interrupt_flag_get(uint16_t flag);
|
||||
void rtc_flag_clear(uint16_t flag);
|
||||
void rtc_wait_config_finish(void);
|
||||
void rtc_wait_update_finish(void);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,627 @@
|
|||
/**
|
||||
**************************************************************************
|
||||
* @file at32f403a_407_sdio.h
|
||||
* @brief at32f403a_407 sdio header file
|
||||
**************************************************************************
|
||||
*
|
||||
* Copyright (c) 2025, Artery Technology, All rights reserved.
|
||||
*
|
||||
* The software Board Support Package (BSP) that is made available to
|
||||
* download from Artery official website is the copyrighted work of Artery.
|
||||
* Artery authorizes customers to use, copy, and distribute the BSP
|
||||
* software and its related documentation for the purpose of design and
|
||||
* development in conjunction with Artery microcontrollers. Use of the
|
||||
* software is governed by this copyright notice and the following disclaimer.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
|
||||
* GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
|
||||
* TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
|
||||
* STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
|
||||
* INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
|
||||
*
|
||||
**************************************************************************
|
||||
*/
|
||||
|
||||
/* define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __AT32F403A_407_SDIO_H
|
||||
#define __AT32F403A_407_SDIO_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
|
||||
/* includes ------------------------------------------------------------------*/
|
||||
#include "at32f403a_407.h"
|
||||
|
||||
/** @addtogroup AT32F403A_407_periph_driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup SDIO
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup SDIO_interrupts_definition
|
||||
* @brief sdio interrupt
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define SDIO_CMDFAIL_INT ((uint32_t)0x00000001) /*!< command response received check failed interrupt */
|
||||
#define SDIO_DTFAIL_INT ((uint32_t)0x00000002) /*!< data block sent/received check failed interrupt */
|
||||
#define SDIO_CMDTIMEOUT_INT ((uint32_t)0x00000004) /*!< command response timerout interrupt */
|
||||
#define SDIO_DTTIMEOUT_INT ((uint32_t)0x00000008) /*!< data timeout interrupt */
|
||||
#define SDIO_TXERRU_INT ((uint32_t)0x00000010) /*!< transmit underrun error interrupt */
|
||||
#define SDIO_RXERRO_INT ((uint32_t)0x00000020) /*!< received overrun error interrupt */
|
||||
#define SDIO_CMDRSPCMPL_INT ((uint32_t)0x00000040) /*!< command response received interrupt */
|
||||
#define SDIO_CMDCMPL_INT ((uint32_t)0x00000080) /*!< command sent interrupt */
|
||||
#define SDIO_DTCMP_INT ((uint32_t)0x00000100) /*!< data sent interrupt */
|
||||
#define SDIO_SBITERR_INT ((uint32_t)0x00000200) /*!< start bit not detected on data bus interrupt */
|
||||
#define SDIO_DTBLKCMPL_INT ((uint32_t)0x00000400) /*!< data block sent/received interrupt */
|
||||
#define SDIO_DOCMD_INT ((uint32_t)0x00000800) /*!< command transfer in progress interrupt */
|
||||
#define SDIO_DOTX_INT ((uint32_t)0x00001000) /*!< data transmit in progress interrupt */
|
||||
#define SDIO_DORX_INT ((uint32_t)0x00002000) /*!< data receive in progress interrupt */
|
||||
#define SDIO_TXBUFH_INT ((uint32_t)0x00004000) /*!< transmit buf half empty interrupt */
|
||||
#define SDIO_RXBUFH_INT ((uint32_t)0x00008000) /*!< receive buf half full interrupt */
|
||||
#define SDIO_TXBUFF_INT ((uint32_t)0x00010000) /*!< transmit buf full interrupt */
|
||||
#define SDIO_RXBUFF_INT ((uint32_t)0x00020000) /*!< receive buf full interrupt */
|
||||
#define SDIO_TXBUFE_INT ((uint32_t)0x00040000) /*!< transmit buf empty interrupt */
|
||||
#define SDIO_RXBUFE_INT ((uint32_t)0x00080000) /*!< receive buf empty interrupt */
|
||||
#define SDIO_TXBUF_INT ((uint32_t)0x00100000) /*!< data available in transmit interrupt */
|
||||
#define SDIO_RXBUF_INT ((uint32_t)0x00200000) /*!< data available in receive interrupt */
|
||||
#define SDIO_SDIOIF_INT ((uint32_t)0x00400000) /*!< sdio interface received interrupt */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SDIO_flags_definition
|
||||
* @brief sdio flag
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define SDIO_CMDFAIL_FLAG ((uint32_t)0x00000001) /*!< command response received check failed flag */
|
||||
#define SDIO_DTFAIL_FLAG ((uint32_t)0x00000002) /*!< data block sent/received check failed flag */
|
||||
#define SDIO_CMDTIMEOUT_FLAG ((uint32_t)0x00000004) /*!< command response timerout flag */
|
||||
#define SDIO_DTTIMEOUT_FLAG ((uint32_t)0x00000008) /*!< data timeout flag */
|
||||
#define SDIO_TXERRU_FLAG ((uint32_t)0x00000010) /*!< transmit underrun error flag */
|
||||
#define SDIO_RXERRO_FLAG ((uint32_t)0x00000020) /*!< received overrun error flag */
|
||||
#define SDIO_CMDRSPCMPL_FLAG ((uint32_t)0x00000040) /*!< command response received flag */
|
||||
#define SDIO_CMDCMPL_FLAG ((uint32_t)0x00000080) /*!< command sent flag */
|
||||
#define SDIO_DTCMPL_FLAG ((uint32_t)0x00000100) /*!< data sent flag */
|
||||
#define SDIO_SBITERR_FLAG ((uint32_t)0x00000200) /*!< start bit not detected on data bus flag */
|
||||
#define SDIO_DTBLKCMPL_FLAG ((uint32_t)0x00000400) /*!< data block sent/received flag */
|
||||
#define SDIO_DOCMD_FLAG ((uint32_t)0x00000800) /*!< command transfer in progress flag */
|
||||
#define SDIO_DOTX_FLAG ((uint32_t)0x00001000) /*!< data transmit in progress flag */
|
||||
#define SDIO_DORX_FLAG ((uint32_t)0x00002000) /*!< data receive in progress flag */
|
||||
#define SDIO_TXBUFH_FLAG ((uint32_t)0x00004000) /*!< transmit buf half empty flag */
|
||||
#define SDIO_RXBUFH_FLAG ((uint32_t)0x00008000) /*!< receive buf half full flag */
|
||||
#define SDIO_TXBUFF_FLAG ((uint32_t)0x00010000) /*!< transmit buf full flag */
|
||||
#define SDIO_RXBUFF_FLAG ((uint32_t)0x00020000) /*!< receive buf full flag */
|
||||
#define SDIO_TXBUFE_FLAG ((uint32_t)0x00040000) /*!< transmit buf empty flag */
|
||||
#define SDIO_RXBUFE_FLAG ((uint32_t)0x00080000) /*!< receive buf empty flag */
|
||||
#define SDIO_TXBUF_FLAG ((uint32_t)0x00100000) /*!< data available in transmit flag */
|
||||
#define SDIO_RXBUF_FLAG ((uint32_t)0x00200000) /*!< data available in receive flag */
|
||||
#define SDIO_SDIOIF_FLAG ((uint32_t)0x00400000) /*!< sdio interface received flag */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SDIO_exported_types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief sdio power state
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
SDIO_POWER_OFF = 0x00, /*!< power-off, clock to card is stopped */
|
||||
SDIO_POWER_ON = 0x03 /*!< power-on, the card is clocked */
|
||||
} sdio_power_state_type;
|
||||
|
||||
/**
|
||||
* @brief sdio edge phase
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
SDIO_CLOCK_EDGE_RISING = 0x00, /*!< sdio bus clock generated on the rising edge of the master clock */
|
||||
SDIO_CLOCK_EDGE_FALLING = 0x01 /*!< sdio bus clock generated on the falling edge of the master clock */
|
||||
} sdio_edge_phase_type;
|
||||
|
||||
/**
|
||||
* @brief sdio bus width
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
SDIO_BUS_WIDTH_D1 = 0x00, /*!< sdio wide bus select 1-bit */
|
||||
SDIO_BUS_WIDTH_D4 = 0x01, /*!< sdio wide bus select 4-bit */
|
||||
SDIO_BUS_WIDTH_D8 = 0x02 /*!< sdio wide bus select 8-bit */
|
||||
} sdio_bus_width_type;
|
||||
|
||||
/**
|
||||
* @brief sdio response type
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
SDIO_RESPONSE_NO = 0x00, /*!< no response */
|
||||
SDIO_RESPONSE_SHORT = 0x01, /*!< short response */
|
||||
SDIO_RESPONSE_LONG = 0x03 /*!< long response */
|
||||
} sdio_reponse_type;
|
||||
|
||||
/**
|
||||
* @brief sdio wait type
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
SDIO_WAIT_FOR_NO = 0x00, /*!< no wait */
|
||||
SDIO_WAIT_FOR_INT = 0x01, /*!< wait interrupt request */
|
||||
SDIO_WAIT_FOR_PEND = 0x02 /*!< wait end of transfer */
|
||||
} sdio_wait_type;
|
||||
|
||||
/**
|
||||
* @brief sdio response register index
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
SDIO_RSP1_INDEX = 0x00, /*!< response index 1, corresponding to sdio_rsp register 1 */
|
||||
SDIO_RSP2_INDEX = 0x01, /*!< response index 2, corresponding to sdio_rsp register 2 */
|
||||
SDIO_RSP3_INDEX = 0x02, /*!< response index 3, corresponding to sdio_rsp register 3 */
|
||||
SDIO_RSP4_INDEX = 0x03 /*!< response index 4, corresponding to sdio_rsp register 4 */
|
||||
} sdio_rsp_index_type;
|
||||
|
||||
/**
|
||||
* @brief sdio data block size
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
SDIO_DATA_BLOCK_SIZE_1B = 0x00, /*!< data block size 1 byte */
|
||||
SDIO_DATA_BLOCK_SIZE_2B = 0x01, /*!< data block size 2 bytes */
|
||||
SDIO_DATA_BLOCK_SIZE_4B = 0x02, /*!< data block size 4 bytes */
|
||||
SDIO_DATA_BLOCK_SIZE_8B = 0x03, /*!< data block size 8 bytes */
|
||||
SDIO_DATA_BLOCK_SIZE_16B = 0x04, /*!< data block size 16 bytes */
|
||||
SDIO_DATA_BLOCK_SIZE_32B = 0x05, /*!< data block size 32 bytes */
|
||||
SDIO_DATA_BLOCK_SIZE_64B = 0x06, /*!< data block size 64 bytes */
|
||||
SDIO_DATA_BLOCK_SIZE_128B = 0x07, /*!< data block size 128 bytes */
|
||||
SDIO_DATA_BLOCK_SIZE_256B = 0x08, /*!< data block size 256 bytes */
|
||||
SDIO_DATA_BLOCK_SIZE_512B = 0x09, /*!< data block size 512 bytes */
|
||||
SDIO_DATA_BLOCK_SIZE_1024B = 0x0A, /*!< data block size 1024 bytes */
|
||||
SDIO_DATA_BLOCK_SIZE_2048B = 0x0B, /*!< data block size 2048 bytes */
|
||||
SDIO_DATA_BLOCK_SIZE_4096B = 0x0C, /*!< data block size 4096 bytes */
|
||||
SDIO_DATA_BLOCK_SIZE_8192B = 0x0D, /*!< data block size 8192 bytes */
|
||||
SDIO_DATA_BLOCK_SIZE_16384B = 0x0E /*!< data block size 16384 bytes */
|
||||
} sdio_block_size_type;
|
||||
|
||||
/**
|
||||
* @brief sdio data transfer mode
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
SDIO_DATA_BLOCK_TRANSFER = 0x00, /*!< the sdio block transfer mode */
|
||||
SDIO_DATA_STREAM_TRANSFER = 0x01 /*!< the sdio stream transfer mode */
|
||||
} sdio_transfer_mode_type;
|
||||
|
||||
/**
|
||||
* @brief sdio data transfer direction
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
SDIO_DATA_TRANSFER_TO_CARD = 0x00, /*!< the sdio controller write */
|
||||
SDIO_DATA_TRANSFER_TO_CONTROLLER = 0x01 /*!< the sdio controller read */
|
||||
} sdio_transfer_direction_type;
|
||||
|
||||
/**
|
||||
* @brief sdio read wait mode
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
SDIO_READ_WAIT_CONTROLLED_BY_D2 = 0x00, /*!< the sdio read wait on data2 line */
|
||||
SDIO_READ_WAIT_CONTROLLED_BY_CK = 0x01 /*!< the sdio read wait on clock line */
|
||||
} sdio_read_wait_mode_type;
|
||||
|
||||
/**
|
||||
* @brief sdio command structure
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t argument; /*!< the sdio command argument is sent to a card as part of command message */
|
||||
uint8_t cmd_index; /*!< the sdio command index */
|
||||
sdio_reponse_type rsp_type; /*!< the sdio response type */
|
||||
sdio_wait_type wait_type; /*!< the sdio wait for interrupt request is enabled or disable */
|
||||
} sdio_command_struct_type;
|
||||
|
||||
/**
|
||||
* @brief sdio data structure
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t timeout; /*!< the sdio data timeout period in car bus clock periods */
|
||||
uint32_t data_length; /*!< the sdio data length */
|
||||
sdio_block_size_type block_size; /*!< the sdio data block size of block transfer mode */
|
||||
sdio_transfer_mode_type transfer_mode; /*!< the sdio transfer mode, block or stream */
|
||||
sdio_transfer_direction_type transfer_direction; /*!< the sdio data transfer direction */
|
||||
} sdio_data_struct_type;
|
||||
|
||||
/**
|
||||
* @brief type define sdio register all
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
/**
|
||||
* @brief sdio pwrctrl register, offset:0x00
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t pwrctrl;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t ps : 2; /* [1:0] */
|
||||
__IO uint32_t reserved1 : 30;/* [31:2] */
|
||||
} pwrctrl_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief sdio clkctrl register, offset:0x04
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t clkctrl;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t clkdiv_l : 8; /* [7:0] */
|
||||
__IO uint32_t clkoen : 1; /* [8] */
|
||||
__IO uint32_t pwrsven : 1; /* [9] */
|
||||
__IO uint32_t bypsen : 1; /* [10] */
|
||||
__IO uint32_t busws : 2; /* [12:11] */
|
||||
__IO uint32_t clkegs : 1; /* [13] */
|
||||
__IO uint32_t hfcen : 1; /* [14] */
|
||||
__IO uint32_t clkdiv_h : 2; /* [16:15] */
|
||||
__IO uint32_t reserved1 : 15;/* [31:17] */
|
||||
} clkctrl_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief sdio argu register, offset:0x08
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t argu;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t argu : 32;/* [31:0] */
|
||||
} argu_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief sdio cmdctrl register, offset:0x0C
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t cmdctrl;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t cmdidx : 6; /* [5:0] */
|
||||
__IO uint32_t rspwt : 2; /* [7:6] */
|
||||
__IO uint32_t intwt : 1; /* [8] */
|
||||
__IO uint32_t pndwt : 1; /* [9] */
|
||||
__IO uint32_t ccsmen : 1; /* [10] */
|
||||
__IO uint32_t iosusp : 1; /* [11] */
|
||||
__IO uint32_t reserved1 : 20;/* [31:12] */
|
||||
} cmdctrl_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief sdio rspcmd register, offset:0x10
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t rspcmd;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t rspcmd : 6; /* [5:0] */
|
||||
__IO uint32_t reserved1 : 26;/* [31:6] */
|
||||
} rspcmd_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief sdio rsp1 register, offset:0x14
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t rsp1;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t cardsts1 : 32;/* [31:0] */
|
||||
} rsp1_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief sdio rsp2 register, offset:0x18
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t rsp2;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t cardsts2 : 32;/* [31:0] */
|
||||
} rsp2_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief sdio rsp3 register, offset:0x1C
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t rsp3;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t cardsts3 : 32;/* [31:0] */
|
||||
} rsp3_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief sdio rsp4 register, offset:0x20
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t rsp4;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t cardsts4 : 32;/* [31:0] */
|
||||
} rsp4_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief sdio dttmr register, offset:0x24
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t dttmr;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t timeout : 32;/* [31:0] */
|
||||
} dttmr_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief sdio dtlen register, offset:0x28
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t dtlen;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t dtlen : 25;/* [24:0] */
|
||||
__IO uint32_t reserved1 : 7; /* [31:25] */
|
||||
} dtlen_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief sdio dtctrl register, offset:0x2C
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t dtctrl;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t tfren : 1; /* [0] */
|
||||
__IO uint32_t tfrdir : 1; /* [1] */
|
||||
__IO uint32_t tfrmode : 1; /* [2] */
|
||||
__IO uint32_t dmaen : 1; /* [3] */
|
||||
__IO uint32_t blksize : 4; /* [7:4] */
|
||||
__IO uint32_t rdwtstart : 1; /* [8] */
|
||||
__IO uint32_t rdwtstop : 1; /* [9] */
|
||||
__IO uint32_t rdwtmode : 1; /* [10] */
|
||||
__IO uint32_t ioen : 1; /* [11] */
|
||||
__IO uint32_t reserved1 : 20;/* [31:12] */
|
||||
} dtctrl_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief sdio dtcnt register, offset:0x30
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t dtcnt;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t cnt : 25;/* [24:0] */
|
||||
__IO uint32_t reserved1 : 7; /* [31:25] */
|
||||
} dtcnt_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief sdio sts register, offset:0x34
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t sts;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t cmdfail : 1; /* [0] */
|
||||
__IO uint32_t dtfail : 1; /* [1] */
|
||||
__IO uint32_t cmdtimeout : 1; /* [2] */
|
||||
__IO uint32_t dttimeout : 1; /* [3] */
|
||||
__IO uint32_t txerru : 1; /* [4] */
|
||||
__IO uint32_t rxerro : 1; /* [5] */
|
||||
__IO uint32_t cmdrspcmpl : 1; /* [6] */
|
||||
__IO uint32_t cmdcmpl : 1; /* [7] */
|
||||
__IO uint32_t dtcmpl : 1; /* [8] */
|
||||
__IO uint32_t sbiterr : 1; /* [9] */
|
||||
__IO uint32_t dtblkcmpl : 1; /* [10] */
|
||||
__IO uint32_t docmd : 1; /* [11] */
|
||||
__IO uint32_t dotx : 1; /* [12] */
|
||||
__IO uint32_t dorx : 1; /* [13] */
|
||||
__IO uint32_t txbufh : 1; /* [14] */
|
||||
__IO uint32_t rxbufh : 1; /* [15] */
|
||||
__IO uint32_t txbuff : 1; /* [16] */
|
||||
__IO uint32_t rxbuff : 1; /* [17] */
|
||||
__IO uint32_t txbufe : 1; /* [18] */
|
||||
__IO uint32_t rxbufe : 1; /* [19] */
|
||||
__IO uint32_t txbuf : 1; /* [20] */
|
||||
__IO uint32_t rxbuf : 1; /* [21] */
|
||||
__IO uint32_t ioif : 1; /* [22] */
|
||||
__IO uint32_t reserved1 : 9; /* [31:23] */
|
||||
} sts_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief sdio intclr register, offset:0x38
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t intclr;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t cmdfail : 1; /* [0] */
|
||||
__IO uint32_t dtfail : 1; /* [1] */
|
||||
__IO uint32_t cmdtimeout : 1; /* [2] */
|
||||
__IO uint32_t dttimeout : 1; /* [3] */
|
||||
__IO uint32_t txerru : 1; /* [4] */
|
||||
__IO uint32_t rxerro : 1; /* [5] */
|
||||
__IO uint32_t cmdrspcmpl : 1; /* [6] */
|
||||
__IO uint32_t cmdcmpl : 1; /* [7] */
|
||||
__IO uint32_t dtcmpl : 1; /* [8] */
|
||||
__IO uint32_t sbiterr : 1; /* [9] */
|
||||
__IO uint32_t dtblkcmpl : 1; /* [10] */
|
||||
__IO uint32_t reserved1 : 11;/* [21:11] */
|
||||
__IO uint32_t ioif : 1; /* [22] */
|
||||
__IO uint32_t reserved2 : 9; /* [31:23] */
|
||||
} intclr_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief sdio inten register, offset:0x3C
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t inten;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t cmdfailien : 1; /* [0] */
|
||||
__IO uint32_t dtfailien : 1; /* [1] */
|
||||
__IO uint32_t cmdtimeoutien : 1; /* [2] */
|
||||
__IO uint32_t dttimeoutien : 1; /* [3] */
|
||||
__IO uint32_t txerruien : 1; /* [4] */
|
||||
__IO uint32_t rxerroien : 1; /* [5] */
|
||||
__IO uint32_t cmdrspcmplien : 1; /* [6] */
|
||||
__IO uint32_t cmdcmplien : 1; /* [7] */
|
||||
__IO uint32_t dtcmplien : 1; /* [8] */
|
||||
__IO uint32_t sbiterrien : 1; /* [9] */
|
||||
__IO uint32_t dtblkcmplien : 1; /* [10] */
|
||||
__IO uint32_t docmdien : 1; /* [11] */
|
||||
__IO uint32_t dotxien : 1; /* [12] */
|
||||
__IO uint32_t dorxien : 1; /* [13] */
|
||||
__IO uint32_t txbufhien : 1; /* [14] */
|
||||
__IO uint32_t rxbufhien : 1; /* [15] */
|
||||
__IO uint32_t txbuffien : 1; /* [16] */
|
||||
__IO uint32_t rxbuffien : 1; /* [17] */
|
||||
__IO uint32_t txbufeien : 1; /* [18] */
|
||||
__IO uint32_t rxbufeien : 1; /* [19] */
|
||||
__IO uint32_t txbufien : 1; /* [20] */
|
||||
__IO uint32_t rxbufien : 1; /* [21] */
|
||||
__IO uint32_t ioifien : 1; /* [22] */
|
||||
__IO uint32_t reserved1 : 9; /* [31:23] */
|
||||
} inten_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief sdio reserved1 register, offset:0x40~0x44
|
||||
*/
|
||||
__IO uint32_t reserved1[2];
|
||||
|
||||
/**
|
||||
* @brief sdio bufcnt register, offset:0x48
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t bufcnt;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t cnt : 24;/* [23:0] */
|
||||
__IO uint32_t reserved1 : 8; /* [31:24] */
|
||||
} bufcnt_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief sdio reserved2 register, offset:0x4C~0x7C
|
||||
*/
|
||||
__IO uint32_t reserved2[13];
|
||||
|
||||
/**
|
||||
* @brief sdio buf register, offset:0x80
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t buf;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t dt : 32;/* [31:0] */
|
||||
} buf_bit;
|
||||
};
|
||||
|
||||
} sdio_type;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#if defined (AT32F403ARx) || defined (AT32F403AVx) || defined (AT32F407Rx) || \
|
||||
defined (AT32F407Vx)
|
||||
#define SDIO1 ((sdio_type *) SDIO1_BASE)
|
||||
#endif
|
||||
#define SDIO2 ((sdio_type *) SDIO2_BASE)
|
||||
|
||||
/** @defgroup SDIO_exported_functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
void sdio_reset(sdio_type *sdio_x);
|
||||
void sdio_power_set(sdio_type *sdio_x, sdio_power_state_type power_state);
|
||||
sdio_power_state_type sdio_power_status_get(sdio_type *sdio_x);
|
||||
void sdio_clock_config(sdio_type *sdio_x, uint16_t clk_div, sdio_edge_phase_type clk_edg);
|
||||
void sdio_bus_width_config(sdio_type *sdio_x, sdio_bus_width_type width);
|
||||
void sdio_clock_bypass(sdio_type *sdio_x, confirm_state new_state);
|
||||
void sdio_power_saving_mode_enable(sdio_type *sdio_x, confirm_state new_state);
|
||||
void sdio_flow_control_enable(sdio_type *sdio_x, confirm_state new_state);
|
||||
void sdio_clock_enable(sdio_type *sdio_x, confirm_state new_state);
|
||||
void sdio_dma_enable(sdio_type *sdio_x, confirm_state new_state);
|
||||
void sdio_interrupt_enable(sdio_type *sdio_x, uint32_t int_opt, confirm_state new_state);
|
||||
flag_status sdio_flag_get(sdio_type *sdio_x, uint32_t flag);
|
||||
flag_status sdio_interrupt_flag_get(sdio_type *sdio_x, uint32_t flag);
|
||||
void sdio_flag_clear(sdio_type *sdio_x, uint32_t flag);
|
||||
void sdio_command_config(sdio_type *sdio_x, sdio_command_struct_type *command_struct);
|
||||
void sdio_command_state_machine_enable(sdio_type *sdio_x, confirm_state new_state);
|
||||
uint8_t sdio_command_response_get(sdio_type *sdio_x);
|
||||
uint32_t sdio_response_get(sdio_type *sdio_x, sdio_rsp_index_type reg_index);
|
||||
void sdio_data_config(sdio_type *sdio_x, sdio_data_struct_type *data_struct);
|
||||
void sdio_data_state_machine_enable(sdio_type *sdio_x, confirm_state new_state);
|
||||
uint32_t sdio_data_counter_get(sdio_type *sdio_x);
|
||||
uint32_t sdio_data_read(sdio_type *sdio_x);
|
||||
uint32_t sdio_buffer_counter_get(sdio_type *sdio_x);
|
||||
void sdio_data_write(sdio_type *sdio_x, uint32_t data);
|
||||
void sdio_read_wait_mode_set(sdio_type *sdio_x, sdio_read_wait_mode_type mode);
|
||||
void sdio_read_wait_start(sdio_type *sdio_x, confirm_state new_state);
|
||||
void sdio_read_wait_stop(sdio_type *sdio_x, confirm_state new_state);
|
||||
void sdio_io_function_enable(sdio_type *sdio_x, confirm_state new_state);
|
||||
void sdio_io_suspend_command_set(sdio_type *sdio_x, confirm_state new_state);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,499 @@
|
|||
/**
|
||||
**************************************************************************
|
||||
* @file at32f403a_407_spi.h
|
||||
* @brief at32f403a_407 spi header file
|
||||
**************************************************************************
|
||||
*
|
||||
* Copyright (c) 2025, Artery Technology, All rights reserved.
|
||||
*
|
||||
* The software Board Support Package (BSP) that is made available to
|
||||
* download from Artery official website is the copyrighted work of Artery.
|
||||
* Artery authorizes customers to use, copy, and distribute the BSP
|
||||
* software and its related documentation for the purpose of design and
|
||||
* development in conjunction with Artery microcontrollers. Use of the
|
||||
* software is governed by this copyright notice and the following disclaimer.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
|
||||
* GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
|
||||
* TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
|
||||
* STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
|
||||
* INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
|
||||
*
|
||||
**************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __AT32F403A_407_SPI_H
|
||||
#define __AT32F403A_407_SPI_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "at32f403a_407.h"
|
||||
|
||||
/** @addtogroup AT32F403A_407_periph_driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup SPI
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup SPI_I2S_flags_definition
|
||||
* @brief spi i2s flag
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define SPI_I2S_RDBF_FLAG 0x0001 /*!< spi or i2s receive data buffer full flag */
|
||||
#define SPI_I2S_TDBE_FLAG 0x0002 /*!< spi or i2s transmit data buffer empty flag */
|
||||
#define I2S_ACS_FLAG 0x0004 /*!< i2s audio channel state flag */
|
||||
#define I2S_TUERR_FLAG 0x0008 /*!< i2s transmitter underload error flag */
|
||||
#define SPI_CCERR_FLAG 0x0010 /*!< spi crc calculation error flag */
|
||||
#define SPI_MMERR_FLAG 0x0020 /*!< spi master mode error flag */
|
||||
#define SPI_I2S_ROERR_FLAG 0x0040 /*!< spi or i2s receiver overflow error flag */
|
||||
#define SPI_I2S_BF_FLAG 0x0080 /*!< spi or i2s busy flag */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @defgroup SPI_I2S_interrupts_definition
|
||||
* @brief spi i2s interrupt
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define SPI_I2S_ERROR_INT 0x0020 /*!< error interrupt */
|
||||
#define SPI_I2S_RDBF_INT 0x0040 /*!< receive data buffer full interrupt */
|
||||
#define SPI_I2S_TDBE_INT 0x0080 /*!< transmit data buffer empty interrupt */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SPI_exported_types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief spi frame bit num type
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
SPI_FRAME_8BIT = 0x00, /*!< 8-bit data frame format */
|
||||
SPI_FRAME_16BIT = 0x01 /*!< 16-bit data frame format */
|
||||
} spi_frame_bit_num_type;
|
||||
|
||||
/**
|
||||
* @brief spi master/slave mode type
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
SPI_MODE_SLAVE = 0x00, /*!< select as slave mode */
|
||||
SPI_MODE_MASTER = 0x01 /*!< select as master mode */
|
||||
} spi_master_slave_mode_type;
|
||||
|
||||
/**
|
||||
* @brief spi clock polarity (clkpol) type
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
SPI_CLOCK_POLARITY_LOW = 0x00, /*!< sck keeps low at idle state */
|
||||
SPI_CLOCK_POLARITY_HIGH = 0x01 /*!< sck keeps high at idle state */
|
||||
} spi_clock_polarity_type;
|
||||
|
||||
/**
|
||||
* @brief spi clock phase (clkpha) type
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
SPI_CLOCK_PHASE_1EDGE = 0x00, /*!< data capture start from the first clock edge */
|
||||
SPI_CLOCK_PHASE_2EDGE = 0x01 /*!< data capture start from the second clock edge */
|
||||
} spi_clock_phase_type;
|
||||
|
||||
/**
|
||||
* @brief spi cs mode type
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
SPI_CS_HARDWARE_MODE = 0x00, /*!< cs is hardware mode */
|
||||
SPI_CS_SOFTWARE_MODE = 0x01 /*!< cs is software mode */
|
||||
} spi_cs_mode_type;
|
||||
|
||||
/**
|
||||
* @brief spi master clock frequency division type
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
SPI_MCLK_DIV_2 = 0x00, /*!< master clock frequency division 2 */
|
||||
SPI_MCLK_DIV_4 = 0x01, /*!< master clock frequency division 4 */
|
||||
SPI_MCLK_DIV_8 = 0x02, /*!< master clock frequency division 8 */
|
||||
SPI_MCLK_DIV_16 = 0x03, /*!< master clock frequency division 16 */
|
||||
SPI_MCLK_DIV_32 = 0x04, /*!< master clock frequency division 32 */
|
||||
SPI_MCLK_DIV_64 = 0x05, /*!< master clock frequency division 64 */
|
||||
SPI_MCLK_DIV_128 = 0x06, /*!< master clock frequency division 128 */
|
||||
SPI_MCLK_DIV_256 = 0x07, /*!< master clock frequency division 256 */
|
||||
SPI_MCLK_DIV_512 = 0x08, /*!< master clock frequency division 512 */
|
||||
SPI_MCLK_DIV_1024 = 0x09 /*!< master clock frequency division 1024 */
|
||||
} spi_mclk_freq_div_type;
|
||||
|
||||
/**
|
||||
* @brief spi transmit first bit (lsb/msb) type
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
SPI_FIRST_BIT_MSB = 0x00, /*!< the frame format is msb first */
|
||||
SPI_FIRST_BIT_LSB = 0x01 /*!< the frame format is lsb first */
|
||||
} spi_first_bit_type;
|
||||
|
||||
/**
|
||||
* @brief spi transmission mode type
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
SPI_TRANSMIT_FULL_DUPLEX = 0x00, /*!< dual line unidirectional full-duplex mode(slben = 0 and ora = 0) */
|
||||
SPI_TRANSMIT_SIMPLEX_RX = 0x01, /*!< dual line unidirectional simplex receive-only mode(slben = 0 and ora = 1) */
|
||||
SPI_TRANSMIT_HALF_DUPLEX_RX = 0x02, /*!< single line bidirectional half duplex mode-receiving(slben = 1 and slbtd = 0) */
|
||||
SPI_TRANSMIT_HALF_DUPLEX_TX = 0x03 /*!< single line bidirectional half duplex mode-transmitting(slben = 1 and slbtd = 1) */
|
||||
} spi_transmission_mode_type;
|
||||
|
||||
/**
|
||||
* @brief spi crc direction type
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
SPI_CRC_RX = 0x0014, /*!< crc direction is rx */
|
||||
SPI_CRC_TX = 0x0018 /*!< crc direction is tx */
|
||||
} spi_crc_direction_type;
|
||||
|
||||
/**
|
||||
* @brief spi single line bidirectional direction type
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
SPI_HALF_DUPLEX_DIRECTION_RX = 0x00, /*!< single line bidirectional half duplex mode direction: receive(slbtd = 0) */
|
||||
SPI_HALF_DUPLEX_DIRECTION_TX = 0x01 /*!< single line bidirectional half duplex mode direction: transmit(slbtd = 1) */
|
||||
} spi_half_duplex_direction_type;
|
||||
|
||||
/**
|
||||
* @brief spi software cs internal level type
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
SPI_SWCS_INTERNAL_LEVEL_LOW = 0x00, /*!< internal level low */
|
||||
SPI_SWCS_INTERNAL_LEVEL_HIGHT = 0x01 /*!< internal level high */
|
||||
} spi_software_cs_level_type;
|
||||
|
||||
/**
|
||||
* @brief i2s audio protocol type
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
I2S_AUDIO_PROTOCOL_PHILLIPS = 0x00, /*!< i2s philip standard */
|
||||
I2S_AUDIO_PROTOCOL_MSB = 0x01, /*!< msb-justified standard */
|
||||
I2S_AUDIO_PROTOCOL_LSB = 0x02, /*!< lsb-justified standard */
|
||||
I2S_AUDIO_PROTOCOL_PCM_SHORT = 0x03, /*!< pcm standard-short frame */
|
||||
I2S_AUDIO_PROTOCOL_PCM_LONG = 0x04 /*!< pcm standard-long frame */
|
||||
} i2s_audio_protocol_type;
|
||||
|
||||
/**
|
||||
* @brief i2s audio frequency type
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
I2S_AUDIO_FREQUENCY_DEFAULT = 2, /*!< i2s audio sampling frequency default */
|
||||
I2S_AUDIO_FREQUENCY_8K = 8000, /*!< i2s audio sampling frequency 8k */
|
||||
I2S_AUDIO_FREQUENCY_11_025K = 11025, /*!< i2s audio sampling frequency 11.025k */
|
||||
I2S_AUDIO_FREQUENCY_16K = 16000, /*!< i2s audio sampling frequency 16k */
|
||||
I2S_AUDIO_FREQUENCY_22_05K = 22050, /*!< i2s audio sampling frequency 22.05k */
|
||||
I2S_AUDIO_FREQUENCY_32K = 32000, /*!< i2s audio sampling frequency 32k */
|
||||
I2S_AUDIO_FREQUENCY_44_1K = 44100, /*!< i2s audio sampling frequency 44.1k */
|
||||
I2S_AUDIO_FREQUENCY_48K = 48000, /*!< i2s audio sampling frequency 48k */
|
||||
I2S_AUDIO_FREQUENCY_96K = 96000, /*!< i2s audio sampling frequency 96k */
|
||||
I2S_AUDIO_FREQUENCY_192K = 192000 /*!< i2s audio sampling frequency 192k */
|
||||
} i2s_audio_sampling_freq_type;
|
||||
|
||||
/**
|
||||
* @brief i2s data bit num and channel bit num type
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
I2S_DATA_16BIT_CHANNEL_16BIT = 0x01, /*!< 16-bit data packed in 16-bit channel frame */
|
||||
I2S_DATA_16BIT_CHANNEL_32BIT = 0x02, /*!< 16-bit data packed in 32-bit channel frame */
|
||||
I2S_DATA_24BIT_CHANNEL_32BIT = 0x03, /*!< 24-bit data packed in 32-bit channel frame */
|
||||
I2S_DATA_32BIT_CHANNEL_32BIT = 0x04 /*!< 32-bit data packed in 32-bit channel frame */
|
||||
} i2s_data_channel_format_type;
|
||||
|
||||
/**
|
||||
* @brief i2s operation mode type
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
I2S_MODE_SLAVE_TX = 0x00, /*!< slave transmission mode */
|
||||
I2S_MODE_SLAVE_RX = 0x01, /*!< slave reception mode */
|
||||
I2S_MODE_MASTER_TX = 0x02, /*!< master transmission mode */
|
||||
I2S_MODE_MASTER_RX = 0x03 /*!< master reception mode */
|
||||
} i2s_operation_mode_type;
|
||||
|
||||
/**
|
||||
* @brief i2s clock polarity type
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
I2S_CLOCK_POLARITY_LOW = 0x00, /*!< i2s clock steady state is low level */
|
||||
I2S_CLOCK_POLARITY_HIGH = 0x01 /*!< i2s clock steady state is high level */
|
||||
} i2s_clock_polarity_type;
|
||||
|
||||
/**
|
||||
* @brief spi init type
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
spi_transmission_mode_type transmission_mode; /*!< transmission mode selection */
|
||||
spi_master_slave_mode_type master_slave_mode; /*!< master or slave mode selection */
|
||||
spi_mclk_freq_div_type mclk_freq_division; /*!< master clock frequency division selection */
|
||||
spi_first_bit_type first_bit_transmission;/*!< transmit lsb or msb selection */
|
||||
spi_frame_bit_num_type frame_bit_num; /*!< frame bit num 8 or 16 bit selection */
|
||||
spi_clock_polarity_type clock_polarity; /*!< clock polarity selection */
|
||||
spi_clock_phase_type clock_phase; /*!< clock phase selection */
|
||||
spi_cs_mode_type cs_mode_selection; /*!< hardware or software cs mode selection */
|
||||
} spi_init_type;
|
||||
|
||||
/**
|
||||
* @brief i2s init type
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
i2s_operation_mode_type operation_mode; /*!< operation mode selection */
|
||||
i2s_audio_protocol_type audio_protocol; /*!< audio protocol selection */
|
||||
i2s_audio_sampling_freq_type audio_sampling_freq; /*!< audio frequency selection */
|
||||
i2s_data_channel_format_type data_channel_format; /*!< data bit num and channel bit num selection */
|
||||
i2s_clock_polarity_type clock_polarity; /*!< clock polarity selection */
|
||||
confirm_state mclk_output_enable; /*!< mclk_output selection */
|
||||
} i2s_init_type;
|
||||
|
||||
/**
|
||||
* @brief type define spi register all
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
|
||||
/**
|
||||
* @brief spi ctrl1 register, offset:0x00
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t ctrl1;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t clkpha : 1; /* [0] */
|
||||
__IO uint32_t clkpol : 1; /* [1] */
|
||||
__IO uint32_t msten : 1; /* [2] */
|
||||
__IO uint32_t mdiv_l : 3; /* [5:3] */
|
||||
__IO uint32_t spien : 1; /* [6] */
|
||||
__IO uint32_t ltf : 1; /* [7] */
|
||||
__IO uint32_t swcsil : 1; /* [8] */
|
||||
__IO uint32_t swcsen : 1; /* [9] */
|
||||
__IO uint32_t ora : 1; /* [10] */
|
||||
__IO uint32_t fbn : 1; /* [11] */
|
||||
__IO uint32_t ntc : 1; /* [12] */
|
||||
__IO uint32_t ccen : 1; /* [13] */
|
||||
__IO uint32_t slbtd : 1; /* [14] */
|
||||
__IO uint32_t slben : 1; /* [15] */
|
||||
__IO uint32_t reserved1 : 16;/* [31:16] */
|
||||
} ctrl1_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief spi ctrl2 register, offset:0x04
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t ctrl2;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t dmaren : 1; /* [0] */
|
||||
__IO uint32_t dmaten : 1; /* [1] */
|
||||
__IO uint32_t hwcsoe : 1; /* [2] */
|
||||
__IO uint32_t reserved1 : 2; /* [4:3] */
|
||||
__IO uint32_t errie : 1; /* [5] */
|
||||
__IO uint32_t rdbfie : 1; /* [6] */
|
||||
__IO uint32_t tdbeie : 1; /* [7] */
|
||||
__IO uint32_t mdiv_h : 1; /* [8] */
|
||||
__IO uint32_t reserved2 : 23;/* [31:9] */
|
||||
} ctrl2_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief spi sts register, offset:0x08
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t sts;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t rdbf : 1; /* [0] */
|
||||
__IO uint32_t tdbe : 1; /* [1] */
|
||||
__IO uint32_t acs : 1; /* [2] */
|
||||
__IO uint32_t tuerr : 1; /* [3] */
|
||||
__IO uint32_t ccerr : 1; /* [4] */
|
||||
__IO uint32_t mmerr : 1; /* [5] */
|
||||
__IO uint32_t roerr : 1; /* [6] */
|
||||
__IO uint32_t bf : 1; /* [7] */
|
||||
__IO uint32_t reserved1 : 24;/* [31:8] */
|
||||
} sts_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief spi dt register, offset:0x0C
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t dt;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t dt : 16;/* [15:0] */
|
||||
__IO uint32_t reserved1 : 16;/* [31:16] */
|
||||
} dt_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief spi cpoly register, offset:0x10
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t cpoly;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t cpoly : 16;/* [15:0] */
|
||||
__IO uint32_t reserved1 : 16;/* [31:16] */
|
||||
} cpoly_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief spi rcrc register, offset:0x14
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t rcrc;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t rcrc : 16;/* [15:0] */
|
||||
__IO uint32_t reserved1 : 16;/* [31:16] */
|
||||
} rcrc_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief spi tcrc register, offset:0x18
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t tcrc;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t tcrc : 16;/* [15:0] */
|
||||
__IO uint32_t reserved1 : 16;/* [31:16] */
|
||||
} tcrc_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief spi i2sctrl register, offset:0x1C
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t i2sctrl;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t i2scbn : 1; /* [0] */
|
||||
__IO uint32_t i2sdbn : 2; /* [2:1] */
|
||||
__IO uint32_t i2sclkpol : 1; /* [3] */
|
||||
__IO uint32_t stdsel : 2; /* [5:4] */
|
||||
__IO uint32_t reserved1 : 1; /* [6] */
|
||||
__IO uint32_t pcmfssel : 1; /* [7] */
|
||||
__IO uint32_t opersel : 2; /* [9:8] */
|
||||
__IO uint32_t i2sen : 1; /* [10] */
|
||||
__IO uint32_t i2smsel : 1; /* [11] */
|
||||
__IO uint32_t reserved2 : 20;/* [31:12] */
|
||||
} i2sctrl_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief spi i2sclk register, offset:0x20
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t i2sclk;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t i2sdiv_l : 8; /* [7:0] */
|
||||
__IO uint32_t i2sodd : 1; /* [8] */
|
||||
__IO uint32_t i2smclkoe : 1; /* [9] */
|
||||
__IO uint32_t i2sdiv_h : 2; /* [11:10] */
|
||||
__IO uint32_t reserved1 : 20;/* [31:12] */
|
||||
} i2sclk_bit;
|
||||
};
|
||||
|
||||
} spi_type;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#define SPI1 ((spi_type *) SPI1_BASE)
|
||||
#define SPI2 ((spi_type *) SPI2_BASE)
|
||||
#define SPI3 ((spi_type *) SPI3_BASE)
|
||||
#define SPI4 ((spi_type *) SPI4_BASE)
|
||||
#define I2S2EXT ((spi_type *) I2S2EXT_BASE)
|
||||
#define I2S3EXT ((spi_type *) I2S3EXT_BASE)
|
||||
|
||||
/** @defgroup SPI_exported_functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
void spi_i2s_reset(spi_type *spi_x);
|
||||
void spi_default_para_init(spi_init_type* spi_init_struct);
|
||||
void spi_init(spi_type* spi_x, spi_init_type* spi_init_struct);
|
||||
void spi_crc_next_transmit(spi_type* spi_x);
|
||||
void spi_crc_polynomial_set(spi_type* spi_x, uint16_t crc_poly);
|
||||
uint16_t spi_crc_polynomial_get(spi_type* spi_x);
|
||||
void spi_crc_enable(spi_type* spi_x, confirm_state new_state);
|
||||
uint16_t spi_crc_value_get(spi_type* spi_x, spi_crc_direction_type crc_direction);
|
||||
void spi_hardware_cs_output_enable(spi_type* spi_x, confirm_state new_state);
|
||||
void spi_software_cs_internal_level_set(spi_type* spi_x, spi_software_cs_level_type level);
|
||||
void spi_frame_bit_num_set(spi_type* spi_x, spi_frame_bit_num_type bit_num);
|
||||
void spi_half_duplex_direction_set(spi_type* spi_x, spi_half_duplex_direction_type direction);
|
||||
void spi_enable(spi_type* spi_x, confirm_state new_state);
|
||||
void i2s_default_para_init(i2s_init_type* i2s_init_struct);
|
||||
void i2s_init(spi_type* spi_x, i2s_init_type* i2s_init_struct);
|
||||
void i2s_enable(spi_type* spi_x, confirm_state new_state);
|
||||
void spi_i2s_interrupt_enable(spi_type* spi_x, uint32_t spi_i2s_int, confirm_state new_state);
|
||||
void spi_i2s_dma_transmitter_enable(spi_type* spi_x, confirm_state new_state);
|
||||
void spi_i2s_dma_receiver_enable(spi_type* spi_x, confirm_state new_state);
|
||||
void spi_i2s_data_transmit(spi_type* spi_x, uint16_t tx_data);
|
||||
uint16_t spi_i2s_data_receive(spi_type* spi_x);
|
||||
flag_status spi_i2s_flag_get(spi_type* spi_x, uint32_t spi_i2s_flag);
|
||||
flag_status spi_i2s_interrupt_flag_get(spi_type* spi_x, uint32_t spi_i2s_flag);
|
||||
void spi_i2s_flag_clear(spi_type* spi_x, uint32_t spi_i2s_flag);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,941 @@
|
|||
/**
|
||||
**************************************************************************
|
||||
* @file at32f403a_407_tmr.h
|
||||
* @brief at32f403a_407 tmr header file
|
||||
**************************************************************************
|
||||
*
|
||||
* Copyright (c) 2025, Artery Technology, All rights reserved.
|
||||
*
|
||||
* The software Board Support Package (BSP) that is made available to
|
||||
* download from Artery official website is the copyrighted work of Artery.
|
||||
* Artery authorizes customers to use, copy, and distribute the BSP
|
||||
* software and its related documentation for the purpose of design and
|
||||
* development in conjunction with Artery microcontrollers. Use of the
|
||||
* software is governed by this copyright notice and the following disclaimer.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
|
||||
* GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
|
||||
* TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
|
||||
* STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
|
||||
* INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
|
||||
*
|
||||
**************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __AT32F403A_407_TMR_H
|
||||
#define __AT32F403A_407_TMR_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "at32f403a_407.h"
|
||||
|
||||
/** @addtogroup AT32F403A_407_periph_driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup TMR
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup TMR_flags_definition
|
||||
* @brief tmr flag
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define TMR_OVF_FLAG ((uint32_t)0x000001) /*!< tmr flag overflow */
|
||||
#define TMR_C1_FLAG ((uint32_t)0x000002) /*!< tmr flag channel 1 */
|
||||
#define TMR_C2_FLAG ((uint32_t)0x000004) /*!< tmr flag channel 2 */
|
||||
#define TMR_C3_FLAG ((uint32_t)0x000008) /*!< tmr flag channel 3 */
|
||||
#define TMR_C4_FLAG ((uint32_t)0x000010) /*!< tmr flag channel 4 */
|
||||
#define TMR_HALL_FLAG ((uint32_t)0x000020) /*!< tmr flag hall */
|
||||
#define TMR_TRIGGER_FLAG ((uint32_t)0x000040) /*!< tmr flag trigger */
|
||||
#define TMR_BRK_FLAG ((uint32_t)0x000080) /*!< tmr flag brake */
|
||||
#define TMR_C1_RECAPTURE_FLAG ((uint32_t)0x000200) /*!< tmr flag channel 1 recapture */
|
||||
#define TMR_C2_RECAPTURE_FLAG ((uint32_t)0x000400) /*!< tmr flag channel 2 recapture */
|
||||
#define TMR_C3_RECAPTURE_FLAG ((uint32_t)0x000800) /*!< tmr flag channel 3 recapture */
|
||||
#define TMR_C4_RECAPTURE_FLAG ((uint32_t)0x001000) /*!< tmr flag channel 4 recapture */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup TMR_interrupt_select_type_definition
|
||||
* @brief tmr interrupt select type
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define TMR_OVF_INT ((uint32_t)0x000001) /*!< tmr interrupt overflow */
|
||||
#define TMR_C1_INT ((uint32_t)0x000002) /*!< tmr interrupt channel 1 */
|
||||
#define TMR_C2_INT ((uint32_t)0x000004) /*!< tmr interrupt channel 2 */
|
||||
#define TMR_C3_INT ((uint32_t)0x000008) /*!< tmr interrupt channel 3 */
|
||||
#define TMR_C4_INT ((uint32_t)0x000010) /*!< tmr interrupt channel 4 */
|
||||
#define TMR_HALL_INT ((uint32_t)0x000020) /*!< tmr interrupt hall */
|
||||
#define TMR_TRIGGER_INT ((uint32_t)0x000040) /*!< tmr interrupt trigger */
|
||||
#define TMR_BRK_INT ((uint32_t)0x000080) /*!< tmr interrupt brake */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup TMR_exported_types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief tmr clock division type
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
TMR_CLOCK_DIV1 = 0x00, /*!< tmr clock division 1 */
|
||||
TMR_CLOCK_DIV2 = 0x01, /*!< tmr clock division 2 */
|
||||
TMR_CLOCK_DIV4 = 0x02 /*!< tmr clock division 4 */
|
||||
} tmr_clock_division_type;
|
||||
|
||||
/**
|
||||
* @brief tmr counter mode type
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
TMR_COUNT_UP = 0x00, /*!< tmr counter mode up */
|
||||
TMR_COUNT_DOWN = 0x01, /*!< tmr counter mode down */
|
||||
TMR_COUNT_TWO_WAY_1 = 0x02, /*!< tmr counter mode two way 1 */
|
||||
TMR_COUNT_TWO_WAY_2 = 0x04, /*!< tmr counter mode two way 2 */
|
||||
TMR_COUNT_TWO_WAY_3 = 0x06 /*!< tmr counter mode two way 3 */
|
||||
} tmr_count_mode_type;
|
||||
|
||||
/**
|
||||
* @brief tmr primary mode select type
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
TMR_PRIMARY_SEL_RESET = 0x00, /*!< tmr primary mode select reset */
|
||||
TMR_PRIMARY_SEL_ENABLE = 0x01, /*!< tmr primary mode select enable */
|
||||
TMR_PRIMARY_SEL_OVERFLOW = 0x02, /*!< tmr primary mode select overflow */
|
||||
TMR_PRIMARY_SEL_COMPARE = 0x03, /*!< tmr primary mode select compare */
|
||||
TMR_PRIMARY_SEL_C1ORAW = 0x04, /*!< tmr primary mode select c1oraw */
|
||||
TMR_PRIMARY_SEL_C2ORAW = 0x05, /*!< tmr primary mode select c2oraw */
|
||||
TMR_PRIMARY_SEL_C3ORAW = 0x06, /*!< tmr primary mode select c3oraw */
|
||||
TMR_PRIMARY_SEL_C4ORAW = 0x07 /*!< tmr primary mode select c4oraw */
|
||||
} tmr_primary_select_type;
|
||||
|
||||
/**
|
||||
* @brief tmr subordinate mode input select type
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
TMR_SUB_INPUT_SEL_IS0 = 0x00, /*!< subordinate mode input select is0 */
|
||||
TMR_SUB_INPUT_SEL_IS1 = 0x01, /*!< subordinate mode input select is1 */
|
||||
TMR_SUB_INPUT_SEL_IS2 = 0x02, /*!< subordinate mode input select is2 */
|
||||
TMR_SUB_INPUT_SEL_IS3 = 0x03, /*!< subordinate mode input select is3 */
|
||||
TMR_SUB_INPUT_SEL_C1INC = 0x04, /*!< subordinate mode input select c1inc */
|
||||
TMR_SUB_INPUT_SEL_C1DF1 = 0x05, /*!< subordinate mode input select c1df1 */
|
||||
TMR_SUB_INPUT_SEL_C2DF2 = 0x06, /*!< subordinate mode input select c2df2 */
|
||||
TMR_SUB_INPUT_SEL_EXTIN = 0x07 /*!< subordinate mode input select extin */
|
||||
} sub_tmr_input_sel_type;
|
||||
|
||||
/**
|
||||
* @brief tmr subordinate mode select type
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
TMR_SUB_MODE_DIABLE = 0x00, /*!< subordinate mode disable */
|
||||
TMR_SUB_ENCODER_MODE_A = 0x01, /*!< subordinate mode select encoder mode a */
|
||||
TMR_SUB_ENCODER_MODE_B = 0x02, /*!< subordinate mode select encoder mode b */
|
||||
TMR_SUB_ENCODER_MODE_C = 0x03, /*!< subordinate mode select encoder mode c */
|
||||
TMR_SUB_RESET_MODE = 0x04, /*!< subordinate mode select reset */
|
||||
TMR_SUB_HANG_MODE = 0x05, /*!< subordinate mode select hang */
|
||||
TMR_SUB_TRIGGER_MODE = 0x06, /*!< subordinate mode select trigger */
|
||||
TMR_SUB_EXTERNAL_CLOCK_MODE_A = 0x07 /*!< subordinate mode external clock mode a */
|
||||
} tmr_sub_mode_select_type;
|
||||
|
||||
/**
|
||||
* @brief tmr encoder mode type
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
TMR_ENCODER_MODE_A = TMR_SUB_ENCODER_MODE_A, /*!< tmr encoder mode a */
|
||||
TMR_ENCODER_MODE_B = TMR_SUB_ENCODER_MODE_B, /*!< tmr encoder mode b */
|
||||
TMR_ENCODER_MODE_C = TMR_SUB_ENCODER_MODE_C /*!< tmr encoder mode c */
|
||||
} tmr_encoder_mode_type;
|
||||
|
||||
/**
|
||||
* @brief tmr output control mode type
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
TMR_OUTPUT_CONTROL_OFF = 0x00, /*!< tmr output control mode off */
|
||||
TMR_OUTPUT_CONTROL_HIGH = 0x01, /*!< tmr output control mode high */
|
||||
TMR_OUTPUT_CONTROL_LOW = 0x02, /*!< tmr output control mode low */
|
||||
TMR_OUTPUT_CONTROL_SWITCH = 0x03, /*!< tmr output control mode switch */
|
||||
TMR_OUTPUT_CONTROL_FORCE_LOW = 0x04, /*!< tmr output control mode force low */
|
||||
TMR_OUTPUT_CONTROL_FORCE_HIGH = 0x05, /*!< tmr output control mode force high */
|
||||
TMR_OUTPUT_CONTROL_PWM_MODE_A = 0x06, /*!< tmr output control mode pwm a */
|
||||
TMR_OUTPUT_CONTROL_PWM_MODE_B = 0x07 /*!< tmr output control mode pwm b */
|
||||
} tmr_output_control_mode_type;
|
||||
|
||||
/**
|
||||
* @brief tmr force output type
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
TMR_FORCE_OUTPUT_HIGH = TMR_OUTPUT_CONTROL_FORCE_HIGH, /*!< tmr force output high */
|
||||
TMR_FORCE_OUTPUT_LOW = TMR_OUTPUT_CONTROL_FORCE_LOW /*!< tmr force output low */
|
||||
} tmr_force_output_type;
|
||||
|
||||
/**
|
||||
* @brief tmr output channel polarity type
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
TMR_OUTPUT_ACTIVE_HIGH = 0x00, /*!< tmr output channel polarity high */
|
||||
TMR_OUTPUT_ACTIVE_LOW = 0x01 /*!< tmr output channel polarity low */
|
||||
} tmr_output_polarity_type;
|
||||
|
||||
/**
|
||||
* @brief tmr input channel polarity type
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
TMR_INPUT_RISING_EDGE = 0x00, /*!< tmr input channel polarity rising */
|
||||
TMR_INPUT_FALLING_EDGE = 0x01, /*!< tmr input channel polarity falling */
|
||||
TMR_INPUT_BOTH_EDGE = 0x03 /*!< tmr input channel polarity both edge */
|
||||
} tmr_input_polarity_type;
|
||||
|
||||
/**
|
||||
* @brief tmr channel select type
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
TMR_SELECT_CHANNEL_1 = 0x00, /*!< tmr channel select channel 1 */
|
||||
TMR_SELECT_CHANNEL_1C = 0x01, /*!< tmr channel select channel 1 complementary */
|
||||
TMR_SELECT_CHANNEL_2 = 0x02, /*!< tmr channel select channel 2 */
|
||||
TMR_SELECT_CHANNEL_2C = 0x03, /*!< tmr channel select channel 2 complementary */
|
||||
TMR_SELECT_CHANNEL_3 = 0x04, /*!< tmr channel select channel 3 */
|
||||
TMR_SELECT_CHANNEL_3C = 0x05, /*!< tmr channel select channel 3 complementary */
|
||||
TMR_SELECT_CHANNEL_4 = 0x06 /*!< tmr channel select channel 4 */
|
||||
} tmr_channel_select_type;
|
||||
|
||||
/**
|
||||
* @brief tmr channel1 input connected type
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
TMR_CHANEL1_CONNECTED_C1IRAW = 0x00, /*!< channel1 pins is only connected to C1IRAW input */
|
||||
TMR_CHANEL1_2_3_CONNECTED_C1IRAW_XOR = 0x01 /*!< channel1/2/3 pins are connected to C1IRAW input after xored */
|
||||
} tmr_channel1_input_connected_type;
|
||||
|
||||
/**
|
||||
* @brief tmr input channel mapped type channel direction
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
TMR_CC_CHANNEL_MAPPED_DIRECT = 0x01, /*!< channel is configured as input, mapped direct */
|
||||
TMR_CC_CHANNEL_MAPPED_INDIRECT = 0x02, /*!< channel is configured as input, mapped indirect */
|
||||
TMR_CC_CHANNEL_MAPPED_STI = 0x03 /*!< channel is configured as input, mapped sti */
|
||||
} tmr_input_direction_mapped_type;
|
||||
|
||||
/**
|
||||
* @brief tmr input divider type
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
TMR_CHANNEL_INPUT_DIV_1 = 0x00, /*!< tmr channel input divider 1 */
|
||||
TMR_CHANNEL_INPUT_DIV_2 = 0x01, /*!< tmr channel input divider 2 */
|
||||
TMR_CHANNEL_INPUT_DIV_4 = 0x02, /*!< tmr channel input divider 4 */
|
||||
TMR_CHANNEL_INPUT_DIV_8 = 0x03 /*!< tmr channel input divider 8 */
|
||||
} tmr_channel_input_divider_type;
|
||||
|
||||
/**
|
||||
* @brief tmr dma request source select type
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
TMR_DMA_REQUEST_BY_CHANNEL = 0x00, /*!< tmr dma request source select channel */
|
||||
TMR_DMA_REQUEST_BY_OVERFLOW = 0x01 /*!< tmr dma request source select overflow */
|
||||
} tmr_dma_request_source_type;
|
||||
|
||||
/**
|
||||
* @brief tmr dma request type
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
TMR_OVERFLOW_DMA_REQUEST = 0x00000100, /*!< tmr dma request select overflow */
|
||||
TMR_C1_DMA_REQUEST = 0x00000200, /*!< tmr dma request select channel 1 */
|
||||
TMR_C2_DMA_REQUEST = 0x00000400, /*!< tmr dma request select channel 2 */
|
||||
TMR_C3_DMA_REQUEST = 0x00000800, /*!< tmr dma request select channel 3 */
|
||||
TMR_C4_DMA_REQUEST = 0x00001000, /*!< tmr dma request select channel 4 */
|
||||
TMR_HALL_DMA_REQUEST = 0x00002000, /*!< tmr dma request select hall */
|
||||
TMR_TRIGGER_DMA_REQUEST = 0x00004000 /*!< tmr dma request select trigger */
|
||||
} tmr_dma_request_type;
|
||||
|
||||
/**
|
||||
* @brief tmr event triggered by software type
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
TMR_OVERFLOW_SWTRIG = 0x00000001, /*!< tmr event triggered by software of overflow */
|
||||
TMR_C1_SWTRIG = 0x00000002, /*!< tmr event triggered by software of channel 1 */
|
||||
TMR_C2_SWTRIG = 0x00000004, /*!< tmr event triggered by software of channel 2 */
|
||||
TMR_C3_SWTRIG = 0x00000008, /*!< tmr event triggered by software of channel 3 */
|
||||
TMR_C4_SWTRIG = 0x00000010, /*!< tmr event triggered by software of channel 4 */
|
||||
TMR_HALL_SWTRIG = 0x00000020, /*!< tmr event triggered by software of hall */
|
||||
TMR_TRIGGER_SWTRIG = 0x00000040, /*!< tmr event triggered by software of trigger */
|
||||
TMR_BRK_SWTRIG = 0x00000080 /*!< tmr event triggered by software of brake */
|
||||
}tmr_event_trigger_type;
|
||||
|
||||
/**
|
||||
* @brief tmr polarity active type
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
TMR_POLARITY_ACTIVE_HIGH = 0x00, /*!< tmr polarity active high */
|
||||
TMR_POLARITY_ACTIVE_LOW = 0x01, /*!< tmr polarity active low */
|
||||
TMR_POLARITY_ACTIVE_BOTH = 0x02 /*!< tmr polarity active both high ande low */
|
||||
}tmr_polarity_active_type;
|
||||
|
||||
/**
|
||||
* @brief tmr external signal divider type
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
TMR_ES_FREQUENCY_DIV_1 = 0x00, /*!< tmr external signal frequency divider 1 */
|
||||
TMR_ES_FREQUENCY_DIV_2 = 0x01, /*!< tmr external signal frequency divider 2 */
|
||||
TMR_ES_FREQUENCY_DIV_4 = 0x02, /*!< tmr external signal frequency divider 4 */
|
||||
TMR_ES_FREQUENCY_DIV_8 = 0x03 /*!< tmr external signal frequency divider 8 */
|
||||
}tmr_external_signal_divider_type;
|
||||
|
||||
/**
|
||||
* @brief tmr external signal polarity type
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
TMR_ES_POLARITY_NON_INVERTED = 0x00, /*!< tmr external signal polarity non-inerted */
|
||||
TMR_ES_POLARITY_INVERTED = 0x01 /*!< tmr external signal polarity inerted */
|
||||
}tmr_external_signal_polarity_type;
|
||||
|
||||
/**
|
||||
* @brief tmr dma transfer length type
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
TMR_DMA_TRANSFER_1BYTE = 0x00, /*!< tmr dma transfer length 1 byte */
|
||||
TMR_DMA_TRANSFER_2BYTES = 0x01, /*!< tmr dma transfer length 2 bytes */
|
||||
TMR_DMA_TRANSFER_3BYTES = 0x02, /*!< tmr dma transfer length 3 bytes */
|
||||
TMR_DMA_TRANSFER_4BYTES = 0x03, /*!< tmr dma transfer length 4 bytes */
|
||||
TMR_DMA_TRANSFER_5BYTES = 0x04, /*!< tmr dma transfer length 5 bytes */
|
||||
TMR_DMA_TRANSFER_6BYTES = 0x05, /*!< tmr dma transfer length 6 bytes */
|
||||
TMR_DMA_TRANSFER_7BYTES = 0x06, /*!< tmr dma transfer length 7 bytes */
|
||||
TMR_DMA_TRANSFER_8BYTES = 0x07, /*!< tmr dma transfer length 8 bytes */
|
||||
TMR_DMA_TRANSFER_9BYTES = 0x08, /*!< tmr dma transfer length 9 bytes */
|
||||
TMR_DMA_TRANSFER_10BYTES = 0x09, /*!< tmr dma transfer length 10 bytes */
|
||||
TMR_DMA_TRANSFER_11BYTES = 0x0A, /*!< tmr dma transfer length 11 bytes */
|
||||
TMR_DMA_TRANSFER_12BYTES = 0x0B, /*!< tmr dma transfer length 12 bytes */
|
||||
TMR_DMA_TRANSFER_13BYTES = 0x0C, /*!< tmr dma transfer length 13 bytes */
|
||||
TMR_DMA_TRANSFER_14BYTES = 0x0D, /*!< tmr dma transfer length 14 bytes */
|
||||
TMR_DMA_TRANSFER_15BYTES = 0x0E, /*!< tmr dma transfer length 15 bytes */
|
||||
TMR_DMA_TRANSFER_16BYTES = 0x0F, /*!< tmr dma transfer length 16 bytes */
|
||||
TMR_DMA_TRANSFER_17BYTES = 0x10, /*!< tmr dma transfer length 17 bytes */
|
||||
TMR_DMA_TRANSFER_18BYTES = 0x11 /*!< tmr dma transfer length 18 bytes */
|
||||
}tmr_dma_transfer_length_type;
|
||||
|
||||
/**
|
||||
* @brief tmr dma base address type
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
TMR_CTRL1_ADDRESS = 0x0000, /*!< tmr dma base address ctrl1 */
|
||||
TMR_CTRL2_ADDRESS = 0x0001, /*!< tmr dma base address ctrl2 */
|
||||
TMR_STCTRL_ADDRESS = 0x0002, /*!< tmr dma base address stctrl */
|
||||
TMR_IDEN_ADDRESS = 0x0003, /*!< tmr dma base address iden */
|
||||
TMR_ISTS_ADDRESS = 0x0004, /*!< tmr dma base address ists */
|
||||
TMR_SWEVT_ADDRESS = 0x0005, /*!< tmr dma base address swevt */
|
||||
TMR_CM1_ADDRESS = 0x0006, /*!< tmr dma base address cm1 */
|
||||
TMR_CM2_ADDRESS = 0x0007, /*!< tmr dma base address cm2 */
|
||||
TMR_CCTRL_ADDRESS = 0x0008, /*!< tmr dma base address cctrl */
|
||||
TMR_CVAL_ADDRESS = 0x0009, /*!< tmr dma base address cval */
|
||||
TMR_DIV_ADDRESS = 0x000A, /*!< tmr dma base address div */
|
||||
TMR_PR_ADDRESS = 0x000B, /*!< tmr dma base address pr */
|
||||
TMR_RPR_ADDRESS = 0x000C, /*!< tmr dma base address rpr */
|
||||
TMR_C1DT_ADDRESS = 0x000D, /*!< tmr dma base address c1dt */
|
||||
TMR_C2DT_ADDRESS = 0x000E, /*!< tmr dma base address c2dt */
|
||||
TMR_C3DT_ADDRESS = 0x000F, /*!< tmr dma base address c3dt */
|
||||
TMR_C4DT_ADDRESS = 0x0010, /*!< tmr dma base address c4dt */
|
||||
TMR_BRK_ADDRESS = 0x0011, /*!< tmr dma base address brake */
|
||||
TMR_DMACTRL_ADDRESS = 0x0012 /*!< tmr dma base address dmactrl */
|
||||
}tmr_dma_address_type;
|
||||
|
||||
/**
|
||||
* @brief tmr brk polarity type
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
TMR_BRK_INPUT_ACTIVE_LOW = 0x00, /*!< tmr brk input channel active low */
|
||||
TMR_BRK_INPUT_ACTIVE_HIGH = 0x01 /*!< tmr brk input channel active high */
|
||||
}tmr_brk_polarity_type;
|
||||
|
||||
/**
|
||||
* @brief tmr write protect level type
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
TMR_WP_OFF = 0x00, /*!< tmr write protect off */
|
||||
TMR_WP_LEVEL_3 = 0x01, /*!< tmr write protect level 3 */
|
||||
TMR_WP_LEVEL_2 = 0x02, /*!< tmr write protect level 2 */
|
||||
TMR_WP_LEVEL_1 = 0x03 /*!< tmr write protect level 1 */
|
||||
}tmr_wp_level_type;
|
||||
|
||||
/**
|
||||
* @brief tmr output config type
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
tmr_output_control_mode_type oc_mode; /*!< output channel mode */
|
||||
confirm_state oc_idle_state; /*!< output channel idle state */
|
||||
confirm_state occ_idle_state; /*!< output channel complementary idle state */
|
||||
tmr_output_polarity_type oc_polarity; /*!< output channel polarity */
|
||||
tmr_output_polarity_type occ_polarity; /*!< output channel complementary polarity */
|
||||
confirm_state oc_output_state; /*!< output channel enable */
|
||||
confirm_state occ_output_state; /*!< output channel complementary enable */
|
||||
} tmr_output_config_type;
|
||||
|
||||
/**
|
||||
* @brief tmr input capture config type
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
tmr_channel_select_type input_channel_select; /*!< tmr input channel select */
|
||||
tmr_input_polarity_type input_polarity_select; /*!< tmr input polarity select */
|
||||
tmr_input_direction_mapped_type input_mapped_select; /*!< tmr channel mapped direct or indirect */
|
||||
uint8_t input_filter_value; /*!< tmr channel filter value */
|
||||
} tmr_input_config_type;
|
||||
|
||||
/**
|
||||
* @brief tmr brkdt config type
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint8_t deadtime; /*!< dead-time generator setup */
|
||||
tmr_brk_polarity_type brk_polarity; /*!< tmr brake polarity */
|
||||
tmr_wp_level_type wp_level; /*!< write protect configuration */
|
||||
confirm_state auto_output_enable; /*!< automatic output enable */
|
||||
confirm_state fcsoen_state; /*!< frozen channel status when output enable */
|
||||
confirm_state fcsodis_state; /*!< frozen channel status when output disable */
|
||||
confirm_state brk_enable; /*!< tmr brk enale */
|
||||
} tmr_brkdt_config_type;
|
||||
|
||||
/**
|
||||
* @brief type define tmr register all
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
/**
|
||||
* @brief tmr ctrl1 register, offset:0x00
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t ctrl1;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t tmren : 1; /* [0] */
|
||||
__IO uint32_t ovfen : 1; /* [1] */
|
||||
__IO uint32_t ovfs : 1; /* [2] */
|
||||
__IO uint32_t ocmen : 1; /* [3] */
|
||||
__IO uint32_t cnt_dir : 3; /* [6:4] */
|
||||
__IO uint32_t prben : 1; /* [7] */
|
||||
__IO uint32_t clkdiv : 2; /* [9:8] */
|
||||
__IO uint32_t pmen : 1; /* [10] */
|
||||
__IO uint32_t reserved1 : 21;/* [31:11] */
|
||||
} ctrl1_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief tmr ctrl2 register, offset:0x04
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t ctrl2;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t cbctrl : 1; /* [0] */
|
||||
__IO uint32_t reserved1 : 1; /* [1] */
|
||||
__IO uint32_t ccfs : 1; /* [2] */
|
||||
__IO uint32_t drs : 1; /* [3] */
|
||||
__IO uint32_t ptos : 3; /* [6:4] */
|
||||
__IO uint32_t c1insel : 1; /* [7] */
|
||||
__IO uint32_t c1ios : 1; /* [8] */
|
||||
__IO uint32_t c1cios : 1; /* [9] */
|
||||
__IO uint32_t c2ios : 1; /* [10] */
|
||||
__IO uint32_t c2cios : 1; /* [11] */
|
||||
__IO uint32_t c3ios : 1; /* [12] */
|
||||
__IO uint32_t c3cios : 1; /* [13] */
|
||||
__IO uint32_t c4ios : 1; /* [14] */
|
||||
__IO uint32_t reserved2 : 17;/* [31:15] */
|
||||
} ctrl2_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief tmr smc register, offset:0x08
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t stctrl;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t smsel : 3; /* [2:0] */
|
||||
__IO uint32_t reserved1 : 1; /* [3] */
|
||||
__IO uint32_t stis : 3; /* [6:4] */
|
||||
__IO uint32_t sts : 1; /* [7] */
|
||||
__IO uint32_t esf : 4; /* [11:8] */
|
||||
__IO uint32_t esdiv : 2; /* [13:12] */
|
||||
__IO uint32_t ecmben : 1; /* [14] */
|
||||
__IO uint32_t esp : 1; /* [15] */
|
||||
__IO uint32_t reserved2 : 16;/* [31:16] */
|
||||
} stctrl_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief tmr die register, offset:0x0C
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t iden;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t ovfien : 1; /* [0] */
|
||||
__IO uint32_t c1ien : 1; /* [1] */
|
||||
__IO uint32_t c2ien : 1; /* [2] */
|
||||
__IO uint32_t c3ien : 1; /* [3] */
|
||||
__IO uint32_t c4ien : 1; /* [4] */
|
||||
__IO uint32_t hallien : 1; /* [5] */
|
||||
__IO uint32_t tien : 1; /* [6] */
|
||||
__IO uint32_t brkie : 1; /* [7] */
|
||||
__IO uint32_t ovfden : 1; /* [8] */
|
||||
__IO uint32_t c1den : 1; /* [9] */
|
||||
__IO uint32_t c2den : 1; /* [10] */
|
||||
__IO uint32_t c3den : 1; /* [11] */
|
||||
__IO uint32_t c4den : 1; /* [12] */
|
||||
__IO uint32_t hallde : 1; /* [13] */
|
||||
__IO uint32_t tden : 1; /* [14] */
|
||||
__IO uint32_t reserved1 : 17;/* [31:15] */
|
||||
} iden_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief tmr ists register, offset:0x10
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t ists;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t ovfif : 1; /* [0] */
|
||||
__IO uint32_t c1if : 1; /* [1] */
|
||||
__IO uint32_t c2if : 1; /* [2] */
|
||||
__IO uint32_t c3if : 1; /* [3] */
|
||||
__IO uint32_t c4if : 1; /* [4] */
|
||||
__IO uint32_t hallif : 1; /* [5] */
|
||||
__IO uint32_t trgif : 1; /* [6] */
|
||||
__IO uint32_t brkif : 1; /* [7] */
|
||||
__IO uint32_t reserved1 : 1; /* [8] */
|
||||
__IO uint32_t c1rf : 1; /* [9] */
|
||||
__IO uint32_t c2rf : 1; /* [10] */
|
||||
__IO uint32_t c3rf : 1; /* [11] */
|
||||
__IO uint32_t c4rf : 1; /* [12] */
|
||||
__IO uint32_t reserved2 : 19;/* [31:13] */
|
||||
} ists_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief tmr eveg register, offset:0x14
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t swevt;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t ovfswtr : 1; /* [0] */
|
||||
__IO uint32_t c1swtr : 1; /* [1] */
|
||||
__IO uint32_t c2swtr : 1; /* [2] */
|
||||
__IO uint32_t c3swtr : 1; /* [3] */
|
||||
__IO uint32_t c4swtr : 1; /* [4] */
|
||||
__IO uint32_t hallswtr : 1; /* [5] */
|
||||
__IO uint32_t trgswtr : 1; /* [6] */
|
||||
__IO uint32_t brkswtr : 1; /* [7] */
|
||||
__IO uint32_t reserved : 24;/* [31:8] */
|
||||
} swevt_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief tmr ccm1 register, offset:0x18
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t cm1;
|
||||
|
||||
/**
|
||||
* @brief channel mode
|
||||
*/
|
||||
struct
|
||||
{
|
||||
__IO uint32_t c1c : 2; /* [1:0] */
|
||||
__IO uint32_t c1oien : 1; /* [2] */
|
||||
__IO uint32_t c1oben : 1; /* [3] */
|
||||
__IO uint32_t c1octrl : 3; /* [6:4] */
|
||||
__IO uint32_t c1osen : 1; /* [7] */
|
||||
__IO uint32_t c2c : 2; /* [9:8] */
|
||||
__IO uint32_t c2oien : 1; /* [10] */
|
||||
__IO uint32_t c2oben : 1; /* [11] */
|
||||
__IO uint32_t c2octrl : 3; /* [14:12] */
|
||||
__IO uint32_t c2osen : 1; /* [15] */
|
||||
__IO uint32_t reserved1 : 16;/* [31:16] */
|
||||
} cm1_output_bit;
|
||||
|
||||
/**
|
||||
* @brief input capture mode
|
||||
*/
|
||||
struct
|
||||
{
|
||||
__IO uint32_t c1c : 2; /* [1:0] */
|
||||
__IO uint32_t c1idiv : 2; /* [3:2] */
|
||||
__IO uint32_t c1df : 4; /* [7:4] */
|
||||
__IO uint32_t c2c : 2; /* [9:8] */
|
||||
__IO uint32_t c2idiv : 2; /* [11:10] */
|
||||
__IO uint32_t c2df : 4; /* [15:12] */
|
||||
__IO uint32_t reserved1 : 16;/* [31:16] */
|
||||
} cm1_input_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief tmr ccm2 register, offset:0x1C
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t cm2;
|
||||
|
||||
/**
|
||||
* @brief channel mode
|
||||
*/
|
||||
struct
|
||||
{
|
||||
__IO uint32_t c3c : 2; /* [1:0] */
|
||||
__IO uint32_t c3oien : 1; /* [2] */
|
||||
__IO uint32_t c3oben : 1; /* [3] */
|
||||
__IO uint32_t c3octrl : 3; /* [6:4] */
|
||||
__IO uint32_t c3osen : 1; /* [7] */
|
||||
__IO uint32_t c4c : 2; /* [9:8] */
|
||||
__IO uint32_t c4oien : 1; /* [10] */
|
||||
__IO uint32_t c4oben : 1; /* [11] */
|
||||
__IO uint32_t c4octrl : 3; /* [14:12] */
|
||||
__IO uint32_t c4osen : 1; /* [15] */
|
||||
__IO uint32_t reserved1 : 16;/* [31:16] */
|
||||
} cm2_output_bit;
|
||||
|
||||
/**
|
||||
* @brief input capture mode
|
||||
*/
|
||||
struct
|
||||
{
|
||||
__IO uint32_t c3c : 2; /* [1:0] */
|
||||
__IO uint32_t c3idiv : 2; /* [3:2] */
|
||||
__IO uint32_t c3df : 4; /* [7:4] */
|
||||
__IO uint32_t c4c : 2; /* [9:8] */
|
||||
__IO uint32_t c4idiv : 2; /* [11:10] */
|
||||
__IO uint32_t c4df : 4; /* [15:12] */
|
||||
__IO uint32_t reserved1 : 16;/* [31:16] */
|
||||
} cm2_input_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief tmr cce register, offset:0x20
|
||||
*/
|
||||
union
|
||||
{
|
||||
uint32_t cctrl;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t c1en : 1; /* [0] */
|
||||
__IO uint32_t c1p : 1; /* [1] */
|
||||
__IO uint32_t c1cen : 1; /* [2] */
|
||||
__IO uint32_t c1cp : 1; /* [3] */
|
||||
__IO uint32_t c2en : 1; /* [4] */
|
||||
__IO uint32_t c2p : 1; /* [5] */
|
||||
__IO uint32_t c2cen : 1; /* [6] */
|
||||
__IO uint32_t c2cp : 1; /* [7] */
|
||||
__IO uint32_t c3en : 1; /* [8] */
|
||||
__IO uint32_t c3p : 1; /* [9] */
|
||||
__IO uint32_t c3cen : 1; /* [10] */
|
||||
__IO uint32_t c3cp : 1; /* [11] */
|
||||
__IO uint32_t c4en : 1; /* [12] */
|
||||
__IO uint32_t c4p : 1; /* [13] */
|
||||
__IO uint32_t reserved1 : 18;/* [31:14] */
|
||||
} cctrl_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief tmr cnt register, offset:0x24
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t cval;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t cval : 32;/* [31:0] */
|
||||
} cval_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief tmr div, offset:0x28
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t div;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t div : 16;/* [15:0] */
|
||||
__IO uint32_t reserved1 : 16;/* [31:16] */
|
||||
} div_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief tmr pr register, offset:0x2C
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t pr;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t pr : 32;/* [31:0] */
|
||||
} pr_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief tmr rpr register, offset:0x30
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t rpr;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t rpr : 8; /* [7:0] */
|
||||
__IO uint32_t reserved1 : 24;/* [31:8] */
|
||||
} rpr_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief tmr c1dt register, offset:0x34
|
||||
*/
|
||||
union
|
||||
{
|
||||
uint32_t c1dt;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t c1dt : 32;/* [31:0] */
|
||||
} c1dt_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief tmr c2dt register, offset:0x38
|
||||
*/
|
||||
union
|
||||
{
|
||||
uint32_t c2dt;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t c2dt : 32;/* [31:0] */
|
||||
} c2dt_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief tmr c3dt register, offset:0x3C
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t c3dt;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t c3dt : 32;/* [31:0] */
|
||||
} c3dt_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief tmr c4dt register, offset:0x40
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t c4dt;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t c4dt : 32;/* [31:0] */
|
||||
} c4dt_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief tmr brk register, offset:0x44
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t brk;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t dtc : 8; /* [7:0] */
|
||||
__IO uint32_t wpc : 2; /* [9:8] */
|
||||
__IO uint32_t fcsodis : 1; /* [10] */
|
||||
__IO uint32_t fcsoen : 1; /* [11] */
|
||||
__IO uint32_t brken : 1; /* [12] */
|
||||
__IO uint32_t brkv : 1; /* [13] */
|
||||
__IO uint32_t aoen : 1; /* [14] */
|
||||
__IO uint32_t oen : 1; /* [15] */
|
||||
__IO uint32_t reserved1 : 16; /* [31:16] */
|
||||
} brk_bit;
|
||||
};
|
||||
/**
|
||||
* @brief tmr dmactrl register, offset:0x48
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t dmactrl;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t addr : 5; /* [4:0] */
|
||||
__IO uint32_t reserved1 : 3; /* [7:5] */
|
||||
__IO uint32_t dtb : 5; /* [12:8] */
|
||||
__IO uint32_t reserved2 : 19;/* [31:13] */
|
||||
} dmactrl_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief tmr dmadt register, offset:0x4C
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t dmadt;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t dmadt : 16;/* [15:0] */
|
||||
__IO uint32_t reserved1 : 16;/* [31:16] */
|
||||
} dmadt_bit;
|
||||
};
|
||||
|
||||
} tmr_type;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#define TMR1 ((tmr_type *) TMR1_BASE)
|
||||
#define TMR2 ((tmr_type *) TMR2_BASE)
|
||||
#define TMR3 ((tmr_type *) TMR3_BASE)
|
||||
#define TMR4 ((tmr_type *) TMR4_BASE)
|
||||
#define TMR5 ((tmr_type *) TMR5_BASE)
|
||||
#define TMR6 ((tmr_type *) TMR6_BASE)
|
||||
#define TMR7 ((tmr_type *) TMR7_BASE)
|
||||
#define TMR8 ((tmr_type *) TMR8_BASE)
|
||||
#define TMR9 ((tmr_type *) TMR9_BASE)
|
||||
#define TMR10 ((tmr_type *) TMR10_BASE)
|
||||
#define TMR11 ((tmr_type *) TMR11_BASE)
|
||||
#define TMR12 ((tmr_type *) TMR12_BASE)
|
||||
#define TMR13 ((tmr_type *) TMR13_BASE)
|
||||
#define TMR14 ((tmr_type *) TMR14_BASE)
|
||||
|
||||
/** @defgroup TMR_exported_functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
void tmr_reset(tmr_type *tmr_x);
|
||||
void tmr_counter_enable(tmr_type *tmr_x, confirm_state new_state);
|
||||
void tmr_output_default_para_init(tmr_output_config_type *tmr_output_struct);
|
||||
void tmr_input_default_para_init(tmr_input_config_type *tmr_input_struct);
|
||||
void tmr_brkdt_default_para_init(tmr_brkdt_config_type *tmr_brkdt_struct);
|
||||
void tmr_base_init(tmr_type* tmr_x, uint32_t tmr_pr, uint32_t tmr_div);
|
||||
void tmr_clock_source_div_set(tmr_type *tmr_x, tmr_clock_division_type tmr_clock_div);
|
||||
void tmr_cnt_dir_set(tmr_type *tmr_x, tmr_count_mode_type tmr_cnt_dir);
|
||||
void tmr_repetition_counter_set(tmr_type *tmr_x, uint8_t tmr_rpr_value);
|
||||
void tmr_counter_value_set(tmr_type *tmr_x, uint32_t tmr_cnt_value);
|
||||
uint32_t tmr_counter_value_get(tmr_type *tmr_x);
|
||||
void tmr_div_value_set(tmr_type *tmr_x, uint32_t tmr_div_value);
|
||||
uint32_t tmr_div_value_get(tmr_type *tmr_x);
|
||||
void tmr_output_channel_config(tmr_type *tmr_x, tmr_channel_select_type tmr_channel, \
|
||||
tmr_output_config_type *tmr_output_struct);
|
||||
void tmr_output_channel_mode_select(tmr_type *tmr_x, tmr_channel_select_type tmr_channel, \
|
||||
tmr_output_control_mode_type oc_mode);
|
||||
void tmr_period_value_set(tmr_type *tmr_x, uint32_t tmr_pr_value);
|
||||
uint32_t tmr_period_value_get(tmr_type *tmr_x);
|
||||
void tmr_channel_value_set(tmr_type *tmr_x, tmr_channel_select_type tmr_channel, \
|
||||
uint32_t tmr_channel_value);
|
||||
uint32_t tmr_channel_value_get(tmr_type *tmr_x, tmr_channel_select_type tmr_channel);
|
||||
void tmr_period_buffer_enable(tmr_type *tmr_x, confirm_state new_state);
|
||||
void tmr_output_channel_buffer_enable(tmr_type *tmr_x, tmr_channel_select_type tmr_channel, \
|
||||
confirm_state new_state);
|
||||
void tmr_output_channel_immediately_set(tmr_type *tmr_x, tmr_channel_select_type tmr_channel, \
|
||||
confirm_state new_state);
|
||||
void tmr_output_channel_switch_set(tmr_type *tmr_x, tmr_channel_select_type tmr_channel, \
|
||||
confirm_state new_state);
|
||||
void tmr_one_cycle_mode_enable(tmr_type *tmr_x, confirm_state new_state);
|
||||
void tmr_32_bit_function_enable (tmr_type *tmr_x, confirm_state new_state);
|
||||
void tmr_overflow_request_source_set(tmr_type *tmr_x, confirm_state new_state);
|
||||
void tmr_overflow_event_disable(tmr_type *tmr_x, confirm_state new_state);
|
||||
void tmr_input_channel_init(tmr_type *tmr_x, tmr_input_config_type *input_struct, \
|
||||
tmr_channel_input_divider_type divider_factor);
|
||||
void tmr_channel_enable(tmr_type *tmr_x, tmr_channel_select_type tmr_channel, confirm_state new_state);
|
||||
void tmr_input_channel_filter_set(tmr_type *tmr_x, tmr_channel_select_type tmr_channel, \
|
||||
uint16_t filter_value);
|
||||
void tmr_pwm_input_config(tmr_type *tmr_x, tmr_input_config_type *input_struct, \
|
||||
tmr_channel_input_divider_type divider_factor);
|
||||
void tmr_channel1_input_select(tmr_type *tmr_x, tmr_channel1_input_connected_type ch1_connect);
|
||||
void tmr_input_channel_divider_set(tmr_type *tmr_x, tmr_channel_select_type tmr_channel, \
|
||||
tmr_channel_input_divider_type divider_factor);
|
||||
void tmr_primary_mode_select(tmr_type *tmr_x, tmr_primary_select_type primary_mode);
|
||||
void tmr_sub_mode_select(tmr_type *tmr_x, tmr_sub_mode_select_type sub_mode);
|
||||
void tmr_channel_dma_select(tmr_type *tmr_x, tmr_dma_request_source_type cc_dma_select);
|
||||
void tmr_hall_select(tmr_type *tmr_x, confirm_state new_state);
|
||||
void tmr_channel_buffer_enable(tmr_type *tmr_x, confirm_state new_state);
|
||||
void tmr_trigger_input_select(tmr_type *tmr_x, sub_tmr_input_sel_type trigger_select);
|
||||
void tmr_sub_sync_mode_set(tmr_type *tmr_x, confirm_state new_state);
|
||||
void tmr_dma_request_enable(tmr_type *tmr_x, tmr_dma_request_type dma_request, confirm_state new_state);
|
||||
void tmr_interrupt_enable(tmr_type *tmr_x, uint32_t tmr_interrupt, confirm_state new_state);
|
||||
flag_status tmr_interrupt_flag_get(tmr_type *tmr_x, uint32_t tmr_flag);
|
||||
flag_status tmr_flag_get(tmr_type *tmr_x, uint32_t tmr_flag);
|
||||
void tmr_flag_clear(tmr_type *tmr_x, uint32_t tmr_flag);
|
||||
void tmr_event_sw_trigger(tmr_type *tmr_x, tmr_event_trigger_type tmr_event);
|
||||
void tmr_output_enable(tmr_type *tmr_x, confirm_state new_state);
|
||||
void tmr_internal_clock_set(tmr_type *tmr_x);
|
||||
|
||||
void tmr_output_channel_polarity_set(tmr_type *tmr_x, tmr_channel_select_type tmr_channel, \
|
||||
tmr_polarity_active_type oc_polarity);
|
||||
void tmr_external_clock_config(tmr_type *tmr_x, tmr_external_signal_divider_type es_divide, \
|
||||
tmr_external_signal_polarity_type es_polarity, uint16_t es_filter);
|
||||
void tmr_external_clock_mode1_config(tmr_type *tmr_x, tmr_external_signal_divider_type es_divide, \
|
||||
tmr_external_signal_polarity_type es_polarity, uint16_t es_filter);
|
||||
void tmr_external_clock_mode2_config(tmr_type *tmr_x, tmr_external_signal_divider_type es_divide, \
|
||||
tmr_external_signal_polarity_type es_polarity, uint16_t es_filter);
|
||||
void tmr_encoder_mode_config(tmr_type *tmr_x, tmr_encoder_mode_type encoder_mode, tmr_input_polarity_type \
|
||||
ic1_polarity, tmr_input_polarity_type ic2_polarity);
|
||||
void tmr_force_output_set(tmr_type *tmr_x, tmr_channel_select_type tmr_channel, \
|
||||
tmr_force_output_type force_output);
|
||||
void tmr_dma_control_config(tmr_type *tmr_x, tmr_dma_transfer_length_type dma_length, \
|
||||
tmr_dma_address_type dma_base_address);
|
||||
void tmr_brkdt_config(tmr_type *tmr_x, tmr_brkdt_config_type *brkdt_struct);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,381 @@
|
|||
/**
|
||||
**************************************************************************
|
||||
* @file at32f403a_407_usart.h
|
||||
* @brief at32f403a_407 usart header file
|
||||
**************************************************************************
|
||||
*
|
||||
* Copyright (c) 2025, Artery Technology, All rights reserved.
|
||||
*
|
||||
* The software Board Support Package (BSP) that is made available to
|
||||
* download from Artery official website is the copyrighted work of Artery.
|
||||
* Artery authorizes customers to use, copy, and distribute the BSP
|
||||
* software and its related documentation for the purpose of design and
|
||||
* development in conjunction with Artery microcontrollers. Use of the
|
||||
* software is governed by this copyright notice and the following disclaimer.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
|
||||
* GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
|
||||
* TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
|
||||
* STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
|
||||
* INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
|
||||
*
|
||||
**************************************************************************
|
||||
*/
|
||||
|
||||
/* define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __AT32F403A_407_USART_H
|
||||
#define __AT32F403A_407_USART_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
|
||||
/* includes ------------------------------------------------------------------*/
|
||||
#include "at32f403a_407.h"
|
||||
|
||||
/** @addtogroup AT32F403A_407_periph_driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup USART
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup USART_flags_definition
|
||||
* @brief usart flag
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define USART_PERR_FLAG ((uint32_t)0x00000001) /*!< usart parity error flag */
|
||||
#define USART_FERR_FLAG ((uint32_t)0x00000002) /*!< usart framing error flag */
|
||||
#define USART_NERR_FLAG ((uint32_t)0x00000004) /*!< usart noise error flag */
|
||||
#define USART_ROERR_FLAG ((uint32_t)0x00000008) /*!< usart receiver overflow error flag */
|
||||
#define USART_IDLEF_FLAG ((uint32_t)0x00000010) /*!< usart idle flag */
|
||||
#define USART_RDBF_FLAG ((uint32_t)0x00000020) /*!< usart receive data buffer full flag */
|
||||
#define USART_TDC_FLAG ((uint32_t)0x00000040) /*!< usart transmit data complete flag */
|
||||
#define USART_TDBE_FLAG ((uint32_t)0x00000080) /*!< usart transmit data buffer empty flag */
|
||||
#define USART_BFF_FLAG ((uint32_t)0x00000100) /*!< usart break frame flag */
|
||||
#define USART_CTSCF_FLAG ((uint32_t)0x00000200) /*!< usart cts change flag */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup USART_interrupts_definition
|
||||
* @brief usart interrupt
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define USART_IDLE_INT MAKE_VALUE(0x0C,0x04) /*!< usart idle interrupt */
|
||||
#define USART_RDBF_INT MAKE_VALUE(0x0C,0x05) /*!< usart receive data buffer full interrupt */
|
||||
#define USART_TDC_INT MAKE_VALUE(0x0C,0x06) /*!< usart transmit data complete interrupt */
|
||||
#define USART_TDBE_INT MAKE_VALUE(0x0C,0x07) /*!< usart transmit data buffer empty interrupt */
|
||||
#define USART_PERR_INT MAKE_VALUE(0x0C,0x08) /*!< usart parity error interrupt */
|
||||
#define USART_BF_INT MAKE_VALUE(0x10,0x06) /*!< usart break frame interrupt */
|
||||
#define USART_ERR_INT MAKE_VALUE(0x14,0x00) /*!< usart error interrupt */
|
||||
#define USART_CTSCF_INT MAKE_VALUE(0x14,0x0A) /*!< usart cts change interrupt */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup USART_exported_types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief usart parity selection type
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
USART_PARITY_NONE = 0x00, /*!< usart no parity */
|
||||
USART_PARITY_EVEN = 0x01, /*!< usart even parity */
|
||||
USART_PARITY_ODD = 0x02 /*!< usart odd parity */
|
||||
} usart_parity_selection_type;
|
||||
|
||||
/**
|
||||
* @brief usart wakeup mode type
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
USART_WAKEUP_BY_IDLE_FRAME = 0x00, /*!< usart wakeup by idle frame */
|
||||
USART_WAKEUP_BY_MATCHING_ID = 0x01 /*!< usart wakeup by matching id */
|
||||
} usart_wakeup_mode_type;
|
||||
|
||||
/**
|
||||
* @brief usart data bit num type
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
USART_DATA_8BITS = 0x00, /*!< usart data size is 8 bits */
|
||||
USART_DATA_9BITS = 0x01 /*!< usart data size is 9 bits */
|
||||
} usart_data_bit_num_type;
|
||||
|
||||
/**
|
||||
* @brief usart break frame bit num type
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
USART_BREAK_10BITS = 0x00, /*!< usart lin mode berak frame detection 10 bits */
|
||||
USART_BREAK_11BITS = 0x01 /*!< usart lin mode berak frame detection 11 bits */
|
||||
} usart_break_bit_num_type;
|
||||
|
||||
/**
|
||||
* @brief usart phase of the clock type
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
USART_CLOCK_PHASE_1EDGE = 0x00, /*!< usart data capture is done on the clock leading edge */
|
||||
USART_CLOCK_PHASE_2EDGE = 0x01 /*!< usart data capture is done on the clock trailing edge */
|
||||
} usart_clock_phase_type;
|
||||
|
||||
/**
|
||||
* @brief usart polarity of the clock type
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
USART_CLOCK_POLARITY_LOW = 0x00, /*!< usart clock stay low level outside transmission window */
|
||||
USART_CLOCK_POLARITY_HIGH = 0x01 /*!< usart clock stay high level outside transmission window */
|
||||
} usart_clock_polarity_type;
|
||||
|
||||
/**
|
||||
* @brief usart last bit clock pulse type
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
USART_CLOCK_LAST_BIT_NONE = 0x00, /*!< usart clock pulse of the last data bit is not outputted */
|
||||
USART_CLOCK_LAST_BIT_OUTPUT = 0x01 /*!< usart clock pulse of the last data bit is outputted */
|
||||
} usart_lbcp_type;
|
||||
|
||||
/**
|
||||
* @brief usart stop bit num type
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
USART_STOP_1_BIT = 0x00, /*!< usart stop bits num is 1 */
|
||||
USART_STOP_0_5_BIT = 0x01, /*!< usart stop bits num is 0.5 */
|
||||
USART_STOP_2_BIT = 0x02, /*!< usart stop bits num is 2 */
|
||||
USART_STOP_1_5_BIT = 0x03 /*!< usart stop bits num is 1.5 */
|
||||
} usart_stop_bit_num_type;
|
||||
|
||||
/**
|
||||
* @brief usart hardware flow control type
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
USART_HARDWARE_FLOW_NONE = 0x00, /*!< usart without hardware flow */
|
||||
USART_HARDWARE_FLOW_RTS = 0x01, /*!< usart hardware flow only rts */
|
||||
USART_HARDWARE_FLOW_CTS = 0x02, /*!< usart hardware flow only cts */
|
||||
USART_HARDWARE_FLOW_RTS_CTS = 0x03 /*!< usart hardware flow both rts and cts */
|
||||
} usart_hardware_flow_control_type;
|
||||
|
||||
/**
|
||||
* @brief type define usart register all
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
/**
|
||||
* @brief usart sts register, offset:0x00
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t sts;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t perr : 1; /* [0] */
|
||||
__IO uint32_t ferr : 1; /* [1] */
|
||||
__IO uint32_t nerr : 1; /* [2] */
|
||||
__IO uint32_t roerr : 1; /* [3] */
|
||||
__IO uint32_t idlef : 1; /* [4] */
|
||||
__IO uint32_t rdbf : 1; /* [5] */
|
||||
__IO uint32_t tdc : 1; /* [6] */
|
||||
__IO uint32_t tdbe : 1; /* [7] */
|
||||
__IO uint32_t bff : 1; /* [8] */
|
||||
__IO uint32_t ctscf : 1; /* [9] */
|
||||
__IO uint32_t reserved1 : 22;/* [31:10] */
|
||||
} sts_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief usart dt register, offset:0x04
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t dt;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t dt : 9; /* [8:0] */
|
||||
__IO uint32_t reserved1 : 23;/* [31:9] */
|
||||
} dt_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief usart baudr register, offset:0x08
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t baudr;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t div : 16;/* [15:0] */
|
||||
__IO uint32_t reserved1 : 16;/* [31:16] */
|
||||
} baudr_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief usart ctrl1 register, offset:0x0C
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t ctrl1;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t sbf : 1; /* [0] */
|
||||
__IO uint32_t rm : 1; /* [1] */
|
||||
__IO uint32_t ren : 1; /* [2] */
|
||||
__IO uint32_t ten : 1; /* [3] */
|
||||
__IO uint32_t idleien : 1; /* [4] */
|
||||
__IO uint32_t rdbfien : 1; /* [5] */
|
||||
__IO uint32_t tdcien : 1; /* [6] */
|
||||
__IO uint32_t tdbeien : 1; /* [7] */
|
||||
__IO uint32_t perrien : 1; /* [8] */
|
||||
__IO uint32_t psel : 1; /* [9] */
|
||||
__IO uint32_t pen : 1; /* [10] */
|
||||
__IO uint32_t wum : 1; /* [11] */
|
||||
__IO uint32_t dbn : 1; /* [12] */
|
||||
__IO uint32_t uen : 1; /* [13] */
|
||||
__IO uint32_t reserved1 : 18;/* [31:14] */
|
||||
} ctrl1_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief usart ctrl2 register, offset:0x10
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t ctrl2;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t id : 4; /* [3:0] */
|
||||
__IO uint32_t reserved1 : 1; /* [4] */
|
||||
__IO uint32_t bfbn : 1; /* [5] */
|
||||
__IO uint32_t bfien : 1; /* [6] */
|
||||
__IO uint32_t reserved2 : 1; /* [7] */
|
||||
__IO uint32_t lbcp : 1; /* [8] */
|
||||
__IO uint32_t clkpha : 1; /* [9] */
|
||||
__IO uint32_t clkpol : 1; /* [10] */
|
||||
__IO uint32_t clken : 1; /* [11] */
|
||||
__IO uint32_t stopbn : 2; /* [13:12] */
|
||||
__IO uint32_t linen : 1; /* [14] */
|
||||
__IO uint32_t reserved3 : 17;/* [31:15] */
|
||||
} ctrl2_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief usart ctrl3 register, offset:0x14
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t ctrl3;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t errien : 1; /* [0] */
|
||||
__IO uint32_t irdaen : 1; /* [1] */
|
||||
__IO uint32_t irdalp : 1; /* [2] */
|
||||
__IO uint32_t slben : 1; /* [3] */
|
||||
__IO uint32_t scnacken : 1; /* [4] */
|
||||
__IO uint32_t scmen : 1; /* [5] */
|
||||
__IO uint32_t dmaren : 1; /* [6] */
|
||||
__IO uint32_t dmaten : 1; /* [7] */
|
||||
__IO uint32_t rtsen : 1; /* [8] */
|
||||
__IO uint32_t ctsen : 1; /* [9] */
|
||||
__IO uint32_t ctscfien : 1; /* [10] */
|
||||
__IO uint32_t reserved1 : 21;/* [31:11] */
|
||||
} ctrl3_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief usart gdiv register, offset:0x18
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t gdiv;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t isdiv : 8; /* [7:0] */
|
||||
__IO uint32_t scgt : 8; /* [15:8] */
|
||||
__IO uint32_t reserved1 : 16;/* [31:16] */
|
||||
} gdiv_bit;
|
||||
};
|
||||
} usart_type;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#define USART1 ((usart_type *) USART1_BASE)
|
||||
#define USART2 ((usart_type *) USART2_BASE)
|
||||
#define USART3 ((usart_type *) USART3_BASE)
|
||||
#define UART4 ((usart_type *) UART4_BASE)
|
||||
#define UART5 ((usart_type *) UART5_BASE)
|
||||
#define USART6 ((usart_type *) USART6_BASE)
|
||||
#define UART7 ((usart_type *) UART7_BASE)
|
||||
#if defined (AT32F403ARx) || defined (AT32F403AVx) || defined (AT32F407Rx) || \
|
||||
defined (AT32F407Vx)
|
||||
#define UART8 ((usart_type *) UART8_BASE)
|
||||
#endif
|
||||
|
||||
/** @defgroup USART_exported_functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
void usart_reset(usart_type* usart_x);
|
||||
void usart_init(usart_type* usart_x, uint32_t baud_rate, usart_data_bit_num_type data_bit, usart_stop_bit_num_type stop_bit);
|
||||
void usart_parity_selection_config(usart_type* usart_x, usart_parity_selection_type parity);
|
||||
void usart_enable(usart_type* usart_x, confirm_state new_state);
|
||||
void usart_transmitter_enable(usart_type* usart_x, confirm_state new_state);
|
||||
void usart_receiver_enable(usart_type* usart_x, confirm_state new_state);
|
||||
void usart_clock_config(usart_type* usart_x, usart_clock_polarity_type clk_pol, usart_clock_phase_type clk_pha, usart_lbcp_type clk_lb);
|
||||
void usart_clock_enable(usart_type* usart_x, confirm_state new_state);
|
||||
void usart_interrupt_enable(usart_type* usart_x, uint32_t usart_int, confirm_state new_state);
|
||||
void usart_dma_transmitter_enable(usart_type* usart_x, confirm_state new_state);
|
||||
void usart_dma_receiver_enable(usart_type* usart_x, confirm_state new_state);
|
||||
void usart_wakeup_id_set(usart_type* usart_x, uint8_t usart_id);
|
||||
void usart_wakeup_mode_set(usart_type* usart_x, usart_wakeup_mode_type wakeup_mode);
|
||||
void usart_receiver_mute_enable(usart_type* usart_x, confirm_state new_state);
|
||||
void usart_break_bit_num_set(usart_type* usart_x, usart_break_bit_num_type break_bit);
|
||||
void usart_lin_mode_enable(usart_type* usart_x, confirm_state new_state);
|
||||
void usart_data_transmit(usart_type* usart_x, uint16_t data);
|
||||
uint16_t usart_data_receive(usart_type* usart_x);
|
||||
void usart_break_send(usart_type* usart_x);
|
||||
void usart_smartcard_guard_time_set(usart_type* usart_x, uint8_t guard_time_val);
|
||||
void usart_irda_smartcard_division_set(usart_type* usart_x, uint8_t div_val);
|
||||
void usart_smartcard_mode_enable(usart_type* usart_x, confirm_state new_state);
|
||||
void usart_smartcard_nack_set(usart_type* usart_x, confirm_state new_state);
|
||||
void usart_single_line_halfduplex_select(usart_type* usart_x, confirm_state new_state);
|
||||
void usart_irda_mode_enable(usart_type* usart_x, confirm_state new_state);
|
||||
void usart_irda_low_power_enable(usart_type* usart_x, confirm_state new_state);
|
||||
void usart_hardware_flow_control_set(usart_type* usart_x,usart_hardware_flow_control_type flow_state);
|
||||
flag_status usart_flag_get(usart_type* usart_x, uint32_t flag);
|
||||
flag_status usart_interrupt_flag_get(usart_type* usart_x, uint32_t flag);
|
||||
void usart_flag_clear(usart_type* usart_x, uint32_t flag);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,712 @@
|
|||
/**
|
||||
**************************************************************************
|
||||
* @file at32f403a_407_usb.h
|
||||
* @brief at32f403a_407 usb header file
|
||||
**************************************************************************
|
||||
*
|
||||
* Copyright (c) 2025, Artery Technology, All rights reserved.
|
||||
*
|
||||
* The software Board Support Package (BSP) that is made available to
|
||||
* download from Artery official website is the copyrighted work of Artery.
|
||||
* Artery authorizes customers to use, copy, and distribute the BSP
|
||||
* software and its related documentation for the purpose of design and
|
||||
* development in conjunction with Artery microcontrollers. Use of the
|
||||
* software is governed by this copyright notice and the following disclaimer.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
|
||||
* GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
|
||||
* TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
|
||||
* STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
|
||||
* INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
|
||||
*
|
||||
**************************************************************************
|
||||
*/
|
||||
|
||||
/** @addtogroup AT32F403A_407_periph_driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup USB
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __AT32F403A_407_USB_H
|
||||
#define __AT32F403A_407_USB_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
|
||||
/* includes ------------------------------------------------------------------*/
|
||||
#include "at32f403a_407.h"
|
||||
|
||||
|
||||
|
||||
/** @defgroup USB_interrupts_definition
|
||||
* @brief usb interrupt mask
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define USB_LSOF_INT ((uint32_t)0x00000100) /*!< usb lost sof interrupt */
|
||||
#define USB_SOF_INT ((uint32_t)0x00000200) /*!< usb sof interrupt */
|
||||
#define USB_RST_INT ((uint32_t)0x00000400) /*!< usb reset interrupt */
|
||||
#define USB_SP_INT ((uint32_t)0x00000800) /*!< usb suspend interrupt */
|
||||
#define USB_WK_INT ((uint32_t)0x00001000) /*!< usb wakeup interrupt */
|
||||
#define USB_BE_INT ((uint32_t)0x00002000) /*!< usb bus error interrupt */
|
||||
#define USB_UCFOR_INT ((uint32_t)0x00004000) /*!< usb core fifo overrun interrupt */
|
||||
#define USB_TC_INT ((uint32_t)0x00008000) /*!< usb transmission completed interrupt */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup USB_interrupt_flags_definition
|
||||
* @brief usb interrupt flag
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define USB_EPT_NUM_FLAG ((uint32_t)0x0000000F) /*!< usb endpoint number */
|
||||
#define USB_INOUT_FLAG ((uint32_t)0x00000010) /*!< usb in/out transcation flag */
|
||||
#define USB_LSOF_FLAG ((uint32_t)0x00000100) /*!< usb lost sof flag */
|
||||
#define USB_SOF_FLAG ((uint32_t)0x00000200) /*!< usb sof flag */
|
||||
#define USB_RST_FLAG ((uint32_t)0x00000400) /*!< usb reset flag */
|
||||
#define USB_SP_FLAG ((uint32_t)0x00000800) /*!< usb suspend flag */
|
||||
#define USB_WK_FLAG ((uint32_t)0x00001000) /*!< usb wakeup flag */
|
||||
#define USB_BE_FLAG ((uint32_t)0x00002000) /*!< usb bus error flag */
|
||||
#define USB_UCFOR_FLAG ((uint32_t)0x00004000) /*!< usb core fifo overrun flag */
|
||||
#define USB_TC_FLAG ((uint32_t)0x00008000) /*!< usb transmission completed flag */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup USB_endpoint_register_bit_definition
|
||||
* @brief usb endpoint register bit define
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define USB_EPTADDR ((uint32_t)0x0000000F) /*!< usb endpoint address */
|
||||
#define USB_TXSTS ((uint32_t)0x00000030) /*!< usb tx status */
|
||||
#define USB_TXDTS ((uint32_t)0x00000040) /*!< usb tx data toggle synchronization */
|
||||
#define USB_TXTC ((uint32_t)0x00000080) /*!< usb tx transcation completed */
|
||||
#define USB_EXF ((uint32_t)0x00000100) /*!< usb endpoint extend funtion */
|
||||
#define USB_TRANS_TYPE ((uint32_t)0x00000600) /*!< usb transfer type */
|
||||
#define USB_SETUPTC ((uint32_t)0x00000800) /*!< usb setup transcation completed */
|
||||
#define USB_RXSTS ((uint32_t)0x00003000) /*!< usb rx status */
|
||||
#define USB_RXDTS ((uint32_t)0x00004000) /*!< usb rx data toggle synchronization */
|
||||
#define USB_RXTC ((uint32_t)0x00008000) /*!< usb rx transcation completed */
|
||||
|
||||
#define USB_EPT_BIT_MASK (uint32_t)(USB_TXTC | USB_SETUPTC | USB_EPTADDR | USB_EXF | USB_RXTC | USB_TRANS_TYPE) /*!< usb bit mask */
|
||||
#define USB_TX_MASK (USB_TXSTS | USB_EPT_BIT_MASK) /*!< usb tx mask */
|
||||
#define USB_RX_MASK (USB_RXSTS | USB_EPT_BIT_MASK) /*!< usb rx mask */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup USB_endpoint_tx_and_rx_status_definition
|
||||
* @brief usb endpoint tx and rx status
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define USB_TX_DISABLE ((uint32_t)0x00000000) /*!< usb tx status disable */
|
||||
#define USB_TX_STALL ((uint32_t)0x00000010) /*!< usb tx status stall */
|
||||
#define USB_TX_NAK ((uint32_t)0x00000020) /*!< usb tx status nak */
|
||||
#define USB_TX_VALID ((uint32_t)0x00000030) /*!< usb tx status valid */
|
||||
|
||||
#define USB_TXDTS0 ((uint32_t)0x00000010) /*!< usb tx data toggle bit 0 */
|
||||
#define USB_TXDTS1 ((uint32_t)0x00000020) /*!< usb tx data toggle bit 1 */
|
||||
|
||||
#define USB_RX_DISABLE ((uint32_t)0x00000000) /*!< usb rx status disable */
|
||||
#define USB_RX_STALL ((uint32_t)0x00001000) /*!< usb rx status stall */
|
||||
#define USB_RX_NAK ((uint32_t)0x00002000) /*!< usb rx status nak */
|
||||
#define USB_RX_VALID ((uint32_t)0x00003000) /*!< usb rx status valid */
|
||||
|
||||
#define USB_RXDTS0 ((uint32_t)0x00001000) /*!< usb rx data toggle bit 0 */
|
||||
#define USB_RXDTS1 ((uint32_t)0x00002000) /*!< usb rx data toggle bit 1 */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup USB_device_endpoint_register_type_definition
|
||||
* @brief usb device endpoint register type define
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define USB_EPT_CONTROL ((uint32_t)0x00000200) /*!< usb endpoint transfer type control */
|
||||
#define USB_EPT_BULK ((uint32_t)0x00000000) /*!< usb endpoint transfer type bulk */
|
||||
#define USB_EPT_INT ((uint32_t)0x00000600) /*!< usb endpoint transfer type interrupt */
|
||||
#define USB_EPT_ISO ((uint32_t)0x00000400) /*!< usb endpoint transfer type iso */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup USB_buffer_table_default_offset_address_definition
|
||||
* @brief usb buffer table default offset address
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define USB_BUFFER_TABLE_ADDRESS 0x0000 /*!< usb buffer table address */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup USB_packet_buffer_start_address_definition
|
||||
* @brief usb packet buffer start address
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define USB_PACKET_BUFFER_ADDRESS 0x40006000 /*!< usb buffer address */
|
||||
#define USB_PACKET_BUFFER_ADDRESS_EX 0x40007800 /*!< usb buffer extend address */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup USB_exported_enum_types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief usb endpoint number define
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
USB_EPT0 = 0x00, /*!< usb endpoint 0 */
|
||||
USB_EPT1 = 0x01, /*!< usb endpoint 1 */
|
||||
USB_EPT2 = 0x02, /*!< usb endpoint 2 */
|
||||
USB_EPT3 = 0x03, /*!< usb endpoint 3 */
|
||||
USB_EPT4 = 0x04, /*!< usb endpoint 4 */
|
||||
USB_EPT5 = 0x05, /*!< usb endpoint 5 */
|
||||
USB_EPT6 = 0x06, /*!< usb endpoint 6 */
|
||||
USB_EPT7 = 0x07 /*!< usb endpoint 7 */
|
||||
} usb_ept_number_type;
|
||||
|
||||
/**
|
||||
* @brief usb endpoint max num define
|
||||
*/
|
||||
#ifndef USB_EPT_MAX_NUM
|
||||
#define USB_EPT_MAX_NUM 8 /*!< usb device support endpoint number */
|
||||
#endif
|
||||
/**
|
||||
* @brief endpoint transfer type define
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
EPT_CONTROL_TYPE = 0x00, /*!< usb transfer type control */
|
||||
EPT_ISO_TYPE = 0x01, /*!< usb transfer type iso */
|
||||
EPT_BULK_TYPE = 0x02, /*!< usb transfer type bulk */
|
||||
EPT_INT_TYPE = 0x03 /*!< usb transfer type interrupt */
|
||||
}ept_trans_type;
|
||||
|
||||
/**
|
||||
* @brief endpoint endpoint direction define
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
EPT_IN = 0x00, /*!< usb endpoint direction in */
|
||||
EPT_OUT = 0x01 /*!< usb endpoint direction out */
|
||||
}ept_inout_type;
|
||||
|
||||
/**
|
||||
* @brief data transfer direction
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
DATA_TRANS_OUT = 0x00, /*!< usb data transfer direction out */
|
||||
DATA_TRANS_IN = 0x01 /*!< usb data transfer direction in */
|
||||
}data_trans_dir;
|
||||
|
||||
/**
|
||||
* @brief usb clock select
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
USB_CLK_HICK,
|
||||
USB_CLK_HEXT
|
||||
}usb_clk48_s;
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup USB_macro_definition
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief set usb endpoint tx status
|
||||
* @param ept_num: endpoint number
|
||||
* @param new_sts: the new tx status of this endpoint number
|
||||
* @retval none
|
||||
*/
|
||||
#define USB_SET_TXSTS(ept_num, new_sts) { \
|
||||
register uint16_t epsts = (USB->ept[ept_num]) & USB_TX_MASK; \
|
||||
if((new_sts & USB_TXDTS0) != 0) \
|
||||
epsts ^= USB_TXDTS0; \
|
||||
if((new_sts & USB_TXDTS1) != 0) \
|
||||
epsts ^= USB_TXDTS1; \
|
||||
USB->ept[ept_num] = epsts | USB_RXTC | USB_TXTC; \
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief set usb endpoint rx status
|
||||
* @param ept_num: endpoint number
|
||||
* @param new_sts: the new rx status of this endpoint number
|
||||
* @retval none
|
||||
*/
|
||||
#define USB_SET_RXSTS(ept_num, new_sts) { \
|
||||
register uint16_t epsts = (USB->ept[ept_num]) & USB_RX_MASK; \
|
||||
if((new_sts & USB_RXDTS0) != 0) \
|
||||
epsts ^= USB_RXDTS0; \
|
||||
if((new_sts & USB_RXDTS1) != 0) \
|
||||
epsts ^= USB_RXDTS1; \
|
||||
USB->ept[ept_num] = epsts | USB_RXTC | USB_TXTC; \
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief get usb endpoint tx/rx length address
|
||||
* @param eptn: endpoint number
|
||||
* @retval the length address of tx/rx
|
||||
*/
|
||||
#define GET_TX_LEN_ADDR(eptn) (uint32_t *)((USB->buftbl + eptn * 8 + 2) * 2 + g_usb_packet_address)
|
||||
#define GET_RX_LEN_ADDR(eptn) (uint32_t *)((USB->buftbl + eptn * 8 + 6) * 2 + g_usb_packet_address)
|
||||
|
||||
/**
|
||||
* @brief get usb endpoint tx/rx data length
|
||||
* @param eptn: endpoint number
|
||||
* @retval the length of tx/rx
|
||||
*/
|
||||
#define USB_GET_TX_LEN(eptn) ((uint16_t)(*GET_TX_LEN_ADDR(eptn)) & 0x3ff)
|
||||
#define USB_GET_RX_LEN(eptn) ((uint16_t)(*GET_RX_LEN_ADDR(eptn)) & 0x3ff)
|
||||
|
||||
/**
|
||||
* @brief double buffer mode get endpoint buf0/buf1 data length
|
||||
* @param eptn: endpoint number
|
||||
* @retval the length of buf0/buf1
|
||||
*/
|
||||
#define USB_DBUF0_GET_LEN(eptn) USB_GET_TX_LEN(eptn)
|
||||
#define USB_DBUF1_GET_LEN(eptn) USB_GET_RX_LEN(eptn)
|
||||
|
||||
/**
|
||||
* @brief set usb length of rx buffer
|
||||
* @param reg: usb rx length register
|
||||
* @param len: rx max length
|
||||
* @param blks: number of blocks
|
||||
*/
|
||||
#define BLK32(reg, len, blks) { \
|
||||
blks = (len) >> 5; \
|
||||
if(((len) & 0x1F) == 0) \
|
||||
blks --; \
|
||||
*reg = ((uint16_t)((blks) << 10) | 0x8000); \
|
||||
}
|
||||
|
||||
#define BLK2(reg, len, blks) { \
|
||||
blks = (len) >> 1; \
|
||||
if(((len) & 0x1) == 0) \
|
||||
blks ++; \
|
||||
*reg = (uint16_t)((blks) << 10); \
|
||||
}
|
||||
|
||||
#define USB_SET_RXLEN_REG(reg, len) { \
|
||||
uint16_t blks; \
|
||||
if(len > 62) \
|
||||
{ \
|
||||
BLK32(reg, len, blks); \
|
||||
} \
|
||||
else \
|
||||
{ \
|
||||
BLK2(reg, len, blks); \
|
||||
} \
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief set endpoint tx/rx transfer length
|
||||
* @param eptn: endpoint number
|
||||
* @param len: transfer length
|
||||
* @retval none
|
||||
*/
|
||||
#define USB_SET_TXLEN(eptn, len) (*(GET_TX_LEN_ADDR(eptn)) = (len))
|
||||
#define USB_SET_RXLEN(eptn, len) { \
|
||||
uint32_t *rx_reg = GET_RX_LEN_ADDR(eptn); \
|
||||
USB_SET_RXLEN_REG(rx_reg, (len)); \
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief double buffer mode set endpoint rx buf0 length
|
||||
* @param eptn: endpoint number
|
||||
* @param len: transfer length
|
||||
* @retval none
|
||||
*/
|
||||
#define USB_OUT_EPT_DOUBLE_BUF0(eptn, len) { \
|
||||
uint32_t *rx_reg = GET_TX_LEN_ADDR(eptn); \
|
||||
USB_SET_RXLEN_REG(rx_reg, (len)); \
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief double buffer mode set endpoint buf0 length
|
||||
* @param eptn: endpoint number
|
||||
* @param len: transfer length
|
||||
* @param dir: transfer direction(in/out)
|
||||
* @retval none
|
||||
*/
|
||||
#define USB_SET_EPT_DOUBLE_BUF0_LEN(eptn, len, dir) { \
|
||||
if(dir == DATA_TRANS_OUT) \
|
||||
{ \
|
||||
USB_OUT_EPT_DOUBLE_BUF0(eptn, len); \
|
||||
} \
|
||||
else \
|
||||
{ \
|
||||
*(GET_TX_LEN_ADDR(eptn)) = (len); \
|
||||
} \
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief double buffer mode set endpoint buf1 length
|
||||
* @param eptn: endpoint number
|
||||
* @param len: transfer length
|
||||
* @param dir: transfer direction(in/out)
|
||||
* @retval none
|
||||
*/
|
||||
#define USB_SET_EPT_DOUBLE_BUF1_LEN(eptn, len, dir) { \
|
||||
if(dir == DATA_TRANS_OUT) \
|
||||
{ \
|
||||
USB_SET_RXLEN(eptn, len); \
|
||||
} \
|
||||
else \
|
||||
{ \
|
||||
*(GET_RX_LEN_ADDR(eptn)) = (len); \
|
||||
} \
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief set usb endpoint tx/rx fifo address
|
||||
* @param eptn: endpoint number
|
||||
* @param address: offset of the fifo address
|
||||
* @retval none
|
||||
*/
|
||||
#define USB_SET_TX_ADDRESS(eptn, address) (*(uint32_t *)((USB->buftbl + eptn * 8) * 2 + g_usb_packet_address) = address)
|
||||
#define USB_SET_RX_ADDRESS(eptn, address) (*(uint32_t *)((USB->buftbl + eptn * 8 + 4) * 2 + g_usb_packet_address) = address)
|
||||
|
||||
/**
|
||||
* @brief set double buffer mode usb endpoint buf0/buf1 fifo address
|
||||
* @param eptn: endpoint number
|
||||
* @param address: offset of the fifo address
|
||||
* @retval none
|
||||
*/
|
||||
#define USB_SET_DOUBLE_BUFF0_ADDRESS(eptn, address) (USB_SET_TX_ADDRESS(eptn, address))
|
||||
#define USB_SET_DOUBLE_BUFF1_ADDRESS(eptn, address) (USB_SET_RX_ADDRESS(eptn, address))
|
||||
|
||||
/**
|
||||
* @brief set usb tx/rx toggle
|
||||
* @param eptn: endpoint number
|
||||
* @retval none
|
||||
*/
|
||||
#define USB_TOGGLE_TXDTS(eptn) (USB->ept[eptn] = ((USB->ept[eptn] & USB_EPT_BIT_MASK) | USB_TXDTS | USB_RXTC | USB_TXTC))
|
||||
#define USB_TOGGLE_RXDTS(eptn) (USB->ept[eptn] = ((USB->ept[eptn] & USB_EPT_BIT_MASK) | USB_RXDTS | USB_RXTC | USB_TXTC))
|
||||
|
||||
/**
|
||||
* @brief clear usb tx/rx toggle
|
||||
* @param eptn: endpoint number
|
||||
* @retval none
|
||||
*/
|
||||
#define USB_CLEAR_TXDTS(eptn) { \
|
||||
if(USB->ept_bit[eptn].txdts != 0) \
|
||||
USB_TOGGLE_TXDTS(eptn); \
|
||||
}
|
||||
#define USB_CLEAR_RXDTS(eptn) { \
|
||||
if(USB->ept_bit[eptn].rxdts != 0) \
|
||||
USB_TOGGLE_RXDTS(eptn); \
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief set usb endpoint type
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief set usb transfer type
|
||||
* @param eptn: endpoint number
|
||||
* @param type: transfer type
|
||||
* @retval none
|
||||
*/
|
||||
#define USB_SET_TRANS_TYPE(eptn, type) (USB->ept[eptn] = (USB->ept[eptn] & USB_EPT_BIT_MASK & (~USB_TRANS_TYPE)) | type)
|
||||
|
||||
/**
|
||||
* @brief set/clear usb extend function
|
||||
* @param eptn: endpoint number
|
||||
* @retval none
|
||||
*/
|
||||
#define USB_SET_EXF(eptn) (USB->ept[eptn] = USB_TXTC | USB_RXTC | ((USB->ept[eptn] | USB_EXF) & USB_EPT_BIT_MASK))
|
||||
#define USB_CLEAR_EXF(eptn) (USB->ept[eptn] = USB_TXTC | USB_RXTC | (USB->ept[eptn] & ((~USB_EXF) & USB_EPT_BIT_MASK)))
|
||||
|
||||
/**
|
||||
* @brief set usb device address
|
||||
* @param eptn: endpoint number
|
||||
* @param address: device address
|
||||
* @retval none
|
||||
*/
|
||||
#define USB_SET_EPT_ADDRESS(eptn, address) (USB->ept[eptn] = ((USB->ept[eptn] & USB_EPT_BIT_MASK & (~USB_EPTADDR)) | address))
|
||||
|
||||
/**
|
||||
* @brief free buffer used by application
|
||||
* @param eptn: endpoint number
|
||||
* @param inout: transfer direction
|
||||
* @retval none
|
||||
*/
|
||||
#define USB_FREE_DB_USER_BUFFER(eptn, inout) { \
|
||||
if(inout == DATA_TRANS_IN) \
|
||||
{ \
|
||||
USB_TOGGLE_RXDTS(eptn); \
|
||||
} \
|
||||
else \
|
||||
{ \
|
||||
USB_TOGGLE_TXDTS(eptn); \
|
||||
} \
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief clear tx/rx transfer completed flag
|
||||
* @param eptn: endpoint number
|
||||
* @retval none
|
||||
*/
|
||||
#define USB_CLEAR_TXTC(eptn) (USB->ept[eptn] &= 0xFF7F & USB_EPT_BIT_MASK)
|
||||
#define USB_CLEAR_RXTC(eptn) (USB->ept[eptn] &= 0x7FFF & USB_EPT_BIT_MASK)
|
||||
|
||||
/**
|
||||
* @brief set/clear endpoint double buffer mode
|
||||
* @param eptn: endpoint number
|
||||
* @retval none
|
||||
*/
|
||||
#define USB_SET_EPT_DOUBLE_BUFFER(eptn) USB_SET_EXF(eptn)
|
||||
#define USB_CLEAR_EPT_DOUBLE_BUFFER(eptn) USB_CLEAR_EXF(eptn)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup USB_exported_types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief usb endpoint infomation structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint8_t eptn; /*!< endpoint register number (0~7) */
|
||||
uint8_t ept_address; /*!< endpoint address */
|
||||
uint8_t inout; /*!< endpoint dir DATA_TRANS_IN or DATA_TRANS_OUT */
|
||||
uint8_t trans_type; /*!< endpoint type:
|
||||
EPT_CONTROL_TYPE, EPT_BULK_TYPE, EPT_INT_TYPE, EPT_ISO_TYPE*/
|
||||
uint16_t tx_addr; /*!< endpoint tx buffer offset address */
|
||||
uint16_t rx_addr; /*!< endpoint rx buffer offset address */
|
||||
uint16_t maxpacket; /*!< endpoint max packet*/
|
||||
uint8_t is_double_buffer; /*!< endpoint double buffer flag */
|
||||
uint8_t stall; /*!< endpoint is stall state */
|
||||
uint16_t status; /*!< endpoint status */
|
||||
|
||||
/* transmission buffer and count */
|
||||
uint16_t total_len; /*!< endpoint transmission total length */
|
||||
uint16_t trans_len; /*!< endpoint transmission length*/
|
||||
uint8_t *trans_buf; /*!< endpoint transmission buffer */
|
||||
|
||||
uint16_t last_len; /*!< last transfer length */
|
||||
uint16_t rem0_len; /*!< rem transfer length */
|
||||
uint16_t ept0_slen; /*!< endpoint 0 transfer sum length */
|
||||
}usb_ept_info;
|
||||
|
||||
/**
|
||||
* @brief type define usb register all
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
/**
|
||||
* @brief usb endpoint register, offset:0x00
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t ept[8];
|
||||
struct
|
||||
{
|
||||
__IO uint32_t eptaddr : 4; /* [3:0] */
|
||||
__IO uint32_t txsts : 2; /* [5:4] */
|
||||
__IO uint32_t txdts : 1; /* [6] */
|
||||
__IO uint32_t txtc : 1; /* [7] */
|
||||
__IO uint32_t exf : 1; /* [8] */
|
||||
__IO uint32_t trans_type : 2; /* [10:9] */
|
||||
__IO uint32_t setuptc : 1; /* [11] */
|
||||
__IO uint32_t rxsts : 2; /* [13:12] */
|
||||
__IO uint32_t rxdts : 1; /* [14] */
|
||||
__IO uint32_t rxtc : 1; /* [15] */
|
||||
__IO uint32_t reserved1 : 16; /* [31:16] */
|
||||
} ept_bit[8];
|
||||
};
|
||||
|
||||
__IO uint32_t reserved1[8];
|
||||
|
||||
/**
|
||||
* @brief usb control register, offset:0x40
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t ctrl;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t csrst : 1; /* [0] */
|
||||
__IO uint32_t disusb : 1; /* [1] */
|
||||
__IO uint32_t lpm : 1; /* [2] */
|
||||
__IO uint32_t ssp : 1; /* [3] */
|
||||
__IO uint32_t gresume : 1; /* [4] */
|
||||
__IO uint32_t reserved1 : 3; /* [7:5] */
|
||||
__IO uint32_t lsofien : 1; /* [8] */
|
||||
__IO uint32_t sofien : 1; /* [9] */
|
||||
__IO uint32_t rstien : 1; /* [10] */
|
||||
__IO uint32_t spien : 1; /* [11] */
|
||||
__IO uint32_t wkien : 1; /* [12] */
|
||||
__IO uint32_t beien : 1; /* [13] */
|
||||
__IO uint32_t ucforien : 1; /* [14] */
|
||||
__IO uint32_t tcien : 1; /* [15] */
|
||||
__IO uint32_t reserved2 : 16; /* [31:16] */
|
||||
} ctrl_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief usb interrupt status register, offset:0x44
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t intsts;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t ept_num : 4; /* [3:0] */
|
||||
__IO uint32_t inout : 1; /* [4] */
|
||||
__IO uint32_t reserved1 : 3; /* [7:5] */
|
||||
__IO uint32_t lsof : 1; /* [8] */
|
||||
__IO uint32_t sof : 1; /* [9] */
|
||||
__IO uint32_t rst : 1; /* [10] */
|
||||
__IO uint32_t sp : 1; /* [11] */
|
||||
__IO uint32_t wk : 1; /* [12] */
|
||||
__IO uint32_t be : 1; /* [13] */
|
||||
__IO uint32_t ucfor : 1; /* [14] */
|
||||
__IO uint32_t tc : 1; /* [15] */
|
||||
__IO uint32_t reserved2 : 16; /* [31:16] */
|
||||
} intsts_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief usb frame number register, offset:0x48
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t sofrnum;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t sofnum : 11; /* [10:0] */
|
||||
__IO uint32_t lsofnum : 2; /* [12:11] */
|
||||
__IO uint32_t clck : 1; /* [13] */
|
||||
__IO uint32_t dmsts : 1; /* [14] */
|
||||
__IO uint32_t dpsts : 1; /* [15] */
|
||||
__IO uint32_t reserved1 : 16; /* [31:16] */
|
||||
} sofrnum_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief usb device address register, offset:0x4c
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t devaddr;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t addr : 7; /* [6:0] */
|
||||
__IO uint32_t cen : 1; /* [7] */
|
||||
__IO uint32_t reserved1 : 24; /* [31:8] */
|
||||
} devaddr_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief usb buffer address register, offset:0x50
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t buftbl;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t reserved1 : 3; /* [2:0] */
|
||||
__IO uint32_t btaddr : 13; /* [15:3] */
|
||||
__IO uint32_t reserved2 : 16; /* [31:16] */
|
||||
} buftbl_bit;
|
||||
};
|
||||
__IO uint32_t reserved2[3];
|
||||
/**
|
||||
* @brief usb cfg control register, offset:0x60
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t cfg;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t sofouten : 1; /* [0] */
|
||||
__IO uint32_t puo : 1; /* [1] */
|
||||
__IO uint32_t reserved1 : 30; /* [31:2] */
|
||||
} cfg_bit;
|
||||
};
|
||||
|
||||
} usbd_type;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#define USB ((usbd_type *) USBFS_BASE)
|
||||
|
||||
typedef usbd_type usb_reg_type;
|
||||
extern uint32_t g_usb_packet_address;
|
||||
|
||||
/** @defgroup USB_exported_functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
void usb_dev_init(usbd_type *usbx);
|
||||
void usb_connect(usbd_type *usbx);
|
||||
void usb_disconnect(usbd_type *usbx);
|
||||
void usb_usbbufs_enable(usbd_type *usbx, confirm_state state);
|
||||
void usb_ept_open(usbd_type *usbx, usb_ept_info *ept_info);
|
||||
void usb_ept_close(usbd_type *usbx, usb_ept_info *ept_info);
|
||||
void usb_write_packet(uint8_t *pusr_buf, uint16_t offset_addr, uint16_t nbytes);
|
||||
void usb_read_packet(uint8_t *pusr_buf, uint16_t offset_addr, uint16_t nbytes);
|
||||
void usb_interrupt_enable(usbd_type *usbx, uint16_t interrupt, confirm_state new_state);
|
||||
void usb_set_address(usbd_type *usbx, uint8_t address);
|
||||
void usb_ept_stall(usbd_type *usbx, usb_ept_info *ept_info);
|
||||
void usb_enter_suspend(usbd_type *usbx);
|
||||
void usb_exit_suspend(usbd_type *usbx);
|
||||
void usb_remote_wkup_set(usbd_type *usbx);
|
||||
void usb_remote_wkup_clear(usbd_type *usbx);
|
||||
uint16_t usb_buffer_malloc(uint16_t maxpacket);
|
||||
void usb_buffer_free(void);
|
||||
flag_status usb_flag_get(usbd_type *usbx, uint16_t flag);
|
||||
flag_status usb_interrupt_flag_get(usbd_type *usbx, uint16_t flag);
|
||||
void usb_flag_clear(usbd_type *usbx, uint16_t flag);
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
|
@ -0,0 +1,182 @@
|
|||
/**
|
||||
**************************************************************************
|
||||
* @file at32f403a_407_wdt.h
|
||||
* @brief at32f403a_407 wdt header file
|
||||
**************************************************************************
|
||||
*
|
||||
* Copyright (c) 2025, Artery Technology, All rights reserved.
|
||||
*
|
||||
* The software Board Support Package (BSP) that is made available to
|
||||
* download from Artery official website is the copyrighted work of Artery.
|
||||
* Artery authorizes customers to use, copy, and distribute the BSP
|
||||
* software and its related documentation for the purpose of design and
|
||||
* development in conjunction with Artery microcontrollers. Use of the
|
||||
* software is governed by this copyright notice and the following disclaimer.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
|
||||
* GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
|
||||
* TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
|
||||
* STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
|
||||
* INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
|
||||
*
|
||||
**************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __AT32F403A_407_WDT_H
|
||||
#define __AT32F403A_407_WDT_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "at32f403a_407.h"
|
||||
|
||||
/** @addtogroup AT32F403A_407_periph_driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup WDT
|
||||
* @{
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup WDT_flags_definition
|
||||
* @brief wdt flag
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define WDT_DIVF_UPDATE_FLAG ((uint16_t)0x0001) /*!< wdt division value update complete flag */
|
||||
#define WDT_RLDF_UPDATE_FLAG ((uint16_t)0x0002) /*!< wdt reload value update complete flag */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup WDT_exported_types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief wdt division value type
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
WDT_CLK_DIV_4 = 0x00, /*!< wdt clock divider value is 4 */
|
||||
WDT_CLK_DIV_8 = 0x01, /*!< wdt clock divider value is 8 */
|
||||
WDT_CLK_DIV_16 = 0x02, /*!< wdt clock divider value is 16 */
|
||||
WDT_CLK_DIV_32 = 0x03, /*!< wdt clock divider value is 32 */
|
||||
WDT_CLK_DIV_64 = 0x04, /*!< wdt clock divider value is 64 */
|
||||
WDT_CLK_DIV_128 = 0x05, /*!< wdt clock divider value is 128 */
|
||||
WDT_CLK_DIV_256 = 0x06 /*!< wdt clock divider value is 256 */
|
||||
} wdt_division_type;
|
||||
|
||||
/**
|
||||
* @brief wdt cmd value type
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
WDT_CMD_LOCK = 0x0000, /*!< disable write protection command */
|
||||
WDT_CMD_UNLOCK = 0x5555, /*!< enable write protection command */
|
||||
WDT_CMD_ENABLE = 0xCCCC, /*!< enable wdt command */
|
||||
WDT_CMD_RELOAD = 0xAAAA /*!< reload command */
|
||||
} wdt_cmd_value_type;
|
||||
|
||||
/**
|
||||
* @brief type define wdt register all
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
|
||||
/**
|
||||
* @brief wdt cmd register, offset:0x00
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t cmd;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t cmd : 16;/* [15:0] */
|
||||
__IO uint32_t reserved1 : 16;/* [31:16] */
|
||||
} cmd_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief wdt div register, offset:0x04
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t div;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t div : 3; /* [2:0] */
|
||||
__IO uint32_t reserved1 : 29;/* [31:3] */
|
||||
} div_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief wdt rld register, offset:0x08
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t rld;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t rld : 12;/* [11:0] */
|
||||
__IO uint32_t reserved1 : 20;/* [31:12] */
|
||||
} rld_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief wdt sts register, offset:0x0C
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t sts;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t divf : 1; /* [0] */
|
||||
__IO uint32_t rldf : 1; /* [1] */
|
||||
__IO uint32_t reserved1 : 30;/* [31:2] */
|
||||
} sts_bit;
|
||||
};
|
||||
|
||||
} wdt_type;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#define WDT ((wdt_type *) WDT_BASE)
|
||||
|
||||
/** @defgroup WDT_exported_functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
void wdt_enable(void);
|
||||
void wdt_counter_reload(void);
|
||||
void wdt_reload_value_set(uint16_t reload_value);
|
||||
void wdt_divider_set(wdt_division_type division);
|
||||
void wdt_register_write_enable( confirm_state new_state);
|
||||
flag_status wdt_flag_get(uint16_t wdt_flag);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,158 @@
|
|||
/**
|
||||
**************************************************************************
|
||||
* @file at32f403a_407_wwdt.h
|
||||
* @brief at32f403a_407 wwdt header file
|
||||
**************************************************************************
|
||||
*
|
||||
* Copyright (c) 2025, Artery Technology, All rights reserved.
|
||||
*
|
||||
* The software Board Support Package (BSP) that is made available to
|
||||
* download from Artery official website is the copyrighted work of Artery.
|
||||
* Artery authorizes customers to use, copy, and distribute the BSP
|
||||
* software and its related documentation for the purpose of design and
|
||||
* development in conjunction with Artery microcontrollers. Use of the
|
||||
* software is governed by this copyright notice and the following disclaimer.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
|
||||
* GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
|
||||
* TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
|
||||
* STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
|
||||
* INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
|
||||
*
|
||||
**************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __AT32F403A_407_WWDT_H
|
||||
#define __AT32F403A_407_WWDT_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "at32f403a_407.h"
|
||||
|
||||
/** @addtogroup AT32F403A_407_periph_driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup WWDT
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup WWDT_enable_bit_definition
|
||||
* @brief wwdt enable bit
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define WWDT_EN_BIT ((uint32_t)0x00000080) /*!< wwdt enable bit */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup WWDT_exported_types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief wwdt division type
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
WWDT_PCLK1_DIV_4096 = 0x00, /*!< wwdt counter clock = (pclk1/4096)/1) */
|
||||
WWDT_PCLK1_DIV_8192 = 0x01, /*!< wwdt counter clock = (pclk1/4096)/2) */
|
||||
WWDT_PCLK1_DIV_16384 = 0x02, /*!< wwdt counter clock = (pclk1/4096)/4) */
|
||||
WWDT_PCLK1_DIV_32768 = 0x03 /*!< wwdt counter clock = (pclk1/4096)/8) */
|
||||
} wwdt_division_type;
|
||||
|
||||
/**
|
||||
* @brief type define wwdt register all
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
|
||||
/**
|
||||
* @brief wwdt ctrl register, offset:0x00
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t ctrl;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t cnt : 7; /* [6:0] */
|
||||
__IO uint32_t wwdten : 1; /* [7] */
|
||||
__IO uint32_t reserved1 : 24;/* [31:8] */
|
||||
} ctrl_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief wwdt cfg register, offset:0x04
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t cfg;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t win : 7; /* [6:0] */
|
||||
__IO uint32_t div : 2; /* [8:7] */
|
||||
__IO uint32_t rldien : 1; /* [9] */
|
||||
__IO uint32_t reserved1 : 22;/* [31:10] */
|
||||
} cfg_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief wwdt cfg register, offset:0x08
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t sts;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t rldf : 1; /* [0] */
|
||||
__IO uint32_t reserved1 : 31;/* [31:1] */
|
||||
} sts_bit;
|
||||
};
|
||||
|
||||
} wwdt_type;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#define WWDT ((wwdt_type *) WWDT_BASE)
|
||||
|
||||
/** @defgroup WWDT_exported_functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
void wwdt_reset(void);
|
||||
void wwdt_divider_set(wwdt_division_type division);
|
||||
void wwdt_flag_clear(void);
|
||||
void wwdt_enable(uint8_t wwdt_cnt);
|
||||
void wwdt_interrupt_enable(void);
|
||||
flag_status wwdt_flag_get(void);
|
||||
flag_status wwdt_interrupt_flag_get(void);
|
||||
void wwdt_counter_set(uint8_t wwdt_cnt);
|
||||
void wwdt_window_counter_set(uint8_t window_cnt);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,568 @@
|
|||
/**
|
||||
**************************************************************************
|
||||
* @file at32f403a_407_xmc.h
|
||||
* @brief at32f403a_407 xmc header file
|
||||
**************************************************************************
|
||||
*
|
||||
* Copyright (c) 2025, Artery Technology, All rights reserved.
|
||||
*
|
||||
* The software Board Support Package (BSP) that is made available to
|
||||
* download from Artery official website is the copyrighted work of Artery.
|
||||
* Artery authorizes customers to use, copy, and distribute the BSP
|
||||
* software and its related documentation for the purpose of design and
|
||||
* development in conjunction with Artery microcontrollers. Use of the
|
||||
* software is governed by this copyright notice and the following disclaimer.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
|
||||
* GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
|
||||
* TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
|
||||
* STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
|
||||
* INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
|
||||
*
|
||||
**************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __AT32F403A_407_XMC_H
|
||||
#define __AT32F403A_407_XMC_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "at32f403a_407.h"
|
||||
|
||||
/** @addtogroup AT32F403A_407_periph_driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup XMC
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup XMC_exported_types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief xmc data address bus multiplexing type
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
XMC_DATA_ADDR_MUX_DISABLE = 0x00000000, /*!< xmc address/data multiplexing disable */
|
||||
XMC_DATA_ADDR_MUX_ENABLE = 0x00000002 /*!< xmc address/data multiplexing enable */
|
||||
} xmc_data_addr_mux_type;
|
||||
|
||||
/**
|
||||
* @brief xmc burst access mode type
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
XMC_BURST_MODE_DISABLE = 0x00000000, /*!< xmc burst mode disable */
|
||||
XMC_BURST_MODE_ENABLE = 0x00000100 /*!< xmc burst mode enable */
|
||||
} xmc_burst_access_mode_type;
|
||||
|
||||
/**
|
||||
* @brief xmc asynchronous wait type
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
XMC_ASYN_WAIT_DISABLE = 0x00000000, /*!< xmc wait signal during asynchronous transfers disbale */
|
||||
XMC_ASYN_WAIT_ENABLE = 0x00008000 /*!< xmc wait signal during asynchronous transfers enable */
|
||||
} xmc_asyn_wait_type;
|
||||
|
||||
/**
|
||||
* @brief xmc wrapped mode type
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
XMC_WRAPPED_MODE_DISABLE = 0x00000000, /*!< xmc direct wrapped burst is disbale */
|
||||
XMC_WRAPPED_MODE_ENABLE = 0x00000400 /*!< xmc direct wrapped burst is enable */
|
||||
} xmc_wrap_mode_type;
|
||||
|
||||
/**
|
||||
* @brief xmc write operation type
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
XMC_WRITE_OPERATION_DISABLE = 0x00000000, /*!< xmc write operations is disable */
|
||||
XMC_WRITE_OPERATION_ENABLE = 0x00001000 /*!< xmc write operations is enable */
|
||||
} xmc_write_operation_type;
|
||||
|
||||
/**
|
||||
* @brief xmc wait signal type
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
XMC_WAIT_SIGNAL_DISABLE = 0x00000000, /*!< xmc nwait signal is disable */
|
||||
XMC_WAIT_SIGNAL_ENABLE = 0x00002000 /*!< xmc nwait signal is enable */
|
||||
} xmc_wait_signal_type;
|
||||
|
||||
/**
|
||||
* @brief xmc write burst type
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
XMC_WRITE_BURST_SYN_DISABLE = 0x00000000, /*!< xmc write operations are always performed in asynchronous mode */
|
||||
XMC_WRITE_BURST_SYN_ENABLE = 0x00080000 /*!< xmc write operations are performed in synchronous mode */
|
||||
} xmc_write_burst_type;
|
||||
|
||||
/**
|
||||
* @brief xmc extended mode type
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
XMC_WRITE_TIMING_DISABLE = 0x00000000, /*!< xmc write timing disable */
|
||||
XMC_WRITE_TIMING_ENABLE = 0x00004000 /*!< xmc write timing enable */
|
||||
} xmc_extended_mode_type;
|
||||
|
||||
/**
|
||||
* @brief xmc nand wait type
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
XMC_WAIT_OPERATION_DISABLE = 0x00000000, /*!< xmc wait operation for the nand flash memory bank disable */
|
||||
XMC_WAIT_OPERATION_ENABLE = 0x00000002 /*!< xmc wait operation for the nand flash memory bank enable */
|
||||
} xmc_nand_wait_type;
|
||||
|
||||
/**
|
||||
* @brief xmc ecc enable type
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
XMC_ECC_OPERATION_DISABLE = 0x00000000, /*!< xmc ecc module disable */
|
||||
XMC_ECC_OPERATION_ENABLE = 0x00000040 /*!< xmc ecc module enable */
|
||||
} xmc_ecc_enable_type;
|
||||
|
||||
/**
|
||||
* @brief xmc nor/sram bank type
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
XMC_BANK1_NOR_SRAM1 = 0x00000000, /*!< xmc nor/sram subbank1 */
|
||||
XMC_BANK1_NOR_SRAM4 = 0x00000003 /*!< xmc nor/sram subbank4 */
|
||||
} xmc_nor_sram_subbank_type;
|
||||
|
||||
/**
|
||||
* @brief xmc class bank type
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
XMC_BANK2_NAND = 0x00000010, /*!< xmc nand flash bank2 */
|
||||
} xmc_class_bank_type;
|
||||
|
||||
/**
|
||||
* @brief xmc memory type
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
XMC_DEVICE_SRAM = 0x00000000, /*!< xmc device choice sram */
|
||||
XMC_DEVICE_PSRAM = 0x00000004, /*!< xmc device choice psram */
|
||||
XMC_DEVICE_NOR = 0x00000008 /*!< xmc device choice nor flash */
|
||||
} xmc_memory_type;
|
||||
|
||||
/**
|
||||
* @brief xmc data width type
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
XMC_BUSTYPE_8_BITS = 0x00000000, /*!< xmc databuss width 8bits */
|
||||
XMC_BUSTYPE_16_BITS = 0x00000010 /*!< xmc databuss width 16bits */
|
||||
} xmc_data_width_type;
|
||||
|
||||
/**
|
||||
* @brief xmc wait signal polarity type
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
XMC_WAIT_SIGNAL_LEVEL_LOW = 0x00000000, /*!< xmc nwait active low */
|
||||
XMC_WAIT_SIGNAL_LEVEL_HIGH = 0x00000200 /*!< xmc nwait active high */
|
||||
} xmc_wait_signal_polarity_type;
|
||||
|
||||
/**
|
||||
* @brief xmc wait timing type
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
XMC_WAIT_SIGNAL_SYN_BEFORE = 0x00000000, /*!< xmc nwait signal is active one data cycle before wait state */
|
||||
XMC_WAIT_SIGNAL_SYN_DURING = 0x00000800 /*!< xmc nwait signal is active during wait state */
|
||||
} xmc_wait_timing_type;
|
||||
|
||||
/**
|
||||
* @brief xmc access mode type
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
XMC_ACCESS_MODE_A = 0x00000000, /*!< xmc access mode A */
|
||||
XMC_ACCESS_MODE_B = 0x10000000, /*!< xmc access mode B */
|
||||
XMC_ACCESS_MODE_C = 0x20000000, /*!< xmc access mode C */
|
||||
XMC_ACCESS_MODE_D = 0x30000000 /*!< xmc access mode D */
|
||||
} xmc_access_mode_type;
|
||||
|
||||
/**
|
||||
* @brief xmc ecc page size type
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
XMC_ECC_PAGESIZE_256_BYTES = 0x00000000, /*!< xmc ecc page size 256 bytes */
|
||||
XMC_ECC_PAGESIZE_512_BYTES = 0x00020000, /*!< xmc ecc page size 512 bytes */
|
||||
XMC_ECC_PAGESIZE_1024_BYTES = 0x00040000, /*!< xmc ecc page size 1024 bytes */
|
||||
XMC_ECC_PAGESIZE_2048_BYTES = 0x00060000, /*!< xmc ecc page size 2048 bytes */
|
||||
XMC_ECC_PAGESIZE_4096_BYTES = 0x00080000, /*!< xmc ecc page size 4096 bytes */
|
||||
XMC_ECC_PAGESIZE_8192_BYTES = 0x000A0000 /*!< xmc ecc page size 8192 bytes */
|
||||
} xmc_ecc_pagesize_type;
|
||||
|
||||
/**
|
||||
* @brief xmc interrupt sources type
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
XMC_INT_RISING_EDGE = 0x00000008, /*!< xmc rising edge detection interrupt enable */
|
||||
XMC_INT_LEVEL = 0x00000010, /*!< xmc high-level edge detection interrupt enable */
|
||||
XMC_INT_FALLING_EDGE = 0x00000020 /*!< xmc falling edge detection interrupt enable */
|
||||
} xmc_interrupt_sources_type;
|
||||
|
||||
/**
|
||||
* @brief xmc interrupt flag type
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
XMC_RISINGEDGE_FLAG = 0x00000001, /*!< xmc interrupt rising edge detection flag */
|
||||
XMC_LEVEL_FLAG = 0x00000002, /*!< xmc interrupt high-level edge detection flag */
|
||||
XMC_FALLINGEDGE_FLAG = 0x00000004, /*!< xmc interrupt falling edge detection flag */
|
||||
XMC_FEMPT_FLAG = 0x00000040 /*!< xmc fifo empty flag */
|
||||
} xmc_interrupt_flag_type;
|
||||
|
||||
/**
|
||||
* @brief nor/sram banks timing parameters
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
xmc_nor_sram_subbank_type subbank; /*!< xmc nor/sram subbank */
|
||||
xmc_extended_mode_type write_timing_enable; /*!< xmc nor/sram write timing enable */
|
||||
uint32_t addr_setup_time; /*!< xmc nor/sram address setup time */
|
||||
uint32_t addr_hold_time; /*!< xmc nor/sram address hold time */
|
||||
uint32_t data_setup_time; /*!< xmc nor/sram data setup time */
|
||||
uint32_t bus_latency_time; /*!< xmc nor/sram bus latency time */
|
||||
uint32_t clk_psc; /*!< xmc nor/sram clock prescale */
|
||||
uint32_t data_latency_time; /*!< xmc nor/sram data latency time */
|
||||
xmc_access_mode_type mode; /*!< xmc nor/sram access mode */
|
||||
} xmc_norsram_timing_init_type;
|
||||
|
||||
/**
|
||||
* @brief xmc nor/sram init structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
xmc_nor_sram_subbank_type subbank; /*!< xmc nor/sram subbank */
|
||||
xmc_data_addr_mux_type data_addr_multiplex; /*!< xmc nor/sram address/data multiplexing enable */
|
||||
xmc_memory_type device; /*!< xmc nor/sram memory device */
|
||||
xmc_data_width_type bus_type; /*!< xmc nor/sram data bus width */
|
||||
xmc_burst_access_mode_type burst_mode_enable; /*!< xmc nor/sram burst mode enable */
|
||||
xmc_asyn_wait_type asynwait_enable; /*!< xmc nor/sram nwait in asynchronous transfer enable */
|
||||
xmc_wait_signal_polarity_type wait_signal_lv; /*!< xmc nor/sram nwait polarity */
|
||||
xmc_wrap_mode_type wrapped_mode_enable; /*!< xmc nor/sram wrapped enable */
|
||||
xmc_wait_timing_type wait_signal_config; /*!< xmc nor/sram nwait timing configuration */
|
||||
xmc_write_operation_type write_enable; /*!< xmc nor/sram write enable */
|
||||
xmc_wait_signal_type wait_signal_enable; /*!< xmc nor/sram nwait in synchronous transfer enable */
|
||||
xmc_extended_mode_type write_timing_enable; /*!< xmc nor/sram read-write timing different */
|
||||
xmc_write_burst_type write_burst_syn; /*!< xmc nor/sram memory write mode control */
|
||||
} xmc_norsram_init_type;
|
||||
|
||||
/**
|
||||
* @brief nand timing parameters xmc
|
||||
*/
|
||||
|
||||
typedef struct
|
||||
{
|
||||
xmc_class_bank_type class_bank; /*!< xmc nand bank */
|
||||
uint32_t mem_setup_time; /*!< xmc nand memory setup time */
|
||||
uint32_t mem_waite_time; /*!< xmc nand memory wait time */
|
||||
uint32_t mem_hold_time; /*!< xmc nand memory hold time */
|
||||
uint32_t mem_hiz_time; /*!< xmc nand memory databus high resistance time */
|
||||
} xmc_nand_timinginit_type;
|
||||
|
||||
/**
|
||||
* @brief xmc nand init structure definition
|
||||
*/
|
||||
|
||||
typedef struct
|
||||
{
|
||||
xmc_class_bank_type nand_bank; /*!< xmc nand bank */
|
||||
xmc_nand_wait_type wait_enable; /*!< xmc wait feature enable */
|
||||
xmc_data_width_type bus_type; /*!< xmc nand bus width */
|
||||
xmc_ecc_enable_type ecc_enable; /*!< xmc nand ecc enable */
|
||||
xmc_ecc_pagesize_type ecc_pagesize; /*!< xmc nand ecc page size */
|
||||
uint32_t delay_time_cycle; /*!< xmc nand cle to re delay */
|
||||
uint32_t delay_time_ar; /*!< xmc nand ale to re delay */
|
||||
} xmc_nand_init_type;
|
||||
|
||||
typedef struct
|
||||
{
|
||||
/**
|
||||
* @brief xmc bank1 bk1ctrl register, offset:0x00+0x08*(x-1) x= 1 or 4
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t bk1ctrl;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t en : 1; /* [0] */
|
||||
__IO uint32_t admuxen : 1; /* [1] */
|
||||
__IO uint32_t dev : 2; /* [3:2] */
|
||||
__IO uint32_t extmdbw : 2; /* [5:4] */
|
||||
__IO uint32_t noren : 1; /* [6] */
|
||||
__IO uint32_t reserved1 : 1; /* [7] */
|
||||
__IO uint32_t syncben : 1; /* [8] */
|
||||
__IO uint32_t nwpol : 1; /* [9] */
|
||||
__IO uint32_t wrapen : 1; /* [10] */
|
||||
__IO uint32_t nwtcfg : 1; /* [11] */
|
||||
__IO uint32_t wen : 1; /* [12] */
|
||||
__IO uint32_t nwsen : 1; /* [13] */
|
||||
__IO uint32_t rwtd : 1; /* [14] */
|
||||
__IO uint32_t nwasen : 1; /* [15] */
|
||||
__IO uint32_t crpgs : 3; /* [18:16] */
|
||||
__IO uint32_t mwmc : 1; /* [19] */
|
||||
__IO uint32_t reserved2 : 12;/* [31:20] */
|
||||
} bk1ctrl_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief xmc bank1 bk1tmg register, offset:0x04+0x08*(x-1) x= 1 or 4
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t bk1tmg;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t addrst : 4; /* [3:0] */
|
||||
__IO uint32_t addrht : 4; /* [7:4] */
|
||||
__IO uint32_t dtst : 8; /* [15:8] */
|
||||
__IO uint32_t buslat : 4; /* [19:16] */
|
||||
__IO uint32_t clkpsc : 4; /* [23:20] */
|
||||
__IO uint32_t dtlat : 4; /* [27:24] */
|
||||
__IO uint32_t asyncm : 2; /* [29:28] */
|
||||
__IO uint32_t reserved1 : 2; /* [31:30] */
|
||||
} bk1tmg_bit;
|
||||
};
|
||||
|
||||
} xmc_bank1_ctrl_tmg_reg_type;
|
||||
|
||||
typedef struct
|
||||
{
|
||||
/**
|
||||
* @brief xmc bank1 bk1tmgwr register, offset:0x104+0x08*(x-1) x= 1 or 4
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t bk1tmgwr;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t addrst : 4; /* [3:0] */
|
||||
__IO uint32_t addrht : 4; /* [7:4] */
|
||||
__IO uint32_t dtst : 8; /* [15:8] */
|
||||
__IO uint32_t buslat : 4; /* [19:16] */
|
||||
__IO uint32_t reserved1 : 8; /* [27:20] */
|
||||
__IO uint32_t asyncm : 2; /* [29:28] */
|
||||
__IO uint32_t reserved2 : 2; /* [31:30] */
|
||||
} bk1tmgwr_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief xmc bank1 reserved register
|
||||
*/
|
||||
__IO uint32_t reserved1;
|
||||
|
||||
} xmc_bank1_tmgwr_reg_type;
|
||||
|
||||
/**
|
||||
* @brief xmc bank1 registers
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
/**
|
||||
* @brief xmc bank1 ctrl and tmg register, offset:0x00~0x1C
|
||||
*/
|
||||
xmc_bank1_ctrl_tmg_reg_type ctrl_tmg_group[4];
|
||||
|
||||
/**
|
||||
* @brief xmc bank1 reserved register, offset:0x20~0x100
|
||||
*/
|
||||
__IO uint32_t reserved1[57];
|
||||
|
||||
/**
|
||||
* @brief xmc bank1 tmgwr register, offset:0x104~0x11C
|
||||
*/
|
||||
xmc_bank1_tmgwr_reg_type tmgwr_group[4];
|
||||
|
||||
/**
|
||||
* @brief xmc bank1 reserved register, offset:0x120~0x220
|
||||
*/
|
||||
__IO uint32_t reserved2[63];
|
||||
|
||||
/**
|
||||
* @brief xmc bank1 ext register, offset:0x220~0x22C
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t ext[4];
|
||||
struct
|
||||
{
|
||||
__IO uint32_t buslatw2w : 8; /* [7:0] */
|
||||
__IO uint32_t buslatr2r : 8; /* [15:8] */
|
||||
__IO uint32_t reserved1 : 16;/* [31:16] */
|
||||
} ext_bit[4];
|
||||
};
|
||||
|
||||
} xmc_bank1_type;
|
||||
|
||||
/**
|
||||
* @brief xmc bank2 registers
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
/**
|
||||
* @brief xmc bk2ctrl register, offset:0x60
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t bk2ctrl;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t reserved1 : 1; /* [0] */
|
||||
__IO uint32_t nwen : 1; /* [1] */
|
||||
__IO uint32_t en : 1; /* [2] */
|
||||
__IO uint32_t dev : 1; /* [3] */
|
||||
__IO uint32_t extmdbw : 2; /* [5:4] */
|
||||
__IO uint32_t eccen : 1; /* [6] */
|
||||
__IO uint32_t reserved2 : 2; /* [8:7] */
|
||||
__IO uint32_t tcr : 4; /* [12:9] */
|
||||
__IO uint32_t tar : 4; /* [16:13] */
|
||||
__IO uint32_t eccpgs : 3; /* [19:17] */
|
||||
__IO uint32_t reserved3 : 12;/* [31:20] */
|
||||
} bk2ctrl_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief xmc bk2is register, offset:0x64
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t bk2is;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t res : 1; /* [0] */
|
||||
__IO uint32_t hls : 1; /* [1] */
|
||||
__IO uint32_t fes : 1; /* [2] */
|
||||
__IO uint32_t reien : 1; /* [3] */
|
||||
__IO uint32_t hlien : 1; /* [4] */
|
||||
__IO uint32_t feien : 1; /* [5] */
|
||||
__IO uint32_t fifoe : 1; /* [6] */
|
||||
__IO uint32_t reserved1 : 25;/* [31:7] */
|
||||
} bk2is_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief xmc bk2tmgmem register, offset:0x68
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t bk2tmgmem;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t cmst : 8; /* [7:0] */
|
||||
__IO uint32_t cmwt : 8; /* [15:8] */
|
||||
__IO uint32_t cmht : 8; /* [23:16] */
|
||||
__IO uint32_t cmdhizt : 8; /* [31:24] */
|
||||
} bk2tmgmem_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief xmc bk2tmgatt register, offset:0x6C
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t bk2tmgatt;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t amst : 8; /* [7:0] */
|
||||
__IO uint32_t amwt : 8; /* [15:8] */
|
||||
__IO uint32_t amht : 8; /* [23:16] */
|
||||
__IO uint32_t amdhizt : 8; /* [31:24] */
|
||||
} bk2tmgatt_bit;
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief xmc reserved register, offset:0x70
|
||||
*/
|
||||
__IO uint32_t reserved1;
|
||||
|
||||
/**
|
||||
* @brief xmc bk2ecc register, offset:0x74
|
||||
*/
|
||||
union
|
||||
{
|
||||
__IO uint32_t bk2ecc;
|
||||
struct
|
||||
{
|
||||
__IO uint32_t ecc : 32; /* [31:0] */
|
||||
} bk2ecc_bit;
|
||||
};
|
||||
|
||||
} xmc_bank2_type;
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#define XMC_BANK1 ((xmc_bank1_type *) XMC_BANK1_REG_BASE)
|
||||
#define XMC_BANK2 ((xmc_bank2_type *) XMC_BANK2_REG_BASE)
|
||||
|
||||
/** @defgroup XMC_exported_functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
void xmc_nor_sram_reset(xmc_nor_sram_subbank_type xmc_subbank);
|
||||
void xmc_nor_sram_init(xmc_norsram_init_type* xmc_norsram_init_struct);
|
||||
void xmc_nor_sram_timing_config(xmc_norsram_timing_init_type* xmc_rw_timing_struct,
|
||||
xmc_norsram_timing_init_type* xmc_w_timing_struct);
|
||||
void xmc_norsram_default_para_init(xmc_norsram_init_type* xmc_nor_sram_init_struct);
|
||||
void xmc_norsram_timing_default_para_init(xmc_norsram_timing_init_type* xmc_rw_timing_struct,
|
||||
xmc_norsram_timing_init_type* xmc_w_timing_struct);
|
||||
void xmc_nor_sram_enable(xmc_nor_sram_subbank_type xmc_subbank, confirm_state new_state);
|
||||
void xmc_ext_timing_config(volatile xmc_nor_sram_subbank_type xmc_sub_bank, uint16_t w2w_timing, uint16_t r2r_timing);
|
||||
void xmc_nand_reset(xmc_class_bank_type xmc_bank);
|
||||
void xmc_nand_init(xmc_nand_init_type* xmc_nand_init_struct);
|
||||
void xmc_nand_timing_config(xmc_nand_timinginit_type* xmc_common_spacetiming_struct,
|
||||
xmc_nand_timinginit_type* xmc_attribute_spacetiming_struct);
|
||||
void xmc_nand_default_para_init(xmc_nand_init_type* xmc_nand_init_struct);
|
||||
void xmc_nand_timing_default_para_init(xmc_nand_timinginit_type* xmc_common_spacetiming_struct,
|
||||
xmc_nand_timinginit_type* xmc_attribute_spacetiming_struct);
|
||||
void xmc_nand_enable(xmc_class_bank_type xmc_bank, confirm_state new_state);
|
||||
void xmc_nand_ecc_enable(xmc_class_bank_type xmc_bank, confirm_state new_state);
|
||||
uint32_t xmc_ecc_get(xmc_class_bank_type xmc_bank);
|
||||
void xmc_interrupt_enable(xmc_class_bank_type xmc_bank, xmc_interrupt_sources_type xmc_int, confirm_state new_state);
|
||||
flag_status xmc_flag_status_get(xmc_class_bank_type xmc_bank, xmc_interrupt_flag_type xmc_flag);
|
||||
flag_status xmc_interrupt_flag_status_get(xmc_class_bank_type xmc_bank, xmc_interrupt_flag_type xmc_flag);
|
||||
void xmc_flag_clear(xmc_class_bank_type xmc_bank, xmc_interrupt_flag_type xmc_flag);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,233 @@
|
|||
/**
|
||||
**************************************************************************
|
||||
* @file at32f403a_407_acc.c
|
||||
* @brief contains all the functions for the acc firmware library
|
||||
**************************************************************************
|
||||
*
|
||||
* Copyright (c) 2025, Artery Technology, All rights reserved.
|
||||
*
|
||||
* The software Board Support Package (BSP) that is made available to
|
||||
* download from Artery official website is the copyrighted work of Artery.
|
||||
* Artery authorizes customers to use, copy, and distribute the BSP
|
||||
* software and its related documentation for the purpose of design and
|
||||
* development in conjunction with Artery microcontrollers. Use of the
|
||||
* software is governed by this copyright notice and the following disclaimer.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
|
||||
* GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
|
||||
* TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
|
||||
* STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
|
||||
* INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
|
||||
*
|
||||
**************************************************************************
|
||||
*/
|
||||
|
||||
#include "at32f403a_407_conf.h"
|
||||
|
||||
/** @addtogroup AT32F403A_407_periph_driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup ACC
|
||||
* @brief ACC driver modules
|
||||
* @{
|
||||
*/
|
||||
|
||||
#ifdef ACC_MODULE_ENABLED
|
||||
|
||||
/** @defgroup ACC_private_functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief enable or disable the acc calibration mode.
|
||||
* @param acc_trim: specifies the acc calibration type.
|
||||
* this parameter can be one of the following values:
|
||||
* - ACC_CAL_HICKCAL
|
||||
* - ACC_CAL_HICKTRIM
|
||||
* @param new_state: specifies the acc calibration to be enabled or disabled.(TRUE or FALSE)
|
||||
* @retval none
|
||||
*/
|
||||
void acc_calibration_mode_enable(uint16_t acc_trim, confirm_state new_state)
|
||||
{
|
||||
if(acc_trim == ACC_CAL_HICKCAL)
|
||||
{
|
||||
ACC->ctrl1_bit.entrim = FALSE;
|
||||
}
|
||||
else
|
||||
{
|
||||
ACC->ctrl1_bit.entrim = TRUE;
|
||||
}
|
||||
ACC->ctrl1_bit.calon = new_state;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief store calibration step data in acc's ctrl1 register.
|
||||
* @param step_value: value to be stored in the acc's ctrl1 register
|
||||
* @retval none
|
||||
*/
|
||||
void acc_step_set(uint8_t step_value)
|
||||
{
|
||||
ACC->ctrl1_bit.step = step_value;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief enable or disable the specified acc interrupts.
|
||||
* @param acc_int: specifies the acc interrupt sources to be enabled or disabled.
|
||||
* this parameter can be one of the following values:
|
||||
* - ACC_CALRDYIEN_INT
|
||||
* - ACC_EIEN_INT
|
||||
* @param new_state (TRUE or FALSE)
|
||||
* @retval none
|
||||
*/
|
||||
void acc_interrupt_enable(uint16_t acc_int, confirm_state new_state)
|
||||
{
|
||||
if(acc_int == ACC_CALRDYIEN_INT)
|
||||
{
|
||||
ACC->ctrl1_bit.calrdyien = new_state;
|
||||
}
|
||||
else
|
||||
{
|
||||
ACC->ctrl1_bit.eien = new_state;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief return the current acc hicktrim value.
|
||||
* @param none
|
||||
* @retval 8-bit hicktrim value.
|
||||
*/
|
||||
uint8_t acc_hicktrim_get(void)
|
||||
{
|
||||
return ((uint8_t)(ACC->ctrl2_bit.hicktrim));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief return the current acc hickcal value.
|
||||
* @param none
|
||||
* @retval 8-bit hicktrim value.
|
||||
*/
|
||||
uint8_t acc_hickcal_get(void)
|
||||
{
|
||||
return ((uint8_t)(ACC->ctrl2_bit.hickcal));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief wtire the value to acc c1 register.
|
||||
* @param acc_c1_value
|
||||
* @retval none.
|
||||
*/
|
||||
void acc_write_c1(uint16_t acc_c1_value)
|
||||
{
|
||||
ACC->c1 = acc_c1_value;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief wtire the value to acc c2 register.
|
||||
* @param acc_c2_value
|
||||
* @retval none.
|
||||
*/
|
||||
void acc_write_c2(uint16_t acc_c2_value)
|
||||
{
|
||||
ACC->c2 = acc_c2_value;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief wtire the value to acc c3 register.
|
||||
* @param acc_c3_value
|
||||
* @retval none.
|
||||
*/
|
||||
void acc_write_c3(uint16_t acc_c3_value)
|
||||
{
|
||||
ACC->c3 = acc_c3_value;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief return the current acc c1 value.
|
||||
* @param none
|
||||
* @retval 16-bit c1 value.
|
||||
*/
|
||||
uint16_t acc_read_c1(void)
|
||||
{
|
||||
return ((uint16_t)(ACC->c1));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief return the current acc c2 value.
|
||||
* @param none
|
||||
* @retval 16-bit c2 value.
|
||||
*/
|
||||
uint16_t acc_read_c2(void)
|
||||
{
|
||||
return ((uint16_t)(ACC->c2));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief return the current acc c3 value.
|
||||
* @param none
|
||||
* @retval 16-bit c3 value.
|
||||
*/
|
||||
uint16_t acc_read_c3(void)
|
||||
{
|
||||
return ((uint16_t)(ACC->c3));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief check whether the specified acc flag is set or not.
|
||||
* @param acc_flag: specifies the flag to check.
|
||||
* this parameter can be one of the following values:
|
||||
* - ACC_RSLOST_FLAG
|
||||
* - ACC_CALRDY_FLAG
|
||||
* @retval flag_status (SET or RESET)
|
||||
*/
|
||||
flag_status acc_flag_get(uint16_t acc_flag)
|
||||
{
|
||||
if(acc_flag == ACC_CALRDY_FLAG)
|
||||
return (flag_status)(ACC->sts_bit.calrdy);
|
||||
else
|
||||
return (flag_status)(ACC->sts_bit.rslost);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief check whether the specified acc interrupt flag is set or not.
|
||||
* @param acc_flag: specifies the flag to check.
|
||||
* this parameter can be one of the following values:
|
||||
* - ACC_RSLOST_FLAG
|
||||
* - ACC_CALRDY_FLAG
|
||||
* @retval flag_status (SET or RESET)
|
||||
*/
|
||||
flag_status acc_interrupt_flag_get(uint16_t acc_flag)
|
||||
{
|
||||
if(acc_flag == ACC_CALRDY_FLAG)
|
||||
return (flag_status)(ACC->sts_bit.calrdy && ACC->ctrl1_bit.calrdyien);
|
||||
else
|
||||
return (flag_status)(ACC->sts_bit.rslost && ACC->ctrl1_bit.eien);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief clear the specified acc flag is set or not.
|
||||
* @param acc_flag: specifies the flag to check.
|
||||
* this parameter can be any combination of the following values:
|
||||
* - ACC_RSLOST_FLAG
|
||||
* - ACC_CALRDY_FLAG
|
||||
* @retval none
|
||||
*/
|
||||
void acc_flag_clear(uint16_t acc_flag)
|
||||
{
|
||||
ACC->sts = ~acc_flag;
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
|
@ -0,0 +1,871 @@
|
|||
/**
|
||||
**************************************************************************
|
||||
* @file at32f403a_407_adc.c
|
||||
* @brief contains all the functions for the adc firmware library
|
||||
**************************************************************************
|
||||
*
|
||||
* Copyright (c) 2025, Artery Technology, All rights reserved.
|
||||
*
|
||||
* The software Board Support Package (BSP) that is made available to
|
||||
* download from Artery official website is the copyrighted work of Artery.
|
||||
* Artery authorizes customers to use, copy, and distribute the BSP
|
||||
* software and its related documentation for the purpose of design and
|
||||
* development in conjunction with Artery microcontrollers. Use of the
|
||||
* software is governed by this copyright notice and the following disclaimer.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
|
||||
* GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
|
||||
* TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
|
||||
* STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
|
||||
* INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
|
||||
*
|
||||
**************************************************************************
|
||||
*/
|
||||
|
||||
#include "at32f403a_407_conf.h"
|
||||
|
||||
/** @addtogroup AT32F403A_407_periph_driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup ADC
|
||||
* @brief ADC driver modules
|
||||
* @{
|
||||
*/
|
||||
|
||||
#ifdef ADC_MODULE_ENABLED
|
||||
|
||||
/** @defgroup ADC_private_functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief deinitialize the adc peripheral registers to their default reset values.
|
||||
* @param adc_x: select the adc peripheral.
|
||||
* this parameter can be one of the following values:
|
||||
* ADC1, ADC2, ADC3.
|
||||
* @retval none
|
||||
*/
|
||||
void adc_reset(adc_type *adc_x)
|
||||
{
|
||||
if(adc_x == ADC1)
|
||||
{
|
||||
crm_periph_reset(CRM_ADC1_PERIPH_RESET, TRUE);
|
||||
crm_periph_reset(CRM_ADC1_PERIPH_RESET, FALSE);
|
||||
}
|
||||
else if(adc_x == ADC2)
|
||||
{
|
||||
crm_periph_reset(CRM_ADC2_PERIPH_RESET, TRUE);
|
||||
crm_periph_reset(CRM_ADC2_PERIPH_RESET, FALSE);
|
||||
}
|
||||
else if(adc_x == ADC3)
|
||||
{
|
||||
crm_periph_reset(CRM_ADC3_PERIPH_RESET, TRUE);
|
||||
crm_periph_reset(CRM_ADC3_PERIPH_RESET, FALSE);
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief enable or disable the specified adc peripheral.
|
||||
* @param adc_x: select the adc peripheral.
|
||||
* this parameter can be one of the following values:
|
||||
* ADC1, ADC2, ADC3.
|
||||
* @param new_state: new state of a/d converter.
|
||||
* this parameter can be: TRUE or FALSE.
|
||||
* note:after adc ready,user set adcen bit will cause ordinary conversion
|
||||
* @retval none
|
||||
*/
|
||||
void adc_enable(adc_type *adc_x, confirm_state new_state)
|
||||
{
|
||||
adc_x->ctrl2_bit.adcen = new_state;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief select combine mode of the specified adc peripheral.
|
||||
* @param combine_mode: select the adc combine mode.
|
||||
* this parameter can be one of the following values:
|
||||
* - ADC_INDEPENDENT_MODE
|
||||
* - ADC_ORDINARY_SMLT_PREEMPT_SMLT_MODE
|
||||
* - ADC_ORDINARY_SMLT_PREEMPT_INTERLTRIG_MODE
|
||||
* - ADC_ORDINARY_SHORTSHIFT_PREEMPT_SMLT_MODE
|
||||
* - ADC_ORDINARY_LONGSHIFT_PREEMPT_SMLT_MODE
|
||||
* - ADC_PREEMPT_SMLT_ONLY_MODE
|
||||
* - ADC_ORDINARY_SMLT_ONLY_MODE
|
||||
* - ADC_ORDINARY_SHORTSHIFT_ONLY_MODE
|
||||
* - ADC_ORDINARY_LONGSHIFT_ONLY_MODE
|
||||
* - ADC_PREEMPT_INTERLTRIG_ONLY_MODE
|
||||
* note:these bits are reserved in adc2 and adc3
|
||||
* @retval none
|
||||
*/
|
||||
void adc_combine_mode_select(adc_combine_mode_type combine_mode)
|
||||
{
|
||||
ADC1->ctrl1_bit.mssel = combine_mode;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief adc base default para init.
|
||||
* @param sequence_mode: set the state of adc sequence mode.
|
||||
* this parameter can be:TRUE or FALSE
|
||||
* @param repeat_mode: set the state of adc repeat conversion mode.
|
||||
* this parameter can be:TRUE or FALSE
|
||||
* @param data_align: set the state of adc data alignment.
|
||||
* this parameter can be one of the following values:
|
||||
* - ADC_RIGHT_ALIGNMENT
|
||||
* - ADC_LEFT_ALIGNMENT
|
||||
* @param ordinary_channel_length: configure the adc ordinary channel sequence length.
|
||||
* this parameter can be:
|
||||
* - (0x1~0x10)
|
||||
* @retval none
|
||||
*/
|
||||
void adc_base_default_para_init(adc_base_config_type *adc_base_struct)
|
||||
{
|
||||
adc_base_struct->sequence_mode = FALSE;
|
||||
adc_base_struct->repeat_mode = FALSE;
|
||||
adc_base_struct->data_align = ADC_RIGHT_ALIGNMENT;
|
||||
adc_base_struct->ordinary_channel_length = 1;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief initialize the adc peripheral according to the specified parameters.
|
||||
* @param adc_x: select the adc peripheral.
|
||||
* this parameter can be one of the following values:
|
||||
* ADC1, ADC2, ADC3.
|
||||
* @param sequence_mode: set the state of adc sequence mode.
|
||||
* this parameter can be:TRUE or FALSE
|
||||
* @param repeat_mode: set the state of adc repeat conversion mode.
|
||||
* this parameter can be:TRUE or FALSE
|
||||
* @param data_align: set the state of adc data alignment.
|
||||
* this parameter can be one of the following values:
|
||||
* - ADC_RIGHT_ALIGNMENT
|
||||
* - ADC_LEFT_ALIGNMENT
|
||||
* @param ordinary_channel_length: configure the adc ordinary channel sequence length.
|
||||
* this parameter can be:
|
||||
* - (0x1~0x10)
|
||||
* @retval none
|
||||
*/
|
||||
void adc_base_config(adc_type *adc_x, adc_base_config_type *adc_base_struct)
|
||||
{
|
||||
adc_x->ctrl1_bit.sqen = adc_base_struct->sequence_mode;
|
||||
adc_x->ctrl2_bit.rpen = adc_base_struct->repeat_mode;
|
||||
adc_x->ctrl2_bit.dtalign = adc_base_struct->data_align;
|
||||
adc_x->osq1_bit.oclen = adc_base_struct->ordinary_channel_length - 1;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief enable or disable the adc dma transfer.
|
||||
* @param adc_x: select the adc peripheral.
|
||||
* this parameter can be one of the following values:
|
||||
* ADC1, ADC3.
|
||||
* note:this bit is reserved in adc2
|
||||
* @param new_state: new state of the adc dma transfer.
|
||||
* this parameter can be: TRUE or FALSE.
|
||||
* @retval none
|
||||
*/
|
||||
void adc_dma_mode_enable(adc_type *adc_x, confirm_state new_state)
|
||||
{
|
||||
adc_x->ctrl2_bit.ocdmaen = new_state;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief enable or disable the specified adc interrupts.
|
||||
* @param adc_x: select the adc peripheral.
|
||||
* this parameter can be one of the following values:
|
||||
* ADC1, ADC2, ADC3.
|
||||
* @param adc_int: specifies the adc interrupt sources to be enabled or disabled.
|
||||
* this parameter can be one of the following values:
|
||||
* - ADC_VMOR_INT
|
||||
* - ADC_CCE_INT
|
||||
* - ADC_PCCE_INT
|
||||
* @param new_state: new state of the specified adc interrupts.
|
||||
* this parameter can be: TRUE or FALSE.
|
||||
* @retval none
|
||||
*/
|
||||
void adc_interrupt_enable(adc_type *adc_x, uint32_t adc_int, confirm_state new_state)
|
||||
{
|
||||
if(new_state == TRUE)
|
||||
{
|
||||
adc_x->ctrl1 |= adc_int;
|
||||
}
|
||||
else if(new_state == FALSE)
|
||||
{
|
||||
adc_x->ctrl1 &= ~adc_int;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief initialize calibration register of the specified adc peripheral.
|
||||
* @param adc_x: select the adc peripheral.
|
||||
* this parameter can be one of the following values:
|
||||
* ADC1, ADC2, ADC3.
|
||||
* @retval none
|
||||
*/
|
||||
void adc_calibration_init(adc_type *adc_x)
|
||||
{
|
||||
adc_x->ctrl2_bit.adcalinit = TRUE;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief get calibration register's initialize status of the specified adc peripheral.
|
||||
* @param adc_x: select the adc peripheral.
|
||||
* this parameter can be one of the following values:
|
||||
* ADC1, ADC2, ADC3.
|
||||
* @retval the new state of reset calibration register status(SET or RESET).
|
||||
*/
|
||||
flag_status adc_calibration_init_status_get(adc_type *adc_x)
|
||||
{
|
||||
if(adc_x->ctrl2_bit.adcalinit)
|
||||
{
|
||||
return SET;
|
||||
}
|
||||
else
|
||||
{
|
||||
return RESET;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief start calibration process of the specified adc peripheral.
|
||||
* @param adc_x: select the adc peripheral.
|
||||
* this parameter can be one of the following values:
|
||||
* ADC1, ADC2, ADC3.
|
||||
* @retval none
|
||||
*/
|
||||
void adc_calibration_start(adc_type *adc_x)
|
||||
{
|
||||
adc_x->ctrl2_bit.adcal = TRUE;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief get calibration status of the specified adc peripheral.
|
||||
* @param adc_x: select the adc peripheral.
|
||||
* this parameter can be one of the following values:
|
||||
* ADC1, ADC2, ADC3.
|
||||
* @retval the new state of calibration status(SET or RESET).
|
||||
*/
|
||||
flag_status adc_calibration_status_get(adc_type *adc_x)
|
||||
{
|
||||
if(adc_x->ctrl2_bit.adcal)
|
||||
{
|
||||
return SET;
|
||||
}
|
||||
else
|
||||
{
|
||||
return RESET;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief enable or disable the voltage monitoring on single/all ordinary or preempt channels of the specified adc peripheral.
|
||||
* @param adc_x: select the adc peripheral.
|
||||
* this parameter can be one of the following values:
|
||||
* ADC1, ADC2, ADC3.
|
||||
* @param adc_voltage_monitoring: choose the adc_voltage_monitoring config.
|
||||
* this parameter can be one of the following values:
|
||||
* - ADC_VMONITOR_SINGLE_ORDINARY
|
||||
* - ADC_VMONITOR_SINGLE_PREEMPT
|
||||
* - ADC_VMONITOR_SINGLE_ORDINARY_PREEMPT
|
||||
* - ADC_VMONITOR_ALL_ORDINARY
|
||||
* - ADC_VMONITOR_ALL_PREEMPT
|
||||
* - ADC_VMONITOR_ALL_ORDINARY_PREEMPT
|
||||
* - ADC_VMONITOR_NONE
|
||||
* @retval none
|
||||
*/
|
||||
void adc_voltage_monitor_enable(adc_type *adc_x, adc_voltage_monitoring_type adc_voltage_monitoring)
|
||||
{
|
||||
adc_x->ctrl1_bit.ocvmen = FALSE;
|
||||
adc_x->ctrl1_bit.pcvmen = FALSE;
|
||||
adc_x->ctrl1_bit.vmsgen = FALSE;
|
||||
adc_x->ctrl1 |= adc_voltage_monitoring;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief set voltage monitoring's high and low thresholds value of the specified adc peripheral.
|
||||
* @param adc_x: select the adc peripheral.
|
||||
* this parameter can be one of the following values:
|
||||
* ADC1, ADC2, ADC3.
|
||||
* @param adc_high_threshold: voltage monitoring's high thresholds value.
|
||||
* this parameter can be:
|
||||
* - (0x000~0xFFF)
|
||||
* @param adc_low_threshold: voltage monitoring's low thresholds value.
|
||||
* this parameter can be:
|
||||
* - (0x000~0xFFF)
|
||||
* @retval none
|
||||
*/
|
||||
void adc_voltage_monitor_threshold_value_set(adc_type *adc_x, uint16_t adc_high_threshold, uint16_t adc_low_threshold)
|
||||
{
|
||||
adc_x->vmhb_bit.vmhb = adc_high_threshold;
|
||||
adc_x->vmlb_bit.vmlb = adc_low_threshold;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief select the voltage monitoring's channel of the specified adc peripheral.
|
||||
* @param adc_x: select the adc peripheral.
|
||||
* this parameter can be one of the following values:
|
||||
* ADC1, ADC2, ADC3.
|
||||
* @param adc_channel: select the channel.
|
||||
* this parameter can be one of the following values:
|
||||
* - ADC_CHANNEL_0 - ADC_CHANNEL_1 - ADC_CHANNEL_2 - ADC_CHANNEL_3
|
||||
* - ADC_CHANNEL_4 - ADC_CHANNEL_5 - ADC_CHANNEL_6 - ADC_CHANNEL_7
|
||||
* - ADC_CHANNEL_8 - ADC_CHANNEL_9 - ADC_CHANNEL_10 - ADC_CHANNEL_11
|
||||
* - ADC_CHANNEL_12 - ADC_CHANNEL_13 - ADC_CHANNEL_14 - ADC_CHANNEL_15
|
||||
* - ADC_CHANNEL_16 - ADC_CHANNEL_17
|
||||
* @retval none
|
||||
*/
|
||||
void adc_voltage_monitor_single_channel_select(adc_type *adc_x, adc_channel_select_type adc_channel)
|
||||
{
|
||||
adc_x->ctrl1_bit.vmcsel = adc_channel;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief set ordinary channel's corresponding rank in the sequencer and sample time of the specified adc peripheral.
|
||||
* @param adc_x: select the adc peripheral.
|
||||
* this parameter can be one of the following values:
|
||||
* ADC1, ADC2, ADC3.
|
||||
* @param adc_channel: select the channel.
|
||||
* this parameter can be one of the following values:
|
||||
* - ADC_CHANNEL_0 - ADC_CHANNEL_1 - ADC_CHANNEL_2 - ADC_CHANNEL_3
|
||||
* - ADC_CHANNEL_4 - ADC_CHANNEL_5 - ADC_CHANNEL_6 - ADC_CHANNEL_7
|
||||
* - ADC_CHANNEL_8 - ADC_CHANNEL_9 - ADC_CHANNEL_10 - ADC_CHANNEL_11
|
||||
* - ADC_CHANNEL_12 - ADC_CHANNEL_13 - ADC_CHANNEL_14 - ADC_CHANNEL_15
|
||||
* - ADC_CHANNEL_16 - ADC_CHANNEL_17
|
||||
* @param adc_sequence: set rank in the ordinary group sequencer.
|
||||
* this parameter must be:
|
||||
* - between 1 to 16
|
||||
* @param adc_sampletime: set the sampletime of adc channel.
|
||||
* this parameter can be one of the following values:
|
||||
* - ADC_SAMPLETIME_1_5
|
||||
* - ADC_SAMPLETIME_7_5
|
||||
* - ADC_SAMPLETIME_13_5
|
||||
* - ADC_SAMPLETIME_28_5
|
||||
* - ADC_SAMPLETIME_41_5
|
||||
* - ADC_SAMPLETIME_55_5
|
||||
* - ADC_SAMPLETIME_71_5
|
||||
* - ADC_SAMPLETIME_239_5
|
||||
* @retval none
|
||||
*/
|
||||
void adc_ordinary_channel_set(adc_type *adc_x, adc_channel_select_type adc_channel, uint8_t adc_sequence, adc_sampletime_select_type adc_sampletime)
|
||||
{
|
||||
uint32_t tmp_reg;
|
||||
if(adc_channel < ADC_CHANNEL_10)
|
||||
{
|
||||
tmp_reg = adc_x->spt2;
|
||||
tmp_reg &= ~(0x07 << 3 * adc_channel);
|
||||
tmp_reg |= adc_sampletime << 3 * adc_channel;
|
||||
adc_x->spt2 = tmp_reg;
|
||||
}
|
||||
else
|
||||
{
|
||||
tmp_reg = adc_x->spt1;
|
||||
tmp_reg &= ~(0x07 << 3 * (adc_channel - ADC_CHANNEL_10));
|
||||
tmp_reg |= adc_sampletime << 3 * (adc_channel - ADC_CHANNEL_10);
|
||||
adc_x->spt1 = tmp_reg;
|
||||
}
|
||||
|
||||
if(adc_sequence >= 13)
|
||||
{
|
||||
tmp_reg = adc_x->osq1;
|
||||
tmp_reg &= ~(0x01F << 5 * (adc_sequence - 13));
|
||||
tmp_reg |= adc_channel << 5 * (adc_sequence - 13);
|
||||
adc_x->osq1 = tmp_reg;
|
||||
}
|
||||
else if(adc_sequence >= 7)
|
||||
{
|
||||
tmp_reg = adc_x->osq2;
|
||||
tmp_reg &= ~(0x01F << 5 * (adc_sequence - 7));
|
||||
tmp_reg |= adc_channel << 5 * (adc_sequence - 7);
|
||||
adc_x->osq2 = tmp_reg;
|
||||
}
|
||||
else
|
||||
{
|
||||
tmp_reg = adc_x->osq3;
|
||||
tmp_reg &= ~(0x01F << 5 * (adc_sequence - 1));
|
||||
tmp_reg |= adc_channel << 5 * (adc_sequence - 1);
|
||||
adc_x->osq3 = tmp_reg;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief set preempt channel lenghth of the specified adc peripheral.
|
||||
* @param adc_x: select the adc peripheral.
|
||||
* this parameter can be one of the following values:
|
||||
* ADC1, ADC2, ADC3.
|
||||
* @param adc_channel_lenght: set the adc preempt channel lenghth.
|
||||
* this parameter can be:
|
||||
* - (0x1~0x4)
|
||||
* @retval none
|
||||
*/
|
||||
void adc_preempt_channel_length_set(adc_type *adc_x, uint8_t adc_channel_lenght)
|
||||
{
|
||||
adc_x->psq_bit.pclen = adc_channel_lenght - 1;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief configure preempt channel's corresponding rank in the sequencer and sample time of the specified adc peripheral.
|
||||
* @param adc_x: select the adc peripheral.
|
||||
* this parameter can be one of the following values:
|
||||
* ADC1, ADC2, ADC3.
|
||||
* @param adc_channel: select the channel.
|
||||
* this parameter can be one of the following values:
|
||||
* - ADC_CHANNEL_0 - ADC_CHANNEL_1 - ADC_CHANNEL_2 - ADC_CHANNEL_3
|
||||
* - ADC_CHANNEL_4 - ADC_CHANNEL_5 - ADC_CHANNEL_6 - ADC_CHANNEL_7
|
||||
* - ADC_CHANNEL_8 - ADC_CHANNEL_9 - ADC_CHANNEL_10 - ADC_CHANNEL_11
|
||||
* - ADC_CHANNEL_12 - ADC_CHANNEL_13 - ADC_CHANNEL_14 - ADC_CHANNEL_15
|
||||
* - ADC_CHANNEL_16 - ADC_CHANNEL_17
|
||||
* @param adc_sequence: set rank in the preempt group sequencer.
|
||||
* this parameter must be:
|
||||
* - between 1 to 4
|
||||
* @param adc_sampletime: config the sampletime of adc channel.
|
||||
* this parameter can be one of the following values:
|
||||
* - ADC_SAMPLETIME_1_5
|
||||
* - ADC_SAMPLETIME_7_5
|
||||
* - ADC_SAMPLETIME_13_5
|
||||
* - ADC_SAMPLETIME_28_5
|
||||
* - ADC_SAMPLETIME_41_5
|
||||
* - ADC_SAMPLETIME_55_5
|
||||
* - ADC_SAMPLETIME_71_5
|
||||
* - ADC_SAMPLETIME_239_5
|
||||
* @retval none
|
||||
*/
|
||||
void adc_preempt_channel_set(adc_type *adc_x, adc_channel_select_type adc_channel, uint8_t adc_sequence, adc_sampletime_select_type adc_sampletime)
|
||||
{
|
||||
uint32_t tmp_reg;
|
||||
uint8_t sequence_index;
|
||||
if(adc_channel < ADC_CHANNEL_10)
|
||||
{
|
||||
tmp_reg = adc_x->spt2;
|
||||
tmp_reg &= ~(0x07 << 3 * adc_channel);
|
||||
tmp_reg |= adc_sampletime << 3 * adc_channel;
|
||||
adc_x->spt2 = tmp_reg;
|
||||
}
|
||||
else
|
||||
{
|
||||
tmp_reg = adc_x->spt1;
|
||||
tmp_reg &= ~(0x07 << 3 * (adc_channel - ADC_CHANNEL_10));
|
||||
tmp_reg |= adc_sampletime << 3 * (adc_channel - ADC_CHANNEL_10);
|
||||
adc_x->spt1 = tmp_reg;
|
||||
}
|
||||
|
||||
sequence_index = adc_sequence + 3 - adc_x->psq_bit.pclen;
|
||||
switch(sequence_index)
|
||||
{
|
||||
case 1:
|
||||
adc_x->psq_bit.psn1 = adc_channel;
|
||||
break;
|
||||
case 2:
|
||||
adc_x->psq_bit.psn2 = adc_channel;
|
||||
break;
|
||||
case 3:
|
||||
adc_x->psq_bit.psn3 = adc_channel;
|
||||
break;
|
||||
case 4:
|
||||
adc_x->psq_bit.psn4 = adc_channel;
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief enable or disable the ordinary channel's external trigger and
|
||||
* set external trigger event of the specified adc peripheral.
|
||||
* @param adc_x: select the adc peripheral.
|
||||
* this parameter can be one of the following values:
|
||||
* ADC1, ADC2, ADC3.
|
||||
* @param adc_ordinary_trig: select the external trigger event.
|
||||
* this parameter can be one of the following values:
|
||||
* adc1 & adc2
|
||||
* - ADC12_ORDINARY_TRIG_TMR1CH1 - ADC12_ORDINARY_TRIG_TMR1CH2 - ADC12_ORDINARY_TRIG_TMR1CH3 - ADC12_ORDINARY_TRIG_TMR2CH2
|
||||
* - ADC12_ORDINARY_TRIG_TMR3TRGOUT - ADC12_ORDINARY_TRIG_TMR4CH4 - ADC12_ORDINARY_TRIG_EXINT11_TMR8TRGOUT - ADC12_ORDINARY_TRIG_SOFTWARE
|
||||
* - ADC12_ORDINARY_TRIG_TMR1TRGOUT - ADC12_ORDINARY_TRIG_TMR8CH1 - ADC12_ORDINARY_TRIG_TMR8CH2
|
||||
* adc3
|
||||
* - ADC3_ORDINARY_TRIG_TMR3CH1 - ADC3_ORDINARY_TRIG_TMR2CH3 - ADC3_ORDINARY_TRIG_TMR1CH3 - ADC3_ORDINARY_TRIG_TMR8CH1
|
||||
* - ADC3_ORDINARY_TRIG_TMR8TRGOUT - ADC3_ORDINARY_TRIG_TMR5CH1 - ADC3_ORDINARY_TRIG_TMR5CH3 - ADC3_ORDINARY_TRIG_SOFTWARE
|
||||
* - ADC3_ORDINARY_TRIG_TMR1TRGOUT - ADC3_ORDINARY_TRIG_TMR1CH1 - ADC3_ORDINARY_TRIG_TMR8CH3
|
||||
* @param new_state: new state of ordinary channel's external trigger.
|
||||
* this parameter can be: TRUE or FALSE.
|
||||
* @retval none
|
||||
*/
|
||||
void adc_ordinary_conversion_trigger_set(adc_type *adc_x, adc_ordinary_trig_select_type adc_ordinary_trig, confirm_state new_state)
|
||||
{
|
||||
if(adc_ordinary_trig > 7)
|
||||
{
|
||||
adc_x->ctrl2_bit.octesel_h = 1;
|
||||
adc_x->ctrl2_bit.octesel_l = adc_ordinary_trig & 0x7;
|
||||
}
|
||||
else
|
||||
{
|
||||
adc_x->ctrl2_bit.octesel_h = 0;
|
||||
adc_x->ctrl2_bit.octesel_l = adc_ordinary_trig & 0x7;
|
||||
}
|
||||
adc_x->ctrl2_bit.octen = new_state;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief enable or disable the preempt channel's external trigger and
|
||||
* set external trigger event of the specified adc peripheral.
|
||||
* @param adc_x: select the adc peripheral.
|
||||
* this parameter can be one of the following values:
|
||||
* ADC1, ADC2, ADC3.
|
||||
* @param adc_preempt_trig: select the external trigger event.
|
||||
* this parameter can be one of the following values:
|
||||
* adc1 & adc2
|
||||
* - ADC12_PREEMPT_TRIG_TMR1TRGOUT - ADC12_PREEMPT_TRIG_TMR1CH4 - ADC12_PREEMPT_TRIG_TMR2TRGOUT - ADC12_PREEMPT_TRIG_TMR2CH1
|
||||
* - ADC12_PREEMPT_TRIG_TMR3CH4 - ADC12_PREEMPT_TRIG_TMR4TRGOUT - ADC12_PREEMPT_TRIG_EXINT15_TMR8CH4 - ADC12_PREEMPT_TRIG_SOFTWARE
|
||||
* - ADC12_PREEMPT_TRIG_TMR1CH1 - ADC12_PREEMPT_TRIG_TMR8CH1 - ADC12_PREEMPT_TRIG_TMR8TRGOUT
|
||||
* adc3
|
||||
* - ADC3_PREEMPT_TRIG_TMR1TRGOUT - ADC3_PREEMPT_TRIG_TMR1CH4 - ADC3_PREEMPT_TRIG_TMR4CH3 - ADC3_PREEMPT_TRIG_TMR8CH2
|
||||
* - ADC3_PREEMPT_TRIG_TMR8CH4 - ADC3_PREEMPT_TRIG_TMR5TRGOUT - ADC3_PREEMPT_TRIG_TMR5CH4 - ADC3_PREEMPT_TRIG_SOFTWARE
|
||||
* - ADC3_PREEMPT_TRIG_TMR1CH1 - ADC3_PREEMPT_TRIG_TMR1CH2 - ADC3_PREEMPT_TRIG_TMR8TRGOUT
|
||||
* @param new_state: new state of preempt channel's external trigger.
|
||||
* this parameter can be: TRUE or FALSE.
|
||||
* @retval none
|
||||
*/
|
||||
void adc_preempt_conversion_trigger_set(adc_type *adc_x, adc_preempt_trig_select_type adc_preempt_trig, confirm_state new_state)
|
||||
{
|
||||
if(adc_preempt_trig > 7)
|
||||
{
|
||||
adc_x->ctrl2_bit.pctesel_h = 1;
|
||||
adc_x->ctrl2_bit.pctesel_l = adc_preempt_trig & 0x7;
|
||||
}
|
||||
else
|
||||
{
|
||||
adc_x->ctrl2_bit.pctesel_h = 0;
|
||||
adc_x->ctrl2_bit.pctesel_l = adc_preempt_trig & 0x7;
|
||||
}
|
||||
adc_x->ctrl2_bit.pcten = new_state;
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief set preempt channel's conversion value offset of the specified adc peripheral.
|
||||
* @param adc_x: select the adc peripheral.
|
||||
* this parameter can be one of the following values:
|
||||
* ADC1, ADC2, ADC3.
|
||||
* @param adc_preempt_channel: select the preempt channel.
|
||||
* this parameter can be one of the following values:
|
||||
* - ADC_PREEMPT_CHANNEL_1
|
||||
* - ADC_PREEMPT_CHANNEL_2
|
||||
* - ADC_PREEMPT_CHANNEL_3
|
||||
* - ADC_PREEMPT_CHANNEL_4
|
||||
* @param adc_offset_value: set the adc preempt channel's conversion value offset.
|
||||
* this parameter can be:
|
||||
* - (0x000~0xFFF)
|
||||
* @retval none
|
||||
*/
|
||||
void adc_preempt_offset_value_set(adc_type *adc_x, adc_preempt_channel_type adc_preempt_channel, uint16_t adc_offset_value)
|
||||
{
|
||||
switch(adc_preempt_channel)
|
||||
{
|
||||
case ADC_PREEMPT_CHANNEL_1:
|
||||
adc_x->pcdto1_bit.pcdto1 = adc_offset_value;
|
||||
break;
|
||||
case ADC_PREEMPT_CHANNEL_2:
|
||||
adc_x->pcdto2_bit.pcdto2 = adc_offset_value;
|
||||
break;
|
||||
case ADC_PREEMPT_CHANNEL_3:
|
||||
adc_x->pcdto3_bit.pcdto3 = adc_offset_value;
|
||||
break;
|
||||
case ADC_PREEMPT_CHANNEL_4:
|
||||
adc_x->pcdto4_bit.pcdto4 = adc_offset_value;
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief set partitioned mode channel count of the specified adc peripheral.
|
||||
* @param adc_x: select the adc peripheral.
|
||||
* this parameter can be one of the following values:
|
||||
* ADC1, ADC2, ADC3.
|
||||
* @param adc_channel_count: configure the adc partitioned mode channel count.
|
||||
* this parameter can be:
|
||||
* - (0x1~0x8)
|
||||
* @retval none
|
||||
*/
|
||||
void adc_ordinary_part_count_set(adc_type *adc_x, uint8_t adc_channel_count)
|
||||
{
|
||||
|
||||
adc_x->ctrl1_bit.ocpcnt = adc_channel_count - 1;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief enable or disable the partitioned mode on ordinary channel of the specified adc peripheral.
|
||||
* @param adc_x: select the adc peripheral.
|
||||
* this parameter can be one of the following values:
|
||||
* ADC1, ADC2, ADC3.
|
||||
* @param new_state: new state of ordinary channel's partitioned mode.
|
||||
* this parameter can be: TRUE or FALSE.
|
||||
* @retval none
|
||||
*/
|
||||
void adc_ordinary_part_mode_enable(adc_type *adc_x, confirm_state new_state)
|
||||
{
|
||||
adc_x->ctrl1_bit.ocpen = new_state;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief enable or disable the partitioned mode on preempt channel of the specified adc peripheral.
|
||||
* @param adc_x: select the adc peripheral.
|
||||
* this parameter can be one of the following values:
|
||||
* ADC1, ADC2, ADC3.
|
||||
* @param new_state: new state of preempt channel's partitioned mode.
|
||||
* this parameter can be: TRUE or FALSE.
|
||||
* @retval none
|
||||
*/
|
||||
void adc_preempt_part_mode_enable(adc_type *adc_x, confirm_state new_state)
|
||||
{
|
||||
adc_x->ctrl1_bit.pcpen = new_state;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief enable or disable automatic preempt group conversion of the specified adc peripheral.
|
||||
* @param adc_x: select the adc peripheral.
|
||||
* this parameter can be one of the following values:
|
||||
* ADC1, ADC2, ADC3.
|
||||
* @param new_state: new state of automatic preempt group conversion.
|
||||
* this parameter can be: TRUE or FALSE.
|
||||
* @retval none
|
||||
*/
|
||||
void adc_preempt_auto_mode_enable(adc_type *adc_x, confirm_state new_state)
|
||||
{
|
||||
adc_x->ctrl1_bit.pcautoen = new_state;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief enable or disable the temperature sensor and vintrv channel.
|
||||
* @param new_state: new state of Internal temperature sensor and vintrv.
|
||||
* this parameter can be: TRUE or FALSE.
|
||||
* note:this bit is present only in adc1
|
||||
* @retval none
|
||||
*/
|
||||
void adc_tempersensor_vintrv_enable(confirm_state new_state)
|
||||
{
|
||||
ADC1->ctrl2_bit.itsrven = new_state;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief enable or disable ordinary software start conversion of the specified adc peripheral.
|
||||
* @param adc_x: select the adc peripheral.
|
||||
* this parameter can be one of the following values:
|
||||
* ADC1, ADC2, ADC3.
|
||||
* @param new_state: new state of ordinary software start conversion.
|
||||
* this parameter can be: TRUE or FALSE.
|
||||
* @retval none
|
||||
*/
|
||||
void adc_ordinary_software_trigger_enable(adc_type *adc_x, confirm_state new_state)
|
||||
{
|
||||
adc_x->ctrl2_bit.ocswtrg = new_state;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief get ordinary software start conversion status of the specified adc peripheral.
|
||||
* @param adc_x: select the adc peripheral.
|
||||
* this parameter can be one of the following values:
|
||||
* ADC1, ADC2, ADC3.
|
||||
* @retval the new state of ordinary software start conversion status(SET or RESET).
|
||||
*/
|
||||
flag_status adc_ordinary_software_trigger_status_get(adc_type *adc_x)
|
||||
{
|
||||
if(adc_x->ctrl2_bit.ocswtrg)
|
||||
{
|
||||
return SET;
|
||||
}
|
||||
else
|
||||
{
|
||||
return RESET;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief enable or disable preempt software start conversion of the specified adc peripheral.
|
||||
* @param adc_x: select the adc peripheral.
|
||||
* this parameter can be one of the following values:
|
||||
* ADC1, ADC2, ADC3.
|
||||
* @param new_state: new state of preempt software start conversion.
|
||||
* this parameter can be: TRUE or FALSE.
|
||||
* @retval none
|
||||
*/
|
||||
void adc_preempt_software_trigger_enable(adc_type *adc_x, confirm_state new_state)
|
||||
{
|
||||
adc_x->ctrl2_bit.pcswtrg = new_state;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief get preempt software start conversion status of the specified adc peripheral.
|
||||
* @param adc_x: select the adc peripheral.
|
||||
* this parameter can be one of the following values:
|
||||
* ADC1, ADC2, ADC3.
|
||||
* @retval the new state of preempt software start conversion status(SET or RESET).
|
||||
*/
|
||||
flag_status adc_preempt_software_trigger_status_get(adc_type *adc_x)
|
||||
{
|
||||
if(adc_x->ctrl2_bit.pcswtrg)
|
||||
{
|
||||
return SET;
|
||||
}
|
||||
else
|
||||
{
|
||||
return RESET;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief return the last conversion data for ordinary channel of the specified adc peripheral.
|
||||
* @param adc_x: select the adc peripheral.
|
||||
* this parameter can be one of the following values:
|
||||
* ADC1, ADC2, ADC3.
|
||||
* @retval the last conversion data for ordinary channel.
|
||||
*/
|
||||
uint16_t adc_ordinary_conversion_data_get(adc_type *adc_x)
|
||||
{
|
||||
return (uint16_t)(adc_x->odt_bit.odt);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief return the last conversion data for ordinary channel of combine adc(adc1 and adc2).
|
||||
* @retval the last conversion data for ordinary channel.
|
||||
*/
|
||||
uint32_t adc_combine_ordinary_conversion_data_get(void)
|
||||
{
|
||||
return (uint32_t)(ADC1->odt);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief return the conversion data for selection preempt channel of the specified adc peripheral.
|
||||
* @param adc_x: select the adc peripheral.
|
||||
* this parameter can be one of the following values:
|
||||
* ADC1, ADC2, ADC3.
|
||||
* @param adc_preempt_channel: select the preempt channel.
|
||||
* this parameter can be one of the following values:
|
||||
* - ADC_PREEMPT_CHANNEL_1
|
||||
* - ADC_PREEMPT_CHANNEL_2
|
||||
* - ADC_PREEMPT_CHANNEL_3
|
||||
* - ADC_PREEMPT_CHANNEL_4
|
||||
* @retval the conversion data for selection preempt channel.
|
||||
*/
|
||||
uint16_t adc_preempt_conversion_data_get(adc_type *adc_x, adc_preempt_channel_type adc_preempt_channel)
|
||||
{
|
||||
uint16_t preempt_conv_data_index = 0;
|
||||
switch(adc_preempt_channel)
|
||||
{
|
||||
case ADC_PREEMPT_CHANNEL_1:
|
||||
preempt_conv_data_index = (uint16_t)(adc_x->pdt1_bit.pdt1);
|
||||
break;
|
||||
case ADC_PREEMPT_CHANNEL_2:
|
||||
preempt_conv_data_index = (uint16_t)(adc_x->pdt2_bit.pdt2);
|
||||
break;
|
||||
case ADC_PREEMPT_CHANNEL_3:
|
||||
preempt_conv_data_index = (uint16_t)(adc_x->pdt3_bit.pdt3);
|
||||
break;
|
||||
case ADC_PREEMPT_CHANNEL_4:
|
||||
preempt_conv_data_index = (uint16_t)(adc_x->pdt4_bit.pdt4);
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
return preempt_conv_data_index;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief get flag of the specified adc peripheral.
|
||||
* @param adc_x: select the adc peripheral.
|
||||
* this parameter can be one of the following values:
|
||||
* ADC1, ADC2, ADC3.
|
||||
* @param adc_flag: select the adc flag.
|
||||
* this parameter can be one of the following values:
|
||||
* - ADC_VMOR_FLAG
|
||||
* - ADC_CCE_FLAG
|
||||
* - ADC_PCCE_FLAG
|
||||
* - ADC_PCCS_FLAG(no interrupt associated)
|
||||
* - ADC_OCCS_FLAG(no interrupt associated)
|
||||
* @retval the new state of adc flag status(SET or RESET).
|
||||
*/
|
||||
flag_status adc_flag_get(adc_type *adc_x, uint8_t adc_flag)
|
||||
{
|
||||
flag_status status = RESET;
|
||||
|
||||
if((adc_x->sts & adc_flag) == RESET)
|
||||
{
|
||||
status = RESET;
|
||||
}
|
||||
else
|
||||
{
|
||||
status = SET;
|
||||
}
|
||||
return status;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief get interrupt flag of the specified adc peripheral.
|
||||
* @param adc_x: select the adc peripheral.
|
||||
* this parameter can be one of the following values:
|
||||
* ADC1, ADC2, ADC3.
|
||||
* @param adc_flag: select the adc flag.
|
||||
* this parameter can be one of the following values:
|
||||
* - ADC_VMOR_FLAG
|
||||
* - ADC_CCE_FLAG
|
||||
* - ADC_PCCE_FLAG
|
||||
* @retval the new state of adc flag status(SET or RESET).
|
||||
*/
|
||||
flag_status adc_interrupt_flag_get(adc_type *adc_x, uint8_t adc_flag)
|
||||
{
|
||||
flag_status status = RESET;
|
||||
switch(adc_flag)
|
||||
{
|
||||
case ADC_VMOR_FLAG:
|
||||
if(adc_x->sts_bit.vmor && adc_x->ctrl1_bit.vmorien)
|
||||
{
|
||||
status = SET;
|
||||
}
|
||||
break;
|
||||
case ADC_CCE_FLAG:
|
||||
if(adc_x->sts_bit.cce && adc_x->ctrl1_bit.cceien)
|
||||
{
|
||||
status = SET;
|
||||
}
|
||||
break;
|
||||
case ADC_PCCE_FLAG:
|
||||
if(adc_x->sts_bit.pcce && adc_x->ctrl1_bit.pcceien)
|
||||
{
|
||||
status = SET;
|
||||
}
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
return status;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief clear flag of the specified adc peripheral.
|
||||
* @param adc_x: select the adc peripheral.
|
||||
* this parameter can be one of the following values:
|
||||
* ADC1, ADC2, ADC3.
|
||||
* @param adc_flag: select the adc flag.
|
||||
* this parameter can be any combination of the following values:
|
||||
* - ADC_VMOR_FLAG
|
||||
* - ADC_CCE_FLAG(also can clear by reading the adc_x->odt)
|
||||
* - ADC_PCCE_FLAG
|
||||
* - ADC_PCCS_FLAG
|
||||
* - ADC_OCCS_FLAG
|
||||
* @retval none
|
||||
*/
|
||||
void adc_flag_clear(adc_type *adc_x, uint32_t adc_flag)
|
||||
{
|
||||
adc_x->sts = ~adc_flag;
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
|
@ -0,0 +1,225 @@
|
|||
/**
|
||||
**************************************************************************
|
||||
* @file at32f403a_407_bpr.c
|
||||
* @brief contains all the functions for the bpr firmware library
|
||||
**************************************************************************
|
||||
*
|
||||
* Copyright (c) 2025, Artery Technology, All rights reserved.
|
||||
*
|
||||
* The software Board Support Package (BSP) that is made available to
|
||||
* download from Artery official website is the copyrighted work of Artery.
|
||||
* Artery authorizes customers to use, copy, and distribute the BSP
|
||||
* software and its related documentation for the purpose of design and
|
||||
* development in conjunction with Artery microcontrollers. Use of the
|
||||
* software is governed by this copyright notice and the following disclaimer.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
|
||||
* GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
|
||||
* TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
|
||||
* STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
|
||||
* INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
|
||||
*
|
||||
**************************************************************************
|
||||
*/
|
||||
|
||||
#include "at32f403a_407_conf.h"
|
||||
|
||||
/** @addtogroup AT32F403A_407_periph_driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup BPR
|
||||
* @brief BPR driver modules
|
||||
* @{
|
||||
*/
|
||||
|
||||
#ifdef BPR_MODULE_ENABLED
|
||||
|
||||
/** @defgroup BPR_private_functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief bpr reset by crm reset register
|
||||
* @param none
|
||||
* @retval none
|
||||
*/
|
||||
void bpr_reset(void)
|
||||
{
|
||||
crm_battery_powered_domain_reset(TRUE);
|
||||
crm_battery_powered_domain_reset(FALSE);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief bpr event flag get, for tamper event flag
|
||||
* @param flag: specifies the flag to check.
|
||||
* this parameter can be one of the following values:
|
||||
* - BPR_TAMPER_INTERRUPT_FLAG: tamper interrupt flag
|
||||
* - BPR_TAMPER_EVENT_FLAG: tamper event flag
|
||||
* @retval state of tamper event flag
|
||||
*/
|
||||
flag_status bpr_flag_get(uint32_t flag)
|
||||
{
|
||||
if(flag == BPR_TAMPER_INTERRUPT_FLAG)
|
||||
{
|
||||
return (flag_status)(BPR->ctrlsts_bit.tpif);
|
||||
}
|
||||
else
|
||||
{
|
||||
return (flag_status)(BPR->ctrlsts_bit.tpef);
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief bpr interrupt flag get
|
||||
* @param flag: specifies the flag to check.
|
||||
* this parameter can be one of the following values:
|
||||
* - BPR_TAMPER_INTERRUPT_FLAG: tamper interrupt flag
|
||||
* - BPR_TAMPER_EVENT_FLAG: tamper event flag
|
||||
* @retval state of tamper event flag
|
||||
*/
|
||||
flag_status bpr_interrupt_flag_get(uint32_t flag)
|
||||
{
|
||||
if(flag == BPR_TAMPER_INTERRUPT_FLAG)
|
||||
{
|
||||
return (flag_status)(BPR->ctrlsts_bit.tpif && BPR->ctrlsts_bit.tpien);
|
||||
}
|
||||
else
|
||||
{
|
||||
return (flag_status)(BPR->ctrlsts_bit.tpef && BPR->ctrlsts_bit.tpien);
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief clear bpr tamper flag
|
||||
* @param flag: specifies the flag to clear.
|
||||
* this parameter can be one of the following values:
|
||||
* - BPR_TAMPER_INTERRUPT_FLAG: tamper interrupt flag
|
||||
* - BPR_TAMPER_EVENT_FLAG: tamper event flag
|
||||
* @retval none
|
||||
*/
|
||||
void bpr_flag_clear(uint32_t flag)
|
||||
{
|
||||
if(flag == BPR_TAMPER_INTERRUPT_FLAG)
|
||||
{
|
||||
BPR->ctrlsts_bit.tpifclr = TRUE;
|
||||
}
|
||||
else
|
||||
{
|
||||
BPR->ctrlsts_bit.tpefclr = TRUE;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief enable or disable bpr tamper interrupt
|
||||
* @param new_state (TRUE or FALSE)
|
||||
* @retval none
|
||||
*/
|
||||
void bpr_interrupt_enable(confirm_state new_state)
|
||||
{
|
||||
BPR->ctrlsts_bit.tpien = new_state;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief read bpr bpr data
|
||||
* @param bpr_data
|
||||
* this parameter can be one of the following values:
|
||||
* - BPR_DATA1
|
||||
* - BPR_DATA2
|
||||
* ...
|
||||
* - BPR_DATA41
|
||||
* - BPR_DATA42
|
||||
* @retval none
|
||||
*/
|
||||
uint16_t bpr_data_read(bpr_data_type bpr_data)
|
||||
{
|
||||
return (*(__IO uint16_t *)(BPR_BASE + bpr_data));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief write bpr data
|
||||
* @param bpr_data
|
||||
* this parameter can be one of the following values:
|
||||
* - BPR_DATA1
|
||||
* - BPR_DATA2
|
||||
* ...
|
||||
* - BPR_DATA41
|
||||
* - BPR_DATA42
|
||||
* @param data_value (0x0000~0xFFFF)
|
||||
* @retval none
|
||||
*/
|
||||
void bpr_data_write(bpr_data_type bpr_data, uint16_t data_value)
|
||||
{
|
||||
(*(__IO uint32_t *)(BPR_BASE + bpr_data)) = data_value;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief select bpr rtc output
|
||||
* @param output_source
|
||||
* this parameter can be one of the following values:
|
||||
* - BPR_RTC_OUTPUT_NONE: output disable.
|
||||
* - BPR_RTC_OUTPUT_CLOCK_CAL_BEFORE: output clock before calibration.
|
||||
* - BPR_RTC_OUTPUT_ALARM: output alarm event with pluse mode.
|
||||
* - BPR_RTC_OUTPUT_SECOND: output second event with pluse mode.
|
||||
* - BPR_RTC_OUTPUT_CLOCK_CAL_AFTER: output clock after calibration.
|
||||
* - BPR_RTC_OUTPUT_ALARM_TOGGLE: output alarm event with toggle mode.
|
||||
* - BPR_RTC_OUTPUT_SECOND_TOGGLE: output second event with toggle mode.
|
||||
* @retval none
|
||||
*/
|
||||
void bpr_rtc_output_select(bpr_rtc_output_type output_source)
|
||||
{
|
||||
/* clear cco,asoe,asos,ccos,togen bits */
|
||||
BPR->rtccal &= (uint32_t)~0x0F80;
|
||||
|
||||
/* set output_source value */
|
||||
BPR->rtccal |= output_source;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief set rtc clock calibration value
|
||||
* @param calibration_value (0x00~0x7f)
|
||||
* @retval none
|
||||
*/
|
||||
void bpr_rtc_clock_calibration_value_set(uint8_t calibration_value)
|
||||
{
|
||||
/* set rtc clock calibration value */
|
||||
BPR->rtccal_bit.calval= calibration_value;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief enable or disable bpr tamper pin
|
||||
* @param new_state (TRUE or FALSE)
|
||||
* @retval none
|
||||
*/
|
||||
void bpr_tamper_pin_enable(confirm_state new_state)
|
||||
{
|
||||
BPR->ctrl_bit.tpen = new_state;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief set bpr tamper pin active level
|
||||
* @param active_level
|
||||
* this parameter can be one of the following values:
|
||||
* - BPR_TAMPER_PIN_ACTIVE_HIGH: tamper pin input active level is high.
|
||||
* - BPR_TAMPER_PIN_ACTIVE_LOW: tamper pin input active level is low.
|
||||
* @retval none
|
||||
*/
|
||||
void bpr_tamper_pin_active_level_set(bpr_tamper_pin_active_level_type active_level)
|
||||
{
|
||||
BPR->ctrl_bit.tpp = active_level;
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
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Reference in New Issue