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Fix IAR Target to Cortex-M4 core so builds work without ArteryTek Device pack. 

Switch OGCoreOrChip to core mode and set J-Link flash device to Cortex-M4 to avoid CMSIS Unknown target when the chip is not selected in the IDE.

Co-authored-by: Cursor <cursoragent@cursor.com>
This commit is contained in:
yuquanjun 2026-08-26 20:50:57 +08:00
parent 9ee3b562f6
commit f754676aa1
3 changed files with 8 additions and 8 deletions
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2
AT32F403ARCT7_BOOT/project/IAR_V7.4/AT32F403ARCT7_BOOT.ewp
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@ -55,7 +55,7 @@
</option>
<option>
<name>OGCoreOrChip</name>
<state>1</state>
<state>0</state>
</option>
<option>
<name>GRuntimeLibSelect</name>

4
project/IAR_V7.4/YNGJ-GT1-M.ewp
View File

@ -55,7 +55,7 @@
</option>
<option>
<name>OGCoreOrChip</name>
<state>1</state>
<state>0</state>
</option>
<option>
<name>GRuntimeLibSelect</name>
@ -1039,7 +1039,7 @@
</option>
<option>
<name>OGCoreOrChip</name>
<state>1</state>
<state>0</state>
</option>
<option>
<name>GRuntimeLibSelect</name>

10
project/IAR_V7.4/settings/YNGJ-GT1-M_YNGJ-GT1-M.jlink
View File

@ -7,13 +7,13 @@ BPDuringExecution = 0
CFISize = 0x00
CFIAddr = 0x00
[CPU]
MonModeVTableAddr = 0xFFFFFFFF
MonModeDebug = 0
MaxNumAPs = 0
LowPowerHandlingMode = 0
OverrideMemMap = 0
AllowSimulation = 1
ScriptFile=""
MonModeVTableAddr = 0xFFFFFFFF
MonModeDebug = 0
MaxNumAPs = 0
[FLASH]
CacheExcludeSize = 0x00
CacheExcludeAddr = 0x00
@ -22,8 +22,8 @@ SkipProgOnCRCMatch = 1
VerifyDownload = 1
AllowCaching = 1
EnableFlashDL = 2
Override = 0
Device="ARM7"
Override = 1
Device="Cortex-M4"
[GENERAL]
WorkRAMSize = 0x00
WorkRAMAddr = 0x00