ASoC: codecs: rk_dsm: clean up code

Delete unused definition and modify the error register definition.

Signed-off-by: Jason Zhu <jason.zhu@rock-chips.com>
Change-Id: I255c17049bc28faf108dbca8ec0337d3ccb11555
This commit is contained in:
Jason Zhu 2023-03-02 10:36:22 +08:00 committed by Tao Huang
parent df50198904
commit 205c5a8113
2 changed files with 9 additions and 22 deletions

View File

@ -239,7 +239,7 @@ static int rk_dsm_set_clk(struct rk_dsm_priv *rd,
DSM_DACSCLKRXINT_DIV_SCKRXDIV(div_bclk)); DSM_DACSCLKRXINT_DIV_SCKRXDIV(div_bclk));
regmap_update_bits(rd->regmap, I2S_CKR0, regmap_update_bits(rd->regmap, I2S_CKR0,
DSM_I2S_CKR0_RSD_MASK, DSM_I2S_CKR0_RSD_MASK,
DSM_I2S_CKR0_RSD(64)); DSM_I2S_CKR0_RSD_64);
} }
return 0; return 0;
@ -258,29 +258,24 @@ static int rk_dsm_set_dai_fmt(struct snd_soc_dai *dai,
DSM_I2S_CKR1_MSS_MASTER); DSM_I2S_CKR1_MSS_MASTER);
mask = DSM_I2S_CKR1_CKP_MASK | mask = DSM_I2S_CKR1_CKP_MASK |
DSM_I2S_CKR1_RLP_MASK | DSM_I2S_CKR1_RLP_MASK;
DSM_I2S_CKR1_TLP_MASK;
switch (fmt & SND_SOC_DAIFMT_INV_MASK) { switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
case SND_SOC_DAIFMT_NB_NF: case SND_SOC_DAIFMT_NB_NF:
val = DSM_I2S_CKR1_CKP_NORMAL | val = DSM_I2S_CKR1_CKP_NORMAL |
DSM_I2S_CKR1_RLP_NORMAL | DSM_I2S_CKR1_RLP_NORMAL;
DSM_I2S_CKR1_TLP_NORMAL;
break; break;
case SND_SOC_DAIFMT_IB_IF: case SND_SOC_DAIFMT_IB_IF:
val = DSM_I2S_CKR1_CKP_INVERTED | val = DSM_I2S_CKR1_CKP_INVERTED |
DSM_I2S_CKR1_RLP_INVERTED | DSM_I2S_CKR1_RLP_INVERTED;
DSM_I2S_CKR1_TLP_INVERTED;
break; break;
case SND_SOC_DAIFMT_IB_NF: case SND_SOC_DAIFMT_IB_NF:
val = DSM_I2S_CKR1_CKP_INVERTED | val = DSM_I2S_CKR1_CKP_INVERTED |
DSM_I2S_CKR1_RLP_NORMAL | DSM_I2S_CKR1_RLP_NORMAL;
DSM_I2S_CKR1_TLP_NORMAL;
break; break;
case SND_SOC_DAIFMT_NB_IF: case SND_SOC_DAIFMT_NB_IF:
val = DSM_I2S_CKR1_CKP_NORMAL | val = DSM_I2S_CKR1_CKP_NORMAL |
DSM_I2S_CKR1_RLP_INVERTED | DSM_I2S_CKR1_RLP_INVERTED;
DSM_I2S_CKR1_TLP_INVERTED;
break; break;
default: default:
return -EINVAL; return -EINVAL;

View File

@ -144,14 +144,11 @@
#define DSM_I2S_RXCR1_RCSR_MASK GENMASK(7, 6) #define DSM_I2S_RXCR1_RCSR_MASK GENMASK(7, 6)
#define DSM_I2S_RXCR1_RCSR_2CH (0x0 << 6) #define DSM_I2S_RXCR1_RCSR_2CH (0x0 << 6)
/* I2S_CKR0 */ /* I2S_CKR0 */
#define DSM_I2S_CKR0_TSD_MASK GENMASK(1, 0)
#define DSM_I2S_CKR0_TSD(x) ((x) << 0)
#define DSM_I2S_CKR0_RSD_MASK GENMASK(3, 2) #define DSM_I2S_CKR0_RSD_MASK GENMASK(3, 2)
#define DSM_I2S_CKR0_RSD(x) ((x) << 2) #define DSM_I2S_CKR0_RSD_64 (0 << 2)
#define DSM_I2S_CKR0_RSD_128 (1 << 2)
#define DSM_I2S_CKR0_RSD_256 (2 << 2)
/* I2S_CKR1 */ /* I2S_CKR1 */
#define DSM_I2S_CKR1_TLP_MASK BIT(0)
#define DSM_I2S_CKR1_TLP_INVERTED BIT(0)
#define DSM_I2S_CKR1_TLP_NORMAL 0
#define DSM_I2S_CKR1_RLP_MASK BIT(1) #define DSM_I2S_CKR1_RLP_MASK BIT(1)
#define DSM_I2S_CKR1_RLP_INVERTED BIT(1) #define DSM_I2S_CKR1_RLP_INVERTED BIT(1)
#define DSM_I2S_CKR1_RLP_NORMAL 0 #define DSM_I2S_CKR1_RLP_NORMAL 0
@ -161,15 +158,10 @@
#define DSM_I2S_CKR1_MSS_MASK BIT(3) #define DSM_I2S_CKR1_MSS_MASK BIT(3)
#define DSM_I2S_CKR1_MSS_MASTER 0 #define DSM_I2S_CKR1_MSS_MASTER 0
/* I2S_XFER */ /* I2S_XFER */
#define DSM_I2S_XFER_TXS_MASK BIT(0)
#define DSM_I2S_XFER_TXS_START BIT(0)
#define DSM_I2S_XFER_TXS_STOP 0
#define DSM_I2S_XFER_RXS_MASK BIT(1) #define DSM_I2S_XFER_RXS_MASK BIT(1)
#define DSM_I2S_XFER_RXS_START BIT(1) #define DSM_I2S_XFER_RXS_START BIT(1)
#define DSM_I2S_XFER_RXS_STOP 0 #define DSM_I2S_XFER_RXS_STOP 0
/* I2S_CLR */ /* I2S_CLR */
#define DSM_I2S_CLR_TXC_MASK BIT(0)
#define DSM_I2S_CLR_TXC_CLR BIT(0)
#define DSM_I2S_CLR_RXC_MASK BIT(1) #define DSM_I2S_CLR_RXC_MASK BIT(1)
#define DSM_I2S_CLR_RXC_CLR BIT(1) #define DSM_I2S_CLR_RXC_CLR BIT(1)