arm64: dts: rockchip: add rk1808 ddr relate node
Change-Id: I06c40f6c5e2832f79626c3438bed74fbb0551c86 Signed-off-by: YouMin Chen <cym@rock-chips.com>
This commit is contained in:
YouMin Chen
parent
02747fd169
commit
30362bd199
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@ -0,0 +1,302 @@
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// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* Copyright (c) 2018 Fuzhou Rockchip Electronics Co., Ltd
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*/
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#include <dt-bindings/clock/rockchip-ddr.h>
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#include <dt-bindings/memory/rk1808-dram.h>
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/ {
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ddr_timing: ddr_timing {
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compatible = "rockchip,ddr-timing";
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ddr2_speed_bin = <DDR2_DEFAULT>;
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ddr3_speed_bin = <DDR3_DEFAULT>;
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ddr4_speed_bin = <DDR4_DEFAULT>;
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pd_idle = <0>;
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sr_idle = <0>;
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sr_mc_gate_idle = <0>;
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srpd_lite_idle = <0>;
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standby_idle = <0>;
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auto_pd_dis_freq = <1066>;
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auto_sr_dis_freq = <800>;
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ddr2_dll_dis_freq = <300>;
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ddr3_dll_dis_freq = <300>;
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ddr4_dll_dis_freq = <625>;
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phy_dll_dis_freq = <400>;
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ddr2_odt_dis_freq = <100>;
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phy_ddr2_odt_dis_freq = <100>;
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ddr2_drv = <DDR2_DS_REDUCE>;
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ddr2_odt = <DDR2_ODT_150ohm>;
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phy_ddr2_ca_drv = <PHY_DDR3_RON_34ohm>;
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phy_ddr2_ck_drv = <PHY_DDR3_RON_43ohm>;
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phy_ddr2_dq_drv = <PHY_DDR3_RON_34ohm>;
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phy_ddr2_odt = <PHY_DDR3_RTT_213ohm>;
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ddr3_odt_dis_freq = <400>;
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phy_ddr3_odt_dis_freq = <400>;
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ddr3_drv = <DDR3_DS_40ohm>;
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ddr3_odt = <DDR3_ODT_120ohm>;
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phy_ddr3_ca_drv = <PHY_DDR3_RON_34ohm>;
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phy_ddr3_ck_drv = <PHY_DDR3_RON_43ohm>;
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phy_ddr3_dq_drv = <PHY_DDR3_RON_34ohm>;
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phy_ddr3_odt = <PHY_DDR3_RTT_213ohm>;
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phy_lpddr2_odt_dis_freq = <666>;
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lpddr2_drv = <LP2_DS_40ohm>;
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phy_lpddr2_ca_drv = <PHY_DDR4_LPDDR2_3_RON_34ohm>;
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phy_lpddr2_ck_drv = <PHY_DDR4_LPDDR2_3_RON_42ohm>;
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phy_lpddr2_dq_drv = <PHY_DDR4_LPDDR2_3_RON_34ohm>;
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phy_lpddr2_odt = <PHY_DDR4_LPDDR2_3_RTT_DISABLE>;
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lpddr3_odt_dis_freq = <400>;
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phy_lpddr3_odt_dis_freq = <400>;
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lpddr3_drv = <LP3_DS_40ohm>;
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lpddr3_odt = <LP3_ODT_240ohm>;
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phy_lpddr3_ca_drv = <PHY_DDR4_LPDDR2_3_RON_34ohm>;
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phy_lpddr3_ck_drv = <PHY_DDR4_LPDDR2_3_RON_42ohm>;
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phy_lpddr3_dq_drv = <PHY_DDR4_LPDDR2_3_RON_34ohm>;
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phy_lpddr3_odt = <PHY_DDR4_LPDDR2_3_RTT_229ohm>;
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lpddr4_odt_dis_freq = <800>;
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phy_lpddr4_odt_dis_freq = <800>;
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lpddr4_drv = <LP4_PDDS_60ohm>;
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lpddr4_dq_odt = <LP4_DQ_ODT_40ohm>;
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lpddr4_ca_odt = <LP4_CA_ODT_40ohm>;
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phy_lpddr4_ca_drv = <PHY_DDR4_LPDDR2_3_RON_42ohm>;
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phy_lpddr4_ck_cs_drv = <PHY_DDR4_LPDDR2_3_RON_75ohm>;
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phy_lpddr4_dq_drv = <PHY_DDR4_LPDDR2_3_RON_75ohm>;
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phy_lpddr4_odt = <PHY_DDR4_LPDDR2_3_RTT_54ohm>;
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ddr4_odt_dis_freq = <666>;
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phy_ddr4_odt_dis_freq = <666>;
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ddr4_drv = <DDR4_DS_34ohm>;
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ddr4_odt = <DDR4_RTT_NOM_240ohm>;
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phy_ddr4_ca_drv = <PHY_DDR4_LPDDR2_3_RON_34ohm>;
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phy_ddr4_ck_drv = <PHY_DDR4_LPDDR2_3_RON_42ohm>;
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phy_ddr4_dq_drv = <PHY_DDR4_LPDDR2_3_RON_34ohm>;
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phy_ddr4_odt = <PHY_DDR4_LPDDR2_3_RTT_229ohm>;
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/*
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* CA de-skew, one step is 15ps, range 0-31
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* DDR3 CA define is different from others(DDR4/LPDDR2/LPDDR3).
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*/
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a0_ddr3a9_de-skew = <7>;
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a1_ddr3a14_de-skew = <7>;
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a2_ddr3a13_de-skew = <7>;
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a3_ddr3a11_de-skew = <7>;
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a4_ddr3a2_de-skew = <7>;
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a5_ddr3a4_de-skew = <7>;
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a6_ddr3a3_de-skew = <7>;
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a7_ddr3a6_de-skew = <7>;
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a8_ddr3a5_de-skew = <7>;
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a9_ddr3a1_de-skew = <7>;
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a10_ddr3a0_de-skew = <7>;
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a11_ddr3a7_de-skew = <7>;
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a12_ddr3casb_de-skew = <7>;
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a13_ddr3a8_de-skew = <7>;
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a14_ddr3odt0_de-skew = <7>;
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a15_ddr3ba1_de-skew = <7>;
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a16_ddr3rasb_de-skew = <7>;
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a17_ddr3null_de-skew = <7>;
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ba0_ddr3ba2_de-skew = <7>;
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ba1_ddr3a12_de-skew = <7>;
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bg0_ddr3ba0_de-skew = <7>;
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bg1_ddr3web_de-skew = <7>;
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cke_ddr3cke_de-skew = <7>;
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ck_ddr3ck_de-skew = <7>;
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ckb_ddr3ckb_de-skew = <7>;
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csb0_ddr3a10_de-skew = <7>;
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odt0_ddr3a15_de-skew = <7>;
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resetn_ddr3resetn_de-skew = <7>;
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actn_ddr3csb0_de-skew = <7>;
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csb1_ddr3csb1_de-skew = <7>;
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odt1_ddr3odt1_de-skew = <7>;
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/* DATA de-skew, one step is 15ps, range 0-31 */
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/* cs0_skew_a */
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cs0_dm0_rx_de-skew = <7>;
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cs0_dm0_tx_de-skew = <7>;
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cs0_dq0_rx_de-skew = <7>;
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cs0_dq0_tx_de-skew = <7>;
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cs0_dq1_rx_de-skew = <7>;
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cs0_dq1_tx_de-skew = <7>;
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cs0_dq2_rx_de-skew = <7>;
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cs0_dq2_tx_de-skew = <7>;
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cs0_dq3_rx_de-skew = <7>;
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cs0_dq3_tx_de-skew = <7>;
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cs0_dq4_rx_de-skew = <7>;
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cs0_dq4_tx_de-skew = <7>;
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cs0_dq5_rx_de-skew = <7>;
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cs0_dq5_tx_de-skew = <7>;
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cs0_dq6_rx_de-skew = <7>;
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cs0_dq6_tx_de-skew = <7>;
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cs0_dq7_rx_de-skew = <7>;
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cs0_dq7_tx_de-skew = <7>;
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cs0_dqs0p_rx_de-skew = <14>;
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cs0_dqs0p_tx_de-skew = <9>;
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cs0_dqs0n_tx_de-skew = <9>;
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cs0_dm1_rx_de-skew = <7>;
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cs0_dm1_tx_de-skew = <7>;
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cs0_dq8_rx_de-skew = <7>;
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cs0_dq8_tx_de-skew = <7>;
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cs0_dq9_rx_de-skew = <7>;
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cs0_dq9_tx_de-skew = <7>;
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cs0_dq10_rx_de-skew = <7>;
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cs0_dq10_tx_de-skew = <7>;
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cs0_dq11_rx_de-skew = <7>;
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cs0_dq11_tx_de-skew = <7>;
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cs0_dq12_rx_de-skew = <7>;
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cs0_dq12_tx_de-skew = <7>;
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cs0_dq13_rx_de-skew = <7>;
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cs0_dq13_tx_de-skew = <7>;
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cs0_dq14_rx_de-skew = <7>;
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cs0_dq14_tx_de-skew = <7>;
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cs0_dq15_rx_de-skew = <7>;
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cs0_dq15_tx_de-skew = <7>;
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cs0_dqs1p_rx_de-skew = <14>;
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cs0_dqs1p_tx_de-skew = <9>;
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cs0_dqs1n_tx_de-skew = <9>;
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cs0_dqs0n_rx_de-skew = <14>;
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cs0_dqs1n_rx_de-skew = <14>;
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/* cs0_skew_b */
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cs0_dm2_rx_de-skew = <7>;
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cs0_dm2_tx_de-skew = <7>;
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cs0_dq16_rx_de-skew = <7>;
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cs0_dq16_tx_de-skew = <7>;
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cs0_dq17_rx_de-skew = <7>;
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cs0_dq17_tx_de-skew = <7>;
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cs0_dq18_rx_de-skew = <7>;
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cs0_dq18_tx_de-skew = <7>;
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cs0_dq19_rx_de-skew = <7>;
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cs0_dq19_tx_de-skew = <7>;
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cs0_dq20_rx_de-skew = <7>;
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cs0_dq20_tx_de-skew = <7>;
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cs0_dq21_rx_de-skew = <7>;
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cs0_dq21_tx_de-skew = <7>;
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cs0_dq22_rx_de-skew = <7>;
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cs0_dq22_tx_de-skew = <7>;
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cs0_dq23_rx_de-skew = <7>;
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cs0_dq23_tx_de-skew = <7>;
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cs0_dqs2p_rx_de-skew = <14>;
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cs0_dqs2p_tx_de-skew = <9>;
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cs0_dqs2n_tx_de-skew = <9>;
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cs0_dm3_rx_de-skew = <7>;
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cs0_dm3_tx_de-skew = <7>;
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cs0_dq24_rx_de-skew = <7>;
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cs0_dq24_tx_de-skew = <7>;
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cs0_dq25_rx_de-skew = <7>;
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cs0_dq25_tx_de-skew = <7>;
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cs0_dq26_rx_de-skew = <7>;
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cs0_dq26_tx_de-skew = <7>;
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cs0_dq27_rx_de-skew = <7>;
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cs0_dq27_tx_de-skew = <7>;
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cs0_dq28_rx_de-skew = <7>;
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cs0_dq28_tx_de-skew = <7>;
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cs0_dq29_rx_de-skew = <7>;
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cs0_dq29_tx_de-skew = <7>;
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cs0_dq30_rx_de-skew = <7>;
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cs0_dq30_tx_de-skew = <7>;
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cs0_dq31_rx_de-skew = <7>;
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cs0_dq31_tx_de-skew = <7>;
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cs0_dqs3p_rx_de-skew = <14>;
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cs0_dqs3p_tx_de-skew = <9>;
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cs0_dqs3n_tx_de-skew = <9>;
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cs0_dqs2n_rx_de-skew = <14>;
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cs0_dqs3n_rx_de-skew = <14>;
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/* cs1_skew_a */
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cs1_dm0_rx_de-skew = <7>;
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cs1_dm0_tx_de-skew = <7>;
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cs1_dq0_rx_de-skew = <7>;
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cs1_dq0_tx_de-skew = <7>;
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cs1_dq1_rx_de-skew = <7>;
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cs1_dq1_tx_de-skew = <7>;
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cs1_dq2_rx_de-skew = <7>;
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cs1_dq2_tx_de-skew = <7>;
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cs1_dq3_rx_de-skew = <7>;
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cs1_dq3_tx_de-skew = <7>;
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cs1_dq4_rx_de-skew = <7>;
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cs1_dq4_tx_de-skew = <7>;
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cs1_dq5_rx_de-skew = <7>;
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cs1_dq5_tx_de-skew = <7>;
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cs1_dq6_rx_de-skew = <7>;
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cs1_dq6_tx_de-skew = <7>;
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cs1_dq7_rx_de-skew = <7>;
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cs1_dq7_tx_de-skew = <7>;
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cs1_dqs0p_rx_de-skew = <14>;
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cs1_dqs0p_tx_de-skew = <9>;
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cs1_dqs0n_tx_de-skew = <9>;
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cs1_dm1_rx_de-skew = <7>;
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cs1_dm1_tx_de-skew = <7>;
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cs1_dq8_rx_de-skew = <7>;
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cs1_dq8_tx_de-skew = <7>;
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cs1_dq9_rx_de-skew = <7>;
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cs1_dq9_tx_de-skew = <7>;
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cs1_dq10_rx_de-skew = <7>;
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cs1_dq10_tx_de-skew = <7>;
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cs1_dq11_rx_de-skew = <7>;
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cs1_dq11_tx_de-skew = <7>;
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cs1_dq12_rx_de-skew = <7>;
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cs1_dq12_tx_de-skew = <7>;
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cs1_dq13_rx_de-skew = <7>;
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cs1_dq13_tx_de-skew = <7>;
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cs1_dq14_rx_de-skew = <7>;
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cs1_dq14_tx_de-skew = <7>;
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cs1_dq15_rx_de-skew = <7>;
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cs1_dq15_tx_de-skew = <7>;
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cs1_dqs1p_rx_de-skew = <14>;
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cs1_dqs1p_tx_de-skew = <9>;
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cs1_dqs1n_tx_de-skew = <9>;
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cs1_dqs0n_rx_de-skew = <14>;
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cs1_dqs1n_rx_de-skew = <14>;
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/* cs1_skew_b */
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cs1_dm2_rx_de-skew = <7>;
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cs1_dm2_tx_de-skew = <7>;
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cs1_dq16_rx_de-skew = <7>;
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cs1_dq16_tx_de-skew = <7>;
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cs1_dq17_rx_de-skew = <7>;
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cs1_dq17_tx_de-skew = <7>;
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cs1_dq18_rx_de-skew = <7>;
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cs1_dq18_tx_de-skew = <7>;
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cs1_dq19_rx_de-skew = <7>;
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cs1_dq19_tx_de-skew = <7>;
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cs1_dq20_rx_de-skew = <7>;
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cs1_dq20_tx_de-skew = <7>;
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cs1_dq21_rx_de-skew = <7>;
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cs1_dq21_tx_de-skew = <7>;
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cs1_dq22_rx_de-skew = <7>;
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cs1_dq22_tx_de-skew = <7>;
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cs1_dq23_rx_de-skew = <7>;
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cs1_dq23_tx_de-skew = <7>;
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cs1_dqs2p_rx_de-skew = <14>;
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cs1_dqs2p_tx_de-skew = <9>;
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cs1_dqs2n_tx_de-skew = <9>;
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cs1_dm3_rx_de-skew = <7>;
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cs1_dm3_tx_de-skew = <7>;
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cs1_dq24_rx_de-skew = <7>;
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cs1_dq24_tx_de-skew = <7>;
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cs1_dq25_rx_de-skew = <7>;
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cs1_dq25_tx_de-skew = <7>;
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cs1_dq26_rx_de-skew = <7>;
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cs1_dq26_tx_de-skew = <7>;
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cs1_dq27_rx_de-skew = <7>;
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cs1_dq27_tx_de-skew = <7>;
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cs1_dq28_rx_de-skew = <7>;
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cs1_dq28_tx_de-skew = <7>;
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cs1_dq29_rx_de-skew = <7>;
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cs1_dq29_tx_de-skew = <7>;
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cs1_dq30_rx_de-skew = <7>;
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cs1_dq30_tx_de-skew = <7>;
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cs1_dq31_rx_de-skew = <7>;
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cs1_dq31_tx_de-skew = <7>;
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cs1_dqs3p_rx_de-skew = <14>;
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cs1_dqs3p_tx_de-skew = <9>;
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cs1_dqs3n_tx_de-skew = <9>;
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cs1_dqs2n_rx_de-skew = <14>;
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cs1_dqs3n_rx_de-skew = <14>;
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};
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};
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@ -8,7 +8,9 @@
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#include <dt-bindings/power/rk1808-power.h>
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#include <dt-bindings/phy/phy.h>
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#include <dt-bindings/soc/rockchip,boot-mode.h>
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#include <dt-bindings/soc/rockchip-system-status.h>
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#include <dt-bindings/thermal/thermal.h>
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#include "rk1808-dram-default-timing.dtsi"
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/ {
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compatible = "rockchip,rk1808";
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@ -1041,6 +1043,11 @@
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status = "disabled";
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};
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dcf: dcf@ff640000 {
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compatible = "syscon";
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reg = <0x0 0xff640000 0x0 0x1000>;
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};
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wdt: watchdog@ff720000 {
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compatible = "snps,dw-wdt";
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reg = <0x0 0xff720000 0x0 0x100>;
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@ -1126,6 +1133,74 @@
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status = "disabled";
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};
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dfi: dfi@ff9c0000 {
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reg = <0x00 0xff9c0000 0x00 0x400>;
|
||||
compatible = "rockchip,rk1808-dfi";
|
||||
rockchip,pmugrf = <&pmugrf>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
dmc: dmc {
|
||||
compatible = "rockchip,rk1808-dmc";
|
||||
dcf_reg = <&dcf>;
|
||||
interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "complete_irq";
|
||||
devfreq-events = <&dfi>;
|
||||
clocks = <&cru SCLK_DDRCLK>;
|
||||
clock-names = "dmc_clk";
|
||||
operating-points-v2 = <&dmc_opp_table>;
|
||||
ddr_timing = <&ddr_timing>;
|
||||
upthreshold = <40>;
|
||||
downdifferential = <20>;
|
||||
system-status-freq = <
|
||||
/*system status freq(KHz)*/
|
||||
SYS_STATUS_NORMAL 924000
|
||||
SYS_STATUS_REBOOT 450000
|
||||
SYS_STATUS_SUSPEND 328000
|
||||
SYS_STATUS_VIDEO_1080P 924000
|
||||
SYS_STATUS_BOOST 924000
|
||||
SYS_STATUS_ISP 924000
|
||||
SYS_STATUS_PERFORMANCE 924000
|
||||
>;
|
||||
auto-min-freq = <328000>;
|
||||
auto-freq-en = <0>;
|
||||
#cooling-cells = <2>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
dmc_opp_table: dmc-opp-table {
|
||||
compatible = "operating-points-v2";
|
||||
|
||||
opp-194000000 {
|
||||
opp-hz = /bits/ 64 <194000000>;
|
||||
opp-microvolt = <800000>;
|
||||
};
|
||||
opp-328000000 {
|
||||
opp-hz = /bits/ 64 <328000000>;
|
||||
opp-microvolt = <800000>;
|
||||
};
|
||||
opp-450000000 {
|
||||
opp-hz = /bits/ 64 <450000000>;
|
||||
opp-microvolt = <800000>;
|
||||
};
|
||||
opp-528000000 {
|
||||
opp-hz = /bits/ 64 <528000000>;
|
||||
opp-microvolt = <800000>;
|
||||
};
|
||||
opp-666000000 {
|
||||
opp-hz = /bits/ 64 <666000000>;
|
||||
opp-microvolt = <800000>;
|
||||
};
|
||||
opp-786000000 {
|
||||
opp-hz = /bits/ 64 <786000000>;
|
||||
opp-microvolt = <800000>;
|
||||
};
|
||||
opp-924000000 {
|
||||
opp-hz = /bits/ 64 <924000000>;
|
||||
opp-microvolt = <800000>;
|
||||
};
|
||||
};
|
||||
|
||||
rk_rga: rk_rga@ffaf0000 {
|
||||
compatible = "rockchip,rga2";
|
||||
dev_mode = <0>;
|
||||
|
|
|
|||
Loading…
Reference in New Issue