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Merge linux-5.10-gen-rkr6

This commit is contained in:
baiywt 2023-10-25 19:17:49 +08:00
parent 66518fdba8
commit 38b0a66a10
655 changed files with 92975 additions and 6992 deletions
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80
Documentation/devicetree/bindings/gpio/novo,nca9539-gpio.yaml Normal file
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@ -0,0 +1,80 @@
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/gpio/novo,nca9539-gpio.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Novosense I2C GPIO controller
maintainers:
- Cody Xie <cody.xie@rock-chips.com>
description: |
This controller is A GPIO expander with I2C interface and one interrupt pin.
properties:
compatible:
const: novo,nca9539-gpio
reg:
items:
- description: the I2C address containing the GPIO controller registers.
gpio-controller: true
'#gpio-cells':
const: 2
ngpios:
minimum: 0
maximum: 32
interrupt-controller: true
'#interrupt-cells':
const: 2
interrupts:
maxItems: 1
vdd-supply:
- description: the regulator for the VDD supplier.
required:
- compatible
- reg
- "#gpio-cells"
- gpio-controller
- vdd-supply
additionalProperties: false
dependencies:
interrupt-controller: [ interrupts ]
examples:
- |
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
/ {
nca9539_vdd: nca9539-vdd {
compatible = "regulator-fixed";
regulator-name = "nca9539_vdd";
enable-active-high;
regulator-boot-on;
regulator-always-on;
};
};
nca9539_gpio: gpio@74 {
compatible = "novo,nca9539-gpio";
reg = <0x74>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
vdd-supply = <&nca9539_vdd>;
};
...

564
Documentation/devicetree/bindings/mfd/rkx110_x120.yaml Normal file
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@ -0,0 +1,564 @@
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/rockchip/rockchip-vop.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Rockchip SerDes MFD driver
description:
Rockchip SerDes MFD driver is a pair chip for long distance transmitting
display image.
maintainers:
- Zhang Yubing <yubing.zhang@rock-chips.com>
properties:
compatible:
enum:
- "rockchip,rkx110", "rockchip,rkx120"
interrupts:
maxItems: 1
description:
The Serdes interrupt is shared by RKX110/RKX120.
clocks:
items:
- description:
clock-names:
items:
- const:
resets:
maxItems: 1
reset-names:
items:
- const:
route:
type: object
description:
A route node descriptor serdes topology
required:
- compatible
- reg
- interrupts
- clocks
- clock-names
- resets
- reset-names
- route
additionalProperties: false
# example0:
# 1 video source input, 1 channel, 1 lane, 1 remote, 1 video output:
# disp in can select follow interface:
# dsi0_rx, dsi1_rx, lvds0_rx, lvds1_rx, dual-lvds_rx, rgb_rx
# disp out can select follow interface:
# dsi_tx, lvds0_tx, lvds1_tx, dual-lvds_tx, rgb_tx
+-------+ +---------+ +---------+ +--------+
| | disp in | | cable0 | | disp out| |
| soc |--------->| RK110 +----------->| RK120 +-------->| screen |
| | | | | | | |
+-------+ +---------+ +---------+ +--------+
examples0:
- |
#include <dt-bindings/mfd/rockchip-serdes.h>
&i2c1 {
status = "okay";
rkx110_x120: rkx110_x120@55 {
compatible = "rockchip,rkx110";
enable-gpios = <&gpio0 RK_PD3 GPIO_ACTIVE_HIGH>;
reset-gpios = <&gpio0 RK_PB7 GPIO_ACTIVE_LOW>;
status = "okay";
remote0-addr = <0x35>;
panel {
compatible = "rockchip,serdes_panel";
status = "okay";
local-port0 = <RK_SERDES_LVDS_RX0>;
remote0-port0 = <RK_SERDES_LVDS_TX0>;
backlight0 = <&backlight>;
power0-supply = <&vcc3v3_lcd_n>;
reset0-gpios = <&gpio0 RK_PC4 GPIO_ACTIVE_LOW>;
reset0-delay-ms = <20>;
enable0-delay-ms = <20>;
prepare0-delay-ms = <20>;
unprepare0-delay-ms = <20>;
disable0-delay-ms = <20>;
bus-format0 = <MEDIA_BUS_FMT_RGB888_1X7X4_SPWG>;
display-timings {
native-mode = <&timing0>;
timing0: timing0 {
clock-frequency = <27000000>;
hactive = <1024>;
vactive = <600>;
hback-porch = <160>;
hfront-porch = <160>;
vback-porch = <20>;
vfront-porch = <15>;
hsync-len = <6>;
vsync-len = <5>;
hsync-active = <0>;
vsync-active = <0>;
de-active = <0>;
pixelclk-active = <0>;
};
};
};
};
};
# example1:
# 1 video source input, 2 channel, 1 lane, 1 remote, 1 video output:
# disp in can select follow interface:
# dsi0_rx, dsi1_rx, lvds0_rx, lvds1_rx, dual-lvds_rx, rgb_rx
# disp out can select follow interface:
# dsi_tx, lvds0_tx, lvds1_tx, dual-lvds_tx, rgb_tx
+-------+ +---------+ cable0 +---------+ +--------+
| | disp in | +----------->| | disp out| |
| soc |--------->| RK110 | cable1 | RK120 +-------->| screen |
| | | +----------->| | | |
+-------+ +---------+ +---------+ +--------+
examples1:
- |
#include <dt-bindings/mfd/rockchip-serdes.h>
&i2c1 {
status = "okay";
rkx110_x120: rkx110_x120@55 {
compatible = "rockchip,rkx110";
enable-gpios = <&gpio0 RK_PD3 GPIO_ACTIVE_HIGH>;
reset-gpios = <&gpio0 RK_PB7 GPIO_ACTIVE_LOW>;
status = "okay";
remote0-addr = <0x35>;
panel {
compatible = "rockchip,serdes_panel";
status = "okay";
local-port0 = <RK_SERDES_LVDS_RX0>;
remote0-port0 = <RK_SERDES_LVDS_TX0>;
num-lanes = <2>;
backlight0 = <&backlight>;
power0-supply = <&vcc3v3_lcd_n>;
reset0-gpios = <&gpio0 RK_PC4 GPIO_ACTIVE_LOW>;
reset0-delay-ms = <20>;
enable0-delay-ms = <20>;
prepare0-delay-ms = <20>;
unprepare0-delay-ms = <20>;
disable0-delay-ms = <20>;
bus-format0 = <MEDIA_BUS_FMT_RGB888_1X7X4_SPWG>;
display-timings {
native-mode = <&timing0>;
timing0: timing0 {
clock-frequency = <27000000>;
hactive = <1024>;
vactive = <600>;
hback-porch = <160>;
hfront-porch = <160>;
vback-porch = <20>;
vfront-porch = <15>;
hsync-len = <6>;
vsync-len = <5>;
hsync-active = <0>;
vsync-active = <0>;
de-active = <0>;
pixelclk-active = <0>;
};
};
};
};
};
# example2:
# 1 video source input, 2 channel, 2 lane, 2 remote, 2 video output:
# disp in can select follow interface:
# dsi0_rx, dsi1_rx, lvds0_rx, lvds1_rx, dual-lvds_rx, rgb_rx
# disp out can select follow interface:
# dsi_tx, lvds0_tx, lvds1_tx, dual-lvds_tx, rgb_tx
+---------+ +--------+
cable0 | |disp0 out| |
+------->| RK120 +-------->| screen |
| | | | |
+-------+ +---------+ | +---------+ +--------+
| | disp in | +---+
| soc |--------->| RK110 |
| | | +---+
+-------+ +---------+ | +---------+ +--------+
|cable1 | |disp1 out| |
+------->| RK120 +-------->| screen |
| | | |
+---------+ +--------+
examples2:
- |
#include <dt-bindings/mfd/rockchip-serdes.h>
&i2c1 {
status = "okay";
rkx110_x120: rkx110_x120@55 {
compatible = "rockchip,rkx110";
enable-gpios = <&gpio0 RK_PD3 GPIO_ACTIVE_HIGH>;
reset-gpios = <&gpio0 RK_PB7 GPIO_ACTIVE_LOW>;
status = "okay";
remote0-addr = <0x35>;
remote1-addr = <0x36>;
panel {
compatible = "rockchip,serdes_panel";
status = "okay";
local-port0 = <RK_SERDES_LVDS_RX0>;
remote0-port0 = <RK_SERDES_LVDS_TX0>;
remote1-port0 = <RK_SERDES_LVDS_TX0>;
backlight0 = <&backlight>;
power0-supply = <&vcc3v3_lcd_n>;
reset0-gpios = <&gpio0 RK_PC4 GPIO_ACTIVE_LOW>;
reset0-delay-ms = <20>;
enable0-delay-ms = <20>;
prepare0-delay-ms = <20>;
unprepare0-delay-ms = <20>;
disable0-delay-ms = <20>;
bus-format0 = <MEDIA_BUS_FMT_RGB888_1X7X4_SPWG>;
display-timings {
native-mode = <&timing0>;
timing0: timing0 {
clock-frequency = <27000000>;
hactive = <1024>;
vactive = <600>;
hback-porch = <160>;
hfront-porch = <160>;
vback-porch = <20>;
vfront-porch = <15>;
hsync-len = <6>;
vsync-len = <5>;
hsync-active = <0>;
vsync-active = <0>;
de-active = <0>;
pixelclk-active = <0>;
};
};
};
};
};
# example3:
# 1 video source input, 2 channel, 1 lane, 1 remote, 2 video output:
# disp in can select follow interface:
# dsi0_rx, dsi1_rx, lvds0_rx, lvds1_rx, dual-lvds_rx, rgb_rx
# disp out can select follow interface:
# lvds0_tx and lvds1_tx
+--------+
lvds0_tx | |
+--->| screen |
+-------+ +---------+ +---------+ | | |
| | disp in | | cable0 | |----+ +--------+
| soc |--------->| RK110 +----------->| RK120 |
| | | | | |----+ +--------+
+-------+ +---------+ +---------+ | | |
+--->| screen |
lvds1_tx | |
+--------+
examples3:
- |
#include <dt-bindings/mfd/rockchip-serdes.h>
&i2c1 {
status = "okay";
rkx110_x120: rkx110_x120@55 {
compatible = "rockchip,rkx110";
enable-gpios = <&gpio0 RK_PD3 GPIO_ACTIVE_HIGH>;
reset-gpios = <&gpio0 RK_PB7 GPIO_ACTIVE_LOW>;
status = "okay";
remote0-addr = <0x35>;
panel {
compatible = "rockchip,serdes_panel";
status = "okay";
local-port0 = <RK_SERDES_LVDS_RX0>;
remote0-port0 = <RK_SERDES_LVDS_TX0>;
remote0-port1 = <RK_SERDES_LVDS_TX1>;
backlight0 = <&backlight>;
power0-supply = <&vcc3v3_lcd_n>;
reset0-gpios = <&gpio0 RK_PC4 GPIO_ACTIVE_LOW>;
reset0-delay-ms = <20>;
enable0-delay-ms = <20>;
prepare0-delay-ms = <20>;
unprepare0-delay-ms = <20>;
disable0-delay-ms = <20>;
bus-format0 = <MEDIA_BUS_FMT_RGB888_1X7X4_SPWG>;
display-timings {
native-mode = <&timing0>;
timing0: timing0 {
clock-frequency = <27000000>;
hactive = <1024>;
vactive = <600>;
hback-porch = <160>;
hfront-porch = <160>;
vback-porch = <20>;
vfront-porch = <15>;
hsync-len = <6>;
vsync-len = <5>;
hsync-active = <0>;
vsync-active = <0>;
de-active = <0>;
pixelclk-active = <0>;
};
};
};
};
};
# example4:
# 2 video source input, 2 channel, 1 lane, 1 remote, 2 video output:
# disp in can select follow interface:
# dsi0_rx and dsi1_rx, or lvds0_rx and lvds1_rx
# disp out can select follow interface:
# lvds0_tx and lvds1_tx
+--------+
lvds0_tx | |
+--->| screen |
+-------+ disp0_rx +---------+ +---------+ | | |
| |--------->| | cable0 | |----+ +--------+
| soc | disp1_rx | RK110 +----------->| RK120 |
| |--------->| | | |----+ +--------+
+-------+ +---------+ +---------+ | | |
+--->| screen |
lvds1_tx | |
+--------+
examples4:
- |
#include <dt-bindings/mfd/rockchip-serdes.h>
&i2c1 {
status = "okay";
rkx110_x120: rkx110_x120@55 {
compatible = "rockchip,rkx110";
enable-gpios = <&gpio0 RK_PD3 GPIO_ACTIVE_HIGH>;
reset-gpios = <&gpio0 RK_PB7 GPIO_ACTIVE_LOW>;
status = "okay";
remote0-addr = <0x35>;
panel {
compatible = "rockchip,serdes_panel";
status = "okay";
local-port0 = <RK_SERDES_LVDS_RX0>;
local-port1 = <RK_SERDES_LVDS_RX1>;
remote0-port0 = <RK_SERDES_LVDS_TX0>;
remote0-port1 = <RK_SERDES_LVDS_TX1>;
backlight0 = <&backlight>;
power0-supply = <&vcc3v3_lcd_n>;
reset0-gpios = <&gpio0 RK_PC4 GPIO_ACTIVE_LOW>;
reset0-delay-ms = <20>;
enable0-delay-ms = <20>;
prepare0-delay-ms = <20>;
unprepare0-delay-ms = <20>;
disable0-delay-ms = <20>;
bus-format0 = <MEDIA_BUS_FMT_RGB888_1X7X4_SPWG>;
display-timings {
native-mode = <&timing0>;
timing0: timing0 {
clock-frequency = <27000000>;
hactive = <1024>;
vactive = <600>;
hback-porch = <160>;
hfront-porch = <160>;
vback-porch = <20>;
vfront-porch = <15>;
hsync-len = <6>;
vsync-len = <5>;
hsync-active = <0>;
vsync-active = <0>;
de-active = <0>;
pixelclk-active = <0>;
};
};
};
};
};
# example5:
# 2 video source input, 2 channel, 2 lane, 1 remote, 2 video output:
# disp in can select follow interface:
# dsi0_rx and dsi1_rx, or lvds0_rx and lvds1_rx
# disp out can select follow interface:
# lvds0_tx and lvds1_tx
+--------+
lvds0_tx | |
+--->| screen |
+-------+ disp0_rx +---------+ cable0 +---------+ | | |
| |--------->| +----------->| |----+ +--------+
| soc | disp1_rx | RK110 | cable1 | RK120 |
| |--------->| +----------->| |----+ +--------+
+-------+ +---------+ +---------+ | | |
+--->| screen |
lvds1_tx | |
+--------+
examples5:
- |
#include <dt-bindings/mfd/rockchip-serdes.h>
&i2c1 {
status = "okay";
rkx110_x120: rkx110_x120@55 {
compatible = "rockchip,rkx110";
enable-gpios = <&gpio0 RK_PD3 GPIO_ACTIVE_HIGH>;
reset-gpios = <&gpio0 RK_PB7 GPIO_ACTIVE_LOW>;
status = "okay";
remote0-addr = <0x35>;
panel {
compatible = "rockchip,serdes_panel";
status = "okay";
local-port0 = <RK_SERDES_LVDS_RX0>;
local-port1 = <RK_SERDES_LVDS_RX1>;
remote0-port0 = <RK_SERDES_LVDS_TX0>;
remote0-port1 = <RK_SERDES_LVDS_TX1>;
num-lanes = <2>;
backlight0 = <&backlight>;
power0-supply = <&vcc3v3_lcd_n>;
reset0-gpios = <&gpio0 RK_PC4 GPIO_ACTIVE_LOW>;
reset0-delay-ms = <20>;
enable0-delay-ms = <20>;
prepare0-delay-ms = <20>;
unprepare0-delay-ms = <20>;
disable0-delay-ms = <20>;
bus-format0 = <MEDIA_BUS_FMT_RGB888_1X7X4_SPWG>;
display-timings {
native-mode = <&timing0>;
timing0: timing0 {
clock-frequency = <27000000>;
hactive = <1024>;
vactive = <600>;
hback-porch = <160>;
hfront-porch = <160>;
vback-porch = <20>;
vfront-porch = <15>;
hsync-len = <6>;
vsync-len = <5>;
hsync-active = <0>;
vsync-active = <0>;
de-active = <0>;
pixelclk-active = <0>;
};
};
};
};
};
# example6:
# 2 video source input, 2 channel, 2 lane, 2 remote, 2 video output:
# disp in can select follow interface:
# dsi0_rx and dsi1_rx, or lvds0_rx and lvds1_rx
# disp out can select follow interface:
# dsi_tx, lvds0_tx, lvds1_tx, dual-lvds_tx, rgb_tx
+---------+ +--------+
cable0 | |disp0 out| |
+------->| RK120 +-------->| screen |
| | | | |
+-------+ disp0_rx +---------+ | +---------+ +--------+
| |--------->| +---+
| soc | disp1_rx | RK110 |
| |--------->| +---+
+-------+ +---------+ | +---------+ +--------+
|cable1 | |disp1 out| |
+------->| RK120 +-------->| screen |
| | | |
+---------+ +--------+
examples6:
- |
#include <dt-bindings/mfd/rockchip-serdes.h>
&i2c1 {
status = "okay";
rkx110_x120: rkx110_x120@55 {
compatible = "rockchip,rkx110";
enable-gpios = <&gpio0 RK_PD3 GPIO_ACTIVE_HIGH>;
reset-gpios = <&gpio0 RK_PB7 GPIO_ACTIVE_LOW>;
status = "okay";
remote0-addr = <0x35>;
remote1-addr = <0x36>;
panel {
compatible = "rockchip,serdes_panel";
status = "okay";
local-port0 = <RK_SERDES_LVDS_RX0>;
local-port1 = <RK_SERDES_LVDS_RX1>;
remote0-port0 = <RK_SERDES_LVDS_TX0>;
remote1-port0 = <RK_SERDES_LVDS_TX0>;
backlight0 = <&backlight>;
power0-supply = <&vcc3v3_lcd_n>;
reset0-gpios = <&gpio0 RK_PC4 GPIO_ACTIVE_LOW>;
reset0-delay-ms = <20>;
enable0-delay-ms = <20>;
prepare0-delay-ms = <20>;
unprepare0-delay-ms = <20>;
disable0-delay-ms = <20>;
bus-format0 = <MEDIA_BUS_FMT_RGB888_1X7X4_SPWG>;
display-timings {
native-mode = <&timing0>;
timing0: timing0 {
clock-frequency = <27000000>;
hactive = <1024>;
vactive = <600>;
hback-porch = <160>;
hfront-porch = <160>;
vback-porch = <20>;
vfront-porch = <15>;
hsync-len = <6>;
vsync-len = <5>;
hsync-active = <0>;
vsync-active = <0>;
de-active = <0>;
pixelclk-active = <0>;
};
};
};
};
};

2
Documentation/devicetree/bindings/regulator/fan53555.txt
View File

@ -2,7 +2,7 @@ Binding for Fairchild FAN53555 regulators
Required properties:
- compatible: one of "fcs,fan53555", "fcs,fan53526", "silergy,syr827" or
"silergy,syr828", "rockchip,rk8603", "rockchip,rk8604"
"silergy,syr828"
- reg: I2C address
Optional properties:

13
Documentation/devicetree/bindings/spi/spi-rockchip.yaml
View File

@ -94,6 +94,19 @@ properties:
description: Add this property to set the transmission method as CPU polling.
type: boolean
rockchip,cs-inactive-disable:
description: Add this property to disable the cs inactive interrupt for spi
slave.
type: boolean
ready-gpios:
description: GPIO spec for the spi slave ready signal.
maxItems: 1
rockchip,autosuspend-delay-ms:
default: 0
description: Set pm runtime autosuspend value in milliseconds.
required:
- compatible
- reg

5
Documentation/devicetree/bindings/usb/snps,dwc3.yaml
View File

@ -190,6 +190,11 @@ properties:
When set, all SuperSpeed bus instances in park mode are disabled.
type: boolean
snps,parkmode-disable-hs-quirk:
description:
When set, all HighSpeed bus instances in park mode are disabled.
type: boolean
snps,dis_metastability_quirk:
description:
When set, disable metastability workaround. CAUTION! Use only if you are

1
arch/arm/Makefile
View File

@ -157,6 +157,7 @@ ifeq ($(CONFIG_ROCKCHIP_THUNDER_BOOT),y)
textofs-$(CONFIG_CPU_RV1106) := 0x00208000
textofs-$(CONFIG_CPU_RV1126) := 0x00608000
endif
textofs-$(CONFIG_RV1106_HPMCU_FAST_WAKEUP) := 0x00208000
# Machine directory name. This list is sorted alphanumerically
# by CONFIG_* macro name.

8
arch/arm/boot/dts/Makefile
View File

@ -984,6 +984,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += \
rv1106g-38x38-ipc-v10.dtb \
rv1106g-38x38-ipc-v10-spi-nand.dtb \
rv1106g-evb1-mcu-display-v11.dtb \
rv1106g-evb1-mcu-display-v20.dtb \
rv1106g-evb1-rgb-display-v11.dtb \
rv1106g-evb1-v10.dtb \
rv1106g-evb1-v11.dtb \
@ -995,11 +996,18 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += \
rv1106g-evb1-v10-dual-cam.dtb \
rv1106g-evb1-v11-dual-cam.dtb \
rv1106g-evb1-v10-facial-gate.dtb \
rv1106g-evb1-v11-facial-gate.dtb \
rv1106g-evb1-v10-spi-nand.dtb \
rv1106g-evb1-v10-spi-nor.dtb \
rv1106g-evb1-v11-nofastae-spi-nand.dtb \
rv1106g-evb2-v10.dtb \
rv1106g-evb2-v10-dual-camera.dtb \
rv1106g-evb2-v11-emmc.dtb \
rv1106g-evb2-v11-trailcam-emmc.dtb \
rv1106g-evb2-v12-nofastae-emmc.dtb \
rv1106g-evb2-v12-nofastae-spi-nand.dtb \
rv1106g-evb2-v12-nofastae-spi-nor.dtb \
rv1106g-evb2-v12-wakeup.dtb \
rv1106g-smart-door-lock-rmsl-v10.dtb \
rv1106g-smart-door-lock-rmsl-v12.dtb \
rv1106g-uvc-demo-v10.dtb \

60
arch/arm/boot/dts/rk3288-evb-rk808-linux.dts
View File

@ -1,42 +1,4 @@
/*
* This file is dual-licensed: you can use it either under the terms
* of the GPL or the X11 license, at your option. Note that this dual
* licensing only applies to this file, and not this project as a
* whole.
*
* a) This file is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of the
* License, or (at your option) any later version.
*
* This file is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* Or, alternatively,
*
* b) Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use,
* copy, modify, merge, publish, distribute, sublicense, and/or
* sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following
* conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/dts-v1/;
#include "rk3288-evb.dtsi"
@ -174,6 +136,14 @@
pinctrl-0 = <&hdmi_ddc>, <&hdmi_cec_c0>;
};
&hdmi_in_vopb {
status = "okay";
};
&hdmi_in_vopl {
status = "disabled";
};
&i2c0 {
clock-frequency = <400000>;
@ -262,7 +232,8 @@
regulator-max-microvolt = <3300000>;
regulator-name = "vcca_codec";
regulator-state-mem {
regulator-off-in-suspend;
regulator-on-in-suspend;
regulator-suspend-microvolt = <3300000>;
};
};
@ -282,10 +253,10 @@
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
regulator-max-microvolt = <1800000>;
regulator-name = "vcc_wl";
regulator-state-mem {
regulator-off-in-suspend;
regulator-on-in-suspend;
};
};
@ -296,8 +267,7 @@
regulator-max-microvolt = <3300000>;
regulator-name = "vccio_sd";
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <3300000>;
regulator-off-in-suspend;
};
};
@ -340,7 +310,7 @@
regulator-boot-on;
regulator-name = "vcc_sd";
regulator-state-mem {
regulator-on-in-suspend;
regulator-off-in-suspend;
};
};

72
arch/arm/boot/dts/rk3288-evb.dtsi
View File

@ -47,43 +47,49 @@
};
};
sound: sound {
compatible = "simple-audio-card";
simple-audio-card,format = "i2s";
simple-audio-card,name = "rockchip,rt5640-codec";
simple-audio-card,mclk-fs = <512>;
rt5640_sound: rt5640-sound {
status = "okay";
simple-audio-card,dai-link@0 {
format = "i2s";
cpu {
sound-dai = <&i2s>;
};
codec {
sound-dai = <&rt5640>;
};
};
simple-audio-card,dai-link@1 {
format = "i2s";
cpu {
sound-dai = <&i2s>;
};
codec {
sound-dai = <&hdmi>;
};
compatible = "rockchip,multicodecs-card";
rockchip,card-name = "rockchip-rt5640";
hp-det-gpio = <&gpio7 RK_PA7 GPIO_ACTIVE_HIGH>;
io-channels = <&saradc 2>;
io-channel-names = "adc-detect";
keyup-threshold-microvolt = <1800000>;
poll-interval = <100>;
rockchip,format = "i2s";
rockchip,mclk-fs = <512>;
rockchip,cpu = <&i2s>;
rockchip,codec = <&rt5640>;
rockchip,audio-routing =
"Headphone", "HPOL",
"Headphone", "HPOR",
"Speaker", "SPOLP",
"Speaker", "SPOLN",
"Speaker", "SPORP",
"Speaker", "SPORN",
"Headphone", "Headphone Power",
"Headphone", "Headphone Power",
"Speaker", "Speaker Power",
"Speaker", "Speaker Power",
"DMIC L1", "Main Mic",
"DMIC R1", "Main Mic",
"IN3P", "Headset Mic",
"Headset Mic", "MICBIAS1";
play-pause-key {
label = "playpause";
linux,code = <KEY_PLAYPAUSE>;
press-threshold-microvolt = <2000>;
};
};
hdmi_analog_sound: hdmi-analog-sound {
compatible = "rockchip,rk3288-hdmi-analog",
"rockchip,rk3368-hdmi-analog";
rockchip,model = "rockchip,rt5640-codec";
rockchip,cpu = <&i2s>;
rockchip,codec = <&rt5640>, <&hdmi>;
hdmi_sound: hdmi-sound {
status = "disabled";
compatible = "rockchip,hdmi";
rockchip,mclk-fs = <256>;
rockchip,card-name = "rockchip-hdmi0";
rockchip,cpu = <&i2s>;
rockchip,codec = <&hdmi>;
rockchip,jack-det;
};
backlight: backlight {
@ -368,8 +374,6 @@
reg = <0x1c>;
clocks = <&cru SCLK_I2S0_OUT>;
clock-names = "mclk";
interrupt-parent = <&gpio7>;
interrupts = <7 IRQ_TYPE_EDGE_FALLING>;
pinctrl-names = "default";
pinctrl-0 = <&i2s0_mclk>;
};

7
arch/arm/boot/dts/rk3288-linux.dtsi
View File

@ -7,6 +7,13 @@
#include "rk3288-dram-default-timing.dtsi"
/ {
aliases {
mshc0 = &emmc;
mshc1 = &sdmmc;
mshc2 = &sdio0;
mshc3 = &sdio1;
};
chosen {
bootargs = "earlycon=uart8250,mmio32,0xff690000 console=ttyFIQ0 vmalloc=496M rw root=PARTUUID=614e0000-0000 rootfstype=ext4 rootwait";
};

6
arch/arm/boot/dts/rk3308-dot-rk816-v10-aarch32.dts
View File

@ -406,6 +406,12 @@
};
};
wireless-bluetooth {
uart4_gpios: uart4-gpios {
rockchip,pins = <4 RK_PA7 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
wireless-wlan {
wifi_wake_host: wifi-wake-host {
rockchip,pins = <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up>;

6
arch/arm/boot/dts/rk3308-dot-v10-aarch32.dts
View File

@ -225,6 +225,12 @@
};
};
wireless-bluetooth {
uart4_gpios: uart4-gpios {
rockchip,pins = <4 RK_PA7 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
wireless-wlan {
wifi_wake_host: wifi-wake-host {
rockchip,pins = <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up>;

8
arch/arm/boot/dts/rk3308-voice-module-mainboard-v10-aarch32.dtsi
View File

@ -390,6 +390,14 @@
status = "okay";
};
&pinctrl {
wireless-bluetooth {
uart4_gpios: uart4-gpios {
rockchip,pins = <4 RK_PA7 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
};
&pwm3 {
status = "okay";
/* Used for IR */

5
arch/arm/boot/dts/rv1103g-battery-ipc-v10.dts
View File

@ -106,6 +106,11 @@
status = "okay";
};
&cpu0 {
/delete-property/ clocks;
/delete-property/ operating-points-v2;
};
&csi2_dphy_hw {
status = "okay";
};

5
arch/arm/boot/dts/rv1103g-battery-ipc-v11.dts
View File

@ -106,6 +106,11 @@
status = "okay";
};
&cpu0 {
/delete-property/ clocks;
/delete-property/ operating-points-v2;
};
&csi2_dphy_hw {
status = "okay";
};

62
arch/arm/boot/dts/rv1103g-evb-mcu-display-v11.dts
View File

@ -91,22 +91,30 @@
status = "okay";
rockchip,data-sync-bypass;
pinctrl-names = "default";
/*
* rgb3x8_pins for RGB3x8(8bit)
* rgb565_pins for RGB565(16bit)
*/
pinctrl-0 = <&rgb3x8_pins>;
/*
* 320x480 RGB/MCU screen K350C4516T
*/
mcu_panel: mcu-panel {
/*
* MEDIA_BUS_FMT_RGB888_3X8 for RGB3x8(8bit)
* MEDIA_BUS_FMT_RGB565_1X16 for RGB565(16bit)
*/
bus-format = <MEDIA_BUS_FMT_RGB888_3X8>;
backlight = <&backlight>;
enable-gpios = <&gpio3 RK_PC7 GPIO_ACTIVE_LOW>;
enable-delay-ms = <20>;
reset-gpios = <&gpio3 RK_PD0 GPIO_ACTIVE_LOW>;
reset-value = <0>;
reset-delay-ms = <10>;
prepare-delay-ms = <20>;
unprepare-delay-ms = <20>;
disable-delay-ms = <20>;
init-delay-ms = <10>;
width-mm = <217>;
height-mm = <136>;
@ -161,20 +169,31 @@
00 00 01 36
01 00 01 48
00 00 01 3a //interface mode control
01 00 01 77 //spi rgb:66(r1 r4 r5) mcu parallel: 55(r2 r3 r6)
// mcu serial: 77(r1 r3 r6)
00 00 01 3a
01 00 01 66 /*
* interface pixel format:
* 66 for RGB3x8(8bit)
* 55 for RGB565(16bit)
*/
00 00 01 b0 //interface mode control
00 00 01 b0
01 00 01 00
00 00 01 b1 //frame rate 70hz
01 00 01 b0
00 00 01 b1
01 00 01 70 /*
* frame rate control:
* 70 (45hz) for RGB3x8(8bit)
* a0 (60hz) for RGB565(16bit)
*/
01 00 01 11
00 00 01 b4
01 00 01 02
00 00 01 B6 //RGB/MCU Interface Control
01 00 01 02 //02 mcu, 32 rgb
00 00 01 B6
01 00 01 02 /*
* display function control:
* 32 for RGB
* 02 for MCU
*/
01 00 01 02
00 00 01 b7
@ -208,7 +227,11 @@
native-mode = <&kd050fwfba002_timing>;
kd050fwfba002_timing: timing0 {
clock-frequency = <20000000>;
/*
* 7840125 for frame rate 45Hz
* 10453500 for frame rate 60Hz
*/
clock-frequency = <7840125>;
hactive = <320>;
vactive = <480>;
hback-porch = <10>;
@ -267,12 +290,25 @@
&vop {
status = "okay";
/*
* Default config is as follows:
*
* mcu-pix-total = <9>;
* mcu-cs-pst = <1>;
* mcu-cs-pend = <8>;
* mcu-rw-pst = <2>;
* mcu-rw-pend = <5>;
* mcu-hold-mode = <0>; // default set to 0
*
* To increase the frame rate, reduce all parameters because
* the max dclk rate of mcu is 150M in rv1103/rv1106.
*/
mcu-timing {
mcu-pix-total = <9>;
mcu-pix-total = <5>;
mcu-cs-pst = <1>;
mcu-cs-pend = <8>;
mcu-cs-pend = <4>;
mcu-rw-pst = <2>;
mcu-rw-pend = <5>;
mcu-rw-pend = <3>;
mcu-hold-mode = <0>; // default set to 0
};

29
arch/arm/boot/dts/rv1106-evb-cam.dtsi
View File

@ -1,6 +1,6 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (c) 2022 Rockchip Electronics Co., Ltd.
* Copyright (c) 2023 Rockchip Electronics Co., Ltd.
*
*/
@ -45,6 +45,11 @@
remote-endpoint = <&jx_k17_out>;
data-lanes = <1 2>;
};
csi_dphy_input5: endpoint@5 {
reg = <5>;
remote-endpoint = <&sc3338_out>;
data-lanes = <1 2>;
};
};
port@1 {
@ -110,6 +115,28 @@
};
};
sc3338: sc3338@30 {
compatible = "smartsens,sc3338";
status = "okay";
reg = <0x30>;
clocks = <&cru MCLK_REF_MIPI0>;
clock-names = "xvclk";
reset-gpios = <&gpio3 RK_PC5 GPIO_ACTIVE_HIGH>;
pwdn-gpios = <&gpio3 RK_PD2 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&mipi_refclk_out0>;
rockchip,camera-module-index = <0>;
rockchip,camera-module-facing = "back";
rockchip,camera-module-name = "FKO1";
rockchip,camera-module-lens-name = "30IRC-F16";
port {
sc3338_out: endpoint {
remote-endpoint = <&csi_dphy_input5>;
data-lanes = <1 2>;
};
};
};
sc4336: sc4336@30 {
compatible = "smartsens,sc4336";
status = "okay";

58
arch/arm/boot/dts/rv1106-evb-dual-cam.dtsi
View File

@ -7,6 +7,8 @@
* sc4336 0x30 lane2~3(dphy2)
* v1.1.0 gc2053 0x37 lane0~1(dphy1)
* gc2053 0x3f lane2~3(dphy2)
* v1.2.0 sc301iot 0x30 lane0~1(dphy1)
* sc301iot 0x32 lane2~3(dphy2)
*/
&csi2_dphy_hw {
@ -36,6 +38,12 @@
remote-endpoint = <&gc2053_out>;
data-lanes = <1 2>;
};
csi_dphy_input4: endpoint@3 {
reg = <3>;
remote-endpoint = <&sc301iot_out>;
data-lanes = <1 2>;
};
};
port@1 {
@ -74,6 +82,12 @@
remote-endpoint = <&gc2053_1_out>;
data-lanes = <1 2>;
};
csi_dphy_input5: endpoint@3 {
reg = <3>;
remote-endpoint = <&sc301iot_1_out>;
data-lanes = <1 2>;
};
};
port@1 {
@ -139,6 +153,28 @@
};
};
sc301iot: sc301iot@30 {
compatible = "smartsens,sc301iot";
status = "okay";
reg = <0x30>;
clocks = <&cru MCLK_REF_MIPI0>;
clock-names = "xvclk";
reset-gpios = <&gpio3 RK_PC5 GPIO_ACTIVE_HIGH>;
pwdn-gpios = <&gpio3 RK_PD2 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&mipi_refclk_out0>;
rockchip,camera-module-index = <0>;
rockchip,camera-module-facing = "back";
rockchip,camera-module-name = "CMK-OT2349-PC1";
rockchip,camera-module-lens-name = "65IRC-F20";
port {
sc301iot_out: endpoint {
remote-endpoint = <&csi_dphy_input4>;
data-lanes = <1 2>;
};
};
};
sc4336: sc4336@30 {
compatible = "smartsens,sc4336";
status = "okay";
@ -182,6 +218,28 @@
};
};
};
sc301iot_1: sc301iot_1@32 {
compatible = "smartsens,sc301iot";
status = "okay";
reg = <0x32>;
clocks = <&cru MCLK_REF_MIPI1>;
clock-names = "xvclk";
reset-gpios = <&gpio3 RK_PD1 GPIO_ACTIVE_HIGH>;
pwdn-gpios = <&gpio3 RK_PA4 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&mipi_refclk_out1>;
rockchip,camera-module-index = <1>;
rockchip,camera-module-facing = "back";
rockchip,camera-module-name = "CMK-OT2349-PC1";
rockchip,camera-module-lens-name = "65IRC-F20";
port {
sc301iot_1_out: endpoint {
remote-endpoint = <&csi_dphy_input5>;
data-lanes = <1 2>;
};
};
};
};
&mipi0_csi2 {

62
arch/arm/boot/dts/rv1106-evb-ext-mcu-v10.dtsi
View File

@ -81,6 +81,10 @@
status = "okay";
rockchip,data-sync-bypass;
pinctrl-names = "default";
/*
* rgb3x8_pins for RGB3x8(8bit)
* rgb565_pins for RGB565(16bit)
*/
pinctrl-0 = <&rgb565_pins>;
/*
@ -88,19 +92,19 @@
*/
mcu_panel: mcu-panel {
/*
* MEDIA_BUS_FMT_RGB888_3X8 for serial mcu
* MEDIA_BUS_FMT_RGB565_1X16 for parallel mcu
* MEDIA_BUS_FMT_RGB888_3X8 for RGB3x8(8bit)
* MEDIA_BUS_FMT_RGB565_1X16 for RGB565(16bit)
*/
bus-format = <MEDIA_BUS_FMT_RGB565_1X16>;
backlight = <&backlight>;
enable-gpios = <&gpio1 RK_PA3 GPIO_ACTIVE_LOW>;
enable-delay-ms = <20>;
reset-gpios = <&gpio1 RK_PA4 GPIO_ACTIVE_LOW>;
reset-value = <0>;
reset-delay-ms = <10>;
prepare-delay-ms = <20>;
unprepare-delay-ms = <20>;
disable-delay-ms = <20>;
init-delay-ms = <10>;
width-mm = <217>;
height-mm = <136>;
@ -155,20 +159,31 @@
00 00 01 36
01 00 01 48
00 00 01 3a //interface mode control
01 00 01 55 //spi rgb:66(r1 r4 r5) mcu parallel: 55(r2 r3 r6)
// mcu serial: 77(r1 r3 r6)
00 00 01 3a
01 00 01 55 /*
* interface pixel format:
* 66 for RGB3x8(8bit)
* 55 for RGB565(16bit)
*/
00 00 01 b0 //interface mode control
00 00 01 b0
01 00 01 00
00 00 01 b1 //frame rate 70hz
01 00 01 b0
00 00 01 b1
01 00 01 a0 /*
* frame rate control:
* 70 (45hz) for RGB3x8(8bit)
* a0 (60hz) for RGB565(16bit)
*/
01 00 01 11
00 00 01 b4
01 00 01 02
00 00 01 B6 //RGB/MCU Interface Control
01 00 01 02 //02 mcu, 32 rgb
00 00 01 B6
01 00 01 02 /*
* display function control:
* 32 for RGB
* 02 for MCU
*/
01 00 01 02
00 00 01 b7
@ -202,7 +217,11 @@
native-mode = <&kd050fwfba002_timing>;
kd050fwfba002_timing: timing0 {
clock-frequency = <20000000>;
/*
* 7840125 for frame rate 45Hz
* 10453500 for frame rate 60Hz
*/
clock-frequency = <10453500>;
hactive = <320>;
vactive = <480>;
hback-porch = <10>;
@ -261,12 +280,25 @@
&vop {
status = "okay";
/*
* Default config is as follows:
*
* mcu-pix-total = <9>;
* mcu-cs-pst = <1>;
* mcu-cs-pend = <8>;
* mcu-rw-pst = <2>;
* mcu-rw-pend = <5>;
* mcu-hold-mode = <0>; // default set to 0
*
* To increase the frame rate, reduce all parameters because
* the max dclk rate of mcu is 150M in rv1103/rv1106.
*/
mcu-timing {
mcu-pix-total = <9>;
mcu-pix-total = <5>;
mcu-cs-pst = <1>;
mcu-cs-pend = <8>;
mcu-cs-pend = <4>;
mcu-rw-pst = <2>;
mcu-rw-pend = <5>;
mcu-rw-pend = <3>;
mcu-hold-mode = <0>; // default set to 0
};

31
arch/arm/boot/dts/rv1106-tb-nofastae-emmc.dtsi Normal file
View File

@ -0,0 +1,31 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (c) 2023 Rockchip Electronics Co., Ltd.
*/
#include "rv1106-tb-nofastae.dtsi"
/ {
reserved-memory {
mmc_ecsd: mmc@3f000 {
reg = <0x3f000 0x00001000>;
};
mmc_idmac: mmc@100000 {
reg = <0x00100000 0x00100000>;
};
};
thunder_boot_mmc: thunder-boot-mmc {
compatible = "rockchip,thunder-boot-mmc";
reg = <0xffa90000 0x4000>;
memory-region-src = <&ramdisk_c>;
memory-region-dst = <&ramdisk_r>;
memory-region-idmac = <&mmc_idmac>;
};
};
&emmc {
memory-region-ecsd = <&mmc_ecsd>;
post-power-on-delay-ms = <0>;
};

19
arch/arm/boot/dts/rv1106-tb-nofastae-spi-nor.dtsi Normal file
View File

@ -0,0 +1,19 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (c) 2023 Rockchip Electronics Co., Ltd.
*/
#include "rv1106-tb-nofastae.dtsi"
/ {
thunder_boot_spi_nor: thunder-boot-spi-nor {
compatible = "rockchip,thunder-boot-sfc";
reg = <0xffac0000 0x4000>;
memory-region-src = <&ramdisk_c>;
memory-region-dst = <&ramdisk_r>;
};
};
&emmc {
status = "disabled";
};

35
arch/arm/boot/dts/rv1106-tb-nofastae.dtsi Normal file
View File

@ -0,0 +1,35 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (c) 2023 Rockchip Electronics Co., Ltd.
*/
/ {
memory: memory {
device_type = "memory";
reg = <0x00000000 0x08000000>;
};
ramdisk: ramdisk {
compatible = "rockchip,ramdisk";
memory-region = <&ramdisk_r>;
};
reserved-memory {
#address-cells = <1>;
#size-cells = <1>;
ranges;
ramdisk_r: ramdisk_r {
reg = <0x800000 (10 * 0x00100000)>;
};
ramdisk_c: ramdisk_c {
reg = <0x1200000 (5 * 0x00100000)>;
};
};
};
&hw_decompress {
status = "okay";
memory-region = <&ramdisk_c>;
};

5
arch/arm/boot/dts/rv1106-thunder-boot.dtsi
View File

@ -98,3 +98,8 @@
&rkisp_vir0 {
memory-region-thunderboot = <&rkisp_thunderboot>;
};
&rkvenc {
assigned-clocks = <&cru CLK_CORE_VEPU>;
assigned-clock-rates = <410000000>;
};

25
arch/arm/boot/dts/rv1106.dtsi
View File

@ -239,6 +239,18 @@
};
};
mipi0_csi2: mipi0-csi2 {
compatible = "rockchip,rv1106-mipi-csi2";
rockchip,hw = <&mipi0_csi2_hw>, <&mipi1_csi2_hw>;
status = "disabled";
};
mipi1_csi2: mipi1-csi2 {
compatible = "rockchip,rv1106-mipi-csi2";
rockchip,hw = <&mipi0_csi2_hw>, <&mipi1_csi2_hw>;
status = "disabled";
};
mpp_srv: mpp-srv {
compatible = "rockchip,mpp-service";
rockchip,taskqueue-count = <2>;
@ -1175,8 +1187,8 @@
status = "disabled";
};
mipi0_csi2: mipi-csi2@ffa20000 {
compatible = "rockchip,rk3588-mipi-csi2";
mipi0_csi2_hw: mipi-csi2-hw@ffa20000 {
compatible = "rockchip,rv1106-mipi-csi2-hw";
reg = <0xffa20000 0x10000>;
reg-names = "csihost_regs";
interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
@ -1186,11 +1198,11 @@
clock-names = "pclk_csi2host", "clk_rxbyte_hs";
resets = <&cru SRST_P_CSIHOST0>;
reset-names = "srst_csihost_p";
status = "disabled";
status = "okay";
};
mipi1_csi2: mipi-csi2@ffa30000 {
compatible = "rockchip,rk3588-mipi-csi2";
mipi1_csi2_hw: mipi-csi2-hw@ffa30000 {
compatible = "rockchip,rv1106-mipi-csi2-hw";
reg = <0xffa30000 0x10000>;
reg-names = "csihost_regs";
interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
@ -1200,7 +1212,7 @@
clock-names = "pclk_csi2host", "clk_rxbyte_hs";
resets = <&cru SRST_P_CSIHOST1>;
reset-names = "srst_csihost_p";
status = "disabled";
status = "okay";
};
rkvenc: rkvenc@ffa50000 {
@ -1411,6 +1423,7 @@
snps,dis-tx-ipgap-linecheck-quirk;
snps,usb2-gadget-lpm-disable;
snps,usb2-lpm-disable;
snps,parkmode-disable-hs-quirk;
status = "disabled";
};
};

314
arch/arm/boot/dts/rv1106g-evb1-mcu-display-v20.dts Normal file
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@ -0,0 +1,314 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (c) 2023 Rockchip Electronics Co., Ltd.
*/
/dts-v1/;
#include <dt-bindings/display/media-bus-format.h>
#include "rv1106g-evb1-v11.dts"
/ {
model = "Rockchip RV1106G EVB1 V11 Board + RK EVB MCU 8BIT Display V20 Ext Board";
compatible = "rockchip,rv1106g-evb1-mcu-display-v20", "rockchip,rv1106";
backlight: backlight {
status = "okay";
compatible = "pwm-backlight";
pwms = <&pwm3 0 25000 0>;
brightness-levels = <
0 1 2 3 4 5 6 7
8 9 10 11 12 13 14 15
16 17 18 19 20 21 22 23
24 25 26 27 28 29 30 31
32 33 34 35 36 37 38 39
40 41 42 43 44 45 46 47
48 49 50 51 52 53 54 55
56 57 58 59 60 61 62 63
64 65 66 67 68 69 70 71
72 73 74 75 76 77 78 79
80 81 82 83 84 85 86 87
88 89 90 91 92 93 94 95
96 97 98 99 100 101 102 103
104 105 106 107 108 109 110 111
112 113 114 115 116 117 118 119
120 121 122 123 124 125 126 127
128 129 130 131 132 133 134 135
136 137 138 139 140 141 142 143
144 145 146 147 148 149 150 151
152 153 154 155 156 157 158 159
160 161 162 163 164 165 166 167
168 169 170 171 172 173 174 175
176 177 178 179 180 181 182 183
184 185 186 187 188 189 190 191
192 193 194 195 196 197 198 199
200 201 202 203 204 205 206 207
208 209 210 211 212 213 214 215
216 217 218 219 220 221 222 223
224 225 226 227 228 229 230 231
232 233 234 235 236 237 238 239
240 241 242 243 244 245 246 247
248 249 250 251 252 253 254 255>;
default-brightness-level = <200>;
};
reserved-memory {
#address-cells = <1>;
#size-cells = <1>;
ranges;
linux,cma {
compatible = "shared-dma-pool";
inactive;
reusable;
size = <0x1000000>;
linux,cma-default;
};
drm_logo: drm-logo@00000000 {
compatible = "rockchip,drm-logo";
reg = <0x0 0x0>;
};
};
};
&display_subsystem {
status = "okay";
logo-memory-region = <&drm_logo>;
};
&pwm3 {
status = "okay";
pinctrl-names = "active";
pinctrl-0 = <&pwm3m1_pins>;
};
&rgb {
status = "okay";
rockchip,data-sync-bypass;
pinctrl-names = "default";
/*
* rgb3x8_pins for RGB3x8(8bit)
* rgb565_pins for RGB565(16bit)
*/
pinctrl-0 = <&rgb3x8_pins>;
/*
* 320x480 RGB/MCU screen K350C4516T
*/
mcu_panel: mcu-panel {
/*
* MEDIA_BUS_FMT_RGB888_3X8 for RGB3x8(8bit)
* MEDIA_BUS_FMT_RGB565_1X16 for RGB565(16bit)
*/
bus-format = <MEDIA_BUS_FMT_RGB888_3X8>;
backlight = <&backlight>;
enable-gpios = <&gpio0 RK_PA0 GPIO_ACTIVE_LOW>;
enable-delay-ms = <20>;
reset-gpios = <&gpio0 RK_PA2 GPIO_ACTIVE_LOW>;
reset-delay-ms = <10>;
prepare-delay-ms = <20>;
unprepare-delay-ms = <20>;
disable-delay-ms = <20>;
init-delay-ms = <10>;
width-mm = <217>;
height-mm = <136>;
// type:0 is cmd, 1 is data
panel-init-sequence = [
//type delay num val1 val2 val3
00 00 01 e0
01 00 01 00
01 00 01 07
01 00 01 0f
01 00 01 0d
01 00 01 1b
01 00 01 0a
01 00 01 3c
01 00 01 78
01 00 01 4a
01 00 01 07
01 00 01 0e
01 00 01 09
01 00 01 1b
01 00 01 1e
01 00 01 0f
00 00 01 e1
01 00 01 00
01 00 01 22
01 00 01 24
01 00 01 06
01 00 01 12
01 00 01 07
01 00 01 36
01 00 01 47
01 00 01 47
01 00 01 06
01 00 01 0a
01 00 01 07
01 00 01 30
01 00 01 37
01 00 01 0f
00 00 01 c0
01 00 01 10
01 00 01 10
00 00 01 c1
01 00 01 41
00 00 01 c5
01 00 01 00
01 00 01 22
01 00 01 80
00 00 01 36
01 00 01 48
00 00 01 3a
01 00 01 66 /*
* interface pixel format:
* 66 for RGB3x8(8bit)
* 55 for RGB565(16bit)
*/
00 00 01 b0
01 00 01 00
00 00 01 b1
01 00 01 70 /*
* frame rate control:
* 70 (45hz) for RGB3x8(8bit)
* a0 (60hz) for RGB565(16bit)
*/
01 00 01 11
00 00 01 b4
01 00 01 02
00 00 01 B6
01 00 01 02 /*
* display function control:
* 32 for RGB
* 02 for MCU
*/
01 00 01 02
00 00 01 b7
01 00 01 c6
00 00 01 be
01 00 01 00
01 00 01 04
00 00 01 e9
01 00 01 00
00 00 01 f7
01 00 01 a9
01 00 01 51
01 00 01 2c
01 00 01 82
00 78 01 11
00 32 01 29
00 00 01 2c
];
panel-exit-sequence = [
//type delay num val1 val2 val3
00 0a 01 28
00 78 01 10
];
display-timings {
native-mode = <&kd050fwfba002_timing>;
kd050fwfba002_timing: timing0 {
/*
* 7840125 for frame rate 45Hz
* 10453500 for frame rate 60Hz
*/
clock-frequency = <7840125>;
hactive = <320>;
vactive = <480>;
hback-porch = <10>;
hfront-porch = <5>;
vback-porch = <10>;
vfront-porch = <5>;
hsync-len = <10>;
vsync-len = <10>;
hsync-active = <0>;
vsync-active = <0>;
de-active = <0>;
pixelclk-active = <1>;
};
};
port {
panel_in_rgb: endpoint {
remote-endpoint = <&rgb_out_panel>;
};
};
};
ports {
rgb_out: port@1 {
reg = <1>;
#address-cells = <1>;
#size-cells = <0>;
rgb_out_panel: endpoint@0 {
reg = <0>;
remote-endpoint = <&panel_in_rgb>;
};
};
};
};
&rgb_in_vop {
status = "okay";
};
&route_rgb {
status = "disabled";
};
/*
* The pins of sdmmc1 and lcd are multiplexed
*/
&sdio {
status = "disabled";
};
&sdio_pwrseq {
status = "disabled";
};
&vop {
status = "okay";
/*
* Default config is as follows:
*
* mcu-pix-total = <9>;
* mcu-cs-pst = <1>;
* mcu-cs-pend = <8>;
* mcu-rw-pst = <2>;
* mcu-rw-pend = <5>;
* mcu-hold-mode = <0>; // default set to 0
*
* To increase the frame rate, reduce all parameters because
* the max dclk rate of mcu is 150M in rv1103/rv1106.
*/
mcu-timing {
mcu-pix-total = <5>;
mcu-cs-pst = <1>;
mcu-cs-pend = <4>;
mcu-rw-pst = <2>;
mcu-rw-pend = <3>;
mcu-hold-mode = <0>; // default set to 0
};
};

29
arch/arm/boot/dts/rv1106g-evb1-v11-facial-gate.dts Normal file
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// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (c) 2023 Rockchip Electronics Co., Ltd.
*/
/dts-v1/;
#include "rv1106g-evb1-rgb-display-v11.dts"
/ {
model = "Rockchip RV1106G EVB1 V11 Board For Facial Gate";
compatible = "rockchip,rv1106g-evb1-v11-spi-nor-facial-gate", "rockchip,rv1106";
};
&emmc {
status = "disabled";
};
&sfc {
status = "okay";
flash@0 {
compatible = "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <80000000>;
spi-rx-bus-width = <4>;
spi-tx-bus-width = <1>;
};
};

29
arch/arm/boot/dts/rv1106g-evb1-v11-nofastae-spi-nand.dts Normal file
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@ -0,0 +1,29 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (c) 2023 Rockchip Electronics Co., Ltd.
*/
/dts-v1/;
#include "rv1106g-evb1-v11.dts"
#include "rv1106-tb-nofastae.dtsi"
/ {
model = "Rockchip RV1106G EVB1 V11 Board";
compatible = "rockchip,rv1106g-evb1-v11", "rockchip,rv1106";
chosen {
bootargs = "loglevel=0 rootfstype=erofs rootflags=dax console=ttyFIQ0 root=/dev/rd0 snd_soc_core.prealloc_buffer_size_kbytes=16 coherent_pool=0 driver_async_probe=dwmmc_rockchip";
};
};
&fiq_debugger {
rockchip,baudrate = <1500000>;
};
&ramdisk_r {
reg = <0x800000 (15 * 0x00100000)>;
};
&ramdisk_c {
reg = <0x1700000 (10 * 0x00100000)>;
};

2
arch/arm/boot/dts/rv1106g-evb2-v10-dual-camera.dts
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@ -149,7 +149,7 @@
};
sc301iot: sc301iot@32 {
compatible = "smartsens,SC301IOT";
compatible = "smartsens,sc301iot";
status = "okay";
reg = <0x32>;
clocks = <&cru MCLK_REF_MIPI0>;

3
arch/arm/boot/dts/rv1106g-evb2-v10.dts
View File

@ -107,7 +107,8 @@
reg = <0x30>;
clocks = <&cru MCLK_REF_MIPI0>;
clock-names = "xvclk";
pwdn-gpios = <&gpio3 RK_PC5 GPIO_ACTIVE_HIGH>;
reset-gpios = <&gpio3 RK_PC5 GPIO_ACTIVE_HIGH>;
pwdn-gpios = <&gpio3 RK_PD2 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&mipi_refclk_out0>;
rockchip,camera-module-index = <0>;

622
arch/arm/boot/dts/rv1106g-evb2-v11-trailcam-emmc.dts Normal file
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// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (c) 2023 Rockchip Electronics Co., Ltd.
*/
/dts-v1/;
#include "rv1106.dtsi"
#include "rv1106-evb-v10.dtsi"
#include "dt-bindings/display/media-bus-format.h"
#include "rv1106-thunder-boot-emmc.dtsi"
/ {
model = "Rockchip RV1106G EVB2 V11 Trailcam Board";
compatible = "rockchip,rv1106g-evb2-v11-trailcam-emmc", "rockchip,rv1106";
chosen {
bootargs = "loglevel=0 rootfstype=erofs rootflags=dax console=ttyFIQ0 root=/dev/rd0 snd_soc_core.prealloc_buffer_size_kbytes=16 coherent_pool=0 driver_async_probe=dwmmc_rockchip";
};
/delete-node/ adc-keys;
adc-keys {
compatible = "adc-keys";
io-channels = <&saradc 0>;
io-channel-names = "buttons";
poll-interval = <100>;
keyup-threshold-microvolt = <901715>;
key_volumeup-key {
label = "key_volumeup";
linux,code = <KEY_VOLUMEUP>;
press-threshold-microvolt = <17578>;
};
};
backlight: backlight {
status = "okay";
compatible = "pwm-backlight";
pwms = <&pwm7 0 25000 0>;
brightness-levels = <
0 1 2 3 4 5 6 7
8 9 10 11 12 13 14 15
16 17 18 19 20 21 22 23
24 25 26 27 28 29 30 31
32 33 34 35 36 37 38 39
40 41 42 43 44 45 46 47
48 49 50 51 52 53 54 55
56 57 58 59 60 61 62 63
64 65 66 67 68 69 70 71
72 73 74 75 76 77 78 79
80 81 82 83 84 85 86 87
88 89 90 91 92 93 94 95
96 97 98 99 100 101 102 103
104 105 106 107 108 109 110 111
112 113 114 115 116 117 118 119
120 121 122 123 124 125 126 127
128 129 130 131 132 133 134 135
136 137 138 139 140 141 142 143
144 145 146 147 148 149 150 151
152 153 154 155 156 157 158 159
160 161 162 163 164 165 166 167
168 169 170 171 172 173 174 175
176 177 178 179 180 181 182 183
184 185 186 187 188 189 190 191
192 193 194 195 196 197 198 199
200 201 202 203 204 205 206 207
208 209 210 211 212 213 214 215
216 217 218 219 220 221 222 223
224 225 226 227 228 229 230 231
232 233 234 235 236 237 238 239
240 241 242 243 244 245 246 247
248 249 250 251 252 253 254 255>;
default-brightness-level = <200>;
};
gpio-keys {
compatible = "gpio-keys";
autorepeat;
key {
gpios = <&gpio0 RK_PA1 GPIO_ACTIVE_HIGH>;
linux,code = <KEY_VOLUMEDOWN>;
label = "GPIO Key";
debounce-interval = <100>;
};
};
reserved-memory {
#address-cells = <1>;
#size-cells = <1>;
ranges;
/*
linux,cma {
compatible = "shared-dma-pool";
inactive;
reusable;
size = <0x300000>;
linux,cma-default;
};
*/
drm_logo: drm-logo@00000000 {
compatible = "rockchip,drm-logo";
reg = <0x0 0x0>;
};
};
vcc_1v8: vcc-1v8 {
compatible = "regulator-fixed";
regulator-name = "vcc_1v8";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
};
vcc_3v3: vcc-3v3 {
compatible = "regulator-fixed";
regulator-name = "vcc_3v3";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
};
vcc3v3_sd: vcc3v3-sd {
compatible = "regulator-fixed";
gpio = <&gpio2 RK_PA7 GPIO_ACTIVE_LOW>;
regulator-name = "vcc3v3_sd";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
pinctrl-names = "default";
pinctrl-0 = <&sdmmc_pwren>;
};
wireless_wlan: wireless-wlan {
compatible = "wlan-platdata";
WIFI,host_wake_irq = <&gpio1 RK_PB0 GPIO_ACTIVE_HIGH>;
status = "okay";
};
};
&acodec {
pa-ctl-gpios = <&gpio2 RK_PB0 GPIO_ACTIVE_HIGH>;
};
&csi2_dphy_hw {
status = "okay";
};
&csi2_dphy0 {
status = "okay";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
#address-cells = <1>;
#size-cells = <0>;
csi_dphy_input0: endpoint@0 {
reg = <0>;
remote-endpoint = <&sc3338_out>;
data-lanes = <1 2>;
};
};
port@1 {
reg = <1>;
#address-cells = <1>;
#size-cells = <0>;
csi_dphy_output: endpoint@0 {
reg = <0>;
remote-endpoint = <&mipi_csi2_input>;
};
};
};
};
&display_subsystem {
status = "okay";
logo-memory-region = <&drm_logo>;
};
&emmc {
status = "okay";
};
&fiq_debugger {
rockchip,baudrate = <1500000>;
pinctrl-names = "default";
pinctrl-0 = <&uart2m1_xfer>;
};
&i2c4 {
rockchip,amp-shared;
sc3338: sc3338@30 {
compatible = "smartsens,sc3338";
status = "okay";
reg = <0x30>;
clocks = <&cru MCLK_REF_MIPI0>;
clock-names = "xvclk";
pwdn-gpios = <&gpio3 RK_PC5 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&mipi_refclk_out0>;
rockchip,camera-module-index = <0>;
rockchip,camera-module-facing = "back";
rockchip,camera-module-name = "FKO1";
rockchip,camera-module-lens-name = "30IRC-F16";
port {
sc3338_out: endpoint {
remote-endpoint = <&csi_dphy_input0>;
data-lanes = <1 2>;
};
};
};
};
&mipi0_csi2 {
status = "okay";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
#address-cells = <1>;
#size-cells = <0>;
mipi_csi2_input: endpoint@1 {
reg = <1>;
remote-endpoint = <&csi_dphy_output>;
};
};
port@1 {
reg = <1>;
#address-cells = <1>;
#size-cells = <0>;
mipi_csi2_output: endpoint@0 {
reg = <0>;
remote-endpoint = <&cif_mipi_in>;
};
};
};
};
&mailbox {
status = "okay";
};
&pwm7 {
status = "okay";
pinctrl-names = "active";
pinctrl-0 = <&pwm7m1_pins>;
};
&pinctrl {
sdmmc {
/omit-if-no-ref/
sdmmc_pwren: sdmmc-pwren {
rockchip,pins = <2 RK_PA7 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
};
&pwm10 {
status = "okay";
};
&pwm11 {
status = "okay";
};
&rgb {
status = "okay";
rockchip,data-sync-bypass;
pinctrl-names = "default";
/*
* rgb3x8_pins for RGB3x8(8bit)
* rgb565_pins for RGB565(16bit)
*/
pinctrl-0 = <&rgb3x8_pins>;
/*
* 320x480 RGB/MCU screen K350C4516T
*/
mcu_panel: mcu-panel {
/*
* MEDIA_BUS_FMT_RGB888_3X8 for RGB3x8(8bit)
* MEDIA_BUS_FMT_RGB565_1X16 for RGB565(16bit)
*/
bus-format = <MEDIA_BUS_FMT_RGB888_3X8>;
backlight = <&backlight>;
enable-gpios = <&gpio2 RK_PA6 GPIO_ACTIVE_LOW>;
enable-delay-ms = <20>;
reset-gpios = <&gpio1 RK_PA1 GPIO_ACTIVE_LOW>;
reset-delay-ms = <10>;
prepare-delay-ms = <20>;
unprepare-delay-ms = <20>;
disable-delay-ms = <20>;
init-delay-ms = <10>;
width-mm = <217>;
height-mm = <136>;
// type:0 is cmd, 1 is data
panel-init-sequence = [
//type delay num val1 val2 val3
00 00 01 e0
01 00 01 00
01 00 01 07
01 00 01 0f
01 00 01 0d
01 00 01 1b
01 00 01 0a
01 00 01 3c
01 00 01 78
01 00 01 4a
01 00 01 07
01 00 01 0e
01 00 01 09
01 00 01 1b
01 00 01 1e
01 00 01 0f
00 00 01 e1
01 00 01 00
01 00 01 22
01 00 01 24
01 00 01 06
01 00 01 12
01 00 01 07
01 00 01 36
01 00 01 47
01 00 01 47
01 00 01 06
01 00 01 0a
01 00 01 07
01 00 01 30
01 00 01 37
01 00 01 0f
00 00 01 c0
01 00 01 10
01 00 01 10
00 00 01 c1
01 00 01 41
00 00 01 c5
01 00 01 00
01 00 01 22
01 00 01 80
00 00 01 36
01 00 01 48
00 00 01 3a
01 00 01 66 /*
* interface pixel format:
* 66 for RGB3x8(8bit)
* 55 for RGB565(16bit)
*/
00 00 01 b0
01 00 01 00
00 00 01 b1
01 00 01 70 /*
* frame rate control:
* 70 (45hz) for RGB3x8(8bit)
* a0 (60hz) for RGB565(16bit)
*/
01 00 01 11
00 00 01 b4
01 00 01 02
00 00 01 B6
01 00 01 02 /*
* display function control:
* 32 for RGB
* 02 for MCU
*/
01 00 01 02
00 00 01 b7
01 00 01 c6
00 00 01 be
01 00 01 00
01 00 01 04
00 00 01 e9
01 00 01 00
00 00 01 f7
01 00 01 a9
01 00 01 51
01 00 01 2c
01 00 01 82
00 78 01 11
00 32 01 29
00 00 01 2c
];
panel-exit-sequence = [
//type delay num val1 val2 val3
00 0a 01 28
00 78 01 10
];
display-timings {
native-mode = <&kd050fwfba002_timing>;
kd050fwfba002_timing: timing0 {
/*
* 7840125 for frame rate 45Hz
* 10453500 for frame rate 60Hz
*/
clock-frequency = <7840125>;
hactive = <320>;
vactive = <480>;
hback-porch = <10>;
hfront-porch = <5>;
vback-porch = <10>;
vfront-porch = <5>;
hsync-len = <10>;
vsync-len = <10>;
hsync-active = <0>;
vsync-active = <0>;
de-active = <0>;
pixelclk-active = <1>;
};
};
port {
panel_in_rgb: endpoint {
remote-endpoint = <&rgb_out_panel>;
};
};
};
ports {
rgb_out: port@1 {
reg = <1>;
#address-cells = <1>;
#size-cells = <0>;
rgb_out_panel: endpoint@0 {
reg = <0>;
remote-endpoint = <&panel_in_rgb>;
};
};
};
};
&rgb_in_vop {
status = "okay";
};
&route_rgb {
status = "disabled";
};
/*
* The pins of sdmmc1 and lcd are multiplexed
*/
&sdio {
status = "disabled";
};
&saradc {
status = "okay";
vref-supply = <&vcc_1v8>;
};
&thunder_boot_service {
status = "okay";
};
&rkisp_thunderboot {
/* reg's offset MUST match with RTOS */
/*
* vicap, capture raw10, ceil(w*10/8/256)*256*h *4(buf num)
* e.g. 2304x1296: 0xf30000
*/
reg = <0x00860000 0xf30000>;
};
&ramdisk_r {
reg = <0x1790000 (20 * 0x00100000)>;
};
&ramdisk_c {
reg = <0x2b90000 (10 * 0x00100000)>;
};
&rkcif {
status = "okay";
};
&rkcif_mipi_lvds {
status = "okay";
memory-region-thunderboot = <&rkisp_thunderboot>;
pinctrl-names = "default";
pinctrl-0 = <&mipi_pins>;
port {
/* MIPI CSI-2 endpoint */
cif_mipi_in: endpoint {
remote-endpoint = <&mipi_csi2_output>;
};
};
};
&rkcif_mipi_lvds_sditf {
status = "okay";
port {
/* MIPI CSI-2 endpoint */
mipi_lvds_sditf: endpoint {
remote-endpoint = <&isp_in>;
};
};
};
&rkisp {
status = "okay";
};
&rkisp_vir0 {
status = "okay";
port@0 {
isp_in: endpoint {
remote-endpoint = <&mipi_lvds_sditf>;
};
};
};
&sdio {
max-frequency = <50000000>;
bus-width = <1>;
cap-sd-highspeed;
cap-sdio-irq;
keep-power-in-suspend;
non-removable;
rockchip,default-sample-phase = <90>;
no-sd;
no-mmc;
supports-sdio;
pinctrl-names = "default";
pinctrl-0 = <&sdmmc1m0_cmd &sdmmc1m0_clk &sdmmc1m0_bus4>;
status = "okay";
};
&sdmmc {
max-frequency = <200000000>;
no-sdio;
no-mmc;
bus-width = <4>;
cap-mmc-highspeed;
cap-sd-highspeed;
disable-wp;
pinctrl-names = "normal", "idle";
pinctrl-0 = <&sdmmc0_clk &sdmmc0_cmd &sdmmc0_det &sdmmc0_bus4>;
pinctrl-1 = <&sdmmc0_idle_pins &sdmmc0_det>;
vmmc-supply = <&vcc3v3_sd>;
status = "okay";
};
&sfc {
assigned-clocks = <&cru SCLK_SFC>;
assigned-clock-rates = <125000000>;
status = "disabled";
flash@0 {
compatible = "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <125000000>;
spi-rx-bus-width = <4>;
spi-tx-bus-width = <1>;
};
};
&usbdrd_dwc3 {
dr_mode = "peripheral";
};
&vop {
status = "okay";
/*
* Default config is as follows:
*
* mcu-pix-total = <9>;
* mcu-cs-pst = <1>;
* mcu-cs-pend = <8>;
* mcu-rw-pst = <2>;
* mcu-rw-pend = <5>;
* mcu-hold-mode = <0>; // default set to 0
*
* To increase the frame rate, reduce all parameters because
* the max dclk rate of mcu is 150M in rv1103/rv1106.
*/
mcu-timing {
mcu-pix-total = <5>;
mcu-cs-pst = <1>;
mcu-cs-pend = <4>;
mcu-rw-pst = <2>;
mcu-rw-pend = <3>;
mcu-hold-mode = <0>; // default set to 0
};
};

134
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// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (c) 2023 Rockchip Electronics Co., Ltd.
*/
/dts-v1/;
#include "rv1106.dtsi"
#include "rv1106-evb-v10.dtsi"
#include "rv1106-evb-cam.dtsi"
#include "rv1106-tb-nofastae-emmc.dtsi"
/ {
model = "Rockchip RV1106G EVB2 V12 Board";
compatible = "rockchip,rv1106g-evb2-v12", "rockchip,rv1106";
chosen {
bootargs = "loglevel=0 rootfstype=erofs rootflags=dax console=ttyFIQ0 root=/dev/rd0 snd_soc_core.prealloc_buffer_size_kbytes=16 coherent_pool=0 driver_async_probe=dwmmc_rockchip";
};
vcc_1v8: vcc-1v8 {
compatible = "regulator-fixed";
regulator-name = "vcc_1v8";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
};
vcc_3v3: vcc-3v3 {
compatible = "regulator-fixed";
regulator-name = "vcc_3v3";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
};
vcc3v3_sd: vcc3v3-sd {
compatible = "regulator-fixed";
gpio = <&gpio2 RK_PA7 GPIO_ACTIVE_LOW>;
regulator-name = "vcc3v3_sd";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
pinctrl-names = "default";
pinctrl-0 = <&sdmmc_pwren>;
};
wireless_wlan: wireless-wlan {
compatible = "wlan-platdata";
WIFI,host_wake_irq = <&gpio1 RK_PB0 GPIO_ACTIVE_HIGH>;
status = "okay";
};
};
&fiq_debugger {
rockchip,baudrate = <1500000>;
pinctrl-names = "default";
pinctrl-0 = <&uart2m1_xfer>;
};
&pinctrl {
sdmmc {
/omit-if-no-ref/
sdmmc_pwren: sdmmc-pwren {
rockchip,pins = <2 RK_PA7 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
};
&pwm10 {
status = "okay";
};
&pwm11 {
status = "okay";
};
&ramdisk_r {
reg = <0x800000 (20 * 0x00100000)>;
};
&ramdisk_c {
reg = <0x1C00000 (10 * 0x00100000)>;
};
&sdio {
max-frequency = <50000000>;
bus-width = <1>;
cap-sd-highspeed;
cap-sdio-irq;
keep-power-in-suspend;
non-removable;
rockchip,default-sample-phase = <90>;
no-sd;
no-mmc;
supports-sdio;
pinctrl-names = "default";
pinctrl-0 = <&sdmmc1m0_cmd &sdmmc1m0_clk &sdmmc1m0_bus4>;
status = "okay";
};
&sdmmc {
max-frequency = <200000000>;
no-sdio;
no-mmc;
bus-width = <4>;
cap-mmc-highspeed;
cap-sd-highspeed;
disable-wp;
pinctrl-names = "normal", "idle";
pinctrl-0 = <&sdmmc0_clk &sdmmc0_cmd &sdmmc0_det &sdmmc0_bus4>;
pinctrl-1 = <&sdmmc0_idle_pins &sdmmc0_det>;
vmmc-supply = <&vcc3v3_sd>;
status = "okay";
};
&sfc {
assigned-clocks = <&cru SCLK_SFC>;
assigned-clock-rates = <125000000>;
status = "disabled";
flash@0 {
compatible = "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <125000000>;
spi-rx-bus-width = <4>;
spi-tx-bus-width = <1>;
};
};
&usbdrd_dwc3 {
dr_mode = "peripheral";
};

129
arch/arm/boot/dts/rv1106g-evb2-v12-nofastae-spi-nand.dts Normal file
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@ -0,0 +1,129 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (c) 2023 Rockchip Electronics Co., Ltd.
*/
/dts-v1/;
#include "rv1106.dtsi"
#include "rv1106-evb-v10.dtsi"
#include "rv1106-evb-cam.dtsi"
#include "rv1106-tb-nofastae.dtsi"
/ {
model = "Rockchip RV1106G EVB2 V12 Board SPI NAND";
compatible = "rockchip,rv1106g-evb2-v12", "rockchip,rv1106";
chosen {
bootargs = "loglevel=0 rootfstype=erofs rootflags=dax console=ttyFIQ0 root=/dev/rd0 snd_soc_core.prealloc_buffer_size_kbytes=16 coherent_pool=0 driver_async_probe=dwmmc_rockchip";
};
vcc_1v8: vcc-1v8 {
compatible = "regulator-fixed";
regulator-name = "vcc_1v8";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
};
vcc_3v3: vcc-3v3 {
compatible = "regulator-fixed";
regulator-name = "vcc_3v3";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
};
vcc3v3_sd: vcc3v3-sd {
compatible = "regulator-fixed";
gpio = <&gpio2 RK_PA7 GPIO_ACTIVE_LOW>;
regulator-name = "vcc3v3_sd";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
pinctrl-names = "default";
pinctrl-0 = <&sdmmc_pwren>;
};
wireless_wlan: wireless-wlan {
compatible = "wlan-platdata";
WIFI,host_wake_irq = <&gpio1 RK_PB0 GPIO_ACTIVE_HIGH>;
status = "okay";
};
};
&fiq_debugger {
rockchip,baudrate = <1500000>;
};
&pinctrl {
sdmmc {
/omit-if-no-ref/
sdmmc_pwren: sdmmc-pwren {
rockchip,pins = <2 RK_PA7 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
};
&pwm10 {
status = "okay";
};
&pwm11 {
status = "okay";
};
&ramdisk_r {
reg = <0x800000 (15 * 0x00100000)>;
};
&ramdisk_c {
reg = <0x1700000 (10 * 0x00100000)>;
};
&sdio {
max-frequency = <50000000>;
bus-width = <1>;
cap-sd-highspeed;
cap-sdio-irq;
keep-power-in-suspend;
non-removable;
rockchip,default-sample-phase = <90>;
no-sd;
no-mmc;
supports-sdio;
pinctrl-names = "default";
pinctrl-0 = <&sdmmc1m0_cmd &sdmmc1m0_clk &sdmmc1m0_bus4>;
status = "okay";
};
&sdmmc {
max-frequency = <200000000>;
no-sdio;
no-mmc;
bus-width = <4>;
cap-mmc-highspeed;
cap-sd-highspeed;
disable-wp;
pinctrl-names = "normal", "idle";
pinctrl-0 = <&sdmmc0_clk &sdmmc0_cmd &sdmmc0_det &sdmmc0_bus4>;
pinctrl-1 = <&sdmmc0_idle_pins &sdmmc0_det>;
vmmc-supply = <&vcc3v3_sd>;
status = "okay";
};
&sfc {
status = "okay";
flash@0 {
compatible = "spi-nand";
reg = <0>;
spi-max-frequency = <75000000>;
spi-rx-bus-width = <4>;
spi-tx-bus-width = <1>;
};
};
&usbdrd_dwc3 {
dr_mode = "peripheral";
};

134
arch/arm/boot/dts/rv1106g-evb2-v12-nofastae-spi-nor.dts Normal file
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@ -0,0 +1,134 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (c) 2023 Rockchip Electronics Co., Ltd.
*/
/dts-v1/;
#include "rv1106.dtsi"
#include "rv1106-evb-v10.dtsi"
#include "rv1106-evb-cam.dtsi"
#include "rv1106-tb-nofastae-spi-nor.dtsi"
/ {
model = "Rockchip RV1106G EVB2 V12 Board";
compatible = "rockchip,rv1106g-evb2-v12", "rockchip,rv1106";
chosen {
bootargs = "loglevel=0 rootfstype=erofs rootflags=dax console=ttyFIQ0 root=/dev/rd0 snd_soc_core.prealloc_buffer_size_kbytes=16 coherent_pool=0 driver_async_probe=dwmmc_rockchip";
};
vcc_1v8: vcc-1v8 {
compatible = "regulator-fixed";
regulator-name = "vcc_1v8";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
};
vcc_3v3: vcc-3v3 {
compatible = "regulator-fixed";
regulator-name = "vcc_3v3";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
};
vcc3v3_sd: vcc3v3-sd {
compatible = "regulator-fixed";
gpio = <&gpio2 RK_PA7 GPIO_ACTIVE_LOW>;
regulator-name = "vcc3v3_sd";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
pinctrl-names = "default";
pinctrl-0 = <&sdmmc_pwren>;
};
wireless_wlan: wireless-wlan {
compatible = "wlan-platdata";
WIFI,host_wake_irq = <&gpio1 RK_PB0 GPIO_ACTIVE_HIGH>;
status = "okay";
};
};
&fiq_debugger {
rockchip,baudrate = <1500000>;
pinctrl-names = "default";
pinctrl-0 = <&uart2m1_xfer>;
};
&pinctrl {
sdmmc {
/omit-if-no-ref/
sdmmc_pwren: sdmmc-pwren {
rockchip,pins = <2 RK_PA7 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
};
&pwm10 {
status = "okay";
};
&pwm11 {
status = "okay";
};
&ramdisk_r {
reg = <0x800000 (10 * 0x00100000)>;
};
&ramdisk_c {
reg = <0x1200000 (5 * 0x00100000)>;
};
&sdio {
max-frequency = <50000000>;
bus-width = <1>;
cap-sd-highspeed;
cap-sdio-irq;
keep-power-in-suspend;
non-removable;
rockchip,default-sample-phase = <90>;
no-sd;
no-mmc;
supports-sdio;
pinctrl-names = "default";
pinctrl-0 = <&sdmmc1m0_cmd &sdmmc1m0_clk &sdmmc1m0_bus4>;
status = "okay";
};
&sdmmc {
max-frequency = <200000000>;
no-sdio;
no-mmc;
bus-width = <4>;
cap-mmc-highspeed;
cap-sd-highspeed;
disable-wp;
pinctrl-names = "normal", "idle";
pinctrl-0 = <&sdmmc0_clk &sdmmc0_cmd &sdmmc0_det &sdmmc0_bus4>;
pinctrl-1 = <&sdmmc0_idle_pins &sdmmc0_det>;
vmmc-supply = <&vcc3v3_sd>;
status = "okay";
};
&sfc {
assigned-clocks = <&cru SCLK_SFC>;
assigned-clock-rates = <125000000>;
status = "okay";
flash@0 {
compatible = "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <125000000>;
spi-rx-bus-width = <4>;
spi-tx-bus-width = <1>;
};
};
&usbdrd_dwc3 {
dr_mode = "peripheral";
};

327
arch/arm/boot/dts/rv1106g-evb2-v12-wakeup.dts Normal file
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@ -0,0 +1,327 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (c) 2023 Rockchip Electronics Co., Ltd.
*/
/dts-v1/;
#include "rv1106.dtsi"
#include "rv1106-evb-v10.dtsi"
/ {
model = "Rockchip RV1106G EVB2 V12 Board";
compatible = "rockchip,rv1106g-evb2-v12-wakeup", "rockchip,rv1106";
chosen {
bootargs = "clk_gate.always_on=1";
};
reserved-memory {
#address-cells = <1>;
#size-cells = <1>;
ranges;
rtos: rtos@40000 {
reg = <0x40000 0x3c000>;
};
meta: meta@800000 {
/* reg's offset MUST match with RTOS */
reg = <0x00800000 0x60000>;
};
rkisp_thunderboot: rkisp@860000 {
/* reg's offset MUST match with RTOS */
/*
* vicap, capture raw10, ceil(w*10/8/256)*256*h *4(buf num)
* e.g. 1920x1080: 0xa8c000
*/
reg = <0x00860000 0xa8c000>;
};
};
thunder_boot_service: thunder-boot-service {
compatible = "rockchip,thunder-boot-service";
mbox-names = "amp-rx";
mboxes = <&mailbox 1>;
resets = <&cru SRST_CORE_MCU>, <&cru SRST_CORE_MCU_PWRUP>,
<&cru SRST_CORE_MCU_CPU>, <&cru SRST_T_CORE_MCU_CPU>;
reset-names = "core_mcu", "core_mcu_pwrup",
"core_mcu_cpu", "t_core_mcu_cpu";
memory-region = <&rtos>;
status = "disabled";
};
vcc_1v8: vcc-1v8 {
compatible = "regulator-fixed";
regulator-name = "vcc_1v8";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
};
vcc_3v3: vcc-3v3 {
compatible = "regulator-fixed";
regulator-name = "vcc_3v3";
regulator-always-on;
regulator-boot-on;
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
};
vcc3v3_sd: vcc3v3-sd {
compatible = "regulator-fixed";
gpio = <&gpio2 RK_PA7 GPIO_ACTIVE_LOW>;
regulator-name = "vcc3v3_sd";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
pinctrl-names = "default";
pinctrl-0 = <&sdmmc_pwren>;
};
wireless_wlan: wireless-wlan {
compatible = "wlan-platdata";
WIFI,host_wake_irq = <&gpio1 RK_PB0 GPIO_ACTIVE_HIGH>;
status = "okay";
};
gpio-keys {
compatible = "gpio-keys";
autorepeat;
pinctrl-names = "default";
pinctrl-0 = <&pwr_key>;
power-key {
gpios = <&gpio0 RK_PA1 GPIO_ACTIVE_HIGH>;
linux,code = <KEY_POWER>;
label ="GPIO Key Power";
debounce-interval = <100>;
wakeup-source;
/* gpio-key,wakeup; */
};
};
};
&pinctrl {
buttons {
pwr_key: pwr-key {
rockchip,pins = <0 RK_PA1 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
};
&csi2_dphy_hw {
status = "okay";
};
&csi2_dphy0 {
status = "okay";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
#address-cells = <1>;
#size-cells = <0>;
csi_dphy_input0: endpoint@0 {
reg = <0>;
remote-endpoint = <&sc3338_out>;
data-lanes = <1 2>;
};
};
port@1 {
reg = <1>;
#address-cells = <1>;
#size-cells = <0>;
csi_dphy_output: endpoint@0 {
reg = <0>;
remote-endpoint = <&mipi_csi2_input>;
};
};
};
};
&emmc {
status = "disabled";
};
&fiq_debugger {
rockchip,baudrate = <1500000>;
pinctrl-names = "default";
pinctrl-0 = <&uart2m1_xfer>;
};
&i2c4 {
rockchip,amp-shared;
sc3338: sc3338@30 {
compatible = "smartsens,sc3338";
status = "okay";
reg = <0x30>;
clocks = <&cru MCLK_REF_MIPI0>;
clock-names = "xvclk";
reset-gpios = <&gpio3 RK_PC5 GPIO_ACTIVE_HIGH>;
pwdn-gpios = <&gpio3 RK_PD2 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&mipi_refclk_out0>;
rockchip,camera-module-index = <0>;
rockchip,camera-module-facing = "back";
rockchip,camera-module-name = "FKO1";
rockchip,camera-module-lens-name = "30IRC-F16";
port {
sc3338_out: endpoint {
remote-endpoint = <&csi_dphy_input0>;
data-lanes = <1 2>;
};
};
};
};
&mipi0_csi2 {
status = "okay";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
#address-cells = <1>;
#size-cells = <0>;
mipi_csi2_input: endpoint@1 {
reg = <1>;
remote-endpoint = <&csi_dphy_output>;
};
};
port@1 {
reg = <1>;
#address-cells = <1>;
#size-cells = <0>;
mipi_csi2_output: endpoint@0 {
reg = <0>;
remote-endpoint = <&cif_mipi_in>;
};
};
};
};
&mailbox {
status = "okay";
};
&rkcif {
status = "okay";
};
&rkcif_mipi_lvds {
status = "okay";
//memory-region-thunderboot = <&rkisp_thunderboot>;
pinctrl-names = "default";
pinctrl-0 = <&mipi_pins>;
port {
/* MIPI CSI-2 endpoint */
cif_mipi_in: endpoint {
remote-endpoint = <&mipi_csi2_output>;
};
};
};
&rkcif_mipi_lvds_sditf {
status = "okay";
port {
/* MIPI CSI-2 endpoint */
mipi_lvds_sditf: endpoint {
remote-endpoint = <&isp_in>;
};
};
};
&rkisp {
status = "okay";
};
&rkisp_vir0 {
status = "okay";
port@0 {
isp_in: endpoint {
remote-endpoint = <&mipi_lvds_sditf>;
};
};
};
&pinctrl {
sdmmc {
/omit-if-no-ref/
sdmmc_pwren: sdmmc-pwren {
rockchip,pins = <2 RK_PA7 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
};
&pwm10 {
status = "okay";
};
&pwm11 {
status = "okay";
};
&sdio {
max-frequency = <50000000>;
bus-width = <1>;
cap-sd-highspeed;
cap-sdio-irq;
keep-power-in-suspend;
non-removable;
rockchip,default-sample-phase = <90>;
no-sd;
no-mmc;
supports-sdio;
pinctrl-names = "default";
pinctrl-0 = <&sdmmc1m0_cmd &sdmmc1m0_clk &sdmmc1m0_bus4>;
status = "okay";
};
&sdmmc {
max-frequency = <200000000>;
no-sdio;
no-mmc;
bus-width = <4>;
cap-mmc-highspeed;
cap-sd-highspeed;
disable-wp;
pinctrl-names = "normal", "idle";
pinctrl-0 = <&sdmmc0_clk &sdmmc0_cmd &sdmmc0_det &sdmmc0_bus4>;
pinctrl-1 = <&sdmmc0_idle_pins &sdmmc0_det>;
vmmc-supply = <&vcc3v3_sd>;
status = "okay";
};
&sfc {
assigned-clocks = <&cru SCLK_SFC>;
assigned-clock-rates = <125000000>;
status = "okay";
flash@0 {
compatible = "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <125000000>;
spi-rx-bus-width = <4>;
spi-tx-bus-width = <1>;
};
};
&usbdrd_dwc3 {
dr_mode = "peripheral";
};

8
arch/arm/boot/dts/rv1106g-smart-door-lock-rmsl-v10.dts
View File

@ -117,6 +117,14 @@
status = "okay";
};
&ramdisk_r {
reg = <0x12ec000 (15 * 0x00100000)>;
};
&ramdisk_c {
reg = <0x21ec000 (7 * 0x00100000)>;
};
&sdmmc {
max-frequency = <50000000>;
bus-width = <1>;

11
arch/arm/boot/dts/rv1126.dtsi
View File

@ -353,6 +353,12 @@
};
};
mipi_csi2: mipi-csi2 {
compatible = "rockchip,rv1126-mipi-csi2";
rockchip,hw = <&mipi_csi2_hw>;
status = "disabled";
};
mpp_srv: mpp-srv {
compatible = "rockchip,mpp-service";
rockchip,taskqueue-count = <4>;
@ -1861,8 +1867,8 @@
status = "disabled";
};
mipi_csi2: mipi-csi2@ffb10000 {
compatible = "rockchip,rv1126-mipi-csi2";
mipi_csi2_hw: mipi-csi2-hw@ffb10000 {
compatible = "rockchip,rv1126-mipi-csi2-hw";
reg = <0xffb10000 0x10000>;
reg-names = "csihost_regs";
interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
@ -2550,6 +2556,7 @@
snps,tx-fifo-resize;
snps,xhci-trb-ent-quirk;
snps,usb2-lpm-disable;
snps,parkmode-disable-hs-quirk;
status = "disabled";
};
};

325
arch/arm/configs/rk3308-aarch32-ia.config Normal file
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@ -0,0 +1,325 @@
CONFIG_BACKLIGHT_CLASS_DEVICE=y
CONFIG_CMA=y
CONFIG_DRM=y
# CONFIG_ETHERNET is not set
# CONFIG_ETHTOOL_NETLINK is not set
CONFIG_FB=y
# CONFIG_INPUT_KEYBOARD is not set
# CONFIG_INPUT_MISC is not set
CONFIG_INPUT_TOUCHSCREEN=y
CONFIG_KCMP=y
# CONFIG_MDIO_DEVICE is not set
# CONFIG_MEDIA_CEC_SUPPORT is not set
# CONFIG_MEDIA_SUPPORT is not set
CONFIG_MFD_RK618=y
# CONFIG_NEW_LEDS is not set
# CONFIG_PHYLIB is not set
# CONFIG_PWRSEQ_EMMC is not set
# CONFIG_RK_NANDC_NAND is not set
# CONFIG_SND_SOC_ROCKCHIP_SPDIF is not set
CONFIG_SYNC_FILE=y
# CONFIG_USB_SUPPORT is not set
# CONFIG_VHOST_MENU is not set
# CONFIG_VIRTIO_MENU is not set
# CONFIG_BACKLIGHT_ADP8860 is not set
# CONFIG_BACKLIGHT_ADP8870 is not set
# CONFIG_BACKLIGHT_ARCXCNN is not set
# CONFIG_BACKLIGHT_BD6107 is not set
# CONFIG_BACKLIGHT_GPIO is not set
# CONFIG_BACKLIGHT_KTD253 is not set
# CONFIG_BACKLIGHT_LM3630A is not set
# CONFIG_BACKLIGHT_LM3639 is not set
# CONFIG_BACKLIGHT_LP855X is not set
# CONFIG_BACKLIGHT_LV5207LP is not set
CONFIG_BACKLIGHT_PWM=y
# CONFIG_BACKLIGHT_QCOM_WLED is not set
CONFIG_CLK_RK618=y
CONFIG_CMA_ALIGNMENT=8
CONFIG_CMA_AREAS=7
# CONFIG_CMA_DEBUG is not set
# CONFIG_CMA_DEBUGFS is not set
# CONFIG_CMA_INACTIVE is not set
CONFIG_CMA_SIZE_MBYTES=16
# CONFIG_CMA_SIZE_SEL_MAX is not set
CONFIG_CMA_SIZE_SEL_MBYTES=y
# CONFIG_CMA_SIZE_SEL_MIN is not set
# CONFIG_CMA_SIZE_SEL_PERCENTAGE is not set
# CONFIG_CMA_SYSFS is not set
CONFIG_COMMON_CLK_ROCKCHIP_REGMAP=y
CONFIG_CONTIG_ALLOC=y
# CONFIG_DMABUF_MOVE_NOTIFY is not set
# CONFIG_DMABUF_SELFTESTS is not set
# CONFIG_DMABUF_SYSFS_STATS is not set
CONFIG_DMA_CMA=y
# CONFIG_DMA_FENCE_TRACE is not set
# CONFIG_DMA_PERNUMA_CMA is not set
CONFIG_DMA_SHARED_BUFFER=y
# CONFIG_DRM_ANALOGIX_ANX6345 is not set
# CONFIG_DRM_ANALOGIX_ANX78XX is not set
# CONFIG_DRM_ARCPGU is not set
# CONFIG_DRM_ARMADA is not set
CONFIG_DRM_BRIDGE=y
# CONFIG_DRM_CDNS_DSI is not set
# CONFIG_DRM_CDNS_MHDP8546 is not set
# CONFIG_DRM_CHRONTEL_CH7033 is not set
# CONFIG_DRM_DEBUG_DP_MST_TOPOLOGY_REFS is not set
# CONFIG_DRM_DEBUG_MM is not set
# CONFIG_DRM_DEBUG_SELFTEST is not set
# CONFIG_DRM_DISPLAY_CONNECTOR is not set
# CONFIG_DRM_DP is not set
# CONFIG_DRM_DP_AUX_CHARDEV is not set
# CONFIG_DRM_DP_CEC is not set
CONFIG_DRM_EDID=y
# CONFIG_DRM_ETNAVIV is not set
# CONFIG_DRM_EXYNOS is not set
CONFIG_DRM_FBDEV_EMULATION=y
# CONFIG_DRM_FBDEV_LEAK_PHYS_SMEM is not set
CONFIG_DRM_FBDEV_OVERALLOC=100
# CONFIG_DRM_FSL_DCU is not set
CONFIG_DRM_GEM_CMA_HELPER=y
# CONFIG_DRM_HDLCD is not set
# CONFIG_DRM_I2C_ADV7511 is not set
# CONFIG_DRM_I2C_CH7006 is not set
# CONFIG_DRM_I2C_NXP_TDA9950 is not set
# CONFIG_DRM_I2C_NXP_TDA998X is not set
# CONFIG_DRM_I2C_SIL164 is not set
CONFIG_DRM_IGNORE_IOTCL_PERMIT=y
# CONFIG_DRM_ITE_IT6161 is not set
CONFIG_DRM_KMS_FB_HELPER=y
CONFIG_DRM_KMS_HELPER=y
# CONFIG_DRM_KOMEDA is not set
# CONFIG_DRM_LEGACY is not set
# CONFIG_DRM_LIMA is not set
# CONFIG_DRM_LOAD_EDID_FIRMWARE is not set
# CONFIG_DRM_LONTIUM_LT9611 is not set
# CONFIG_DRM_LVDS_CODEC is not set
# CONFIG_DRM_MALI_DISPLAY is not set
# CONFIG_DRM_MAXIM_MAX96745 is not set
# CONFIG_DRM_MAXIM_MAX96755F is not set
# CONFIG_DRM_MCDE is not set
# CONFIG_DRM_MEGACHIPS_STDPXXXX_GE_B850V3_FW is not set
CONFIG_DRM_MIPI_DSI=y
# CONFIG_DRM_MXSFB is not set
# CONFIG_DRM_NWL_MIPI_DSI is not set
# CONFIG_DRM_NXP_PTN3460 is not set
# CONFIG_DRM_OMAP is not set
CONFIG_DRM_PANEL=y
# CONFIG_DRM_PANEL_ARM_VERSATILE is not set
# CONFIG_DRM_PANEL_ASUS_Z00T_TM5P5_NT35596 is not set
# CONFIG_DRM_PANEL_BOE_HIMAX8279D is not set
# CONFIG_DRM_PANEL_BOE_TV101WUM_NL6 is not set
CONFIG_DRM_PANEL_BRIDGE=y
# CONFIG_DRM_PANEL_ELIDA_KD35T133 is not set
# CONFIG_DRM_PANEL_FEIXIN_K101_IM2BA02 is not set
# CONFIG_DRM_PANEL_FEIYANG_FY07024DI26A30D is not set
# CONFIG_DRM_PANEL_ILITEK_IL9322 is not set
# CONFIG_DRM_PANEL_ILITEK_ILI9881C is not set
# CONFIG_DRM_PANEL_INNOLUX_P079ZCA is not set
# CONFIG_DRM_PANEL_JDI_LT070ME05000 is not set
# CONFIG_DRM_PANEL_KINGDISPLAY_KD097D04 is not set
# CONFIG_DRM_PANEL_LEADTEK_LTK050H3146W is not set
# CONFIG_DRM_PANEL_LEADTEK_LTK500HD1829 is not set
# CONFIG_DRM_PANEL_LG_LB035Q02 is not set
# CONFIG_DRM_PANEL_LG_LG4573 is not set
# CONFIG_DRM_PANEL_LVDS is not set
# CONFIG_DRM_PANEL_MANTIX_MLAF057WE51 is not set
# CONFIG_DRM_PANEL_MAXIM_MAX96752F is not set
# CONFIG_DRM_PANEL_MAXIM_MAX96772 is not set
# CONFIG_DRM_PANEL_NEC_NL8048HL11 is not set
# CONFIG_DRM_PANEL_NOVATEK_NT35510 is not set
# CONFIG_DRM_PANEL_NOVATEK_NT39016 is not set
# CONFIG_DRM_PANEL_OLIMEX_LCD_OLINUXINO is not set
CONFIG_DRM_PANEL_ORIENTATION_QUIRKS=y
# CONFIG_DRM_PANEL_ORISETECH_OTM8009A is not set
# CONFIG_DRM_PANEL_OSD_OSD101T2587_53TS is not set
# CONFIG_DRM_PANEL_PANASONIC_VVX10F034N00 is not set
# CONFIG_DRM_PANEL_RASPBERRYPI_TOUCHSCREEN is not set
# CONFIG_DRM_PANEL_RAYDIUM_RM67191 is not set
# CONFIG_DRM_PANEL_RAYDIUM_RM68200 is not set
# CONFIG_DRM_PANEL_RONBO_RB070D30 is not set
# CONFIG_DRM_PANEL_SAMSUNG_LD9040 is not set
# CONFIG_DRM_PANEL_SAMSUNG_S6D16D0 is not set
# CONFIG_DRM_PANEL_SAMSUNG_S6E3HA2 is not set
# CONFIG_DRM_PANEL_SAMSUNG_S6E63J0X03 is not set
# CONFIG_DRM_PANEL_SAMSUNG_S6E63M0 is not set
# CONFIG_DRM_PANEL_SAMSUNG_S6E88A0_AMS452EF01 is not set
# CONFIG_DRM_PANEL_SAMSUNG_S6E8AA0 is not set
# CONFIG_DRM_PANEL_SEIKO_43WVF1G is not set
# CONFIG_DRM_PANEL_SHARP_LQ101R1SX01 is not set
# CONFIG_DRM_PANEL_SHARP_LS037V7DW01 is not set
# CONFIG_DRM_PANEL_SHARP_LS043T1LE01 is not set
CONFIG_DRM_PANEL_SIMPLE=y
# CONFIG_DRM_PANEL_SITRONIX_ST7701 is not set
# CONFIG_DRM_PANEL_SITRONIX_ST7703 is not set
# CONFIG_DRM_PANEL_SITRONIX_ST7789V is not set
# CONFIG_DRM_PANEL_SONY_ACX424AKP is not set
# CONFIG_DRM_PANEL_SONY_ACX565AKM is not set
# CONFIG_DRM_PANEL_TPO_TD028TTEC1 is not set
# CONFIG_DRM_PANEL_TPO_TD043MTEA1 is not set
# CONFIG_DRM_PANEL_TPO_TPG110 is not set
# CONFIG_DRM_PANEL_TRULY_NT35597_WQXGA is not set
# CONFIG_DRM_PANEL_VISIONOX_RM69299 is not set
# CONFIG_DRM_PANEL_XINPENG_XPP055C272 is not set
# CONFIG_DRM_PANFROST is not set
# CONFIG_DRM_PARADE_PS8622 is not set
# CONFIG_DRM_PARADE_PS8640 is not set
# CONFIG_DRM_PL111 is not set
# CONFIG_DRM_RCAR_DW_HDMI is not set
# CONFIG_DRM_RCAR_LVDS is not set
# CONFIG_DRM_RK1000_TVE is not set
CONFIG_DRM_ROCKCHIP=y
CONFIG_DRM_ROCKCHIP_RK618=y
# CONFIG_DRM_ROCKCHIP_VVOP is not set
# CONFIG_DRM_ROHM_BU18XL82 is not set
# CONFIG_DRM_SII902X is not set
# CONFIG_DRM_SII9234 is not set
# CONFIG_DRM_SIL_SII8620 is not set
# CONFIG_DRM_SIMPLE_BRIDGE is not set
# CONFIG_DRM_STI is not set
# CONFIG_DRM_STM is not set
# CONFIG_DRM_THINE_THC63LVD1024 is not set
# CONFIG_DRM_TIDSS is not set
# CONFIG_DRM_TILCDC is not set
# CONFIG_DRM_TI_SN65DSI86 is not set
# CONFIG_DRM_TI_TFP410 is not set
# CONFIG_DRM_TI_TPD12S015 is not set
# CONFIG_DRM_TOSHIBA_TC358762 is not set
# CONFIG_DRM_TOSHIBA_TC358764 is not set
# CONFIG_DRM_TOSHIBA_TC358767 is not set
# CONFIG_DRM_TOSHIBA_TC358768 is not set
# CONFIG_DRM_TOSHIBA_TC358775 is not set
# CONFIG_DRM_TVE200 is not set
# CONFIG_DRM_VGEM is not set
# CONFIG_DRM_VKMS is not set
# CONFIG_FB_ARMCLCD is not set
CONFIG_FB_CFB_COPYAREA=y
CONFIG_FB_CFB_FILLRECT=y
CONFIG_FB_CFB_IMAGEBLIT=y
CONFIG_FB_CMDLINE=y
CONFIG_FB_DEFERRED_IO=y
# CONFIG_FB_FOREIGN_ENDIAN is not set
# CONFIG_FB_IBM_GXT4500 is not set
# CONFIG_FB_METRONOME is not set
# CONFIG_FB_MODE_HELPERS is not set
CONFIG_FB_NOTIFY=y
# CONFIG_FB_OPENCORES is not set
# CONFIG_FB_S1D13XXX is not set
# CONFIG_FB_SIMPLE is not set
# CONFIG_FB_SSD1307 is not set
CONFIG_FB_SYS_COPYAREA=y
CONFIG_FB_SYS_FILLRECT=y
CONFIG_FB_SYS_FOPS=y
CONFIG_FB_SYS_IMAGEBLIT=y
# CONFIG_FB_TFT is not set
# CONFIG_FB_TILEBLITTING is not set
# CONFIG_FB_VIRTUAL is not set
# CONFIG_FIRMWARE_EDID is not set
CONFIG_HDMI=y
CONFIG_I2C_ALGOBIT=y
# CONFIG_LOGO is not set
# CONFIG_LT7911D_FB_NOTIFIER is not set
CONFIG_MEMORY_ISOLATION=y
CONFIG_MFD_CORE=y
CONFIG_MIGRATION=y
CONFIG_REGMAP_IRQ=y
# CONFIG_REGULATOR_RASPBERRYPI_TOUCHSCREEN_ATTINY is not set
# CONFIG_RK_CMA_PROCFS is not set
# CONFIG_RK_DMABUF_PROCFS is not set
# CONFIG_ROCKCHIP_ANALOGIX_DP is not set
# CONFIG_ROCKCHIP_CDN_DP is not set
# CONFIG_ROCKCHIP_DRM_DEBUG is not set
# CONFIG_ROCKCHIP_DRM_DIRECT_SHOW is not set
# CONFIG_ROCKCHIP_DRM_TVE is not set
# CONFIG_ROCKCHIP_DW_DP is not set
# CONFIG_ROCKCHIP_DW_HDCP2 is not set
# CONFIG_ROCKCHIP_DW_HDMI is not set
# CONFIG_ROCKCHIP_DW_MIPI_DSI is not set
# CONFIG_ROCKCHIP_INNO_HDMI is not set
# CONFIG_ROCKCHIP_LVDS is not set
CONFIG_ROCKCHIP_RGB=y
# CONFIG_ROCKCHIP_RK3066_HDMI is not set
# CONFIG_ROCKCHIP_RKNPU is not set
# CONFIG_ROCKCHIP_SERDES_DRM_PANEL is not set
# CONFIG_ROCKCHIP_VCONN is not set
CONFIG_ROCKCHIP_VOP=y
# CONFIG_ROCKCHIP_VOP2 is not set
# CONFIG_SW_SYNC is not set
# CONFIG_TINYDRM_HX8357D is not set
# CONFIG_TINYDRM_ILI9225 is not set
# CONFIG_TINYDRM_ILI9341 is not set
# CONFIG_TINYDRM_ILI9486 is not set
# CONFIG_TINYDRM_MI0283QT is not set
# CONFIG_TINYDRM_REPAPER is not set
# CONFIG_TINYDRM_ST7586 is not set
# CONFIG_TINYDRM_ST7735R is not set
# CONFIG_TOUCHSCREEN_AD7877 is not set
# CONFIG_TOUCHSCREEN_AD7879 is not set
# CONFIG_TOUCHSCREEN_ADC is not set
# CONFIG_TOUCHSCREEN_ADS7846 is not set
# CONFIG_TOUCHSCREEN_AR1021_I2C is not set
# CONFIG_TOUCHSCREEN_ATMEL_MXT is not set
# CONFIG_TOUCHSCREEN_AUO_PIXCIR is not set
# CONFIG_TOUCHSCREEN_BU21013 is not set
# CONFIG_TOUCHSCREEN_BU21029 is not set
# CONFIG_TOUCHSCREEN_CHIPONE_ICN8318 is not set
# CONFIG_TOUCHSCREEN_CY8CTMA140 is not set
# CONFIG_TOUCHSCREEN_CY8CTMG110 is not set
# CONFIG_TOUCHSCREEN_CYTTSP4_CORE is not set
# CONFIG_TOUCHSCREEN_CYTTSP_CORE is not set
# CONFIG_TOUCHSCREEN_DYNAPRO is not set
# CONFIG_TOUCHSCREEN_EDT_FT5X06 is not set
# CONFIG_TOUCHSCREEN_EETI is not set
# CONFIG_TOUCHSCREEN_EGALAX is not set
# CONFIG_TOUCHSCREEN_EGALAX_SERIAL is not set
# CONFIG_TOUCHSCREEN_EKTF2127 is not set
# CONFIG_TOUCHSCREEN_ELAN is not set
# CONFIG_TOUCHSCREEN_ELAN5515 is not set
# CONFIG_TOUCHSCREEN_ELO is not set
# CONFIG_TOUCHSCREEN_EXC3000 is not set
# CONFIG_TOUCHSCREEN_FTS is not set
# CONFIG_TOUCHSCREEN_FUJITSU is not set
# CONFIG_TOUCHSCREEN_GOODIX is not set
# CONFIG_TOUCHSCREEN_GSL3673 is not set
# CONFIG_TOUCHSCREEN_GSL3673_800X1280 is not set
# CONFIG_TOUCHSCREEN_GSLX680_PAD is not set
CONFIG_TOUCHSCREEN_GT1X=y
# CONFIG_TOUCHSCREEN_GUNZE is not set
# CONFIG_TOUCHSCREEN_HAMPSHIRE is not set
# CONFIG_TOUCHSCREEN_HIDEEP is not set
# CONFIG_TOUCHSCREEN_ILI210X is not set
# CONFIG_TOUCHSCREEN_IMX6UL_TSC is not set
# CONFIG_TOUCHSCREEN_INEXIO is not set
# CONFIG_TOUCHSCREEN_IQS5XX is not set
# CONFIG_TOUCHSCREEN_MAX11801 is not set
# CONFIG_TOUCHSCREEN_MCS5000 is not set
# CONFIG_TOUCHSCREEN_MELFAS_MIP4 is not set
# CONFIG_TOUCHSCREEN_MK712 is not set
# CONFIG_TOUCHSCREEN_MMS114 is not set
# CONFIG_TOUCHSCREEN_MTOUCH is not set
# CONFIG_TOUCHSCREEN_PENMOUNT is not set
# CONFIG_TOUCHSCREEN_PIXCIR is not set
CONFIG_TOUCHSCREEN_PROPERTIES=y
# CONFIG_TOUCHSCREEN_RM_TS is not set
# CONFIG_TOUCHSCREEN_ROHM_BU21023 is not set
# CONFIG_TOUCHSCREEN_S6SY761 is not set
# CONFIG_TOUCHSCREEN_SILEAD is not set
# CONFIG_TOUCHSCREEN_SIS_I2C is not set
# CONFIG_TOUCHSCREEN_ST1232 is not set
# CONFIG_TOUCHSCREEN_SURFACE3_SPI is not set
# CONFIG_TOUCHSCREEN_SX8654 is not set
# CONFIG_TOUCHSCREEN_TOUCHIT213 is not set
# CONFIG_TOUCHSCREEN_TOUCHRIGHT is not set
# CONFIG_TOUCHSCREEN_TOUCHWIN is not set
# CONFIG_TOUCHSCREEN_TPS6507X is not set
# CONFIG_TOUCHSCREEN_TSC2004 is not set
# CONFIG_TOUCHSCREEN_TSC2005 is not set
# CONFIG_TOUCHSCREEN_TSC2007 is not set
# CONFIG_TOUCHSCREEN_TSC_SERIO is not set
# CONFIG_TOUCHSCREEN_WACOM_I2C is not set
# CONFIG_TOUCHSCREEN_WACOM_W8001 is not set
# CONFIG_TOUCHSCREEN_WDT87XX_I2C is not set
# CONFIG_TOUCHSCREEN_ZET6223 is not set
# CONFIG_TOUCHSCREEN_ZFORCE is not set
# CONFIG_TOUCHSCREEN_ZINITIX is not set
# CONFIG_UDMABUF is not set
CONFIG_VIDEOMODE_HELPERS=y

313
arch/arm/configs/rk3308bs_aarch32_mipi_display.config Normal file
View File

@ -0,0 +1,313 @@
CONFIG_BACKLIGHT_CLASS_DEVICE=y
CONFIG_CMA=y
CONFIG_DRM=y
CONFIG_FB=y
CONFIG_INPUT_TOUCHSCREEN=y
CONFIG_KCMP=y
CONFIG_MFD_RK618=y
CONFIG_SYNC_FILE=y
# CONFIG_BACKLIGHT_ADP8860 is not set
# CONFIG_BACKLIGHT_ADP8870 is not set
# CONFIG_BACKLIGHT_ARCXCNN is not set
# CONFIG_BACKLIGHT_BD6107 is not set
# CONFIG_BACKLIGHT_GPIO is not set
# CONFIG_BACKLIGHT_KTD253 is not set
# CONFIG_BACKLIGHT_LED is not set
# CONFIG_BACKLIGHT_LM3630A is not set
# CONFIG_BACKLIGHT_LM3639 is not set
# CONFIG_BACKLIGHT_LP855X is not set
# CONFIG_BACKLIGHT_LV5207LP is not set
CONFIG_BACKLIGHT_PWM=y
# CONFIG_BACKLIGHT_QCOM_WLED is not set
CONFIG_CLK_RK618=y
CONFIG_CMA_ALIGNMENT=8
CONFIG_CMA_AREAS=7
# CONFIG_CMA_DEBUG is not set
# CONFIG_CMA_DEBUGFS is not set
# CONFIG_CMA_INACTIVE is not set
CONFIG_CMA_SIZE_MBYTES=16
# CONFIG_CMA_SIZE_SEL_MAX is not set
CONFIG_CMA_SIZE_SEL_MBYTES=y
# CONFIG_CMA_SIZE_SEL_MIN is not set
# CONFIG_CMA_SIZE_SEL_PERCENTAGE is not set
# CONFIG_CMA_SYSFS is not set
CONFIG_COMMON_CLK_ROCKCHIP_REGMAP=y
CONFIG_CONTIG_ALLOC=y
# CONFIG_DMABUF_MOVE_NOTIFY is not set
# CONFIG_DMABUF_SELFTESTS is not set
# CONFIG_DMABUF_SYSFS_STATS is not set
CONFIG_DMA_CMA=y
# CONFIG_DMA_FENCE_TRACE is not set
# CONFIG_DMA_PERNUMA_CMA is not set
CONFIG_DMA_SHARED_BUFFER=y
# CONFIG_DRM_ANALOGIX_ANX6345 is not set
# CONFIG_DRM_ANALOGIX_ANX78XX is not set
# CONFIG_DRM_ARCPGU is not set
# CONFIG_DRM_ARMADA is not set
CONFIG_DRM_BRIDGE=y
# CONFIG_DRM_CDNS_DSI is not set
# CONFIG_DRM_CDNS_MHDP8546 is not set
# CONFIG_DRM_CHRONTEL_CH7033 is not set
# CONFIG_DRM_DEBUG_DP_MST_TOPOLOGY_REFS is not set
# CONFIG_DRM_DEBUG_MM is not set
# CONFIG_DRM_DEBUG_SELFTEST is not set
# CONFIG_DRM_DISPLAY_CONNECTOR is not set
CONFIG_DRM_DP=y
# CONFIG_DRM_DP_AUX_CHARDEV is not set
# CONFIG_DRM_DP_CEC is not set
CONFIG_DRM_EDID=y
# CONFIG_DRM_ETNAVIV is not set
# CONFIG_DRM_EXYNOS is not set
CONFIG_DRM_FBDEV_EMULATION=y
# CONFIG_DRM_FBDEV_LEAK_PHYS_SMEM is not set
CONFIG_DRM_FBDEV_OVERALLOC=100
# CONFIG_DRM_FSL_DCU is not set
CONFIG_DRM_GEM_CMA_HELPER=y
# CONFIG_DRM_HDLCD is not set
# CONFIG_DRM_I2C_ADV7511 is not set
# CONFIG_DRM_I2C_CH7006 is not set
# CONFIG_DRM_I2C_NXP_TDA9950 is not set
# CONFIG_DRM_I2C_NXP_TDA998X is not set
# CONFIG_DRM_I2C_SIL164 is not set
CONFIG_DRM_IGNORE_IOTCL_PERMIT=y
# CONFIG_DRM_ITE_IT6161 is not set
CONFIG_DRM_KMS_FB_HELPER=y
CONFIG_DRM_KMS_HELPER=y
# CONFIG_DRM_KOMEDA is not set
# CONFIG_DRM_LEGACY is not set
# CONFIG_DRM_LIMA is not set
# CONFIG_DRM_LOAD_EDID_FIRMWARE is not set
# CONFIG_DRM_LONTIUM_LT9611 is not set
# CONFIG_DRM_LVDS_CODEC is not set
# CONFIG_DRM_MALI_DISPLAY is not set
# CONFIG_DRM_MAXIM_MAX96745 is not set
# CONFIG_DRM_MAXIM_MAX96755F is not set
# CONFIG_DRM_MCDE is not set
# CONFIG_DRM_MEGACHIPS_STDPXXXX_GE_B850V3_FW is not set
CONFIG_DRM_MIPI_DSI=y
# CONFIG_DRM_MXSFB is not set
# CONFIG_DRM_NWL_MIPI_DSI is not set
# CONFIG_DRM_NXP_PTN3460 is not set
# CONFIG_DRM_OMAP is not set
CONFIG_DRM_PANEL=y
# CONFIG_DRM_PANEL_ARM_VERSATILE is not set
# CONFIG_DRM_PANEL_ASUS_Z00T_TM5P5_NT35596 is not set
# CONFIG_DRM_PANEL_BOE_HIMAX8279D is not set
# CONFIG_DRM_PANEL_BOE_TV101WUM_NL6 is not set
CONFIG_DRM_PANEL_BRIDGE=y
# CONFIG_DRM_PANEL_ELIDA_KD35T133 is not set
# CONFIG_DRM_PANEL_FEIXIN_K101_IM2BA02 is not set
# CONFIG_DRM_PANEL_FEIYANG_FY07024DI26A30D is not set
# CONFIG_DRM_PANEL_ILITEK_IL9322 is not set
# CONFIG_DRM_PANEL_ILITEK_ILI9881C is not set
# CONFIG_DRM_PANEL_INNOLUX_P079ZCA is not set
# CONFIG_DRM_PANEL_JDI_LT070ME05000 is not set
# CONFIG_DRM_PANEL_KINGDISPLAY_KD097D04 is not set
# CONFIG_DRM_PANEL_LEADTEK_LTK050H3146W is not set
# CONFIG_DRM_PANEL_LEADTEK_LTK500HD1829 is not set
# CONFIG_DRM_PANEL_LG_LB035Q02 is not set
# CONFIG_DRM_PANEL_LG_LG4573 is not set
# CONFIG_DRM_PANEL_LVDS is not set
# CONFIG_DRM_PANEL_MANTIX_MLAF057WE51 is not set
# CONFIG_DRM_PANEL_MAXIM_MAX96752F is not set
# CONFIG_DRM_PANEL_MAXIM_MAX96772 is not set
# CONFIG_DRM_PANEL_NEC_NL8048HL11 is not set
# CONFIG_DRM_PANEL_NOVATEK_NT35510 is not set
# CONFIG_DRM_PANEL_NOVATEK_NT39016 is not set
# CONFIG_DRM_PANEL_OLIMEX_LCD_OLINUXINO is not set
CONFIG_DRM_PANEL_ORIENTATION_QUIRKS=y
# CONFIG_DRM_PANEL_ORISETECH_OTM8009A is not set
# CONFIG_DRM_PANEL_OSD_OSD101T2587_53TS is not set
# CONFIG_DRM_PANEL_PANASONIC_VVX10F034N00 is not set
# CONFIG_DRM_PANEL_RASPBERRYPI_TOUCHSCREEN is not set
# CONFIG_DRM_PANEL_RAYDIUM_RM67191 is not set
# CONFIG_DRM_PANEL_RAYDIUM_RM68200 is not set
# CONFIG_DRM_PANEL_RONBO_RB070D30 is not set
# CONFIG_DRM_PANEL_SAMSUNG_LD9040 is not set
# CONFIG_DRM_PANEL_SAMSUNG_S6D16D0 is not set
# CONFIG_DRM_PANEL_SAMSUNG_S6E3HA2 is not set
# CONFIG_DRM_PANEL_SAMSUNG_S6E63J0X03 is not set
# CONFIG_DRM_PANEL_SAMSUNG_S6E63M0 is not set
# CONFIG_DRM_PANEL_SAMSUNG_S6E88A0_AMS452EF01 is not set
# CONFIG_DRM_PANEL_SAMSUNG_S6E8AA0 is not set
# CONFIG_DRM_PANEL_SEIKO_43WVF1G is not set
# CONFIG_DRM_PANEL_SHARP_LQ101R1SX01 is not set
# CONFIG_DRM_PANEL_SHARP_LS037V7DW01 is not set
# CONFIG_DRM_PANEL_SHARP_LS043T1LE01 is not set
CONFIG_DRM_PANEL_SIMPLE=y
# CONFIG_DRM_PANEL_SITRONIX_ST7701 is not set
# CONFIG_DRM_PANEL_SITRONIX_ST7703 is not set
# CONFIG_DRM_PANEL_SITRONIX_ST7789V is not set
# CONFIG_DRM_PANEL_SONY_ACX424AKP is not set
# CONFIG_DRM_PANEL_SONY_ACX565AKM is not set
# CONFIG_DRM_PANEL_TPO_TD028TTEC1 is not set
# CONFIG_DRM_PANEL_TPO_TD043MTEA1 is not set
# CONFIG_DRM_PANEL_TPO_TPG110 is not set
# CONFIG_DRM_PANEL_TRULY_NT35597_WQXGA is not set
# CONFIG_DRM_PANEL_VISIONOX_RM69299 is not set
# CONFIG_DRM_PANEL_XINPENG_XPP055C272 is not set
# CONFIG_DRM_PANFROST is not set
# CONFIG_DRM_PARADE_PS8622 is not set
# CONFIG_DRM_PARADE_PS8640 is not set
# CONFIG_DRM_PL111 is not set
# CONFIG_DRM_RCAR_DW_HDMI is not set
# CONFIG_DRM_RCAR_LVDS is not set
# CONFIG_DRM_RK1000_TVE is not set
CONFIG_DRM_ROCKCHIP=y
CONFIG_DRM_ROCKCHIP_RK618=y
# CONFIG_DRM_ROCKCHIP_VVOP is not set
# CONFIG_DRM_ROHM_BU18XL82 is not set
# CONFIG_DRM_SII902X is not set
# CONFIG_DRM_SII9234 is not set
# CONFIG_DRM_SIL_SII8620 is not set
# CONFIG_DRM_SIMPLE_BRIDGE is not set
# CONFIG_DRM_STI is not set
# CONFIG_DRM_STM is not set
# CONFIG_DRM_THINE_THC63LVD1024 is not set
# CONFIG_DRM_TIDSS is not set
# CONFIG_DRM_TILCDC is not set
# CONFIG_DRM_TI_SN65DSI86 is not set
# CONFIG_DRM_TI_TFP410 is not set
# CONFIG_DRM_TI_TPD12S015 is not set
# CONFIG_DRM_TOSHIBA_TC358762 is not set
# CONFIG_DRM_TOSHIBA_TC358764 is not set
# CONFIG_DRM_TOSHIBA_TC358767 is not set
# CONFIG_DRM_TOSHIBA_TC358768 is not set
# CONFIG_DRM_TOSHIBA_TC358775 is not set
# CONFIG_DRM_TVE200 is not set
# CONFIG_DRM_VGEM is not set
# CONFIG_DRM_VKMS is not set
# CONFIG_FB_ARMCLCD is not set
CONFIG_FB_CFB_COPYAREA=y
CONFIG_FB_CFB_FILLRECT=y
CONFIG_FB_CFB_IMAGEBLIT=y
CONFIG_FB_CMDLINE=y
CONFIG_FB_DEFERRED_IO=y
# CONFIG_FB_FOREIGN_ENDIAN is not set
# CONFIG_FB_IBM_GXT4500 is not set
# CONFIG_FB_METRONOME is not set
# CONFIG_FB_MODE_HELPERS is not set
CONFIG_FB_NOTIFY=y
# CONFIG_FB_OPENCORES is not set
# CONFIG_FB_S1D13XXX is not set
# CONFIG_FB_SIMPLE is not set
# CONFIG_FB_SSD1307 is not set
CONFIG_FB_SYS_COPYAREA=y
CONFIG_FB_SYS_FILLRECT=y
CONFIG_FB_SYS_FOPS=y
CONFIG_FB_SYS_IMAGEBLIT=y
# CONFIG_FB_TFT is not set
# CONFIG_FB_TILEBLITTING is not set
# CONFIG_FB_VIRTUAL is not set
# CONFIG_FIRMWARE_EDID is not set
CONFIG_HDMI=y
CONFIG_I2C_ALGOBIT=y
# CONFIG_LOGO is not set
# CONFIG_LT7911D_FB_NOTIFIER is not set
CONFIG_MEMORY_ISOLATION=y
CONFIG_MFD_CORE=y
CONFIG_MIGRATION=y
CONFIG_REGMAP_IRQ=y
# CONFIG_REGULATOR_RASPBERRYPI_TOUCHSCREEN_ATTINY is not set
# CONFIG_RK_CMA_PROCFS is not set
# CONFIG_RK_DMABUF_PROCFS is not set
# CONFIG_ROCKCHIP_ANALOGIX_DP is not set
# CONFIG_ROCKCHIP_CDN_DP is not set
# CONFIG_ROCKCHIP_DRM_DEBUG is not set
# CONFIG_ROCKCHIP_DRM_DIRECT_SHOW is not set
# CONFIG_ROCKCHIP_DRM_TVE is not set
# CONFIG_ROCKCHIP_DW_DP is not set
# CONFIG_ROCKCHIP_DW_HDCP2 is not set
# CONFIG_ROCKCHIP_DW_HDMI is not set
# CONFIG_ROCKCHIP_DW_MIPI_DSI is not set
# CONFIG_ROCKCHIP_INNO_HDMI is not set
# CONFIG_ROCKCHIP_LVDS is not set
CONFIG_ROCKCHIP_RGB=y
# CONFIG_ROCKCHIP_RK3066_HDMI is not set
# CONFIG_ROCKCHIP_RKNPU is not set
# CONFIG_ROCKCHIP_VCONN is not set
CONFIG_ROCKCHIP_VOP=y
# CONFIG_ROCKCHIP_VOP2 is not set
# CONFIG_SW_SYNC is not set
# CONFIG_TINYDRM_HX8357D is not set
# CONFIG_TINYDRM_ILI9225 is not set
# CONFIG_TINYDRM_ILI9341 is not set
# CONFIG_TINYDRM_ILI9486 is not set
# CONFIG_TINYDRM_MI0283QT is not set
# CONFIG_TINYDRM_REPAPER is not set
# CONFIG_TINYDRM_ST7586 is not set
# CONFIG_TINYDRM_ST7735R is not set
# CONFIG_TOUCHSCREEN_AD7877 is not set
# CONFIG_TOUCHSCREEN_AD7879 is not set
# CONFIG_TOUCHSCREEN_ADC is not set
# CONFIG_TOUCHSCREEN_ADS7846 is not set
# CONFIG_TOUCHSCREEN_AR1021_I2C is not set
# CONFIG_TOUCHSCREEN_ATMEL_MXT is not set
# CONFIG_TOUCHSCREEN_AUO_PIXCIR is not set
# CONFIG_TOUCHSCREEN_BU21013 is not set
# CONFIG_TOUCHSCREEN_BU21029 is not set
# CONFIG_TOUCHSCREEN_CHIPONE_ICN8318 is not set
# CONFIG_TOUCHSCREEN_CY8CTMA140 is not set
# CONFIG_TOUCHSCREEN_CY8CTMG110 is not set
# CONFIG_TOUCHSCREEN_CYTTSP4_CORE is not set
# CONFIG_TOUCHSCREEN_CYTTSP_CORE is not set
# CONFIG_TOUCHSCREEN_DYNAPRO is not set
# CONFIG_TOUCHSCREEN_EDT_FT5X06 is not set
# CONFIG_TOUCHSCREEN_EETI is not set
# CONFIG_TOUCHSCREEN_EGALAX is not set
# CONFIG_TOUCHSCREEN_EGALAX_SERIAL is not set
# CONFIG_TOUCHSCREEN_EKTF2127 is not set
# CONFIG_TOUCHSCREEN_ELAN is not set
# CONFIG_TOUCHSCREEN_ELAN5515 is not set
# CONFIG_TOUCHSCREEN_ELO is not set
# CONFIG_TOUCHSCREEN_EXC3000 is not set
# CONFIG_TOUCHSCREEN_FTS is not set
# CONFIG_TOUCHSCREEN_FUJITSU is not set
# CONFIG_TOUCHSCREEN_GOODIX is not set
# CONFIG_TOUCHSCREEN_GSL3673 is not set
# CONFIG_TOUCHSCREEN_GSL3673_800X1280 is not set
# CONFIG_TOUCHSCREEN_GSLX680_PAD is not set
CONFIG_TOUCHSCREEN_GT1X=y
# CONFIG_TOUCHSCREEN_GUNZE is not set
# CONFIG_TOUCHSCREEN_HAMPSHIRE is not set
# CONFIG_TOUCHSCREEN_HIDEEP is not set
# CONFIG_TOUCHSCREEN_ILI210X is not set
# CONFIG_TOUCHSCREEN_IMX6UL_TSC is not set
# CONFIG_TOUCHSCREEN_INEXIO is not set
# CONFIG_TOUCHSCREEN_IQS5XX is not set
# CONFIG_TOUCHSCREEN_MAX11801 is not set
# CONFIG_TOUCHSCREEN_MCS5000 is not set
# CONFIG_TOUCHSCREEN_MELFAS_MIP4 is not set
# CONFIG_TOUCHSCREEN_MK712 is not set
# CONFIG_TOUCHSCREEN_MMS114 is not set
# CONFIG_TOUCHSCREEN_MTOUCH is not set
# CONFIG_TOUCHSCREEN_PENMOUNT is not set
# CONFIG_TOUCHSCREEN_PIXCIR is not set
CONFIG_TOUCHSCREEN_PROPERTIES=y
# CONFIG_TOUCHSCREEN_RM_TS is not set
# CONFIG_TOUCHSCREEN_ROHM_BU21023 is not set
# CONFIG_TOUCHSCREEN_S6SY761 is not set
# CONFIG_TOUCHSCREEN_SILEAD is not set
# CONFIG_TOUCHSCREEN_SIS_I2C is not set
# CONFIG_TOUCHSCREEN_ST1232 is not set
# CONFIG_TOUCHSCREEN_STMFTS is not set
# CONFIG_TOUCHSCREEN_SURFACE3_SPI is not set
# CONFIG_TOUCHSCREEN_SX8654 is not set
# CONFIG_TOUCHSCREEN_TOUCHIT213 is not set
# CONFIG_TOUCHSCREEN_TOUCHRIGHT is not set
# CONFIG_TOUCHSCREEN_TOUCHWIN is not set
# CONFIG_TOUCHSCREEN_TPS6507X is not set
# CONFIG_TOUCHSCREEN_TSC2004 is not set
# CONFIG_TOUCHSCREEN_TSC2005 is not set
# CONFIG_TOUCHSCREEN_TSC2007 is not set
# CONFIG_TOUCHSCREEN_TSC_SERIO is not set
# CONFIG_TOUCHSCREEN_USB_COMPOSITE is not set
# CONFIG_TOUCHSCREEN_WACOM_I2C is not set
# CONFIG_TOUCHSCREEN_WACOM_W8001 is not set
# CONFIG_TOUCHSCREEN_WDT87XX_I2C is not set
# CONFIG_TOUCHSCREEN_ZET6223 is not set
# CONFIG_TOUCHSCREEN_ZFORCE is not set
# CONFIG_TOUCHSCREEN_ZINITIX is not set
# CONFIG_UDMABUF is not set
CONFIG_VIDEOMODE_HELPERS=y
# CONFIG_VIRTIO_DMA_SHARED_BUFFER is not set

13
arch/arm/configs/rockchip_linux_defconfig
View File

@ -168,7 +168,6 @@ CONFIG_MD=y
CONFIG_BLK_DEV_DM=y
CONFIG_DM_CRYPT=y
CONFIG_DM_THIN_PROVISIONING=y
CONFIG_DM_VERITY=y
CONFIG_NETDEVICES=y
CONFIG_TUN=y
CONFIG_VETH=y
@ -334,7 +333,9 @@ CONFIG_SND_SOC_ROCKCHIP=y
CONFIG_SND_SOC_ROCKCHIP_SAI=y
CONFIG_SND_SOC_ROCKCHIP_SPDIF=y
CONFIG_SND_SOC_ROCKCHIP_MAX98090=y
CONFIG_SND_SOC_ROCKCHIP_MULTICODECS=y
CONFIG_SND_SOC_ROCKCHIP_RT5645=y
CONFIG_SND_SOC_ROCKCHIP_HDMI=y
CONFIG_SND_SOC_ES8311=y
CONFIG_SND_SOC_ES8323=y
CONFIG_SND_SOC_ES8396=y
@ -414,11 +415,6 @@ CONFIG_DMADEVICES=y
CONFIG_PL330_DMA=y
CONFIG_STAGING=y
CONFIG_ASHMEM=y
CONFIG_FIQ_DEBUGGER=y
CONFIG_FIQ_DEBUGGER_NO_SLEEP=y
CONFIG_FIQ_DEBUGGER_CONSOLE=y
CONFIG_FIQ_DEBUGGER_CONSOLE_DEFAULT_ENABLE=y
CONFIG_FIQ_DEBUGGER_TRUST_ZONE=y
CONFIG_COMMON_CLK_RK808=y
CONFIG_ROCKCHIP_IOMMU=y
CONFIG_CPU_RK312X=y
@ -437,6 +433,11 @@ CONFIG_ROCKCHIP_PVTM=y
CONFIG_ROCKCHIP_SUSPEND_MODE=y
CONFIG_ROCKCHIP_SYSTEM_MONITOR=y
CONFIG_ROCKCHIP_VENDOR_STORAGE_UPDATE_LOADER=y
CONFIG_FIQ_DEBUGGER=y
CONFIG_FIQ_DEBUGGER_NO_SLEEP=y
CONFIG_FIQ_DEBUGGER_CONSOLE=y
CONFIG_FIQ_DEBUGGER_CONSOLE_DEFAULT_ENABLE=y
CONFIG_FIQ_DEBUGGER_TRUST_ZONE=y
CONFIG_PM_DEVFREQ=y
CONFIG_DEVFREQ_GOV_PERFORMANCE=y
CONFIG_DEVFREQ_GOV_POWERSAVE=y

5
arch/arm/configs/rv1106-smart-door.config
View File

@ -29,6 +29,8 @@ CONFIG_SPI=y
CONFIG_USB_SUPPORT=y
CONFIG_VIDEO_GC2093=y
CONFIG_VIDEO_SC035GS=y
CONFIG_VIDEO_SC230AI=y
CONFIG_VIDEO_SC301IOT=y
CONFIG_VIDEO_SC3338=y
CONFIG_WIRELESS=y
CONFIG_WLAN=y
@ -233,6 +235,7 @@ CONFIG_MPILIB=y
# CONFIG_MTD_MCHP23K256 is not set
# CONFIG_MTD_SPI_NAND is not set
CONFIG_MTD_SPI_NOR=m
# CONFIG_MTD_SPI_NOR_MISC is not set
# CONFIG_MTD_SPI_NOR_USE_4K_SECTORS is not set
# CONFIG_MTD_SST25L is not set
# CONFIG_NL80211_TESTMODE is not set
@ -257,8 +260,10 @@ CONFIG_RFKILL_RK=y
CONFIG_ROCKCHIP_MBOX=y
# CONFIG_ROCKCHIP_MMC_VENDOR_STORAGE is not set
CONFIG_ROCKCHIP_MTD_VENDOR_STORAGE=m
# CONFIG_ROCKCHIP_RAM_VENDOR_STORAGE is not set
CONFIG_ROCKCHIP_THUNDER_BOOT_SERVICE=y
# CONFIG_RPMSG_QCOM_GLINK_RPM is not set
# CONFIG_RPMSG_ROCKCHIP is not set
# CONFIG_RTC_DRV_DS1302 is not set
# CONFIG_RTC_DRV_DS1305 is not set
# CONFIG_RTC_DRV_DS1343 is not set

421
arch/arm/configs/rv1106-tb-nofastae.config Normal file
View File

@ -0,0 +1,421 @@
CONFIG_BLK_DEV_INITRD=y
CONFIG_CRC16=m
CONFIG_CRYPTO=y
CONFIG_DAX=y
CONFIG_EROFS_FS=y
# CONFIG_ETHERNET is not set
CONFIG_EXT4_FS=m
CONFIG_FILE_LOCKING=y
CONFIG_JFFS2_FS=y
CONFIG_KERNEL_GZIP=y
# CONFIG_KERNEL_XZ is not set
CONFIG_LIBCRC32C=y
CONFIG_MAILBOX=y
# CONFIG_MDIO_DEVICE is not set
CONFIG_MMC=y
CONFIG_MSDOS_FS=m
CONFIG_MSDOS_PARTITION=y
CONFIG_MTD_BLOCK=m
CONFIG_NLS_CODEPAGE_936=m
# CONFIG_PHYLIB is not set
CONFIG_PHY_ROCKCHIP_CSI2_DPHY=y
CONFIG_PRINTK_TIME_FROM_ARM_ARCH_TIMER=y
CONFIG_ROCKCHIP_DVBM=y
CONFIG_ROCKCHIP_HW_DECOMPRESS=y
CONFIG_ROCKCHIP_MULTI_RGA=y
CONFIG_ROCKCHIP_RAMDISK=y
CONFIG_ROCKCHIP_RGA_PROC_FS=y
CONFIG_ROCKCHIP_THUNDER_BOOT=y
CONFIG_ROCKCHIP_VENDOR_STORAGE=m
# CONFIG_SLUB_SYSFS is not set
CONFIG_SND_SIMPLE_CARD=m
CONFIG_SND_SIMPLE_CARD_UTILS=m
CONFIG_SND_SOC_ROCKCHIP=m
CONFIG_SND_SOC_ROCKCHIP_I2S_TDM=m
CONFIG_SND_SOC_RV1106=m
CONFIG_SPI=y
CONFIG_VFAT_FS=m
CONFIG_VIDEO_ROCKCHIP_CIF=y
CONFIG_VIDEO_ROCKCHIP_ISP=y
CONFIG_VIDEO_SC230AI=y
CONFIG_VIDEO_SC301IOT=y
CONFIG_VIDEO_SC3338=y
# CONFIG_AD2S1200 is not set
# CONFIG_AD2S1210 is not set
# CONFIG_AD2S90 is not set
# CONFIG_AD5360 is not set
# CONFIG_AD5421 is not set
# CONFIG_AD5449 is not set
# CONFIG_AD5504 is not set
# CONFIG_AD5592R is not set
# CONFIG_AD5624R_SPI is not set
# CONFIG_AD5686_SPI is not set
# CONFIG_AD5755 is not set
# CONFIG_AD5758 is not set
# CONFIG_AD5761 is not set
# CONFIG_AD5764 is not set
# CONFIG_AD5770R is not set
# CONFIG_AD5791 is not set
# CONFIG_AD7124 is not set
# CONFIG_AD7192 is not set
# CONFIG_AD7266 is not set
# CONFIG_AD7280 is not set
# CONFIG_AD7292 is not set
# CONFIG_AD7298 is not set
# CONFIG_AD7303 is not set
# CONFIG_AD7476 is not set
# CONFIG_AD7606_IFACE_SPI is not set
# CONFIG_AD7766 is not set
# CONFIG_AD7768_1 is not set
# CONFIG_AD7780 is not set
# CONFIG_AD7791 is not set
# CONFIG_AD7793 is not set
# CONFIG_AD7816 is not set
# CONFIG_AD7887 is not set
# CONFIG_AD7923 is not set
# CONFIG_AD7949 is not set
# CONFIG_AD8366 is not set
# CONFIG_AD8801 is not set
# CONFIG_AD9523 is not set
# CONFIG_AD9832 is not set
# CONFIG_AD9834 is not set
# CONFIG_ADF4350 is not set
# CONFIG_ADF4371 is not set
# CONFIG_ADIS16080 is not set
# CONFIG_ADIS16130 is not set
# CONFIG_ADIS16136 is not set
# CONFIG_ADIS16201 is not set
# CONFIG_ADIS16203 is not set
# CONFIG_ADIS16209 is not set
# CONFIG_ADIS16240 is not set
# CONFIG_ADIS16260 is not set
# CONFIG_ADIS16400 is not set
# CONFIG_ADIS16460 is not set
# CONFIG_ADIS16475 is not set
# CONFIG_ADIS16480 is not set
# CONFIG_ADXL345_SPI is not set
# CONFIG_ADXL372_SPI is not set
# CONFIG_ADXRS290 is not set
# CONFIG_ADXRS450 is not set
# CONFIG_AFE4403 is not set
# CONFIG_ALTERA_MBOX is not set
# CONFIG_ARM_CRYPTO is not set
# CONFIG_ARM_MHU is not set
# CONFIG_ARM_SCMI_PROTOCOL is not set
# CONFIG_ARM_SCPI_PROTOCOL is not set
# CONFIG_AS3935 is not set
# CONFIG_BMA220 is not set
# CONFIG_BMC150_MAGN_SPI is not set
# CONFIG_BMI160_SPI is not set
# CONFIG_BSD_DISKLABEL is not set
# CONFIG_CRYPTO_842 is not set
# CONFIG_CRYPTO_ADIANTUM is not set
# CONFIG_CRYPTO_AEGIS128 is not set
# CONFIG_CRYPTO_AES is not set
# CONFIG_CRYPTO_AES_TI is not set
CONFIG_CRYPTO_ALGAPI=y
CONFIG_CRYPTO_ALGAPI2=y
# CONFIG_CRYPTO_ANSI_CPRNG is not set
# CONFIG_CRYPTO_AUTHENC is not set
# CONFIG_CRYPTO_BLAKE2B is not set
# CONFIG_CRYPTO_BLAKE2S is not set
# CONFIG_CRYPTO_BLOWFISH is not set
# CONFIG_CRYPTO_CAMELLIA is not set
# CONFIG_CRYPTO_CAST5 is not set
# CONFIG_CRYPTO_CAST6 is not set
# CONFIG_CRYPTO_CBC is not set
# CONFIG_CRYPTO_CCM is not set
# CONFIG_CRYPTO_CFB is not set
# CONFIG_CRYPTO_CHACHA20 is not set
# CONFIG_CRYPTO_CHACHA20POLY1305 is not set
# CONFIG_CRYPTO_CMAC is not set
# CONFIG_CRYPTO_CRC32 is not set
CONFIG_CRYPTO_CRC32C=y
# CONFIG_CRYPTO_CRCT10DIF is not set
# CONFIG_CRYPTO_CRYPTD is not set
# CONFIG_CRYPTO_CTR is not set
# CONFIG_CRYPTO_CTS is not set
# CONFIG_CRYPTO_CURVE25519 is not set
# CONFIG_CRYPTO_DEFLATE is not set
# CONFIG_CRYPTO_DES is not set
# CONFIG_CRYPTO_DH is not set
# CONFIG_CRYPTO_DRBG_MENU is not set
# CONFIG_CRYPTO_ECB is not set
# CONFIG_CRYPTO_ECDH is not set
# CONFIG_CRYPTO_ECHAINIV is not set
# CONFIG_CRYPTO_ECRDSA is not set
# CONFIG_CRYPTO_ESSIV is not set
# CONFIG_CRYPTO_FCRYPT is not set
# CONFIG_CRYPTO_GCM is not set
# CONFIG_CRYPTO_GHASH is not set
CONFIG_CRYPTO_HASH=y
CONFIG_CRYPTO_HASH2=y
# CONFIG_CRYPTO_HMAC is not set
# CONFIG_CRYPTO_HW is not set
# CONFIG_CRYPTO_JITTERENTROPY is not set
# CONFIG_CRYPTO_KEYWRAP is not set
# CONFIG_CRYPTO_LIB_CHACHA is not set
# CONFIG_CRYPTO_LIB_CHACHA20POLY1305 is not set
# CONFIG_CRYPTO_LRW is not set
# CONFIG_CRYPTO_LZ4 is not set
# CONFIG_CRYPTO_LZ4HC is not set
# CONFIG_CRYPTO_LZO is not set
# CONFIG_CRYPTO_MANAGER is not set
CONFIG_CRYPTO_MANAGER_DISABLE_TESTS=y
# CONFIG_CRYPTO_MD4 is not set
# CONFIG_CRYPTO_MD5 is not set
# CONFIG_CRYPTO_MICHAEL_MIC is not set
# CONFIG_CRYPTO_NULL is not set
# CONFIG_CRYPTO_OFB is not set
# CONFIG_CRYPTO_PCBC is not set
# CONFIG_CRYPTO_POLY1305 is not set
# CONFIG_CRYPTO_RMD128 is not set
# CONFIG_CRYPTO_RMD160 is not set
# CONFIG_CRYPTO_RMD256 is not set
# CONFIG_CRYPTO_RMD320 is not set
# CONFIG_CRYPTO_RSA is not set
# CONFIG_CRYPTO_SALSA20 is not set
# CONFIG_CRYPTO_SEQIV is not set
# CONFIG_CRYPTO_SERPENT is not set
# CONFIG_CRYPTO_SHA1 is not set
# CONFIG_CRYPTO_SHA256 is not set
# CONFIG_CRYPTO_SHA3 is not set
# CONFIG_CRYPTO_SHA512 is not set
# CONFIG_CRYPTO_SM2 is not set
# CONFIG_CRYPTO_SM3 is not set
# CONFIG_CRYPTO_SM4 is not set
# CONFIG_CRYPTO_STREEBOG is not set
# CONFIG_CRYPTO_TEST is not set
# CONFIG_CRYPTO_TGR192 is not set
# CONFIG_CRYPTO_TWOFISH is not set
# CONFIG_CRYPTO_USER is not set
# CONFIG_CRYPTO_USER_API_AEAD is not set
# CONFIG_CRYPTO_USER_API_HASH is not set
# CONFIG_CRYPTO_USER_API_RNG is not set
# CONFIG_CRYPTO_USER_API_SKCIPHER is not set
# CONFIG_CRYPTO_VMAC is not set
# CONFIG_CRYPTO_WP512 is not set
# CONFIG_CRYPTO_XCBC is not set
# CONFIG_CRYPTO_XTS is not set
# CONFIG_CRYPTO_XXHASH is not set
# CONFIG_CRYPTO_ZSTD is not set
# CONFIG_EEPROM_93XX46 is not set
# CONFIG_EEPROM_AT25 is not set
# CONFIG_EROFS_FS_DEBUG is not set
# CONFIG_EROFS_FS_XATTR is not set
# CONFIG_EROFS_FS_ZIP is not set
# CONFIG_EXT4_DEBUG is not set
# CONFIG_EXT4_FS_POSIX_ACL is not set
# CONFIG_EXT4_FS_SECURITY is not set
CONFIG_EXT4_USE_FOR_EXT2=y
# CONFIG_EZX_PCAP is not set
CONFIG_FAT_DEFAULT_CODEPAGE=936
CONFIG_FAT_DEFAULT_IOCHARSET="cp936"
CONFIG_FAT_DEFAULT_UTF8=y
CONFIG_FAT_FS=m
CONFIG_FS_DAX=y
CONFIG_FS_IOMAP=y
CONFIG_FS_MBCACHE=m
# CONFIG_FXOS8700_SPI is not set
# CONFIG_GPIO_74X164 is not set
# CONFIG_GPIO_MAX3191X is not set
# CONFIG_GPIO_MAX7301 is not set
# CONFIG_GPIO_MC33880 is not set
# CONFIG_GPIO_PISOSR is not set
# CONFIG_GPIO_XRA1403 is not set
# CONFIG_HI8435 is not set
# CONFIG_IIO_SSP_SENSORHUB is not set
# CONFIG_INITCALL_ASYNC is not set
# CONFIG_INITRAMFS_FORCE is not set
CONFIG_INITRAMFS_SOURCE=""
CONFIG_INITRD_ASYNC=y
# CONFIG_INV_ICM42600_SPI is not set
# CONFIG_INV_MPU6050_SPI is not set
CONFIG_JBD2=m
# CONFIG_JBD2_DEBUG is not set
# CONFIG_JFFS2_CMODE_FAVOURLZO is not set
# CONFIG_JFFS2_CMODE_NONE is not set
CONFIG_JFFS2_CMODE_PRIORITY=y
# CONFIG_JFFS2_CMODE_SIZE is not set
CONFIG_JFFS2_COMPRESSION_OPTIONS=y
CONFIG_JFFS2_FS_DEBUG=0
# CONFIG_JFFS2_FS_WBUF_VERIFY is not set
CONFIG_JFFS2_FS_WRITEBUFFER=y
# CONFIG_JFFS2_FS_XATTR is not set
# CONFIG_JFFS2_LZO is not set
# CONFIG_JFFS2_RTIME is not set
# CONFIG_JFFS2_RUBIN is not set
# CONFIG_JFFS2_SUMMARY is not set
CONFIG_JFFS2_ZLIB=y
# CONFIG_LATTICE_ECP3_CONFIG is not set
CONFIG_LIB_MEMNEQ=y
# CONFIG_LTC1660 is not set
# CONFIG_LTC2496 is not set
# CONFIG_LTC2632 is not set
# CONFIG_LTC2983 is not set
# CONFIG_MAILBOX_TEST is not set
CONFIG_MANDATORY_FILE_LOCKING=y
# CONFIG_MAX1027 is not set
# CONFIG_MAX11100 is not set
# CONFIG_MAX1118 is not set
# CONFIG_MAX1241 is not set
# CONFIG_MAX31856 is not set
# CONFIG_MAX5481 is not set
# CONFIG_MAX5487 is not set
# CONFIG_MAXIM_THERMOCOUPLE is not set
# CONFIG_MCP320X is not set
# CONFIG_MCP3911 is not set
# CONFIG_MCP41010 is not set
# CONFIG_MCP4131 is not set
# CONFIG_MCP4922 is not set
# CONFIG_MFD_ARIZONA_SPI is not set
# CONFIG_MFD_CPCAP is not set
# CONFIG_MFD_DA9052_SPI is not set
# CONFIG_MFD_INTEL_M10_BMC is not set
# CONFIG_MFD_MC13XXX_SPI is not set
# CONFIG_MFD_RK806_SPI is not set
# CONFIG_MFD_TPS65912_SPI is not set
# CONFIG_MFD_WM831X_SPI is not set
# CONFIG_MICREL_KS8995MA is not set
# CONFIG_MINIX_SUBPARTITION is not set
# CONFIG_MMA7455_SPI is not set
# CONFIG_MMC_ARMMMCI is not set
CONFIG_MMC_BLOCK=m
CONFIG_MMC_BLOCK_MINORS=32
# CONFIG_MMC_CQHCI is not set
# CONFIG_MMC_DEBUG is not set
CONFIG_MMC_DW=m
# CONFIG_MMC_DW_BLUEFIELD is not set
# CONFIG_MMC_DW_EXYNOS is not set
# CONFIG_MMC_DW_HI3798CV200 is not set
# CONFIG_MMC_DW_K3 is not set
CONFIG_MMC_DW_PLTFM=m
CONFIG_MMC_DW_ROCKCHIP=m
# CONFIG_MMC_HSQ is not set
# CONFIG_MMC_MTK is not set
CONFIG_MMC_QUEUE_DEPTH=1
# CONFIG_MMC_SDHCI is not set
# CONFIG_MMC_SPI is not set
# CONFIG_MMC_TEST is not set
# CONFIG_MMC_USDHI6ROL0 is not set
# CONFIG_MOXTET is not set
# CONFIG_MPL115_SPI is not set
CONFIG_MTD_BLKDEVS=m
# CONFIG_MTD_DATAFLASH is not set
# CONFIG_MTD_MCHP23K256 is not set
# CONFIG_MTD_SPI_NAND is not set
CONFIG_MTD_SPI_NOR=m
CONFIG_MTD_SPI_NOR_MISC=y
# CONFIG_MTD_SPI_NOR_USE_4K_SECTORS is not set
# CONFIG_MTD_SST25L is not set
# CONFIG_PI433 is not set
# CONFIG_PL320_MBOX is not set
# CONFIG_PLATFORM_MHU is not set
# CONFIG_PWRSEQ_EMMC is not set
# CONFIG_PWRSEQ_SIMPLE is not set
# CONFIG_RD_BZIP2 is not set
# CONFIG_RD_GZIP is not set
# CONFIG_RD_LZ4 is not set
# CONFIG_RD_LZMA is not set
# CONFIG_RD_LZO is not set
# CONFIG_RD_XZ is not set
# CONFIG_RD_ZSTD is not set
CONFIG_REGMAP_SPI=y
# CONFIG_REGULATOR_TPS6524X is not set
# CONFIG_ROCKCHIP_MBOX is not set
# CONFIG_ROCKCHIP_MMC_VENDOR_STORAGE is not set
CONFIG_ROCKCHIP_MTD_VENDOR_STORAGE=m
CONFIG_ROCKCHIP_RGA_DEBUGGER=y
CONFIG_ROCKCHIP_THUNDER_BOOT_MMC=y
# CONFIG_ROCKCHIP_THUNDER_BOOT_SERVICE is not set
CONFIG_ROCKCHIP_THUNDER_BOOT_SFC=y
# CONFIG_RPMSG_QCOM_GLINK_RPM is not set
# CONFIG_RTC_DRV_DS1302 is not set
# CONFIG_RTC_DRV_DS1305 is not set
# CONFIG_RTC_DRV_DS1343 is not set
# CONFIG_RTC_DRV_DS1347 is not set
# CONFIG_RTC_DRV_DS1390 is not set
# CONFIG_RTC_DRV_M41T93 is not set
# CONFIG_RTC_DRV_M41T94 is not set
# CONFIG_RTC_DRV_MAX6902 is not set
# CONFIG_RTC_DRV_MAX6916 is not set
# CONFIG_RTC_DRV_MCP795 is not set
# CONFIG_RTC_DRV_PCF2123 is not set
# CONFIG_RTC_DRV_R9701 is not set
# CONFIG_RTC_DRV_RS5C348 is not set
# CONFIG_RTC_DRV_RX4581 is not set
# CONFIG_RTC_DRV_RX6110 is not set
# CONFIG_SCA3000 is not set
# CONFIG_SDIO_UART is not set
# CONFIG_SENSORS_HMC5843_SPI is not set
# CONFIG_SENSORS_RM3100_SPI is not set
# CONFIG_SERIAL_IFX6X60 is not set
# CONFIG_SERIAL_MAX3100 is not set
# CONFIG_SERIAL_MAX310X is not set
# CONFIG_SND_SOC_ADAU1761_SPI is not set
# CONFIG_SND_SOC_AK4104 is not set
# CONFIG_SND_SOC_CS4271_SPI is not set
# CONFIG_SND_SOC_ES8328_SPI is not set
# CONFIG_SND_SOC_PCM179X_SPI is not set
# CONFIG_SND_SOC_PCM186X_SPI is not set
# CONFIG_SND_SOC_PCM3060_SPI is not set
# CONFIG_SND_SOC_PCM3168A_SPI is not set
# CONFIG_SND_SOC_PCM512x_SPI is not set
# CONFIG_SND_SOC_RK3399_GRU_SOUND is not set
# CONFIG_SND_SOC_SSM2602_SPI is not set
# CONFIG_SND_SOC_TLV320AIC23_SPI is not set
# CONFIG_SND_SOC_TLV320AIC32X4_SPI is not set
# CONFIG_SND_SOC_WM8770 is not set
# CONFIG_SND_SOC_WM8804_SPI is not set
# CONFIG_SND_SOC_ZL38060 is not set
# CONFIG_SND_SPI is not set
# CONFIG_SOLARIS_X86_PARTITION is not set
# CONFIG_SPI_ALTERA is not set
# CONFIG_SPI_AMD is not set
# CONFIG_SPI_AXI_SPI_ENGINE is not set
# CONFIG_SPI_BITBANG is not set
# CONFIG_SPI_CADENCE is not set
# CONFIG_SPI_CADENCE_QUADSPI is not set
# CONFIG_SPI_DEBUG is not set
# CONFIG_SPI_DESIGNWARE is not set
# CONFIG_SPI_FSL_SPI is not set
# CONFIG_SPI_GPIO is not set
# CONFIG_SPI_LOOPBACK_TEST is not set
CONFIG_SPI_MASTER=y
CONFIG_SPI_MEM=y
# CONFIG_SPI_MUX is not set
# CONFIG_SPI_MXIC is not set
# CONFIG_SPI_NXP_FLEXSPI is not set
# CONFIG_SPI_OC_TINY is not set
# CONFIG_SPI_PL022 is not set
# CONFIG_SPI_ROCKCHIP is not set
CONFIG_SPI_ROCKCHIP_SFC=y
# CONFIG_SPI_SC18IS602 is not set
# CONFIG_SPI_SIFIVE is not set
# CONFIG_SPI_SLAVE is not set
# CONFIG_SPI_SPIDEV is not set
# CONFIG_SPI_TLE62X0 is not set
# CONFIG_SPI_XCOMM is not set
# CONFIG_SPI_XILINX is not set
# CONFIG_SPI_ZYNQMP_GQSPI is not set
# CONFIG_TI_ADC0832 is not set
# CONFIG_TI_ADC084S021 is not set
# CONFIG_TI_ADC108S102 is not set
# CONFIG_TI_ADC12138 is not set
# CONFIG_TI_ADC128S052 is not set
# CONFIG_TI_ADC161S626 is not set
# CONFIG_TI_ADS124S08 is not set
# CONFIG_TI_ADS7950 is not set
# CONFIG_TI_ADS8344 is not set
# CONFIG_TI_ADS8688 is not set
# CONFIG_TI_DAC082S085 is not set
# CONFIG_TI_DAC7311 is not set
# CONFIG_TI_DAC7612 is not set
# CONFIG_TI_TLC4541 is not set
# CONFIG_UNIXWARE_DISKLABEL is not set
# CONFIG_VIDEO_GS1662 is not set
# CONFIG_VIDEO_ROCKCHIP_PREISP is not set
# CONFIG_VIDEO_ROCKCHIP_THUNDER_BOOT_ISP is not set
# CONFIG_VIDEO_S5C73M3 is not set
CONFIG_ZLIB_DEFLATE=y
CONFIG_ZLIB_INFLATE=y

105
arch/arm/configs/rv1106-tee.config
View File

@ -1,13 +1,118 @@
CONFIG_ARM_PSCI=y
CONFIG_CRYPTO=y
# CONFIG_FIQ_DEBUGGER_FIQ_GLUE is not set
CONFIG_FIQ_DEBUGGER_TRUST_ZONE=y
CONFIG_TEE=y
CONFIG_ARM_CPU_SUSPEND=y
# CONFIG_ARM_CRYPTO is not set
# CONFIG_ARM_HIGHBANK_CPUIDLE is not set
# CONFIG_ARM_PSCI_CPUIDLE is not set
CONFIG_ARM_PSCI_FW=y
# CONFIG_ARM_SCMI_PROTOCOL is not set
CONFIG_ARM_SMCCC_SOC_ID=y
# CONFIG_CRYPTO_842 is not set
# CONFIG_CRYPTO_ADIANTUM is not set
# CONFIG_CRYPTO_AEGIS128 is not set
# CONFIG_CRYPTO_AES is not set
# CONFIG_CRYPTO_AES_TI is not set
CONFIG_CRYPTO_ALGAPI=y
CONFIG_CRYPTO_ALGAPI2=y
# CONFIG_CRYPTO_ANSI_CPRNG is not set
# CONFIG_CRYPTO_AUTHENC is not set
# CONFIG_CRYPTO_BLAKE2B is not set
# CONFIG_CRYPTO_BLAKE2S is not set
# CONFIG_CRYPTO_BLOWFISH is not set
# CONFIG_CRYPTO_CAMELLIA is not set
# CONFIG_CRYPTO_CAST5 is not set
# CONFIG_CRYPTO_CAST6 is not set
# CONFIG_CRYPTO_CBC is not set
# CONFIG_CRYPTO_CCM is not set
# CONFIG_CRYPTO_CFB is not set
# CONFIG_CRYPTO_CHACHA20 is not set
# CONFIG_CRYPTO_CHACHA20POLY1305 is not set
# CONFIG_CRYPTO_CMAC is not set
# CONFIG_CRYPTO_CRC32 is not set
# CONFIG_CRYPTO_CRC32C is not set
# CONFIG_CRYPTO_CRCT10DIF is not set
# CONFIG_CRYPTO_CRYPTD is not set
# CONFIG_CRYPTO_CTR is not set
# CONFIG_CRYPTO_CTS is not set
# CONFIG_CRYPTO_CURVE25519 is not set
# CONFIG_CRYPTO_DEFLATE is not set
# CONFIG_CRYPTO_DES is not set
# CONFIG_CRYPTO_DEV_AMLOGIC_GXL is not set
# CONFIG_CRYPTO_DEV_ATMEL_ECC is not set
# CONFIG_CRYPTO_DEV_ATMEL_SHA204A is not set
# CONFIG_CRYPTO_DEV_CCREE is not set
# CONFIG_CRYPTO_DEV_ROCKCHIP is not set
# CONFIG_CRYPTO_DEV_SAFEXCEL is not set
# CONFIG_CRYPTO_DH is not set
# CONFIG_CRYPTO_DRBG_MENU is not set
# CONFIG_CRYPTO_ECB is not set
# CONFIG_CRYPTO_ECDH is not set
# CONFIG_CRYPTO_ECHAINIV is not set
# CONFIG_CRYPTO_ECRDSA is not set
# CONFIG_CRYPTO_ESSIV is not set
# CONFIG_CRYPTO_FCRYPT is not set
# CONFIG_CRYPTO_GCM is not set
# CONFIG_CRYPTO_GHASH is not set
CONFIG_CRYPTO_HASH=y
CONFIG_CRYPTO_HASH2=y
# CONFIG_CRYPTO_HMAC is not set
CONFIG_CRYPTO_HW=y
# CONFIG_CRYPTO_JITTERENTROPY is not set
# CONFIG_CRYPTO_KEYWRAP is not set
# CONFIG_CRYPTO_LIB_CHACHA is not set
# CONFIG_CRYPTO_LIB_CHACHA20POLY1305 is not set
# CONFIG_CRYPTO_LRW is not set
# CONFIG_CRYPTO_LZ4 is not set
# CONFIG_CRYPTO_LZ4HC is not set
# CONFIG_CRYPTO_LZO is not set
# CONFIG_CRYPTO_MANAGER is not set
CONFIG_CRYPTO_MANAGER_DISABLE_TESTS=y
# CONFIG_CRYPTO_MD4 is not set
# CONFIG_CRYPTO_MD5 is not set
# CONFIG_CRYPTO_MICHAEL_MIC is not set
# CONFIG_CRYPTO_NULL is not set
# CONFIG_CRYPTO_OFB is not set
# CONFIG_CRYPTO_PCBC is not set
# CONFIG_CRYPTO_POLY1305 is not set
# CONFIG_CRYPTO_RMD128 is not set
# CONFIG_CRYPTO_RMD160 is not set
# CONFIG_CRYPTO_RMD256 is not set
# CONFIG_CRYPTO_RMD320 is not set
# CONFIG_CRYPTO_RSA is not set
# CONFIG_CRYPTO_SALSA20 is not set
# CONFIG_CRYPTO_SEQIV is not set
# CONFIG_CRYPTO_SERPENT is not set
CONFIG_CRYPTO_SHA1=y
# CONFIG_CRYPTO_SHA256 is not set
# CONFIG_CRYPTO_SHA3 is not set
# CONFIG_CRYPTO_SHA512 is not set
# CONFIG_CRYPTO_SM2 is not set
# CONFIG_CRYPTO_SM3 is not set
# CONFIG_CRYPTO_SM4 is not set
# CONFIG_CRYPTO_STREEBOG is not set
# CONFIG_CRYPTO_TEST is not set
# CONFIG_CRYPTO_TGR192 is not set
# CONFIG_CRYPTO_TWOFISH is not set
# CONFIG_CRYPTO_USER is not set
# CONFIG_CRYPTO_USER_API_AEAD is not set
# CONFIG_CRYPTO_USER_API_HASH is not set
# CONFIG_CRYPTO_USER_API_RNG is not set
# CONFIG_CRYPTO_USER_API_SKCIPHER is not set
# CONFIG_CRYPTO_VMAC is not set
# CONFIG_CRYPTO_WP512 is not set
# CONFIG_CRYPTO_XCBC is not set
# CONFIG_CRYPTO_XTS is not set
# CONFIG_CRYPTO_XXHASH is not set
# CONFIG_CRYPTO_ZSTD is not set
CONFIG_GLOB=y
# CONFIG_GLOB_SELFTEST is not set
CONFIG_HAVE_ARM_SMCCC_DISCOVERY=y
CONFIG_HW_RANDOM_OPTEE=y
CONFIG_LIB_MEMNEQ=y
CONFIG_OPTEE=y
CONFIG_OPTEE_SHM_NUM_PRIV_PAGES=1
CONFIG_ROCKCHIP_SIP=y
CONFIG_SOC_BUS=y

506
arch/arm/configs/rv1106-trailcam.config Normal file
View File

@ -0,0 +1,506 @@
CONFIG_BACKLIGHT_CLASS_DEVICE=y
CONFIG_CONFIGFS_FS=y
CONFIG_CRC16=y
CONFIG_DRM=y
CONFIG_EXT4_FS=y
CONFIG_FB=y
CONFIG_FILE_LOCKING=y
CONFIG_I2C_GPIO=y
CONFIG_I2C_MUX=y
CONFIG_INPUT=y
CONFIG_JFFS2_FS=y
CONFIG_KCMP=y
CONFIG_MAILBOX=y
CONFIG_MMC_DW_ROCKCHIP=y
CONFIG_MSDOS_PARTITION=y
CONFIG_NLS_CODEPAGE_437=y
CONFIG_NLS_ISO8859_1=y
CONFIG_RK_CMA_PROCFS=y
CONFIG_RK_DMABUF_PROCFS=y
CONFIG_RK_MEMBLOCK_PROCFS=y
CONFIG_ROCKCHIP_RVE=y
CONFIG_SPI=y
CONFIG_VFAT_FS=y
CONFIG_VIDEO_SC230AI=y
CONFIG_VIDEO_SC301IOT=y
CONFIG_VIDEO_SC3338=y
# CONFIG_AD2S1200 is not set
# CONFIG_AD2S1210 is not set
# CONFIG_AD2S90 is not set
# CONFIG_AD5360 is not set
# CONFIG_AD5421 is not set
# CONFIG_AD5449 is not set
# CONFIG_AD5504 is not set
# CONFIG_AD5592R is not set
# CONFIG_AD5624R_SPI is not set
# CONFIG_AD5686_SPI is not set
# CONFIG_AD5755 is not set
# CONFIG_AD5758 is not set
# CONFIG_AD5761 is not set
# CONFIG_AD5764 is not set
# CONFIG_AD5770R is not set
# CONFIG_AD5791 is not set
# CONFIG_AD7124 is not set
# CONFIG_AD7192 is not set
# CONFIG_AD7266 is not set
# CONFIG_AD7280 is not set
# CONFIG_AD7292 is not set
# CONFIG_AD7298 is not set
# CONFIG_AD7303 is not set
# CONFIG_AD7476 is not set
# CONFIG_AD7606_IFACE_SPI is not set
# CONFIG_AD7766 is not set
# CONFIG_AD7768_1 is not set
# CONFIG_AD7780 is not set
# CONFIG_AD7791 is not set
# CONFIG_AD7793 is not set
# CONFIG_AD7816 is not set
# CONFIG_AD7887 is not set
# CONFIG_AD7923 is not set
# CONFIG_AD7949 is not set
# CONFIG_AD8366 is not set
# CONFIG_AD8801 is not set
# CONFIG_AD9523 is not set
# CONFIG_AD9832 is not set
# CONFIG_AD9834 is not set
# CONFIG_ADF4350 is not set
# CONFIG_ADF4371 is not set
# CONFIG_ADIS16080 is not set
# CONFIG_ADIS16130 is not set
# CONFIG_ADIS16136 is not set
# CONFIG_ADIS16201 is not set
# CONFIG_ADIS16203 is not set
# CONFIG_ADIS16209 is not set
# CONFIG_ADIS16240 is not set
# CONFIG_ADIS16260 is not set
# CONFIG_ADIS16400 is not set
# CONFIG_ADIS16460 is not set
# CONFIG_ADIS16475 is not set
# CONFIG_ADIS16480 is not set
# CONFIG_ADXL345_SPI is not set
# CONFIG_ADXL372_SPI is not set
# CONFIG_ADXRS290 is not set
# CONFIG_ADXRS450 is not set
# CONFIG_AFE4403 is not set
# CONFIG_ALTERA_MBOX is not set
# CONFIG_ARM_MHU is not set
# CONFIG_ARM_SCMI_PROTOCOL is not set
# CONFIG_ARM_SCPI_PROTOCOL is not set
# CONFIG_AS3935 is not set
# CONFIG_BACKLIGHT_ADP8860 is not set
# CONFIG_BACKLIGHT_ADP8870 is not set
# CONFIG_BACKLIGHT_ARCXCNN is not set
# CONFIG_BACKLIGHT_BD6107 is not set
# CONFIG_BACKLIGHT_GPIO is not set
# CONFIG_BACKLIGHT_KTD253 is not set
# CONFIG_BACKLIGHT_LM3630A is not set
# CONFIG_BACKLIGHT_LM3639 is not set
# CONFIG_BACKLIGHT_LP855X is not set
# CONFIG_BACKLIGHT_LV5207LP is not set
CONFIG_BACKLIGHT_PWM=y
# CONFIG_BACKLIGHT_QCOM_WLED is not set
# CONFIG_BMA220 is not set
# CONFIG_BMC150_MAGN_SPI is not set
# CONFIG_BMI160_SPI is not set
# CONFIG_BSD_DISKLABEL is not set
# CONFIG_DLM is not set
# CONFIG_DRM_ANALOGIX_ANX6345 is not set
# CONFIG_DRM_ANALOGIX_ANX78XX is not set
# CONFIG_DRM_ARCPGU is not set
# CONFIG_DRM_ARMADA is not set
CONFIG_DRM_BRIDGE=y
# CONFIG_DRM_CDNS_DSI is not set
# CONFIG_DRM_CDNS_MHDP8546 is not set
# CONFIG_DRM_CHRONTEL_CH7033 is not set
# CONFIG_DRM_DEBUG_DP_MST_TOPOLOGY_REFS is not set
# CONFIG_DRM_DEBUG_MM is not set
# CONFIG_DRM_DEBUG_SELFTEST is not set
# CONFIG_DRM_DISPLAY_CONNECTOR is not set
# CONFIG_DRM_DP is not set
# CONFIG_DRM_DP_AUX_CHARDEV is not set
# CONFIG_DRM_DP_CEC is not set
# CONFIG_DRM_EDID is not set
# CONFIG_DRM_ETNAVIV is not set
# CONFIG_DRM_EXYNOS is not set
CONFIG_DRM_FBDEV_EMULATION=y
# CONFIG_DRM_FBDEV_LEAK_PHYS_SMEM is not set
CONFIG_DRM_FBDEV_OVERALLOC=100
# CONFIG_DRM_FSL_DCU is not set
CONFIG_DRM_GEM_CMA_HELPER=y
# CONFIG_DRM_HDLCD is not set
# CONFIG_DRM_I2C_ADV7511 is not set
# CONFIG_DRM_I2C_CH7006 is not set
# CONFIG_DRM_I2C_NXP_TDA9950 is not set
# CONFIG_DRM_I2C_NXP_TDA998X is not set
# CONFIG_DRM_I2C_SIL164 is not set
# CONFIG_DRM_IGNORE_IOTCL_PERMIT is not set
# CONFIG_DRM_ITE_IT6161 is not set
CONFIG_DRM_KMS_FB_HELPER=y
CONFIG_DRM_KMS_HELPER=y
# CONFIG_DRM_KOMEDA is not set
# CONFIG_DRM_LEGACY is not set
# CONFIG_DRM_LIMA is not set
# CONFIG_DRM_LOAD_EDID_FIRMWARE is not set
# CONFIG_DRM_LONTIUM_LT9611 is not set
# CONFIG_DRM_LVDS_CODEC is not set
# CONFIG_DRM_MALI_DISPLAY is not set
# CONFIG_DRM_MAXIM_MAX96745 is not set
# CONFIG_DRM_MAXIM_MAX96755F is not set
# CONFIG_DRM_MCDE is not set
# CONFIG_DRM_MEGACHIPS_STDPXXXX_GE_B850V3_FW is not set
# CONFIG_DRM_MXSFB is not set
# CONFIG_DRM_NWL_MIPI_DSI is not set
# CONFIG_DRM_NXP_PTN3460 is not set
# CONFIG_DRM_OMAP is not set
CONFIG_DRM_PANEL=y
# CONFIG_DRM_PANEL_ARM_VERSATILE is not set
CONFIG_DRM_PANEL_BRIDGE=y
# CONFIG_DRM_PANEL_ILITEK_IL9322 is not set
# CONFIG_DRM_PANEL_LG_LB035Q02 is not set
# CONFIG_DRM_PANEL_LG_LG4573 is not set
# CONFIG_DRM_PANEL_LVDS is not set
# CONFIG_DRM_PANEL_MAXIM_DESERIALIZER is not set
# CONFIG_DRM_PANEL_NEC_NL8048HL11 is not set
# CONFIG_DRM_PANEL_NOVATEK_NT39016 is not set
# CONFIG_DRM_PANEL_OLIMEX_LCD_OLINUXINO is not set
CONFIG_DRM_PANEL_ORIENTATION_QUIRKS=y
# CONFIG_DRM_PANEL_SAMSUNG_LD9040 is not set
# CONFIG_DRM_PANEL_SAMSUNG_S6E63M0 is not set
# CONFIG_DRM_PANEL_SAMSUNG_S6E88A0_AMS452EF01 is not set
# CONFIG_DRM_PANEL_SAMSUNG_S6E8AA0 is not set
# CONFIG_DRM_PANEL_SEIKO_43WVF1G is not set
# CONFIG_DRM_PANEL_SHARP_LS037V7DW01 is not set
CONFIG_DRM_PANEL_SIMPLE=y
# CONFIG_DRM_PANEL_SITRONIX_ST7789V is not set
# CONFIG_DRM_PANEL_SONY_ACX565AKM is not set
# CONFIG_DRM_PANEL_TPO_TD028TTEC1 is not set
# CONFIG_DRM_PANEL_TPO_TD043MTEA1 is not set
# CONFIG_DRM_PANEL_TPO_TPG110 is not set
# CONFIG_DRM_PANFROST is not set
# CONFIG_DRM_PARADE_PS8622 is not set
# CONFIG_DRM_PARADE_PS8640 is not set
# CONFIG_DRM_PL111 is not set
# CONFIG_DRM_RCAR_DW_HDMI is not set
# CONFIG_DRM_RCAR_LVDS is not set
# CONFIG_DRM_RK1000_TVE is not set
CONFIG_DRM_ROCKCHIP=y
# CONFIG_DRM_ROCKCHIP_VVOP is not set
# CONFIG_DRM_ROHM_BU18XL82 is not set
# CONFIG_DRM_SII902X is not set
# CONFIG_DRM_SII9234 is not set
# CONFIG_DRM_SIL_SII8620 is not set
# CONFIG_DRM_SIMPLE_BRIDGE is not set
# CONFIG_DRM_STI is not set
# CONFIG_DRM_STM is not set
# CONFIG_DRM_THINE_THC63LVD1024 is not set
# CONFIG_DRM_TIDSS is not set
# CONFIG_DRM_TILCDC is not set
# CONFIG_DRM_TI_SN65DSI86 is not set
# CONFIG_DRM_TI_TFP410 is not set
# CONFIG_DRM_TI_TPD12S015 is not set
# CONFIG_DRM_TOSHIBA_TC358762 is not set
# CONFIG_DRM_TOSHIBA_TC358764 is not set
# CONFIG_DRM_TOSHIBA_TC358767 is not set
# CONFIG_DRM_TOSHIBA_TC358768 is not set
# CONFIG_DRM_TOSHIBA_TC358775 is not set
# CONFIG_DRM_TVE200 is not set
# CONFIG_DRM_VGEM is not set
# CONFIG_DRM_VKMS is not set
# CONFIG_EEPROM_93XX46 is not set
# CONFIG_EEPROM_AT25 is not set
# CONFIG_EXT4_DEBUG is not set
# CONFIG_EXT4_FS_POSIX_ACL is not set
# CONFIG_EXT4_FS_SECURITY is not set
CONFIG_EXT4_USE_FOR_EXT2=y
# CONFIG_EZX_PCAP is not set
CONFIG_FAT_DEFAULT_CODEPAGE=437
CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
# CONFIG_FAT_DEFAULT_UTF8 is not set
CONFIG_FAT_FS=y
# CONFIG_FB_ARMCLCD is not set
CONFIG_FB_CFB_COPYAREA=y
CONFIG_FB_CFB_FILLRECT=y
CONFIG_FB_CFB_IMAGEBLIT=y
CONFIG_FB_CMDLINE=y
CONFIG_FB_DEFERRED_IO=y
# CONFIG_FB_FOREIGN_ENDIAN is not set
# CONFIG_FB_IBM_GXT4500 is not set
# CONFIG_FB_METRONOME is not set
# CONFIG_FB_MODE_HELPERS is not set
CONFIG_FB_NOTIFY=y
# CONFIG_FB_OPENCORES is not set
# CONFIG_FB_S1D13XXX is not set
# CONFIG_FB_SIMPLE is not set
# CONFIG_FB_SSD1307 is not set
CONFIG_FB_SYS_COPYAREA=y
CONFIG_FB_SYS_FILLRECT=y
CONFIG_FB_SYS_FOPS=y
CONFIG_FB_SYS_IMAGEBLIT=y
# CONFIG_FB_TFT is not set
# CONFIG_FB_TILEBLITTING is not set
# CONFIG_FB_VIRTUAL is not set
# CONFIG_FIRMWARE_EDID is not set
CONFIG_FS_MBCACHE=y
# CONFIG_FXOS8700_SPI is not set
# CONFIG_GPIO_74X164 is not set
# CONFIG_GPIO_MAX3191X is not set
# CONFIG_GPIO_MAX7301 is not set
# CONFIG_GPIO_MC33880 is not set
# CONFIG_GPIO_PISOSR is not set
# CONFIG_GPIO_XRA1403 is not set
# CONFIG_HI8435 is not set
# CONFIG_HID is not set
CONFIG_I2C_ALGOBIT=y
# CONFIG_I2C_ARB_GPIO_CHALLENGE is not set
# CONFIG_I2C_DEMUX_PINCTRL is not set
# CONFIG_I2C_GPIO_FAULT_INJECTOR is not set
# CONFIG_I2C_HID is not set
# CONFIG_I2C_MUX_GPIO is not set
# CONFIG_I2C_MUX_GPMUX is not set
# CONFIG_I2C_MUX_LTC4306 is not set
# CONFIG_I2C_MUX_MLXCPLD is not set
# CONFIG_I2C_MUX_PCA9541 is not set
# CONFIG_I2C_MUX_PCA954x is not set
# CONFIG_I2C_MUX_PINCTRL is not set
# CONFIG_I2C_MUX_REG is not set
# CONFIG_IIO_SSP_SENSORHUB is not set
# CONFIG_INPUT_EVBUG is not set
CONFIG_INPUT_EVDEV=y
# CONFIG_INPUT_FF_MEMLESS is not set
# CONFIG_INPUT_JOYDEV is not set
# CONFIG_INPUT_JOYSTICK is not set
CONFIG_INPUT_KEYBOARD=y
# CONFIG_INPUT_MATRIXKMAP is not set
# CONFIG_INPUT_MISC is not set
# CONFIG_INPUT_MOUSE is not set
# CONFIG_INPUT_MOUSEDEV is not set
# CONFIG_INPUT_POLLDEV is not set
# CONFIG_INPUT_SPARSEKMAP is not set
# CONFIG_INPUT_TABLET is not set
# CONFIG_INPUT_TOUCHSCREEN is not set
# CONFIG_INV_ICM42600_SPI is not set
# CONFIG_INV_MPU6050_SPI is not set
CONFIG_JBD2=y
# CONFIG_JBD2_DEBUG is not set
# CONFIG_JFFS2_CMODE_FAVOURLZO is not set
# CONFIG_JFFS2_CMODE_NONE is not set
CONFIG_JFFS2_CMODE_PRIORITY=y
# CONFIG_JFFS2_CMODE_SIZE is not set
CONFIG_JFFS2_COMPRESSION_OPTIONS=y
CONFIG_JFFS2_FS_DEBUG=0
# CONFIG_JFFS2_FS_WBUF_VERIFY is not set
CONFIG_JFFS2_FS_WRITEBUFFER=y
# CONFIG_JFFS2_FS_XATTR is not set
# CONFIG_JFFS2_LZO is not set
# CONFIG_JFFS2_RTIME is not set
# CONFIG_JFFS2_RUBIN is not set
# CONFIG_JFFS2_SUMMARY is not set
CONFIG_JFFS2_ZLIB=y
CONFIG_KEYBOARD_ADC=y
# CONFIG_KEYBOARD_ADP5588 is not set
# CONFIG_KEYBOARD_ADP5589 is not set
# CONFIG_KEYBOARD_ATKBD is not set
# CONFIG_KEYBOARD_BCM is not set
# CONFIG_KEYBOARD_CAP11XX is not set
# CONFIG_KEYBOARD_DLINK_DIR685 is not set
CONFIG_KEYBOARD_GPIO=y
# CONFIG_KEYBOARD_GPIO_POLLED is not set
# CONFIG_KEYBOARD_LKKBD is not set
# CONFIG_KEYBOARD_LM8333 is not set
# CONFIG_KEYBOARD_MATRIX is not set
# CONFIG_KEYBOARD_MAX7359 is not set
# CONFIG_KEYBOARD_MCS is not set
# CONFIG_KEYBOARD_MPR121 is not set
# CONFIG_KEYBOARD_NEWTON is not set
# CONFIG_KEYBOARD_OMAP4 is not set
# CONFIG_KEYBOARD_OPENCORES is not set
# CONFIG_KEYBOARD_QT1050 is not set
# CONFIG_KEYBOARD_QT1070 is not set
# CONFIG_KEYBOARD_QT2160 is not set
# CONFIG_KEYBOARD_SAMSUNG is not set
# CONFIG_KEYBOARD_STOWAWAY is not set
# CONFIG_KEYBOARD_SUNKBD is not set
# CONFIG_KEYBOARD_TCA6416 is not set
# CONFIG_KEYBOARD_TCA8418 is not set
# CONFIG_KEYBOARD_XTKBD is not set
# CONFIG_LATTICE_ECP3_CONFIG is not set
# CONFIG_LOGO is not set
# CONFIG_LTC1660 is not set
# CONFIG_LTC2496 is not set
# CONFIG_LTC2632 is not set
# CONFIG_LTC2983 is not set
# CONFIG_MAILBOX_TEST is not set
# CONFIG_MANAGER_SBS is not set
CONFIG_MANDATORY_FILE_LOCKING=y
# CONFIG_MAX1027 is not set
# CONFIG_MAX11100 is not set
# CONFIG_MAX1118 is not set
# CONFIG_MAX1241 is not set
# CONFIG_MAX31856 is not set
# CONFIG_MAX5481 is not set
# CONFIG_MAX5487 is not set
# CONFIG_MAXIM_THERMOCOUPLE is not set
# CONFIG_MCP320X is not set
# CONFIG_MCP3911 is not set
# CONFIG_MCP41010 is not set
# CONFIG_MCP4131 is not set
# CONFIG_MCP4922 is not set
# CONFIG_MFD_ARIZONA_SPI is not set
# CONFIG_MFD_CPCAP is not set
# CONFIG_MFD_DA9052_SPI is not set
# CONFIG_MFD_INTEL_M10_BMC is not set
# CONFIG_MFD_MC13XXX_SPI is not set
# CONFIG_MFD_RK806_SPI is not set
# CONFIG_MFD_TPS65912_SPI is not set
# CONFIG_MFD_WM831X_SPI is not set
# CONFIG_MICREL_KS8995MA is not set
# CONFIG_MINIX_SUBPARTITION is not set
# CONFIG_MMA7455_SPI is not set
# CONFIG_MMC_SPI is not set
# CONFIG_MOST is not set
# CONFIG_MOXTET is not set
# CONFIG_MPL115_SPI is not set
# CONFIG_MTD_DATAFLASH is not set
# CONFIG_MTD_MCHP23K256 is not set
# CONFIG_MTD_SPI_NAND is not set
# CONFIG_MTD_SPI_NOR is not set
# CONFIG_MTD_SST25L is not set
# CONFIG_NVME_TARGET is not set
# CONFIG_OCFS2_FS is not set
# CONFIG_PI433 is not set
# CONFIG_PL320_MBOX is not set
# CONFIG_PLATFORM_MHU is not set
# CONFIG_RC_CORE is not set
CONFIG_REGMAP_SPI=y
# CONFIG_REGULATOR_RASPBERRYPI_TOUCHSCREEN_ATTINY is not set
# CONFIG_REGULATOR_TPS6524X is not set
# CONFIG_RMI4_CORE is not set
# CONFIG_ROCKCHIP_ANALOGIX_DP is not set
# CONFIG_ROCKCHIP_CDN_DP is not set
# CONFIG_ROCKCHIP_DRM_CUBIC_LUT is not set
# CONFIG_ROCKCHIP_DRM_DIRECT_SHOW is not set
# CONFIG_ROCKCHIP_DRM_TVE is not set
# CONFIG_ROCKCHIP_DW_DP is not set
# CONFIG_ROCKCHIP_DW_HDCP2 is not set
# CONFIG_ROCKCHIP_DW_HDMI is not set
# CONFIG_ROCKCHIP_DW_MIPI_DSI is not set
# CONFIG_ROCKCHIP_INNO_HDMI is not set
# CONFIG_ROCKCHIP_LVDS is not set
CONFIG_ROCKCHIP_MBOX=y
# CONFIG_ROCKCHIP_MTD_VENDOR_STORAGE is not set
# CONFIG_ROCKCHIP_REMOTECTL is not set
CONFIG_ROCKCHIP_RGB=y
# CONFIG_ROCKCHIP_RK3066_HDMI is not set
# CONFIG_ROCKCHIP_RKNPU_DRM_GEM is not set
CONFIG_ROCKCHIP_THUNDER_BOOT_SERVICE=y
# CONFIG_ROCKCHIP_VCONN is not set
CONFIG_ROCKCHIP_VOP=y
# CONFIG_ROCKCHIP_VOP2 is not set
# CONFIG_RPMSG_QCOM_GLINK_RPM is not set
# CONFIG_RPMSG_ROCKCHIP is not set
# CONFIG_RTC_DRV_DS1302 is not set
# CONFIG_RTC_DRV_DS1305 is not set
# CONFIG_RTC_DRV_DS1343 is not set
# CONFIG_RTC_DRV_DS1347 is not set
# CONFIG_RTC_DRV_DS1390 is not set
# CONFIG_RTC_DRV_M41T93 is not set
# CONFIG_RTC_DRV_M41T94 is not set
# CONFIG_RTC_DRV_MAX6902 is not set
# CONFIG_RTC_DRV_MAX6916 is not set
# CONFIG_RTC_DRV_MCP795 is not set
# CONFIG_RTC_DRV_PCF2123 is not set
# CONFIG_RTC_DRV_R9701 is not set
# CONFIG_RTC_DRV_RS5C348 is not set
# CONFIG_RTC_DRV_RX4581 is not set
# CONFIG_RTC_DRV_RX6110 is not set
# CONFIG_SCA3000 is not set
# CONFIG_SENSORS_HMC5843_SPI is not set
# CONFIG_SENSORS_LIS3_I2C is not set
# CONFIG_SENSORS_LIS3_SPI is not set
# CONFIG_SENSORS_RM3100_SPI is not set
# CONFIG_SENSOR_DEVICE is not set
# CONFIG_SERIAL_IFX6X60 is not set
# CONFIG_SERIAL_MAX3100 is not set
# CONFIG_SERIAL_MAX310X is not set
CONFIG_SND_JACK_INPUT_DEV=y
# CONFIG_SND_SOC_ADAU1761_SPI is not set
# CONFIG_SND_SOC_AK4104 is not set
# CONFIG_SND_SOC_CS4271_SPI is not set
# CONFIG_SND_SOC_CS42L52 is not set
# CONFIG_SND_SOC_CS42L56 is not set
# CONFIG_SND_SOC_ES8328_SPI is not set
# CONFIG_SND_SOC_PCM179X_SPI is not set
# CONFIG_SND_SOC_PCM186X_SPI is not set
# CONFIG_SND_SOC_PCM3060_SPI is not set
# CONFIG_SND_SOC_PCM3168A_SPI is not set
# CONFIG_SND_SOC_PCM512x_SPI is not set
# CONFIG_SND_SOC_RK3399_GRU_SOUND is not set
# CONFIG_SND_SOC_SSM2602_SPI is not set
# CONFIG_SND_SOC_TLV320AIC23_SPI is not set
# CONFIG_SND_SOC_TLV320AIC32X4_SPI is not set
# CONFIG_SND_SOC_WM8770 is not set
# CONFIG_SND_SOC_WM8804_SPI is not set
# CONFIG_SND_SOC_WM8962 is not set
# CONFIG_SND_SOC_ZL38060 is not set
# CONFIG_SND_SPI is not set
# CONFIG_SOLARIS_X86_PARTITION is not set
# CONFIG_SPI_ALTERA is not set
# CONFIG_SPI_AMD is not set
# CONFIG_SPI_AXI_SPI_ENGINE is not set
# CONFIG_SPI_BITBANG is not set
# CONFIG_SPI_CADENCE is not set
# CONFIG_SPI_CADENCE_QUADSPI is not set
# CONFIG_SPI_DEBUG is not set
# CONFIG_SPI_DESIGNWARE is not set
# CONFIG_SPI_FSL_SPI is not set
# CONFIG_SPI_GPIO is not set
# CONFIG_SPI_LOOPBACK_TEST is not set
CONFIG_SPI_MASTER=y
CONFIG_SPI_MEM=y
# CONFIG_SPI_MUX is not set
# CONFIG_SPI_MXIC is not set
# CONFIG_SPI_NXP_FLEXSPI is not set
# CONFIG_SPI_OC_TINY is not set
# CONFIG_SPI_PL022 is not set
CONFIG_SPI_ROCKCHIP=y
# CONFIG_SPI_ROCKCHIP_MISCDEV is not set
CONFIG_SPI_ROCKCHIP_SFC=y
# CONFIG_SPI_SC18IS602 is not set
# CONFIG_SPI_SIFIVE is not set
# CONFIG_SPI_SLAVE is not set
CONFIG_SPI_SPIDEV=y
# CONFIG_SPI_TLE62X0 is not set
# CONFIG_SPI_XCOMM is not set
# CONFIG_SPI_XILINX is not set
# CONFIG_SPI_ZYNQMP_GQSPI is not set
# CONFIG_TINYDRM_HX8357D is not set
# CONFIG_TINYDRM_ILI9225 is not set
# CONFIG_TINYDRM_ILI9341 is not set
# CONFIG_TINYDRM_ILI9486 is not set
# CONFIG_TINYDRM_MI0283QT is not set
# CONFIG_TINYDRM_REPAPER is not set
# CONFIG_TINYDRM_ST7586 is not set
# CONFIG_TINYDRM_ST7735R is not set
# CONFIG_TI_ADC0832 is not set
# CONFIG_TI_ADC084S021 is not set
# CONFIG_TI_ADC108S102 is not set
# CONFIG_TI_ADC12138 is not set
# CONFIG_TI_ADC128S052 is not set
# CONFIG_TI_ADC161S626 is not set
# CONFIG_TI_ADS124S08 is not set
# CONFIG_TI_ADS7950 is not set
# CONFIG_TI_ADS8344 is not set
# CONFIG_TI_ADS8688 is not set
# CONFIG_TI_DAC082S085 is not set
# CONFIG_TI_DAC7311 is not set
# CONFIG_TI_DAC7612 is not set
# CONFIG_TI_TLC4541 is not set
# CONFIG_UNIXWARE_DISKLABEL is not set
CONFIG_VIDEOMODE_HELPERS=y
# CONFIG_VIDEO_GS1662 is not set
# CONFIG_VIDEO_MAX9286 is not set
# CONFIG_VIDEO_ROCKCHIP_PREISP is not set
# CONFIG_VIDEO_S5C73M3 is not set
CONFIG_ZLIB_DEFLATE=y
CONFIG_ZLIB_INFLATE=y

127
arch/arm/configs/rv1106-wakeup.config Normal file
View File

@ -0,0 +1,127 @@
CONFIG_INPUT=y
CONFIG_RV1106_HPMCU_FAST_WAKEUP=y
CONFIG_VIDEO_SC301IOT=y
# CONFIG_VIDEO_SC3336 is not set
CONFIG_VIDEO_SC3338=y
# CONFIG_VIDEO_SC4336 is not set
# CONFIG_VIDEO_SC530AI is not set
CONFIG_HID=y
# CONFIG_HIDRAW is not set
# CONFIG_HID_A4TECH is not set
# CONFIG_HID_ACRUX is not set
# CONFIG_HID_ALPS is not set
# CONFIG_HID_APPLE is not set
# CONFIG_HID_AUREAL is not set
# CONFIG_HID_BATTERY_STRENGTH is not set
# CONFIG_HID_BELKIN is not set
# CONFIG_HID_CHERRY is not set
# CONFIG_HID_CMEDIA is not set
# CONFIG_HID_COUGAR is not set
# CONFIG_HID_CYPRESS is not set
# CONFIG_HID_DRAGONRISE is not set
# CONFIG_HID_ELECOM is not set
# CONFIG_HID_EMS_FF is not set
# CONFIG_HID_EZKEY is not set
# CONFIG_HID_GEMBIRD is not set
CONFIG_HID_GENERIC=y
# CONFIG_HID_GFRM is not set
# CONFIG_HID_GLORIOUS is not set
# CONFIG_HID_GREENASIA is not set
# CONFIG_HID_GYRATION is not set
# CONFIG_HID_ICADE is not set
# CONFIG_HID_ITE is not set
# CONFIG_HID_JABRA is not set
# CONFIG_HID_KENSINGTON is not set
# CONFIG_HID_KEYTOUCH is not set
# CONFIG_HID_KYE is not set
# CONFIG_HID_LCPOWER is not set
# CONFIG_HID_LENOVO is not set
# CONFIG_HID_MACALLY is not set
# CONFIG_HID_MAGICMOUSE is not set
# CONFIG_HID_MALTRON is not set
# CONFIG_HID_MAYFLASH is not set
# CONFIG_HID_MICROSOFT is not set
# CONFIG_HID_MONTEREY is not set
# CONFIG_HID_MULTITOUCH is not set
# CONFIG_HID_NINTENDO is not set
# CONFIG_HID_NTI is not set
# CONFIG_HID_ORTEK is not set
# CONFIG_HID_PANTHERLORD is not set
# CONFIG_HID_PETALYNX is not set
# CONFIG_HID_PICOLCD is not set
# CONFIG_HID_PLANTRONICS is not set
# CONFIG_HID_PLAYSTATION is not set
# CONFIG_HID_PRIMAX is not set
# CONFIG_HID_REDRAGON is not set
# CONFIG_HID_RMI is not set
# CONFIG_HID_SAITEK is not set
# CONFIG_HID_SENSOR_HUB is not set
# CONFIG_HID_SMARTJOYPLUS is not set
# CONFIG_HID_SPEEDLINK is not set
# CONFIG_HID_STEAM is not set
# CONFIG_HID_STEELSERIES is not set
# CONFIG_HID_SUNPLUS is not set
# CONFIG_HID_THRUSTMASTER is not set
# CONFIG_HID_TIVO is not set
# CONFIG_HID_TOPSEED is not set
# CONFIG_HID_TWINHAN is not set
# CONFIG_HID_UDRAW_PS3 is not set
# CONFIG_HID_VIEWSONIC is not set
# CONFIG_HID_VIVALDI is not set
# CONFIG_HID_WALTOP is not set
# CONFIG_HID_XINMO is not set
# CONFIG_HID_ZEROPLUS is not set
# CONFIG_HID_ZYDACRON is not set
# CONFIG_I2C_HID is not set
# CONFIG_INPUT_EVBUG is not set
# CONFIG_INPUT_EVDEV is not set
# CONFIG_INPUT_FF_MEMLESS is not set
# CONFIG_INPUT_JOYDEV is not set
# CONFIG_INPUT_JOYSTICK is not set
CONFIG_INPUT_KEYBOARD=y
# CONFIG_INPUT_MATRIXKMAP is not set
# CONFIG_INPUT_MISC is not set
# CONFIG_INPUT_MOUSE is not set
# CONFIG_INPUT_MOUSEDEV is not set
# CONFIG_INPUT_POLLDEV is not set
# CONFIG_INPUT_SPARSEKMAP is not set
# CONFIG_INPUT_TABLET is not set
# CONFIG_INPUT_TOUCHSCREEN is not set
# CONFIG_KEYBOARD_ADC is not set
# CONFIG_KEYBOARD_ADP5588 is not set
# CONFIG_KEYBOARD_ADP5589 is not set
# CONFIG_KEYBOARD_ATKBD is not set
# CONFIG_KEYBOARD_BCM is not set
# CONFIG_KEYBOARD_CAP11XX is not set
# CONFIG_KEYBOARD_DLINK_DIR685 is not set
CONFIG_KEYBOARD_GPIO=y
# CONFIG_KEYBOARD_GPIO_POLLED is not set
# CONFIG_KEYBOARD_LKKBD is not set
# CONFIG_KEYBOARD_LM8333 is not set
# CONFIG_KEYBOARD_MATRIX is not set
# CONFIG_KEYBOARD_MAX7359 is not set
# CONFIG_KEYBOARD_MCS is not set
# CONFIG_KEYBOARD_MPR121 is not set
# CONFIG_KEYBOARD_NEWTON is not set
# CONFIG_KEYBOARD_OMAP4 is not set
# CONFIG_KEYBOARD_OPENCORES is not set
# CONFIG_KEYBOARD_QT1050 is not set
# CONFIG_KEYBOARD_QT1070 is not set
# CONFIG_KEYBOARD_QT2160 is not set
# CONFIG_KEYBOARD_SAMSUNG is not set
# CONFIG_KEYBOARD_STOWAWAY is not set
# CONFIG_KEYBOARD_SUNKBD is not set
# CONFIG_KEYBOARD_TCA6416 is not set
# CONFIG_KEYBOARD_TCA8418 is not set
# CONFIG_KEYBOARD_XTKBD is not set
# CONFIG_RC_CORE is not set
# CONFIG_RMI4_CORE is not set
# CONFIG_ROCKCHIP_REMOTECTL is not set
# CONFIG_SENSORS_LIS3_I2C is not set
# CONFIG_SENSORS_LIS3_SPI is not set
# CONFIG_SENSOR_DEVICE is not set
CONFIG_SND_JACK_INPUT_DEV=y
# CONFIG_SND_SOC_CS42L52 is not set
# CONFIG_SND_SOC_CS42L56 is not set
# CONFIG_SND_SOC_WM8962 is not set
# CONFIG_UHID is not set

6
arch/arm/mach-rockchip/Kconfig
View File

@ -22,3 +22,9 @@ config ARCH_ROCKCHIP
help
Support for Rockchip's Cortex-A9 Single-to-Quad-Core-SoCs
containing the RK2928, RK30xx and RK31xx series.
config RV1106_HPMCU_FAST_WAKEUP
bool "Rockchip RV1106 HPMCU fast wakeup configuration support"
depends on PM_SLEEP && CPU_RV1106
help
This config aims to support HPMCU fast wakeup.

117
arch/arm/mach-rockchip/rv1106_pm.c
View File

@ -15,6 +15,7 @@
#include <asm/fiq_glue.h>
#include <asm/tlbflush.h>
#include <asm/suspend.h>
#include <linux/irqchip/arm-gic.h>
#include "rkpm_gicv2.h"
#include "rkpm_helpers.h"
@ -91,6 +92,7 @@ static void __iomem *firewall_syssram_base;
static void __iomem *pmu_base;
static void __iomem *nstimer_base;
static void __iomem *stimer_base;
static void __iomem *mbox_base;
static void __iomem *ddrc_base;
static void __iomem *ioc_base[5];
static void __iomem *gpio_base[5];
@ -309,7 +311,10 @@ static void gic400_save(void)
static void gic400_restore(void)
{
rkpm_gicv2_dist_restore(gicd_base, &gicd_ctx_save);
if (IS_ENABLED(CONFIG_RV1106_HPMCU_FAST_WAKEUP))
writel_relaxed(0x3, gicd_base + GIC_DIST_CTRL);
else
rkpm_gicv2_dist_restore(gicd_base, &gicd_ctx_save);
rkpm_gicv2_cpu_restore(gicd_base, gicc_base, &gicc_ctx_save);
}
@ -410,6 +415,87 @@ static void __init rv1106_config_bootdata(void)
rkpm_bootdata_l2ctlr = rv1106_l2_config();
}
static void writel_clrset_bits(u32 clr, u32 set, void __iomem *addr)
{
u32 val = readl_relaxed(addr);
val &= ~clr;
val |= set;
writel_relaxed(val, addr);
}
static void gic_irq_en(int irq)
{
writel_clrset_bits(0xff << irq % 4 * 8, 0x1 << irq % 4 * 8,
gicd_base + GIC_DIST_TARGET + (irq >> 2 << 2));
writel_clrset_bits(0xff << irq % 4 * 8, 0xa0 << irq % 4 * 8,
gicd_base + GIC_DIST_PRI + (irq >> 2 << 2));
writel_clrset_bits(0x3 << irq % 16 * 2, 0x1 << irq % 16 * 2,
gicd_base + GIC_DIST_CONFIG + (irq >> 4 << 2));
writel_clrset_bits(BIT(irq % 32), BIT(irq % 32),
gicd_base + GIC_DIST_IGROUP + (irq >> 5 << 2));
dsb(sy);
writel_relaxed(0x1 << irq % 32, gicd_base + GIC_DIST_ENABLE_SET + (irq >> 5 << 2));
dsb(sy);
}
static int is_hpmcu_mbox_int(void)
{
return !!(readl(mbox_base + RV1106_MBOX_B2A_STATUS) & BIT(0));
}
static void hpmcu_start(void)
{
/* enable hpmcu mailbox AP irq */
gic_irq_en(RV1106_HPMCU_MBOX_IRQ_AP);
/* tell hpmcu that we are currently in system wake up. */
writel(RV1106_SYS_IS_WKUP, pmu_base + RV1106_PMU_SYS_REG(0));
/* set the mcu uncache area, usually set the devices address */
writel(0xff000, coregrf_base + RV1106_COREGRF_CACHE_PERI_ADDR_START);
writel(0xffc00, coregrf_base + RV1106_COREGRF_CACHE_PERI_ADDR_END);
/* Reset the hp mcu */
writel(0x1e001e, corecru_base + RV1106_COERCRU_SFTRST_CON(1));
/* set the mcu addr */
writel(RV1106_HPMCU_BOOT_ADDR,
coresgrf_base + RV1106_CORESGRF_HPMCU_BOOTADDR);
dsb(sy);
/* release the mcu */
writel(0x1e0000, corecru_base + RV1106_COERCRU_SFTRST_CON(1));
dsb(sy);
}
static int hpmcu_fast_wkup(void)
{
u32 cmd;
hpmcu_start();
while (1) {
rkpm_printstr("-s-\n");
dsb(sy);
wfi();
rkpm_printstr("-w-\n");
if (is_hpmcu_mbox_int()) {
rkpm_printstr("-h-mbox-\n");
/* clear system wake up state */
writel(0, pmu_base + RV1106_PMU_SYS_REG(0));
writel(BIT(0), mbox_base + RV1106_MBOX_B2A_STATUS);
break;
}
}
cmd = readl(mbox_base + RV1106_MBOX_B2A_CMD_0);
if (cmd == RV1106_MBOX_CMD_AP_SUSPEND)
return 1;
else
return 0;
}
static void clock_suspend(void)
{
int i;
@ -616,10 +702,11 @@ static void pmu_sleep_config(void)
ddr_data.ioc1_1a_iomux_l = readl_relaxed(ioc_base[1] + 0);
pmu_wkup_con =
/* BIT(RV1106_PMU_WAKEUP_TIMEROUT_EN) | */
/* BIT(RV1106_PMU_WAKEUP_CPU_INT_EN) | */
BIT(RV1106_PMU_WAKEUP_GPIO_INT_EN) |
0;
if (IS_ENABLED(CONFIG_RV1106_HPMCU_FAST_WAKEUP))
pmu_wkup_con |= BIT(RV1106_PMU_WAKEUP_TIMEROUT_EN);
pmu_pwr_con =
BIT(RV1106_PMU_PWRMODE_EN) |
@ -949,7 +1036,18 @@ static int rockchip_lpmode_enter(unsigned long arg)
cpu_do_idle();
pr_err("%s: Failed to suspend\n", __func__);
#if RV1106_WAKEUP_TO_SYSTEM_RESET
/* If reaches here, it means wakeup source cames before cpu enter wfi.
* So we should do system reset if RV1106_WAKEUP_TO_SYSTEM_RESET.
*/
writel_relaxed(0x000c000c, cru_base + RV1106_CRU_GLB_RST_CON);
writel_relaxed(0xffff0000, pmugrf_base + RV1106_PMUGRF_SOC_CON(4));
writel_relaxed(0xffff0000, pmugrf_base + RV1106_PMUGRF_SOC_CON(5));
dsb(sy);
writel_relaxed(0xfdb9, cru_base + RV1106_CRU_GLB_SRST_FST);
#endif
rkpm_printstr("Failed to suspend\n");
return 1;
}
@ -964,6 +1062,7 @@ static int rv1106_suspend_enter(suspend_state_t state)
rkpm_printch('-');
RE_ENTER_SLEEP:
clock_suspend();
rkpm_printch('0');
@ -1001,6 +1100,17 @@ static int rv1106_suspend_enter(suspend_state_t state)
clock_resume();
rkpm_printch('-');
/* Check whether it's time_out wakeup */
if (IS_ENABLED(CONFIG_RV1106_HPMCU_FAST_WAKEUP) && ddr_data.pmu_wkup_int_st == 0) {
if (hpmcu_fast_wkup()) {
rkpm_gicv2_dist_restore(gicd_base, &gicd_ctx_save);
goto RE_ENTER_SLEEP;
} else {
rkpm_gicv2_dist_restore(gicd_base, &gicd_ctx_save);
rkpm_gicv2_cpu_restore(gicd_base, gicc_base, &gicc_ctx_save);
}
}
fiq_glue_resume();
rv1106_dbg_irq_finish();
@ -1062,6 +1172,7 @@ static int __init rv1106_suspend_init(struct device_node *np)
corecru_base = dev_reg_base + RV1106_CORECRU_OFFSET;
venccru_base = dev_reg_base + RV1106_VENCCRU_OFFSET;
vocru_base = dev_reg_base + RV1106_VOCRU_OFFSET;
mbox_base = dev_reg_base + RV1106_MBOX_OFFSET;
ioc_base[0] = dev_reg_base + RV1106_GPIO0IOC_OFFSET;
ioc_base[1] = dev_reg_base + RV1106_GPIO1IOC_OFFSET;

21
arch/arm/mach-rockchip/rv1106_pm.h
View File

@ -7,6 +7,7 @@
#define __MACH_ROCKCHIP_RV1106_PM_H
#define RV1106_WAKEUP_TO_SYSTEM_RESET 0
#define RV1106_HPMCU_FAST_WKUP_TIMEOUT 2000 /* ms */
#define RV1106_PERIGRF_OFFSET 0x0
#define RV1106_VENCGRF_OFFSET 0x10000
@ -54,6 +55,7 @@
#define RV1106_NSTIMER_OFFSET 0x580000
#define RV1106_STIMER_OFFSET 0x590000
#define RV1106_MBOX_OFFSET 0x5c0000
#define RV1106_PMUSRAM_OFFSET 0x670000
#define RV1106_DDRC_OFFSET 0x800000
#define RV1106_FW_DDR_OFFSET 0x900000
@ -70,6 +72,8 @@
#define RV1106_CRU_MODE_CON00 0x280
#define RV1106_CRU_GATE_CON(i) (0x800 + (i) * 4)
#define RV1106_CRU_GATE_CON_NUM 4
#define RV1106_CRU_GLB_SRST_FST 0xc08
#define RV1106_CRU_GLB_RST_CON 0xc10
#define CRU_PLLCON1_PWRDOWN BIT(13)
#define CRU_PLLCON1_LOCK_STATUS BIT(10)
@ -101,6 +105,7 @@
#define RV1106_CORECRU_GATE_CON(i) (0x800 + (i) * 4)
#define RV1106_COERCRU_CLKSEL_CON(i) (0x300 + (i) * 4)
#define RV1106_CORECRU_GATE_CON_NUM 2
#define RV1106_COERCRU_SFTRST_CON(i) (0xa00 + (i) * 4)
/* grf */
#define RV1106_PMUGRF_SOC_CON(i) ((i) * 4)
@ -110,6 +115,11 @@
#define RV1106_DDRGRF_CON(i) ((i) * 0x4)
#define RV1106_CORESGRF_HPMCU_BOOTADDR 0x44
#define RV1106_COREGRF_CACHE_PERI_ADDR_START 0x24
#define RV1106_COREGRF_CACHE_PERI_ADDR_END 0x28
/* pvmt */
#define RV1106_PVTM_CON(i) (0x4 + (i) * 4)
#define RV1106_PVTM_INTEN 0x70
@ -177,6 +187,17 @@
#define PMU_SUSPEND_MAGIC 0x02468ace
#define PMU_RESUME_MAGIC 0x13579bdf
/* mcu */
#define RV1106_MBOX_B2A_STATUS 0x2c
#define RV1106_MBOX_B2A_CMD_0 0x30
#define RV1106_HPMCU_MBOX_IRQ_AP 33
#define RV1106_HPMCU_BOOT_ADDR 0x40000
#define RV1106_MBOX_CMD_AP_SUSPEND 0x12345600
#define RV1106_MBOX_CMD_AP_RESUME 0x12345601
#define RV1106_SYS_IS_WKUP 0x87654300
#ifndef __ASSEMBLER__
extern unsigned long rkpm_bootdata_cpusp;
extern unsigned long rkpm_bootdata_cpu_code;

8
arch/arm/mach-rockchip/rv1106_sleep.S
View File

@ -13,6 +13,9 @@
#define RV1106_PMUGRF_SOC_CON4 0xff020010
#define RV1106_CRU_GLB_SRST_FST 0xff3b0c08
#define RV1106_CRU_GLB_RST_CON_ADDR 0xff3b0c10
#define CRU_FST_RST_PMU_VAL 0x000c000c
#if RV1106_SLEEP_DEBUG
/********************* console used for sleep.S ******************************/
#define UART_REG_DLL (0x00)
@ -98,6 +101,11 @@ ENTRY(rockchip_slp_cpu_resume)
ldr r1, [r1]
str r1, [r0]
/* enable first reset trigger pmu reset */
ldr r0, =RV1106_CRU_GLB_RST_CON_ADDR
ldr r1, =CRU_FST_RST_PMU_VAL
str r1, [r0]
/* clear pmu reset hold */
ldr r0, =RV1106_PMUGRF_SOC_CON4
ldr r1, =0xffff0000

4
arch/arm64/boot/dts/rockchip/px30-dram-default-timing.dtsi
View File

@ -70,8 +70,8 @@
phy_lpddr4_dq_drv = <PHY_DDR4_LPDDR3_2_RON_RTT_80ohm>;
phy_lpddr4_odt = <PHY_DDR4_LPDDR3_2_RON_RTT_60ohm>;
ddr4_odt_dis_freq = <666>;
phy_ddr4_odt_dis_freq = <666>;
ddr4_odt_dis_freq = <625>;
phy_ddr4_odt_dis_freq = <625>;
ddr4_drv = <DDR4_DS_34ohm>;
ddr4_odt = <DDR4_RTT_NOM_240ohm>;
phy_ddr4_ca_drv = <PHY_DDR4_LPDDR3_2_RON_RTT_34ohm>;

41
arch/arm64/boot/dts/rockchip/px30.dtsi
View File

@ -644,7 +644,7 @@
status = "disabled";
};
reboot-mode {
reboot_mode: reboot-mode {
compatible = "syscon-reboot-mode";
offset = <0x200>;
mode-bootloader = <BOOT_BL_DOWNLOAD>;
@ -2013,11 +2013,11 @@
downdifferential = <20>;
system-status-freq = <
/*system status freq(KHz)*/
SYS_STATUS_NORMAL 528000
SYS_STATUS_NORMAL 666000
SYS_STATUS_REBOOT 450000
SYS_STATUS_SUSPEND 194000
SYS_STATUS_VIDEO_1080P 450000
SYS_STATUS_BOOST 528000
SYS_STATUS_BOOST 666000
SYS_STATUS_ISP 666000
SYS_STATUS_PERFORMANCE 1056000
>;
@ -2087,14 +2087,6 @@
opp-microvolt-L2 = <950000>;
opp-microvolt-L3 = <950000>;
};
opp-528000000 {
opp-hz = /bits/ 64 <528000000>;
opp-microvolt = <975000>;
opp-microvolt-L0 = <975000>;
opp-microvolt-L1 = <975000>;
opp-microvolt-L2 = <950000>;
opp-microvolt-L3 = <950000>;
};
opp-666000000 {
opp-hz = /bits/ 64 <666000000>;
opp-microvolt = <1050000>;
@ -2125,11 +2117,6 @@
opp-hz = /bits/ 64 <328000000>;
opp-microvolt = <950000>;
};
opp-528000000 {
opp-hz = /bits/ 64 <528000000>;
opp-microvolt = <950000>;
status = "disabled";
};
opp-666000000 {
opp-hz = /bits/ 64 <666000000>;
opp-microvolt = <950000>;
@ -2636,27 +2623,27 @@
i2s0 {
i2s0_8ch_mclk: i2s0-8ch-mclk {
rockchip,pins =
<3 RK_PC1 2 &pcfg_pull_none>;
<3 RK_PC1 2 &pcfg_pull_none_smt>;
};
i2s0_8ch_sclktx: i2s0-8ch-sclktx {
rockchip,pins =
<3 RK_PC3 2 &pcfg_pull_none>;
<3 RK_PC3 2 &pcfg_pull_none_smt>;
};
i2s0_8ch_sclkrx: i2s0-8ch-sclkrx {
rockchip,pins =
<3 RK_PB4 2 &pcfg_pull_none>;
<3 RK_PB4 2 &pcfg_pull_none_smt>;
};
i2s0_8ch_lrcktx: i2s0-8ch-lrcktx {
rockchip,pins =
<3 RK_PC2 2 &pcfg_pull_none>;
<3 RK_PC2 2 &pcfg_pull_none_smt>;
};
i2s0_8ch_lrckrx: i2s0-8ch-lrckrx {
rockchip,pins =
<3 RK_PB5 2 &pcfg_pull_none>;
<3 RK_PB5 2 &pcfg_pull_none_smt>;
};
i2s0_8ch_sdo0: i2s0-8ch-sdo0 {
@ -2703,17 +2690,17 @@
i2s1 {
i2s1_2ch_mclk: i2s1-2ch-mclk {
rockchip,pins =
<2 RK_PC3 1 &pcfg_pull_none>;
<2 RK_PC3 1 &pcfg_pull_none_smt>;
};
i2s1_2ch_sclk: i2s1-2ch-sclk {
rockchip,pins =
<2 RK_PC2 1 &pcfg_pull_none>;
<2 RK_PC2 1 &pcfg_pull_none_smt>;
};
i2s1_2ch_lrck: i2s1-2ch-lrck {
rockchip,pins =
<2 RK_PC1 1 &pcfg_pull_none>;
<2 RK_PC1 1 &pcfg_pull_none_smt>;
};
i2s1_2ch_sdi: i2s1-2ch-sdi {
@ -2730,17 +2717,17 @@
i2s2 {
i2s2_2ch_mclk: i2s2-2ch-mclk {
rockchip,pins =
<3 RK_PA1 2 &pcfg_pull_none>;
<3 RK_PA1 2 &pcfg_pull_none_smt>;
};
i2s2_2ch_sclk: i2s2-2ch-sclk {
rockchip,pins =
<3 RK_PA2 2 &pcfg_pull_none>;
<3 RK_PA2 2 &pcfg_pull_none_smt>;
};
i2s2_2ch_lrck: i2s2-2ch-lrck {
rockchip,pins =
<3 RK_PA3 2 &pcfg_pull_none>;
<3 RK_PA3 2 &pcfg_pull_none_smt>;
};
i2s2_2ch_sdi: i2s2-2ch-sdi {

10
arch/arm64/boot/dts/rockchip/px30s-dram-default-timing.dtsi
View File

@ -310,12 +310,12 @@
dram_dll_dis_freq = <IGNORE_THIS>;
phy_dll_dis_freq = <IGNORE_THIS>;
/* drv when odt on */
phy_dq_drv_odten = <35>;
phy_dq_drv_odten = <44>;
phy_ca_drv_odten = <38>;
phy_clk_drv_odten = <47>;
dram_dq_drv_odten = <40>;
/* drv when odt off */
phy_dq_drv_odtoff = <35>;
phy_dq_drv_odtoff = <44>;
phy_ca_drv_odtoff = <38>;
phy_clk_drv_odtoff = <47>;
dram_dq_drv_odtoff = <40>;
@ -328,11 +328,11 @@
dram_dq_odt_en_freq = <800>;
phy_odt_en_freq = <800>;
/* slew rate when odt enable */
phy_dq_sr_odten = <0x0>;
phy_dq_sr_odten = <0x7>;
phy_ca_sr_odten = <0x1>;
phy_clk_sr_odten = <0x1>;
/* slew rate when odt disable */
phy_dq_sr_odtoff = <0x0>;
phy_dq_sr_odtoff = <0x7>;
phy_ca_sr_odtoff = <0x1>;
phy_clk_sr_odtoff = <0x1>;
/* ssmod setting*/
@ -371,7 +371,7 @@
lp4_dq_vref_odten = <276>;
lp4_ca_vref_odten = <380>;
/* lp4 vref info when odt disable */
phy_lp4_dq_vref_odtoff = <340>;
phy_lp4_dq_vref_odtoff = <420>;
lp4_dq_vref_odtoff = <420>;
lp4_ca_vref_odtoff = <420>;
};

30
arch/arm64/boot/dts/rockchip/rk1808.dtsi
View File

@ -247,6 +247,12 @@
#clock-cells = <0>;
};
mipi_csi2: mipi-csi2 {
compatible = "rockchip,rk1808-mipi-csi2";
rockchip,hw = <&mipi_csi2_hw>;
status = "disabled";
};
psci {
compatible = "arm,psci-1.0";
method = "smc";
@ -372,13 +378,15 @@
phy-names = "usb2-phy", "usb3-phy";
phy_type = "utmi_wide";
snps,dis_enblslpm_quirk;
snps,dis-u1u2-quirk;
snps,dis-u1-entry-quirk;
snps,dis-u2-entry-quirk;
snps,dis-u2-freeclk-exists-quirk;
snps,dis_u2_susphy_quirk;
snps,dis_u3_susphy_quirk;
snps,dis-del-phy-power-chg-quirk;
snps,tx-ipgap-linecheck-dis-quirk;
snps,xhci-trb-ent-quirk;
snps,parkmode-disable-hs-quirk;
snps,parkmode-disable-ss-quirk;
status = "disabled";
};
@ -1525,8 +1533,8 @@
status = "disabled";
};
mipi_csi2: mipi-csi2@ffb10000 {
compatible = "rockchip,rk1808-mipi-csi2";
mipi_csi2_hw: mipi-csi2-hw@ffb10000 {
compatible = "rockchip,rk1808-mipi-csi2-hw";
reg = <0x0 0xffb10000 0x0 0x100>;
reg-names = "csihost_regs";
interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
@ -2246,15 +2254,15 @@
i2s1 {
i2s1_2ch_lrck: i2s1-2ch-lrck {
rockchip,pins =
<3 RK_PA0 1 &pcfg_pull_none_2ma>;
<3 RK_PA0 1 &pcfg_pull_none_2ma_smt>;
};
i2s1_2ch_sclk: i2s1-2ch-sclk {
rockchip,pins =
<3 RK_PA1 1 &pcfg_pull_none_2ma>;
<3 RK_PA1 1 &pcfg_pull_none_2ma_smt>;
};
i2s1_2ch_mclk: i2s1-2ch-mclk {
rockchip,pins =
<3 RK_PA2 1 &pcfg_pull_none_2ma>;
<3 RK_PA2 1 &pcfg_pull_none_2ma_smt>;
};
i2s1_2ch_sdo: i2s1-2ch-sdo {
rockchip,pins =
@ -2281,11 +2289,11 @@
};
i2s0_8ch_sclkrx: i2s0-8ch-sclkrx {
rockchip,pins =
<3 RK_PB0 1 &pcfg_pull_none_2ma>;
<3 RK_PB0 1 &pcfg_pull_none_2ma_smt>;
};
i2s0_8ch_lrckrx: i2s0-8ch-lrckrx {
rockchip,pins =
<3 RK_PB1 1 &pcfg_pull_none_2ma>;
<3 RK_PB1 1 &pcfg_pull_none_2ma_smt>;
};
i2s0_8ch_sdo3: i2s0-8ch-sdo3 {
rockchip,pins =
@ -2301,15 +2309,15 @@
};
i2s0_8ch_mclk: i2s0-8ch-mclk {
rockchip,pins =
<3 RK_PB5 1 &pcfg_pull_none_2ma>;
<3 RK_PB5 1 &pcfg_pull_none_2ma_smt>;
};
i2s0_8ch_lrcktx: i2s0-8ch-lrcktx {
rockchip,pins =
<3 RK_PB6 1 &pcfg_pull_none_2ma>;
<3 RK_PB6 1 &pcfg_pull_none_2ma_smt>;
};
i2s0_8ch_sclktx: i2s0-8ch-sclktx {
rockchip,pins =
<3 RK_PB7 1 &pcfg_pull_none_2ma>;
<3 RK_PB7 1 &pcfg_pull_none_2ma_smt>;
};
i2s0_8ch_sdo0: i2s0-8ch-sdo0 {
rockchip,pins =

6
arch/arm64/boot/dts/rockchip/rk3308-ai-va-v10.dts
View File

@ -620,6 +620,12 @@
};
};
wireless-bluetooth {
uart4_gpios: uart4-gpios {
rockchip,pins = <4 RK_PA7 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
wireless-wlan {
wifi_wake_host: wifi-wake-host {
rockchip,pins = <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up>;

4
arch/arm64/boot/dts/rockchip/rk3308-evb-amic-v11.dts
View File

@ -42,10 +42,6 @@
#sound-dai-cells = <0>;
};
&is31fl3236 {
reg = <0x3f>;
};
&vad {
status = "okay";
rockchip,audio-src = <&i2s_8ch_2>;

52
arch/arm64/boot/dts/rockchip/rk3308-evb-amic-v13.dts Normal file
View File

@ -0,0 +1,52 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (c) 2023 Rockchip Electronics Co., Ltd
*/
/dts-v1/;
#include "rk3308-evb-v13.dtsi"
/ {
model = "Rockchip RK3308 evb analog mic v13 board";
compatible = "rockchip,rk3308-evb-amic-v13", "rockchip,rk3308";
vad_acodec_sound: vad-acodec-sound {
status = "okay";
compatible = "rockchip,multicodecs-card";
rockchip,card-name = "rockchip,rk3308-vad";
rockchip,codec-hp-det;
rockchip,mclk-fs = <256>;
rockchip,cpu = <&i2s_8ch_2>;
rockchip,codec = <&acodec>, <&vad>;
};
};
&acodec {
rockchip,micbias1;
rockchip,micbias2;
rockchip,en-always-grps = <1 2 3>;
rockchip,adc-grps-route = <1 2 3 0>;
};
&acodec_sound {
status = "disabled";
};
&bluetooth_sound {
status = "okay";
};
&i2s_2ch_0 {
status = "okay";
#sound-dai-cells = <0>;
};
&vad {
status = "okay";
rockchip,audio-src = <&i2s_8ch_2>;
rockchip,det-channel = <0>;
rockchip,buffer-time-ms = <200>;
rockchip,mode = <1>;
#sound-dai-cells = <0>;
};

92
arch/arm64/boot/dts/rockchip/rk3308-evb-dmic-pdm-v13.dts Normal file
View File

@ -0,0 +1,92 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (c) 2023 Rockchip Electronics Co., Ltd
*/
/dts-v1/;
#include "rk3308-evb-v13.dtsi"
/ {
model = "Rockchip RK3308 evb digital-pdm mic v13 board";
compatible = "rockchip,rk3308-evb-dmic-pdm-v13", "rockchip,rk3308";
pdm_i2s_dais: pdm-i2s-dais {
status = "okay";
compatible = "rockchip,rk3308-multi-dais", "rockchip,multi-dais";
dais = <&pdm_8ch>, <&i2s_8ch_2>;
capture,channel-mapping = <6 2>;
playback,channel-mapping = <0 2>;
bitclock-inversion = <1 0>;
};
pdm-mic-array {
status = "disabled";
compatible = "simple-audio-card";
simple-audio-card,name = "rockchip,pdm-mic-array";
simple-audio-card,cpu {
sound-dai = <&pdm_8ch>;
};
simple-audio-card,codec {
sound-dai = <&dummy_codec>;
};
};
vad-sound {
status = "okay";
compatible = "rockchip,multicodecs-card";
rockchip,card-name = "rockchip,rk3308-vad";
rockchip,cpu = <&pdm_i2s_dais>;
rockchip,codec = <&acodec>, <&vad>;
};
};
&rk_timer_rtc {
status = "okay";
};
&acodec_sound {
status = "disabled";
};
&bluetooth_sound {
status = "okay";
};
&i2s_2ch_0 {
status = "okay";
#sound-dai-cells = <0>;
};
&pdm_8ch {
status = "okay";
#sound-dai-cells = <0>;
rockchip,no-dmaengine;
pinctrl-names = "default";
pinctrl-0 = <&pdm_m2_clk
&pdm_m2_clkm
&pdm_m2_sdi0
&pdm_m2_sdi1
&pdm_m2_sdi2
&pdm_m2_sdi3>;
};
&vad {
status = "okay";
rockchip,audio-src = <&pdm_8ch>;
rockchip,det-channel = <0>;
rockchip,mode = <1>;
rockchip,buffer-time-ms = <200>;
#sound-dai-cells = <0>;
};
&i2s_8ch_2 {
status = "okay";
rockchip,no-dmaengine;
#sound-dai-cells = <0>;
};
&pdm_i2s_dais {
status = "okay";
#sound-dai-cells = <0>;
};

270
arch/arm64/boot/dts/rockchip/rk3308-evb-ext-v10.dtsi
View File

@ -45,143 +45,171 @@
default-brightness-level = <200>;
};
panel: panel {
compatible = "simple-panel";
bus-format = <MEDIA_BUS_FMT_RGB666_1X18>;
backlight = <&backlight>;
enable-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_LOW>;
enable-delay-ms = <20>;
reset-gpios = <&gpio0 RK_PC4 GPIO_ACTIVE_LOW>;
reset-delay-ms = <10>;
prepare-delay-ms = <20>;
unprepare-delay-ms = <20>;
disable-delay-ms = <20>;
/* spi-sdo-gpios = <&gpio3 RK_PD2 GPIO_ACTIVE_HIGH>; */
spi-sdi-gpios = <&gpio1 RK_PC7 GPIO_ACTIVE_HIGH>;
spi-scl-gpios = <&gpio1 RK_PD0 GPIO_ACTIVE_HIGH>;
spi-cs-gpios = <&gpio1 RK_PD1 GPIO_ACTIVE_HIGH>;
width-mm = <217>;
height-mm = <136>;
status = "okay";
spi_gpio: spi-gpio {
compatible = "spi-gpio";
#address-cells = <0x1>;
#size-cells = <0x0>;
pinctrl-names = "default";
pinctrl-0 = <&spi_init_cmd>;
rockchip,cmd-type = "spi";
pinctrl-0 = <&spi_pins>;
spi-delay-us = <10>;
status = "okay";
/* type:0 is cmd, 1 is data */
panel-init-sequence = [
/* type delay num val1 val2 val3 */
00 00 01 e0
01 00 01 00
01 00 01 07
01 00 01 0f
01 00 01 0d
01 00 01 1b
01 00 01 0a
01 00 01 3c
01 00 01 78
01 00 01 4a
01 00 01 07
01 00 01 0e
01 00 01 09
01 00 01 1b
01 00 01 1e
01 00 01 0f
00 00 01 e1
01 00 01 00
01 00 01 22
01 00 01 24
01 00 01 06
01 00 01 12
01 00 01 07
01 00 01 36
01 00 01 47
01 00 01 47
01 00 01 06
01 00 01 0a
01 00 01 07
01 00 01 30
01 00 01 37
01 00 01 0f
sck-gpios = <&gpio1 RK_PD0 GPIO_ACTIVE_HIGH>;
miso-gpios = <&gpio3 RK_PD2 GPIO_ACTIVE_HIGH>;
mosi-gpios = <&gpio1 RK_PC7 GPIO_ACTIVE_HIGH>;
cs-gpios = <&gpio1 RK_PD1 GPIO_ACTIVE_HIGH>;
num-chipselects = <1>;
00 00 01 c0
01 00 01 10
01 00 01 10
/*
* 320x480 RGB/MCU screen K350C4516T
*/
panel: panel {
compatible = "simple-panel-spi";
reg = <0>;
bus-format = <MEDIA_BUS_FMT_RGB666_1X18>;
backlight = <&backlight>;
enable-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_LOW>;
enable-delay-ms = <20>;
reset-gpios = <&gpio0 RK_PC4 GPIO_ACTIVE_LOW>;
reset-delay-ms = <10>;
prepare-delay-ms = <20>;
unprepare-delay-ms = <20>;
disable-delay-ms = <20>;
init-delay-ms = <10>;
width-mm = <217>;
height-mm = <136>;
rockchip,cmd-type = "spi";
status = "okay";
00 00 01 c1
01 00 01 41
// type:0 is cmd, 1 is data
panel-init-sequence = [
/* type delay num val1 val2 val3 */
00 00 01 e0
01 00 01 00
01 00 01 07
01 00 01 0f
01 00 01 0d
01 00 01 1b
01 00 01 0a
01 00 01 3c
01 00 01 78
01 00 01 4a
01 00 01 07
01 00 01 0e
01 00 01 09
01 00 01 1b
01 00 01 1e
01 00 01 0f
00 00 01 e1
01 00 01 00
01 00 01 22
01 00 01 24
01 00 01 06
01 00 01 12
01 00 01 07
01 00 01 36
01 00 01 47
01 00 01 47
01 00 01 06
01 00 01 0a
01 00 01 07
01 00 01 30
01 00 01 37
01 00 01 0f
00 00 01 c5
01 00 01 00
01 00 01 22
01 00 01 80
00 00 01 c0
01 00 01 10
01 00 01 10
00 00 01 36
01 00 01 48
00 00 01 c1
01 00 01 41
00 00 01 3a /* interface mode control */
01 00 01 66
00 00 01 c5
01 00 01 00
01 00 01 22
01 00 01 80
00 00 01 b0 /* interface mode control */
01 00 01 00
00 00 01 36
01 00 01 48
00 00 01 b1 /* frame rate 70hz */
01 00 01 b0
01 00 01 11
00 00 01 b4
01 00 01 02
00 00 01 B6 /* RGB/MCU Interface Control */
01 00 01 32 /* 02 mcu, 32 rgb */
01 00 01 02
00 00 01 3a
01 00 01 66 /*
* interface pixel format:
* 66 for RGB666(18bit)
*/
00 00 01 b7
01 00 01 c6
00 00 01 b0
01 00 01 00
00 00 01 be
01 00 01 00
01 00 01 04
00 00 01 b1
01 00 01 a0 /*
* frame rate control:
* a0 (60hz) for RGB666(18bit)
*/
01 00 01 11
00 00 01 b4
01 00 01 02
00 00 01 B6
01 00 01 32 /*
* display function control:
* 32 for RGB
* 02 for MCU
*/
01 00 01 02
00 00 01 e9
01 00 01 00
00 00 01 b7
01 00 01 c6
00 00 01 f7
01 00 01 a9
01 00 01 51
01 00 01 2c
01 00 01 82
00 00 01 be
01 00 01 00
01 00 01 04
00 78 01 11
00 00 01 29
];
00 00 01 e9
01 00 01 00
panel-exit-sequence = [
/* type delay num val1 val2 val3 */
00 0a 01 28
00 78 01 10
];
00 00 01 f7
01 00 01 a9
01 00 01 51
01 00 01 2c
01 00 01 82
display-timings {
native-mode = <&kd050fwfba002_timing>;
00 78 01 11
00 00 01 29
];
kd050fwfba002_timing: timing0 {
clock-frequency = <12000000>;
hactive = <320>;
vactive = <480>;
hback-porch = <10>;
hfront-porch = <5>;
vback-porch = <10>;
vfront-porch = <5>;
hsync-len = <10>;
vsync-len = <10>;
hsync-active = <0>;
vsync-active = <0>;
de-active = <0>;
pixelclk-active = <0>;
panel-exit-sequence = [
//type delay num val1 val2 val3
00 0a 01 28
00 78 01 10
];
display-timings {
native-mode = <&kd050fwfba002_timing>;
kd050fwfba002_timing: timing0 {
/*
* 10453500 for RGB666(18bit)
*/
clock-frequency = <10453500>;
hactive = <320>;
vactive = <480>;
hback-porch = <10>;
hfront-porch = <5>;
vback-porch = <10>;
vfront-porch = <5>;
hsync-len = <10>;
vsync-len = <10>;
hsync-active = <0>;
vsync-active = <0>;
de-active = <0>;
pixelclk-active = <1>;
};
};
};
port {
panel_in_rgb: endpoint {
remote-endpoint = <&rgb_out_panel>;
port {
panel_in_rgb: endpoint {
remote-endpoint = <&rgb_out_panel>;
};
};
};
};
@ -192,9 +220,11 @@
};
&pinctrl {
spi_panel {
spi_init_cmd: spi-init-cmd {
soft_spi {
spi_pins: spi-pins {
rockchip,pins =
/* spi sdo */
<3 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>,
/* spi sdi */
<1 RK_PC7 RK_FUNC_GPIO &pcfg_pull_none>,
/* spi scl */

7
arch/arm64/boot/dts/rockchip/rk3308-evb-v10.dtsi
View File

@ -738,6 +738,13 @@
rockchip,pins = <0 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
wireless-bluetooth {
uart4_gpios: uart4-gpios {
rockchip,pins = <4 RK_PA7 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
};
&pwm0 {

10
arch/arm64/boot/dts/rockchip/rk3308-evb-v11.dtsi
View File

@ -373,9 +373,9 @@
reset-gpios = <&gpio1 RK_PA1 GPIO_ACTIVE_LOW>;
};
is31fl3236: led-controller@3c {
is31fl3236: led-controller@3f {
compatible = "issi,is31fl3236";
reg = <0x3c>;
reg = <0x3f>;
#address-cells = <1>;
#size-cells = <0>;
reset-gpios = <&gpio0 RK_PB0 GPIO_ACTIVE_HIGH>;
@ -797,6 +797,12 @@
};
};
wireless-bluetooth {
uart4_gpios: uart4-gpios {
rockchip,pins = <4 RK_PA7 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
wireless-wlan {
wifi_wake_host: wifi-wake-host {
rockchip,pins = <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up>;

23
arch/arm64/boot/dts/rockchip/rk3308-evb-v13.dtsi Normal file
View File

@ -0,0 +1,23 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (c) 2023 Rockchip Electronics Co., Ltd
*/
#include <dt-bindings/input/input.h>
#include "rk3308-evb-v11.dtsi"
/ {
model = "Rockchip RK3308 EVB V13";
compatible = "rockchip,rk3308-evb-v13", "rockchip,rk3308";
/delete-node/ wireless-wlan;
wireless-wlan {
compatible = "wlan-platdata";
rockchip,grf = <&grf>;
pinctrl-names = "default";
pinctrl-0 = <&wifi_wake_host>, <&rtc_32k>;
wifi_chip_type = "ap6256";
WIFI,host_wake_irq = <&gpio2 RK_PB4 GPIO_ACTIVE_HIGH>;
status = "okay";
};
};

38
arch/arm64/boot/dts/rockchip/rk3308.dtsi
View File

@ -281,7 +281,7 @@
route_rgb: route-rgb {
status = "disabled";
logo,uboot = "logo.bmp";
/* logo,kernel = "logo_kernel.bmp"; */
logo,kernel = "logo_kernel.bmp";
logo,mode = "center";
charge_logo,mode = "center";
connect = <&vop_out_rgb>;
@ -1812,17 +1812,17 @@
i2s_2ch_0 {
i2s_2ch_0_mclk: i2s-2ch-0-mclk {
rockchip,pins =
<4 RK_PB4 1 &pcfg_pull_none>;
<4 RK_PB4 1 &pcfg_pull_none_smt>;
};
i2s_2ch_0_sclk: i2s-2ch-0-sclk {
rockchip,pins =
<4 RK_PB5 1 &pcfg_pull_none>;
<4 RK_PB5 1 &pcfg_pull_none_smt>;
};
i2s_2ch_0_lrck: i2s-2ch-0-lrck {
rockchip,pins =
<4 RK_PB6 1 &pcfg_pull_none>;
<4 RK_PB6 1 &pcfg_pull_none_smt>;
};
i2s_2ch_0_sdo: i2s-2ch-0-sdo {
@ -1839,27 +1839,27 @@
i2s_8ch_0 {
i2s_8ch_0_mclk: i2s-8ch-0-mclk {
rockchip,pins =
<2 RK_PA4 1 &pcfg_pull_none>;
<2 RK_PA4 1 &pcfg_pull_none_smt>;
};
i2s_8ch_0_sclktx: i2s-8ch-0-sclktx {
rockchip,pins =
<2 RK_PA5 1 &pcfg_pull_none>;
<2 RK_PA5 1 &pcfg_pull_none_smt>;
};
i2s_8ch_0_sclkrx: i2s-8ch-0-sclkrx {
rockchip,pins =
<2 RK_PA6 1 &pcfg_pull_none>;
<2 RK_PA6 1 &pcfg_pull_none_smt>;
};
i2s_8ch_0_lrcktx: i2s-8ch-0-lrcktx {
rockchip,pins =
<2 RK_PA7 1 &pcfg_pull_none>;
<2 RK_PA7 1 &pcfg_pull_none_smt>;
};
i2s_8ch_0_lrckrx: i2s-8ch-0-lrckrx {
rockchip,pins =
<2 RK_PB0 1 &pcfg_pull_none>;
<2 RK_PB0 1 &pcfg_pull_none_smt>;
};
i2s_8ch_0_sdo0: i2s-8ch-0-sdo0 {
@ -1906,27 +1906,27 @@
i2s_8ch_1_m0 {
i2s_8ch_1_m0_mclk: i2s-8ch-1-m0-mclk {
rockchip,pins =
<1 RK_PA2 2 &pcfg_pull_none>;
<1 RK_PA2 2 &pcfg_pull_none_smt>;
};
i2s_8ch_1_m0_sclktx: i2s-8ch-1-m0-sclktx {
rockchip,pins =
<1 RK_PA3 2 &pcfg_pull_none>;
<1 RK_PA3 2 &pcfg_pull_none_smt>;
};
i2s_8ch_1_m0_sclkrx: i2s-8ch-1-m0-sclkrx {
rockchip,pins =
<1 RK_PA4 2 &pcfg_pull_none>;
<1 RK_PA4 2 &pcfg_pull_none_smt>;
};
i2s_8ch_1_m0_lrcktx: i2s-8ch-1-m0-lrcktx {
rockchip,pins =
<1 RK_PA5 2 &pcfg_pull_none>;
<1 RK_PA5 2 &pcfg_pull_none_smt>;
};
i2s_8ch_1_m0_lrckrx: i2s-8ch-1-m0-lrckrx {
rockchip,pins =
<1 RK_PA6 2 &pcfg_pull_none>;
<1 RK_PA6 2 &pcfg_pull_none_smt>;
};
i2s_8ch_1_m0_sdo0: i2s-8ch-1-m0-sdo0 {
@ -1958,27 +1958,27 @@
i2s_8ch_1_m1 {
i2s_8ch_1_m1_mclk: i2s-8ch-1-m1-mclk {
rockchip,pins =
<1 RK_PB4 2 &pcfg_pull_none>;
<1 RK_PB4 2 &pcfg_pull_none_smt>;
};
i2s_8ch_1_m1_sclktx: i2s-8ch-1-m1-sclktx {
rockchip,pins =
<1 RK_PB5 2 &pcfg_pull_none>;
<1 RK_PB5 2 &pcfg_pull_none_smt>;
};
i2s_8ch_1_m1_sclkrx: i2s-8ch-1-m1-sclkrx {
rockchip,pins =
<1 RK_PB6 2 &pcfg_pull_none>;
<1 RK_PB6 2 &pcfg_pull_none_smt>;
};
i2s_8ch_1_m1_lrcktx: i2s-8ch-1-m1-lrcktx {
rockchip,pins =
<1 RK_PB7 2 &pcfg_pull_none>;
<1 RK_PB7 2 &pcfg_pull_none_smt>;
};
i2s_8ch_1_m1_lrckrx: i2s-8ch-1-m1-lrckrx {
rockchip,pins =
<1 RK_PC0 2 &pcfg_pull_none>;
<1 RK_PC0 2 &pcfg_pull_none_smt>;
};
i2s_8ch_1_m1_sdo0: i2s-8ch-1-m1-sdo0 {

4
arch/arm64/boot/dts/rockchip/rk3308b-amp.dtsi
View File

@ -3,6 +3,8 @@
* Copyright (c) 2023 Rockchip Electronics Co., Ltd.
*/
#include <dt-bindings/soc/rockchip-amp.h>
/ {
rockchip_amp: rockchip-amp {
compatible = "rockchip,amp";
@ -12,6 +14,8 @@
pinctrl-names = "default";
pinctrl-0 = <&uart1_xfer>;
status = "okay";
amp-cpu-aff-maskbits = <0x0 0x1 0x1 0x2 0x2 0x4 0x3 0x8>;
amp-irqs = <GIC_AMP_IRQ_CFG_ROUTE(51, 0xd0, CPU_GET_AFFINITY(3, 0))>;
};
reserved-memory {

4
arch/arm64/boot/dts/rockchip/rk3308b-evb-amic-v10.dts
View File

@ -48,10 +48,6 @@
&i2s_8ch_0_sdo2>;
};
&is31fl3236 {
reg = <0x3f>;
};
&vad {
status = "okay";
rockchip,audio-src = <&i2s_8ch_2>;

10
arch/arm64/boot/dts/rockchip/rk3308b-evb-v10.dtsi
View File

@ -317,9 +317,9 @@
clock-frequency = <400000>;
status = "okay";
is31fl3236: led-controller@3c {
is31fl3236: led-controller@3f {
compatible = "issi,is31fl3236";
reg = <0x3c>;
reg = <0x3f>;
#address-cells = <1>;
#size-cells = <0>;
reset-gpios = <&gpio0 RK_PB0 GPIO_ACTIVE_HIGH>;
@ -701,6 +701,12 @@
};
};
wireless-bluetooth {
uart0_gpios: uart0-gpios {
rockchip,pins = <2 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
wireless-wlan {
wifi_wake_host: wifi-wake-host {
rockchip,pins = <2 RK_PB4 RK_FUNC_GPIO &pcfg_pull_up>;

122
arch/arm64/boot/dts/rockchip/rk3308bs-evb-ext-mcu-v10.dtsi
View File

@ -45,8 +45,40 @@
default-brightness-level = <200>;
};
panel: panel {
compatible = "simple-panel";
reserved-memory {
#address-cells = <2>;
#size-cells = <2>;
ranges;
cma {
compatible = "shared-dma-pool";
reusable;
size = <0x0 0x800000>;
linux,cma-default;
};
};
};
&display_subsystem {
status = "okay";
};
&pwm1 {
status = "okay";
};
&rgb {
status = "okay";
rockchip,data-sync-bypass;
/*
* 320x480 RGB/MCU screen K350C4516T
*/
mcu_panel: mcu-panel {
/*
* MEDIA_BUS_FMT_RGB888_3X8 for RGB3x8(8bit)
* MEDIA_BUS_FMT_RGB565_1X16 for RGB565(16bit)
*/
bus-format = <MEDIA_BUS_FMT_RGB565_1X16>;
backlight = <&backlight>;
enable-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_LOW>;
@ -59,8 +91,6 @@
disable-delay-ms = <20>;
width-mm = <217>;
height-mm = <136>;
status = "okay";
rockchip,cmd-type = "mcu";
// type:0 is cmd, 1 is data
panel-init-sequence = [
@ -113,19 +143,31 @@
00 00 01 36
01 00 01 48
00 00 01 3a //interface mode control
01 00 01 55 //spi rgb:66(r1 r4 r5), mcu: 55(r2, r3 r6)
00 00 01 3a
01 00 01 55 /*
* interface pixel format:
* 66 for RGB3x8(8bit)
* 55 for RGB565(16bit)
*/
00 00 01 b0 //interface mode control
00 00 01 b0
01 00 01 00
00 00 01 b1 //frame rate 70hz
01 00 01 b0
00 00 01 b1
01 00 01 a0 /*
* frame rate control:
* 70 (45hz) for RGB3x8(8bit)
* a0 (60hz) for RGB565(16bit)
*/
01 00 01 11
00 00 01 b4
01 00 01 02
00 00 01 B6 //RGB/MCU Interface Control
01 00 01 02 //02 mcu, 32 rgb
00 00 01 B6
01 00 01 02 /*
* display function control:
* 32 for RGB
* 02 for MCU
*/
01 00 01 02
00 00 01 b7
@ -159,7 +201,11 @@
native-mode = <&kd050fwfba002_timing>;
kd050fwfba002_timing: timing0 {
clock-frequency = <20000000>;
/*
* 7840125 for frame rate 45Hz
* 10453500 for frame rate 60Hz
*/
clock-frequency = <10453500>;
hactive = <320>;
vactive = <480>;
hback-porch = <10>;
@ -182,35 +228,6 @@
};
};
reserved-memory {
#address-cells = <2>;
#size-cells = <2>;
ranges;
cma {
compatible = "shared-dma-pool";
reusable;
size = <0x0 0x800000>;
linux,cma-default;
};
};
};
&display_subsystem {
status = "okay";
};
&route_rgb {
status = "okay";
};
&pwm1 {
status = "okay";
};
&rgb {
status = "okay";
ports {
rgb_out: port@1 {
reg = <1>;
@ -225,15 +242,32 @@
};
};
&route_rgb {
status = "okay";
};
&vop {
status = "okay";
/*
* Default config is as follows:
*
* mcu-pix-total = <9>;
* mcu-cs-pst = <1>;
* mcu-cs-pend = <8>;
* mcu-rw-pst = <2>;
* mcu-rw-pend = <5>;
* mcu-hold-mode = <0>; // default set to 0
*
* To increase the frame rate, reduce all parameters because
* the max dclk rate of mcu is 150M in rk3308.
*/
mcu-timing {
mcu-pix-total = <9>;
mcu-pix-total = <5>;
mcu-cs-pst = <1>;
mcu-cs-pend = <8>;
mcu-cs-pend = <4>;
mcu-rw-pst = <2>;
mcu-rw-pend = <5>;
mcu-rw-pend = <3>;
mcu-hold-mode = <0>; // default set to 0
};

16
arch/arm64/boot/dts/rockchip/rk3308bs-evb-mipi-display-v11.dts
View File

@ -18,6 +18,22 @@
status = "disabled";
};
&lcdc_rgb888_m1 {
rockchip,pins =
/* d18 */
<3 RK_PA6 3 &pcfg_pull_none_2ma>,
/* d19 */
<3 RK_PA7 3 &pcfg_pull_none_2ma>,
/* d20 */
<3 RK_PB0 3 &pcfg_pull_none_2ma>,
/* d21 */
<3 RK_PB1 3 &pcfg_pull_none_2ma>,
/* d22 */
<3 RK_PB2 4 &pcfg_pull_none_2ma>,
/* d23 */
<3 RK_PB3 4 &pcfg_pull_none_2ma>;
};
&pdm_8ch {
pinctrl-names = "default";
pinctrl-0 = <&pdm_m2_clk

139
arch/arm64/boot/dts/rockchip/rk3308bs-evb-rgb-display-v20.dts Normal file
View File

@ -0,0 +1,139 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (c) 2022 Rockchip Electronics Co., Ltd
*/
/dts-v1/;
#include "rk3308bs-evb-amic-v11.dts"
/ {
model = "Rockchip RK3308B-S EVB DDR3 V20 Board + Rockchip RK3308 RGB ExtBoard V10";
compatible = "rockchip,rk3308bs-evb-rgb-display-v20", "rockchip,rk3308";
backlight: backlight {
status = "okay";
compatible = "pwm-backlight";
pwms = <&pwm1 0 25000 0>;
brightness-levels = <
0 1 2 3 4 5 6 7
8 9 10 11 12 13 14 15
16 17 18 19 20 21 22 23
24 25 26 27 28 29 30 31
32 33 34 35 36 37 38 39
40 41 42 43 44 45 46 47
48 49 50 51 52 53 54 55
56 57 58 59 60 61 62 63
64 65 66 67 68 69 70 71
72 73 74 75 76 77 78 79
80 81 82 83 84 85 86 87
88 89 90 91 92 93 94 95
96 97 98 99 100 101 102 103
104 105 106 107 108 109 110 111
112 113 114 115 116 117 118 119
120 121 122 123 124 125 126 127
128 129 130 131 132 133 134 135
136 137 138 139 140 141 142 143
144 145 146 147 148 149 150 151
152 153 154 155 156 157 158 159
160 161 162 163 164 165 166 167
168 169 170 171 172 173 174 175
176 177 178 179 180 181 182 183
184 185 186 187 188 189 190 191
192 193 194 195 196 197 198 199
200 201 202 203 204 205 206 207
208 209 210 211 212 213 214 215
216 217 218 219 220 221 222 223
224 225 226 227 228 229 230 231
232 233 234 235 236 237 238 239
240 241 242 243 244 245 246 247
248 249 250 251 252 253 254 255>;
default-brightness-level = <200>;
};
panel: panel {
compatible = "simple-panel";
bus-format = <MEDIA_BUS_FMT_RGB888_1X24>;
backlight = <&backlight>;
enable-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_LOW>;
enable-delay-ms = <20>;
reset-gpios = <&gpio0 RK_PC4 GPIO_ACTIVE_LOW>;
reset-value = <0>;
reset-delay-ms = <10>;
status = "okay";
display-timings {
native-mode = <&fx070_dhm11boe_timing>;
fx070_dhm11boe_timing: timing0 {
clock-frequency = <50000000>;
hactive = <1024>;
vactive = <600>;
hback-porch = <140>;
hfront-porch = <160>;
vback-porch = <20>;
vfront-porch = <20>;
hsync-len = <20>;
vsync-len = <2>; //value range <2~22>
hsync-active = <0>;
vsync-active = <0>;
de-active = <0>;
pixelclk-active = <0>;
};
};
port {
panel_in_rgb: endpoint {
remote-endpoint = <&rgb_out_panel>;
};
};
};
reserved-memory {
#address-cells = <2>;
#size-cells = <2>;
ranges;
cma {
compatible = "shared-dma-pool";
reusable;
size = <0x0 0x800000>;
linux,cma-default;
};
};
};
&display_subsystem {
status = "okay";
};
&pwm1 {
status = "okay";
};
&rgb {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&lcdc_ctl &lcdc_rgb888_m1>;
ports {
rgb_out: port@1 {
reg = <1>;
#address-cells = <1>;
#size-cells = <0>;
rgb_out_panel: endpoint@0 {
reg = <0>;
remote-endpoint = <&panel_in_rgb>;
};
};
};
};
&route_rgb {
status = "okay";
};
&vop {
status = "okay";
};

41
arch/arm64/boot/dts/rockchip/rk3308bs-pinctrl.dtsi
View File

@ -9,6 +9,11 @@
bias-disable;
drive-strength-s = <4>;
};
pcfg_pull_none_0_4ma_smt: pcfg-pull-none-0-4ma-smt {
bias-disable;
drive-strength-s = <4>;
input-schmitt-enable;
};
pcfg_pull_up_0_4ma: pcfg-pull-up-0-4ma {
bias-pull-up;
drive-strength-s = <4>;
@ -127,17 +132,17 @@
i2s_2ch_0 {
i2s_2ch_0_mclk: i2s-2ch-0-mclk {
rockchip,pins =
<4 RK_PB4 1 &pcfg_pull_none>;
<4 RK_PB4 1 &pcfg_pull_none_smt>;
};
i2s_2ch_0_sclk: i2s-2ch-0-sclk {
rockchip,pins =
<4 RK_PB5 1 &pcfg_pull_none>;
<4 RK_PB5 1 &pcfg_pull_none_smt>;
};
i2s_2ch_0_lrck: i2s-2ch-0-lrck {
rockchip,pins =
<4 RK_PB6 1 &pcfg_pull_none_0_4ma>;
<4 RK_PB6 1 &pcfg_pull_none_0_4ma_smt>;
};
i2s_2ch_0_sdo: i2s-2ch-0-sdo {
@ -154,27 +159,27 @@
i2s_8ch_0 {
i2s_8ch_0_mclk: i2s-8ch-0-mclk {
rockchip,pins =
<2 RK_PA4 1 &pcfg_pull_none_0_4ma>;
<2 RK_PA4 1 &pcfg_pull_none_0_4ma_smt>;
};
i2s_8ch_0_sclktx: i2s-8ch-0-sclktx {
rockchip,pins =
<2 RK_PA5 1 &pcfg_pull_none_0_4ma>;
<2 RK_PA5 1 &pcfg_pull_none_0_4ma_smt>;
};
i2s_8ch_0_sclkrx: i2s-8ch-0-sclkrx {
rockchip,pins =
<2 RK_PA6 1 &pcfg_pull_none_0_4ma>;
<2 RK_PA6 1 &pcfg_pull_none_0_4ma_smt>;
};
i2s_8ch_0_lrcktx: i2s-8ch-0-lrcktx {
rockchip,pins =
<2 RK_PA7 1 &pcfg_pull_none_0_4ma>;
<2 RK_PA7 1 &pcfg_pull_none_0_4ma_smt>;
};
i2s_8ch_0_lrckrx: i2s-8ch-0-lrckrx {
rockchip,pins =
<2 RK_PB0 1 &pcfg_pull_none_0_4ma>;
<2 RK_PB0 1 &pcfg_pull_none_0_4ma_smt>;
};
i2s_8ch_0_sdo0: i2s-8ch-0-sdo0 {
@ -222,27 +227,27 @@
i2s_8ch_1_m0 {
i2s_8ch_1_m0_mclk: i2s-8ch-1-m0-mclk {
rockchip,pins =
<1 RK_PA2 2 &pcfg_pull_none_0_4ma>;
<1 RK_PA2 2 &pcfg_pull_none_0_4ma_smt>;
};
i2s_8ch_1_m0_sclktx: i2s-8ch-1-m0-sclktx {
rockchip,pins =
<1 RK_PA3 2 &pcfg_pull_none_0_4ma>;
<1 RK_PA3 2 &pcfg_pull_none_0_4ma_smt>;
};
i2s_8ch_1_m0_sclkrx: i2s-8ch-1-m0-sclkrx {
rockchip,pins =
<1 RK_PA4 2 &pcfg_pull_none_0_4ma>;
<1 RK_PA4 2 &pcfg_pull_none_0_4ma_smt>;
};
i2s_8ch_1_m0_lrcktx: i2s-8ch-1-m0-lrcktx {
rockchip,pins =
<1 RK_PA5 2 &pcfg_pull_none_0_4ma>;
<1 RK_PA5 2 &pcfg_pull_none_0_4ma_smt>;
};
i2s_8ch_1_m0_lrckrx: i2s-8ch-1-m0-lrckrx {
rockchip,pins =
<1 RK_PA6 2 &pcfg_pull_none_0_4ma>;
<1 RK_PA6 2 &pcfg_pull_none_0_4ma_smt>;
};
i2s_8ch_1_m0_sdo0: i2s-8ch-1-m0-sdo0 {
@ -274,27 +279,27 @@
i2s_8ch_1_m1 {
i2s_8ch_1_m1_mclk: i2s-8ch-1-m1-mclk {
rockchip,pins =
<1 RK_PB4 2 &pcfg_pull_none_0_4ma>;
<1 RK_PB4 2 &pcfg_pull_none_0_4ma_smt>;
};
i2s_8ch_1_m1_sclktx: i2s-8ch-1-m1-sclktx {
rockchip,pins =
<1 RK_PB5 2 &pcfg_pull_none_0_4ma>;
<1 RK_PB5 2 &pcfg_pull_none_0_4ma_smt>;
};
i2s_8ch_1_m1_sclkrx: i2s-8ch-1-m1-sclkrx {
rockchip,pins =
<1 RK_PB6 2 &pcfg_pull_none_0_4ma>;
<1 RK_PB6 2 &pcfg_pull_none_0_4ma_smt>;
};
i2s_8ch_1_m1_lrcktx: i2s-8ch-1-m1-lrcktx {
rockchip,pins =
<1 RK_PB7 2 &pcfg_pull_none_0_4ma>;
<1 RK_PB7 2 &pcfg_pull_none_0_4ma_smt>;
};
i2s_8ch_1_m1_lrckrx: i2s-8ch-1-m1-lrckrx {
rockchip,pins =
<1 RK_PC0 2 &pcfg_pull_none_0_4ma>;
<1 RK_PC0 2 &pcfg_pull_none_0_4ma_smt>;
};
i2s_8ch_1_m1_sdo0: i2s-8ch-1-m1-sdo0 {

1
arch/arm64/boot/dts/rockchip/rk3328.dtsi
View File

@ -1003,6 +1003,7 @@
snps,dis-u2-freeclk-exists-quirk;
snps,dis_u2_susphy_quirk;
snps,dis_u3_susphy_quirk;
snps,parkmode-disable-hs-quirk;
snps,parkmode-disable-ss-quirk;
status = "disabled";
};

1
arch/arm64/boot/dts/rockchip/rk3399-evb-ind.dtsi
View File

@ -175,6 +175,7 @@
wifi_chip_type = "ap6354";
sdio_vref = <1800>;
WIFI,host_wake_irq = <&gpio0 3 GPIO_ACTIVE_HIGH>; /* GPIO0_a3 */
WIFI,poweren_gpio = <&gpio0 10 GPIO_ACTIVE_HIGH>;
status = "okay";
};

1
arch/arm64/boot/dts/rockchip/rk3399-evb.dtsi
View File

@ -210,6 +210,7 @@
wifi_chip_type = "ap6354";
sdio_vref = <1800>;
WIFI,host_wake_irq = <&gpio0 3 GPIO_ACTIVE_HIGH>; /* GPIO0_a3 */
WIFI,poweren_gpio = <&gpio0 10 GPIO_ACTIVE_HIGH>;
status = "okay";
};

48
arch/arm64/boot/dts/rockchip/rk3399-excavator-sapphire.dtsi
View File

@ -10,23 +10,34 @@
compatible = "rockchip,rk3399-sapphire-excavator", "rockchip,rk3399";
rt5651_sound: rt5651-sound {
compatible = "simple-audio-card";
simple-audio-card,format = "i2s";
simple-audio-card,name = "realtek,rt5651-codec";
simple-audio-card,mclk-fs = <256>;
simple-audio-card,widgets =
"Microphone", "Mic Jack",
"Headphone", "Headphone Jack";
simple-audio-card,routing =
"Mic Jack", "MICBIAS1",
"IN1P", "Mic Jack",
"Headphone Jack", "HPOL",
"Headphone Jack", "HPOR";
simple-audio-card,cpu {
sound-dai = <&i2s0>;
};
simple-audio-card,codec {
sound-dai = <&rt5651>;
status = "okay";
compatible = "rockchip,multicodecs-card";
rockchip,card-name = "realtek,rt5651-codec";
keyup-threshold-microvolt = <1800000>;
poll-interval = <100>;
spk-con-gpio = <&gpio0 11 GPIO_ACTIVE_HIGH>;
hp-det-gpio = <&gpio4 28 GPIO_ACTIVE_HIGH>;
rockchip,format = "i2s";
rockchip,mclk-fs = <256>;
rockchip,cpu = <&i2s0>;
rockchip,codec = <&rt5651>;
rockchip,audio-routing =
"Headphone", "HPOL",
"Headphone", "HPOR",
"Speaker", "HPOL",
"Speaker", "HPOR",
"Headphone", "Headphone Power",
"Headphone", "Headphone Power",
"Speaker", "Speaker Power",
"Speaker", "Speaker Power",
"IN1P", "Main Mic",
"IN2P", "Headset Mic",
"IN2N", "Headset Mic",
"Headset Mic", "micbias1";
play-pause-key {
label = "playpause";
linux,code = <KEY_PLAYPAUSE>;
press-threshold-microvolt = <2000>;
};
};
@ -70,6 +81,7 @@
wifi_chip_type = "ap6354";
sdio_vref = <1800>;
WIFI,host_wake_irq = <&gpio0 3 GPIO_ACTIVE_HIGH>; /* GPIO0_a3 */
WIFI,poweren_gpio = <&gpio0 10 GPIO_ACTIVE_HIGH>;
status = "okay";
};
@ -151,8 +163,6 @@
clock-names = "mclk";
pinctrl-names = "default";
pinctrl-0 = <&i2s_8ch_mclk>;
spk-con-gpio = <&gpio0 11 GPIO_ACTIVE_HIGH>;
hp-det-gpio = <&gpio4 28 GPIO_ACTIVE_LOW>;
};
};

4
arch/arm64/boot/dts/rockchip/rk3399-sapphire-excavator-edp-avb.dts
View File

@ -24,9 +24,9 @@
&i2c1 {
status = "okay";
/delete-node/ tc358749x@0f;
/delete-node/ tc358749x@f;
tc35874x: tc35874x@0f {
tc35874x: tc35874x@f {
status = "disabled";
reg = <0x0f>;
compatible = "toshiba,tc358749";

12
arch/arm64/boot/dts/rockchip/rk3399-sapphire-excavator-edp.dtsi
View File

@ -192,7 +192,7 @@
};
};
tc358749x: tc358749x@0f {
tc358749x: tc358749x@f {
compatible = "toshiba,tc358749x";
reg = <0x0f>;
power-gpios = <&gpio2 6 GPIO_ACTIVE_HIGH>;
@ -207,7 +207,7 @@
status = "disabled";
};
vm149c: vm149c@0c {
vm149c: vm149c@c {
compatible = "silicon touch,vm149c";
status = "okay";
reg = <0x0c>;
@ -240,14 +240,6 @@
};
};
vm149c: vm149c@0c {
compatible = "silicon touch,vm149c";
status = "okay";
reg = <0x0c>;
rockchip,camera-module-index = <0>;
rockchip,camera-module-facing = "back";
};
ov13850: ov13850@10 {
compatible = "ovti,ov13850";
status = "okay";

53
arch/arm64/boot/dts/rockchip/rk3399-sapphire-excavator-lp4-linux.dts
View File

@ -11,6 +11,46 @@
model = "Rockchip RK3399 Excavator Board (Linux Opensource)";
compatible = "rockchip,rk3399-excavator-linux", "rockchip,rk3399";
backlight: backlight {
compatible = "pwm-backlight";
brightness-levels = <
0 1 2 3 4 5 6 7
8 9 10 11 12 13 14 15
16 17 18 19 20 21 22 23
24 25 26 27 28 29 30 31
32 33 34 35 36 37 38 39
40 41 42 43 44 45 46 47
48 49 50 51 52 53 54 55
56 57 58 59 60 61 62 63
64 65 66 67 68 69 70 71
72 73 74 75 76 77 78 79
80 81 82 83 84 85 86 87
88 89 90 91 92 93 94 95
96 97 98 99 100 101 102 103
104 105 106 107 108 109 110 111
112 113 114 115 116 117 118 119
120 121 122 123 124 125 126 127
128 129 130 131 132 133 134 135
136 137 138 139 140 141 142 143
144 145 146 147 148 149 150 151
152 153 154 155 156 157 158 159
160 161 162 163 164 165 166 167
168 169 170 171 172 173 174 175
176 177 178 179 180 181 182 183
184 185 186 187 188 189 190 191
192 193 194 195 196 197 198 199
200 201 202 203 204 205 206 207
208 209 210 211 212 213 214 215
216 217 218 219 220 221 222 223
224 225 226 227 228 229 230 231
232 233 234 235 236 237 238 239
240 241 242 243 244 245 246 247
248 249 250 251 252 253 254 255>;
default-brightness-level = <200>;
pwms = <&pwm0 0 25000 0>;
enable-gpios = <&gpio4 29 GPIO_ACTIVE_HIGH>;
};
vcc_lcd: vcc-lcd {
compatible = "regulator-fixed";
regulator-name = "vcc_lcd";
@ -20,7 +60,7 @@
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
vin-supply = <&vcc5v0_sys>;
vin-supply = <&vcc_sys>;
};
panel: panel {
@ -329,17 +369,6 @@
vref-supply = <&vccadc_ref>;
};
&backlight {
status = "okay";
enable-gpios = <&gpio4 29 GPIO_ACTIVE_HIGH>;
};
&cdn_dp {
status = "okay";
extcon = <&fusb0>;
phys = <&tcphy0_dp>;
};
&display_subsystem {
status = "okay";
};

2
arch/arm64/boot/dts/rockchip/rk3399.dtsi
View File

@ -456,6 +456,7 @@
snps,dis_u2_susphy_quirk;
snps,dis-del-phy-power-chg-quirk;
snps,dis-tx-ipgap-linecheck-quirk;
snps,parkmode-disable-hs-quirk;
snps,parkmode-disable-ss-quirk;
power-domains = <&power RK3399_PD_USB3>;
status = "disabled";
@ -493,6 +494,7 @@
snps,dis_u2_susphy_quirk;
snps,dis-del-phy-power-chg-quirk;
snps,dis-tx-ipgap-linecheck-quirk;
snps,parkmode-disable-hs-quirk;
snps,parkmode-disable-ss-quirk;
power-domains = <&power RK3399_PD_USB3>;
status = "disabled";

3
arch/arm64/boot/dts/rockchip/rk3399pro-npu.dtsi
View File

@ -149,7 +149,8 @@
phy-names = "usb2-phy", "usb3-phy";
phy_type = "utmi_wide";
snps,dis_enblslpm_quirk;
snps,dis-u1u2-quirk;
snps,dis-u1-entry-quirk;
snps,dis-u2-entry-quirk;
snps,dis-u2-freeclk-exists-quirk;
snps,dis_u2_susphy_quirk;
snps,dis_u3_susphy_quirk;

18
arch/arm64/boot/dts/rockchip/rk3528-demo4-ddr4-v10-linux.dts Normal file
View File

@ -0,0 +1,18 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (c) 2022 Rockchip Electronics Co., Ltd.
*
*/
#include "rk3528-demo4-ddr4-v10.dtsi"
#include "rk3528-linux.dtsi"
/ {
chosen: chosen {
bootargs = "earlycon=uart8250,mmio32,0xff9f0000 console=ttyFIQ0 root=PARTUUID=614e0000-0000 rw rootwait";
};
};
&sdmmc {
status = "okay";
};

22
arch/arm64/boot/dts/rockchip/rk3528-demo6-ddr3-v10.dts Normal file
View File

@ -0,0 +1,22 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (c) 2023 Rockchip Electronics Co., Ltd.
*
*/
#include "rk3528-demo6-ddr3-v10.dtsi"
#include "rk3528-android.dtsi"
&pdm {
status = "okay";
pinctrl-0 = <&pdm_clk1
&pdm_sdi1>;
};
&pdmics {
status = "okay";
};
&pdm_mic_array {
status = "okay";
};

337
arch/arm64/boot/dts/rockchip/rk3528-demo6-ddr3-v10.dtsi Normal file
View File

@ -0,0 +1,337 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (c) 2023 Rockchip Electronics Co., Ltd.
*
*/
/dts-v1/;
#include "rk3528.dtsi"
#include "rk3528-demo.dtsi"
/ {
model = "Rockchip RK3528 DEMO6 DDR3 V10 Board";
compatible = "rockchip,rk3528-demo6-ddr3-v10", "rockchip,rk3528";
/delete-node/ vcc-ddr-s3;
/delete-node/ vcc-3v3-s3;
/delete-node/ vdd-cpu;
/delete-node/ vdd-logic;
/delete-node/ vdd-0v9-s3;
/delete-node/ vdd-1v8-s3;
/omit-if-no-ref/
vcc_sd: vcc-sd {
compatible = "regulator-fixed";
regulator-boot-on;
gpio = <&gpio4 RK_PA1 GPIO_ACTIVE_LOW>;
regulator-name = "vcc_sd";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
vin-supply = <&vcc_3v3_s3>;
};
sdio_pwrseq: sdio-pwrseq {
compatible = "mmc-pwrseq-simple";
pinctrl-names = "default";
pinctrl-0 = <&wifi_enable_h &clkm1_32k_out>;
reset-gpios = <&gpio1 RK_PA6 GPIO_ACTIVE_LOW>;
};
/omit-if-no-ref/
vccio_sd: vccio-sd {
compatible = "regulator-gpio";
regulator-name = "vccio_sd";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
gpios = <&gpio4 RK_PB6 GPIO_ACTIVE_HIGH>;
vin-supply = <&vcc5v0_sys>;
states = <1800000 0x0
3300000 0x1>;
};
wireless_bluetooth: wireless-bluetooth {
compatible = "bluetooth-platdata";
//wifi-bt-power-toggle;
uart_rts_gpios = <&gpio1 RK_PB2 GPIO_ACTIVE_LOW>;
pinctrl-names = "default", "rts_gpio";
pinctrl-0 = <&uart2m1_rtsn &bt_enable_h>;
pinctrl-1 = <&uart2m1_gpios>;
BT,reset_gpio = <&gpio1 RK_PC1 GPIO_ACTIVE_HIGH>;
BT,wake_gpio = <&gpio1 RK_PB4 GPIO_ACTIVE_HIGH>;
BT,wake_host_irq = <&gpio1 RK_PC2 GPIO_ACTIVE_HIGH>;
status = "okay";
};
wireless_wlan: wireless-wlan {
compatible = "wlan-platdata";
rockchip,grf = <&grf>;
wifi_chip_type = "aic8800";
pinctrl-names = "default";
pinctrl-0 = <&wifi_host_wake_irq >;
WIFI,host_wake_irq = <&gpio1 RK_PA7 GPIO_ACTIVE_HIGH>;
//WIFI,reset_gpio = <&gpio1 RK_PA6 GPIO_ACTIVE_HIGH>;
status = "okay";
};
};
&gmac0 {
status = "disabled";
};
&gmac1 {
/* Use rgmii-rxid mode to disable rx delay inside Soc */
phy-mode = "rgmii-rxid";
clock_in_out = "output";
snps,reset-gpio = <&gpio4 RK_PC2 GPIO_ACTIVE_LOW>;
snps,reset-active-low;
/* Reset time is 20ms, 100ms for rtl8211f */
snps,reset-delays-us = <0 20000 100000>;
tx_delay = <0x30>;
/* rx_delay = <0x3f>; */
pinctrl-names = "default";
pinctrl-0 = <&rgmii_miim
&rgmii_tx_bus2
&rgmii_rx_bus2
&rgmii_rgmii_clk
&rgmii_rgmii_bus
&eth_pins>;
phy-handle = <&rgmii_phy>;
status = "okay";
};
&i2c0 {
status = "okay";
rk805: rk805@18 {
compatible = "rockchip,rk805";
status = "okay";
reg = <0x18>;
interrupt-parent = <&gpio4>;
interrupts = <RK_PB2 IRQ_TYPE_LEVEL_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&pmic_int_l>;
wakeup-source;
gpio-controller;
#gpio-cells = <2>;
#clock-cells = <1>;
clock-output-names = "rk805-clkout1", "rk805-clkout2";
rockchip,system-power-controller;
vcc1-supply = <&vcc5v0_sys>;
vcc2-supply = <&vcc5v0_sys>;
vcc3-supply = <&vcc5v0_sys>;
vcc4-supply = <&vcc5v0_sys>;
vcc5-supply = <&vcc_3v3_s3>;
vcc6-supply = <&vcc5v0_sys>;
rtc {
status = "okay";
};
pwrkey {
status = "disabled";
};
gpio {
status = "okay";
};
regulators {
vdd_cpu: DCDC_REG1 {
regulator-name = "vdd_cpu";
regulator-min-microvolt = <712500>;
regulator-max-microvolt = <1450000>;
regulator-init-microvolt = <953000>;
regulator-initial-mode = <0x1>;
regulator-ramp-delay = <12500>;
regulator-boot-on;
regulator-always-on;
regulator-state-mem {
regulator-off-in-suspend;
};
};
vdd_logic: DCDC_REG2 {
regulator-name = "vdd_logic";
regulator-min-microvolt = <712500>;
regulator-max-microvolt = <1450000>;
regulator-init-microvolt = <900000>;
regulator-initial-mode = <0x1>;
regulator-ramp-delay = <12500>;
regulator-boot-on;
regulator-always-on;
regulator-state-mem {
regulator-mode = <0x2>;
regulator-on-in-suspend;
regulator-suspend-microvolt = <712500>;
};
};
vcc_ddr_s3: DCDC_REG3 {
regulator-name = "vcc_ddr_s3";
regulator-initial-mode = <0x1>;
regulator-boot-on;
regulator-always-on;
regulator-state-mem {
regulator-mode = <0x2>;
regulator-on-in-suspend;
};
};
vcc_3v3_s3: DCDC_REG4 {
regulator-name = "vcc_3v3_s3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-initial-mode = <0x1>;
regulator-boot-on;
regulator-always-on;
regulator-state-mem {
regulator-mode = <0x2>;
regulator-on-in-suspend;
regulator-suspend-microvolt = <3300000>;
};
};
vdd_1v8_s3: LDO_REG1 {
regulator-name = "vdd_1v8_s3";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-boot-on;
regulator-always-on;
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <1800000>;
};
};
vcc_18emmc: LDO_REG2 {
regulator-name = "vcc_18emmc";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-boot-on;
regulator-always-on;
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <1800000>;
};
};
vdd_0v9_s3: LDO_REG3 {
regulator-name = "vdd_0v9_s3";
regulator-min-microvolt = <900000>;
regulator-max-microvolt = <900000>;
regulator-boot-on;
regulator-always-on;
regulator-state-mem {
regulator-on-in-suspend;
regulator-suspend-microvolt = <900000>;
};
};
};
};
};
&mdio1 {
rgmii_phy: phy@1 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <0x1>;
clocks = <&cru CLK_GMAC1_VPU_25M>;
};
};
&pinctrl {
pmic {
pmic_int_l: pmic-int-l {
rockchip,pins =
<4 RK_PB2 RK_FUNC_GPIO &pcfg_pull_up>;
};
};
sdio-pwrseq {
wifi_enable_h: wifi-enable-h {
rockchip,pins = <1 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>;
};
};
wireless-wlan {
wifi_host_wake_irq: wifi-host-wake-irq {
rockchip,pins = <1 RK_PA7 RK_FUNC_GPIO &pcfg_pull_down>;
};
};
wireless-bluetooth {
uart2m1_gpios: uart2m1-gpios {
rockchip,pins = <1 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>;
};
bt_enable_h: bt-enable-h {
rockchip,pins = <1 RK_PC1 RK_FUNC_GPIO &pcfg_pull_down>;
};
};
};
&pwm1 {
status = "disabled";
};
&pwm2 {
status = "disabled";
};
&rockchip_suspend {
status = "okay";
rockchip,sleep-mode-config = <
(0
|RKPM_SLP_ARMOFF
)
>;
};
&sdio0 {
max-frequency = <200000000>;
no-sd;
no-mmc;
supports-sdio;
bus-width = <4>;
disable-wp;
cap-sd-highspeed;
cap-sdio-irq;
keep-power-in-suspend;
non-removable;
mmc-pwrseq = <&sdio_pwrseq>;
pinctrl-names = "default";
pinctrl-0 = <&sdio0_bus4 &sdio0_cmd &sdio0_clk>;
post-power-on-delay-ms = <50>;
/delete-property/ rockchip,use-v2-tuning;
sd-uhs-sdr104;
status = "okay";
};
&sdmmc {
bus-width = <4>;
cap-mmc-highspeed;
cap-sd-highspeed;
disable-wp;
max-frequency = <150000000>;
pinctrl-names = "default";
pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_det &sdmmc_bus4>;
rockchip,default-sample-phase = <90>;
supports-sd;
sd-uhs-sdr12;
sd-uhs-sdr25;
sd-uhs-sdr50;
sd-uhs-sdr104;
vqmmc-supply = <&vccio_sd>;
vmmc-supply = <&vcc_sd>;
status = "okay";
};
&uart2 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&uart2m1_xfer &uart2m1_ctsn>;
};

6
arch/arm64/boot/dts/rockchip/rk3528-evb1-ddr4-v10-linux.dts
View File

@ -7,6 +7,12 @@
#include "rk3528-evb1-ddr4-v10.dtsi"
#include "rk3528-linux.dtsi"
/ {
chosen: chosen {
bootargs = "earlycon=uart8250,mmio32,0xff9f0000 console=ttyFIQ0 root=PARTUUID=614e0000-0000 rw rootwait";
};
};
&sdmmc {
status = "okay";
};

29
arch/arm64/boot/dts/rockchip/rk3528-evb1-ddr4-v10-spi-nand-linux.dts Normal file
View File

@ -0,0 +1,29 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (c) 2022 Rockchip Electronics Co., Ltd.
*
*/
#include "rk3528-evb1-ddr4-v10.dtsi"
#include "rk3528-linux.dtsi"
/ {
chosen: chosen {
bootargs = "earlycon=uart8250,mmio32,0xff9f0000 console=ttyFIQ0 ubi.mtd=3 root=ubi0:rootfs rootfstype=ubifs rw rootwait";
};
};
&sdmmc {
status = "disabled";
};
&sfc {
status = "okay";
flash@0 {
compatible = "spi-nand";
reg = <0>;
spi-max-frequency = <75000000>;
spi-rx-bus-width = <4>;
spi-tx-bus-width = <1>;
};
};

38
arch/arm64/boot/dts/rockchip/rk3528-pinctrl.dtsi
View File

@ -366,21 +366,21 @@
i2s0m0_lrck: i2s0m0-lrck {
rockchip,pins =
/* i2s0_lrck_m0 */
<3 RK_PB6 1 &pcfg_pull_none>;
<3 RK_PB6 1 &pcfg_pull_none_smt>;
};
/omit-if-no-ref/
i2s0m0_mclk: i2s0m0-mclk {
rockchip,pins =
/* i2s0_mclk_m0 */
<3 RK_PB4 1 &pcfg_pull_none>;
<3 RK_PB4 1 &pcfg_pull_none_smt>;
};
/omit-if-no-ref/
i2s0m0_sclk: i2s0m0-sclk {
rockchip,pins =
/* i2s0_sclk_m0 */
<3 RK_PB5 1 &pcfg_pull_none>;
<3 RK_PB5 1 &pcfg_pull_none_smt>;
};
/omit-if-no-ref/
@ -400,21 +400,21 @@
i2s0m1_lrck: i2s0m1-lrck {
rockchip,pins =
/* i2s0_lrck_m1 */
<1 RK_PB6 1 &pcfg_pull_none>;
<1 RK_PB6 1 &pcfg_pull_none_smt>;
};
/omit-if-no-ref/
i2s0m1_mclk: i2s0m1-mclk {
rockchip,pins =
/* i2s0_mclk_m1 */
<1 RK_PB4 1 &pcfg_pull_none>;
<1 RK_PB4 1 &pcfg_pull_none_smt>;
};
/omit-if-no-ref/
i2s0m1_sclk: i2s0m1-sclk {
rockchip,pins =
/* i2s0_sclk_m1 */
<1 RK_PB5 1 &pcfg_pull_none>;
<1 RK_PB5 1 &pcfg_pull_none_smt>;
};
/omit-if-no-ref/
@ -436,21 +436,21 @@
i2s1_lrck: i2s1-lrck {
rockchip,pins =
/* i2s1_lrck */
<4 RK_PA6 1 &pcfg_pull_none>;
<4 RK_PA6 1 &pcfg_pull_none_smt>;
};
/omit-if-no-ref/
i2s1_mclk: i2s1-mclk {
rockchip,pins =
/* i2s1_mclk */
<4 RK_PA4 1 &pcfg_pull_none>;
<4 RK_PA4 1 &pcfg_pull_none_smt>;
};
/omit-if-no-ref/
i2s1_sclk: i2s1-sclk {
rockchip,pins =
/* i2s1_sclk */
<4 RK_PA5 1 &pcfg_pull_none>;
<4 RK_PA5 1 &pcfg_pull_none_smt>;
};
/omit-if-no-ref/
@ -1030,24 +1030,24 @@
spi0_pins: spi0-pins {
rockchip,pins =
/* spi0_clk */
<4 RK_PB4 2 &pcfg_pull_none>,
<4 RK_PB4 2 &pcfg_pull_none_drv_level_2>,
/* spi0_miso */
<4 RK_PB3 2 &pcfg_pull_none>,
<4 RK_PB3 2 &pcfg_pull_none_drv_level_2>,
/* spi0_mosi */
<4 RK_PB2 2 &pcfg_pull_none>;
<4 RK_PB2 2 &pcfg_pull_none_drv_level_2>;
};
/omit-if-no-ref/
spi0_csn0: spi0-csn0 {
rockchip,pins =
/* spi0_csn0 */
<4 RK_PB6 2 &pcfg_pull_none>;
<4 RK_PB6 2 &pcfg_pull_none_drv_level_2>;
};
/omit-if-no-ref/
spi0_csn1: spi0-csn1 {
rockchip,pins =
/* spi0_csn1 */
<4 RK_PC1 2 &pcfg_pull_none>;
<4 RK_PC1 2 &pcfg_pull_none_drv_level_2>;
};
};
@ -1056,24 +1056,24 @@
spi1_pins: spi1-pins {
rockchip,pins =
/* spi1_clk */
<1 RK_PB6 2 &pcfg_pull_none>,
<1 RK_PB6 2 &pcfg_pull_none_drv_level_2>,
/* spi1_miso */
<1 RK_PC0 2 &pcfg_pull_none>,
<1 RK_PC0 2 &pcfg_pull_none_drv_level_2>,
/* spi1_mosi */
<1 RK_PB7 2 &pcfg_pull_none>;
<1 RK_PB7 2 &pcfg_pull_none_drv_level_2>;
};
/omit-if-no-ref/
spi1_csn0: spi1-csn0 {
rockchip,pins =
/* spi1_csn0 */
<1 RK_PC1 1 &pcfg_pull_none>;
<1 RK_PC1 1 &pcfg_pull_none_drv_level_2>;
};
/omit-if-no-ref/
spi1_csn1: spi1-csn1 {
rockchip,pins =
/* spi1_csn1 */
<1 RK_PC2 1 &pcfg_pull_none>;
<1 RK_PC2 1 &pcfg_pull_none_drv_level_2>;
};
};

16
arch/arm64/boot/dts/rockchip/rk3528.dtsi
View File

@ -644,12 +644,15 @@
resets = <&cru SRST_ARESETN_USB3OTG>;
reset-names = "usb3-otg";
snps,dis_enblslpm_quirk;
snps,dis-u1u2-quirk;
snps,dis-u1-entry-quirk;
snps,dis-u2-entry-quirk;
snps,dis-u2-freeclk-exists-quirk;
snps,dis-del-phy-power-chg-quirk;
snps,dis-tx-ipgap-linecheck-quirk;
snps,xhci-trb-ent-quirk;
snps,dis_rxdet_inp3_quirk;
snps,parkmode-disable-hs-quirk;
snps,parkmode-disable-ss-quirk;
quirk-skip-phy-init;
status = "disabled";
};
@ -1528,9 +1531,8 @@
ddc-i2c-scl-low-time-ns = <10000>;
reg-io-width = <4>;
rockchip,grf = <&grf>;
pinctrl-names = "default", "idle";
pinctrl-names = "default";
pinctrl-0 = <&hdmi_pins>;
pinctrl-1 = <&hdmi_pins_idle>;
phys = <&hdmiphy>;
phy-names = "hdmi";
#sound-dai-cells = <0>;
@ -1916,6 +1918,8 @@
rockchip,hw-tshut-temp = <120000>;
rockchip,hw-tshut-mode = <0>; /* tshut mode 0:CRU 1:GPIO */
rockchip,hw-tshut-polarity = <0>; /* tshut polarity 0:LOW 1:HIGH */
nvmem-cells = <&cpu_tsadc_trim_l>, <&cpu_tsadc_trim_h>;
nvmem-cell-names = "trim_l", "trim_h";
status = "disabled";
};
@ -2316,6 +2320,12 @@
dmc_opp_info: dmc-opp-info@3e {
reg = <0x3e 0x6>;
};
cpu_tsadc_trim_l: cpu-tsadc-trim-l@44 {
reg = <0x44 0x1>;
};
cpu_tsadc_trim_h: cpu-tsadc-trim-h@45 {
reg = <0x45 0x1>;
};
};
dmac: dma-controller@ffd60000 {

57
arch/arm64/boot/dts/rockchip/rk3562-amp.dtsi
View File

@ -1,11 +1,13 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (c) 2022 Rockchip Electronics Co., Ltd.
* Copyright (c) 2023 Rockchip Electronics Co., Ltd.
*/
#include <dt-bindings/soc/rockchip-amp.h>
/ {
rockchip_amp: rockchip-amp {
compatible = "rockchip,mcu-amp";
compatible = "rockchip,amp";
clocks = <&cru FCLK_BUS_CM0_CORE>, <&cru CLK_BUS_CM0_RTC>,
<&cru PCLK_MAILBOX>, <&cru PCLK_INTC>,
<&cru SCLK_UART7>, <&cru PCLK_UART7>,
@ -14,17 +16,8 @@
pinctrl-names = "default";
pinctrl-0 = <&uart7m1_xfer>;
status = "okay";
};
rpmsg: rpmsg@a0000000 {
compatible = "rockchip,rk3562-rpmsg";
mbox-names = "rpmsg-rx", "rpmsg-tx";
mboxes = <&mailbox 0 &mailbox 3>;
rockchip,vdev-nums = <1>;
rockchip,link-id = <0x04>;
reg = <0x0 0xa0000000 0x0 0x20000>;
memory-region = <&rpmsg_dma_reserved>;
amp-cpu-aff-maskbits = <0x0 0x1 0x1 0x2 0x2 0x4 0x3 0x8>;
amp-irqs = <GIC_AMP_IRQ_CFG_ROUTE(81, 0xd0, CPU_GET_AFFINITY(3, 0))>;
status = "okay";
};
@ -34,25 +27,45 @@
#size-cells = <2>;
ranges;
/* remote amp core address */
amp_shmem_reserved: amp-shmem@7800000 {
reg = <0x0 0x7800000 0x0 0x400000>;
no-map;
};
rpmsg_reserved: rpmsg@7c00000 {
reg = <0x0 0x07c00000 0x0 0x400000>;
no-map;
};
rpmsg_dma_reserved: rpmsg-dma@8000000 {
compatible = "shared-dma-pool";
reg = <0x0 0x08000000 0x0 0x100000>;
no-map;
};
/* mcu address */
mcu_reserved: mcu@8200000 {
reg = <0x0 0x8200000 0x0 0x100000>;
no-map;
};
rpmsg_reserved: rpmsg@a0000000 {
reg = <0x0 0xa0000000 0x0 0x400000>;
no-map;
};
};
rpmsg_dma_reserved: rpmsg-dma@a0400000 {
compatible = "shared-dma-pool";
reg = <0x0 0xa0400000 0x0 0x100000>;
no-map;
};
rpmsg: rpmsg@7c00000 {
compatible = "rockchip,rpmsg";
mbox-names = "rpmsg-rx", "rpmsg-tx";
mboxes = <&mailbox 0 &mailbox 3>;
rockchip,vdev-nums = <1>;
rockchip,link-id = <0x04>;
reg = <0x0 0x7c00000 0x0 0x20000>;
memory-region = <&rpmsg_dma_reserved>;
status = "okay";
};
};
&mailbox {
rockchip,txpoll-period-ms = <1>;
status = "okay";
};

6
arch/arm64/boot/dts/rockchip/rk3562-android.dtsi
View File

@ -5,6 +5,12 @@
*/
/ {
aliases {
mmc0 = &sdmmc0;
mmc1 = &sdmmc1;
mmc2 = &sdhci;
};
chosen: chosen {
bootargs = "earlycon=uart8250,mmio32,0xff210000 console=ttyFIQ0";
};

18
arch/arm64/boot/dts/rockchip/rk3562-evb1-lp4x-v10-linux-amp.dts
View File

@ -8,3 +8,21 @@
#include "rk3562-linux.dtsi"
#include "rk3562-rk817.dtsi"
#include "rk3562-amp.dtsi"
/ {
memory {
device_type = "memory";
reg = <0x0 0x02000000 0x0 0x06400000>,
<0x0 0x0a200000 0x0 0xf1e00000>;
};
};
&arm_pmu {
interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>;
};
/delete-node/ &cpu3;
&sdmmc0 {
status = "disabled";
};

64
arch/arm64/boot/dts/rockchip/rk3562-evb1-lp4x-v10-mcu-k350c4516t.dts
View File

@ -47,8 +47,8 @@
rockchip,data-sync-bypass;
pinctrl-names = "default";
/*
* rgb3x8_pins_m0/rgb3x8_pins_m1 for serial mcu
* rgb565_pins for parallel mcu
* rgb3x8_pins_m0/rgb3x8_pins_m1 for RGB3x8(8bit)
* rgb565_pins for RGB565(16bit)
*/
pinctrl-0 = <&rgb565_pins>;
@ -57,19 +57,19 @@
*/
mcu_panel: mcu-panel {
/*
* MEDIA_BUS_FMT_RGB888_3X8 for serial mcu
* MEDIA_BUS_FMT_RGB565_1X16 for parallel mcu
* MEDIA_BUS_FMT_RGB888_3X8 for RGB3x8(8bit)
* MEDIA_BUS_FMT_RGB565_1X16 for RGB565(16bit)
*/
bus-format = <MEDIA_BUS_FMT_RGB565_1X16>;
backlight = <&backlight>;
enable-gpios = <&gpio3 RK_PA6 GPIO_ACTIVE_LOW>;
enable-delay-ms = <20>;
reset-gpios = <&gpio3 RK_PB0 GPIO_ACTIVE_LOW>;
reset-value = <0>;
reset-delay-ms = <10>;
prepare-delay-ms = <20>;
unprepare-delay-ms = <20>;
disable-delay-ms = <20>;
init-delay-ms = <10>;
width-mm = <217>;
height-mm = <136>;
@ -124,20 +124,31 @@
00 00 01 36
01 00 01 48
00 00 01 3a //interface mode control
01 00 01 55 //spi rgb:66(r1 r4 r5) mcu parallel: 55(r2 r3 r6)
// mcu serial: 77(r1 r3 r6)
00 00 01 3a
01 00 01 55 /*
* interface pixel format:
* 66 for RGB3x8(8bit)
* 55 for RGB565(16bit)
*/
00 00 01 b0 //interface mode control
00 00 01 b0
01 00 01 00
00 00 01 b1 //frame rate 70hz
01 00 01 b0
00 00 01 b1
01 00 01 a0 /*
* frame rate control:
* 70 (45hz) for RGB3x8(8bit)
* a0 (60hz) for RGB565(16bit)
*/
01 00 01 11
00 00 01 b4
01 00 01 02
00 00 01 B6 //RGB/MCU Interface Control
01 00 01 02 //02 mcu, 32 rgb
00 00 01 B6
01 00 01 02 /*
* display function control:
* 32 for RGB
* 02 for MCU
*/
01 00 01 02
00 00 01 b7
@ -171,7 +182,11 @@
native-mode = <&kd050fwfba002_timing>;
kd050fwfba002_timing: timing0 {
clock-frequency = <80000000>;
/*
* 7840125 for frame rate 45Hz
* 10453500 for frame rate 60Hz
*/
clock-frequency = <10453500>;
hactive = <320>;
vactive = <480>;
hback-porch = <10>;
@ -237,12 +252,27 @@
};
&vp0 {
status = "okay";
/*
* Default config is as follows:
*
* mcu-pix-total = <9>;
* mcu-cs-pst = <1>;
* mcu-cs-pend = <8>;
* mcu-rw-pst = <2>;
* mcu-rw-pend = <5>;
* mcu-hold-mode = <0>; // default set to 0
*
* To increase the frame rate, reduce all parameters because
* the max dclk rate of mcu is 150M in rk3562.
*/
mcu-timing {
mcu-pix-total = <9>;
mcu-pix-total = <5>;
mcu-cs-pst = <1>;
mcu-cs-pend = <8>;
mcu-cs-pend = <4>;
mcu-rw-pst = <2>;
mcu-rw-pend = <5>;
mcu-rw-pend = <3>;
mcu-hold-mode = <0>; // default set to 0
};

30
arch/arm64/boot/dts/rockchip/rk3562-evb1-lp4x-v10-rgb-k350c4516t.dts
View File

@ -43,6 +43,7 @@
prepare-delay-ms = <20>;
unprepare-delay-ms = <20>;
disable-delay-ms = <20>;
init-delay-ms = <10>;
width-mm = <217>;
height-mm = <136>;
rockchip,cmd-type = "spi";
@ -99,19 +100,29 @@
00 00 01 36
01 00 01 48
00 00 01 3a /* interface mode control */
01 00 01 66
00 00 01 3a
01 00 01 66 /*
* interface pixel format:
* 66 for RGB666(18bit)
*/
00 00 01 b0 /* interface mode control */
00 00 01 b0
01 00 01 00
00 00 01 b1 /* frame rate 70hz */
01 00 01 b0
00 00 01 b1
01 00 01 a0 /*
* frame rate control:
* a0 (60hz) for RGB666(18bit)
*/
01 00 01 11
00 00 01 b4
01 00 01 02
00 00 01 B6 /* RGB/MCU Interface Control */
01 00 01 32 /* 02 mcu, 32 rgb */
00 00 01 B6
01 00 01 32 /*
* display function control:
* 32 for RGB
* 02 for MCU
*/
01 00 01 02
00 00 01 b7
@ -144,7 +155,10 @@
native-mode = <&kd050fwfba002_timing>;
kd050fwfba002_timing: timing0 {
clock-frequency = <12000000>;
/*
* 10453500 for RGB666(18bit)
*/
clock-frequency = <10453500>;
hactive = <320>;
vactive = <480>;
hback-porch = <10>;

132
arch/arm64/boot/dts/rockchip/rk3562-evb1-lp4x-v10-sii9022-rgb2hdmi.dts Normal file
View File

@ -0,0 +1,132 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (c) 2023 Rockchip Electronics Co., Ltd.
*
*/
#include <dt-bindings/display/media-bus-format.h>
#include "rk3562-evb1-lp4x-v10.dtsi"
#include "rk3562-android.dtsi"
#include "rk3562-rk817.dtsi"
/ {
model = "Rockchip RK3562 EVB1 LP4X V10 Board + RK EVB SII9022 RGB2HDMI DISPLAY Ext Board";
compatible = "rockchip,rk3562-evb1-lp4x-v10-sii9022-rgb2hdmi", "rockchip,rk3562";
};
&dsi {
status = "disabled";
};
&dsi_in_vp0 {
status = "disabled";
};
/*
* The pins of gmac0 and rgb are multiplexed
*/
&gmac0 {
status = "disabled";
};
&i2c3 {
clock-frequency = <400000>;
pinctrl-0 = <&i2c3m0_xfer>;
status = "okay";
sii9022: sii9022@39 {
compatible = "sil,sii9022";
reg = <0x39>;
pinctrl-names = "default";
pinctrl-0 = <&sii902x_hdmi>;
interrupt-parent = <&gpio3>;
interrupts = <RK_PA7 IRQ_TYPE_LEVEL_HIGH>;
reset-gpio = <&gpio3 RK_PB0 GPIO_ACTIVE_LOW>;
enable-gpio = <&gpio3 RK_PA6 GPIO_ACTIVE_HIGH>;
bus-format = <MEDIA_BUS_FMT_RGB888_1X24>;
status = "okay";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
sii9022_in_rgb: endpoint {
remote-endpoint = <&rgb_out_sii9022>;
};
};
};
};
};
/*
* The pins of pcie2x1/pdm_codec and rgb are multiplexed
*/
&pcie2x1 {
status = "disabled";
};
&pdm_codec {
status = "disabled";
};
&pinctrl {
sii902x {
sii902x_hdmi: sii902x-hdmi {
rockchip,pins = <3 RK_PA7 RK_FUNC_GPIO &pcfg_pull_up>;
};
};
};
&rgb {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&vo_pins>;
ports {
port@1 {
reg = <1>;
#address-cells = <1>;
#size-cells = <0>;
rgb_out_sii9022: endpoint@0 {
reg = <0>;
remote-endpoint = <&sii9022_in_rgb>;
};
};
};
};
&rgb_in_vp0 {
status = "okay";
};
&route_rgb {
status = "disabled";
connect = <&vp0_out_rgb>;
};
/*
* The pins of sai0/vcc_mipicsi0/u2phy_host and rgb are multiplexed
*/
&sai0 {
status = "disabled";
};
&u2phy_host {
status = "disabled";
};
&vcc5v0_usb_host {
status = "disabled";
};
&vcc_mipicsi0 {
status = "disabled";
};
&video_phy {
status = "disabled";
};

12
arch/arm64/boot/dts/rockchip/rk3562-evb1-lp4x-v10.dtsi
View File

@ -179,6 +179,18 @@
};
};
&bus_soc {
rockchip,soc-bus-table = <0 0x00a000a8 0x7001>,
<1 0x00a000a8 0x7c39>,
<2 0x00a000a8 0x7c39>,
<3 0x00a000a8 0x7c39>,
<4 0x00a000a5 0xb007>,
<5 0x00a000a8 0x7034>,
<6 0x00a000a8 0x7034>,
<7 0x00a000a8 0x7034>,
<8 0x00a000a8 0x7001>;
};
&gmac0 {
/* Use rgmii-rxid mode to disable rx delay inside Soc */
phy-mode = "rgmii-rxid";

6
arch/arm64/boot/dts/rockchip/rk3562-linux.dtsi
View File

@ -5,6 +5,12 @@
*/
/ {
aliases {
mmc0 = &sdhci;
mmc1 = &sdmmc0;
mmc2 = &sdmmc1;
};
chosen: chosen {
bootargs = "earlycon=uart8250,mmio32,0xff210000 console=ttyFIQ0 root=PARTUUID=614e0000-0000 rw rootwait";
};

242
arch/arm64/boot/dts/rockchip/rk3562-pinctrl.dtsi
View File

@ -370,21 +370,21 @@
i2s0m0_lrck: i2s0m0-lrck {
rockchip,pins =
/* i2s0_lrck_m0 */
<3 RK_PA4 1 &pcfg_pull_none>;
<3 RK_PA4 1 &pcfg_pull_none_smt>;
};
/omit-if-no-ref/
i2s0m0_mclk: i2s0m0-mclk {
rockchip,pins =
/* i2s0_mclk_m0 */
<3 RK_PA2 1 &pcfg_pull_none>;
<3 RK_PA2 1 &pcfg_pull_none_smt>;
};
/omit-if-no-ref/
i2s0m0_sclk: i2s0m0-sclk {
rockchip,pins =
/* i2s0_sclk_m0 */
<3 RK_PA3 1 &pcfg_pull_none>;
<3 RK_PA3 1 &pcfg_pull_none_smt>;
};
/omit-if-no-ref/
@ -447,21 +447,21 @@
i2s0m1_lrck: i2s0m1-lrck {
rockchip,pins =
/* i2s0_lrck_m1 */
<1 RK_PC4 3 &pcfg_pull_none>;
<1 RK_PC4 3 &pcfg_pull_none_smt>;
};
/omit-if-no-ref/
i2s0m1_mclk: i2s0m1-mclk {
rockchip,pins =
/* i2s0_mclk_m1 */
<1 RK_PC6 3 &pcfg_pull_none>;
<1 RK_PC6 3 &pcfg_pull_none_smt>;
};
/omit-if-no-ref/
i2s0m1_sclk: i2s0m1-sclk {
rockchip,pins =
/* i2s0_sclk_m1 */
<1 RK_PC5 3 &pcfg_pull_none>;
<1 RK_PC5 3 &pcfg_pull_none_smt>;
};
/omit-if-no-ref/
@ -526,21 +526,21 @@
i2s1m0_lrck: i2s1m0-lrck {
rockchip,pins =
/* i2s1_lrck_m0 */
<3 RK_PC6 2 &pcfg_pull_none>;
<3 RK_PC6 2 &pcfg_pull_none_smt>;
};
/omit-if-no-ref/
i2s1m0_mclk: i2s1m0-mclk {
rockchip,pins =
/* i2s1_mclk_m0 */
<3 RK_PC4 2 &pcfg_pull_none>;
<3 RK_PC4 2 &pcfg_pull_none_smt>;
};
/omit-if-no-ref/
i2s1m0_sclk: i2s1m0-sclk {
rockchip,pins =
/* i2s1_sclk_m0 */
<3 RK_PC5 2 &pcfg_pull_none>;
<3 RK_PC5 2 &pcfg_pull_none_smt>;
};
/omit-if-no-ref/
@ -603,21 +603,21 @@
i2s1m1_lrck: i2s1m1-lrck {
rockchip,pins =
/* i2s1_lrck_m1 */
<3 RK_PB4 1 &pcfg_pull_none>;
<3 RK_PB4 1 &pcfg_pull_none_smt>;
};
/omit-if-no-ref/
i2s1m1_mclk: i2s1m1-mclk {
rockchip,pins =
/* i2s1_mclk_m1 */
<3 RK_PB2 1 &pcfg_pull_none>;
<3 RK_PB2 1 &pcfg_pull_none_smt>;
};
/omit-if-no-ref/
i2s1m1_sclk: i2s1m1-sclk {
rockchip,pins =
/* i2s1_sclk_m1 */
<3 RK_PB3 1 &pcfg_pull_none>;
<3 RK_PB3 1 &pcfg_pull_none_smt>;
};
/omit-if-no-ref/
@ -682,21 +682,21 @@
i2s2m0_lrck: i2s2m0-lrck {
rockchip,pins =
/* i2s2_lrck_m0 */
<1 RK_PD6 1 &pcfg_pull_none>;
<1 RK_PD6 1 &pcfg_pull_none_smt>;
};
/omit-if-no-ref/
i2s2m0_mclk: i2s2m0-mclk {
rockchip,pins =
/* i2s2_mclk_m0 */
<2 RK_PA1 1 &pcfg_pull_none>;
<2 RK_PA1 1 &pcfg_pull_none_smt>;
};
/omit-if-no-ref/
i2s2m0_sclk: i2s2m0-sclk {
rockchip,pins =
/* i2s2_sclk_m0 */
<1 RK_PD5 1 &pcfg_pull_none>;
<1 RK_PD5 1 &pcfg_pull_none_smt>;
};
/omit-if-no-ref/
@ -717,21 +717,21 @@
i2s2m1_lrck: i2s2m1-lrck {
rockchip,pins =
/* i2s2_lrck_m1 */
<4 RK_PA1 3 &pcfg_pull_none>;
<4 RK_PA1 3 &pcfg_pull_none_smt>;
};
/omit-if-no-ref/
i2s2m1_mclk: i2s2m1-mclk {
rockchip,pins =
/* i2s2_mclk_m1 */
<3 RK_PD6 3 &pcfg_pull_none>;
<3 RK_PD6 3 &pcfg_pull_none_smt>;
};
/omit-if-no-ref/
i2s2m1_sclk: i2s2m1-sclk {
rockchip,pins =
/* i2s2_sclk_m1 */
<4 RK_PB1 4 &pcfg_pull_none>;
<4 RK_PB1 4 &pcfg_pull_none_smt>;
};
/omit-if-no-ref/
@ -2071,61 +2071,61 @@
vo_pins: vo-pins {
rockchip,pins =
/* vo_lcdc_clk */
<4 RK_PB7 1 &pcfg_pull_none>,
<4 RK_PB7 1 &pcfg_pull_none_drv_level_4>,
/* vo_lcdc_d0 */
<4 RK_PA4 1 &pcfg_pull_none>,
<4 RK_PA4 1 &pcfg_pull_none_drv_level_3>,
/* vo_lcdc_d1 */
<4 RK_PA5 1 &pcfg_pull_none>,
<4 RK_PA5 1 &pcfg_pull_none_drv_level_3>,
/* vo_lcdc_d2 */
<4 RK_PB2 1 &pcfg_pull_none>,
<4 RK_PB2 1 &pcfg_pull_none_drv_level_3>,
/* vo_lcdc_d3 */
<3 RK_PC4 1 &pcfg_pull_none>,
<3 RK_PC4 1 &pcfg_pull_none_drv_level_3>,
/* vo_lcdc_d4 */
<3 RK_PC5 1 &pcfg_pull_none>,
<3 RK_PC5 1 &pcfg_pull_none_drv_level_3>,
/* vo_lcdc_d5 */
<3 RK_PC6 1 &pcfg_pull_none>,
<3 RK_PC6 1 &pcfg_pull_none_drv_level_3>,
/* vo_lcdc_d6 */
<3 RK_PC7 1 &pcfg_pull_none>,
<3 RK_PC7 1 &pcfg_pull_none_drv_level_3>,
/* vo_lcdc_d7 */
<3 RK_PD0 1 &pcfg_pull_none>,
<3 RK_PD0 1 &pcfg_pull_none_drv_level_3>,
/* vo_lcdc_d8 */
<4 RK_PA6 1 &pcfg_pull_none>,
<4 RK_PA6 1 &pcfg_pull_none_drv_level_3>,
/* vo_lcdc_d9 */
<4 RK_PA7 1 &pcfg_pull_none>,
<4 RK_PA7 1 &pcfg_pull_none_drv_level_3>,
/* vo_lcdc_d10 */
<3 RK_PD1 1 &pcfg_pull_none>,
<3 RK_PD1 1 &pcfg_pull_none_drv_level_3>,
/* vo_lcdc_d11 */
<3 RK_PD2 1 &pcfg_pull_none>,
<3 RK_PD2 1 &pcfg_pull_none_drv_level_3>,
/* vo_lcdc_d12 */
<3 RK_PD3 1 &pcfg_pull_none>,
<3 RK_PD3 1 &pcfg_pull_none_drv_level_3>,
/* vo_lcdc_d13 */
<3 RK_PD4 1 &pcfg_pull_none>,
<3 RK_PD4 1 &pcfg_pull_none_drv_level_3>,
/* vo_lcdc_d14 */
<3 RK_PD5 1 &pcfg_pull_none>,
<3 RK_PD5 1 &pcfg_pull_none_drv_level_3>,
/* vo_lcdc_d15 */
<3 RK_PD6 1 &pcfg_pull_none>,
<3 RK_PD6 1 &pcfg_pull_none_drv_level_3>,
/* vo_lcdc_d16 */
<4 RK_PB0 1 &pcfg_pull_none>,
<4 RK_PB0 1 &pcfg_pull_none_drv_level_3>,
/* vo_lcdc_d17 */
<4 RK_PB1 1 &pcfg_pull_none>,
<4 RK_PB1 1 &pcfg_pull_none_drv_level_3>,
/* vo_lcdc_d18 */
<4 RK_PB3 1 &pcfg_pull_none>,
<4 RK_PB3 1 &pcfg_pull_none_drv_level_3>,
/* vo_lcdc_d19 */
<3 RK_PD7 1 &pcfg_pull_none>,
<3 RK_PD7 1 &pcfg_pull_none_drv_level_3>,
/* vo_lcdc_d20 */
<4 RK_PA0 1 &pcfg_pull_none>,
<4 RK_PA0 1 &pcfg_pull_none_drv_level_3>,
/* vo_lcdc_d21 */
<4 RK_PA1 1 &pcfg_pull_none>,
<4 RK_PA1 1 &pcfg_pull_none_drv_level_3>,
/* vo_lcdc_d22 */
<4 RK_PA2 1 &pcfg_pull_none>,
<4 RK_PA2 1 &pcfg_pull_none_drv_level_3>,
/* vo_lcdc_d23 */
<4 RK_PA3 1 &pcfg_pull_none>,
<4 RK_PA3 1 &pcfg_pull_none_drv_level_3>,
/* vo_lcdc_den */
<4 RK_PB6 1 &pcfg_pull_none>,
<4 RK_PB6 1 &pcfg_pull_none_drv_level_3>,
/* vo_lcdc_hsync */
<4 RK_PB4 1 &pcfg_pull_none>,
<4 RK_PB4 1 &pcfg_pull_none_drv_level_3>,
/* vo_lcdc_vsync */
<4 RK_PB5 1 &pcfg_pull_none>;
<4 RK_PB5 1 &pcfg_pull_none_drv_level_3>;
};
};
};
@ -2178,175 +2178,175 @@
bt656_pins: bt656-pins {
rockchip,pins =
/* vo_lcdc_clk */
<4 RK_PB7 1 &pcfg_pull_none_drv_level_2>,
<4 RK_PB7 1 &pcfg_pull_none_drv_level_4>,
/* vo_lcdc_d3 */
<3 RK_PC4 1 &pcfg_pull_none_drv_level_2>,
<3 RK_PC4 1 &pcfg_pull_none_drv_level_3>,
/* vo_lcdc_d4 */
<3 RK_PC5 1 &pcfg_pull_none_drv_level_2>,
<3 RK_PC5 1 &pcfg_pull_none_drv_level_3>,
/* vo_lcdc_d5 */
<3 RK_PC6 1 &pcfg_pull_none_drv_level_2>,
<3 RK_PC6 1 &pcfg_pull_none_drv_level_3>,
/* vo_lcdc_d6 */
<3 RK_PC7 1 &pcfg_pull_none_drv_level_2>,
<3 RK_PC7 1 &pcfg_pull_none_drv_level_3>,
/* vo_lcdc_d7 */
<3 RK_PD0 1 &pcfg_pull_none_drv_level_2>,
<3 RK_PD0 1 &pcfg_pull_none_drv_level_3>,
/* vo_lcdc_d10 */
<3 RK_PD1 1 &pcfg_pull_none_drv_level_2>,
<3 RK_PD1 1 &pcfg_pull_none_drv_level_3>,
/* vo_lcdc_d11 */
<3 RK_PD2 1 &pcfg_pull_none_drv_level_2>,
<3 RK_PD2 1 &pcfg_pull_none_drv_level_3>,
/* vo_lcdc_d12 */
<3 RK_PD3 1 &pcfg_pull_none_drv_level_2>;
<3 RK_PD3 1 &pcfg_pull_none_drv_level_3>;
};
/omit-if-no-ref/
rgb3x8_pins_m0: rgb3x8-pins-m0 {
rockchip,pins =
/* vo_lcdc_clk */
<4 RK_PB7 1 &pcfg_pull_none_drv_level_2>,
<4 RK_PB7 1 &pcfg_pull_none_drv_level_4>,
/* vo_lcdc_d3 */
<3 RK_PC4 1 &pcfg_pull_none_drv_level_2>,
<3 RK_PC4 1 &pcfg_pull_none_drv_level_3>,
/* vo_lcdc_d4 */
<3 RK_PC5 1 &pcfg_pull_none_drv_level_2>,
<3 RK_PC5 1 &pcfg_pull_none_drv_level_3>,
/* vo_lcdc_d5 */
<3 RK_PC6 1 &pcfg_pull_none_drv_level_2>,
<3 RK_PC6 1 &pcfg_pull_none_drv_level_3>,
/* vo_lcdc_d6 */
<3 RK_PC7 1 &pcfg_pull_none_drv_level_2>,
<3 RK_PC7 1 &pcfg_pull_none_drv_level_3>,
/* vo_lcdc_d7 */
<3 RK_PD0 1 &pcfg_pull_none_drv_level_2>,
<3 RK_PD0 1 &pcfg_pull_none_drv_level_3>,
/* vo_lcdc_d10 */
<3 RK_PD1 1 &pcfg_pull_none_drv_level_2>,
<3 RK_PD1 1 &pcfg_pull_none_drv_level_3>,
/* vo_lcdc_d11 */
<3 RK_PD2 1 &pcfg_pull_none_drv_level_2>,
<3 RK_PD2 1 &pcfg_pull_none_drv_level_3>,
/* vo_lcdc_d12 */
<3 RK_PD3 1 &pcfg_pull_none_drv_level_2>,
<3 RK_PD3 1 &pcfg_pull_none_drv_level_3>,
/* vo_lcdc_den */
<4 RK_PB6 1 &pcfg_pull_none_drv_level_2>,
<4 RK_PB6 1 &pcfg_pull_none_drv_level_3>,
/* vo_lcdc_hsync */
<4 RK_PB4 1 &pcfg_pull_none_drv_level_2>,
<4 RK_PB4 1 &pcfg_pull_none_drv_level_3>,
/* vo_lcdc_vsync */
<4 RK_PB5 1 &pcfg_pull_none_drv_level_2>;
<4 RK_PB5 1 &pcfg_pull_none_drv_level_3>;
};
/omit-if-no-ref/
rgb3x8_pins_m1: rgb3x8-pins-m1 {
rockchip,pins =
/* vo_lcdc_clk */
<4 RK_PB7 1 &pcfg_pull_none_drv_level_2>,
<4 RK_PB7 1 &pcfg_pull_none_drv_level_4>,
/* vo_lcdc_d13 */
<3 RK_PD4 1 &pcfg_pull_none_drv_level_2>,
<3 RK_PD4 1 &pcfg_pull_none_drv_level_3>,
/* vo_lcdc_d14 */
<3 RK_PD5 1 &pcfg_pull_none_drv_level_2>,
<3 RK_PD5 1 &pcfg_pull_none_drv_level_3>,
/* vo_lcdc_d15 */
<3 RK_PD6 1 &pcfg_pull_none_drv_level_2>,
<3 RK_PD6 1 &pcfg_pull_none_drv_level_3>,
/* vo_lcdc_d19 */
<3 RK_PD7 1 &pcfg_pull_none_drv_level_2>,
<3 RK_PD7 1 &pcfg_pull_none_drv_level_3>,
/* vo_lcdc_d20 */
<4 RK_PA0 1 &pcfg_pull_none_drv_level_2>,
<4 RK_PA0 1 &pcfg_pull_none_drv_level_3>,
/* vo_lcdc_d21 */
<4 RK_PA1 1 &pcfg_pull_none_drv_level_2>,
<4 RK_PA1 1 &pcfg_pull_none_drv_level_3>,
/* vo_lcdc_d22 */
<4 RK_PA2 1 &pcfg_pull_none_drv_level_2>,
<4 RK_PA2 1 &pcfg_pull_none_drv_level_3>,
/* vo_lcdc_d23 */
<4 RK_PA3 1 &pcfg_pull_none_drv_level_2>,
<4 RK_PA3 1 &pcfg_pull_none_drv_level_3>,
/* vo_lcdc_den */
<4 RK_PB6 1 &pcfg_pull_none_drv_level_2>,
<4 RK_PB6 1 &pcfg_pull_none_drv_level_3>,
/* vo_lcdc_hsync */
<4 RK_PB4 1 &pcfg_pull_none_drv_level_2>,
<4 RK_PB4 1 &pcfg_pull_none_drv_level_3>,
/* vo_lcdc_vsync */
<4 RK_PB5 1 &pcfg_pull_none_drv_level_2>;
<4 RK_PB5 1 &pcfg_pull_none_drv_level_3>;
};
/omit-if-no-ref/
rgb565_pins: rgb565-pins {
rockchip,pins =
/* vo_lcdc_clk */
<4 RK_PB7 1 &pcfg_pull_none_drv_level_2>,
<4 RK_PB7 1 &pcfg_pull_none_drv_level_4>,
/* vo_lcdc_d3 */
<3 RK_PC4 1 &pcfg_pull_none_drv_level_2>,
<3 RK_PC4 1 &pcfg_pull_none_drv_level_3>,
/* vo_lcdc_d4 */
<3 RK_PC5 1 &pcfg_pull_none_drv_level_2>,
<3 RK_PC5 1 &pcfg_pull_none_drv_level_3>,
/* vo_lcdc_d5 */
<3 RK_PC6 1 &pcfg_pull_none_drv_level_2>,
<3 RK_PC6 1 &pcfg_pull_none_drv_level_3>,
/* vo_lcdc_d6 */
<3 RK_PC7 1 &pcfg_pull_none_drv_level_2>,
<3 RK_PC7 1 &pcfg_pull_none_drv_level_3>,
/* vo_lcdc_d7 */
<3 RK_PD0 1 &pcfg_pull_none_drv_level_2>,
<3 RK_PD0 1 &pcfg_pull_none_drv_level_3>,
/* vo_lcdc_d10 */
<3 RK_PD1 1 &pcfg_pull_none_drv_level_2>,
<3 RK_PD1 1 &pcfg_pull_none_drv_level_3>,
/* vo_lcdc_d11 */
<3 RK_PD2 1 &pcfg_pull_none_drv_level_2>,
<3 RK_PD2 1 &pcfg_pull_none_drv_level_3>,
/* vo_lcdc_d12 */
<3 RK_PD3 1 &pcfg_pull_none_drv_level_2>,
<3 RK_PD3 1 &pcfg_pull_none_drv_level_3>,
/* vo_lcdc_d13 */
<3 RK_PD4 1 &pcfg_pull_none_drv_level_2>,
<3 RK_PD4 1 &pcfg_pull_none_drv_level_3>,
/* vo_lcdc_d14 */
<3 RK_PD5 1 &pcfg_pull_none_drv_level_2>,
<3 RK_PD5 1 &pcfg_pull_none_drv_level_3>,
/* vo_lcdc_d15 */
<3 RK_PD6 1 &pcfg_pull_none_drv_level_2>,
<3 RK_PD6 1 &pcfg_pull_none_drv_level_3>,
/* vo_lcdc_d19 */
<3 RK_PD7 1 &pcfg_pull_none_drv_level_2>,
<3 RK_PD7 1 &pcfg_pull_none_drv_level_3>,
/* vo_lcdc_d20 */
<4 RK_PA0 1 &pcfg_pull_none_drv_level_2>,
<4 RK_PA0 1 &pcfg_pull_none_drv_level_3>,
/* vo_lcdc_d21 */
<4 RK_PA1 1 &pcfg_pull_none_drv_level_2>,
<4 RK_PA1 1 &pcfg_pull_none_drv_level_3>,
/* vo_lcdc_d22 */
<4 RK_PA2 1 &pcfg_pull_none_drv_level_2>,
<4 RK_PA2 1 &pcfg_pull_none_drv_level_3>,
/* vo_lcdc_d23 */
<4 RK_PA3 1 &pcfg_pull_none_drv_level_2>,
<4 RK_PA3 1 &pcfg_pull_none_drv_level_3>,
/* vo_lcdc_den */
<4 RK_PB6 1 &pcfg_pull_none_drv_level_2>,
<4 RK_PB6 1 &pcfg_pull_none_drv_level_3>,
/* vo_lcdc_hsync */
<4 RK_PB4 1 &pcfg_pull_none_drv_level_2>,
<4 RK_PB4 1 &pcfg_pull_none_drv_level_3>,
/* vo_lcdc_vsync */
<4 RK_PB5 1 &pcfg_pull_none_drv_level_2>;
<4 RK_PB5 1 &pcfg_pull_none_drv_level_3>;
};
/omit-if-no-ref/
rgb666_pins: rgb666-pins {
rockchip,pins =
/* vo_lcdc_clk */
<4 RK_PB7 1 &pcfg_pull_none_drv_level_2>,
<4 RK_PB7 1 &pcfg_pull_none_drv_level_4>,
/* vo_lcdc_d2 */
<4 RK_PB2 1 &pcfg_pull_none_drv_level_2>,
<4 RK_PB2 1 &pcfg_pull_none_drv_level_3>,
/* vo_lcdc_d3 */
<3 RK_PC4 1 &pcfg_pull_none_drv_level_2>,
<3 RK_PC4 1 &pcfg_pull_none_drv_level_3>,
/* vo_lcdc_d4 */
<3 RK_PC5 1 &pcfg_pull_none_drv_level_2>,
<3 RK_PC5 1 &pcfg_pull_none_drv_level_3>,
/* vo_lcdc_d5 */
<3 RK_PC6 1 &pcfg_pull_none_drv_level_2>,
<3 RK_PC6 1 &pcfg_pull_none_drv_level_3>,
/* vo_lcdc_d6 */
<3 RK_PC7 1 &pcfg_pull_none_drv_level_2>,
<3 RK_PC7 1 &pcfg_pull_none_drv_level_3>,
/* vo_lcdc_d7 */
<3 RK_PD0 1 &pcfg_pull_none_drv_level_2>,
<3 RK_PD0 1 &pcfg_pull_none_drv_level_3>,
/* vo_lcdc_d10 */
<3 RK_PD1 1 &pcfg_pull_none_drv_level_2>,
<3 RK_PD1 1 &pcfg_pull_none_drv_level_3>,
/* vo_lcdc_d11 */
<3 RK_PD2 1 &pcfg_pull_none_drv_level_2>,
<3 RK_PD2 1 &pcfg_pull_none_drv_level_3>,
/* vo_lcdc_d12 */
<3 RK_PD3 1 &pcfg_pull_none_drv_level_2>,
<3 RK_PD3 1 &pcfg_pull_none_drv_level_3>,
/* vo_lcdc_d13 */
<3 RK_PD4 1 &pcfg_pull_none_drv_level_2>,
<3 RK_PD4 1 &pcfg_pull_none_drv_level_3>,
/* vo_lcdc_d14 */
<3 RK_PD5 1 &pcfg_pull_none_drv_level_2>,
<3 RK_PD5 1 &pcfg_pull_none_drv_level_3>,
/* vo_lcdc_d15 */
<3 RK_PD6 1 &pcfg_pull_none_drv_level_2>,
<3 RK_PD6 1 &pcfg_pull_none_drv_level_3>,
/* vo_lcdc_d18 */
<4 RK_PB3 1 &pcfg_pull_none_drv_level_2>,
<4 RK_PB3 1 &pcfg_pull_none_drv_level_3>,
/* vo_lcdc_d19 */
<3 RK_PD7 1 &pcfg_pull_none_drv_level_2>,
<3 RK_PD7 1 &pcfg_pull_none_drv_level_3>,
/* vo_lcdc_d20 */
<4 RK_PA0 1 &pcfg_pull_none_drv_level_2>,
<4 RK_PA0 1 &pcfg_pull_none_drv_level_3>,
/* vo_lcdc_d21 */
<4 RK_PA1 1 &pcfg_pull_none_drv_level_2>,
<4 RK_PA1 1 &pcfg_pull_none_drv_level_3>,
/* vo_lcdc_d22 */
<4 RK_PA2 1 &pcfg_pull_none_drv_level_2>,
<4 RK_PA2 1 &pcfg_pull_none_drv_level_3>,
/* vo_lcdc_d23 */
<4 RK_PA3 1 &pcfg_pull_none_drv_level_2>,
<4 RK_PA3 1 &pcfg_pull_none_drv_level_3>,
/* vo_lcdc_den */
<4 RK_PB6 1 &pcfg_pull_none_drv_level_2>,
<4 RK_PB6 1 &pcfg_pull_none_drv_level_3>,
/* vo_lcdc_hsync */
<4 RK_PB4 1 &pcfg_pull_none_drv_level_2>,
<4 RK_PB4 1 &pcfg_pull_none_drv_level_3>,
/* vo_lcdc_vsync */
<4 RK_PB5 1 &pcfg_pull_none_drv_level_2>;
<4 RK_PB5 1 &pcfg_pull_none_drv_level_3>;
};
};
};

7
arch/arm64/boot/dts/rockchip/rk3562-rk817-tablet-camera.dtsi
View File

@ -89,10 +89,11 @@
compatible = "dongwoon,dw9763";
status = "okay";
reg = <0x0c>;
avdd-supply = <&vcc2v8_dvp>;
rockchip,vcm-max-current = <120>;
rockchip,vcm-start-current = <20>;
rockchip,vcm-rated-current = <90>;
rockchip,vcm-step-mode = <3>;
rockchip,vcm-start-current = <25>;
rockchip,vcm-rated-current = <100>;
rockchip,vcm-step-mode = <4>;
rockchip,vcm-t-src = <0x20>;
rockchip,vcm-t-div = <1>;
rockchip,camera-module-index = <0>;

12
arch/arm64/boot/dts/rockchip/rk3562-rk817-tablet-v10.dts
View File

@ -209,6 +209,18 @@
cpu-supply = <&vdd_cpu>;
};
&bus_soc {
rockchip,soc-bus-table = <0 0x00a000a8 0x7001>,
<1 0x00a000a8 0x7c39>,
<2 0x00a000a8 0x7c39>,
<3 0x00a000a8 0x7c39>,
<4 0x00a000a5 0xb007>,
<5 0x00a000a8 0x7034>,
<6 0x00a000a8 0x7034>,
<7 0x00a000a8 0x7034>,
<8 0x00a000a8 0x7001>;
};
&dfi {
status = "okay";
};

3
arch/arm64/boot/dts/rockchip/rk3562-rk817.dtsi
View File

@ -114,7 +114,8 @@
regulator-initial-mode = <0x2>;
regulator-name = "vcc_3v3";
regulator-state-mem {
regulator-off-in-suspend;
regulator-on-in-suspend;
regulator-suspend-microvolt = <3300000>;
};
};

91
arch/arm64/boot/dts/rockchip/rk3562.dtsi
View File

@ -352,7 +352,7 @@
};
};
arm-pmu {
arm_pmu: arm-pmu {
compatible = "arm,cortex-a53-pmu";
interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>,
@ -368,7 +368,7 @@
<1 0x00a000a8 0x7c39>,
<2 0x00a000a8 0x7c39>,
<3 0x00a000a8 0x7c39>,
<4 0x00a000a5 0xb007>,
<4 0x00a000a4 0xb007>,
<5 0x00a000a8 0x7034>,
<6 0x00a000a8 0x7034>,
<7 0x00a000a8 0x7034>,
@ -384,42 +384,42 @@
/* dphy0 full mode */
csi2_dphy0: csi2-dphy0 {
compatible = "rockchip,rk3562-csi2-dphy";
rockchip,hw = <&csi2_dphy0_hw>;
rockchip,hw = <&csi2_dphy0_hw>, <&csi2_dphy1_hw>;
status = "disabled";
};
/* dphy0 split mode 01 */
csi2_dphy1: csi2-dphy1 {
compatible = "rockchip,rk3562-csi2-dphy";
rockchip,hw = <&csi2_dphy0_hw>;
rockchip,hw = <&csi2_dphy0_hw>, <&csi2_dphy1_hw>;
status = "disabled";
};
/* dphy0 split mode 23 */
csi2_dphy2: csi2-dphy2 {
compatible = "rockchip,rk3562-csi2-dphy";
rockchip,hw = <&csi2_dphy0_hw>;
rockchip,hw = <&csi2_dphy0_hw>, <&csi2_dphy1_hw>;
status = "disabled";
};
/* dphy1 full mode */
csi2_dphy3: csi2-dphy3 {
compatible = "rockchip,rk3562-csi2-dphy";
rockchip,hw = <&csi2_dphy1_hw>;
rockchip,hw = <&csi2_dphy0_hw>, <&csi2_dphy1_hw>;
status = "disabled";
};
/* dphy1 split mode 01 */
csi2_dphy4: csi2-dphy4 {
compatible = "rockchip,rk3562-csi2-dphy";
rockchip,hw = <&csi2_dphy1_hw>;
rockchip,hw = <&csi2_dphy0_hw>, <&csi2_dphy1_hw>;
status = "disabled";
};
/* dphy1 split mode 23 */
csi2_dphy5: csi2-dphy5 {
compatible = "rockchip,rk3562-csi2-dphy";
rockchip,hw = <&csi2_dphy1_hw>;
rockchip,hw = <&csi2_dphy0_hw>, <&csi2_dphy1_hw>;
status = "disabled";
};
@ -536,6 +536,34 @@
status = "disabled";
};
mipi0_csi2: mipi0-csi2 {
compatible = "rockchip,rk3562-mipi-csi2";
rockchip,hw = <&mipi0_csi2_hw>, <&mipi1_csi2_hw>,
<&mipi2_csi2_hw>, <&mipi3_csi2_hw>;
status = "disabled";
};
mipi1_csi2: mipi1-csi2 {
compatible = "rockchip,rk3562-mipi-csi2";
rockchip,hw = <&mipi0_csi2_hw>, <&mipi1_csi2_hw>,
<&mipi2_csi2_hw>, <&mipi3_csi2_hw>;
status = "disabled";
};
mipi2_csi2: mipi2-csi2 {
compatible = "rockchip,rk3562-mipi-csi2";
rockchip,hw = <&mipi0_csi2_hw>, <&mipi1_csi2_hw>,
<&mipi2_csi2_hw>, <&mipi3_csi2_hw>;
status = "disabled";
};
mipi3_csi2: mipi3-csi2 {
compatible = "rockchip,rk3562-mipi-csi2";
rockchip,hw = <&mipi0_csi2_hw>, <&mipi1_csi2_hw>,
<&mipi2_csi2_hw>, <&mipi3_csi2_hw>;
status = "disabled";
};
psci {
compatible = "arm,psci-1.0";
method = "smc";
@ -815,6 +843,8 @@
snps,dis-del-phy-power-chg-quirk;
snps,dis-tx-ipgap-linecheck-quirk;
snps,dis_rxdet_inp3_quirk;
snps,parkmode-disable-hs-quirk;
snps,parkmode-disable-ss-quirk;
quirk-skip-phy-init;
status = "disabled";
};
@ -1110,9 +1140,9 @@
#reset-cells = <1>;
assigned-clocks =
<&cru PLL_GPLL>, <&cru PLL_CPLL>;
<&cru PLL_GPLL>, <&cru PLL_CPLL>, <&cru PLL_HPLL>;
assigned-clock-rates =
<1188000000>, <1000000000>;
<1188000000>, <1000000000>, <983040000>;
};
i2c0: i2c@ff200000 {
@ -1554,8 +1584,8 @@
status = "disabled";
};
mipi0_csi2: mipi0-csi2@ff380000 {
compatible = "rockchip,rk3562-mipi-csi2";
mipi0_csi2_hw: mipi0-csi2-hw@ff380000 {
compatible = "rockchip,rk3562-mipi-csi2-hw";
reg = <0x0 0xff380000 0x0 0x10000>;
reg-names = "csihost_regs";
interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>,
@ -1565,11 +1595,11 @@
clock-names = "pclk_csi2host";
resets = <&cru SRST_P_CSIHOST0>;
reset-names = "srst_csihost_p";
status = "disabled";
status = "okay";
};
mipi1_csi2: mipi1-csi2@ff390000 {
compatible = "rockchip,rk3562-mipi-csi2";
mipi1_csi2_hw: mipi1-csi2-hw@ff390000 {
compatible = "rockchip,rk3562-mipi-csi2-hw";
reg = <0x0 0xff390000 0x0 0x10000>;
reg-names = "csihost_regs";
interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>,
@ -1579,11 +1609,11 @@
clock-names = "pclk_csi2host";
resets = <&cru SRST_P_CSIHOST1>;
reset-names = "srst_csihost_p";
status = "disabled";
status = "okay";
};
mipi2_csi2: mipi2-csi2@ff3a0000 {
compatible = "rockchip,rk3562-mipi-csi2";
mipi2_csi2_hw: mipi2-csi2-hw@ff3a0000 {
compatible = "rockchip,rk3562-mipi-csi2-hw";
reg = <0x0 0xff3a0000 0x0 0x10000>;
reg-names = "csihost_regs";
interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>,
@ -1593,11 +1623,11 @@
clock-names = "pclk_csi2host";
resets = <&cru SRST_P_CSIHOST2>;
reset-names = "srst_csihost_p";
status = "disabled";
status = "okay";
};
mipi3_csi2: mipi3-csi2@ff3b0000 {
compatible = "rockchip,rk3562-mipi-csi2";
mipi3_csi2_hw: mipi3-csi2-hw@ff3b0000 {
compatible = "rockchip,rk3562-mipi-csi2-hw";
reg = <0x0 0xff3b0000 0x0 0x10000>;
reg-names = "csihost_regs";
interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>,
@ -1607,7 +1637,7 @@
clock-names = "pclk_csi2host";
resets = <&cru SRST_P_CSIHOST3>;
reset-names = "srst_csihost_p";
status = "disabled";
status = "okay";
};
csi2_dphy0_hw: csi2-dphy0-hw@ff3c0000 {
@ -1618,7 +1648,7 @@
resets = <&cru SRST_P_CSIPHY0>;
reset-names = "srst_p_csiphy0";
rockchip,grf = <&sys_grf>;
status = "disabled";
status = "okay";
};
csi2_dphy1_hw: csi2-dphy1-hw@ff3d0000 {
@ -1629,7 +1659,7 @@
resets = <&cru SRST_P_CSIPHY1>;
reset-names = "srst_p_csiphy1";
rockchip,grf = <&sys_grf>;
status = "disabled";
status = "okay";
};
rkcif: rkcif@ff3e0000 {
@ -2221,6 +2251,8 @@
interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru MCLK_SAI0>, <&cru HCLK_SAI0>;
clock-names = "mclk", "hclk";
assigned-clocks = <&cru CLK_SAI0_SRC>;
assigned-clock-parents = <&cru PLL_HPLL>;
dmas = <&dmac 19>, <&dmac 18>;
dma-names = "tx", "rx";
resets = <&cru SRST_M_SAI0_8CH>, <&cru SRST_H_SAI0_8CH>;
@ -2234,6 +2266,7 @@
&i2s0m0_sdo2
&i2s0m0_sdo3>;
#sound-dai-cells = <0>;
sound-name-prefix = "SAI0";
status = "disabled";
};
@ -2243,6 +2276,8 @@
interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru MCLK_SAI1>, <&cru HCLK_SAI1>;
clock-names = "mclk", "hclk";
assigned-clocks = <&cru CLK_SAI1_SRC>;
assigned-clock-parents = <&cru PLL_HPLL>;
dmas = <&dmac 21>, <&dmac 20>;
dma-names = "tx", "rx";
resets = <&cru SRST_M_SAI1_8CH>, <&cru SRST_H_SAI1_8CH>;
@ -2259,6 +2294,7 @@
&i2s1m0_sdo2
&i2s1m0_sdo3>;
#sound-dai-cells = <0>;
sound-name-prefix = "SAI1";
status = "disabled";
};
@ -2268,6 +2304,8 @@
interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru MCLK_SAI2>, <&cru HCLK_SAI2>;
clock-names = "mclk", "hclk";
assigned-clocks = <&cru CLK_SAI2_SRC>;
assigned-clock-parents = <&cru PLL_HPLL>;
dmas = <&dmac 23>, <&dmac 22>;
dma-names = "tx", "rx";
resets = <&cru SRST_M_SAI2_2CH>, <&cru SRST_H_SAI2_2CH>;
@ -2278,6 +2316,7 @@
&i2s2m0_sdi
&i2s2m0_sdo>;
#sound-dai-cells = <0>;
sound-name-prefix = "SAI2";
status = "disabled";
};
@ -2286,6 +2325,8 @@
reg = <0x0 0xff830000 0x0 0x1000>;
clocks = <&cru MCLK_PDM>, <&cru HCLK_PDM>;
clock-names = "pdm_clk", "pdm_hclk";
assigned-clocks = <&cru MCLK_PDM>;
assigned-clock-parents = <&cru PLL_HPLL>;
dmas = <&dmac 31>;
dma-names = "rx";
pinctrl-names = "default";
@ -2307,6 +2348,8 @@
dma-names = "tx";
clock-names = "mclk", "hclk";
clocks = <&cru MCLK_SPDIF>, <&cru HCLK_SPDIF>;
assigned-clocks = <&cru CLK_SPDIF_SRC>;
assigned-clock-parents = <&cru PLL_HPLL>;
#sound-dai-cells = <0>;
pinctrl-names = "default";
pinctrl-0 = <&spdifm0_pins>;

4
arch/arm64/boot/dts/rockchip/rk3566.dtsi
View File

@ -8,6 +8,7 @@
/ {
aliases {
/delete-property/ ethernet0;
/delete-property/ lvds1;
};
};
@ -55,6 +56,7 @@
/delete-node/ &gmac0_xpcsclk;
/delete-node/ &gmac0;
/delete-node/ &gmac_uio0;
/delete-node/ &lvds1;
/delete-node/ &pcie30_phy_grf;
/delete-node/ &pcie30phy;
/delete-node/ &pcie3x1;
@ -63,3 +65,5 @@
/delete-node/ &qos_pcie3x2;
/delete-node/ &qos_sata0;
/delete-node/ &sata0;
/delete-node/ &vp1_out_lvds1;
/delete-node/ &vp2_out_lvds1;

168
arch/arm64/boot/dts/rockchip/rk3567-evb2-lp4x-v10-dual-channel-lvds.dts Normal file
View File

@ -0,0 +1,168 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (c) 2023 Rockchip Electronics Co., Ltd.
*/
/dts-v1/;
#include <dt-bindings/display/media-bus-format.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/pinctrl/rockchip.h>
#include "rk3567-evb2-lp4x-v10.dtsi"
#include "rk3568-android.dtsi"
/ {
model = "Rockchip RK3567 EVB2 LP4X V10 Board";
compatible = "rockchip,rk3567-evb2-lp4x-v10", "rockchip,rk3567";
panel {
compatible = "simple-panel";
backlight = <&backlight>;
power-supply = <&vcc3v3_lcd0_n>;
enable-delay-ms = <20>;
prepare-delay-ms = <20>;
unprepare-delay-ms = <20>;
disable-delay-ms = <20>;
bus-format = <MEDIA_BUS_FMT_RGB888_1X7X4_SPWG>;
width-mm = <217>;
height-mm = <136>;
display-timings {
native-mode = <&timing0>;
timing0: timing0 {
clock-frequency = <148500000>;
hactive = <1920>;
vactive = <1080>;
hback-porch = <96>;
hfront-porch = <120>;
vback-porch = <16>;
vfront-porch = <64>;
hsync-len = <64>;
vsync-len = <16>;
hsync-active = <0>;
vsync-active = <0>;
de-active = <0>;
pixelclk-active = <0>;
};
};
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
dual-lvds-odd-pixels;
panel_in_lvds0: endpoint {
remote-endpoint = <&lvds0_out_panel>;
};
};
port@1 {
reg = <1>;
dual-lvds-even-pixels;
panel_in_lvds1: endpoint {
remote-endpoint = <&lvds1_out_panel>;
};
};
};
};
};
&backlight1 {
status = "okay";
};
&backlight {
status = "okay";
};
&lvds {
status = "okay";
dual-channel;
ports {
port@1 {
reg = <1>;
lvds0_out_panel: endpoint {
remote-endpoint = <&panel_in_lvds0>;
};
};
};
};
&lvds1 {
status = "okay";
ports {
port@1 {
reg = <1>;
lvds1_out_panel: endpoint {
remote-endpoint = <&panel_in_lvds1>;
};
};
};
};
&lvds_in_vp1 {
status = "okay";
};
&lvds1_in_vp1 {
status = "disabled";
};
&lvds1_in_vp2 {
status = "okay";
};
/* enable hdmi */
&hdmi_in_vp1 {
status = "okay";
};
/* enable video phy */
&video_phy0 {
status = "okay";
};
&video_phy1 {
status = "okay";
};
/* disable other encoder output */
&dsi0 {
status = "disabled";
};
&dsi0_in_vp0 {
status = "disabled";
};
&dsi0_in_vp1 {
status = "disabled";
};
&dsi1_in_vp1 {
status = "disabled";
};
&edp_in_vp1 {
status = "disabled";
};
&rgb_in_vp2 {
status = "disabled";
};
&vcc3v3_lcd0_n {
gpio = <&gpio0 RK_PC7 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
&vcc3v3_lcd1_n {
gpio = <&gpio0 RK_PC5 GPIO_ACTIVE_HIGH>;
enable-active-high;
};

172
arch/arm64/boot/dts/rockchip/rk3567-evb2-lp4x-v10-dual-lvds.dts Normal file
View File

@ -0,0 +1,172 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (c) 2023 Rockchip Electronics Co., Ltd.
*/
/dts-v1/;
#include <dt-bindings/display/media-bus-format.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/pinctrl/rockchip.h>
#include "rk3567-evb2-lp4x-v10.dtsi"
#include "rk3568-android.dtsi"
/ {
model = "Rockchip RK3567 EVB2 LP4X V10 Board";
compatible = "rockchip,rk3567-evb2-lp4x-v10", "rockchip,rk3567";
panel {
compatible = "simple-panel";
backlight = <&backlight>;
power-supply = <&vcc3v3_lcd0_n>;
enable-delay-ms = <20>;
prepare-delay-ms = <20>;
unprepare-delay-ms = <20>;
disable-delay-ms = <20>;
bus-format = <MEDIA_BUS_FMT_RGB666_1X7X3_SPWG>;
width-mm = <217>;
height-mm = <136>;
display-timings {
native-mode = <&timing0>;
timing0: timing0 {
clock-frequency = <134000000>;
hactive = <1600>;
vactive = <1280>;
hback-porch = <60>;
hfront-porch = <60>;
vback-porch = <4>;
vfront-porch = <2>;
hsync-len = <8>;
vsync-len = <2>;
hsync-active = <0>;
vsync-active = <0>;
de-active = <0>;
pixelclk-active = <0>;
};
};
ports {
#address-cells = <1>;
#size-cells = <0>;
/**
* Panel <----> LVDS0
* Panel <----> LVDS1
*/
port@0 {
reg = <0>;
dual-lvds-left-pixels;
panel_in_lvds0: endpoint {
remote-endpoint = <&lvds0_out_panel>;
};
};
port@1 {
reg = <1>;
dual-lvds-right-pixels;
panel_in_lvds1: endpoint {
remote-endpoint = <&lvds1_out_panel>;
};
};
};
};
};
&backlight1 {
status = "okay";
};
&backlight {
status = "okay";
};
&lvds {
status = "okay";
dual-channel;
ports {
port@1 {
reg = <1>;
lvds0_out_panel: endpoint {
remote-endpoint = <&panel_in_lvds0>;
};
};
};
};
&lvds1 {
status = "okay";
ports {
port@1 {
reg = <1>;
lvds1_out_panel: endpoint {
remote-endpoint = <&panel_in_lvds1>;
};
};
};
};
&lvds_in_vp1 {
status = "okay";
};
&lvds1_in_vp1 {
status = "disabled";
};
&lvds1_in_vp2 {
status = "okay";
};
/* enable hdmi */
&hdmi_in_vp1 {
status = "okay";
};
/* enable video phy */
&video_phy0 {
status = "okay";
};
&video_phy1 {
status = "okay";
};
/* disable other encoder output */
&dsi0 {
status = "disabled";
};
&dsi0_in_vp0 {
status = "disabled";
};
&dsi0_in_vp1 {
status = "disabled";
};
&dsi1_in_vp1 {
status = "disabled";
};
&edp_in_vp1 {
status = "disabled";
};
&rgb_in_vp2 {
status = "disabled";
};
&vcc3v3_lcd0_n {
gpio = <&gpio0 RK_PC7 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
&vcc3v3_lcd1_n {
gpio = <&gpio0 RK_PC5 GPIO_ACTIVE_HIGH>;
enable-active-high;
};

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