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Add wl source code

This commit is contained in:
leeboby 2020-11-18 10:07:26 +08:00
parent 2dbd89c6ae
commit 3ce7777768
147 changed files with 103999 additions and 0 deletions
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1
external/cache/sources/wl/Android.mk vendored Normal file
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include $(call all-subdir-makefiles)

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external/cache/sources/wl/Makefile vendored Normal file
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all: wl_tool dhd_tool
wl_tool:
$(MAKE) -C shared CROSS_COMPILE=$(CROSS_COMPILE)
$(MAKE) -C wl CROSS_COMPILE=$(CROSS_COMPILE)
dhd_tool:
$(MAKE) -C shared CROSS_COMPILE=$(CROSS_COMPILE)
$(MAKE) -C dhd CROSS_COMPILE=$(CROSS_COMPILE)
clean:
$(MAKE) clean -C shared CROSS_COMPILE=$(CROSS_COMPILE)
$(MAKE) clean -C wl CROSS_COMPILE=$(CROSS_COMPILE)
$(MAKE) clean -C dhd CROSS_COMPILE=$(CROSS_COMPILE)

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external/cache/sources/wl/dhd/Android.mk vendored Normal file
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LOCAL_PATH:= $(call my-dir)
#OBJS_c := dhdu.c dhdu_linux.c bcmutils.c miniopt.c
OBJS_c := dhdu.c dhdu_linux.c ucode_download.c
#OBJS_c += ../shared/bcmutils.c ../shared/miniopt.c ../shared/wlu_pipe.c ../shared/wlu_pipe_linux.c ../shared/wlu_client_shared.c
INCLUDES := $(LOCAL_PATH)/../include $(LOCAL_PATH)/../shared
L_CFLAGS := -DBCMWPA2 -DWLCNT -DWLBTAMP -Wextra -DWLPFN -DWLPFN_AUTO_CONNECT -DLINUX -DRWLASD -DRWL_SOCKET -DRWL_DONGLE -DRWL_WIFI
L_CFLAGS += -DSDTEST -DTARGETENV_android -Dlinux -DLINUX
include $(CLEAR_VARS)
LOCAL_MODULE := dhd
LOCAL_MODULE_TAGS := debug tests
LOCAL_SHARED_LIBRARIES := libcutils
LOCAL_STATIC_LIBRARIES := libshared
LOCAL_CFLAGS = $(L_CFLAGS)
LOCAL_SRC_FILES := $(OBJS_c)
LOCAL_C_INCLUDES := $(INCLUDES)
LOCAL_MODULE_PATH := $(TARGET_OUT_OPTIONAL_EXECUTABLES)
include $(BUILD_EXECUTABLE)
include $(CLEAR_VARS)
LOCAL_MODULE := libdhd
LOCAL_MODULE_TAGS := debug tests
LOCAL_SHARED_LIBRARIES := libcutils
LOCAL_STATIC_LIBRARIES := libshared
LOCAL_CFLAGS = $(L_CFLAGS)
LOCAL_CFLAGS += -DLIB
LOCAL_SRC_FILES := $(OBJS_c)
LOCAL_C_INCLUDES := $(INCLUDES)
include $(BUILD_STATIC_LIBRARY)

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external/cache/sources/wl/dhd/Makefile vendored Normal file
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CC = $(CROSS_COMPILE)gcc
#IFLAGS := -I../include -I../wl -I../shared -g -Wall -static
IFLAGS := -I../include -I../wl -I../shared -g -Wall
DFLAGS := -DBCMWPA2 -DWLCNT -DWLBTAMP -Wextra -DWLPFN -DWLPFN_AUTO_CONNECT -DLINUX -DRWLASD -DRWL_SOCKET -DRWL_DONGLE -DRWL_WIFI
#IFLAGS += -DIL_BIGENDIAN
obj-dhd = dhdu.o dhdu_linux.o ucode_download.o
DHD = dhd
ALL = all
LIBLINK := ../shared/libshared.a
LIBDHD = libdhd.a
CFLAGS += $(IFLAGS) $(DFLAGS)
ifeq ($(LIB),y)
CFLAGS += -DLIB
endif
all: $(ALL)
$(ALL):
make clean
make $(DHD)
mv dhd dhd.back
make clean
make $(LIBDHD) LIB=y
mv dhd.back dhd
$(DHD): $(obj-dhd)
$(CC) -o $@ $(obj-dhd) $(LIBLINK)
$(LIBDHD): $(obj-dhd)
ar rscv $(LIBDHD) $(obj-dhd) $(LIBLINK)
# $(CC) $(obj-dhd) -shared -o $(LIBDHD) $(LIBLINK)
# for sequance
# $(CC) -Wl,-elf2flt -o $@ $(obj-dhd)
clean:
-rm -f $(DHD) *.o *.a *.so

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external/cache/sources/wl/dhd/dhdu.c vendored Normal file
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51
external/cache/sources/wl/dhd/dhdu.h vendored Normal file
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/*
* Definitions for DHD command-line utility
*
* $Copyright Open Broadcom Corporation$
*
* $Id: dhdu.h 294362 2011-11-06 22:26:56Z $
*/
#ifndef _dhdu_h_
#define _dhdu_h_
#include "dhdu_cmd.h"
extern char *dhdu_av0;
/* parse common option */
extern int dhd_option(char ***pargv, char **pifname, int *phelp);
extern void dhd_cmd_init(void);
/* print usage */
extern void dhd_cmd_usage(cmd_t *cmd);
extern void dhd_usage(cmd_t *port_cmds);
extern void dhd_cmds_usage(cmd_t *port_cmds);
/* print helpers */
extern void dhd_printlasterror(void *dhd);
extern void dhd_printint(int val);
/* check driver version */
extern int dhd_check(void *dhd);
/* utility functions */
struct ipv4_addr;
int dhd_ether_atoe(const char *a, struct ether_addr *n);
int dhd_atoip(const char *a, struct ipv4_addr *n);
#define USAGE_ERROR -1 /* Error code for Usage */
#define IOCTL_ERROR -2 /* Error code for ioctl failure */
#define COMMAND_ERROR -3 /* Error code for general command failure */
/* integer output format */
#define INT_FMT_DEC 0 /* signed integer */
#define INT_FMT_UINT 1 /* unsigned integer */
#define INT_FMT_HEX 2 /* hexdecimal */
/* command line argument usage */
#define CMD_ERR -1 /* Error for command */
#define CMD_OPT 0 /* a command line option */
#define CMD_DHD 1 /* the start of a dhd command */
#endif /* _dhdu_h_ */

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external/cache/sources/wl/dhd/dhdu_cmd.h vendored Normal file
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/*
* Command structure for dhd command line utility, copied from wl utility
*
* $Copyright Open Broadcom Corporation$
*
* $Id: dhdu_cmd.h 241182 2011-02-17 21:50:03Z $
*/
#ifndef _dhdu_cmd_h_
#define _dhdu_cmd_h_
typedef struct cmd cmd_t;
typedef int (cmd_func_t)(void *dhd, cmd_t *cmd, char **argv);
/* generic command line argument handler */
struct cmd {
char *name;
cmd_func_t *func;
int get;
int set;
char *help;
};
/* list of command line arguments */
extern cmd_t dhd_cmds[];
extern cmd_t dhd_varcmd;
/* Special set cmds to do download via dev node interface if present */
#define DHD_DLDN_ST 0x400
#define DHD_DLDN_WRITE (DHD_DLDN_ST + 1)
#define DHD_DLDN_END (DHD_DLDN_ST + 2)
/* per-port ioctl handlers */
extern int dhd_get(void *dhd, int cmd, void *buf, int len);
extern int dhd_set(void *dhd, int cmd, void *buf, int len);
#endif /* _dhdu_cmd_h_ */

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external/cache/sources/wl/dhd/dhdu_common.h vendored Normal file
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/*
* Linux port of dhd command line utility, hacked from wl utility.
*
* Copyright (C) 2013, Broadcom Corporation
* All Rights Reserved.
*
* This is UNPUBLISHED PROPRIETARY SOURCE CODE of Broadcom Corporation;
* the contents of this file may not be disclosed to third parties, copied
* or duplicated in any form, in whole or in part, without the prior
* written permission of Broadcom Corporation.
*
* $Id: dhdu_common.h 281524 2011-09-02 17:09:25Z $
*/
/* Common header file for dhdu_linux.c and dhdu_ndis.c */
#ifndef _dhdu_common_h
#define _dhdu_common_h
/* DHD utility function declarations */
extern int dhd_check(void *dhd);
extern int dhd_atoip(const char *a, struct ipv4_addr *n);
extern int dhd_option(char ***pargv, char **pifname, int *phelp);
void dhd_usage(cmd_t *port_cmds);
/* Remote DHD declarations */
int remote_type = NO_REMOTE;
extern char *g_rwl_buf_mac;
extern char* g_rwl_device_name_serial;
unsigned short g_rwl_servport;
char *g_rwl_servIP = NULL;
unsigned short defined_debug = DEBUG_ERR | DEBUG_INFO;
static int process_args(struct ifreq* ifr, char **argv);
#define dtoh32(i) i
#define dtoh16(i) i
#endif /* _dhdu_common_h_ */

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/*
* Linux port of dhd command line utility, hacked from wl utility.
*
* $Copyright Open Broadcom Corporation$
*
* $Id: dhdu_linux.c 281524 2011-09-02 17:09:25Z $
*/
#include <stdio.h>
#include <stdlib.h>
#include <unistd.h>
#include <ctype.h>
#include <string.h>
#include <errno.h>
#include <sys/types.h>
#include <sys/wait.h>
#include <sys/socket.h>
#include <proto/ethernet.h>
#include <proto/bcmip.h>
#include <arpa/inet.h>
#include <sys/ioctl.h>
#include <net/if.h>
#include <fcntl.h>
#include <sys/ioctl.h>
#include <unistd.h>
#ifndef TARGETENV_android
#include <error.h>
typedef u_int64_t u64;
typedef u_int32_t u32;
typedef u_int16_t u16;
typedef u_int8_t u8;
#endif /* TARGETENV_android */
#include <linux/sockios.h>
#include <linux/types.h>
#include <linux/ethtool.h>
#include <typedefs.h>
#include <signal.h>
#include <dhdioctl.h>
#include <wlioctl.h>
#include <bcmcdc.h>
#include <bcmutils.h>
#include "dhdu.h"
#include "wlu_remote.h"
#include "wlu_client_shared.h"
#include "wlu_pipe.h"
#include <netdb.h>
#include <netinet/in.h>
#include <dhdioctl.h>
#include "dhdu_common.h"
char *av0;
static int rwl_os_type = LINUX_OS;
/* Search the dhd_cmds table for a matching command name.
* Return the matching command or NULL if no match found.
*/
static cmd_t *
dhd_find_cmd(char* name)
{
cmd_t *cmd = NULL;
/* search the dhd_cmds for a matching name */
for (cmd = dhd_cmds; cmd->name && strcmp(cmd->name, name); cmd++);
if (cmd->name == NULL)
cmd = NULL;
return cmd;
}
static void
syserr(char *s)
{
fprintf(stderr, "%s: ", dhdu_av0);
perror(s);
exit(errno);
}
/* This function is called by ioctl_setinformation_fe or ioctl_queryinformation_fe
* for executing remote commands or local commands
*/
static int
dhd_ioctl(void *dhd, int cmd, void *buf, int len, bool set)
{
struct ifreq *ifr = (struct ifreq *)dhd;
dhd_ioctl_t ioc;
int ret = 0;
int s;
/* By default try to execute wl commands */
int driver_magic = WLC_IOCTL_MAGIC;
int get_magic = WLC_GET_MAGIC;
/* For local dhd commands execute dhd. For wifi transport we still
* execute wl commands.
*/
if (remote_type == NO_REMOTE && strncmp (buf, RWL_WIFI_ACTION_CMD,
strlen(RWL_WIFI_ACTION_CMD)) && strncmp(buf, RWL_WIFI_GET_ACTION_CMD,
strlen(RWL_WIFI_GET_ACTION_CMD))) {
driver_magic = DHD_IOCTL_MAGIC;
get_magic = DHD_GET_MAGIC;
}
/* open socket to kernel */
if ((s = socket(AF_INET, SOCK_DGRAM, 0)) < 0)
syserr("socket");
/* do it */
ioc.cmd = cmd;
ioc.buf = buf;
ioc.len = len;
ioc.set = set;
ioc.driver = driver_magic;
ifr->ifr_data = (caddr_t) &ioc;
if ((ret = ioctl(s, SIOCDEVPRIVATE, ifr)) < 0) {
if (cmd != get_magic) {
ret = IOCTL_ERROR;
}
}
/* cleanup */
close(s);
return ret;
}
/* This function is called in wlu_pipe.c remote_wifi_ser_init() to execute
* the initial set of wl commands for wifi transport (e.g slow_timer, fast_timer etc)
*/
int wl_ioctl(void *wl, int cmd, void *buf, int len, bool set)
{
return dhd_ioctl(wl, cmd, buf, len, set); /* Call actual wl_ioctl here: Shubhro */
}
/* Search if dhd adapter or wl adapter is present
* This is called by dhd_find to check if it supports wl or dhd
* The reason for checking wl adapter is that we can still send remote dhd commands over
* wifi transport.
*/
static int
dhd_get_dev_type(char *name, void *buf, char *type)
{
int s;
int ret;
struct ifreq ifr;
struct ethtool_drvinfo info;
/* open socket to kernel */
if ((s = socket(AF_INET, SOCK_DGRAM, 0)) < 0)
syserr("socket");
/* get device type */
memset(&info, 0, sizeof(info));
info.cmd = ETHTOOL_GDRVINFO;
strcpy(info.driver, "?");
strcat(info.driver, type);
ifr.ifr_data = (caddr_t)&info;
strncpy(ifr.ifr_name, name, IFNAMSIZ);
if ((ret = ioctl(s, SIOCETHTOOL, &ifr)) < 0) {
/* print a good diagnostic if not superuser */
if (errno == EPERM)
syserr("dhd_get_dev_type");
*(char *)buf = '\0';
}
else
strcpy(buf, info.driver);
close(s);
return ret;
}
/* dhd_get/dhd_set is called by several functions in dhdu.c. This used to call dhd_ioctl
* directly. However now we need to execute the dhd commands remotely.
* So we make use of wl pipes to execute this.
* wl_get or wl_set functions also check if it is a local command hence they in turn
* call dhd_ioctl if required. Name wl_get/wl_set is retained because these functions are
* also called by wlu_pipe.c wlu_client_shared.c
*/
int
dhd_get(void *dhd, int cmd, void *buf, int len)
{
return wl_get(dhd, cmd, buf, len);
}
/*
* To use /dev/node interface:
* 1. mknod /dev/hnd0 c 248 0
* 2. chmod 777 /dev/hnd0
*/
#define NODE "/dev/hnd0"
int
dhd_set(void *dhd, int cmd, void *buf, int len)
{
static int dnode = -1;
switch (cmd) {
case DHD_DLDN_ST:
if (dnode == -1)
dnode = open(NODE, O_RDWR);
else
fprintf(stderr, "devnode already opened!\n");
return dnode;
break;
case DHD_DLDN_WRITE:
if (dnode > 0)
return write(dnode, buf, len);
break;
case DHD_DLDN_END:
if (dnode > 0)
return close(dnode);
break;
default:
return wl_set(dhd, cmd, buf, len);
}
return -1;
}
/* Verify the wl adapter found.
* This is called by dhd_find to check if it supports wl
* The reason for checking wl adapter is that we can still send remote dhd commands over
* wifi transport. The function is copied from wlu.c.
*/
int
wl_check(void *wl)
{
int ret;
int val = 0;
if (!dhd_check (wl))
return 0;
/*
* If dhd_check() fails then go for a regular wl driver verification
*/
if ((ret = wl_get(wl, WLC_GET_MAGIC, &val, sizeof(int))) < 0)
return ret;
if (val != WLC_IOCTL_MAGIC)
return BCME_ERROR;
if ((ret = wl_get(wl, WLC_GET_VERSION, &val, sizeof(int))) < 0)
return ret;
if (val > WLC_IOCTL_VERSION) {
fprintf(stderr, "Version mismatch, please upgrade\n");
return BCME_ERROR;
}
return 0;
}
/* Search and verify the request type of adapter (wl or dhd)
* This is called by main before executing local dhd commands
* or sending remote dhd commands over wifi transport
*/
void
dhd_find(struct ifreq *ifr, char *type)
{
char proc_net_dev[] = "/proc/net/dev";
FILE *fp;
static char buf[400];
char *c, *name;
char dev_type[32];
ifr->ifr_name[0] = '\0';
/* eat first two lines */
if (!(fp = fopen(proc_net_dev, "r")) ||
!fgets(buf, sizeof(buf), fp) ||
!fgets(buf, sizeof(buf), fp))
return;
while (fgets(buf, sizeof(buf), fp)) {
c = buf;
while (isspace(*c))
c++;
if (!(name = strsep(&c, ":")))
continue;
strncpy(ifr->ifr_name, name, IFNAMSIZ);
if (dhd_get_dev_type(name, dev_type, type) >= 0 &&
!strncmp(dev_type, type, strlen(dev_type) - 1))
{
if (!wl_check((void*)ifr))
break;
}
ifr->ifr_name[0] = '\0';
}
fclose(fp);
}
/* This function is called by wl_get to execute either local dhd command
* or send a dhd command over wl transport
*/
static int
ioctl_queryinformation_fe(void *wl, int cmd, void* input_buf, int *input_len)
{
if (remote_type == NO_REMOTE) {
return dhd_ioctl(wl, cmd, input_buf, *input_len, FALSE);
} else {
return rwl_queryinformation_fe(wl, cmd, input_buf,
(unsigned long*)input_len, 0, RDHD_GET_IOCTL);
}
}
/* This function is called by wl_set to execute either local dhd command
* or send a dhd command over wl transport
*/
static int
ioctl_setinformation_fe(void *wl, int cmd, void* buf, int *len)
{
if (remote_type == NO_REMOTE) {
return dhd_ioctl(wl, cmd, buf, *len, TRUE);
} else {
return rwl_setinformation_fe(wl, cmd, buf, (unsigned long*)len, 0, RDHD_SET_IOCTL);
}
}
/* The function is replica of wl_get in wlu_linux.c. Optimize when we have some
* common code between wlu_linux.c and dhdu_linux.c
*/
int
wl_get(void *wl, int cmd, void *buf, int len)
{
int error = BCME_OK;
/* For RWL: When interfacing to a Windows client, need t add in OID_BASE */
if ((rwl_os_type == WIN32_OS) && (remote_type != NO_REMOTE)) {
error = (int)ioctl_queryinformation_fe(wl, WL_OID_BASE + cmd, buf, &len);
} else {
error = (int)ioctl_queryinformation_fe(wl, cmd, buf, &len);
}
if (error == SERIAL_PORT_ERR)
return SERIAL_PORT_ERR;
if (error != 0)
return IOCTL_ERROR;
return error;
}
/* The function is replica of wl_set in wlu_linux.c. Optimize when we have some
* common code between wlu_linux.c and dhdu_linux.c
*/
int
wl_set(void *wl, int cmd, void *buf, int len)
{
int error = BCME_OK;
/* For RWL: When interfacing to a Windows client, need t add in OID_BASE */
if ((rwl_os_type == WIN32_OS) && (remote_type != NO_REMOTE)) {
error = (int)ioctl_setinformation_fe(wl, WL_OID_BASE + cmd, buf, &len);
} else {
error = (int)ioctl_setinformation_fe(wl, cmd, buf, &len);
}
if (error == SERIAL_PORT_ERR)
return SERIAL_PORT_ERR;
if (error != 0) {
return IOCTL_ERROR;
}
return error;
}
int
wl_validatedev(void *dev_handle)
{
int retval = 1;
struct ifreq *ifr = (struct ifreq *)dev_handle;
/* validate the interface */
if (!ifr->ifr_name || wl_check((void *)ifr)) {
retval = 0;
}
return retval;
}
/* Main client function
* The code is mostly from wlu_linux.c. This function takes care of executing remote dhd commands
* along with the local dhd commands now.
*/
int
#if defined(LIB)
dhd_main(int argc, char **argv)
#else
main(int argc, char **argv)
#endif
{
struct ifreq ifr;
char *ifname = NULL;
int err = 0;
int help = 0;
int status = CMD_DHD;
void* serialHandle = NULL;
UNUSED_PARAMETER(argc);
av0 = argv[0];
memset(&ifr, 0, sizeof(ifr));
argv++;
if ((status = dhd_option(&argv, &ifname, &help)) == CMD_OPT) {
if (ifname)
strncpy(ifr.ifr_name, ifname, IFNAMSIZ);
}
/* Linux client looking for a Win32 server */
if (*argv && strncmp (*argv, "--wince", strlen(*argv)) == 0) {
rwl_os_type = WIN32_OS;
argv++;
}
/* RWL socket transport Usage: --socket ipaddr [port num] */
if (*argv && strncmp (*argv, "--socket", strlen(*argv)) == 0) {
argv++;
remote_type = REMOTE_SOCKET;
if (!(*argv)) {
rwl_usage(remote_type);
return err;
}
g_rwl_servIP = *argv;
argv++;
g_rwl_servport = DEFAULT_SERVER_PORT;
if ((*argv) && isdigit(**argv)) {
g_rwl_servport = atoi(*argv);
argv++;
}
}
/* RWL from system serial port on client to uart dongle port on server */
/* Usage: --dongle /dev/ttyS0 */
if (*argv && strncmp (*argv, "--dongle", strlen(*argv)) == 0) {
argv++;
remote_type = REMOTE_DONGLE;
if (!(*argv)) {
rwl_usage(remote_type);
return err;
}
g_rwl_device_name_serial = *argv;
argv++;
if ((serialHandle = rwl_open_pipe(remote_type, "\0", 0, 0)) == NULL) {
DPRINT_ERR(ERR, "serial device open error\r\n");
return BCME_ERROR;
}
ifr = (*(struct ifreq *)serialHandle);
}
/* RWL over wifi. Usage: --wifi mac_address */
if (*argv && strncmp (*argv, "--wifi", strlen(*argv)) == 0) {
argv++;
remote_type = NO_REMOTE;
if (!ifr.ifr_name[0])
{
dhd_find(&ifr, "wl");
}
/* validate the interface */
if (!ifr.ifr_name[0] || wl_check((void*)&ifr)) {
fprintf(stderr, "%s: wl driver adapter not found\n", av0);
exit(1);
}
remote_type = REMOTE_WIFI;
if (argc < 4) {
rwl_usage(remote_type);
return err;
}
/* copy server mac address to local buffer for later use by findserver cmd */
if (!dhd_ether_atoe(*argv, (struct ether_addr *)g_rwl_buf_mac)) {
fprintf(stderr,
"could not parse as an ethernet MAC address\n");
return FAIL;
}
argv++;
}
/* Process for local dhd */
if (remote_type == NO_REMOTE) {
err = process_args(&ifr, argv);
return err;
}
if (*argv) {
err = process_args(&ifr, argv);
if ((err == SERIAL_PORT_ERR) && (remote_type == REMOTE_DONGLE)) {
DPRINT_ERR(ERR, "\n Retry again\n");
err = process_args((struct ifreq*)&ifr, argv);
}
return err;
}
rwl_usage(remote_type);
if (remote_type == REMOTE_DONGLE)
rwl_close_pipe(remote_type, (void*)&ifr);
return err;
}
/*
* Function called for 'local' execution and for 'remote' non-interactive session
* (shell cmd, wl cmd) .The code is mostly from wlu_linux.c. This code can be
* common to wlu_linux.c and dhdu_linux.c
*/
static int
process_args(struct ifreq* ifr, char **argv)
{
char *ifname = NULL;
int help = 0;
int status = 0;
int err = BCME_OK;
cmd_t *cmd = NULL;
while (*argv) {
if ((strcmp (*argv, "sh") == 0) && (remote_type != NO_REMOTE)) {
argv++; /* Get the shell command */
if (*argv) {
/* Register handler in case of shell command only */
signal(SIGINT, ctrlc_handler);
err = rwl_shell_cmd_proc((void*)ifr, argv, SHELL_CMD);
} else {
DPRINT_ERR(ERR,
"Enter the shell command (e.g ls(Linux) or dir(Win CE) \n");
err = BCME_ERROR;
}
return err;
}
if ((status = dhd_option(&argv, &ifname, &help)) == CMD_OPT) {
if (help)
break;
if (ifname)
strncpy(ifr->ifr_name, ifname, IFNAMSIZ);
continue;
}
/* parse error */
else if (status == CMD_ERR)
break;
if (remote_type == NO_REMOTE) {
/* use default interface */
if (!ifr->ifr_name[0])
dhd_find(ifr, "dhd");
/* validate the interface */
if (!ifr->ifr_name[0] || dhd_check((void *)ifr)) {
if (strcmp("dldn", *argv) != 0) {
fprintf(stderr, "%s: dhd driver adapter not found\n", av0);
exit(BCME_ERROR);
}
}
}
/* search for command */
cmd = dhd_find_cmd(*argv);
/* if not found, use default set_var and get_var commands */
if (!cmd) {
cmd = &dhd_varcmd;
}
/* do command */
err = (*cmd->func)((void *) ifr, cmd, argv);
break;
} /* while loop end */
/* provide for help on a particular command */
if (help && *argv) {
cmd = dhd_find_cmd(*argv);
if (cmd) {
dhd_cmd_usage(cmd);
} else {
DPRINT_ERR(ERR, "%s: Unrecognized command \"%s\", type -h for help\n",
av0, *argv);
}
} else if (!cmd)
dhd_usage(NULL);
else if (err == USAGE_ERROR)
dhd_cmd_usage(cmd);
else if (err == IOCTL_ERROR)
dhd_printlasterror((void *) ifr);
return err;
}
int
rwl_shell_createproc(void *wl)
{
UNUSED_PARAMETER(wl);
return fork();
}
void
rwl_shell_killproc(int pid)
{
kill(pid, SIGKILL);
}
#ifdef RWL_SOCKET
/* to validate hostname/ip given by the client */
int validate_server_address()
{
struct hostent *he;
struct ipv4_addr temp;
if (!dhd_atoip(g_rwl_servIP, &temp)) {
/* Wrong IP address format check for hostname */
if ((he = gethostbyname(g_rwl_servIP)) != NULL) {
if (!dhd_atoip(*he->h_addr_list, &temp)) {
g_rwl_servIP =
inet_ntoa(*(struct in_addr *)*he->h_addr_list);
if (g_rwl_servIP == NULL) {
DPRINT_ERR(ERR, "Error at inet_ntoa \n");
return FAIL;
}
} else {
DPRINT_ERR(ERR, "Error in IP address \n");
return FAIL;
}
} else {
DPRINT_ERR(ERR, "Enter correct IP address/hostname format\n");
return FAIL;
}
}
return SUCCESS;
}
#endif /* RWL_SOCKET */

251
external/cache/sources/wl/dhd/ucode_download.c vendored Normal file
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/*
* Ucode download related utility functions
*
* $Copyright Open Broadcom Corporation$
*
* $Id: ucode_download.c 297277 2011-11-18 14:10:09Z $
*/
#include <unistd.h>
#include <errno.h>
#include <trxhdr.h>
#include <bcmendian.h>
#include <wlu_common.h>
#define DEVPRESENT_DELAY 10000 /* in microsecs */
#define DEVPRESENT_RETRIES 100
extern int wl_validatedev(void *dev_handle);
int
dload_generic_data(void *wl, uint16 dload_type, unsigned char *dload_buf, int len)
{
struct wl_dload_data *dload_ptr = (struct wl_dload_data *)dload_buf;
int err = 0;
int actual_data_offset;
char *buf;
actual_data_offset = OFFSETOF(struct wl_dload_data, data);
dload_ptr->flag = (DLOAD_HANDLER_VER << DLOAD_FLAG_VER_SHIFT);
dload_ptr->flag |= DL_CRC_NOT_INUSE;
dload_ptr->dload_type = dload_type;
dload_ptr->len = htod32(len - actual_data_offset);
dload_ptr->crc = 0;
len = len + 8 - (len%8);
buf = malloc(WLC_IOCTL_MEDLEN);
if (buf) {
bzero(buf, WLC_IOCTL_MEDLEN);
err = wlu_iovar_setbuf(wl, "generic_dload", dload_buf, len, buf,
WLC_IOCTL_MEDLEN);
}
free(buf);
return err;
}
int
dload_ucode_part(void *wl, uint8 ucode_type, uint32 datalen, unsigned char *org_buf)
{
int num_chunks, chunk_len, cumulative_len = 0;
int size2alloc, ucode_chunk_len = 0;
unsigned char *new_buf;
struct wl_ucode_info *ucode_ptr;
int err = 0, ucode_offset, chunk_offset;
ucode_offset = OFFSETOF(wl_dload_data_t, data);
chunk_offset = OFFSETOF(wl_ucode_info_t, data_chunk);
err = wlu_iovar_getint(wl, "ucdload_chunk_len",
&ucode_chunk_len);
if (err) {
printf("err in getting ucode chunk len, exiting\n");
return err;
}
num_chunks = datalen/ucode_chunk_len;
if (datalen % ucode_chunk_len != 0)
num_chunks++;
size2alloc = ucode_offset + chunk_offset + ucode_chunk_len;
/* single chunk buffer */
new_buf = (unsigned char *)malloc(size2alloc);
memset(new_buf, 0, size2alloc);
ucode_ptr = (struct wl_ucode_info *)((uint8 *)new_buf+ucode_offset);
ucode_ptr->ucode_type = ucode_type;
ucode_ptr->num_chunks = num_chunks;
do {
if (datalen >= ucode_chunk_len)
chunk_len = ucode_chunk_len;
else
chunk_len = datalen;
memset(new_buf+ucode_offset+chunk_offset, 0, size2alloc-ucode_offset-chunk_offset);
ucode_ptr->chunk_len = htod32(chunk_len);
ucode_ptr->chunk_num++;
memcpy(&ucode_ptr->data_chunk[0], org_buf + cumulative_len, chunk_len);
cumulative_len += chunk_len;
err = dload_generic_data(wl, DL_TYPE_UCODE, new_buf, size2alloc);
if (err) {
printf("error while writing %s to the memory\n",
(ucode_type == UCODE_FW)? "ucode" : "initvals");
break;
}
datalen = datalen - chunk_len;
} while (datalen > 0);
free(new_buf);
return err;
}
static int
check_ucode_file(unsigned char *headers)
{
struct trx_header *trx;
int actual_data_len = -1;
/* Extract trx header */
trx = (struct trx_header *)headers;
if (trx->magic != TRX_MAGIC) {
printf("Error: trx bad hdr\n");
goto err;
}
actual_data_len = ROUNDUP(trx->offsets[0], 4) + ROUNDUP(trx->offsets[1], 4);
err:
return actual_data_len;
}
int
proc_ucode_download(char* fw_filename, void *dev_handle)
{
FILE *fp = NULL;
int ret = 0, loopcnt = 0;
struct trx_header main_trx_hdr, *ucode_trx_hdr;
uint32 maintrx_hdr_len, tmp_len;
uint32 fw_size, second_offset, ucode_trx_offset;
long ucode_pos;
unsigned long ucode_info_len = 0, status;
unsigned char *ucodetrx_buf, *initvals_ptr;
int ucode_len, initvals_len;
int ucdload_status = 0;
int is_devpresent;
/* read the file and push blocks down to memory */
if ((fp = fopen(fw_filename, "rb")) == NULL) {
fprintf(stderr, "%s: unable to open %s: %s\n",
__FUNCTION__, fw_filename, strerror(errno));
ret = -1;
goto exit;
}
maintrx_hdr_len = sizeof(struct trx_header);
tmp_len = fread(&main_trx_hdr, sizeof(uint8), maintrx_hdr_len, fp);
if (tmp_len == maintrx_hdr_len) {
if (main_trx_hdr.magic == TRX_MAGIC) {
fw_size = main_trx_hdr.offsets[0];
second_offset = main_trx_hdr.offsets[2];
if (second_offset == maintrx_hdr_len) {
second_offset = 0;
}
ucode_trx_offset = maintrx_hdr_len +
ROUNDUP(fw_size, 4) + ROUNDUP(second_offset, 4);
ucode_pos = fseek(fp, ucode_trx_offset, SEEK_SET);
BCM_REFERENCE(ucode_pos);
if ((ucode_trx_hdr = malloc(sizeof(struct trx_header)))
== NULL) {
printf("Unable to allocate %d bytes!\n", maintrx_hdr_len);
ret = -ENOMEM;
goto exit;
}
/* Read ONLY the firmware-file-header into the new_buffer */
status = fread(ucode_trx_hdr, sizeof(uint8),
maintrx_hdr_len, fp);
if (status < sizeof(struct trx_header)) {
printf("Short read in hdr read for %s!\n", fw_filename);
ret = -EINVAL;
goto exit;
}
if ((ucode_info_len = check_ucode_file(
(unsigned char *)ucode_trx_hdr)) <= 0) {
printf("not a valid ucode.trx\n");
ret = -1;
goto exit;
}
ucodetrx_buf = (unsigned char *)malloc(ucode_info_len *
sizeof(char));
tmp_len = fread(ucodetrx_buf, sizeof(uint8),
ucode_info_len, fp);
if (ucode_info_len > 0) {
ucode_len = ucode_trx_hdr->offsets[0];
initvals_ptr = ucodetrx_buf +
ROUNDUP(ucode_trx_hdr->offsets[0], 4);
initvals_len = ucode_trx_hdr->offsets[1];
}
free(ucode_trx_hdr);
init_cmd_batchingmode();
do {
is_devpresent = wl_validatedev(dev_handle);
loopcnt++;
/* in USB after dongle fw starts running wl interface
might not appear in the list of interfaces immediately, hence try
after some delay of 10ms
*/
if (!is_devpresent)
usleep(DEVPRESENT_DELAY);
else {
/* below iovar to verify if the for foundout
interface has already ucode been downloaded
*/
ret = wlu_iovar_getint(dev_handle, "ucdload_status",
&ucdload_status);
if (ret) {
printf("err in ucdload_status, exiting\n");
goto exit;
}
if (ucdload_status) {
/* Number of 'wl' interfaces to skip
in the next round of going thru wl_find
*/
printf("ucode is already downloaded\n");
}
}
/* usb seems to take some time to come up, hence the
loop value of 100
*/
} while (loopcnt < DEVPRESENT_RETRIES && !is_devpresent);
if (loopcnt < DEVPRESENT_RETRIES) {
/* download the ucode fw */
ret = dload_ucode_part(dev_handle, UCODE_FW, ucode_len,
ucodetrx_buf);
if (ret) {
printf("error while downloading ucode, exiting\n");
goto exit;
}
/* download the initvals to the dongle */
ret = dload_ucode_part(dev_handle, INIT_VALS,
initvals_len, initvals_ptr);
if (ret) {
printf("error while downloading initvals, exiting\n");
goto exit;
}
}
else {
printf("wl device is not present\n");
}
free(ucodetrx_buf);
}
}
exit:
if (fp)
fclose(fp);
return ret;
}

9
external/cache/sources/wl/dhd/ucode_download.h vendored Normal file
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/*
* Ucode download related utility functions
*
* $Copyright Open Broadcom Corporation$
*
* $Id: ucode_download.h 241182 2011-02-17 21:50:03Z $
*/
extern int
proc_ucode_download(char* fw_filename, void *dev_handle);

53
external/cache/sources/wl/include/Makefile vendored Normal file
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#!/bin/bash
#
# This script serves following purpose:
#
# 1. It generates native version information by querying
# automerger maintained database to see where src/include
# came from
# 2. For select components, as listed in compvers.sh
# it generates component version files
#
# Copyright 2005, Broadcom, Inc.
#
# $Id: Makefile 241686 2011-02-19 00:22:45Z $
#
SRCBASE := ..
TARGETS := epivers.h
ifdef VERBOSE
export VERBOSE
endif
all release: epivers compvers
# Generate epivers.h for native branch version
epivers:
bash epivers.sh
# Generate epivers.h for native branch version
compvers:
@if [ -s "compvers.sh" ]; then \
echo "Generating component versions, if any"; \
bash compvers.sh; \
else \
echo "Skipping component version generation"; \
fi
# Generate epivers.h for native branch version
clean_compvers:
@if [ -s "compvers.sh" ]; then \
echo "bash compvers.sh clean"; \
bash compvers.sh clean; \
else \
echo "Skipping component version clean"; \
fi
clean:
rm -f $(TARGETS) *.prev
clean_all: clean clean_compvers
.PHONY: all release clean epivers compvers clean_compvers

368
external/cache/sources/wl/include/aidmp.h vendored Normal file
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/*
* Broadcom AMBA Interconnect definitions.
*
* $Copyright Open Broadcom Corporation$
*
* $Id: aidmp.h 382794 2013-02-04 17:34:08Z $
*/
#ifndef _AIDMP_H
#define _AIDMP_H
#define MFGID_ARM 0x43b
#define MFGID_BRCM 0x4bf
#define MFGID_MIPS 0x4a7
#define CC_SIM 0
#define CC_EROM 1
#define CC_CORESIGHT 9
#define CC_VERIF 0xb
#define CC_OPTIMO 0xd
#define CC_GEN 0xe
#define CC_PRIMECELL 0xf
#define ER_EROMENTRY 0x000
#define ER_REMAPCONTROL 0xe00
#define ER_REMAPSELECT 0xe04
#define ER_MASTERSELECT 0xe10
#define ER_ITCR 0xf00
#define ER_ITIP 0xf04
#define ER_TAG 0xe
#define ER_TAG1 0x6
#define ER_VALID 1
#define ER_CI 0
#define ER_MP 2
#define ER_ADD 4
#define ER_END 0xe
#define ER_BAD 0xffffffff
#define CIA_MFG_MASK 0xfff00000
#define CIA_MFG_SHIFT 20
#define CIA_CID_MASK 0x000fff00
#define CIA_CID_SHIFT 8
#define CIA_CCL_MASK 0x000000f0
#define CIA_CCL_SHIFT 4
#define CIB_REV_MASK 0xff000000
#define CIB_REV_SHIFT 24
#define CIB_NSW_MASK 0x00f80000
#define CIB_NSW_SHIFT 19
#define CIB_NMW_MASK 0x0007c000
#define CIB_NMW_SHIFT 14
#define CIB_NSP_MASK 0x00003e00
#define CIB_NSP_SHIFT 9
#define CIB_NMP_MASK 0x000001f0
#define CIB_NMP_SHIFT 4
#define MPD_MUI_MASK 0x0000ff00
#define MPD_MUI_SHIFT 8
#define MPD_MP_MASK 0x000000f0
#define MPD_MP_SHIFT 4
#define AD_ADDR_MASK 0xfffff000
#define AD_SP_MASK 0x00000f00
#define AD_SP_SHIFT 8
#define AD_ST_MASK 0x000000c0
#define AD_ST_SHIFT 6
#define AD_ST_SLAVE 0x00000000
#define AD_ST_BRIDGE 0x00000040
#define AD_ST_SWRAP 0x00000080
#define AD_ST_MWRAP 0x000000c0
#define AD_SZ_MASK 0x00000030
#define AD_SZ_SHIFT 4
#define AD_SZ_4K 0x00000000
#define AD_SZ_8K 0x00000010
#define AD_SZ_16K 0x00000020
#define AD_SZ_SZD 0x00000030
#define AD_AG32 0x00000008
#define AD_ADDR_ALIGN 0x00000fff
#define AD_SZ_BASE 0x00001000
#define SD_SZ_MASK 0xfffff000
#define SD_SG32 0x00000008
#define SD_SZ_ALIGN 0x00000fff
#ifndef _LANGUAGE_ASSEMBLY
typedef volatile struct _aidmp {
uint32 oobselina30;
uint32 oobselina74;
uint32 PAD[6];
uint32 oobselinb30;
uint32 oobselinb74;
uint32 PAD[6];
uint32 oobselinc30;
uint32 oobselinc74;
uint32 PAD[6];
uint32 oobselind30;
uint32 oobselind74;
uint32 PAD[38];
uint32 oobselouta30;
uint32 oobselouta74;
uint32 PAD[6];
uint32 oobseloutb30;
uint32 oobseloutb74;
uint32 PAD[6];
uint32 oobseloutc30;
uint32 oobseloutc74;
uint32 PAD[6];
uint32 oobseloutd30;
uint32 oobseloutd74;
uint32 PAD[38];
uint32 oobsynca;
uint32 oobseloutaen;
uint32 PAD[6];
uint32 oobsyncb;
uint32 oobseloutben;
uint32 PAD[6];
uint32 oobsyncc;
uint32 oobseloutcen;
uint32 PAD[6];
uint32 oobsyncd;
uint32 oobseloutden;
uint32 PAD[38];
uint32 oobaextwidth;
uint32 oobainwidth;
uint32 oobaoutwidth;
uint32 PAD[5];
uint32 oobbextwidth;
uint32 oobbinwidth;
uint32 oobboutwidth;
uint32 PAD[5];
uint32 oobcextwidth;
uint32 oobcinwidth;
uint32 oobcoutwidth;
uint32 PAD[5];
uint32 oobdextwidth;
uint32 oobdinwidth;
uint32 oobdoutwidth;
uint32 PAD[37];
uint32 ioctrlset;
uint32 ioctrlclear;
uint32 ioctrl;
uint32 PAD[61];
uint32 iostatus;
uint32 PAD[127];
uint32 ioctrlwidth;
uint32 iostatuswidth;
uint32 PAD[62];
uint32 resetctrl;
uint32 resetstatus;
uint32 resetreadid;
uint32 resetwriteid;
uint32 PAD[60];
uint32 errlogctrl;
uint32 errlogdone;
uint32 errlogstatus;
uint32 errlogaddrlo;
uint32 errlogaddrhi;
uint32 errlogid;
uint32 errloguser;
uint32 errlogflags;
uint32 PAD[56];
uint32 intstatus;
uint32 PAD[255];
uint32 config;
uint32 PAD[63];
uint32 itcr;
uint32 PAD[3];
uint32 itipooba;
uint32 itipoobb;
uint32 itipoobc;
uint32 itipoobd;
uint32 PAD[4];
uint32 itipoobaout;
uint32 itipoobbout;
uint32 itipoobcout;
uint32 itipoobdout;
uint32 PAD[4];
uint32 itopooba;
uint32 itopoobb;
uint32 itopoobc;
uint32 itopoobd;
uint32 PAD[4];
uint32 itopoobain;
uint32 itopoobbin;
uint32 itopoobcin;
uint32 itopoobdin;
uint32 PAD[4];
uint32 itopreset;
uint32 PAD[15];
uint32 peripherialid4;
uint32 peripherialid5;
uint32 peripherialid6;
uint32 peripherialid7;
uint32 peripherialid0;
uint32 peripherialid1;
uint32 peripherialid2;
uint32 peripherialid3;
uint32 componentid0;
uint32 componentid1;
uint32 componentid2;
uint32 componentid3;
} aidmp_t;
#endif
#define OOB_BUSCONFIG 0x020
#define OOB_STATUSA 0x100
#define OOB_STATUSB 0x104
#define OOB_STATUSC 0x108
#define OOB_STATUSD 0x10c
#define OOB_ENABLEA0 0x200
#define OOB_ENABLEA1 0x204
#define OOB_ENABLEA2 0x208
#define OOB_ENABLEA3 0x20c
#define OOB_ENABLEB0 0x280
#define OOB_ENABLEB1 0x284
#define OOB_ENABLEB2 0x288
#define OOB_ENABLEB3 0x28c
#define OOB_ENABLEC0 0x300
#define OOB_ENABLEC1 0x304
#define OOB_ENABLEC2 0x308
#define OOB_ENABLEC3 0x30c
#define OOB_ENABLED0 0x380
#define OOB_ENABLED1 0x384
#define OOB_ENABLED2 0x388
#define OOB_ENABLED3 0x38c
#define OOB_ITCR 0xf00
#define OOB_ITIPOOBA 0xf10
#define OOB_ITIPOOBB 0xf14
#define OOB_ITIPOOBC 0xf18
#define OOB_ITIPOOBD 0xf1c
#define OOB_ITOPOOBA 0xf30
#define OOB_ITOPOOBB 0xf34
#define OOB_ITOPOOBC 0xf38
#define OOB_ITOPOOBD 0xf3c
#define AI_OOBSELINA30 0x000
#define AI_OOBSELINA74 0x004
#define AI_OOBSELINB30 0x020
#define AI_OOBSELINB74 0x024
#define AI_OOBSELINC30 0x040
#define AI_OOBSELINC74 0x044
#define AI_OOBSELIND30 0x060
#define AI_OOBSELIND74 0x064
#define AI_OOBSELOUTA30 0x100
#define AI_OOBSELOUTA74 0x104
#define AI_OOBSELOUTB30 0x120
#define AI_OOBSELOUTB74 0x124
#define AI_OOBSELOUTC30 0x140
#define AI_OOBSELOUTC74 0x144
#define AI_OOBSELOUTD30 0x160
#define AI_OOBSELOUTD74 0x164
#define AI_OOBSYNCA 0x200
#define AI_OOBSELOUTAEN 0x204
#define AI_OOBSYNCB 0x220
#define AI_OOBSELOUTBEN 0x224
#define AI_OOBSYNCC 0x240
#define AI_OOBSELOUTCEN 0x244
#define AI_OOBSYNCD 0x260
#define AI_OOBSELOUTDEN 0x264
#define AI_OOBAEXTWIDTH 0x300
#define AI_OOBAINWIDTH 0x304
#define AI_OOBAOUTWIDTH 0x308
#define AI_OOBBEXTWIDTH 0x320
#define AI_OOBBINWIDTH 0x324
#define AI_OOBBOUTWIDTH 0x328
#define AI_OOBCEXTWIDTH 0x340
#define AI_OOBCINWIDTH 0x344
#define AI_OOBCOUTWIDTH 0x348
#define AI_OOBDEXTWIDTH 0x360
#define AI_OOBDINWIDTH 0x364
#define AI_OOBDOUTWIDTH 0x368
#define AI_IOCTRLSET 0x400
#define AI_IOCTRLCLEAR 0x404
#define AI_IOCTRL 0x408
#define AI_IOSTATUS 0x500
#define AI_RESETCTRL 0x800
#define AI_RESETSTATUS 0x804
#define AI_IOCTRLWIDTH 0x700
#define AI_IOSTATUSWIDTH 0x704
#define AI_RESETREADID 0x808
#define AI_RESETWRITEID 0x80c
#define AI_ERRLOGCTRL 0xa00
#define AI_ERRLOGDONE 0xa04
#define AI_ERRLOGSTATUS 0xa08
#define AI_ERRLOGADDRLO 0xa0c
#define AI_ERRLOGADDRHI 0xa10
#define AI_ERRLOGID 0xa14
#define AI_ERRLOGUSER 0xa18
#define AI_ERRLOGFLAGS 0xa1c
#define AI_INTSTATUS 0xa00
#define AI_CONFIG 0xe00
#define AI_ITCR 0xf00
#define AI_ITIPOOBA 0xf10
#define AI_ITIPOOBB 0xf14
#define AI_ITIPOOBC 0xf18
#define AI_ITIPOOBD 0xf1c
#define AI_ITIPOOBAOUT 0xf30
#define AI_ITIPOOBBOUT 0xf34
#define AI_ITIPOOBCOUT 0xf38
#define AI_ITIPOOBDOUT 0xf3c
#define AI_ITOPOOBA 0xf50
#define AI_ITOPOOBB 0xf54
#define AI_ITOPOOBC 0xf58
#define AI_ITOPOOBD 0xf5c
#define AI_ITOPOOBAIN 0xf70
#define AI_ITOPOOBBIN 0xf74
#define AI_ITOPOOBCIN 0xf78
#define AI_ITOPOOBDIN 0xf7c
#define AI_ITOPRESET 0xf90
#define AI_PERIPHERIALID4 0xfd0
#define AI_PERIPHERIALID5 0xfd4
#define AI_PERIPHERIALID6 0xfd8
#define AI_PERIPHERIALID7 0xfdc
#define AI_PERIPHERIALID0 0xfe0
#define AI_PERIPHERIALID1 0xfe4
#define AI_PERIPHERIALID2 0xfe8
#define AI_PERIPHERIALID3 0xfec
#define AI_COMPONENTID0 0xff0
#define AI_COMPONENTID1 0xff4
#define AI_COMPONENTID2 0xff8
#define AI_COMPONENTID3 0xffc
#define AIRC_RESET 1
#define AICFG_OOB 0x00000020
#define AICFG_IOS 0x00000010
#define AICFG_IOC 0x00000008
#define AICFG_TO 0x00000004
#define AICFG_ERRL 0x00000002
#define AICFG_RST 0x00000001
#define OOB_SEL_OUTEN_B_5 15
#define OOB_SEL_OUTEN_B_6 23
#define AI_OOBSEL_MASK 0x1F
#define AI_OOBSEL_0_SHIFT 0
#define AI_OOBSEL_1_SHIFT 8
#define AI_OOBSEL_2_SHIFT 16
#define AI_OOBSEL_3_SHIFT 24
#define AI_OOBSEL_4_SHIFT 0
#define AI_OOBSEL_5_SHIFT 8
#define AI_OOBSEL_6_SHIFT 16
#define AI_OOBSEL_7_SHIFT 24
#endif

44
external/cache/sources/wl/include/bcm_android_types.h vendored Normal file
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/*
* Android related remote wl declarations
*
* Copyright (C) 2013, Broadcom Corporation
* All Rights Reserved.
*
* This is UNPUBLISHED PROPRIETARY SOURCE CODE of Broadcom Corporation;
* the contents of this file may not be disclosed to third parties, copied
* or duplicated in any form, in whole or in part, without the prior
* written permission of Broadcom Corporation.
* $Id: bcm_android_types.h 241182 2011-02-17 21:50:03Z $
*
*/
#ifndef _wlu_android_h
#define _wlu_android_h
#define __fd_mask unsigned long
typedef struct
{
#ifdef __USE_XOPEN
__fd_mask fds_bits[__FD_SETSIZE / __NFDBITS];
# define __FDS_BITS(set) ((set)->fds_bits)
#else
__fd_mask __fds_bits[__FD_SETSIZE / __NFDBITS];
# define __FDS_BITS(set) ((set)->__fds_bits)
#endif
} fd_set1;
#define fd_set fd_set1
#define htons(x) BCMSWAP16(x)
#define htonl(x) BCMSWAP32(x)
#define __FD_ZERO(s) \
do { \
unsigned int __i; \
fd_set *__arr = (s); \
for (__i = 0; __i < sizeof (fd_set) / sizeof (__fd_mask); ++__i) \
__FDS_BITS(__arr)[__i] = 0; \
} while (0)
#define __FD_SET(d, s) (__FDS_BITS (s)[__FDELT(d)] |= __FDMASK(d))
#define __FD_CLR(d, s) (__FDS_BITS (s)[__FDELT(d)] &= ~__FDMASK(d))
#define __FD_ISSET(d, s) ((__FDS_BITS (s)[__FDELT(d)] & __FDMASK(d)) != 0)
#define MCL_CURRENT 1
#define MCL_FUTURE 2
#endif

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/*
* BCM common config options
*
* $Copyright Open Broadcom Corporation$
*
* $Id: bcm_cfg.h 294399 2011-11-07 03:31:22Z hharte $
*/
#ifndef _bcm_cfg_h_
#define _bcm_cfg_h_
#if defined(__NetBSD__) || defined(__FreeBSD__)
#if defined(_KERNEL)
#include <opt_bcm.h>
#endif /* defined(_KERNEL) */
#endif /* defined(__NetBSD__) || defined(__FreeBSD__) */
#endif /* _bcm_cfg_h_ */

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/*
* Memory pools library, Public interface
*
* API Overview
*
* This package provides a memory allocation subsystem based on pools of
* homogenous objects.
*
* Instrumentation is available for reporting memory utilization both
* on a per-data-structure basis and system wide.
*
* There are two main types defined in this API.
*
* pool manager: A singleton object that acts as a factory for
* pool allocators. It also is used for global
* instrumentation, such as reporting all blocks
* in use across all data structures. The pool manager
* creates and provides individual memory pools
* upon request to application code.
*
* memory pool: An object for allocating homogenous memory blocks.
*
* Global identifiers in this module use the following prefixes:
* bcm_mpm_* Memory pool manager
* bcm_mp_* Memory pool
*
* There are two main types of memory pools:
*
* prealloc: The contiguous memory block of objects can either be supplied
* by the client or malloc'ed by the memory manager. The objects are
* allocated out of a block of memory and freed back to the block.
*
* heap: The memory pool allocator uses the heap (malloc/free) for memory.
* In this case, the pool allocator is just providing statistics
* and instrumentation on top of the heap, without modifying the heap
* allocation implementation.
*
* $Copyright Open Broadcom Corporation$
*
* $Id$
*/
#ifndef _BCM_MPOOL_PUB_H
#define _BCM_MPOOL_PUB_H 1
#include <typedefs.h> /* needed for uint16 */
/*
**************************************************************************
*
* Type definitions, handles
*
**************************************************************************
*/
/* Forward declaration of OSL handle. */
struct osl_info;
/* Forward declaration of string buffer. */
struct bcmstrbuf;
/*
* Opaque type definition for the pool manager handle. This object is used for global
* memory pool operations such as obtaining a new pool, deleting a pool, iterating and
* instrumentation/debugging.
*/
struct bcm_mpm_mgr;
typedef struct bcm_mpm_mgr *bcm_mpm_mgr_h;
/*
* Opaque type definition for an instance of a pool. This handle is used for allocating
* and freeing memory through the pool, as well as management/instrumentation on this
* specific pool.
*/
struct bcm_mp_pool;
typedef struct bcm_mp_pool *bcm_mp_pool_h;
/*
* To make instrumentation more readable, every memory
* pool must have a readable name. Pool names are up to
* 8 bytes including '\0' termination. (7 printable characters.)
*/
#define BCM_MP_NAMELEN 8
/*
* Type definition for pool statistics.
*/
typedef struct bcm_mp_stats {
char name[BCM_MP_NAMELEN]; /* Name of this pool. */
unsigned int objsz; /* Object size allocated in this pool */
uint16 nobj; /* Total number of objects in this pool */
uint16 num_alloc; /* Number of objects currently allocated */
uint16 high_water; /* Max number of allocated objects. */
uint16 failed_alloc; /* Failed allocations. */
} bcm_mp_stats_t;
/*
**************************************************************************
*
* API Routines on the pool manager.
*
**************************************************************************
*/
/*
* bcm_mpm_init() - initialize the whole memory pool system.
*
* Parameters:
* osh: INPUT Operating system handle. Needed for heap memory allocation.
* max_pools: INPUT Maximum number of mempools supported.
* mgr: OUTPUT The handle is written with the new pools manager object/handle.
*
* Returns:
* BCME_OK Object initialized successfully. May be used.
* BCME_NOMEM Initialization failed due to no memory. Object must not be used.
*/
int bcm_mpm_init(struct osl_info *osh, int max_pools, bcm_mpm_mgr_h *mgrp);
/*
* bcm_mpm_deinit() - de-initialize the whole memory pool system.
*
* Parameters:
* mgr: INPUT Pointer to pool manager handle.
*
* Returns:
* BCME_OK Memory pool manager successfully de-initialized.
* other Indicated error occured during de-initialization.
*/
int bcm_mpm_deinit(bcm_mpm_mgr_h *mgrp);
/*
* bcm_mpm_create_prealloc_pool() - Create a new pool for fixed size objects. The
* pool uses a contiguous block of pre-alloced
* memory. The memory block may either be provided
* by the client or dynamically allocated by the
* pool manager.
*
* Parameters:
* mgr: INPUT The handle to the pool manager
* obj_sz: INPUT Size of objects that will be allocated by the new pool
* Must be >= sizeof(void *).
* nobj: INPUT Maximum number of concurrently existing objects to support
* memstart INPUT Pointer to the memory to use, or NULL to malloc()
* memsize INPUT Number of bytes referenced from memstart (for error checking).
* Must be 0 if 'memstart' is NULL.
* poolname INPUT For instrumentation, the name of the pool
* newp: OUTPUT The handle for the new pool, if creation is successful
*
* Returns:
* BCME_OK Pool created ok.
* other Pool not created due to indicated error. newpoolp set to NULL.
*
*
*/
int bcm_mpm_create_prealloc_pool(bcm_mpm_mgr_h mgr,
unsigned int obj_sz,
int nobj,
void *memstart,
unsigned int memsize,
const char poolname[BCM_MP_NAMELEN],
bcm_mp_pool_h *newp);
/*
* bcm_mpm_delete_prealloc_pool() - Delete a memory pool. This should only be called after
* all memory objects have been freed back to the pool.
*
* Parameters:
* mgr: INPUT The handle to the pools manager
* pool: INPUT The handle of the pool to delete
*
* Returns:
* BCME_OK Pool deleted ok.
* other Pool not deleted due to indicated error.
*
*/
int bcm_mpm_delete_prealloc_pool(bcm_mpm_mgr_h mgr, bcm_mp_pool_h *poolp);
/*
* bcm_mpm_create_heap_pool() - Create a new pool for fixed size objects. The memory
* pool allocator uses the heap (malloc/free) for memory.
* In this case, the pool allocator is just providing
* statistics and instrumentation on top of the heap,
* without modifying the heap allocation implementation.
*
* Parameters:
* mgr: INPUT The handle to the pool manager
* obj_sz: INPUT Size of objects that will be allocated by the new pool
* poolname INPUT For instrumentation, the name of the pool
* newp: OUTPUT The handle for the new pool, if creation is successful
*
* Returns:
* BCME_OK Pool created ok.
* other Pool not created due to indicated error. newpoolp set to NULL.
*
*
*/
int bcm_mpm_create_heap_pool(bcm_mpm_mgr_h mgr, unsigned int obj_sz,
const char poolname[BCM_MP_NAMELEN],
bcm_mp_pool_h *newp);
/*
* bcm_mpm_delete_heap_pool() - Delete a memory pool. This should only be called after
* all memory objects have been freed back to the pool.
*
* Parameters:
* mgr: INPUT The handle to the pools manager
* pool: INPUT The handle of the pool to delete
*
* Returns:
* BCME_OK Pool deleted ok.
* other Pool not deleted due to indicated error.
*
*/
int bcm_mpm_delete_heap_pool(bcm_mpm_mgr_h mgr, bcm_mp_pool_h *poolp);
/*
* bcm_mpm_stats() - Return stats for all pools
*
* Parameters:
* mgr: INPUT The handle to the pools manager
* stats: OUTPUT Array of pool statistics.
* nentries: MOD Max elements in 'stats' array on INPUT. Actual number
* of array elements copied to 'stats' on OUTPUT.
*
* Returns:
* BCME_OK Ok
* other Error getting stats.
*
*/
int bcm_mpm_stats(bcm_mpm_mgr_h mgr, bcm_mp_stats_t *stats, int *nentries);
/*
* bcm_mpm_dump() - Display statistics on all pools
*
* Parameters:
* mgr: INPUT The handle to the pools manager
* b: OUTPUT Output buffer.
*
* Returns:
* BCME_OK Ok
* other Error during dump.
*
*/
int bcm_mpm_dump(bcm_mpm_mgr_h mgr, struct bcmstrbuf *b);
/*
* bcm_mpm_get_obj_size() - The size of memory objects may need to be padded to
* compensate for alignment requirements of the objects.
* This function provides the padded object size. If clients
* pre-allocate a memory slab for a memory pool, the
* padded object size should be used by the client to allocate
* the memory slab (in order to provide sufficent space for
* the maximum number of objects).
*
* Parameters:
* mgr: INPUT The handle to the pools manager.
* obj_sz: INPUT Input object size.
* padded_obj_sz: OUTPUT Padded object size.
*
* Returns:
* BCME_OK Ok
* BCME_BADARG Bad arguments.
*
*/
int bcm_mpm_get_obj_size(bcm_mpm_mgr_h mgr, unsigned int obj_sz, unsigned int *padded_obj_sz);
/*
***************************************************************************
*
* API Routines on a specific pool.
*
***************************************************************************
*/
/*
* bcm_mp_alloc() - Allocate a memory pool object.
*
* Parameters:
* pool: INPUT The handle to the pool.
*
* Returns:
* A pointer to the new object. NULL on error.
*
*/
void* bcm_mp_alloc(bcm_mp_pool_h pool);
/*
* bcm_mp_free() - Free a memory pool object.
*
* Parameters:
* pool: INPUT The handle to the pool.
* objp: INPUT A pointer to the object to free.
*
* Returns:
* BCME_OK Ok
* other Error during free.
*
*/
int bcm_mp_free(bcm_mp_pool_h pool, void *objp);
/*
* bcm_mp_stats() - Return stats for this pool
*
* Parameters:
* pool: INPUT The handle to the pool
* stats: OUTPUT Pool statistics
*
* Returns:
* BCME_OK Ok
* other Error getting statistics.
*
*/
int bcm_mp_stats(bcm_mp_pool_h pool, bcm_mp_stats_t *stats);
/*
* bcm_mp_dump() - Dump a pool
*
* Parameters:
* pool: INPUT The handle to the pool
* b OUTPUT Output buffer
*
* Returns:
* BCME_OK Ok
* other Error during dump.
*
*/
int bcm_mp_dump(bcm_mp_pool_h pool, struct bcmstrbuf *b);
#endif /* _BCM_MPOOL_PUB_H */

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/*
* CDC network driver ioctl/indication encoding
* Broadcom 802.11abg Networking Device Driver
*
* Definitions subject to change without notice.
*
* $Copyright Open Broadcom Corporation$
*
* $Id: bcmcdc.h 291086 2011-10-21 01:17:24Z linm $
*/
#ifndef _bcmcdc_h_
#define _bcmcdc_h_
#include <proto/ethernet.h>
typedef struct cdc_ioctl {
uint32 cmd; /* ioctl command value */
uint32 len; /* lower 16: output buflen; upper 16: input buflen (excludes header) */
uint32 flags; /* flag defns given below */
uint32 status; /* status code returned from the device */
} cdc_ioctl_t;
/* Max valid buffer size that can be sent to the dongle */
#define CDC_MAX_MSG_SIZE ETHER_MAX_LEN
/* len field is divided into input and output buffer lengths */
#define CDCL_IOC_OUTLEN_MASK 0x0000FFFF /* maximum or expected response length, */
/* excluding IOCTL header */
#define CDCL_IOC_OUTLEN_SHIFT 0
#define CDCL_IOC_INLEN_MASK 0xFFFF0000 /* input buffer length, excluding IOCTL header */
#define CDCL_IOC_INLEN_SHIFT 16
/* CDC flag definitions */
#define CDCF_IOC_ERROR 0x01 /* 0=success, 1=ioctl cmd failed */
#define CDCF_IOC_SET 0x02 /* 0=get, 1=set cmd */
#define CDCF_IOC_OVL_IDX_MASK 0x3c /* overlay region index mask */
#define CDCF_IOC_OVL_RSV 0x40 /* 1=reserve this overlay region */
#define CDCF_IOC_OVL 0x80 /* 1=this ioctl corresponds to an overlay */
#define CDCF_IOC_ACTION_MASK 0xfe /* SET/GET, OVL_IDX, OVL_RSV, OVL mask */
#define CDCF_IOC_ACTION_SHIFT 1 /* SET/GET, OVL_IDX, OVL_RSV, OVL shift */
#define CDCF_IOC_IF_MASK 0xF000 /* I/F index */
#define CDCF_IOC_IF_SHIFT 12
#define CDCF_IOC_ID_MASK 0xFFFF0000 /* used to uniquely id an ioctl req/resp pairing */
#define CDCF_IOC_ID_SHIFT 16 /* # of bits of shift for ID Mask */
#define CDC_IOC_IF_IDX(flags) (((flags) & CDCF_IOC_IF_MASK) >> CDCF_IOC_IF_SHIFT)
#define CDC_IOC_ID(flags) (((flags) & CDCF_IOC_ID_MASK) >> CDCF_IOC_ID_SHIFT)
#define CDC_GET_IF_IDX(hdr) \
((int)((((hdr)->flags) & CDCF_IOC_IF_MASK) >> CDCF_IOC_IF_SHIFT))
#define CDC_SET_IF_IDX(hdr, idx) \
((hdr)->flags = (((hdr)->flags & ~CDCF_IOC_IF_MASK) | ((idx) << CDCF_IOC_IF_SHIFT)))
/*
* BDC header
*
* The BDC header is used on data packets to convey priority across USB.
*/
#define BDC_HEADER_LEN 4
#define BDC_PROTO_VER_1 1 /* Old Protocol version */
#define BDC_PROTO_VER 2 /* Protocol version */
#define BDC_FLAG_VER_MASK 0xf0 /* Protocol version mask */
#define BDC_FLAG_VER_SHIFT 4 /* Protocol version shift */
#ifndef EXT_STA
#define BDC_FLAG__UNUSED 0x03 /* Unassigned */
#else
#define BDC_FLAG_EXEMPT 0x03 /* Vista/EXT_STA: use for encryption exemption */
#endif /* EXT_STA */
#define BDC_FLAG_SUM_GOOD 0x04 /* Dongle has verified good RX checksums */
#define BDC_FLAG_SUM_NEEDED 0x08 /* Dongle needs to do TX checksums */
#define BDC_PRIORITY_MASK 0x7
#define BDC_FLAG2_FC_FLAG 0x10 /* flag to indicate if pkt contains */
/* FLOW CONTROL info only */
#define BDC_PRIORITY_FC_SHIFT 4 /* flow control info shift */
#define BDC_FLAG2_IF_MASK 0x0f /* APSTA: interface on which the packet was received */
#define BDC_FLAG2_IF_SHIFT 0
/* XXX PR86912 WAR: host pads out to multiple of 64 bytes; device trims pad bytes */
#define BDC_FLAG2_PAD_MASK 0xf0
#define BDC_FLAG_PAD_MASK 0x03
#define BDC_FLAG2_PAD_SHIFT 2
#define BDC_FLAG_PAD_SHIFT 0
#define BDC_FLAG2_PAD_IDX 0x3c
#define BDC_FLAG_PAD_IDX 0x03
#define BDC_GET_PAD_LEN(hdr) \
((int)(((((hdr)->flags2) & BDC_FLAG2_PAD_MASK) >> BDC_FLAG2_PAD_SHIFT) | \
((((hdr)->flags) & BDC_FLAG_PAD_MASK) >> BDC_FLAG_PAD_SHIFT)))
#define BDC_SET_PAD_LEN(hdr, idx) \
((hdr)->flags2 = (((hdr)->flags2 & ~BDC_FLAG2_PAD_MASK) | \
(((idx) & BDC_FLAG2_PAD_IDX) << BDC_FLAG2_PAD_SHIFT))); \
((hdr)->flags = (((hdr)->flags & ~BDC_FLAG_PAD_MASK) | \
(((idx) & BDC_FLAG_PAD_IDX) << BDC_FLAG_PAD_SHIFT)))
/* XXX END PR86912 WAR */
#define BDC_GET_IF_IDX(hdr) \
((int)((((hdr)->flags2) & BDC_FLAG2_IF_MASK) >> BDC_FLAG2_IF_SHIFT))
#define BDC_SET_IF_IDX(hdr, idx) \
((hdr)->flags2 = (((hdr)->flags2 & ~BDC_FLAG2_IF_MASK) | ((idx) << BDC_FLAG2_IF_SHIFT)))
struct bdc_header {
uint8 flags; /* Flags */
uint8 priority; /* 802.1d Priority 0:2 bits, 4:7 USB flow control info */
uint8 flags2;
uint8 dataOffset; /* Offset from end of BDC header to packet data, in
* 4-byte words. Leaves room for optional headers.
*/
};
/* XXX: Just to keep support for old twigs */
#define BDC_PROTO_VER_1 1 /* Old Protocol version */
#endif /* _bcmcdc_h_ */

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/*
* Misc system wide definitions
*
* $Copyright Open Broadcom Corporation$
*
* $Id: bcmdefs.h 401759 2013-05-13 16:08:08Z sudhirbs $
*/
#ifndef _bcmdefs_h_
#define _bcmdefs_h_
/*
* One doesn't need to include this file explicitly, gets included automatically if
* typedefs.h is included.
*/
/* Use BCM_REFERENCE to suppress warnings about intentionally-unused function
* arguments or local variables.
*/
#define BCM_REFERENCE(data) ((void)(data))
#ifdef EFI
#define STATIC_ASSERT(expr) ASSERT((expr))
#else
/* Compile-time assert can be used in place of ASSERT if the expression evaluates
* to a constant at compile time.
*/
#define STATIC_ASSERT(expr) { \
/* Make sure the expression is constant. */ \
typedef enum { _STATIC_ASSERT_NOT_CONSTANT = (expr) } _static_assert_e; \
/* Make sure the expression is true. */ \
typedef char STATIC_ASSERT_FAIL[(expr) ? 1 : -1]; \
}
#endif
/* Reclaiming text and data :
* The following macros specify special linker sections that can be reclaimed
* after a system is considered 'up'.
* BCMATTACHFN is also used for detach functions (it's not worth having a BCMDETACHFN,
* as in most cases, the attach function calls the detach function to clean up on error).
*/
#ifdef DONGLEBUILD
extern bool bcmreclaimed;
extern bool attach_part_reclaimed;
#define BCMATTACHDATA(_data) __attribute__ ((__section__ (".dataini2." #_data))) _data
#define BCMATTACHFN(_fn) __attribute__ ((__section__ (".textini2." #_fn), noinline)) _fn
#ifndef PREATTACH_NORECLAIM
#define BCMPREATTACHDATA(_data) __attribute__ ((__section__ (".dataini3." #_data))) _data
#define BCMPREATTACHFN(_fn) __attribute__ ((__section__ (".textini3." #_fn), noinline)) _fn
#else
#define BCMPREATTACHDATA(_data) __attribute__ ((__section__ (".dataini2." #_data))) _data
#define BCMPREATTACHFN(_fn) __attribute__ ((__section__ (".textini2." #_fn), noinline)) _fn
#endif
#if defined(BCMRECLAIM)
#define BCMINITDATA(_data) __attribute__ ((__section__ (".dataini1." #_data))) _data
#define BCMINITFN(_fn) __attribute__ ((__section__ (".textini1." #_fn), noinline)) _fn
#define CONST
#else
#define BCMINITDATA(_data) _data
#define BCMINITFN(_fn) _fn
#define CONST const
#endif
/* Non-manufacture or internal attach function/dat */
#if !(defined(WLTEST) || defined(BCMINTERNAL))
#define BCMNMIATTACHFN(_fn) BCMATTACHFN(_fn)
#define BCMNMIATTACHDATA(_data) BCMATTACHDATA(_data)
#else
#define BCMNMIATTACHFN(_fn) _fn
#define BCMNMIATTACHDATA(_data) _data
#endif /* WLTEST || BCMINTERNAL */
#ifdef BCMNODOWN
#define BCMUNINITFN(_fn) BCMINITFN(_fn)
#else
#define BCMUNINITFN(_fn) _fn
#endif
#define BCMFASTPATH
#else /* DONGLEBUILD */
#define bcmreclaimed 0
#define BCMATTACHDATA(_data) _data
#define BCMATTACHFN(_fn) _fn
#define BCMPREATTACHDATA(_data) _data
#define BCMPREATTACHFN(_fn) _fn
#define BCMINITDATA(_data) _data
#define BCMINITFN(_fn) _fn
#define BCMUNINITFN(_fn) _fn
#define BCMNMIATTACHFN(_fn) _fn
#define BCMNMIATTACHDATA(_data) _data
#define CONST const
#if defined(BCM47XX) && defined(__ARM_ARCH_7A__)
#define BCM47XX_CA9
#else
#undef BCM47XX_CA9
#endif
#ifndef BCMFASTPATH
#if defined(mips) || defined(BCM47XX_CA9)
#define BCMFASTPATH __attribute__ ((__section__ (".text.fastpath")))
#define BCMFASTPATH_HOST __attribute__ ((__section__ (".text.fastpath_host")))
#else
#define BCMFASTPATH
#define BCMFASTPATH_HOST
#endif
#endif /* BCMFASTPATH */
#endif /* DONGLEBUILD */
#if defined(BCMROMOFFLOAD) || defined(BCMROMBUILD)
typedef struct {
uint16 esiz;
uint16 cnt;
void *addr;
} bcmromdat_patch_t;
#endif
/* Put some library data/code into ROM to reduce RAM requirements */
#if defined(BCMROMOFFLOAD)
#define BCMROMBASE ((uint32) 0x1e000000)
#define BCMROMEND (BCMROMBASE + (uint32) 0x100000)
/* These are legacy macros - make them nop's. */
#define BCMROMDATA(_data) _data
#define BCMROMFN(_fn) _fn
#define STATIC static
#define BCMROMDAT_NAME(_data) _data
#define BCMROMDAT_ARYSIZ(data) ARRAYSIZE(data)
#define BCMROMDAT_SIZEOF(data) sizeof(data)
#define BCMROMDAT_APATCH(data) \
bcmromdat_patch_t BCMROMDATA(data##__bcmpatch) = \
{ sizeof(data[0]), sizeof(data)/sizeof(data[0]), ((void*)data) };
#define BCMROMDAT_SPATCH(data) \
bcmromdat_patch_t BCMROMDATA(data##__bcmpatch) = \
{ sizeof(data), 1, ((void*)&data) };
#define BCMROMFN_NAME(_fn) _fn
#elif defined(BCMROMBUILD) && !defined(BCMROMSYMGEN_BUILD) && !defined(BCMJMPTBL_TCAM)
#include <bcmjmptbl.h>
#define STATIC static
#else /* !BCMROMBUILD */
#define BCMROMDATA(_data) _data
#define BCMROMDAT_NAME(_data) _data
#define BCMROMFN(_fn) _fn
#define BCMROMFN_NAME(_fn) _fn
#define STATIC static
#define BCMROMDAT_ARYSIZ(data) ARRAYSIZE(data)
#define BCMROMDAT_SIZEOF(data) sizeof(data)
#define BCMROMDAT_APATCH(data)
#define BCMROMDAT_SPATCH(data)
#endif /* !BCMROMBUILD */
/* Bus types */
#define SI_BUS 0 /* SOC Interconnect */
#define PCI_BUS 1 /* PCI target */
#define PCMCIA_BUS 2 /* PCMCIA target */
#define SDIO_BUS 3 /* SDIO target */
#define JTAG_BUS 4 /* JTAG */
#define USB_BUS 5 /* USB (does not support R/W REG) */
#define SPI_BUS 6 /* gSPI target */
#define RPC_BUS 7 /* RPC target */
/* Allows size optimization for single-bus image */
#ifdef BCMBUSTYPE
#define BUSTYPE(bus) (BCMBUSTYPE)
#else
#define BUSTYPE(bus) (bus)
#endif
/* Allows size optimization for single-backplane image */
#ifdef BCMCHIPTYPE
#define CHIPTYPE(bus) (BCMCHIPTYPE)
#else
#define CHIPTYPE(bus) (bus)
#endif
/* Allows size optimization for SPROM support */
#if defined(BCMSPROMBUS)
#define SPROMBUS (BCMSPROMBUS)
#elif defined(SI_PCMCIA_SROM)
#define SPROMBUS (PCMCIA_BUS)
#else
#define SPROMBUS (PCI_BUS)
#endif
/* Allows size optimization for single-chip image */
/* XXX These macros are NOT meant to encourage writing chip-specific code.
* Use them only when it is appropriate for example in PMU PLL/CHIP/SWREG
* controls and in chip-specific workarounds.
*/
#ifdef BCMCHIPID
#define CHIPID(chip) (BCMCHIPID)
#else
#define CHIPID(chip) (chip)
#endif
#ifdef BCMCHIPREV
#define CHIPREV(rev) (BCMCHIPREV)
#else
#define CHIPREV(rev) (rev)
#endif
/* Defines for DMA Address Width - Shared between OSL and HNDDMA */
#define DMADDR_MASK_32 0x0 /* Address mask for 32-bits */
#define DMADDR_MASK_30 0xc0000000 /* Address mask for 30-bits */
#define DMADDR_MASK_0 0xffffffff /* Address mask for 0-bits (hi-part) */
#define DMADDRWIDTH_30 30 /* 30-bit addressing capability */
#define DMADDRWIDTH_32 32 /* 32-bit addressing capability */
#define DMADDRWIDTH_63 63 /* 64-bit addressing capability */
#define DMADDRWIDTH_64 64 /* 64-bit addressing capability */
#ifdef BCMDMA64OSL
typedef struct {
uint32 loaddr;
uint32 hiaddr;
} dma64addr_t;
typedef dma64addr_t dmaaddr_t;
#define PHYSADDRHI(_pa) ((_pa).hiaddr)
#define PHYSADDRHISET(_pa, _val) \
do { \
(_pa).hiaddr = (_val); \
} while (0)
#define PHYSADDRLO(_pa) ((_pa).loaddr)
#define PHYSADDRLOSET(_pa, _val) \
do { \
(_pa).loaddr = (_val); \
} while (0)
#else
typedef unsigned long dmaaddr_t;
#define PHYSADDRHI(_pa) (0)
#define PHYSADDRHISET(_pa, _val)
#define PHYSADDRLO(_pa) ((_pa))
#define PHYSADDRLOSET(_pa, _val) \
do { \
(_pa) = (_val); \
} while (0)
#endif /* BCMDMA64OSL */
/* One physical DMA segment */
typedef struct {
dmaaddr_t addr;
uint32 length;
} hnddma_seg_t;
#if defined(MACOSX)
/* In MacOS, the OS API may return large number of segments. Setting this number lower
* will result in failure of dma map
*/
#define MAX_DMA_SEGS 8
#elif defined(__NetBSD__)
/* In NetBSD we also want more segments because the lower level mbuf mapping api might
* allocate a large number of segments
*/
#define MAX_DMA_SEGS 32
#elif defined(linux)
#define MAX_DMA_SEGS 8
#else
#define MAX_DMA_SEGS 4
#endif
typedef struct {
void *oshdmah; /* Opaque handle for OSL to store its information */
uint origsize; /* Size of the virtual packet */
uint nsegs;
hnddma_seg_t segs[MAX_DMA_SEGS];
} hnddma_seg_map_t;
/* packet headroom necessary to accommodate the largest header in the system, (i.e TXOFF).
* By doing, we avoid the need to allocate an extra buffer for the header when bridging to WL.
* There is a compile time check in wlc.c which ensure that this value is at least as big
* as TXOFF. This value is used in dma_rxfill (hnddma.c).
*/
#if defined(BCM_RPC_NOCOPY) || defined(BCM_RCP_TXNOCOPY)
/* add 40 bytes to allow for extra RPC header and info */
#define BCMEXTRAHDROOM 260
#else /* BCM_RPC_NOCOPY || BCM_RPC_TXNOCOPY */
#ifdef CTFMAP
#define BCMEXTRAHDROOM 208
#else /* CTFMAP */
#define BCMEXTRAHDROOM 204
#endif /* CTFMAP */
#endif /* BCM_RPC_NOCOPY || BCM_RPC_TXNOCOPY */
/* Packet alignment for most efficient SDIO (can change based on platform) */
#ifndef SDALIGN
#define SDALIGN 32
#endif
/* Headroom required for dongle-to-host communication. Packets allocated
* locally in the dongle (e.g. for CDC ioctls or RNDIS messages) should
* leave this much room in front for low-level message headers which may
* be needed to get across the dongle bus to the host. (These messages
* don't go over the network, so room for the full WL header above would
* be a waste.).
*/
/*
* XXX: set the numbers to be MAX of all the devices, to avoid problems with ROM builds
* USB BCMDONGLEHDRSZ and BCMDONGLEPADSZ is 0
* SDIO BCMDONGLEHDRSZ 12 and BCMDONGLEPADSZ 16
*/
#define BCMDONGLEHDRSZ 12
#define BCMDONGLEPADSZ 16
#define BCMDONGLEOVERHEAD (BCMDONGLEHDRSZ + BCMDONGLEPADSZ)
#ifdef BCMDBG
#ifndef BCMDBG_ERR
#define BCMDBG_ERR
#endif /* BCMDBG_ERR */
#ifndef BCMDBG_ASSERT
#define BCMDBG_ASSERT
#endif /* BCMDBG_ASSERT */
#endif /* BCMDBG */
#if defined(BCMDBG_ASSERT) || defined(BCMASSERT_LOG)
#define BCMASSERT_SUPPORT
#endif /* BCMDBG_ASSERT || BCMASSERT_LOG */
/* Macros for doing definition and get/set of bitfields
* Usage example, e.g. a three-bit field (bits 4-6):
* #define <NAME>_M BITFIELD_MASK(3)
* #define <NAME>_S 4
* ...
* regval = R_REG(osh, &regs->regfoo);
* field = GFIELD(regval, <NAME>);
* regval = SFIELD(regval, <NAME>, 1);
* W_REG(osh, &regs->regfoo, regval);
*/
#define BITFIELD_MASK(width) \
(((unsigned)1 << (width)) - 1)
#define GFIELD(val, field) \
(((val) >> field ## _S) & field ## _M)
#define SFIELD(val, field, bits) \
(((val) & (~(field ## _M << field ## _S))) | \
((unsigned)(bits) << field ## _S))
/* define BCMSMALL to remove misc features for memory-constrained environments */
#ifdef BCMSMALL
#undef BCMSPACE
#define bcmspace FALSE /* if (bcmspace) code is discarded */
#else
#define BCMSPACE
#define bcmspace TRUE /* if (bcmspace) code is retained */
#endif
/* Max. nvram variable table size */
#ifndef MAXSZ_NVRAM_VARS
#define MAXSZ_NVRAM_VARS 4096 /* XXX should be reduced */
#endif
#ifdef EFI
#define __attribute__(x) /* CSTYLED */
#endif
#endif /* _bcmdefs_h_ */

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/*
* Byte order utilities
*
* $Copyright Open Broadcom Corporation$
*
* $Id: bcmendian.h 370210 2012-11-21 05:35:27Z nisar $
*
* This file by default provides proper behavior on little-endian architectures.
* On big-endian architectures, IL_BIGENDIAN should be defined.
*/
#ifndef _BCMENDIAN_H_
#define _BCMENDIAN_H_
#include <typedefs.h>
/* Reverse the bytes in a 16-bit value */
#define BCMSWAP16(val) \
((uint16)((((uint16)(val) & (uint16)0x00ffU) << 8) | \
(((uint16)(val) & (uint16)0xff00U) >> 8)))
/* Reverse the bytes in a 32-bit value */
#define BCMSWAP32(val) \
((uint32)((((uint32)(val) & (uint32)0x000000ffU) << 24) | \
(((uint32)(val) & (uint32)0x0000ff00U) << 8) | \
(((uint32)(val) & (uint32)0x00ff0000U) >> 8) | \
(((uint32)(val) & (uint32)0xff000000U) >> 24)))
/* Reverse the two 16-bit halves of a 32-bit value */
#define BCMSWAP32BY16(val) \
((uint32)((((uint32)(val) & (uint32)0x0000ffffU) << 16) | \
(((uint32)(val) & (uint32)0xffff0000U) >> 16)))
/* Reverse the bytes in a 64-bit value */
#define BCMSWAP64(val) \
((uint64)((((uint64)(val) & 0x00000000000000ffULL) << 56) | \
(((uint64)(val) & 0x000000000000ff00ULL) << 40) | \
(((uint64)(val) & 0x0000000000ff0000ULL) << 24) | \
(((uint64)(val) & 0x00000000ff000000ULL) << 8) | \
(((uint64)(val) & 0x000000ff00000000ULL) >> 8) | \
(((uint64)(val) & 0x0000ff0000000000ULL) >> 24) | \
(((uint64)(val) & 0x00ff000000000000ULL) >> 40) | \
(((uint64)(val) & 0xff00000000000000ULL) >> 56)))
/* Reverse the two 32-bit halves of a 64-bit value */
#define BCMSWAP64BY32(val) \
((uint64)((((uint64)(val) & 0x00000000ffffffffULL) << 32) | \
(((uint64)(val) & 0xffffffff00000000ULL) >> 32)))
/* Byte swapping macros
* Host <=> Network (Big Endian) for 16- and 32-bit values
* Host <=> Little-Endian for 16- and 32-bit values
*/
#ifndef hton16
#ifndef IL_BIGENDIAN
#define HTON16(i) BCMSWAP16(i)
#define hton16(i) bcmswap16(i)
#define HTON32(i) BCMSWAP32(i)
#define hton32(i) bcmswap32(i)
#define NTOH16(i) BCMSWAP16(i)
#define ntoh16(i) bcmswap16(i)
#define NTOH32(i) BCMSWAP32(i)
#define ntoh32(i) bcmswap32(i)
#define LTOH16(i) (i)
#define ltoh16(i) (i)
#define LTOH32(i) (i)
#define ltoh32(i) (i)
#define HTOL16(i) (i)
#define htol16(i) (i)
#define HTOL32(i) (i)
#define htol32(i) (i)
#define HTOL64(i) (i)
#define htol64(i) (i)
#else /* IL_BIGENDIAN */
#define HTON16(i) (i)
#define hton16(i) (i)
#define HTON32(i) (i)
#define hton32(i) (i)
#define NTOH16(i) (i)
#define ntoh16(i) (i)
#define NTOH32(i) (i)
#define ntoh32(i) (i)
#define LTOH16(i) BCMSWAP16(i)
#define ltoh16(i) bcmswap16(i)
#define LTOH32(i) BCMSWAP32(i)
#define ltoh32(i) bcmswap32(i)
#define HTOL16(i) BCMSWAP16(i)
#define htol16(i) bcmswap16(i)
#define HTOL32(i) BCMSWAP32(i)
#define htol32(i) bcmswap32(i)
#define HTOL64(i) BCMSWAP64(i)
#define htol64(i) bcmswap64(i)
#endif /* IL_BIGENDIAN */
#endif /* hton16 */
#ifndef IL_BIGENDIAN
#define ltoh16_buf(buf, i)
#define htol16_buf(buf, i)
#else
#define ltoh16_buf(buf, i) bcmswap16_buf((uint16 *)(buf), (i))
#define htol16_buf(buf, i) bcmswap16_buf((uint16 *)(buf), (i))
#endif /* IL_BIGENDIAN */
/* Unaligned loads and stores in host byte order */
#ifndef IL_BIGENDIAN
#define load32_ua(a) ltoh32_ua(a)
#define store32_ua(a, v) htol32_ua_store(v, a)
#define load16_ua(a) ltoh16_ua(a)
#define store16_ua(a, v) htol16_ua_store(v, a)
#else
#define load32_ua(a) ntoh32_ua(a)
#define store32_ua(a, v) hton32_ua_store(v, a)
#define load16_ua(a) ntoh16_ua(a)
#define store16_ua(a, v) hton16_ua_store(v, a)
#endif /* IL_BIGENDIAN */
#define _LTOH16_UA(cp) ((cp)[0] | ((cp)[1] << 8))
#define _LTOH32_UA(cp) ((cp)[0] | ((cp)[1] << 8) | ((cp)[2] << 16) | ((cp)[3] << 24))
#define _NTOH16_UA(cp) (((cp)[0] << 8) | (cp)[1])
#define _NTOH32_UA(cp) (((cp)[0] << 24) | ((cp)[1] << 16) | ((cp)[2] << 8) | (cp)[3])
#define ltoh_ua(ptr) \
(sizeof(*(ptr)) == sizeof(uint8) ? *(const uint8 *)(ptr) : \
sizeof(*(ptr)) == sizeof(uint16) ? _LTOH16_UA((const uint8 *)(ptr)) : \
sizeof(*(ptr)) == sizeof(uint32) ? _LTOH32_UA((const uint8 *)(ptr)) : \
*(uint8 *)0)
#define ntoh_ua(ptr) \
(sizeof(*(ptr)) == sizeof(uint8) ? *(const uint8 *)(ptr) : \
sizeof(*(ptr)) == sizeof(uint16) ? _NTOH16_UA((const uint8 *)(ptr)) : \
sizeof(*(ptr)) == sizeof(uint32) ? _NTOH32_UA((const uint8 *)(ptr)) : \
*(uint8 *)0)
#ifdef __GNUC__
/* GNU macro versions avoid referencing the argument multiple times, while also
* avoiding the -fno-inline used in ROM builds.
*/
#define bcmswap16(val) ({ \
uint16 _val = (val); \
BCMSWAP16(_val); \
})
#define bcmswap32(val) ({ \
uint32 _val = (val); \
BCMSWAP32(_val); \
})
#define bcmswap64(val) ({ \
uint64 _val = (val); \
BCMSWAP64(_val); \
})
#define bcmswap32by16(val) ({ \
uint32 _val = (val); \
BCMSWAP32BY16(_val); \
})
#define bcmswap16_buf(buf, len) ({ \
uint16 *_buf = (uint16 *)(buf); \
uint _wds = (len) / 2; \
while (_wds--) { \
*_buf = bcmswap16(*_buf); \
_buf++; \
} \
})
#define htol16_ua_store(val, bytes) ({ \
uint16 _val = (val); \
uint8 *_bytes = (uint8 *)(bytes); \
_bytes[0] = _val & 0xff; \
_bytes[1] = _val >> 8; \
})
#define htol32_ua_store(val, bytes) ({ \
uint32 _val = (val); \
uint8 *_bytes = (uint8 *)(bytes); \
_bytes[0] = _val & 0xff; \
_bytes[1] = (_val >> 8) & 0xff; \
_bytes[2] = (_val >> 16) & 0xff; \
_bytes[3] = _val >> 24; \
})
#define hton16_ua_store(val, bytes) ({ \
uint16 _val = (val); \
uint8 *_bytes = (uint8 *)(bytes); \
_bytes[0] = _val >> 8; \
_bytes[1] = _val & 0xff; \
})
#define hton32_ua_store(val, bytes) ({ \
uint32 _val = (val); \
uint8 *_bytes = (uint8 *)(bytes); \
_bytes[0] = _val >> 24; \
_bytes[1] = (_val >> 16) & 0xff; \
_bytes[2] = (_val >> 8) & 0xff; \
_bytes[3] = _val & 0xff; \
})
#define ltoh16_ua(bytes) ({ \
const uint8 *_bytes = (const uint8 *)(bytes); \
_LTOH16_UA(_bytes); \
})
#define ltoh32_ua(bytes) ({ \
const uint8 *_bytes = (const uint8 *)(bytes); \
_LTOH32_UA(_bytes); \
})
#define ntoh16_ua(bytes) ({ \
const uint8 *_bytes = (const uint8 *)(bytes); \
_NTOH16_UA(_bytes); \
})
#define ntoh32_ua(bytes) ({ \
const uint8 *_bytes = (const uint8 *)(bytes); \
_NTOH32_UA(_bytes); \
})
#else /* !__GNUC__ */
/* Inline versions avoid referencing the argument multiple times */
static INLINE uint16
bcmswap16(uint16 val)
{
return BCMSWAP16(val);
}
static INLINE uint32
bcmswap32(uint32 val)
{
return BCMSWAP32(val);
}
static INLINE uint64
bcmswap64(uint64 val)
{
return BCMSWAP64(val);
}
static INLINE uint32
bcmswap32by16(uint32 val)
{
return BCMSWAP32BY16(val);
}
/* Reverse pairs of bytes in a buffer (not for high-performance use) */
/* buf - start of buffer of shorts to swap */
/* len - byte length of buffer */
static INLINE void
bcmswap16_buf(uint16 *buf, uint len)
{
len = len / 2;
while (len--) {
*buf = bcmswap16(*buf);
buf++;
}
}
/*
* Store 16-bit value to unaligned little-endian byte array.
*/
static INLINE void
htol16_ua_store(uint16 val, uint8 *bytes)
{
bytes[0] = val & 0xff;
bytes[1] = val >> 8;
}
/*
* Store 32-bit value to unaligned little-endian byte array.
*/
static INLINE void
htol32_ua_store(uint32 val, uint8 *bytes)
{
bytes[0] = val & 0xff;
bytes[1] = (val >> 8) & 0xff;
bytes[2] = (val >> 16) & 0xff;
bytes[3] = val >> 24;
}
/*
* Store 16-bit value to unaligned network-(big-)endian byte array.
*/
static INLINE void
hton16_ua_store(uint16 val, uint8 *bytes)
{
bytes[0] = val >> 8;
bytes[1] = val & 0xff;
}
/*
* Store 32-bit value to unaligned network-(big-)endian byte array.
*/
static INLINE void
hton32_ua_store(uint32 val, uint8 *bytes)
{
bytes[0] = val >> 24;
bytes[1] = (val >> 16) & 0xff;
bytes[2] = (val >> 8) & 0xff;
bytes[3] = val & 0xff;
}
/*
* Load 16-bit value from unaligned little-endian byte array.
*/
static INLINE uint16
ltoh16_ua(const void *bytes)
{
return _LTOH16_UA((const uint8 *)bytes);
}
/*
* Load 32-bit value from unaligned little-endian byte array.
*/
static INLINE uint32
ltoh32_ua(const void *bytes)
{
return _LTOH32_UA((const uint8 *)bytes);
}
/*
* Load 16-bit value from unaligned big-(network-)endian byte array.
*/
static INLINE uint16
ntoh16_ua(const void *bytes)
{
return _NTOH16_UA((const uint8 *)bytes);
}
/*
* Load 32-bit value from unaligned big-(network-)endian byte array.
*/
static INLINE uint32
ntoh32_ua(const void *bytes)
{
return _NTOH32_UA((const uint8 *)bytes);
}
#endif /* !__GNUC__ */
#endif /* !_BCMENDIAN_H_ */

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/*
* NVRAM variable manipulation
*
* $Copyright Open Broadcom Corporation$
*
* $Id: bcmnvram.h 401759 2013-05-13 16:08:08Z sudhirbs $
*/
#ifndef _bcmnvram_h_
#define _bcmnvram_h_
#ifndef _LANGUAGE_ASSEMBLY
#include <typedefs.h>
#include <bcmdefs.h>
struct nvram_header {
uint32 magic;
uint32 len;
uint32 crc_ver_init; /* 0:7 crc, 8:15 ver, 16:31 sdram_init */
uint32 config_refresh; /* 0:15 sdram_config, 16:31 sdram_refresh */
uint32 config_ncdl; /* ncdl values for memc */
};
struct nvram_tuple {
char *name;
char *value;
struct nvram_tuple *next;
};
/*
* Get default value for an NVRAM variable
*/
extern char *nvram_default_get(const char *name);
/*
* validate/restore all per-interface related variables
*/
extern void nvram_validate_all(char *prefix, bool restore);
/*
* restore specific per-interface variable
*/
extern void nvram_restore_var(char *prefix, char *name);
/*
* Initialize NVRAM access. May be unnecessary or undefined on certain
* platforms.
*/
extern int nvram_init(void *sih);
extern int nvram_deinit(void *sih);
#if defined(_CFE_) && defined(BCM_DEVINFO)
extern char *flashdrv_nvram;
extern char *devinfo_flashdrv_nvram;
extern int devinfo_nvram_init(void *sih);
extern int devinfo_nvram_sync(void);
extern void _nvram_hash_select(int idx);
#endif
/*
* Append a chunk of nvram variables to the global list
*/
extern int nvram_append(void *si, char *vars, uint varsz);
extern void nvram_get_global_vars(char **varlst, uint *varsz);
/*
* Check for reset button press for restoring factory defaults.
*/
extern int nvram_reset(void *sih);
/*
* Disable NVRAM access. May be unnecessary or undefined on certain
* platforms.
*/
extern void nvram_exit(void *sih);
/*
* Get the value of an NVRAM variable. The pointer returned may be
* invalid after a set.
* @param name name of variable to get
* @return value of variable or NULL if undefined
*/
extern char * nvram_get(const char *name);
/*
* Read the reset GPIO value from the nvram and set the GPIO
* as input
*/
extern int BCMINITFN(nvram_resetgpio_init)(void *sih);
/*
* Get the value of an NVRAM variable.
* @param name name of variable to get
* @return value of variable or NUL if undefined
*/
static INLINE char *
nvram_safe_get(const char *name)
{
char *p = nvram_get(name);
return p ? p : "";
}
/*
* Match an NVRAM variable.
* @param name name of variable to match
* @param match value to compare against value of variable
* @return TRUE if variable is defined and its value is string equal
* to match or FALSE otherwise
*/
static INLINE int
nvram_match(const char *name, const char *match)
{
const char *value = nvram_get(name);
return (value && !strcmp(value, match));
}
/*
* Inversely match an NVRAM variable.
* @param name name of variable to match
* @param match value to compare against value of variable
* @return TRUE if variable is defined and its value is not string
* equal to invmatch or FALSE otherwise
*/
static INLINE int
nvram_invmatch(const char *name, const char *invmatch)
{
const char *value = nvram_get(name);
return (value && strcmp(value, invmatch));
}
/*
* Set the value of an NVRAM variable. The name and value strings are
* copied into private storage. Pointers to previously set values
* may become invalid. The new value may be immediately
* retrieved but will not be permanently stored until a commit.
* @param name name of variable to set
* @param value value of variable
* @return 0 on success and errno on failure
*/
extern int nvram_set(const char *name, const char *value);
/*
* Unset an NVRAM variable. Pointers to previously set values
* remain valid until a set.
* @param name name of variable to unset
* @return 0 on success and errno on failure
* NOTE: use nvram_commit to commit this change to flash.
*/
extern int nvram_unset(const char *name);
/*
* Commit NVRAM variables to permanent storage. All pointers to values
* may be invalid after a commit.
* NVRAM values are undefined after a commit.
* @param nvram_corrupt true to corrupt nvram, false otherwise.
* @return 0 on success and errno on failure
*/
extern int nvram_commit_internal(bool nvram_corrupt);
/*
* Commit NVRAM variables to permanent storage. All pointers to values
* may be invalid after a commit.
* NVRAM values are undefined after a commit.
* @return 0 on success and errno on failure
*/
extern int nvram_commit(void);
/*
* Get all NVRAM variables (format name=value\0 ... \0\0).
* @param buf buffer to store variables
* @param count size of buffer in bytes
* @return 0 on success and errno on failure
*/
extern int nvram_getall(char *nvram_buf, int count);
/*
* returns the crc value of the nvram
* @param nvh nvram header pointer
*/
uint8 nvram_calc_crc(struct nvram_header * nvh);
extern int nvram_space;
#endif /* _LANGUAGE_ASSEMBLY */
/* The NVRAM version number stored as an NVRAM variable */
#define NVRAM_SOFTWARE_VERSION "1"
#define NVRAM_MAGIC 0x48534C46 /* 'FLSH' */
#define NVRAM_CLEAR_MAGIC 0x0
#define NVRAM_INVALID_MAGIC 0xFFFFFFFF
#define NVRAM_VERSION 1
#define NVRAM_HEADER_SIZE 20
/* This definition is for precommit staging, and will be removed */
#define NVRAM_SPACE 0x8000
/* For CFE builds this gets passed in thru the makefile */
#ifndef MAX_NVRAM_SPACE
#define MAX_NVRAM_SPACE 0x10000
#endif
#define DEF_NVRAM_SPACE 0x8000
#define ROM_ENVRAM_SPACE 0x1000
#define NVRAM_LZMA_MAGIC 0x4c5a4d41 /* 'LZMA' */
#define NVRAM_MAX_VALUE_LEN 255
#define NVRAM_MAX_PARAM_LEN 64
#define NVRAM_CRC_START_POSITION 9 /* magic, len, crc8 to be skipped */
#define NVRAM_CRC_VER_MASK 0xffffff00 /* for crc_ver_init */
/* Offsets to embedded nvram area */
#define NVRAM_START_COMPRESSED 0x400
#define NVRAM_START 0x1000
#define BCM_JUMBO_NVRAM_DELIMIT '\n'
#define BCM_JUMBO_START "Broadcom Jumbo Nvram file"
#if !defined(BCMDONGLEHOST) && !defined(BCMHIGHSDIO) && defined(BCMTRXV2)
extern char *_vars;
extern uint _varsz;
#endif /* !defined(BCMDONGLEHOST) && !defined(BCMHIGHSDIO) && defined(BCMTRXV2) */
#if (defined(FAILSAFE_UPGRADE) || defined(CONFIG_FAILSAFE_UPGRADE) || \
defined(__CONFIG_FAILSAFE_UPGRADE_SUPPORT__))
#define IMAGE_SIZE "image_size"
#define BOOTPARTITION "bootpartition"
#define IMAGE_BOOT BOOTPARTITION
#define PARTIALBOOTS "partialboots"
#define MAXPARTIALBOOTS "maxpartialboots"
#define IMAGE_1ST_FLASH_TRX "flash0.trx"
#define IMAGE_1ST_FLASH_OS "flash0.os"
#define IMAGE_2ND_FLASH_TRX "flash0.trx2"
#define IMAGE_2ND_FLASH_OS "flash0.os2"
#define IMAGE_FIRST_OFFSET "image_first_offset"
#define IMAGE_SECOND_OFFSET "image_second_offset"
#define LINUX_FIRST "linux"
#define LINUX_SECOND "linux2"
#endif
#if (defined(DUAL_IMAGE) || defined(CONFIG_DUAL_IMAGE) || \
defined(__CONFIG_DUAL_IMAGE_FLASH_SUPPORT__))
/* Shared by all: CFE, Linux Kernel, and Ap */
#define IMAGE_BOOT "image_boot"
#define BOOTPARTITION IMAGE_BOOT
/* CFE variables */
#define IMAGE_1ST_FLASH_TRX "flash0.trx"
#define IMAGE_1ST_FLASH_OS "flash0.os"
#define IMAGE_2ND_FLASH_TRX "flash0.trx2"
#define IMAGE_2ND_FLASH_OS "flash0.os2"
#define IMAGE_SIZE "image_size"
/* CFE and Linux Kernel shared variables */
#define IMAGE_FIRST_OFFSET "image_first_offset"
#define IMAGE_SECOND_OFFSET "image_second_offset"
/* Linux application variables */
#define LINUX_FIRST "linux"
#define LINUX_SECOND "linux2"
#define POLICY_TOGGLE "toggle"
#define LINUX_PART_TO_FLASH "linux_to_flash"
#define LINUX_FLASH_POLICY "linux_flash_policy"
#endif /* defined(DUAL_IMAGE||CONFIG_DUAL_IMAGE)||__CONFIG_DUAL_IMAGE_FLASH_SUPPORT__ */
#endif /* _bcmnvram_h_ */

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/*
* OTP support.
*
* $Copyright Open Broadcom Corporation$
*
* $Id: bcmotp.h 325751 2012-04-04 19:08:48Z nvalji $
*/
#ifndef _bcmotp_h_
#define _bcmotp_h_
/* OTP regions */
#define OTP_HW_RGN 1
#define OTP_SW_RGN 2
#define OTP_CI_RGN 4
#define OTP_FUSE_RGN 8
#define OTP_ALL_RGN 0xf /* From h/w region to end of OTP including checksum */
/* OTP Size */
#define OTP_SZ_MAX (6144/8) /* maximum bytes in one CIS */
/* Fixed size subregions sizes in words */
#define OTPGU_CI_SZ 2
/* OTP usage */
#define OTP4325_FM_DISABLED_OFFSET 188
#if defined(BCMNVRAMW) || defined(OTP_REWRITE)
/* Global RDE index for chips not having an OTP PMU resource. */
#define OTP_GLOBAL_RDE_IDX 0xFF
#endif
/* Exported functions */
extern int otp_status(void *oh);
extern int otp_size(void *oh);
extern uint16 otp_read_bit(void *oh, uint offset);
extern void* otp_init(si_t *sih);
#if !defined(BCMDONGLEHOST)
extern int otp_read_region(si_t *sih, int region, uint16 *data, uint *wlen);
extern int otp_read_word(si_t *sih, uint wn, uint16 *data);
extern int otp_nvread(void *oh, char *data, uint *len);
#ifdef BCMNVRAMW
extern int otp_write_region(si_t *sih, int region, uint16 *data, uint wlen);
extern int otp_write_word(si_t *sih, uint wn, uint16 data);
extern int otp_cis_append_region(si_t *sih, int region, char *vars, int count);
extern int otp_lock(si_t *sih);
extern int otp_nvwrite(void *oh, uint16 *data, uint wlen);
#endif /* BCMNVRAMW */
#endif /* !defined(BCMDONGLEHOST) */
extern int otp_dump(void *oh, int arg, char *buf, uint size);
extern int otp_dumpstats(void *oh, int arg, char *buf, uint size);
#if !defined(BCMDONGLEHOST) && defined(BCMNVRAMW)
#define otp_write_rde(oh, rde, bit, val) ipxotp_write_rde(oh, rde, bit, val)
extern int otp_write_bits(void *oh, uint offset, int bits, uint8* data);
#ifdef OTP_DEBUG
extern int otp_verify1x(void *oh, uint off, uint fuse);
extern int otp_read1x(void *oh, uint off, uint fuse);
extern int otp_repair_bit(void *oh, uint off, uint val);
extern int otp_write_ones(void *oh, uint off, uint bits);
extern int otp_write_ones_old(void *oh, uint off, uint bits);
#endif
#endif /* !defined(BCMDONGLEHOST) && defined(BCMNVRAMW) */
#if !defined(BCMDONGLEHOST) && (defined(BCMNVRAMW) || defined(OTP_REWRITE))
extern int ipxotp_write_rde(void *oh, int rde, uint bit, uint val);
extern int otp_rewrite_all(void *oh);
#endif /* !BCMDONGLEHOST) && (BCMNVRAMW || OTP_REWRITE) */
#endif /* _bcmotp_h_ */

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/*
* Broadcom PCI-SPI Host Controller Register Definitions
*
* $ Copyright Open Broadcom Corporation $
*
* $Id: bcmpcispi.h 241182 2011-02-17 21:50:03Z $
*/
#ifndef _BCM_PCI_SPI_H
#define _BCM_PCI_SPI_H
/* cpp contortions to concatenate w/arg prescan */
#ifndef PAD
#define _PADLINE(line) pad ## line
#define _XSTR(line) _PADLINE(line)
#define PAD _XSTR(__LINE__)
#endif /* PAD */
typedef volatile struct {
uint32 spih_ctrl; /* 0x00 SPI Control Register */
uint32 spih_stat; /* 0x04 SPI Status Register */
uint32 spih_data; /* 0x08 SPI Data Register, 32-bits wide */
uint32 spih_ext; /* 0x0C SPI Extension Register */
uint32 PAD[4]; /* 0x10-0x1F PADDING */
uint32 spih_gpio_ctrl; /* 0x20 SPI GPIO Control Register */
uint32 spih_gpio_data; /* 0x24 SPI GPIO Data Register */
uint32 PAD[6]; /* 0x28-0x3F PADDING */
uint32 spih_int_edge; /* 0x40 SPI Interrupt Edge Register (0=Level, 1=Edge) */
uint32 spih_int_pol; /* 0x44 SPI Interrupt Polarity Register (0=Active Low, */
/* 1=Active High) */
uint32 spih_int_mask; /* 0x48 SPI Interrupt Mask */
uint32 spih_int_status; /* 0x4C SPI Interrupt Status */
uint32 PAD[4]; /* 0x50-0x5F PADDING */
uint32 spih_hex_disp; /* 0x60 SPI 4-digit hex display value */
uint32 spih_current_ma; /* 0x64 SPI SD card current consumption in mA */
uint32 PAD[1]; /* 0x68 PADDING */
uint32 spih_disp_sel; /* 0x6c SPI 4-digit hex display mode select (1=current) */
uint32 PAD[4]; /* 0x70-0x7F PADDING */
uint32 PAD[8]; /* 0x80-0x9F PADDING */
uint32 PAD[8]; /* 0xA0-0xBF PADDING */
uint32 spih_pll_ctrl; /* 0xC0 PLL Control Register */
uint32 spih_pll_status; /* 0xC4 PLL Status Register */
uint32 spih_xtal_freq; /* 0xC8 External Clock Frequency in units of 10000Hz */
uint32 spih_clk_count; /* 0xCC External Clock Count Register */
} spih_regs_t;
typedef volatile struct {
uint32 cfg_space[0x40]; /* 0x000-0x0FF PCI Configuration Space (Read Only) */
uint32 P_IMG_CTRL0; /* 0x100 PCI Image0 Control Register */
uint32 P_BA0; /* 0x104 32 R/W PCI Image0 Base Address register */
uint32 P_AM0; /* 0x108 32 R/W PCI Image0 Address Mask register */
uint32 P_TA0; /* 0x10C 32 R/W PCI Image0 Translation Address register */
uint32 P_IMG_CTRL1; /* 0x110 32 R/W PCI Image1 Control register */
uint32 P_BA1; /* 0x114 32 R/W PCI Image1 Base Address register */
uint32 P_AM1; /* 0x118 32 R/W PCI Image1 Address Mask register */
uint32 P_TA1; /* 0x11C 32 R/W PCI Image1 Translation Address register */
uint32 P_IMG_CTRL2; /* 0x120 32 R/W PCI Image2 Control register */
uint32 P_BA2; /* 0x124 32 R/W PCI Image2 Base Address register */
uint32 P_AM2; /* 0x128 32 R/W PCI Image2 Address Mask register */
uint32 P_TA2; /* 0x12C 32 R/W PCI Image2 Translation Address register */
uint32 P_IMG_CTRL3; /* 0x130 32 R/W PCI Image3 Control register */
uint32 P_BA3; /* 0x134 32 R/W PCI Image3 Base Address register */
uint32 P_AM3; /* 0x138 32 R/W PCI Image3 Address Mask register */
uint32 P_TA3; /* 0x13C 32 R/W PCI Image3 Translation Address register */
uint32 P_IMG_CTRL4; /* 0x140 32 R/W PCI Image4 Control register */
uint32 P_BA4; /* 0x144 32 R/W PCI Image4 Base Address register */
uint32 P_AM4; /* 0x148 32 R/W PCI Image4 Address Mask register */
uint32 P_TA4; /* 0x14C 32 R/W PCI Image4 Translation Address register */
uint32 P_IMG_CTRL5; /* 0x150 32 R/W PCI Image5 Control register */
uint32 P_BA5; /* 0x154 32 R/W PCI Image5 Base Address register */
uint32 P_AM5; /* 0x158 32 R/W PCI Image5 Address Mask register */
uint32 P_TA5; /* 0x15C 32 R/W PCI Image5 Translation Address register */
uint32 P_ERR_CS; /* 0x160 32 R/W PCI Error Control and Status register */
uint32 P_ERR_ADDR; /* 0x164 32 R PCI Erroneous Address register */
uint32 P_ERR_DATA; /* 0x168 32 R PCI Erroneous Data register */
uint32 PAD[5]; /* 0x16C-0x17F PADDING */
uint32 WB_CONF_SPC_BAR; /* 0x180 32 R WISHBONE Configuration Space Base Address */
uint32 W_IMG_CTRL1; /* 0x184 32 R/W WISHBONE Image1 Control register */
uint32 W_BA1; /* 0x188 32 R/W WISHBONE Image1 Base Address register */
uint32 W_AM1; /* 0x18C 32 R/W WISHBONE Image1 Address Mask register */
uint32 W_TA1; /* 0x190 32 R/W WISHBONE Image1 Translation Address reg */
uint32 W_IMG_CTRL2; /* 0x194 32 R/W WISHBONE Image2 Control register */
uint32 W_BA2; /* 0x198 32 R/W WISHBONE Image2 Base Address register */
uint32 W_AM2; /* 0x19C 32 R/W WISHBONE Image2 Address Mask register */
uint32 W_TA2; /* 0x1A0 32 R/W WISHBONE Image2 Translation Address reg */
uint32 W_IMG_CTRL3; /* 0x1A4 32 R/W WISHBONE Image3 Control register */
uint32 W_BA3; /* 0x1A8 32 R/W WISHBONE Image3 Base Address register */
uint32 W_AM3; /* 0x1AC 32 R/W WISHBONE Image3 Address Mask register */
uint32 W_TA3; /* 0x1B0 32 R/W WISHBONE Image3 Translation Address reg */
uint32 W_IMG_CTRL4; /* 0x1B4 32 R/W WISHBONE Image4 Control register */
uint32 W_BA4; /* 0x1B8 32 R/W WISHBONE Image4 Base Address register */
uint32 W_AM4; /* 0x1BC 32 R/W WISHBONE Image4 Address Mask register */
uint32 W_TA4; /* 0x1C0 32 R/W WISHBONE Image4 Translation Address reg */
uint32 W_IMG_CTRL5; /* 0x1C4 32 R/W WISHBONE Image5 Control register */
uint32 W_BA5; /* 0x1C8 32 R/W WISHBONE Image5 Base Address register */
uint32 W_AM5; /* 0x1CC 32 R/W WISHBONE Image5 Address Mask register */
uint32 W_TA5; /* 0x1D0 32 R/W WISHBONE Image5 Translation Address reg */
uint32 W_ERR_CS; /* 0x1D4 32 R/W WISHBONE Error Control and Status reg */
uint32 W_ERR_ADDR; /* 0x1D8 32 R WISHBONE Erroneous Address register */
uint32 W_ERR_DATA; /* 0x1DC 32 R WISHBONE Erroneous Data register */
uint32 CNF_ADDR; /* 0x1E0 32 R/W Configuration Cycle register */
uint32 CNF_DATA; /* 0x1E4 32 R/W Configuration Cycle Generation Data reg */
uint32 INT_ACK; /* 0x1E8 32 R Interrupt Acknowledge register */
uint32 ICR; /* 0x1EC 32 R/W Interrupt Control register */
uint32 ISR; /* 0x1F0 32 R/W Interrupt Status register */
} spih_pciregs_t;
/*
* PCI Core interrupt enable and status bit definitions.
*/
/* PCI Core ICR Register bit definitions */
#define PCI_INT_PROP_EN (1 << 0) /* Interrupt Propagation Enable */
#define PCI_WB_ERR_INT_EN (1 << 1) /* Wishbone Error Interrupt Enable */
#define PCI_PCI_ERR_INT_EN (1 << 2) /* PCI Error Interrupt Enable */
#define PCI_PAR_ERR_INT_EN (1 << 3) /* Parity Error Interrupt Enable */
#define PCI_SYS_ERR_INT_EN (1 << 4) /* System Error Interrupt Enable */
#define PCI_SOFTWARE_RESET (1U << 31) /* Software reset of the PCI Core. */
/* PCI Core ISR Register bit definitions */
#define PCI_INT_PROP_ST (1 << 0) /* Interrupt Propagation Status */
#define PCI_WB_ERR_INT_ST (1 << 1) /* Wishbone Error Interrupt Status */
#define PCI_PCI_ERR_INT_ST (1 << 2) /* PCI Error Interrupt Status */
#define PCI_PAR_ERR_INT_ST (1 << 3) /* Parity Error Interrupt Status */
#define PCI_SYS_ERR_INT_ST (1 << 4) /* System Error Interrupt Status */
/* Registers on the Wishbone bus */
#define SPIH_CTLR_INTR (1 << 0) /* SPI Host Controller Core Interrupt */
#define SPIH_DEV_INTR (1 << 1) /* SPI Device Interrupt */
#define SPIH_WFIFO_INTR (1 << 2) /* SPI Tx FIFO Empty Intr (FPGA Rev >= 8) */
/* GPIO Bit definitions */
#define SPIH_CS (1 << 0) /* SPI Chip Select (active low) */
#define SPIH_SLOT_POWER (1 << 1) /* SD Card Slot Power Enable */
#define SPIH_CARD_DETECT (1 << 2) /* SD Card Detect */
/* SPI Status Register Bit definitions */
#define SPIH_STATE_MASK 0x30 /* SPI Transfer State Machine state mask */
#define SPIH_STATE_SHIFT 4 /* SPI Transfer State Machine state shift */
#define SPIH_WFFULL (1 << 3) /* SPI Write FIFO Full */
#define SPIH_WFEMPTY (1 << 2) /* SPI Write FIFO Empty */
#define SPIH_RFFULL (1 << 1) /* SPI Read FIFO Full */
#define SPIH_RFEMPTY (1 << 0) /* SPI Read FIFO Empty */
#define SPIH_EXT_CLK (1U << 31) /* Use External Clock as PLL Clock source. */
#define SPIH_PLL_NO_CLK (1 << 1) /* Set to 1 if the PLL's input clock is lost. */
#define SPIH_PLL_LOCKED (1 << 3) /* Set to 1 when the PLL is locked. */
/* Spin bit loop bound check */
#define SPI_SPIN_BOUND 0xf4240 /* 1 million */
#endif /* _BCM_PCI_SPI_H */

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/*
* Performance counters software interface.
*
* $Copyright Open Broadcom Corporation$
*
* $Id: bcmperf.h 241182 2011-02-17 21:50:03Z $
*/
/* essai */
#ifndef _BCMPERF_H_
#define _BCMPERF_H_
/* get cache hits and misses */
#define BCMPERF_ENABLE_INSTRCOUNT()
#define BCMPERF_ENABLE_ICACHE_MISS()
#define BCMPERF_ENABLE_ICACHE_HIT()
#define BCMPERF_GETICACHE_MISS(x) ((x) = 0)
#define BCMPERF_GETICACHE_HIT(x) ((x) = 0)
#define BCMPERF_GETINSTRCOUNT(x) ((x) = 0)
#endif /* _BCMPERF_H_ */

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/*
* BRCM SDIO HOST CONTROLLER driver
*
* Copyright (C) 2012, Broadcom Corporation
* All Rights Reserved.
*
* This is UNPUBLISHED PROPRIETARY SOURCE CODE of Broadcom Corporation;
* the contents of this file may not be disclosed to third parties, copied
* or duplicated in any form, in whole or in part, without the prior
* written permission of Broadcom Corporation.
*
* $Id: bcmsdbrcm.h 241182 2011-02-17 21:50:03Z gmo $
*/
/* global msglevel for debug messages */
#ifdef BCMDBG
#define sd_err(x) do { if (sd_msglevel & SDH_ERROR_VAL) printf x; } while (0)
#define sd_trace(x) do { if (sd_msglevel & SDH_TRACE_VAL) printf x; } while (0)
#define sd_info(x) do { if (sd_msglevel & SDH_INFO_VAL) printf x; } while (0)
#define sd_debug(x) do { if (sd_msglevel & SDH_DEBUG_VAL) printf x; } while (0)
#define sd_data(x) do { if (sd_msglevel & SDH_DATA_VAL) printf x; } while (0)
#define sd_ctrl(x) do { if (sd_msglevel & SDH_CTRL_VAL) printf x; } while (0)
#else
#define sd_err(x)
#define sd_trace(x)
#define sd_info(x)
#define sd_debug(x)
#define sd_data(x)
#define sd_ctrl(x)
#endif
#ifdef BCMPERFSTATS
#define sd_log(x) do { if (sd_msglevel & SDH_LOG_VAL) bcmlog x; } while (0)
#else
#define sd_log(x)
#endif
/* SDIOH public information, used by per-port code */
struct sdioh_pubinfo {
int local_intrcount; /* Controller interrupt count */
bool dev_init_done; /* Client SDIO interface initted */
bool host_init_done; /* Controller initted */
bool intr_registered; /* Client handler registered */
bool dev_intr_enabled; /* Device interrupt enabled/disabled */
uint lockcount; /* Next count of sdbrcm_lock() calls */
void *sdos_info; /* Pointer to per-OS private data */
};
#define BLOCK_SIZE_4318 64
#define BLOCK_SIZE_4328 512
/* private bus modes */
/* move to API or hardware header. */
#define SDIOH_MODE_SPI 0
#define SDIOH_MODE_SD1 1
#define SDIOH_MODE_SD4 2
/* Expected dev status value for CMD7 */
#define SDIOH_CMD7_EXP_STATUS 0x00001E00
#define RETRIES_SMALL 20
#define RETRIES_LARGE 500000
#define SD_TIMEOUT 250000 /* Timeout after several ms if CMD not complete. */
#define ARVM_MASK 0xFF10
#define USE_PIO 0x0 /* DMA or PIO */
#define USE_DMA 0x1
#define NTXD 4
#define NRXD 4
#define RXBUFSZ 8192
#define NRXBUFPOST 4
#define HWRXOFF 8
#define USE_BLOCKMODE 0x2 /* Block mode can be single block or multi */
#define USE_MULTIBLOCK 0x4
#define EXT_CLK 0xffffffff /* external clock improve comment. */
extern int isr_sdbrcm_check_dev_intr(struct sdioh_pubinfo *sd);
extern uint sd_msglevel;
extern uint32 *sdbrcm_reg_map(osl_t *osh, int32 addr, int size);
extern void sdbrcm_reg_unmap(osl_t *osh, int32 addr, int size);
extern int sdbrcm_register_irq(sdioh_info_t *sd, uint irq);
extern void sdbrcm_free_irq(uint irq, sdioh_info_t *sd);
extern void sdbrcm_lock(sdioh_info_t *sd);
extern void sdbrcm_unlock(sdioh_info_t *sd);
extern void sdbrcm_devintr_on(sdioh_info_t *sd);
extern void sdbrcm_devintr_off(sdioh_info_t *sd);
/* Allocate/init/free per-OS private data */
extern int sdbrcm_osinit(sdioh_info_t *sd, osl_t *osh);
extern void sdbrcm_osfree(sdioh_info_t *sd, osl_t *osh);

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/*
* Definitions for API from sdio common code (bcmsdh) to individual
* host controller drivers.
*
* $Copyright Open Broadcom Corporation$
*
* $Id: bcmsdbus.h 299859 2011-12-01 03:53:27Z $
*/
#ifndef _sdio_api_h_
#define _sdio_api_h_
#define SDIOH_API_RC_SUCCESS (0x00)
#define SDIOH_API_RC_FAIL (0x01)
#define SDIOH_API_SUCCESS(status) (status == 0)
#define SDIOH_READ 0 /* Read request */
#define SDIOH_WRITE 1 /* Write request */
#define SDIOH_DATA_FIX 0 /* Fixed addressing */
#define SDIOH_DATA_INC 1 /* Incremental addressing */
#define SDIOH_CMD_TYPE_NORMAL 0 /* Normal command */
#define SDIOH_CMD_TYPE_APPEND 1 /* Append command */
#define SDIOH_CMD_TYPE_CUTTHRU 2 /* Cut-through command */
#define SDIOH_DATA_PIO 0 /* PIO mode */
#define SDIOH_DATA_DMA 1 /* DMA mode */
typedef int SDIOH_API_RC;
/* SDio Host structure */
typedef struct sdioh_info sdioh_info_t;
/* callback function, taking one arg */
typedef void (*sdioh_cb_fn_t)(void *);
/* attach, return handler on success, NULL if failed.
* The handler shall be provided by all subsequent calls. No local cache
* cfghdl points to the starting address of pci device mapped memory
*/
extern sdioh_info_t * sdioh_attach(osl_t *osh, void *cfghdl, uint irq);
extern SDIOH_API_RC sdioh_detach(osl_t *osh, sdioh_info_t *si);
extern SDIOH_API_RC sdioh_interrupt_register(sdioh_info_t *si, sdioh_cb_fn_t fn, void *argh);
extern SDIOH_API_RC sdioh_interrupt_deregister(sdioh_info_t *si);
/* query whether SD interrupt is enabled or not */
extern SDIOH_API_RC sdioh_interrupt_query(sdioh_info_t *si, bool *onoff);
/* enable or disable SD interrupt */
extern SDIOH_API_RC sdioh_interrupt_set(sdioh_info_t *si, bool enable_disable);
#if defined(DHD_DEBUG)
extern bool sdioh_interrupt_pending(sdioh_info_t *si);
#endif
/* read or write one byte using cmd52 */
extern SDIOH_API_RC sdioh_request_byte(sdioh_info_t *si, uint rw, uint fnc, uint addr, uint8 *byte);
/* read or write 2/4 bytes using cmd53 */
extern SDIOH_API_RC sdioh_request_word(sdioh_info_t *si, uint cmd_type, uint rw, uint fnc,
uint addr, uint32 *word, uint nbyte);
/* read or write any buffer using cmd53 */
extern SDIOH_API_RC sdioh_request_buffer(sdioh_info_t *si, uint pio_dma, uint fix_inc,
uint rw, uint fnc_num, uint32 addr, uint regwidth, uint32 buflen, uint8 *buffer,
void *pkt);
/* get cis data */
extern SDIOH_API_RC sdioh_cis_read(sdioh_info_t *si, uint fuc, uint8 *cis, uint32 length);
extern SDIOH_API_RC sdioh_cfg_read(sdioh_info_t *si, uint fuc, uint32 addr, uint8 *data);
extern SDIOH_API_RC sdioh_cfg_write(sdioh_info_t *si, uint fuc, uint32 addr, uint8 *data);
/* query number of io functions */
extern uint sdioh_query_iofnum(sdioh_info_t *si);
/* handle iovars */
extern int sdioh_iovar_op(sdioh_info_t *si, const char *name,
void *params, int plen, void *arg, int len, bool set);
/* Issue abort to the specified function and clear controller as needed */
extern int sdioh_abort(sdioh_info_t *si, uint fnc);
/* Start and Stop SDIO without re-enumerating the SD card. */
extern int sdioh_start(sdioh_info_t *si, int stage);
extern int sdioh_stop(sdioh_info_t *si);
/* Wait system lock free */
extern int sdioh_waitlockfree(sdioh_info_t *si);
/* Reset and re-initialize the device */
extern int sdioh_sdio_reset(sdioh_info_t *si);
/* Helper function */
void *bcmsdh_get_sdioh(bcmsdh_info_t *sdh);
#ifdef BCMSPI
/* Function to pass gSPI specific device-status bits to dhd. */
extern uint32 sdioh_get_dstatus(sdioh_info_t *si);
/* chipid and chiprev info for lower layers to control sw WAR's for hw bugs. */
extern void sdioh_chipinfo(sdioh_info_t *si, uint32 chip, uint32 chiprev);
extern void sdioh_dwordmode(sdioh_info_t *si, bool set);
#endif /* BCMSPI */
#if defined(BCMSDIOH_STD)
#define SDIOH_SLEEP_ENABLED
#endif
extern SDIOH_API_RC sdioh_sleep(sdioh_info_t *si, bool enab);
/* GPIO support */
extern SDIOH_API_RC sdioh_gpio_init(sdioh_info_t *sd);
extern bool sdioh_gpioin(sdioh_info_t *sd, uint32 gpio);
extern SDIOH_API_RC sdioh_gpioouten(sdioh_info_t *sd, uint32 gpio);
extern SDIOH_API_RC sdioh_gpioout(sdioh_info_t *sd, uint32 gpio, bool enab);
#endif /* _sdio_api_h_ */

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/*
* SDIO host client driver interface of Broadcom HNBU
* export functions to client drivers
* abstract OS and BUS specific details of SDIO
*
* $ Copyright Open License Broadcom Corporation $
*
* $Id: bcmsdh.h 327775 2012-04-16 18:54:32Z $
*/
/**
* @file bcmsdh.h
*/
#ifndef _bcmsdh_h_
#define _bcmsdh_h_
#define BCMSDH_ERROR_VAL 0x0001 /* Error */
#define BCMSDH_INFO_VAL 0x0002 /* Info */
extern const uint bcmsdh_msglevel;
#define BCMSDH_ERROR(x)
#define BCMSDH_INFO(x)
#if (defined(BCMSDIOH_STD) || defined(BCMSDIOH_BCM) || defined(BCMSDIOH_SPI))
#define BCMSDH_ADAPTER
#endif /* BCMSDIO && (BCMSDIOH_STD || BCMSDIOH_BCM || BCMSDIOH_SPI) */
/* forward declarations */
typedef struct bcmsdh_info bcmsdh_info_t;
typedef void (*bcmsdh_cb_fn_t)(void *);
/* Attach and build an interface to the underlying SD host driver.
* - Allocates resources (structs, arrays, mem, OS handles, etc) needed by bcmsdh.
* - Returns the bcmsdh handle and virtual address base for register access.
* The returned handle should be used in all subsequent calls, but the bcmsh
* implementation may maintain a single "default" handle (e.g. the first or
* most recent one) to enable single-instance implementations to pass NULL.
*/
#if 0 && (NDISVER >= 0x0630) && 1
extern bcmsdh_info_t *bcmsdh_attach(osl_t *osh, void *cfghdl,
void **regsva, uint irq, shared_info_t *sh);
#else
extern bcmsdh_info_t *bcmsdh_attach(osl_t *osh, void *cfghdl, void **regsva, uint irq);
#endif
/* Detach - freeup resources allocated in attach */
extern int bcmsdh_detach(osl_t *osh, void *sdh);
/* Query if SD device interrupts are enabled */
extern bool bcmsdh_intr_query(void *sdh);
/* Enable/disable SD interrupt */
extern int bcmsdh_intr_enable(void *sdh);
extern int bcmsdh_intr_disable(void *sdh);
/* Register/deregister device interrupt handler. */
extern int bcmsdh_intr_reg(void *sdh, bcmsdh_cb_fn_t fn, void *argh);
extern int bcmsdh_intr_dereg(void *sdh);
#if defined(DHD_DEBUG)
/* Query pending interrupt status from the host controller */
extern bool bcmsdh_intr_pending(void *sdh);
#endif
/* Register a callback to be called if and when bcmsdh detects
* device removal. No-op in the case of non-removable/hardwired devices.
*/
extern int bcmsdh_devremove_reg(void *sdh, bcmsdh_cb_fn_t fn, void *argh);
/* Access SDIO address space (e.g. CCCR) using CMD52 (single-byte interface).
* fn: function number
* addr: unmodified SDIO-space address
* data: data byte to write
* err: pointer to error code (or NULL)
*/
extern uint8 bcmsdh_cfg_read(void *sdh, uint func, uint32 addr, int *err);
extern void bcmsdh_cfg_write(void *sdh, uint func, uint32 addr, uint8 data, int *err);
/* Read/Write 4bytes from/to cfg space */
extern uint32 bcmsdh_cfg_read_word(void *sdh, uint fnc_num, uint32 addr, int *err);
extern void bcmsdh_cfg_write_word(void *sdh, uint fnc_num, uint32 addr, uint32 data, int *err);
/* Read CIS content for specified function.
* fn: function whose CIS is being requested (0 is common CIS)
* cis: pointer to memory location to place results
* length: number of bytes to read
* Internally, this routine uses the values from the cis base regs (0x9-0xB)
* to form an SDIO-space address to read the data from.
*/
extern int bcmsdh_cis_read(void *sdh, uint func, uint8 *cis, uint length);
/* Synchronous access to device (client) core registers via CMD53 to F1.
* addr: backplane address (i.e. >= regsva from attach)
* size: register width in bytes (2 or 4)
* data: data for register write
*/
extern uint32 bcmsdh_reg_read(void *sdh, uint32 addr, uint size);
extern uint32 bcmsdh_reg_write(void *sdh, uint32 addr, uint size, uint32 data);
/* set sb address window */
extern int bcmsdhsdio_set_sbaddr_window(void *sdh, uint32 address, bool force_set);
/* Indicate if last reg read/write failed */
extern bool bcmsdh_regfail(void *sdh);
/* Buffer transfer to/from device (client) core via cmd53.
* fn: function number
* addr: backplane address (i.e. >= regsva from attach)
* flags: backplane width, address increment, sync/async
* buf: pointer to memory data buffer
* nbytes: number of bytes to transfer to/from buf
* pkt: pointer to packet associated with buf (if any)
* complete: callback function for command completion (async only)
* handle: handle for completion callback (first arg in callback)
* Returns 0 or error code.
* NOTE: Async operation is not currently supported.
*/
typedef void (*bcmsdh_cmplt_fn_t)(void *handle, int status, bool sync_waiting);
extern int bcmsdh_send_buf(void *sdh, uint32 addr, uint fn, uint flags,
uint8 *buf, uint nbytes, void *pkt,
bcmsdh_cmplt_fn_t complete_fn, void *handle);
extern int bcmsdh_recv_buf(void *sdh, uint32 addr, uint fn, uint flags,
uint8 *buf, uint nbytes, void *pkt,
bcmsdh_cmplt_fn_t complete_fn, void *handle);
/* Flags bits */
#define SDIO_REQ_4BYTE 0x1 /* Four-byte target (backplane) width (vs. two-byte) */
#define SDIO_REQ_FIXED 0x2 /* Fixed address (FIFO) (vs. incrementing address) */
#define SDIO_REQ_ASYNC 0x4 /* Async request (vs. sync request) */
#define SDIO_BYTE_MODE 0x8 /* Byte mode request(non-block mode) */
/* Pending (non-error) return code */
#define BCME_PENDING 1
/* Read/write to memory block (F1, no FIFO) via CMD53 (sync only).
* rw: read or write (0/1)
* addr: direct SDIO address
* buf: pointer to memory data buffer
* nbytes: number of bytes to transfer to/from buf
* Returns 0 or error code.
*/
extern int bcmsdh_rwdata(void *sdh, uint rw, uint32 addr, uint8 *buf, uint nbytes);
/* Issue an abort to the specified function */
extern int bcmsdh_abort(void *sdh, uint fn);
/* Start SDIO Host Controller communication */
extern int bcmsdh_start(void *sdh, int stage);
/* Stop SDIO Host Controller communication */
extern int bcmsdh_stop(void *sdh);
/* Wait system lock free */
extern int bcmsdh_waitlockfree(void *sdh);
/* Returns the "Device ID" of target device on the SDIO bus. */
extern int bcmsdh_query_device(void *sdh);
/* Returns the number of IO functions reported by the device */
extern uint bcmsdh_query_iofnum(void *sdh);
/* Miscellaneous knob tweaker. */
extern int bcmsdh_iovar_op(void *sdh, const char *name,
void *params, int plen, void *arg, int len, bool set);
/* Reset and reinitialize the device */
extern int bcmsdh_reset(bcmsdh_info_t *sdh);
/* helper functions */
extern void *bcmsdh_get_sdioh(bcmsdh_info_t *sdh);
/* callback functions */
typedef struct {
/* attach to device */
void *(*attach)(uint16 vend_id, uint16 dev_id, uint16 bus, uint16 slot,
uint16 func, uint bustype, void * regsva, osl_t * osh,
void * param);
/* detach from device */
void (*detach)(void *ch);
} bcmsdh_driver_t;
/* platform specific/high level functions */
extern int bcmsdh_register(bcmsdh_driver_t *driver);
extern void bcmsdh_unregister(void);
extern bool bcmsdh_chipmatch(uint16 vendor, uint16 device);
extern void bcmsdh_device_remove(void * sdh);
#if defined(OOB_INTR_ONLY)
extern int bcmsdh_register_oob_intr(void * dhdp);
extern void bcmsdh_unregister_oob_intr(void);
extern void bcmsdh_oob_intr_set(bool enable);
#endif /* defined(OOB_INTR_ONLY) */
/* Function to pass device-status bits to DHD. */
extern uint32 bcmsdh_get_dstatus(void *sdh);
/* Function to return current window addr */
extern uint32 bcmsdh_cur_sbwad(void *sdh);
/* Function to pass chipid and rev to lower layers for controlling pr's */
extern void bcmsdh_chipinfo(void *sdh, uint32 chip, uint32 chiprev);
#ifdef BCMSPI
extern void bcmsdh_dwordmode(void *sdh, bool set);
#endif /* BCMSPI */
extern int bcmsdh_sleep(void *sdh, bool enab);
/* GPIO support */
extern int bcmsdh_gpio_init(void *sd);
extern bool bcmsdh_gpioin(void *sd, uint32 gpio);
extern int bcmsdh_gpioouten(void *sd, uint32 gpio);
extern int bcmsdh_gpioout(void *sd, uint32 gpio, bool enab);
#endif /* _bcmsdh_h_ */

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/*
* BCMSDH Function Driver for SDIO-Linux
*
* Copyright (C) 1999-2012, Broadcom Corporation
*
* Unless you and Broadcom execute a separate written software license
* agreement governing use of this software, this software is licensed to you
* under the terms of the GNU General Public License version 2 (the "GPL"),
* available at http://www.broadcom.com/licenses/GPLv2.php, with the
* following added to such license:
*
* As a special exception, the copyright holders of this software give you
* permission to link this software with independent modules, and to copy and
* distribute the resulting executable under terms of your choice, provided that
* you also meet, for each linked independent module, the terms and conditions of
* the license of that module. An independent module is a module which is not
* derived from this software. The special exception does not apply to any
* modifications of the software.
*
* Notwithstanding the above, under no circumstances may you combine this
* software in any way with any other Broadcom software provided under a license
* other than the GPL, without Broadcom's express prior written consent.
*
* $Id: bcmsdh_fd.h 241182 2011-02-17 21:50:03Z gmo $
*/
#ifndef __BCMSDH_FD_H__
#define __BCMSDH_FD_H__
#ifdef BCMDBG
#define sd_err(x) do { if (sd_msglevel & SDH_ERROR_VAL) printf x; } while (0)
#define sd_trace(x) do { if (sd_msglevel & SDH_TRACE_VAL) printf x; } while (0)
#define sd_info(x) do { if (sd_msglevel & SDH_INFO_VAL) printf x; } while (0)
#define sd_debug(x) do { if (sd_msglevel & SDH_DEBUG_VAL) printf x; } while (0)
#define sd_data(x) do { if (sd_msglevel & SDH_DATA_VAL) printf x; } while (0)
#define sd_ctrl(x) do { if (sd_msglevel & SDH_CTRL_VAL) printf x; } while (0)
#else
#define sd_err(x)
#define sd_trace(x)
#define sd_info(x)
#define sd_debug(x)
#define sd_data(x)
#define sd_ctrl(x)
#endif
#define sd_sync_dma(sd, read, nbytes)
#define sd_init_dma(sd)
#define sd_ack_intr(sd)
#define sd_wakeup(sd);
/* Allocate/init/free per-OS private data */
extern int sdiohfd_osinit(sdioh_info_t *sd);
extern void sdiohfd_osfree(sdioh_info_t *sd);
#ifdef BCMPERFSTATS
#define sd_log(x) do { if (sd_msglevel & SDH_LOG_VAL) bcmlog x; } while (0)
#else
#define sd_log(x)
#endif
#define SDIOH_ASSERT(exp) \
do { if (!(exp)) \
printf("!!!ASSERT fail: file %s lines %d", __FILE__, __LINE__); \
} while (0)
#define BLOCK_SIZE_4318 64
#define BLOCK_SIZE_4328 512
/* internal return code */
#define SUCCESS 0
#define ERROR 1
/* private bus modes */
#define SDIOH_MODE_SD4 2
#define CLIENT_INTR 0x100 /* Get rid of this! */
#define DMA_MAX_LEN (7*1024)
struct sdioh_info {
osl_t *osh; /* osh handler */
bool client_intr_enabled; /* interrupt connnected flag */
bool intr_handler_valid; /* client driver interrupt handler valid */
sdioh_cb_fn_t intr_handler; /* registered interrupt handler */
void *intr_handler_arg; /* argument to call interrupt handler */
uint16 intmask; /* Current active interrupts */
void *sdos_info; /* Pointer to per-OS private data */
uint irq; /* Client irq */
int intrcount; /* Client interrupts */
bool sd_use_dma; /* DMA on CMD53 */
bool sd_blockmode; /* sd_blockmode == FALSE => 64 Byte Cmd 53s. */
/* Must be on for sd_multiblock to be effective */
bool use_client_ints; /* If this is false, make sure to restore */
int sd_mode; /* SD1/SD4/SPI */
int client_block_size[SDIOD_MAX_IOFUNCS]; /* Blocksize */
uint8 num_funcs; /* Supported funcs on client */
uint32 com_cis_ptr;
uint32 func_cis_ptr[SDIOD_MAX_IOFUNCS];
uint max_dma_len;
uint max_dma_descriptors; /* DMA Descriptors supported by this controller. */
SDDMA_DESCRIPTOR SGList[32]; /* Scatter/Gather DMA List */
};
/************************************************************
* Internal interfaces: per-port references into bcmsdiohfd.c
*/
/* Global message bits */
extern uint sd_msglevel;
/* OS-independent interrupt handler */
extern bool check_client_intr(sdioh_info_t *sd);
/* Core interrupt enable/disable of device interrupts */
extern void sdiohfd_devintr_on(sdioh_info_t *sd);
extern void sdiohfd_devintr_off(sdioh_info_t *sd);
/**************************************************************
* Internal interfaces: bcmsdiohfd.c references to per-port code
*/
/* Register mapping routines */
extern uint32 *sdiohfd_reg_map(osl_t *osh, int32 addr, int size);
extern void sdiohfd_reg_unmap(osl_t *osh, int32 addr, int size);
/* Interrupt (de)registration routines */
extern int sdiohfd_register_irq(sdioh_info_t *sd, uint irq);
extern void sdiohfd_free_irq(uint irq, sdioh_info_t *sd);
typedef struct _BCMSDH_FD_INSTANCE {
PSDDEVICE pDevice[3]; /* bus driver's device we are supporting */
sdioh_info_t *sd;
SDIO_STATUS LastRequestStatus; /* last request status */
} BCMSDH_FD_INSTANCE, *PBCMSDH_FD_INSTANCE;
typedef struct _BCMSDH_FD_CONTEXT {
SDFUNCTION Function; /* function description for bus driver */
PBCMSDH_FD_INSTANCE pInstance;
SD_BUSCLOCK_RATE ClockOverride; /* clock rate override */
} BCMSDH_FD_CONTEXT, *PBCMSDH_FD_CONTEXT;
/* prototypes */
SDIO_STATUS client_init(PBCMSDH_FD_CONTEXT pFuncContext,
PBCMSDH_FD_INSTANCE pInstance,
PSDDEVICE pDevice);
void client_detach(PBCMSDH_FD_CONTEXT pFuncContext,
PBCMSDH_FD_INSTANCE pInstance);
#endif /* __BCMSDH_FD_H__ */

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/*
* BCMSDH Function Driver for the native SDIO/MMC driver in the Linux Kernel
*
* Copyright (C) 1999-2013, Broadcom Corporation
*
* Unless you and Broadcom execute a separate written software license
* agreement governing use of this software, this software is licensed to you
* under the terms of the GNU General Public License version 2 (the "GPL"),
* available at http://www.broadcom.com/licenses/GPLv2.php, with the
* following added to such license:
*
* As a special exception, the copyright holders of this software give you
* permission to link this software with independent modules, and to copy and
* distribute the resulting executable under terms of your choice, provided that
* you also meet, for each linked independent module, the terms and conditions of
* the license of that module. An independent module is a module which is not
* derived from this software. The special exception does not apply to any
* modifications of the software.
*
* Notwithstanding the above, under no circumstances may you combine this
* software in any way with any other Broadcom software provided under a license
* other than the GPL, without Broadcom's express prior written consent.
*
* $Id: bcmsdh_sdmmc.h 294363 2011-11-06 23:02:20Z $
*/
#ifndef __BCMSDH_SDMMC_H__
#define __BCMSDH_SDMMC_H__
#define sd_err(x)
#define sd_trace(x)
#define sd_info(x)
#define sd_debug(x)
#define sd_data(x)
#define sd_ctrl(x)
#define sd_sync_dma(sd, read, nbytes)
#define sd_init_dma(sd)
#define sd_ack_intr(sd)
#define sd_wakeup(sd);
/* Allocate/init/free per-OS private data */
extern int sdioh_sdmmc_osinit(sdioh_info_t *sd);
extern void sdioh_sdmmc_osfree(sdioh_info_t *sd);
#define sd_log(x)
#define SDIOH_ASSERT(exp) \
do { if (!(exp)) \
printf("!!!ASSERT fail: file %s lines %d", __FILE__, __LINE__); \
} while (0)
#define BLOCK_SIZE_4318 64
#define BLOCK_SIZE_4328 512
/* internal return code */
#define SUCCESS 0
#define ERROR 1
/* private bus modes */
#define SDIOH_MODE_SD4 2
#define CLIENT_INTR 0x100 /* Get rid of this! */
struct sdioh_info {
osl_t *osh; /* osh handler */
bool client_intr_enabled; /* interrupt connnected flag */
bool intr_handler_valid; /* client driver interrupt handler valid */
sdioh_cb_fn_t intr_handler; /* registered interrupt handler */
void *intr_handler_arg; /* argument to call interrupt handler */
uint16 intmask; /* Current active interrupts */
void *sdos_info; /* Pointer to per-OS private data */
uint irq; /* Client irq */
int intrcount; /* Client interrupts */
bool sd_use_dma; /* DMA on CMD53 */
bool sd_blockmode; /* sd_blockmode == FALSE => 64 Byte Cmd 53s. */
/* Must be on for sd_multiblock to be effective */
bool use_client_ints; /* If this is false, make sure to restore */
int sd_mode; /* SD1/SD4/SPI */
int client_block_size[SDIOD_MAX_IOFUNCS]; /* Blocksize */
uint8 num_funcs; /* Supported funcs on client */
uint32 com_cis_ptr;
uint32 func_cis_ptr[SDIOD_MAX_IOFUNCS];
uint max_dma_len;
uint max_dma_descriptors; /* DMA Descriptors supported by this controller. */
// SDDMA_DESCRIPTOR SGList[32]; /* Scatter/Gather DMA List */
};
/************************************************************
* Internal interfaces: per-port references into bcmsdh_sdmmc.c
*/
/* Global message bits */
extern uint sd_msglevel;
/* OS-independent interrupt handler */
extern bool check_client_intr(sdioh_info_t *sd);
/* Core interrupt enable/disable of device interrupts */
extern void sdioh_sdmmc_devintr_on(sdioh_info_t *sd);
extern void sdioh_sdmmc_devintr_off(sdioh_info_t *sd);
/**************************************************************
* Internal interfaces: bcmsdh_sdmmc.c references to per-port code
*/
/* Register mapping routines */
extern uint32 *sdioh_sdmmc_reg_map(osl_t *osh, int32 addr, int size);
extern void sdioh_sdmmc_reg_unmap(osl_t *osh, int32 addr, int size);
/* Interrupt (de)registration routines */
extern int sdioh_sdmmc_register_irq(sdioh_info_t *sd, uint irq);
extern void sdioh_sdmmc_free_irq(uint irq, sdioh_info_t *sd);
typedef struct _BCMSDH_SDMMC_INSTANCE {
sdioh_info_t *sd;
struct sdio_func *func[SDIOD_MAX_IOFUNCS];
} BCMSDH_SDMMC_INSTANCE, *PBCMSDH_SDMMC_INSTANCE;
#endif /* __BCMSDH_SDMMC_H__ */

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/*
* Broadcom SDIO/PCMCIA
* Software-specific definitions shared between device and host side
*
* $Copyright Open 2005 Broadcom Corporation$
*
* $Id: bcmsdpcm.h 314495 2012-02-12 07:56:39Z $
*/
#ifndef _bcmsdpcm_h_
#define _bcmsdpcm_h_
/*
* Software allocation of To SB Mailbox resources
*/
/* intstatus bits */
#define I_SMB_NAK I_SMB_SW0 /* To SB Mailbox Frame NAK */
#define I_SMB_INT_ACK I_SMB_SW1 /* To SB Mailbox Host Interrupt ACK */
#define I_SMB_USE_OOB I_SMB_SW2 /* To SB Mailbox Use OOB Wakeup */
#define I_SMB_DEV_INT I_SMB_SW3 /* To SB Mailbox Miscellaneous Interrupt */
#define I_TOSBMAIL (I_SMB_NAK | I_SMB_INT_ACK | I_SMB_USE_OOB | I_SMB_DEV_INT)
/* tosbmailbox bits corresponding to intstatus bits */
#define SMB_NAK (1 << 0) /* To SB Mailbox Frame NAK */
#define SMB_INT_ACK (1 << 1) /* To SB Mailbox Host Interrupt ACK */
#define SMB_USE_OOB (1 << 2) /* To SB Mailbox Use OOB Wakeup */
#define SMB_DEV_INT (1 << 3) /* To SB Mailbox Miscellaneous Interrupt */
#define SMB_MASK 0x0000000f /* To SB Mailbox Mask */
/* tosbmailboxdata */
#define SMB_DATA_VERSION_MASK 0x00ff0000 /* host protocol version (sent with F2 enable) */
#define SMB_DATA_VERSION_SHIFT 16 /* host protocol version (sent with F2 enable) */
/*
* Software allocation of To Host Mailbox resources
*/
/* intstatus bits */
#define I_HMB_FC_STATE I_HMB_SW0 /* To Host Mailbox Flow Control State */
#define I_HMB_FC_CHANGE I_HMB_SW1 /* To Host Mailbox Flow Control State Changed */
#define I_HMB_FRAME_IND I_HMB_SW2 /* To Host Mailbox Frame Indication */
#define I_HMB_HOST_INT I_HMB_SW3 /* To Host Mailbox Miscellaneous Interrupt */
#define I_TOHOSTMAIL (I_HMB_FC_CHANGE | I_HMB_FRAME_IND | I_HMB_HOST_INT)
/* tohostmailbox bits corresponding to intstatus bits */
#define HMB_FC_ON (1 << 0) /* To Host Mailbox Flow Control State */
#define HMB_FC_CHANGE (1 << 1) /* To Host Mailbox Flow Control State Changed */
#define HMB_FRAME_IND (1 << 2) /* To Host Mailbox Frame Indication */
#define HMB_HOST_INT (1 << 3) /* To Host Mailbox Miscellaneous Interrupt */
#define HMB_MASK 0x0000000f /* To Host Mailbox Mask */
/* tohostmailboxdata */
#define HMB_DATA_NAKHANDLED 0x01 /* we're ready to retransmit NAK'd frame to host */
#define HMB_DATA_DEVREADY 0x02 /* we're ready to to talk to host after enable */
#define HMB_DATA_FC 0x04 /* per prio flowcontrol update flag to host */
#define HMB_DATA_FWREADY 0x08 /* firmware is ready for protocol activity */
#define HMB_DATA_FWHALT 0x10 /* firmware has halted operation */
#define HMB_DATA_FCDATA_MASK 0xff000000 /* per prio flowcontrol data */
#define HMB_DATA_FCDATA_SHIFT 24 /* per prio flowcontrol data */
#define HMB_DATA_VERSION_MASK 0x00ff0000 /* device protocol version (with devready) */
#define HMB_DATA_VERSION_SHIFT 16 /* device protocol version (with devready) */
/*
* Software-defined protocol header
*/
/* Current protocol version */
#define SDPCM_PROT_VERSION 4
/* SW frame header */
#define SDPCM_SEQUENCE_MASK 0x000000ff /* Sequence Number Mask */
#define SDPCM_PACKET_SEQUENCE(p) (((uint8 *)p)[0] & 0xff) /* p starts w/SW Header */
#define SDPCM_CHANNEL_MASK 0x00000f00 /* Channel Number Mask */
#define SDPCM_CHANNEL_SHIFT 8 /* Channel Number Shift */
#define SDPCM_PACKET_CHANNEL(p) (((uint8 *)p)[1] & 0x0f) /* p starts w/SW Header */
#define SDPCM_FLAGS_MASK 0x0000f000 /* Mask of flag bits */
#define SDPCM_FLAGS_SHIFT 12 /* Flag bits shift */
#define SDPCM_PACKET_FLAGS(p) ((((uint8 *)p)[1] & 0xf0) >> 4) /* p starts w/SW Header */
/* Next Read Len: lookahead length of next frame, in 16-byte units (rounded up) */
#define SDPCM_NEXTLEN_MASK 0x00ff0000 /* Next Read Len Mask */
#define SDPCM_NEXTLEN_SHIFT 16 /* Next Read Len Shift */
#define SDPCM_NEXTLEN_VALUE(p) ((((uint8 *)p)[2] & 0xff) << 4) /* p starts w/SW Header */
#define SDPCM_NEXTLEN_OFFSET 2
/* Data Offset from SOF (HW Tag, SW Tag, Pad) */
#define SDPCM_DOFFSET_OFFSET 3 /* Data Offset */
#define SDPCM_DOFFSET_VALUE(p) (((uint8 *)p)[SDPCM_DOFFSET_OFFSET] & 0xff)
#define SDPCM_DOFFSET_MASK 0xff000000
#define SDPCM_DOFFSET_SHIFT 24
#define SDPCM_FCMASK_OFFSET 4 /* Flow control */
#define SDPCM_FCMASK_VALUE(p) (((uint8 *)p)[SDPCM_FCMASK_OFFSET ] & 0xff)
#define SDPCM_WINDOW_OFFSET 5 /* Credit based fc */
#define SDPCM_WINDOW_VALUE(p) (((uint8 *)p)[SDPCM_WINDOW_OFFSET] & 0xff)
#define SDPCM_VERSION_OFFSET 6 /* Version # */
#define SDPCM_VERSION_VALUE(p) (((uint8 *)p)[SDPCM_VERSION_OFFSET] & 0xff)
#define SDPCM_UNUSED_OFFSET 7 /* Spare */
#define SDPCM_UNUSED_VALUE(p) (((uint8 *)p)[SDPCM_UNUSED_OFFSET] & 0xff)
#define SDPCM_SWHEADER_LEN 8 /* SW header is 64 bits */
/* logical channel numbers */
#define SDPCM_CONTROL_CHANNEL 0 /* Control Request/Response Channel Id */
#define SDPCM_EVENT_CHANNEL 1 /* Asyc Event Indication Channel Id */
#define SDPCM_DATA_CHANNEL 2 /* Data Xmit/Recv Channel Id */
#define SDPCM_GLOM_CHANNEL 3 /* For coalesced packets (superframes) */
#define SDPCM_TEST_CHANNEL 15 /* Reserved for test/debug packets */
#define SDPCM_MAX_CHANNEL 15
#define SDPCM_SEQUENCE_WRAP 256 /* wrap-around val for eight-bit frame seq number */
#define SDPCM_FLAG_RESVD0 0x01
#define SDPCM_FLAG_RESVD1 0x02
#define SDPCM_FLAG_GSPI_TXENAB 0x04
#define SDPCM_FLAG_GLOMDESC 0x08 /* Superframe descriptor mask */
/* For GLOM_CHANNEL frames, use a flag to indicate descriptor frame */
#define SDPCM_GLOMDESC_FLAG (SDPCM_FLAG_GLOMDESC << SDPCM_FLAGS_SHIFT)
#define SDPCM_GLOMDESC(p) (((uint8 *)p)[1] & 0x80)
/* For TEST_CHANNEL packets, define another 4-byte header */
#define SDPCM_TEST_HDRLEN 4 /* Generally: Cmd(1), Ext(1), Len(2);
* Semantics of Ext byte depend on command.
* Len is current or requested frame length, not
* including test header; sent little-endian.
*/
#define SDPCM_TEST_DISCARD 0x01 /* Receiver discards. Ext is a pattern id. */
#define SDPCM_TEST_ECHOREQ 0x02 /* Echo request. Ext is a pattern id. */
#define SDPCM_TEST_ECHORSP 0x03 /* Echo response. Ext is a pattern id. */
#define SDPCM_TEST_BURST 0x04 /* Receiver to send a burst. Ext is a frame count */
#define SDPCM_TEST_SEND 0x05 /* Receiver sets send mode. Ext is boolean on/off */
/* Handy macro for filling in datagen packets with a pattern */
#define SDPCM_TEST_FILL(byteno, id) ((uint8)(id + byteno))
/*
* Software counters (first part matches hardware counters)
*/
typedef volatile struct {
uint32 cmd52rd; /* Cmd52RdCount, SDIO: cmd52 reads */
uint32 cmd52wr; /* Cmd52WrCount, SDIO: cmd52 writes */
uint32 cmd53rd; /* Cmd53RdCount, SDIO: cmd53 reads */
uint32 cmd53wr; /* Cmd53WrCount, SDIO: cmd53 writes */
uint32 abort; /* AbortCount, SDIO: aborts */
uint32 datacrcerror; /* DataCrcErrorCount, SDIO: frames w/CRC error */
uint32 rdoutofsync; /* RdOutOfSyncCount, SDIO/PCMCIA: Rd Frm out of sync */
uint32 wroutofsync; /* RdOutOfSyncCount, SDIO/PCMCIA: Wr Frm out of sync */
uint32 writebusy; /* WriteBusyCount, SDIO: device asserted "busy" */
uint32 readwait; /* ReadWaitCount, SDIO: no data ready for a read cmd */
uint32 readterm; /* ReadTermCount, SDIO: read frame termination cmds */
uint32 writeterm; /* WriteTermCount, SDIO: write frames termination cmds */
uint32 rxdescuflo; /* receive descriptor underflows */
uint32 rxfifooflo; /* receive fifo overflows */
uint32 txfifouflo; /* transmit fifo underflows */
uint32 runt; /* runt (too short) frames recv'd from bus */
uint32 badlen; /* frame's rxh len does not match its hw tag len */
uint32 badcksum; /* frame's hw tag chksum doesn't agree with len value */
uint32 seqbreak; /* break in sequence # space from one rx frame to the next */
uint32 rxfcrc; /* frame rx header indicates crc error */
uint32 rxfwoos; /* frame rx header indicates write out of sync */
uint32 rxfwft; /* frame rx header indicates write frame termination */
uint32 rxfabort; /* frame rx header indicates frame aborted */
uint32 woosint; /* write out of sync interrupt */
uint32 roosint; /* read out of sync interrupt */
uint32 rftermint; /* read frame terminate interrupt */
uint32 wftermint; /* write frame terminate interrupt */
} sdpcmd_cnt_t;
/*
* Register Access Macros
*/
#define SDIODREV_IS(var, val) ((var) == (val))
#define SDIODREV_GE(var, val) ((var) >= (val))
#define SDIODREV_GT(var, val) ((var) > (val))
#define SDIODREV_LT(var, val) ((var) < (val))
#define SDIODREV_LE(var, val) ((var) <= (val))
#define SDIODDMAREG32(h, dir, chnl) \
((dir) == DMA_TX ? \
(void *)(uintptr)&((h)->regs->dma.sdiod32.dma32regs[chnl].xmt) : \
(void *)(uintptr)&((h)->regs->dma.sdiod32.dma32regs[chnl].rcv))
#define SDIODDMAREG64(h, dir, chnl) \
((dir) == DMA_TX ? \
(void *)(uintptr)&((h)->regs->dma.sdiod64.dma64regs[chnl].xmt) : \
(void *)(uintptr)&((h)->regs->dma.sdiod64.dma64regs[chnl].rcv))
#define SDIODDMAREG(h, dir, chnl) \
(SDIODREV_LT((h)->corerev, 1) ? \
SDIODDMAREG32((h), (dir), (chnl)) : \
SDIODDMAREG64((h), (dir), (chnl)))
#define PCMDDMAREG(h, dir, chnl) \
((dir) == DMA_TX ? \
(void *)(uintptr)&((h)->regs->dma.pcm32.dmaregs.xmt) : \
(void *)(uintptr)&((h)->regs->dma.pcm32.dmaregs.rcv))
#define SDPCMDMAREG(h, dir, chnl, coreid) \
((coreid) == SDIOD_CORE_ID ? \
SDIODDMAREG(h, dir, chnl) : \
PCMDDMAREG(h, dir, chnl))
#define SDIODFIFOREG(h, corerev) \
(SDIODREV_LT((corerev), 1) ? \
((dma32diag_t *)(uintptr)&((h)->regs->dma.sdiod32.dmafifo)) : \
((dma32diag_t *)(uintptr)&((h)->regs->dma.sdiod64.dmafifo)))
#define PCMDFIFOREG(h) \
((dma32diag_t *)(uintptr)&((h)->regs->dma.pcm32.dmafifo))
#define SDPCMFIFOREG(h, coreid, corerev) \
((coreid) == SDIOD_CORE_ID ? \
SDIODFIFOREG(h, corerev) : \
PCMDFIFOREG(h))
/*
* Shared structure between dongle and the host.
* The structure contains pointers to trap or assert information.
*/
#define SDPCM_SHARED_VERSION 0x0001
#define SDPCM_SHARED_VERSION_MASK 0x00FF
#define SDPCM_SHARED_ASSERT_BUILT 0x0100
#define SDPCM_SHARED_ASSERT 0x0200
#define SDPCM_SHARED_TRAP 0x0400
#define SDPCM_SHARED_IN_BRPT 0x0800
#define SDPCM_SHARED_SET_BRPT 0x1000
#define SDPCM_SHARED_PENDING_BRPT 0x2000
typedef struct {
uint32 flags;
uint32 trap_addr;
uint32 assert_exp_addr;
uint32 assert_file_addr;
uint32 assert_line;
uint32 console_addr; /* Address of hndrte_cons_t */
uint32 msgtrace_addr;
uint32 fwid;
} sdpcm_shared_t;
extern sdpcm_shared_t sdpcm_shared;
/* Function can be used to notify host of FW halt */
extern void sdpcmd_fwhalt(void);
#endif /* _bcmsdpcm_h_ */

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/*
* SD-SPI Protocol Conversion - BCMSDH->SPI Translation Layer
*
* $ Copyright Open Broadcom Corporation $
*
* $Id: bcmsdspi.h 294363 2011-11-06 23:02:20Z $
*/
#ifndef _BCM_SD_SPI_H
#define _BCM_SD_SPI_H
/* global msglevel for debug messages - bitvals come from sdiovar.h */
#define sd_err(x)
#define sd_trace(x)
#define sd_info(x)
#define sd_debug(x)
#define sd_data(x)
#define sd_ctrl(x)
#define sd_log(x)
#define SDIOH_ASSERT(exp) \
do { if (!(exp)) \
printf("!!!ASSERT fail: file %s lines %d", __FILE__, __LINE__); \
} while (0)
#define BLOCK_SIZE_4318 64
#define BLOCK_SIZE_4328 512
/* internal return code */
#define SUCCESS 0
#undef ERROR
#define ERROR 1
/* private bus modes */
#define SDIOH_MODE_SPI 0
#define USE_BLOCKMODE 0x2 /* Block mode can be single block or multi */
#define USE_MULTIBLOCK 0x4
struct sdioh_info {
uint cfg_bar; /* pci cfg address for bar */
uint32 caps; /* cached value of capabilities reg */
uint bar0; /* BAR0 for PCI Device */
osl_t *osh; /* osh handler */
void *controller; /* Pointer to SPI Controller's private data struct */
uint lockcount; /* nest count of sdspi_lock() calls */
bool client_intr_enabled; /* interrupt connnected flag */
bool intr_handler_valid; /* client driver interrupt handler valid */
sdioh_cb_fn_t intr_handler; /* registered interrupt handler */
void *intr_handler_arg; /* argument to call interrupt handler */
bool initialized; /* card initialized */
uint32 target_dev; /* Target device ID */
uint32 intmask; /* Current active interrupts */
void *sdos_info; /* Pointer to per-OS private data */
uint32 controller_type; /* Host controller type */
uint8 version; /* Host Controller Spec Compliance Version */
uint irq; /* Client irq */
uint32 intrcount; /* Client interrupts */
uint32 local_intrcount; /* Controller interrupts */
bool host_init_done; /* Controller initted */
bool card_init_done; /* Client SDIO interface initted */
bool polled_mode; /* polling for command completion */
bool sd_use_dma; /* DMA on CMD53 */
bool sd_blockmode; /* sd_blockmode == FALSE => 64 Byte Cmd 53s. */
/* Must be on for sd_multiblock to be effective */
bool use_client_ints; /* If this is false, make sure to restore */
bool got_hcint; /* Host Controller interrupt. */
/* polling hack in wl_linux.c:wl_timer() */
int adapter_slot; /* Maybe dealing with multiple slots/controllers */
int sd_mode; /* SD1/SD4/SPI */
int client_block_size[SDIOD_MAX_IOFUNCS]; /* Blocksize */
uint32 data_xfer_count; /* Current register transfer size */
uint32 cmd53_wr_data; /* Used to pass CMD53 write data */
uint32 card_response; /* Used to pass back response status byte */
uint32 card_rsp_data; /* Used to pass back response data word */
uint16 card_rca; /* Current Address */
uint8 num_funcs; /* Supported funcs on client */
uint32 com_cis_ptr;
uint32 func_cis_ptr[SDIOD_MAX_IOFUNCS];
void *dma_buf;
ulong dma_phys;
int r_cnt; /* rx count */
int t_cnt; /* tx_count */
};
/************************************************************
* Internal interfaces: per-port references into bcmsdspi.c
*/
/* Global message bits */
extern uint sd_msglevel;
/**************************************************************
* Internal interfaces: bcmsdspi.c references to per-port code
*/
/* Register mapping routines */
extern uint32 *spi_reg_map(osl_t *osh, uintptr addr, int size);
extern void spi_reg_unmap(osl_t *osh, uintptr addr, int size);
/* Interrupt (de)registration routines */
extern int spi_register_irq(sdioh_info_t *sd, uint irq);
extern void spi_free_irq(uint irq, sdioh_info_t *sd);
/* OS-specific interrupt wrappers (atomic interrupt enable/disable) */
extern void spi_lock(sdioh_info_t *sd);
extern void spi_unlock(sdioh_info_t *sd);
/* Allocate/init/free per-OS private data */
extern int spi_osinit(sdioh_info_t *sd);
extern void spi_osfree(sdioh_info_t *sd);
#endif /* _BCM_SD_SPI_H */

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/*
* 'Standard' SDIO HOST CONTROLLER driver
*
* $ Copyright Open Broadcom Corporation $
*
* $Id: bcmsdstd.h 324979 2012-03-30 23:47:19Z $
*/
#ifndef _BCM_SD_STD_H
#define _BCM_SD_STD_H
/* global msglevel for debug messages - bitvals come from sdiovar.h */
#define sd_err(x) do { if (sd_msglevel & SDH_ERROR_VAL) printf x; } while (0)
#define sd_trace(x)
#define sd_info(x)
#define sd_debug(x)
#define sd_data(x)
#define sd_ctrl(x)
#define sd_dma(x)
#define sd_sync_dma(sd, read, nbytes)
#define sd_init_dma(sd)
#define sd_ack_intr(sd)
#define sd_wakeup(sd);
/* Allocate/init/free per-OS private data */
extern int sdstd_osinit(sdioh_info_t *sd);
extern void sdstd_osfree(sdioh_info_t *sd);
#define sd_log(x)
#define SDIOH_ASSERT(exp) \
do { if (!(exp)) \
printf("!!!ASSERT fail: file %s lines %d", __FILE__, __LINE__); \
} while (0)
#define BLOCK_SIZE_4318 64
#define BLOCK_SIZE_4328 512
/* internal return code */
#define SUCCESS 0
#define ERROR 1
/* private bus modes */
#define SDIOH_MODE_SPI 0
#define SDIOH_MODE_SD1 1
#define SDIOH_MODE_SD4 2
#define MAX_SLOTS 6 /* For PCI: Only 6 BAR entries => 6 slots */
#define SDIOH_REG_WINSZ 0x100 /* Number of registers in Standard Host Controller */
#define SDIOH_TYPE_ARASAN_HDK 1
#define SDIOH_TYPE_BCM27XX 2
#define SDIOH_TYPE_TI_PCIXX21 4 /* TI PCIxx21 Standard Host Controller */
#define SDIOH_TYPE_RICOH_R5C822 5 /* Ricoh Co Ltd R5C822 SD/SDIO/MMC/MS/MSPro Host Adapter */
#define SDIOH_TYPE_JMICRON 6 /* JMicron Standard SDIO Host Controller */
/* For linux, allow yielding for dongle */
#define BCMSDYIELD
/* Expected card status value for CMD7 */
#define SDIOH_CMD7_EXP_STATUS 0x00001E00
#define RETRIES_LARGE 100000
#define sdstd_os_yield(sd) do {} while (0)
#define RETRIES_SMALL 100
#define USE_BLOCKMODE 0x2 /* Block mode can be single block or multi */
#define USE_MULTIBLOCK 0x4
#define USE_FIFO 0x8 /* Fifo vs non-fifo */
#define CLIENT_INTR 0x100 /* Get rid of this! */
#define HC_INTR_RETUNING 0x1000
struct sdioh_info {
uint cfg_bar; /* pci cfg address for bar */
uint32 caps; /* cached value of capabilities reg */
uint32 curr_caps; /* max current capabilities reg */
osl_t *osh; /* osh handler */
volatile char *mem_space; /* pci device memory va */
uint lockcount; /* nest count of sdstd_lock() calls */
bool client_intr_enabled; /* interrupt connnected flag */
bool intr_handler_valid; /* client driver interrupt handler valid */
sdioh_cb_fn_t intr_handler; /* registered interrupt handler */
void *intr_handler_arg; /* argument to call interrupt handler */
bool initialized; /* card initialized */
uint target_dev; /* Target device ID */
uint16 intmask; /* Current active interrupts */
void *sdos_info; /* Pointer to per-OS private data */
uint32 controller_type; /* Host controller type */
uint8 version; /* Host Controller Spec Compliance Version */
uint irq; /* Client irq */
int intrcount; /* Client interrupts */
int local_intrcount; /* Controller interrupts */
bool host_init_done; /* Controller initted */
bool card_init_done; /* Client SDIO interface initted */
bool polled_mode; /* polling for command completion */
bool sd_blockmode; /* sd_blockmode == FALSE => 64 Byte Cmd 53s. */
/* Must be on for sd_multiblock to be effective */
bool use_client_ints; /* If this is false, make sure to restore */
/* polling hack in wl_linux.c:wl_timer() */
int adapter_slot; /* Maybe dealing with multiple slots/controllers */
int sd_mode; /* SD1/SD4/SPI */
int client_block_size[SDIOD_MAX_IOFUNCS]; /* Blocksize */
uint32 data_xfer_count; /* Current transfer */
uint16 card_rca; /* Current Address */
int8 sd_dma_mode; /* DMA Mode (PIO, SDMA, ... ADMA2) on CMD53 */
uint8 num_funcs; /* Supported funcs on client */
uint32 com_cis_ptr;
uint32 func_cis_ptr[SDIOD_MAX_FUNCS];
void *dma_buf; /* DMA Buffer virtual address */
ulong dma_phys; /* DMA Buffer physical address */
void *adma2_dscr_buf; /* ADMA2 Descriptor Buffer virtual address */
ulong adma2_dscr_phys; /* ADMA2 Descriptor Buffer physical address */
/* adjustments needed to make the dma align properly */
void *dma_start_buf;
ulong dma_start_phys;
uint alloced_dma_size;
void *adma2_dscr_start_buf;
ulong adma2_dscr_start_phys;
uint alloced_adma2_dscr_size;
int r_cnt; /* rx count */
int t_cnt; /* tx_count */
bool got_hcint; /* local interrupt flag */
uint16 last_intrstatus; /* to cache intrstatus */
int host_UHSISupported; /* whether UHSI is supported for HC. */
int card_UHSI_voltage_Supported; /* whether UHSI is supported for
* Card in terms of Voltage [1.8 or 3.3].
*/
int global_UHSI_Supp; /* type of UHSI support in both host and card.
* HOST_SDR_UNSUPP: capabilities not supported/matched
* HOST_SDR_12_25: SDR12 and SDR25 supported
* HOST_SDR_50_104_DDR: one of SDR50/SDR104 or DDR50 supptd
*/
volatile int sd3_dat_state; /* data transfer state used for retuning check */
volatile int sd3_tun_state; /* tuning state used for retuning check */
bool sd3_tuning_reqd; /* tuning requirement parameter */
uint32 caps3; /* cached value of 32 MSbits capabilities reg (SDIO 3.0) */
};
#define DMA_MODE_NONE 0
#define DMA_MODE_SDMA 1
#define DMA_MODE_ADMA1 2
#define DMA_MODE_ADMA2 3
#define DMA_MODE_ADMA2_64 4
#define DMA_MODE_AUTO -1
#define USE_DMA(sd) ((bool)((sd->sd_dma_mode > 0) ? TRUE : FALSE))
/* States for Tuning and corr data */
#define TUNING_IDLE 0
#define TUNING_START 1
#define TUNING_START_AFTER_DAT 2
#define TUNING_ONGOING 3
#define DATA_TRANSFER_IDLE 0
#define DATA_TRANSFER_ONGOING 1
#define CHECK_TUNING_PRE_DATA 1
#define CHECK_TUNING_POST_DATA 2
/************************************************************
* Internal interfaces: per-port references into bcmsdstd.c
*/
/* Global message bits */
extern uint sd_msglevel;
/* OS-independent interrupt handler */
extern bool check_client_intr(sdioh_info_t *sd);
/* Core interrupt enable/disable of device interrupts */
extern void sdstd_devintr_on(sdioh_info_t *sd);
extern void sdstd_devintr_off(sdioh_info_t *sd);
/* Enable/disable interrupts for local controller events */
extern void sdstd_intrs_on(sdioh_info_t *sd, uint16 norm, uint16 err);
extern void sdstd_intrs_off(sdioh_info_t *sd, uint16 norm, uint16 err);
/* Wait for specified interrupt and error bits to be set */
extern void sdstd_spinbits(sdioh_info_t *sd, uint16 norm, uint16 err);
/**************************************************************
* Internal interfaces: bcmsdstd.c references to per-port code
*/
/* Register mapping routines */
extern uint32 *sdstd_reg_map(osl_t *osh, int32 addr, int size);
extern void sdstd_reg_unmap(osl_t *osh, int32 addr, int size);
/* Interrupt (de)registration routines */
extern int sdstd_register_irq(sdioh_info_t *sd, uint irq);
extern void sdstd_free_irq(uint irq, sdioh_info_t *sd);
/* OS-specific interrupt wrappers (atomic interrupt enable/disable) */
extern void sdstd_lock(sdioh_info_t *sd);
extern void sdstd_unlock(sdioh_info_t *sd);
extern void sdstd_waitlockfree(sdioh_info_t *sd);
/* OS-specific wait-for-interrupt-or-status */
extern int sdstd_waitbits(sdioh_info_t *sd, uint16 norm, uint16 err, bool yield, uint16 *bits);
/* used by bcmsdstd_linux [implemented in sdstd] */
extern void sdstd_3_enable_retuning_int(sdioh_info_t *sd);
extern void sdstd_3_disable_retuning_int(sdioh_info_t *sd);
extern bool sdstd_3_is_retuning_int_set(sdioh_info_t *sd);
extern void sdstd_3_check_and_do_tuning(sdioh_info_t *sd, int tuning_param);
extern bool sdstd_3_check_and_set_retuning(sdioh_info_t *sd);
extern int sdstd_3_get_tune_state(sdioh_info_t *sd);
extern int sdstd_3_get_data_state(sdioh_info_t *sd);
extern void sdstd_3_set_tune_state(sdioh_info_t *sd, int state);
extern void sdstd_3_set_data_state(sdioh_info_t *sd, int state);
extern uint8 sdstd_3_get_tuning_exp(sdioh_info_t *sd);
extern uint32 sdstd_3_get_uhsi_clkmode(sdioh_info_t *sd);
extern int sdstd_3_clk_tuning(sdioh_info_t *sd, uint32 sd3ClkMode);
/* used by sdstd [implemented in bcmsdstd_linux/ndis] */
extern void sdstd_3_start_tuning(sdioh_info_t *sd);
extern void sdstd_3_osinit_tuning(sdioh_info_t *sd);
extern void sdstd_3_osclean_tuning(sdioh_info_t *sd);
#endif /* _BCM_SD_STD_H */

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/*
* Broadcom SPI Low-Level Hardware Driver API
*
* $ Copyright Open Broadcom Corporation $
*
* $Id: bcmspi.h 241182 2011-02-17 21:50:03Z $
*/
#ifndef _BCM_SPI_H
#define _BCM_SPI_H
extern void spi_devintr_off(sdioh_info_t *sd);
extern void spi_devintr_on(sdioh_info_t *sd);
extern bool spi_start_clock(sdioh_info_t *sd, uint16 new_sd_divisor);
extern bool spi_controller_highspeed_mode(sdioh_info_t *sd, bool hsmode);
extern bool spi_check_client_intr(sdioh_info_t *sd, int *is_dev_intr);
extern bool spi_hw_attach(sdioh_info_t *sd);
extern bool spi_hw_detach(sdioh_info_t *sd);
extern void spi_sendrecv(sdioh_info_t *sd, uint8 *msg_out, uint8 *msg_in, int msglen);
extern void spi_spinbits(sdioh_info_t *sd);
extern void spi_waitbits(sdioh_info_t *sd, bool yield);
#endif /* _BCM_SPI_H */

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/*
* SD-SPI Protocol Conversion - BCMSDH->gSPI Translation Layer
*
* Copyright (C) 2013, Broadcom Corporation
* All Rights Reserved.
*
* This is UNPUBLISHED PROPRIETARY SOURCE CODE of Broadcom Corporation;
* the contents of this file may not be disclosed to third parties, copied
* or duplicated in any form, in whole or in part, without the prior
* written permission of Broadcom Corporation.
*
* $Id: bcmspibrcm.h 241182 2011-02-17 21:50:03Z $
*/
#ifndef _BCM_SPI_BRCM_H
#define _BCM_SPI_BRCM_H
/* global msglevel for debug messages - bitvals come from sdiovar.h */
#define sd_err(x)
#define sd_trace(x)
#define sd_info(x)
#define sd_debug(x)
#define sd_data(x)
#define sd_ctrl(x)
#define sd_log(x)
#define SDIOH_ASSERT(exp) \
do { if (!(exp)) \
printf("!!!ASSERT fail: file %s lines %d", __FILE__, __LINE__); \
} while (0)
#define BLOCK_SIZE_F1 64
#define BLOCK_SIZE_F2 2048
#define BLOCK_SIZE_F3 2048
/* internal return code */
#define SUCCESS 0
#undef ERROR
#define ERROR 1
#define ERROR_UF 2
#define ERROR_OF 3
/* private bus modes */
#define SDIOH_MODE_SPI 0
#define USE_BLOCKMODE 0x2 /* Block mode can be single block or multi */
#define USE_MULTIBLOCK 0x4
struct sdioh_info {
uint cfg_bar; /* pci cfg address for bar */
uint32 caps; /* cached value of capabilities reg */
void *bar0; /* BAR0 for PCI Device */
osl_t *osh; /* osh handler */
void *controller; /* Pointer to SPI Controller's private data struct */
uint lockcount; /* nest count of spi_lock() calls */
bool client_intr_enabled; /* interrupt connnected flag */
bool intr_handler_valid; /* client driver interrupt handler valid */
sdioh_cb_fn_t intr_handler; /* registered interrupt handler */
void *intr_handler_arg; /* argument to call interrupt handler */
bool initialized; /* card initialized */
uint32 target_dev; /* Target device ID */
uint32 intmask; /* Current active interrupts */
void *sdos_info; /* Pointer to per-OS private data */
uint32 controller_type; /* Host controller type */
uint8 version; /* Host Controller Spec Compliance Version */
uint irq; /* Client irq */
uint32 intrcount; /* Client interrupts */
uint32 local_intrcount; /* Controller interrupts */
bool host_init_done; /* Controller initted */
bool card_init_done; /* Client SDIO interface initted */
bool polled_mode; /* polling for command completion */
bool sd_use_dma; /* DMA on CMD53 */
bool sd_blockmode; /* sd_blockmode == FALSE => 64 Byte Cmd 53s. */
/* Must be on for sd_multiblock to be effective */
bool use_client_ints; /* If this is false, make sure to restore */
/* polling hack in wl_linux.c:wl_timer() */
int adapter_slot; /* Maybe dealing with multiple slots/controllers */
int sd_mode; /* SD1/SD4/SPI */
int client_block_size[SPI_MAX_IOFUNCS]; /* Blocksize */
uint32 data_xfer_count; /* Current transfer */
uint16 card_rca; /* Current Address */
uint8 num_funcs; /* Supported funcs on client */
uint32 card_dstatus; /* 32bit device status */
uint32 com_cis_ptr;
uint32 func_cis_ptr[SPI_MAX_IOFUNCS];
void *dma_buf;
ulong dma_phys;
int r_cnt; /* rx count */
int t_cnt; /* tx_count */
uint32 wordlen; /* host processor 16/32bits */
uint32 prev_fun;
uint32 chip;
uint32 chiprev;
bool resp_delay_all;
bool dwordmode;
bool resp_delay_new;
struct spierrstats_t spierrstats;
};
/************************************************************
* Internal interfaces: per-port references into bcmspibrcm.c
*/
/* Global message bits */
extern uint sd_msglevel;
/**************************************************************
* Internal interfaces: bcmspibrcm.c references to per-port code
*/
/* Interrupt (de)registration routines */
extern int spi_register_irq(sdioh_info_t *sd, uint irq);
extern void spi_free_irq(uint irq, sdioh_info_t *sd);
/* OS-specific interrupt wrappers (atomic interrupt enable/disable) */
extern void spi_lock(sdioh_info_t *sd);
extern void spi_unlock(sdioh_info_t *sd);
/* Allocate/init/free per-OS private data */
extern int spi_osinit(sdioh_info_t *sd);
extern void spi_osfree(sdioh_info_t *sd);
#define SPI_RW_FLAG_M BITFIELD_MASK(1) /* Bit [31] - R/W Command Bit */
#define SPI_RW_FLAG_S 31
#define SPI_ACCESS_M BITFIELD_MASK(1) /* Bit [30] - Fixed/Incr Access */
#define SPI_ACCESS_S 30
#define SPI_FUNCTION_M BITFIELD_MASK(2) /* Bit [29:28] - Function Number */
#define SPI_FUNCTION_S 28
#define SPI_REG_ADDR_M BITFIELD_MASK(17) /* Bit [27:11] - Address */
#define SPI_REG_ADDR_S 11
#define SPI_LEN_M BITFIELD_MASK(11) /* Bit [10:0] - Packet length */
#define SPI_LEN_S 0
#endif /* _BCM_SPI_BRCM_H */

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/*
* Misc useful routines to access NIC local SROM/OTP .
*
* $Copyright Open Broadcom Corporation$
*
* $Id: bcmsrom.h 241182 2011-02-17 21:50:03Z gmo $
*/
#ifndef _bcmsrom_h_
#define _bcmsrom_h_
#include <bcmsrom_fmt.h>
/* Prototypes */
extern int srom_var_init(si_t *sih, uint bus, void *curmap, osl_t *osh,
char **vars, uint *count);
extern void srom_var_deinit(si_t *sih);
extern int srom_read(si_t *sih, uint bus, void *curmap, osl_t *osh,
uint byteoff, uint nbytes, uint16 *buf,
bool check_crc);
extern int srom_write(si_t *sih, uint bus, void *curmap, osl_t *osh,
uint byteoff, uint nbytes, uint16 *buf);
extern int srom_otp_cisrwvar(si_t *sih, osl_t *osh, char *vars, int *count);
extern int srom_otp_write_region_crc(si_t *sih, uint nbytes, uint16* buf16, bool write);
/* parse standard PCMCIA cis, normally used by SB/PCMCIA/SDIO/SPI/OTP
* and extract from it into name=value pairs
*/
extern int srom_parsecis(osl_t *osh, uint8 **pcis, uint ciscnt,
char **vars, uint *count);
#endif /* _bcmsrom_h_ */

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/*
* SROM format definition.
*
* $Copyright Open Broadcom Corporation$
*
* $Id: bcmsrom_fmt.h 401759 2013-05-13 16:08:08Z sudhirbs $
*/
#ifndef _bcmsrom_fmt_h_
#define _bcmsrom_fmt_h_
#define SROM_MAXREV 11 /* max revisiton supported by driver */
/* Maximum srom: 6 Kilobits == 768 bytes */
#define SROM_MAX 768
#define SROM_MAXW 384
#define VARS_MAX 4096
/* PCI fields */
#define PCI_F0DEVID 48
/* SROM Rev 2: 1 Kilobit map for 11a/b/g devices.
* SROM Rev 3: Upward compatible modification for lpphy and PCIe
* hardware workaround.
*/
#define SROM_WORDS 64
#define SROM3_SWRGN_OFF 28 /* s/w region offset in words */
#define SROM_SSID 2
#define SROM_SVID 3
#define SROM_WL1LHMAXP 29
#define SROM_WL1LPAB0 30
#define SROM_WL1LPAB1 31
#define SROM_WL1LPAB2 32
#define SROM_WL1HPAB0 33
#define SROM_WL1HPAB1 34
#define SROM_WL1HPAB2 35
#define SROM_MACHI_IL0 36
#define SROM_MACMID_IL0 37
#define SROM_MACLO_IL0 38
#define SROM_MACHI_ET0 39
#define SROM_MACMID_ET0 40
#define SROM_MACLO_ET0 41
#define SROM_MACHI_ET1 42
#define SROM_MACMID_ET1 43
#define SROM_MACLO_ET1 44
#define SROM3_MACHI 37
#define SROM3_MACMID 38
#define SROM3_MACLO 39
#define SROM_BXARSSI2G 40
#define SROM_BXARSSI5G 41
#define SROM_TRI52G 42
#define SROM_TRI5GHL 43
#define SROM_RXPO52G 45
#define SROM2_ENETPHY 45
#define SROM_AABREV 46
/* Fields in AABREV */
#define SROM_BR_MASK 0x00ff
#define SROM_CC_MASK 0x0f00
#define SROM_CC_SHIFT 8
#define SROM_AA0_MASK 0x3000
#define SROM_AA0_SHIFT 12
#define SROM_AA1_MASK 0xc000
#define SROM_AA1_SHIFT 14
#define SROM_WL0PAB0 47
#define SROM_WL0PAB1 48
#define SROM_WL0PAB2 49
#define SROM_LEDBH10 50
#define SROM_LEDBH32 51
#define SROM_WL10MAXP 52
#define SROM_WL1PAB0 53
#define SROM_WL1PAB1 54
#define SROM_WL1PAB2 55
#define SROM_ITT 56
#define SROM_BFL 57
#define SROM_BFL2 28
#define SROM3_BFL2 61
#define SROM_AG10 58
#define SROM_CCODE 59
#define SROM_OPO 60
#define SROM3_LEDDC 62
#define SROM_CRCREV 63
/* SROM Rev 4: Reallocate the software part of the srom to accomodate
* MIMO features. It assumes up to two PCIE functions and 440 bytes
* of useable srom i.e. the useable storage in chips with OTP that
* implements hardware redundancy.
*/
#define SROM4_WORDS 220
#define SROM4_SIGN 32
#define SROM4_SIGNATURE 0x5372
#define SROM4_BREV 33
#define SROM4_BFL0 34
#define SROM4_BFL1 35
#define SROM4_BFL2 36
#define SROM4_BFL3 37
#define SROM5_BFL0 37
#define SROM5_BFL1 38
#define SROM5_BFL2 39
#define SROM5_BFL3 40
#define SROM4_MACHI 38
#define SROM4_MACMID 39
#define SROM4_MACLO 40
#define SROM5_MACHI 41
#define SROM5_MACMID 42
#define SROM5_MACLO 43
#define SROM4_CCODE 41
#define SROM4_REGREV 42
#define SROM5_CCODE 34
#define SROM5_REGREV 35
#define SROM4_LEDBH10 43
#define SROM4_LEDBH32 44
#define SROM5_LEDBH10 59
#define SROM5_LEDBH32 60
#define SROM4_LEDDC 45
#define SROM5_LEDDC 45
#define SROM4_AA 46
#define SROM4_AA2G_MASK 0x00ff
#define SROM4_AA2G_SHIFT 0
#define SROM4_AA5G_MASK 0xff00
#define SROM4_AA5G_SHIFT 8
#define SROM4_AG10 47
#define SROM4_AG32 48
#define SROM4_TXPID2G 49
#define SROM4_TXPID5G 51
#define SROM4_TXPID5GL 53
#define SROM4_TXPID5GH 55
#define SROM4_TXRXC 61
#define SROM4_TXCHAIN_MASK 0x000f
#define SROM4_TXCHAIN_SHIFT 0
#define SROM4_RXCHAIN_MASK 0x00f0
#define SROM4_RXCHAIN_SHIFT 4
#define SROM4_SWITCH_MASK 0xff00
#define SROM4_SWITCH_SHIFT 8
/* Per-path fields */
#define MAX_PATH_SROM 4
#define SROM4_PATH0 64
#define SROM4_PATH1 87
#define SROM4_PATH2 110
#define SROM4_PATH3 133
#define SROM4_2G_ITT_MAXP 0
#define SROM4_2G_PA 1
#define SROM4_5G_ITT_MAXP 5
#define SROM4_5GLH_MAXP 6
#define SROM4_5G_PA 7
#define SROM4_5GL_PA 11
#define SROM4_5GH_PA 15
/* Fields in the ITT_MAXP and 5GLH_MAXP words */
#define B2G_MAXP_MASK 0xff
#define B2G_ITT_SHIFT 8
#define B5G_MAXP_MASK 0xff
#define B5G_ITT_SHIFT 8
#define B5GH_MAXP_MASK 0xff
#define B5GL_MAXP_SHIFT 8
/* All the miriad power offsets */
#define SROM4_2G_CCKPO 156
#define SROM4_2G_OFDMPO 157
#define SROM4_5G_OFDMPO 159
#define SROM4_5GL_OFDMPO 161
#define SROM4_5GH_OFDMPO 163
#define SROM4_2G_MCSPO 165
#define SROM4_5G_MCSPO 173
#define SROM4_5GL_MCSPO 181
#define SROM4_5GH_MCSPO 189
#define SROM4_CDDPO 197
#define SROM4_STBCPO 198
#define SROM4_BW40PO 199
#define SROM4_BWDUPPO 200
#define SROM4_CRCREV 219
/* SROM Rev 8: Make space for a 48word hardware header for PCIe rev >= 6.
* This is acombined srom for both MIMO and SISO boards, usable in
* the .130 4Kilobit OTP with hardware redundancy.
*/
#define SROM8_SIGN 64
#define SROM8_BREV 65
#define SROM8_BFL0 66
#define SROM8_BFL1 67
#define SROM8_BFL2 68
#define SROM8_BFL3 69
#define SROM8_MACHI 70
#define SROM8_MACMID 71
#define SROM8_MACLO 72
#define SROM8_CCODE 73
#define SROM8_REGREV 74
#define SROM8_LEDBH10 75
#define SROM8_LEDBH32 76
#define SROM8_LEDDC 77
#define SROM8_AA 78
#define SROM8_AG10 79
#define SROM8_AG32 80
#define SROM8_TXRXC 81
#define SROM8_BXARSSI2G 82
#define SROM8_BXARSSI5G 83
#define SROM8_TRI52G 84
#define SROM8_TRI5GHL 85
#define SROM8_RXPO52G 86
#define SROM8_FEM2G 87
#define SROM8_FEM5G 88
#define SROM8_FEM_ANTSWLUT_MASK 0xf800
#define SROM8_FEM_ANTSWLUT_SHIFT 11
#define SROM8_FEM_TR_ISO_MASK 0x0700
#define SROM8_FEM_TR_ISO_SHIFT 8
#define SROM8_FEM_PDET_RANGE_MASK 0x00f8
#define SROM8_FEM_PDET_RANGE_SHIFT 3
#define SROM8_FEM_EXTPA_GAIN_MASK 0x0006
#define SROM8_FEM_EXTPA_GAIN_SHIFT 1
#define SROM8_FEM_TSSIPOS_MASK 0x0001
#define SROM8_FEM_TSSIPOS_SHIFT 0
#define SROM8_THERMAL 89
/* Temp sense related entries */
#define SROM8_MPWR_RAWTS 90
#define SROM8_TS_SLP_OPT_CORRX 91
/* FOC: freiquency offset correction, HWIQ: H/W IOCAL enable, IQSWP: IQ CAL swap disable */
#define SROM8_FOC_HWIQ_IQSWP 92
#define SROM8_EXTLNAGAIN 93
/* Temperature delta for PHY calibration */
#define SROM8_PHYCAL_TEMPDELTA 94
/* Measured power 1 & 2, 0-13 bits at offset 95, MSB 2 bits are unused for now. */
#define SROM8_MPWR_1_AND_2 95
/* Per-path offsets & fields */
#define SROM8_PATH0 96
#define SROM8_PATH1 112
#define SROM8_PATH2 128
#define SROM8_PATH3 144
#define SROM8_2G_ITT_MAXP 0
#define SROM8_2G_PA 1
#define SROM8_5G_ITT_MAXP 4
#define SROM8_5GLH_MAXP 5
#define SROM8_5G_PA 6
#define SROM8_5GL_PA 9
#define SROM8_5GH_PA 12
/* All the miriad power offsets */
#define SROM8_2G_CCKPO 160
#define SROM8_2G_OFDMPO 161
#define SROM8_5G_OFDMPO 163
#define SROM8_5GL_OFDMPO 165
#define SROM8_5GH_OFDMPO 167
#define SROM8_2G_MCSPO 169
#define SROM8_5G_MCSPO 177
#define SROM8_5GL_MCSPO 185
#define SROM8_5GH_MCSPO 193
#define SROM8_CDDPO 201
#define SROM8_STBCPO 202
#define SROM8_BW40PO 203
#define SROM8_BWDUPPO 204
/* SISO PA parameters are in the path0 spaces */
#define SROM8_SISO 96
/* Legacy names for SISO PA paramters */
#define SROM8_W0_ITTMAXP (SROM8_SISO + SROM8_2G_ITT_MAXP)
#define SROM8_W0_PAB0 (SROM8_SISO + SROM8_2G_PA)
#define SROM8_W0_PAB1 (SROM8_SISO + SROM8_2G_PA + 1)
#define SROM8_W0_PAB2 (SROM8_SISO + SROM8_2G_PA + 2)
#define SROM8_W1_ITTMAXP (SROM8_SISO + SROM8_5G_ITT_MAXP)
#define SROM8_W1_MAXP_LCHC (SROM8_SISO + SROM8_5GLH_MAXP)
#define SROM8_W1_PAB0 (SROM8_SISO + SROM8_5G_PA)
#define SROM8_W1_PAB1 (SROM8_SISO + SROM8_5G_PA + 1)
#define SROM8_W1_PAB2 (SROM8_SISO + SROM8_5G_PA + 2)
#define SROM8_W1_PAB0_LC (SROM8_SISO + SROM8_5GL_PA)
#define SROM8_W1_PAB1_LC (SROM8_SISO + SROM8_5GL_PA + 1)
#define SROM8_W1_PAB2_LC (SROM8_SISO + SROM8_5GL_PA + 2)
#define SROM8_W1_PAB0_HC (SROM8_SISO + SROM8_5GH_PA)
#define SROM8_W1_PAB1_HC (SROM8_SISO + SROM8_5GH_PA + 1)
#define SROM8_W1_PAB2_HC (SROM8_SISO + SROM8_5GH_PA + 2)
#define SROM8_CRCREV 219
/* SROM REV 9 */
#define SROM9_2GPO_CCKBW20 160
#define SROM9_2GPO_CCKBW20UL 161
#define SROM9_2GPO_LOFDMBW20 162
#define SROM9_2GPO_LOFDMBW20UL 164
#define SROM9_5GLPO_LOFDMBW20 166
#define SROM9_5GLPO_LOFDMBW20UL 168
#define SROM9_5GMPO_LOFDMBW20 170
#define SROM9_5GMPO_LOFDMBW20UL 172
#define SROM9_5GHPO_LOFDMBW20 174
#define SROM9_5GHPO_LOFDMBW20UL 176
#define SROM9_2GPO_MCSBW20 178
#define SROM9_2GPO_MCSBW20UL 180
#define SROM9_2GPO_MCSBW40 182
#define SROM9_5GLPO_MCSBW20 184
#define SROM9_5GLPO_MCSBW20UL 186
#define SROM9_5GLPO_MCSBW40 188
#define SROM9_5GMPO_MCSBW20 190
#define SROM9_5GMPO_MCSBW20UL 192
#define SROM9_5GMPO_MCSBW40 194
#define SROM9_5GHPO_MCSBW20 196
#define SROM9_5GHPO_MCSBW20UL 198
#define SROM9_5GHPO_MCSBW40 200
#define SROM9_PO_MCS32 202
#define SROM9_PO_LOFDM40DUP 203
#define SROM8_RXGAINERR_2G 205
#define SROM8_RXGAINERR_5GL 206
#define SROM8_RXGAINERR_5GM 207
#define SROM8_RXGAINERR_5GH 208
#define SROM8_RXGAINERR_5GU 209
#define SROM8_SUBBAND_PPR 210
#define SROM8_PCIEINGRESS_WAR 211
#define SROM9_SAR 212
#define SROM8_NOISELVL_2G 213
#define SROM8_NOISELVL_5GL 214
#define SROM8_NOISELVL_5GM 215
#define SROM8_NOISELVL_5GH 216
#define SROM8_NOISELVL_5GU 217
#define SROM9_REV_CRC 219
#define SROM10_CCKPWROFFSET 218
#define SROM10_SIGN 219
#define SROM10_SWCTRLMAP_2G 220
#define SROM10_CRCREV 229
#define SROM10_WORDS 230
#define SROM10_SIGNATURE SROM4_SIGNATURE
/* SROM REV 11 */
#define SROM11_BREV 65
#define SROM11_BFL0 66
#define SROM11_BFL1 67
#define SROM11_BFL2 68
#define SROM11_BFL3 69
#define SROM11_BFL4 70
#define SROM11_BFL5 71
#define SROM11_MACHI 72
#define SROM11_MACMID 73
#define SROM11_MACLO 74
#define SROM11_CCODE 75
#define SROM11_REGREV 76
#define SROM11_LEDBH10 77
#define SROM11_LEDBH32 78
#define SROM11_LEDDC 79
#define SROM11_AA 80
#define SROM11_AGBG10 81
#define SROM11_AGBG2A0 82
#define SROM11_AGA21 83
#define SROM11_TXRXC 84
#define SROM11_FEM_CFG1 85
#define SROM11_FEM_CFG2 86
/* Masks and offsets for FEM_CFG */
#define SROM11_FEMCTRL_MASK 0xf800
#define SROM11_FEMCTRL_SHIFT 11
#define SROM11_PAPDCAP_MASK 0x0400
#define SROM11_PAPDCAP_SHIFT 10
#define SROM11_TWORANGETSSI_MASK 0x0200
#define SROM11_TWORANGETSSI_SHIFT 9
#define SROM11_PDGAIN_MASK 0x01f0
#define SROM11_PDGAIN_SHIFT 4
#define SROM11_EPAGAIN_MASK 0x000e
#define SROM11_EPAGAIN_SHIFT 1
#define SROM11_TSSIPOSSLOPE_MASK 0x0001
#define SROM11_TSSIPOSSLOPE_SHIFT 0
#define SROM11_GAINCTRLSPH_MASK 0xf800
#define SROM11_GAINCTRLSPH_SHIFT 11
#define SROM11_THERMAL 87
#define SROM11_MPWR_RAWTS 88
#define SROM11_TS_SLP_OPT_CORRX 89
#define SROM11_XTAL_FREQ 90
#define SROM11_5GB0_4080_W0_A1 91
#define SROM11_PHYCAL_TEMPDELTA 92
#define SROM11_MPWR_1_AND_2 93
#define SROM11_5GB0_4080_W1_A1 94
#define SROM11_TSSIFLOOR_2G 95
#define SROM11_TSSIFLOOR_5GL 96
#define SROM11_TSSIFLOOR_5GM 97
#define SROM11_TSSIFLOOR_5GH 98
#define SROM11_TSSIFLOOR_5GU 99
/* Masks and offsets for Terrmal parameters */
#define SROM11_TEMPS_PERIOD_MASK 0xf0
#define SROM11_TEMPS_PERIOD_SHIFT 4
#define SROM11_TEMPS_HYSTERESIS_MASK 0x0f
#define SROM11_TEMPS_HYSTERESIS_SHIFT 0
#define SROM11_TEMPCORRX_MASK 0xfc
#define SROM11_TEMPCORRX_SHIFT 2
#define SROM11_TEMPSENSE_OPTION_MASK 0x3
#define SROM11_TEMPSENSE_OPTION_SHIFT 0
#define SROM11_PDOFF_2G_40M_A0_MASK 0x000f
#define SROM11_PDOFF_2G_40M_A0_SHIFT 0
#define SROM11_PDOFF_2G_40M_A1_MASK 0x00f0
#define SROM11_PDOFF_2G_40M_A1_SHIFT 4
#define SROM11_PDOFF_2G_40M_A2_MASK 0x0f00
#define SROM11_PDOFF_2G_40M_A2_SHIFT 8
#define SROM11_PDOFF_2G_40M_VALID_MASK 0x8000
#define SROM11_PDOFF_2G_40M_VALID_SHIFT 15
#define SROM11_PDOFF_2G_40M 100
#define SROM11_PDOFF_40M_A0 101
#define SROM11_PDOFF_40M_A1 102
#define SROM11_PDOFF_40M_A2 103
#define SROM11_5GB0_4080_W2_A1 103
#define SROM11_PDOFF_80M_A0 104
#define SROM11_PDOFF_80M_A1 105
#define SROM11_PDOFF_80M_A2 106
#define SROM11_5GB1_4080_W0_A1 106
#define SROM11_SUBBAND5GVER 107
/* Per-path fields and offset */
#define MAX_PATH_SROM_11 3
#define SROM11_PATH0 108
#define SROM11_PATH1 128
#define SROM11_PATH2 148
#define SROM11_2G_MAXP 0
#define SROM11_5GB1_4080_PA 0
#define SROM11_2G_PA 1
#define SROM11_5GB2_4080_PA 2
#define SROM11_RXGAINS1 4
#define SROM11_RXGAINS 5
#define SROM11_5GB3_4080_PA 5
#define SROM11_5GB1B0_MAXP 6
#define SROM11_5GB3B2_MAXP 7
#define SROM11_5GB0_PA 8
#define SROM11_5GB1_PA 11
#define SROM11_5GB2_PA 14
#define SROM11_5GB3_PA 17
/* Masks and offsets for rxgains */
#define SROM11_RXGAINS5GTRELNABYPA_MASK 0x8000
#define SROM11_RXGAINS5GTRELNABYPA_SHIFT 15
#define SROM11_RXGAINS5GTRISOA_MASK 0x7800
#define SROM11_RXGAINS5GTRISOA_SHIFT 11
#define SROM11_RXGAINS5GELNAGAINA_MASK 0x0700
#define SROM11_RXGAINS5GELNAGAINA_SHIFT 8
#define SROM11_RXGAINS2GTRELNABYPA_MASK 0x0080
#define SROM11_RXGAINS2GTRELNABYPA_SHIFT 7
#define SROM11_RXGAINS2GTRISOA_MASK 0x0078
#define SROM11_RXGAINS2GTRISOA_SHIFT 3
#define SROM11_RXGAINS2GELNAGAINA_MASK 0x0007
#define SROM11_RXGAINS2GELNAGAINA_SHIFT 0
#define SROM11_RXGAINS5GHTRELNABYPA_MASK 0x8000
#define SROM11_RXGAINS5GHTRELNABYPA_SHIFT 15
#define SROM11_RXGAINS5GHTRISOA_MASK 0x7800
#define SROM11_RXGAINS5GHTRISOA_SHIFT 11
#define SROM11_RXGAINS5GHELNAGAINA_MASK 0x0700
#define SROM11_RXGAINS5GHELNAGAINA_SHIFT 8
#define SROM11_RXGAINS5GMTRELNABYPA_MASK 0x0080
#define SROM11_RXGAINS5GMTRELNABYPA_SHIFT 7
#define SROM11_RXGAINS5GMTRISOA_MASK 0x0078
#define SROM11_RXGAINS5GMTRISOA_SHIFT 3
#define SROM11_RXGAINS5GMELNAGAINA_MASK 0x0007
#define SROM11_RXGAINS5GMELNAGAINA_SHIFT 0
/* Power per rate */
#define SROM11_CCKBW202GPO 168
#define SROM11_CCKBW20UL2GPO 169
#define SROM11_MCSBW202GPO 170
#define SROM11_MCSBW202GPO_1 171
#define SROM11_MCSBW402GPO 172
#define SROM11_MCSBW402GPO_1 173
#define SROM11_DOT11AGOFDMHRBW202GPO 174
#define SROM11_OFDMLRBW202GPO 175
#define SROM11_MCSBW205GLPO 176
#define SROM11_MCSBW205GLPO_1 177
#define SROM11_MCSBW405GLPO 178
#define SROM11_MCSBW405GLPO_1 179
#define SROM11_MCSBW805GLPO 180
#define SROM11_MCSBW805GLPO_1 181
#define SROM11_RPCAL_2G 182
#define SROM11_RPCAL_5GL 183
#define SROM11_MCSBW205GMPO 184
#define SROM11_MCSBW205GMPO_1 185
#define SROM11_MCSBW405GMPO 186
#define SROM11_MCSBW405GMPO_1 187
#define SROM11_MCSBW805GMPO 188
#define SROM11_MCSBW805GMPO_1 189
#define SROM11_RPCAL_5GM 190
#define SROM11_RPCAL_5GH 191
#define SROM11_MCSBW205GHPO 192
#define SROM11_MCSBW205GHPO_1 193
#define SROM11_MCSBW405GHPO 194
#define SROM11_MCSBW405GHPO_1 195
#define SROM11_MCSBW805GHPO 196
#define SROM11_MCSBW805GHPO_1 197
#define SROM11_RPCAL_5GU 198
#define SROM11_MCSLR5GLPO 200
#define SROM11_MCSLR5GMPO 201
#define SROM11_MCSLR5GHPO 202
#define SROM11_SB20IN40HRPO 203
#define SROM11_SB20IN80AND160HR5GLPO 204
#define SROM11_SB40AND80HR5GLPO 205
#define SROM11_SB20IN80AND160HR5GMPO 206
#define SROM11_SB40AND80HR5GMPO 207
#define SROM11_SB20IN80AND160HR5GHPO 208
#define SROM11_SB40AND80HR5GHPO 209
#define SROM11_SB20IN40LRPO 210
#define SROM11_SB20IN80AND160LR5GLPO 211
#define SROM11_SB40AND80LR5GLPO 212
#define SROM11_TXIDXCAP2G 212
#define SROM11_SB20IN80AND160LR5GMPO 213
#define SROM11_SB40AND80LR5GMPO 214
#define SROM11_TXIDXCAP5G 214
#define SROM11_SB20IN80AND160LR5GHPO 215
#define SROM11_SB40AND80LR5GHPO 216
#define SROM11_DOT11AGDUPHRPO 217
#define SROM11_DOT11AGDUPLRPO 218
/* MISC */
#define SROM11_PCIEINGRESS_WAR 220
#define SROM11_SAR 221
#define SROM11_NOISELVL_2G 222
#define SROM11_NOISELVL_5GL 223
#define SROM11_NOISELVL_5GM 224
#define SROM11_NOISELVL_5GH 225
#define SROM11_NOISELVL_5GU 226
#define SROM11_RXGAINERR_2G 227
#define SROM11_RXGAINERR_5GL 228
#define SROM11_RXGAINERR_5GM 229
#define SROM11_RXGAINERR_5GH 230
#define SROM11_RXGAINERR_5GU 231
#define SROM11_SIGN 64
#define SROM11_CRCREV 233
#define SROM11_WORDS 234
#define SROM11_SIGNATURE 0x0634
typedef struct {
uint8 tssipos; /* TSSI positive slope, 1: positive, 0: negative */
uint8 extpagain; /* Ext PA gain-type: full-gain: 0, pa-lite: 1, no_pa: 2 */
uint8 pdetrange; /* support 32 combinations of different Pdet dynamic ranges */
uint8 triso; /* TR switch isolation */
uint8 antswctrllut; /* antswctrl lookup table configuration: 32 possible choices */
} srom_fem_t;
#endif /* _bcmsrom_fmt_h_ */

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/*
* Broadcom USB/HSIC framing
* Software-specific framing definitions shared between host and device
*
* $Copyright Open 2012 Broadcom Corporation$
*
* $Id: bcmusb.h 281591 2012-09-02 18:43:02Z sgsiener $
*/
#ifndef _bcmusb_h_
#define _bcmusb_h_
/*
* Software-defined USB frame header
*/
#ifdef USB_FRAME_HEADER
#define USBF_HEADER_LEN 16
#else
#define USBF_HEADER_LEN 0
#endif
#ifdef USBF_CKSUM_OVER_FRAME
#define USBF_DEF_CKSUM_LEN 0
#else
#define USBF_DEF_CKSUM_LEN USBF_HEADER_LEN
#endif
/* Current protocol version */
#define USBF_PROT_VERSION 1
/* ----- first 32-bit word ----- */
/* 4-bit version field */
#define USBF_VER_MASK 0x0000000f
/* 8-bit flags field */
#define USBF_FLAGS_MASK 0x00000ff0
#define USBF_FLAGS_SHIFT 4
/* flags field definitions */
#define USBF_FLAGS_TIMESTAMPED 0x01 /* frame header includes timestamp */
#define USBF_FLAGS_FRAME_EVENT 0x02 /* set when frame contains an Event indication */
#define USBF_FLAGS_FRAME_CKSUM 0x04 /* set when cksum is over entire frame */
/* 3-bit channel identifier field */
#define USBF_CHAN_MASK 0x00007000
#define USBF_CHAN_SHIFT 12
#define USBF_CHAN_CONTROL 0
#define USBF_CHAN_INTERRUPT 1
#define USBF_CHAN_DATAEVENT 2
/* used by host & device to disambiguate frames with this header from ones without */
#define USBF_TAG 0x00008000 /* bit won't appear in bdc/ioctl header */
/* 16-bit checksum */
#define USBF_CHECKSUM_MASK 0xffff0000 /* checksum mask */
#define USBF_CHECKSUM_SHIFT 16
/* ----- second 32-bit word ----- */
/* 16-bit length */
#define USBF_LENGTH_MASK 0x0000ffff /* length mask */
/* 16-bit sequence number */
#define USBF_SEQNUM_MASK 0xffff0000 /* sequence number mask */
#define USBF_SEQSUM_SHIFT 16
/* ----- third 32-bit word ----- */
/* 32-bit timestamp */
#define USBF_TIMESTAMP_MASK 0xffffffff /* timestamp value mask */
/* ----- fourth 32-bit word ----- */
/* reserve 32 bits for future use */
#define USBF_RESERVED_MASK 0xffffffff /* reserved for future use mask */
#endif /* _bcmusb_h_ */

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/*
* Misc useful os-independent macros and functions.
*
* $Copyright Open Broadcom Corporation$
*
* $Id: bcmutils.h 409286 2013-06-24 22:03:30Z stafford $
*/
#ifndef _bcmutils_h_
#define _bcmutils_h_
#if defined(UNDER_CE)
#include <bcmsafestr.h>
#else
#define bcm_strcpy_s(dst, noOfElements, src) strcpy((dst), (src))
#define bcm_strncpy_s(dst, noOfElements, src, count) strncpy((dst), (src), (count))
#define bcm_strcat_s(dst, noOfElements, src) strcat((dst), (src))
#endif
#ifdef __cplusplus
extern "C" {
#endif
#ifdef PKTQ_LOG
#include <wlioctl.h>
#endif
/* ctype replacement */
#define _BCM_U 0x01 /* upper */
#define _BCM_L 0x02 /* lower */
#define _BCM_D 0x04 /* digit */
#define _BCM_C 0x08 /* cntrl */
#define _BCM_P 0x10 /* punct */
#define _BCM_S 0x20 /* white space (space/lf/tab) */
#define _BCM_X 0x40 /* hex digit */
#define _BCM_SP 0x80 /* hard space (0x20) */
#if defined(BCMROMBUILD)
extern const unsigned char BCMROMDATA(bcm_ctype)[];
#else
extern const unsigned char bcm_ctype[];
#endif
#define bcm_ismask(x) (bcm_ctype[(int)(unsigned char)(x)])
#define bcm_isalnum(c) ((bcm_ismask(c)&(_BCM_U|_BCM_L|_BCM_D)) != 0)
#define bcm_isalpha(c) ((bcm_ismask(c)&(_BCM_U|_BCM_L)) != 0)
#define bcm_iscntrl(c) ((bcm_ismask(c)&(_BCM_C)) != 0)
#define bcm_isdigit(c) ((bcm_ismask(c)&(_BCM_D)) != 0)
#define bcm_isgraph(c) ((bcm_ismask(c)&(_BCM_P|_BCM_U|_BCM_L|_BCM_D)) != 0)
#define bcm_islower(c) ((bcm_ismask(c)&(_BCM_L)) != 0)
#define bcm_isprint(c) ((bcm_ismask(c)&(_BCM_P|_BCM_U|_BCM_L|_BCM_D|_BCM_SP)) != 0)
#define bcm_ispunct(c) ((bcm_ismask(c)&(_BCM_P)) != 0)
#define bcm_isspace(c) ((bcm_ismask(c)&(_BCM_S)) != 0)
#define bcm_isupper(c) ((bcm_ismask(c)&(_BCM_U)) != 0)
#define bcm_isxdigit(c) ((bcm_ismask(c)&(_BCM_D|_BCM_X)) != 0)
#define bcm_tolower(c) (bcm_isupper((c)) ? ((c) + 'a' - 'A') : (c))
#define bcm_toupper(c) (bcm_islower((c)) ? ((c) + 'A' - 'a') : (c))
/* Buffer structure for collecting string-formatted data
* using bcm_bprintf() API.
* Use bcm_binit() to initialize before use
*/
struct bcmstrbuf {
char *buf; /* pointer to current position in origbuf */
unsigned int size; /* current (residual) size in bytes */
char *origbuf; /* unmodified pointer to orignal buffer */
unsigned int origsize; /* unmodified orignal buffer size in bytes */
};
/* ** driver-only section ** */
#ifdef BCMDRIVER
#ifdef EFI
/* forward declare structyre type */
struct spktq;
#endif
#include <osl.h>
#define GPIO_PIN_NOTDEFINED 0x20 /* Pin not defined */
/*
* Spin at most 'us' microseconds while 'exp' is true.
* Caller should explicitly test 'exp' when this completes
* and take appropriate error action if 'exp' is still true.
*/
#ifdef MACOSX
#define SPINWAIT_POLL_PERIOD 20
#else
#define SPINWAIT_POLL_PERIOD 10
#endif
#define SPINWAIT(exp, us) { \
uint countdown = (us) + (SPINWAIT_POLL_PERIOD - 1); \
while ((exp) && (countdown >= SPINWAIT_POLL_PERIOD)) {\
OSL_DELAY(SPINWAIT_POLL_PERIOD); \
countdown -= SPINWAIT_POLL_PERIOD; \
} \
}
/* osl multi-precedence packet queue */
#define PKTQ_LEN_MAX 0xFFFF /* Max uint16 65535 packets */
#ifndef PKTQ_LEN_DEFAULT
#define PKTQ_LEN_DEFAULT 128 /* Max 128 packets */
#endif
#ifndef PKTQ_MAX_PREC
#define PKTQ_MAX_PREC 16 /* Maximum precedence levels */
#endif
typedef struct pktq_prec {
void *head; /* first packet to dequeue */
void *tail; /* last packet to dequeue */
uint16 len; /* number of queued packets */
uint16 max; /* maximum number of queued packets */
} pktq_prec_t;
#ifdef PKTQ_LOG
typedef struct {
uint32 requested; /* packets requested to be stored */
uint32 stored; /* packets stored */
uint32 saved; /* packets saved,
because a lowest priority queue has given away one packet
*/
uint32 selfsaved; /* packets saved,
because an older packet from the same queue has been dropped
*/
uint32 full_dropped; /* packets dropped,
because pktq is full with higher precedence packets
*/
uint32 dropped; /* packets dropped because pktq per that precedence is full */
uint32 sacrificed; /* packets dropped,
in order to save one from a queue of a highest priority
*/
uint32 busy; /* packets droped because of hardware/transmission error */
uint32 retry; /* packets re-sent because they were not received */
uint32 ps_retry; /* packets retried again prior to moving power save mode */
uint32 suppress; /* packets which were suppressed and not transmitted */
uint32 retry_drop; /* packets finally dropped after retry limit */
uint32 max_avail; /* the high-water mark of the queue capacity for packets -
goes to zero as queue fills
*/
uint32 max_used; /* the high-water mark of the queue utilisation for packets -
increases with use ('inverse' of max_avail)
*/
uint32 queue_capacity; /* the maximum capacity of the queue */
uint32 rtsfail; /* count of rts attempts that failed to receive cts */
uint32 acked; /* count of packets sent (acked) successfully */
uint32 txrate_succ; /* running total of phy rate of packets sent successfully */
uint32 txrate_main; /* running totoal of primary phy rate of all packets */
uint32 throughput; /* actual data transferred successfully */
uint32 _logtime; /* timestamp of last counter clear */
} pktq_counters_t;
typedef struct {
uint32 _prec_log;
pktq_counters_t* _prec_cnt[PKTQ_MAX_PREC]; /* Counters per queue */
} pktq_log_t;
#endif /* PKTQ_LOG */
#define PKTQ_COMMON \
uint16 num_prec; /* number of precedences in use */ \
uint16 hi_prec; /* rapid dequeue hint (>= highest non-empty prec) */ \
uint16 max; /* total max packets */ \
uint16 len; /* total number of packets */
/* multi-priority pkt queue */
struct pktq {
PKTQ_COMMON
/* q array must be last since # of elements can be either PKTQ_MAX_PREC or 1 */
struct pktq_prec q[PKTQ_MAX_PREC];
#ifdef PKTQ_LOG
pktq_log_t* pktqlog;
#endif
};
/* simple, non-priority pkt queue */
struct spktq {
PKTQ_COMMON
/* q array must be last since # of elements can be either PKTQ_MAX_PREC or 1 */
struct pktq_prec q[1];
};
#define PKTQ_PREC_ITER(pq, prec) for (prec = (pq)->num_prec - 1; prec >= 0; prec--)
/* fn(pkt, arg). return true if pkt belongs to if */
typedef bool (*ifpkt_cb_t)(void*, int);
#ifdef BCMPKTPOOL
#define POOL_ENAB(pool) ((pool) && (pool)->inited)
#if defined(BCM4329C0)
#define SHARED_POOL (pktpool_shared_ptr)
#else
#define SHARED_POOL (pktpool_shared)
#endif /* BCM4329C0 */
#else /* BCMPKTPOOL */
#define POOL_ENAB(bus) 0
#define SHARED_POOL ((struct pktpool *)NULL)
#endif /* BCMPKTPOOL */
#ifndef PKTPOOL_LEN_MAX
#define PKTPOOL_LEN_MAX 40
#endif /* PKTPOOL_LEN_MAX */
#define PKTPOOL_CB_MAX 3
struct pktpool;
typedef void (*pktpool_cb_t)(struct pktpool *pool, void *arg);
typedef struct {
pktpool_cb_t cb;
void *arg;
} pktpool_cbinfo_t;
#ifdef BCMDBG_POOL
/* pkt pool debug states */
#define POOL_IDLE 0
#define POOL_RXFILL 1
#define POOL_RXDH 2
#define POOL_RXD11 3
#define POOL_TXDH 4
#define POOL_TXD11 5
#define POOL_AMPDU 6
#define POOL_TXENQ 7
typedef struct {
void *p;
uint32 cycles;
uint32 dur;
} pktpool_dbg_t;
typedef struct {
uint8 txdh; /* tx to host */
uint8 txd11; /* tx to d11 */
uint8 enq; /* waiting in q */
uint8 rxdh; /* rx from host */
uint8 rxd11; /* rx from d11 */
uint8 rxfill; /* dma_rxfill */
uint8 idle; /* avail in pool */
} pktpool_stats_t;
#endif /* BCMDBG_POOL */
typedef struct pktpool {
bool inited;
uint16 r;
uint16 w;
uint16 len;
uint16 maxlen;
uint16 plen;
bool istx;
bool empty;
uint8 cbtoggle;
uint8 cbcnt;
uint8 ecbcnt;
bool emptycb_disable;
pktpool_cbinfo_t *availcb_excl;
pktpool_cbinfo_t cbs[PKTPOOL_CB_MAX];
pktpool_cbinfo_t ecbs[PKTPOOL_CB_MAX];
void *q[PKTPOOL_LEN_MAX + 1];
#ifdef BCMDBG_POOL
uint8 dbg_cbcnt;
pktpool_cbinfo_t dbg_cbs[PKTPOOL_CB_MAX];
uint16 dbg_qlen;
pktpool_dbg_t dbg_q[PKTPOOL_LEN_MAX + 1];
#endif
} pktpool_t;
#if defined(BCM4329C0)
extern pktpool_t *pktpool_shared_ptr;
#else
extern pktpool_t *pktpool_shared;
#endif /* BCM4329C0 */
extern int pktpool_init(osl_t *osh, pktpool_t *pktp, int *pktplen, int plen, bool istx);
extern int pktpool_deinit(osl_t *osh, pktpool_t *pktp);
extern int pktpool_fill(osl_t *osh, pktpool_t *pktp, bool minimal);
extern void* pktpool_get(pktpool_t *pktp);
extern void pktpool_free(pktpool_t *pktp, void *p);
extern int pktpool_add(pktpool_t *pktp, void *p);
extern uint16 pktpool_avail(pktpool_t *pktp);
extern int pktpool_avail_notify_normal(osl_t *osh, pktpool_t *pktp);
extern int pktpool_avail_notify_exclusive(osl_t *osh, pktpool_t *pktp, pktpool_cb_t cb);
extern int pktpool_avail_register(pktpool_t *pktp, pktpool_cb_t cb, void *arg);
extern int pktpool_empty_register(pktpool_t *pktp, pktpool_cb_t cb, void *arg);
extern int pktpool_setmaxlen(pktpool_t *pktp, uint16 maxlen);
extern int pktpool_setmaxlen_strict(osl_t *osh, pktpool_t *pktp, uint16 maxlen);
extern void pktpool_emptycb_disable(pktpool_t *pktp, bool disable);
extern bool pktpool_emptycb_disabled(pktpool_t *pktp);
#define POOLPTR(pp) ((pktpool_t *)(pp))
#define pktpool_len(pp) (POOLPTR(pp)->len - 1)
#define pktpool_plen(pp) (POOLPTR(pp)->plen)
#define pktpool_maxlen(pp) (POOLPTR(pp)->maxlen)
#ifdef BCMDBG_POOL
extern int pktpool_dbg_register(pktpool_t *pktp, pktpool_cb_t cb, void *arg);
extern int pktpool_start_trigger(pktpool_t *pktp, void *p);
extern int pktpool_dbg_dump(pktpool_t *pktp);
extern int pktpool_dbg_notify(pktpool_t *pktp);
extern int pktpool_stats_dump(pktpool_t *pktp, pktpool_stats_t *stats);
#endif /* BCMDBG_POOL */
/* forward definition of ether_addr structure used by some function prototypes */
struct ether_addr;
extern int ether_isbcast(const void *ea);
extern int ether_isnulladdr(const void *ea);
/* operations on a specific precedence in packet queue */
#define pktq_psetmax(pq, prec, _max) ((pq)->q[prec].max = (_max))
#define pktq_pmax(pq, prec) ((pq)->q[prec].max)
#define pktq_plen(pq, prec) ((pq)->q[prec].len)
#define pktq_pavail(pq, prec) ((pq)->q[prec].max - (pq)->q[prec].len)
#define pktq_pfull(pq, prec) ((pq)->q[prec].len >= (pq)->q[prec].max)
#define pktq_pempty(pq, prec) ((pq)->q[prec].len == 0)
#define pktq_ppeek(pq, prec) ((pq)->q[prec].head)
#define pktq_ppeek_tail(pq, prec) ((pq)->q[prec].tail)
extern void *pktq_penq(struct pktq *pq, int prec, void *p);
extern void *pktq_penq_head(struct pktq *pq, int prec, void *p);
extern void *pktq_pdeq(struct pktq *pq, int prec);
extern void *pktq_pdeq_prev(struct pktq *pq, int prec, void *prev_p);
extern void *pktq_pdeq_tail(struct pktq *pq, int prec);
/* Empty the queue at particular precedence level */
extern void pktq_pflush(osl_t *osh, struct pktq *pq, int prec, bool dir,
ifpkt_cb_t fn, int arg);
/* Remove a specified packet from its queue */
extern bool pktq_pdel(struct pktq *pq, void *p, int prec);
/* operations on a set of precedences in packet queue */
extern int pktq_mlen(struct pktq *pq, uint prec_bmp);
extern void *pktq_mdeq(struct pktq *pq, uint prec_bmp, int *prec_out);
extern void *pktq_mpeek(struct pktq *pq, uint prec_bmp, int *prec_out);
/* operations on packet queue as a whole */
#define pktq_len(pq) ((int)(pq)->len)
#define pktq_max(pq) ((int)(pq)->max)
#define pktq_avail(pq) ((int)((pq)->max - (pq)->len))
#define pktq_full(pq) ((pq)->len >= (pq)->max)
#define pktq_empty(pq) ((pq)->len == 0)
/* operations for single precedence queues */
#define pktenq(pq, p) pktq_penq(((struct pktq *)(void *)pq), 0, (p))
#define pktenq_head(pq, p) pktq_penq_head(((struct pktq *)(void *)pq), 0, (p))
#define pktdeq(pq) pktq_pdeq(((struct pktq *)(void *)pq), 0)
#define pktdeq_tail(pq) pktq_pdeq_tail(((struct pktq *)(void *)pq), 0)
#define pktqinit(pq, len) pktq_init(((struct pktq *)(void *)pq), 1, len)
extern void pktq_init(struct pktq *pq, int num_prec, int max_len);
extern void pktq_set_max_plen(struct pktq *pq, int prec, int max_len);
/* prec_out may be NULL if caller is not interested in return value */
extern void *pktq_deq(struct pktq *pq, int *prec_out);
extern void *pktq_deq_tail(struct pktq *pq, int *prec_out);
extern void *pktq_peek(struct pktq *pq, int *prec_out);
extern void *pktq_peek_tail(struct pktq *pq, int *prec_out);
extern void pktq_flush(osl_t *osh, struct pktq *pq, bool dir, ifpkt_cb_t fn, int arg);
/* externs */
/* packet */
extern uint pktcopy(osl_t *osh, void *p, uint offset, int len, uchar *buf);
extern uint pktfrombuf(osl_t *osh, void *p, uint offset, int len, uchar *buf);
extern uint pkttotlen(osl_t *osh, void *p);
extern void *pktlast(osl_t *osh, void *p);
extern uint pktsegcnt(osl_t *osh, void *p);
extern uint pktsegcnt_war(osl_t *osh, void *p);
extern uint8 *pktdataoffset(osl_t *osh, void *p, uint offset);
extern void *pktoffset(osl_t *osh, void *p, uint offset);
/* Get priority from a packet and pass it back in scb (or equiv) */
#define PKTPRIO_VDSCP 0x100 /* DSCP prio found after VLAN tag */
#define PKTPRIO_VLAN 0x200 /* VLAN prio found */
#define PKTPRIO_UPD 0x400 /* DSCP used to update VLAN prio */
#define PKTPRIO_DSCP 0x800 /* DSCP prio found */
extern uint pktsetprio(void *pkt, bool update_vtag);
/* string */
extern int BCMROMFN(bcm_atoi)(const char *s);
extern ulong BCMROMFN(bcm_strtoul)(const char *cp, char **endp, uint base);
extern char *BCMROMFN(bcmstrstr)(const char *haystack, const char *needle);
extern char *BCMROMFN(bcmstrcat)(char *dest, const char *src);
extern char *BCMROMFN(bcmstrncat)(char *dest, const char *src, uint size);
extern ulong wchar2ascii(char *abuf, ushort *wbuf, ushort wbuflen, ulong abuflen);
char* bcmstrtok(char **string, const char *delimiters, char *tokdelim);
int bcmstricmp(const char *s1, const char *s2);
int bcmstrnicmp(const char* s1, const char* s2, int cnt);
/* ethernet address */
extern char *bcm_ether_ntoa(const struct ether_addr *ea, char *buf);
extern int BCMROMFN(bcm_ether_atoe)(const char *p, struct ether_addr *ea);
/* ip address */
struct ipv4_addr;
extern char *bcm_ip_ntoa(struct ipv4_addr *ia, char *buf);
extern char *bcm_ipv6_ntoa(void *ipv6, char *buf);
/* delay */
extern void bcm_mdelay(uint ms);
/* variable access */
#if defined (DONGLEBUILD) && !defined(WLTEST) && !defined (BCMINTERNAL) && !defined(BCMDBG_DUMP)
#ifdef BCMDBG
#define NVRAM_RECLAIM_CHECK(name) \
if (attach_part_reclaimed == TRUE) { \
printf("%s: NVRAM already reclaimed, %s\n", __FUNCTION__, (name)); \
*(char*) 0 = 0; /* TRAP */ \
return NULL; \
}
#else /* BCMDBG */
#define NVRAM_RECLAIM_CHECK(name) \
if (attach_part_reclaimed == TRUE) { \
*(char*) 0 = 0; /* TRAP */ \
return NULL; \
}
#endif /* BCMDBG */
#else /* DONGLEBUILD && !WLTEST && !BCMINTERNAL && !BCMDBG_DUMP */
#define NVRAM_RECLAIM_CHECK(name)
#endif /* DONGLEBUILD && !WLTEST && !BCMINTERNAL && !BCMDBG_DUMP */
extern char *getvar(char *vars, const char *name);
extern int getintvar(char *vars, const char *name);
extern int getintvararray(char *vars, const char *name, int index);
extern int getintvararraysize(char *vars, const char *name);
extern uint getgpiopin(char *vars, char *pin_name, uint def_pin);
#ifdef BCMDBG
extern void prpkt(const char *msg, osl_t *osh, void *p0);
#endif /* BCMDBG */
#ifdef BCMPERFSTATS
extern void bcm_perf_enable(void);
extern void bcmstats(char *fmt);
extern void bcmlog(char *fmt, uint a1, uint a2);
extern void bcmdumplog(char *buf, int size);
extern int bcmdumplogent(char *buf, uint idx);
#else
#define bcm_perf_enable()
#define bcmstats(fmt)
#define bcmlog(fmt, a1, a2)
#define bcmdumplog(buf, size) *buf = '\0'
#define bcmdumplogent(buf, idx) -1
#endif /* BCMPERFSTATS */
#define TSF_TICKS_PER_MS 1024
#if defined(BCMTSTAMPEDLOGS)
/* Store a TSF timestamp and a log line in the log buffer */
extern void bcmtslog(uint32 tstamp, char *fmt, uint a1, uint a2);
/* Print out the log buffer with timestamps */
extern void bcmprinttslogs(void);
/* Print out a microsecond timestamp as "sec.ms.us " */
extern void bcmprinttstamp(uint32 us);
/* Dump to buffer a microsecond timestamp as "sec.ms.us " */
extern void bcmdumptslog(char *buf, int size);
#else
#define bcmtslog(tstamp, fmt, a1, a2)
#define bcmprinttslogs()
#define bcmprinttstamp(us)
#define bcmdumptslog(buf, size)
#endif /* BCMTSTAMPEDLOGS */
extern char *bcm_nvram_vars(uint *length);
extern int bcm_nvram_cache(void *sih);
/* Support for sharing code across in-driver iovar implementations.
* The intent is that a driver use this structure to map iovar names
* to its (private) iovar identifiers, and the lookup function to
* find the entry. Macros are provided to map ids and get/set actions
* into a single number space for a switch statement.
*/
/* iovar structure */
typedef struct bcm_iovar {
const char *name; /* name for lookup and display */
uint16 varid; /* id for switch */
uint16 flags; /* driver-specific flag bits */
uint16 type; /* base type of argument */
uint16 minlen; /* min length for buffer vars */
} bcm_iovar_t;
/* varid definitions are per-driver, may use these get/set bits */
/* IOVar action bits for id mapping */
#define IOV_GET 0 /* Get an iovar */
#define IOV_SET 1 /* Set an iovar */
/* Varid to actionid mapping */
#define IOV_GVAL(id) ((id) * 2)
#define IOV_SVAL(id) ((id) * 2 + IOV_SET)
#define IOV_ISSET(actionid) ((actionid & IOV_SET) == IOV_SET)
#define IOV_ID(actionid) (actionid >> 1)
/* flags are per-driver based on driver attributes */
extern const bcm_iovar_t *bcm_iovar_lookup(const bcm_iovar_t *table, const char *name);
extern int bcm_iovar_lencheck(const bcm_iovar_t *table, void *arg, int len, bool set);
#if defined(WLTINYDUMP) || defined(BCMDBG) || defined(WLMSG_INFORM) || \
defined(WLMSG_ASSOC) || defined(WLMSG_PRPKT) || defined(WLMSG_WSEC)
extern int bcm_format_ssid(char* buf, const uchar ssid[], uint ssid_len);
#endif /* WLTINYDUMP || BCMDBG || WLMSG_INFORM || WLMSG_ASSOC || WLMSG_PRPKT */
#endif /* BCMDRIVER */
/* Base type definitions */
#define IOVT_VOID 0 /* no value (implictly set only) */
#define IOVT_BOOL 1 /* any value ok (zero/nonzero) */
#define IOVT_INT8 2 /* integer values are range-checked */
#define IOVT_UINT8 3 /* unsigned int 8 bits */
#define IOVT_INT16 4 /* int 16 bits */
#define IOVT_UINT16 5 /* unsigned int 16 bits */
#define IOVT_INT32 6 /* int 32 bits */
#define IOVT_UINT32 7 /* unsigned int 32 bits */
#define IOVT_BUFFER 8 /* buffer is size-checked as per minlen */
#define BCM_IOVT_VALID(type) (((unsigned int)(type)) <= IOVT_BUFFER)
/* Initializer for IOV type strings */
#define BCM_IOV_TYPE_INIT { \
"void", \
"bool", \
"int8", \
"uint8", \
"int16", \
"uint16", \
"int32", \
"uint32", \
"buffer", \
"" }
#define BCM_IOVT_IS_INT(type) (\
(type == IOVT_BOOL) || \
(type == IOVT_INT8) || \
(type == IOVT_UINT8) || \
(type == IOVT_INT16) || \
(type == IOVT_UINT16) || \
(type == IOVT_INT32) || \
(type == IOVT_UINT32))
/* ** driver/apps-shared section ** */
#define BCME_STRLEN 64 /* Max string length for BCM errors */
#define VALID_BCMERROR(e) ((e <= 0) && (e >= BCME_LAST))
/*
* error codes could be added but the defined ones shouldn't be changed/deleted
* these error codes are exposed to the user code
* when ever a new error code is added to this list
* please update errorstring table with the related error string and
* update osl files with os specific errorcode map
*/
#define BCME_OK 0 /* Success */
#define BCME_ERROR -1 /* Error generic */
#define BCME_BADARG -2 /* Bad Argument */
#define BCME_BADOPTION -3 /* Bad option */
#define BCME_NOTUP -4 /* Not up */
#define BCME_NOTDOWN -5 /* Not down */
#define BCME_NOTAP -6 /* Not AP */
#define BCME_NOTSTA -7 /* Not STA */
#define BCME_BADKEYIDX -8 /* BAD Key Index */
#define BCME_RADIOOFF -9 /* Radio Off */
#define BCME_NOTBANDLOCKED -10 /* Not band locked */
#define BCME_NOCLK -11 /* No Clock */
#define BCME_BADRATESET -12 /* BAD Rate valueset */
#define BCME_BADBAND -13 /* BAD Band */
#define BCME_BUFTOOSHORT -14 /* Buffer too short */
#define BCME_BUFTOOLONG -15 /* Buffer too long */
#define BCME_BUSY -16 /* Busy */
#define BCME_NOTASSOCIATED -17 /* Not Associated */
#define BCME_BADSSIDLEN -18 /* Bad SSID len */
#define BCME_OUTOFRANGECHAN -19 /* Out of Range Channel */
#define BCME_BADCHAN -20 /* Bad Channel */
#define BCME_BADADDR -21 /* Bad Address */
#define BCME_NORESOURCE -22 /* Not Enough Resources */
#define BCME_UNSUPPORTED -23 /* Unsupported */
#define BCME_BADLEN -24 /* Bad length */
#define BCME_NOTREADY -25 /* Not Ready */
#define BCME_EPERM -26 /* Not Permitted */
#define BCME_NOMEM -27 /* No Memory */
#define BCME_ASSOCIATED -28 /* Associated */
#define BCME_RANGE -29 /* Not In Range */
#define BCME_NOTFOUND -30 /* Not Found */
#define BCME_WME_NOT_ENABLED -31 /* WME Not Enabled */
#define BCME_TSPEC_NOTFOUND -32 /* TSPEC Not Found */
#define BCME_ACM_NOTSUPPORTED -33 /* ACM Not Supported */
#define BCME_NOT_WME_ASSOCIATION -34 /* Not WME Association */
#define BCME_SDIO_ERROR -35 /* SDIO Bus Error */
#define BCME_DONGLE_DOWN -36 /* Dongle Not Accessible */
#define BCME_VERSION -37 /* Incorrect version */
#define BCME_TXFAIL -38 /* TX failure */
#define BCME_RXFAIL -39 /* RX failure */
#define BCME_NODEVICE -40 /* Device not present */
#define BCME_NMODE_DISABLED -41 /* NMODE disabled */
#define BCME_NONRESIDENT -42 /* access to nonresident overlay */
#define BCME_SCANREJECT -43 /* reject scan request */
/* Leave gap between -44 and -46 to synchronize with trunk. */
#define BCME_DISABLED -47 /* Disabled in this build */
#define BCME_LAST BCME_DISABLED
/* These are collection of BCME Error strings */
#define BCMERRSTRINGTABLE { \
"OK", \
"Undefined error", \
"Bad Argument", \
"Bad Option", \
"Not up", \
"Not down", \
"Not AP", \
"Not STA", \
"Bad Key Index", \
"Radio Off", \
"Not band locked", \
"No clock", \
"Bad Rate valueset", \
"Bad Band", \
"Buffer too short", \
"Buffer too long", \
"Busy", \
"Not Associated", \
"Bad SSID len", \
"Out of Range Channel", \
"Bad Channel", \
"Bad Address", \
"Not Enough Resources", \
"Unsupported", \
"Bad length", \
"Not Ready", \
"Not Permitted", \
"No Memory", \
"Associated", \
"Not In Range", \
"Not Found", \
"WME Not Enabled", \
"TSPEC Not Found", \
"ACM Not Supported", \
"Not WME Association", \
"SDIO Bus Error", \
"Dongle Not Accessible", \
"Incorrect version", \
"TX Failure", \
"RX Failure", \
"Device Not Present", \
"NMODE Disabled", \
"Nonresident overlay access", \
"Scan Rejected", \
"unused", \
"unused", \
"unused", \
"Disabled", \
}
#ifndef ABS
#define ABS(a) (((a) < 0) ? -(a) : (a))
#endif /* ABS */
#ifndef MIN
#define MIN(a, b) (((a) < (b)) ? (a) : (b))
#endif /* MIN */
#ifndef MAX
#define MAX(a, b) (((a) > (b)) ? (a) : (b))
#endif /* MAX */
/* limit to [min, max] */
#ifndef LIMIT_TO_RANGE
#define LIMIT_TO_RANGE(x, min, max) \
((x) < (min) ? (min) : ((x) > (max) ? (max) : (x)))
#endif /* LIMIT_TO_RANGE */
/* limit to max */
#ifndef LIMIT_TO_MAX
#define LIMIT_TO_MAX(x, max) \
(((x) > (max) ? (max) : (x)))
#endif /* LIMIT_TO_MAX */
/* limit to min */
#ifndef LIMIT_TO_MIN
#define LIMIT_TO_MIN(x, min) \
(((x) < (min) ? (min) : (x)))
#endif /* LIMIT_TO_MIN */
#define CEIL(x, y) (((x) + ((y) - 1)) / (y))
#define ROUNDUP(x, y) ((((x) + ((y) - 1)) / (y)) * (y))
#define ISALIGNED(a, x) (((uintptr)(a) & ((x) - 1)) == 0)
#define ALIGN_ADDR(addr, boundary) (void *)(((uintptr)(addr) + (boundary) - 1) \
& ~((boundary) - 1))
#define ALIGN_SIZE(size, boundary) (((size) + (boundary) - 1) \
& ~((boundary) - 1))
#define ISPOWEROF2(x) ((((x) - 1) & (x)) == 0)
#define VALID_MASK(mask) !((mask) & ((mask) + 1))
#ifndef OFFSETOF
#ifdef __ARMCC_VERSION
/*
* The ARM RVCT compiler complains when using OFFSETOF where a constant
* expression is expected, such as an initializer for a static object.
* offsetof from the runtime library doesn't have that problem.
*/
#include <stddef.h>
#define OFFSETOF(type, member) offsetof(type, member)
#elif __GNUC__ >= 4
/* New versions of GCC are also complaining if the usual macro is used */
#define OFFSETOF(type, member) __builtin_offsetof(type, member)
#else
#define OFFSETOF(type, member) ((uint)(uintptr)&((type *)0)->member)
#endif /* __ARMCC_VERSION */
#endif /* OFFSETOF */
#ifndef ARRAYSIZE
#define ARRAYSIZE(a) (sizeof(a) / sizeof(a[0]))
#endif
/* Reference a function; used to prevent a static function from being optimized out */
extern void *_bcmutils_dummy_fn;
#define REFERENCE_FUNCTION(f) (_bcmutils_dummy_fn = (void *)(f))
#if defined(__NetBSD__)
/* use internal
* setbit/clrbit since it has a cast and netbsd Xbit funcs dont
* and the wl driver doesnt cast. this results in us offsetting
* incorrectly and corrupting memory.
*/
#ifdef setbit
#undef setbit
#undef clrbit
#undef isset
#undef isclr
#undef NBBY
#endif
#endif /* __NetBSD__ */
/* bit map related macros */
#ifndef setbit
#ifndef NBBY /* the BSD family defines NBBY */
#define NBBY 8 /* 8 bits per byte */
#endif /* #ifndef NBBY */
#define setbit(a, i) (((uint8 *)a)[(i) / NBBY] |= 1 << ((i) % NBBY))
#define clrbit(a, i) (((uint8 *)a)[(i) / NBBY] &= ~(1 << ((i) % NBBY)))
#define isset(a, i) (((const uint8 *)a)[(i) / NBBY] & (1 << ((i) % NBBY)))
#define isclr(a, i) ((((const uint8 *)a)[(i) / NBBY] & (1 << ((i) % NBBY))) == 0)
#endif /* setbit */
#define isbitset(a, i) (((a) & (1 << (i))) != 0)
#define NBITS(type) (sizeof(type) * 8)
#define NBITVAL(nbits) (1 << (nbits))
#define MAXBITVAL(nbits) ((1 << (nbits)) - 1)
#define NBITMASK(nbits) MAXBITVAL(nbits)
#define MAXNBVAL(nbyte) MAXBITVAL((nbyte) * 8)
/* basic mux operation - can be optimized on several architectures */
#define MUX(pred, true, false) ((pred) ? (true) : (false))
/* modulo inc/dec - assumes x E [0, bound - 1] */
#define MODDEC(x, bound) MUX((x) == 0, (bound) - 1, (x) - 1)
#define MODINC(x, bound) MUX((x) == (bound) - 1, 0, (x) + 1)
/* modulo inc/dec, bound = 2^k */
#define MODDEC_POW2(x, bound) (((x) - 1) & ((bound) - 1))
#define MODINC_POW2(x, bound) (((x) + 1) & ((bound) - 1))
/* modulo add/sub - assumes x, y E [0, bound - 1] */
#define MODADD(x, y, bound) \
MUX((x) + (y) >= (bound), (x) + (y) - (bound), (x) + (y))
#define MODSUB(x, y, bound) \
MUX(((int)(x)) - ((int)(y)) < 0, (x) - (y) + (bound), (x) - (y))
/* module add/sub, bound = 2^k */
#define MODADD_POW2(x, y, bound) (((x) + (y)) & ((bound) - 1))
#define MODSUB_POW2(x, y, bound) (((x) - (y)) & ((bound) - 1))
/* crc defines */
#define CRC8_INIT_VALUE 0xff /* Initial CRC8 checksum value */
#define CRC8_GOOD_VALUE 0x9f /* Good final CRC8 checksum value */
#define CRC16_INIT_VALUE 0xffff /* Initial CRC16 checksum value */
#define CRC16_GOOD_VALUE 0xf0b8 /* Good final CRC16 checksum value */
#define CRC32_INIT_VALUE 0xffffffff /* Initial CRC32 checksum value */
#define CRC32_GOOD_VALUE 0xdebb20e3 /* Good final CRC32 checksum value */
/* use for direct output of MAC address in printf etc */
#define MACF "%02x:%02x:%02x:%02x:%02x:%02x"
#define ETHERP_TO_MACF(ea) ((struct ether_addr *) (ea))->octet[0], \
((struct ether_addr *) (ea))->octet[1], \
((struct ether_addr *) (ea))->octet[2], \
((struct ether_addr *) (ea))->octet[3], \
((struct ether_addr *) (ea))->octet[4], \
((struct ether_addr *) (ea))->octet[5]
#define ETHER_TO_MACF(ea) (ea).octet[0], \
(ea).octet[1], \
(ea).octet[2], \
(ea).octet[3], \
(ea).octet[4], \
(ea).octet[5]
/* bcm_format_flags() bit description structure */
typedef struct bcm_bit_desc {
uint32 bit;
const char* name;
} bcm_bit_desc_t;
/* bcm_format_field */
typedef struct bcm_bit_desc_ex {
uint32 mask;
const bcm_bit_desc_t *bitfield;
} bcm_bit_desc_ex_t;
/* tag_ID/length/value_buffer tuple */
typedef struct bcm_tlv {
uint8 id;
uint8 len;
uint8 data[1];
} bcm_tlv_t;
/* Check that bcm_tlv_t fits into the given buflen */
#define bcm_valid_tlv(elt, buflen) ((buflen) >= 2 && (int)(buflen) >= (int)(2 + (elt)->len))
/* buffer length for ethernet address from bcm_ether_ntoa() */
#define ETHER_ADDR_STR_LEN 18 /* 18-bytes of Ethernet address buffer length */
/* crypto utility function */
/* 128-bit xor: *dst = *src1 xor *src2. dst1, src1 and src2 may have any alignment */
static INLINE void
xor_128bit_block(const uint8 *src1, const uint8 *src2, uint8 *dst)
{
if (
#ifdef __i386__
1 ||
#endif
(((uintptr)src1 | (uintptr)src2 | (uintptr)dst) & 3) == 0) {
/* ARM CM3 rel time: 1229 (727 if alignment check could be omitted) */
/* x86 supports unaligned. This version runs 6x-9x faster on x86. */
((uint32 *)dst)[0] = ((const uint32 *)src1)[0] ^ ((const uint32 *)src2)[0];
((uint32 *)dst)[1] = ((const uint32 *)src1)[1] ^ ((const uint32 *)src2)[1];
((uint32 *)dst)[2] = ((const uint32 *)src1)[2] ^ ((const uint32 *)src2)[2];
((uint32 *)dst)[3] = ((const uint32 *)src1)[3] ^ ((const uint32 *)src2)[3];
} else {
/* ARM CM3 rel time: 4668 (4191 if alignment check could be omitted) */
int k;
for (k = 0; k < 16; k++)
dst[k] = src1[k] ^ src2[k];
}
}
/* externs */
/* crc */
extern uint8 BCMROMFN(hndcrc8)(uint8 *p, uint nbytes, uint8 crc);
extern uint16 BCMROMFN(hndcrc16)(uint8 *p, uint nbytes, uint16 crc);
extern uint32 BCMROMFN(hndcrc32)(uint8 *p, uint nbytes, uint32 crc);
/* format/print */
#if defined(BCMDBG) || defined(DHD_DEBUG) || defined(BCMDBG_ERR) || defined(WLMSG_PRHDRS) || \
defined(WLMSG_PRPKT) || defined(WLMSG_ASSOC) || defined(BCMDBG_DUMP)
/* print out the value a field has: fields may have 1-32 bits and may hold any value */
extern int bcm_format_field(const bcm_bit_desc_ex_t *bd, uint32 field, char* buf, int len);
/* print out which bits in flags are set */
extern int bcm_format_flags(const bcm_bit_desc_t *bd, uint32 flags, char* buf, int len);
#endif
#if defined(BCMDBG) || defined(DHD_DEBUG) || defined(BCMDBG_ERR) || defined(WLMSG_PRHDRS) || \
defined(WLMSG_PRPKT) || defined(WLMSG_ASSOC) || defined(BCMDBG_DUMP) || \
defined(WLMEDIA_PEAKRATE)
extern int bcm_format_hex(char *str, const void *bytes, int len);
#endif
#ifdef BCMDBG
extern void deadbeef(void *p, uint len);
#endif
extern const char *bcm_crypto_algo_name(uint algo);
extern char *bcm_chipname(uint chipid, char *buf, uint len);
extern char *bcm_brev_str(uint32 brev, char *buf);
extern void printbig(char *buf);
extern void prhex(const char *msg, uchar *buf, uint len);
/* IE parsing */
extern bcm_tlv_t *BCMROMFN(bcm_next_tlv)(bcm_tlv_t *elt, int *buflen);
extern bcm_tlv_t *BCMROMFN(bcm_parse_tlvs)(void *buf, int buflen, uint key);
extern bcm_tlv_t *BCMROMFN(bcm_parse_ordered_tlvs)(void *buf, int buflen, uint key);
/* bcmerror */
extern const char *bcmerrorstr(int bcmerror);
extern bcm_tlv_t *BCMROMFN(bcm_parse_tlvs)(void *buf, int buflen, uint key);
/* multi-bool data type: set of bools, mbool is true if any is set */
typedef uint32 mbool;
#define mboolset(mb, bit) ((mb) |= (bit)) /* set one bool */
#define mboolclr(mb, bit) ((mb) &= ~(bit)) /* clear one bool */
#define mboolisset(mb, bit) (((mb) & (bit)) != 0) /* TRUE if one bool is set */
#define mboolmaskset(mb, mask, val) ((mb) = (((mb) & ~(mask)) | (val)))
/* generic datastruct to help dump routines */
struct fielddesc {
const char *nameandfmt;
uint32 offset;
uint32 len;
};
extern void bcm_binit(struct bcmstrbuf *b, char *buf, uint size);
extern void bcm_bprhex(struct bcmstrbuf *b, const char *msg, bool newline, uint8 *buf, int len);
extern void bcm_inc_bytes(uchar *num, int num_bytes, uint8 amount);
extern int bcm_cmp_bytes(const uchar *arg1, const uchar *arg2, uint8 nbytes);
extern void bcm_print_bytes(const char *name, const uchar *cdata, int len);
typedef uint32 (*bcmutl_rdreg_rtn)(void *arg0, uint arg1, uint32 offset);
extern uint bcmdumpfields(bcmutl_rdreg_rtn func_ptr, void *arg0, uint arg1, struct fielddesc *str,
char *buf, uint32 bufsize);
extern uint BCMROMFN(bcm_bitcount)(uint8 *bitmap, uint bytelength);
extern int bcm_bprintf(struct bcmstrbuf *b, const char *fmt, ...);
/* power conversion */
extern uint16 BCMROMFN(bcm_qdbm_to_mw)(uint8 qdbm);
extern uint8 BCMROMFN(bcm_mw_to_qdbm)(uint16 mw);
extern uint bcm_mkiovar(char *name, char *data, uint datalen, char *buf, uint len);
#ifdef BCMDBG_PKT /* pkt logging for debugging */
#define PKTLIST_SIZE 3000
#ifdef BCMDBG_PTRACE
#define PKTTRACE_MAX_BYTES 12
#define PKTTRACE_MAX_BITS (PKTTRACE_MAX_BYTES * NBBY)
enum pkttrace_info {
PKTLIST_PRECQ, /* Pkt in Prec Q */
PKTLIST_FAIL_PRECQ, /* Pkt failed to Q in PRECQ */
PKTLIST_DMAQ, /* Pkt in DMA Q */
PKTLIST_MI_TFS_RCVD, /* Received TX status */
PKTLIST_TXDONE, /* Pkt TX done */
PKTLIST_TXFAIL, /* Pkt TX failed */
PKTLIST_PKTFREE, /* pkt is freed */
PKTLIST_PRECREQ, /* Pkt requeued in precq */
PKTLIST_TXFIFO /* To trace in wlc_fifo */
};
#endif /* BCMDBG_PTRACE */
typedef struct pkt_dbginfo {
int line;
char *file;
void *pkt;
#ifdef BCMDBG_PTRACE
char pkt_trace[PKTTRACE_MAX_BYTES];
#endif /* BCMDBG_PTRACE */
} pkt_dbginfo_t;
typedef struct {
pkt_dbginfo_t list[PKTLIST_SIZE]; /* List of pointers to packets */
uint16 count; /* Total count of the packets */
} pktlist_info_t;
extern void pktlist_add(pktlist_info_t *pktlist, void *p, int len, char *file);
extern void pktlist_remove(pktlist_info_t *pktlist, void *p);
extern char* pktlist_dump(pktlist_info_t *pktlist, char *buf);
#ifdef BCMDBG_PTRACE
extern void pktlist_trace(pktlist_info_t *pktlist, void *pkt, uint16 bit);
#endif /* BCMDBG_PTRACE */
#endif /* BCMDBG_PKT */
unsigned int process_nvram_vars(char *varbuf, unsigned int len);
/* calculate a * b + c */
extern void bcm_uint64_multiple_add(uint32* r_high, uint32* r_low, uint32 a, uint32 b, uint32 c);
/* calculate a / b */
extern void bcm_uint64_divide(uint32* r, uint32 a_high, uint32 a_low, uint32 b);
/* calculate a >> b */
void bcm_uint64_right_shift(uint32* r, uint32 a_high, uint32 a_low, uint32 b);
#ifdef __cplusplus
}
#endif
#endif /* _bcmutils_h_ */

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/*
* Misc utility routines for WL and Apps
* This header file housing the define and function prototype use by
* both the wl driver, tools & Apps.
*
* $Copyright Open Broadcom Corporation$
*
* $Id: bcmwifi.h 374015 2012-12-11 08:55:11Z maheshd $
*/
#ifndef _bcmwifi_h_
#define _bcmwifi_h_
typedef uint16 chanspec_t;
#define CH_UPPER_SB 0x01
#define CH_LOWER_SB 0x02
#define CH_EWA_VALID 0x04
#define CH_20MHZ_APART 4
#define CH_10MHZ_APART 2
#define CH_5MHZ_APART 1
#define CH_MAX_2G_CHANNEL 14
#define WLC_MAX_2G_CHANNEL CH_MAX_2G_CHANNEL
#define MAXCHANNEL 224
#define CHSPEC_CTLOVLP(sp1, sp2, sep) \
(ABS(wf_chspec_ctlchan(sp1) - wf_chspec_ctlchan(sp2)) < (sep))
#define WL_CHANSPEC_CHAN_MASK 0x00ff
#define WL_CHANSPEC_CHAN_SHIFT 0
#define WL_CHANSPEC_CTL_SB_MASK 0x0300
#define WL_CHANSPEC_CTL_SB_SHIFT 8
#define WL_CHANSPEC_CTL_SB_LOWER 0x0100
#define WL_CHANSPEC_CTL_SB_UPPER 0x0200
#define WL_CHANSPEC_CTL_SB_NONE 0x0300
#define WL_CHANSPEC_BW_MASK 0x0C00
#define WL_CHANSPEC_BW_SHIFT 10
#define WL_CHANSPEC_BW_10 0x0400
#define WL_CHANSPEC_BW_20 0x0800
#define WL_CHANSPEC_BW_40 0x0C00
#define WL_CHANSPEC_BAND_MASK 0xf000
#define WL_CHANSPEC_BAND_SHIFT 12
#define WL_CHANSPEC_BAND_5G 0x1000
#define WL_CHANSPEC_BAND_2G 0x2000
#define INVCHANSPEC 255
#define WF_CHAN_FACTOR_2_4_G 4814
#define WF_CHAN_FACTOR_5_G 10000
#define WF_CHAN_FACTOR_4_G 8000
#define LOWER_20_SB(channel) (((channel) > CH_10MHZ_APART) ? ((channel) - CH_10MHZ_APART) : 0)
#define UPPER_20_SB(channel) (((channel) < (MAXCHANNEL - CH_10MHZ_APART)) ? \
((channel) + CH_10MHZ_APART) : 0)
#define CHSPEC_WLCBANDUNIT(chspec) (CHSPEC_IS5G(chspec) ? BAND_5G_INDEX : BAND_2G_INDEX)
#define CH20MHZ_CHSPEC(channel) (chanspec_t)((chanspec_t)(channel) | WL_CHANSPEC_BW_20 | \
WL_CHANSPEC_CTL_SB_NONE | (((channel) <= CH_MAX_2G_CHANNEL) ? \
WL_CHANSPEC_BAND_2G : WL_CHANSPEC_BAND_5G))
#define NEXT_20MHZ_CHAN(channel) (((channel) < (MAXCHANNEL - CH_20MHZ_APART)) ? \
((channel) + CH_20MHZ_APART) : 0)
#define CH40MHZ_CHSPEC(channel, ctlsb) (chanspec_t) \
((channel) | (ctlsb) | WL_CHANSPEC_BW_40 | \
((channel) <= CH_MAX_2G_CHANNEL ? WL_CHANSPEC_BAND_2G : \
WL_CHANSPEC_BAND_5G))
#define CHSPEC_CHANNEL(chspec) ((uint8)((chspec) & WL_CHANSPEC_CHAN_MASK))
#define CHSPEC_BAND(chspec) ((chspec) & WL_CHANSPEC_BAND_MASK)
#define CHSPEC_CTL_SB(chspec) ((chspec) & WL_CHANSPEC_CTL_SB_MASK)
#define CHSPEC_BW(chspec) ((chspec) & WL_CHANSPEC_BW_MASK)
#ifdef WL11N_20MHZONLY
#define CHSPEC_IS10(chspec) 0
#define CHSPEC_IS20(chspec) 1
#ifndef CHSPEC_IS40
#define CHSPEC_IS40(chspec) 0
#endif
#else
#define CHSPEC_IS10(chspec) (((chspec) & WL_CHANSPEC_BW_MASK) == WL_CHANSPEC_BW_10)
#define CHSPEC_IS20(chspec) (((chspec) & WL_CHANSPEC_BW_MASK) == WL_CHANSPEC_BW_20)
#ifndef CHSPEC_IS40
#define CHSPEC_IS40(chspec) (((chspec) & WL_CHANSPEC_BW_MASK) == WL_CHANSPEC_BW_40)
#endif
#endif
#define CHSPEC_IS5G(chspec) (((chspec) & WL_CHANSPEC_BAND_MASK) == WL_CHANSPEC_BAND_5G)
#define CHSPEC_IS2G(chspec) (((chspec) & WL_CHANSPEC_BAND_MASK) == WL_CHANSPEC_BAND_2G)
#define CHSPEC_SB_NONE(chspec) (((chspec) & WL_CHANSPEC_CTL_SB_MASK) == WL_CHANSPEC_CTL_SB_NONE)
#define CHSPEC_SB_UPPER(chspec) (((chspec) & WL_CHANSPEC_CTL_SB_MASK) == WL_CHANSPEC_CTL_SB_UPPER)
#define CHSPEC_SB_LOWER(chspec) (((chspec) & WL_CHANSPEC_CTL_SB_MASK) == WL_CHANSPEC_CTL_SB_LOWER)
#define CHSPEC_CTL_CHAN(chspec) ((CHSPEC_SB_LOWER(chspec)) ? \
(LOWER_20_SB(((chspec) & WL_CHANSPEC_CHAN_MASK))) : \
(UPPER_20_SB(((chspec) & WL_CHANSPEC_CHAN_MASK))))
#define CHSPEC2WLC_BAND(chspec) (CHSPEC_IS5G(chspec) ? WLC_BAND_5G : WLC_BAND_2G)
#define CHANSPEC_STR_LEN 8
#define WLC_MAXRATE 108
#define WLC_RATE_1M 2
#define WLC_RATE_2M 4
#define WLC_RATE_5M5 11
#define WLC_RATE_11M 22
#define WLC_RATE_6M 12
#define WLC_RATE_9M 18
#define WLC_RATE_12M 24
#define WLC_RATE_18M 36
#define WLC_RATE_24M 48
#define WLC_RATE_36M 72
#define WLC_RATE_48M 96
#define WLC_RATE_54M 108
#define WLC_2G_25MHZ_OFFSET 5
extern char * wf_chspec_ntoa(chanspec_t chspec, char *buf);
extern chanspec_t wf_chspec_aton(char *a);
extern bool wf_chspec_malformed(chanspec_t chanspec);
extern uint8 wf_chspec_ctlchan(chanspec_t chspec);
extern chanspec_t wf_chspec_ctlchspec(chanspec_t chspec);
extern int wf_mhz2channel(uint freq, uint start_factor);
extern int wf_channel2mhz(uint channel, uint start_factor);
#endif

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/*
* Misc utility routines for WL and Apps
* This header file housing the define and function prototype use by
* both the wl driver, tools & Apps.
*
* $Copyright Open Broadcom Corporation$
*
* $Id: bcmwifi_channels.h 309193 2012-01-19 00:03:57Z stafford $
*/
#ifndef _bcmwifi_channels_h_
#define _bcmwifi_channels_h_
/* A chanspec holds the channel number, band, bandwidth and control sideband */
typedef uint16 chanspec_t;
/* channel defines */
#define CH_UPPER_SB 0x01
#define CH_LOWER_SB 0x02
#define CH_EWA_VALID 0x04
#define CH_80MHZ_APART 16
#define CH_40MHZ_APART 8
#define CH_20MHZ_APART 4
#define CH_10MHZ_APART 2
#define CH_5MHZ_APART 1 /* 2G band channels are 5 Mhz apart */
#define CH_MAX_2G_CHANNEL 14 /* Max channel in 2G band */
#define MAXCHANNEL 224 /* max # supported channels. The max channel no is 216,
* this is that + 1 rounded up to a multiple of NBBY (8).
* DO NOT MAKE it > 255: channels are uint8's all over
*/
#define CHSPEC_CTLOVLP(sp1, sp2, sep) (ABS(wf_chspec_ctlchan(sp1) - wf_chspec_ctlchan(sp2)) < \
(sep))
#ifndef D11AC_IOTYPES
#define WL_CHANSPEC_CHAN_MASK 0x00ff
#define WL_CHANSPEC_CHAN_SHIFT 0
#define WL_CHANSPEC_CTL_SB_MASK 0x0300
#define WL_CHANSPEC_CTL_SB_SHIFT 8
#define WL_CHANSPEC_CTL_SB_LOWER 0x0100
#define WL_CHANSPEC_CTL_SB_UPPER 0x0200
#define WL_CHANSPEC_CTL_SB_NONE 0x0300
#define WL_CHANSPEC_BW_MASK 0x0C00
#define WL_CHANSPEC_BW_SHIFT 10
#define WL_CHANSPEC_BW_10 0x0400
#define WL_CHANSPEC_BW_20 0x0800
#define WL_CHANSPEC_BW_40 0x0C00
#define WL_CHANSPEC_BAND_MASK 0xf000
#define WL_CHANSPEC_BAND_SHIFT 12
#ifdef WL_CHANSPEC_BAND_5G
#undef WL_CHANSPEC_BAND_5G
#endif
#ifdef WL_CHANSPEC_BAND_2G
#undef WL_CHANSPEC_BAND_2G
#endif
#define WL_CHANSPEC_BAND_5G 0x1000
#define WL_CHANSPEC_BAND_2G 0x2000
#define INVCHANSPEC 255
/* channel defines */
#define LOWER_20_SB(channel) (((channel) > CH_10MHZ_APART) ? ((channel) - CH_10MHZ_APART) : 0)
#define UPPER_20_SB(channel) (((channel) < (MAXCHANNEL - CH_10MHZ_APART)) ? \
((channel) + CH_10MHZ_APART) : 0)
#define LL_20_SB(channel) (((channel) > 3 * CH_10MHZ_APART) ? ((channel) - 3 * CH_10MHZ_APART) : 0)
#define UU_20_SB(channel) (((channel) < (MAXCHANNEL - 3 * CH_10MHZ_APART)) ? \
((channel) + 3 * CH_10MHZ_APART) : 0)
#define LU_20_SB(channel) LOWER_20_SB(channel)
#define UL_20_SB(channel) UPPER_20_SB(channel)
#define CHSPEC_WLCBANDUNIT(chspec) (CHSPEC_IS5G(chspec) ? BAND_5G_INDEX : BAND_2G_INDEX)
#define CH20MHZ_CHSPEC(channel) (chanspec_t)((chanspec_t)(channel) | WL_CHANSPEC_BW_20 | \
WL_CHANSPEC_CTL_SB_NONE | (((channel) <= CH_MAX_2G_CHANNEL) ? \
WL_CHANSPEC_BAND_2G : WL_CHANSPEC_BAND_5G))
#define NEXT_20MHZ_CHAN(channel) (((channel) < (MAXCHANNEL - CH_20MHZ_APART)) ? \
((channel) + CH_20MHZ_APART) : 0)
#define CH40MHZ_CHSPEC(channel, ctlsb) (chanspec_t) \
((channel) | (ctlsb) | WL_CHANSPEC_BW_40 | \
((channel) <= CH_MAX_2G_CHANNEL ? WL_CHANSPEC_BAND_2G : \
WL_CHANSPEC_BAND_5G))
#define CHSPEC_CHANNEL(chspec) ((uint8)((chspec) & WL_CHANSPEC_CHAN_MASK))
#define CHSPEC_BAND(chspec) ((chspec) & WL_CHANSPEC_BAND_MASK)
/* chanspec stores radio channel & flags to indicate control channel location, i.e. upper/lower */
#define CHSPEC_CTL_SB(chspec) ((chspec) & WL_CHANSPEC_CTL_SB_MASK)
#define CHSPEC_BW(chspec) ((chspec) & WL_CHANSPEC_BW_MASK)
#ifdef WL11N_20MHZONLY
#define CHSPEC_IS10(chspec) 0
#define CHSPEC_IS20(chspec) 1
#ifndef CHSPEC_IS40
#define CHSPEC_IS40(chspec) 0
#endif
#else /* !WL11N_20MHZONLY */
#define CHSPEC_IS10(chspec) (((chspec) & WL_CHANSPEC_BW_MASK) == WL_CHANSPEC_BW_10)
#define CHSPEC_IS20(chspec) (((chspec) & WL_CHANSPEC_BW_MASK) == WL_CHANSPEC_BW_20)
#ifndef CHSPEC_IS40
#define CHSPEC_IS40(chspec) (((chspec) & WL_CHANSPEC_BW_MASK) == WL_CHANSPEC_BW_40)
#endif
#endif /* !WL11N_20MHZONLY */
#define CHSPEC_IS5G(chspec) (((chspec) & WL_CHANSPEC_BAND_MASK) == WL_CHANSPEC_BAND_5G)
#define CHSPEC_IS2G(chspec) (((chspec) & WL_CHANSPEC_BAND_MASK) == WL_CHANSPEC_BAND_2G)
#define CHSPEC_SB_NONE(chspec) (((chspec) & WL_CHANSPEC_CTL_SB_MASK) == WL_CHANSPEC_CTL_SB_NONE)
#define CHSPEC_SB_UPPER(chspec) (((chspec) & WL_CHANSPEC_CTL_SB_MASK) == WL_CHANSPEC_CTL_SB_UPPER)
#define CHSPEC_SB_LOWER(chspec) (((chspec) & WL_CHANSPEC_CTL_SB_MASK) == WL_CHANSPEC_CTL_SB_LOWER)
#define CHSPEC_CTL_CHAN(chspec) ((CHSPEC_SB_LOWER(chspec)) ? \
(LOWER_20_SB(((chspec) & WL_CHANSPEC_CHAN_MASK))) : \
(UPPER_20_SB(((chspec) & WL_CHANSPEC_CHAN_MASK))))
#define CHSPEC2WLC_BAND(chspec) (CHSPEC_IS5G(chspec) ? WLC_BAND_5G : WLC_BAND_2G)
#define CHANSPEC_STR_LEN 8
#else /* D11AC_IOTYPES */
#define WL_CHANSPEC_CHAN_MASK 0x00ff
#define WL_CHANSPEC_CHAN_SHIFT 0
#define WL_CHANSPEC_CHAN1_MASK 0x000f
#define WL_CHANSPEC_CHAN1_SHIFT 0
#define WL_CHANSPEC_CHAN2_MASK 0x00f0
#define WL_CHANSPEC_CHAN2_SHIFT 4
#define WL_CHANSPEC_CTL_SB_MASK 0x0700
#define WL_CHANSPEC_CTL_SB_SHIFT 8
#define WL_CHANSPEC_CTL_SB_LLL 0x0000
#define WL_CHANSPEC_CTL_SB_LLU 0x0100
#define WL_CHANSPEC_CTL_SB_LUL 0x0200
#define WL_CHANSPEC_CTL_SB_LUU 0x0300
#define WL_CHANSPEC_CTL_SB_ULL 0x0400
#define WL_CHANSPEC_CTL_SB_ULU 0x0500
#define WL_CHANSPEC_CTL_SB_UUL 0x0600
#define WL_CHANSPEC_CTL_SB_UUU 0x0700
#define WL_CHANSPEC_CTL_SB_LL WL_CHANSPEC_CTL_SB_LLL
#define WL_CHANSPEC_CTL_SB_LU WL_CHANSPEC_CTL_SB_LLU
#define WL_CHANSPEC_CTL_SB_UL WL_CHANSPEC_CTL_SB_LUL
#define WL_CHANSPEC_CTL_SB_UU WL_CHANSPEC_CTL_SB_LUU
#define WL_CHANSPEC_CTL_SB_L WL_CHANSPEC_CTL_SB_LLL
#define WL_CHANSPEC_CTL_SB_U WL_CHANSPEC_CTL_SB_LLU
#define WL_CHANSPEC_CTL_SB_LOWER WL_CHANSPEC_CTL_SB_LLL
#define WL_CHANSPEC_CTL_SB_UPPER WL_CHANSPEC_CTL_SB_LLU
#define WL_CHANSPEC_BW_MASK 0x3800
#define WL_CHANSPEC_BW_SHIFT 11
#define WL_CHANSPEC_BW_5 0x0000
#define WL_CHANSPEC_BW_10 0x0800
#define WL_CHANSPEC_BW_20 0x1000
#define WL_CHANSPEC_BW_40 0x1800
#define WL_CHANSPEC_BW_80 0x2000
#define WL_CHANSPEC_BW_160 0x2800
#define WL_CHANSPEC_BW_8080 0x3000
#define WL_CHANSPEC_BAND_MASK 0xc000
#define WL_CHANSPEC_BAND_SHIFT 14
#define WL_CHANSPEC_BAND_2G 0x0000
#define WL_CHANSPEC_BAND_3G 0x4000
#define WL_CHANSPEC_BAND_4G 0x8000
#define WL_CHANSPEC_BAND_5G 0xc000
#define INVCHANSPEC 255
/* channel defines */
#define LOWER_20_SB(channel) (((channel) > CH_10MHZ_APART) ? \
((channel) - CH_10MHZ_APART) : 0)
#define UPPER_20_SB(channel) (((channel) < (MAXCHANNEL - CH_10MHZ_APART)) ? \
((channel) + CH_10MHZ_APART) : 0)
#define LL_20_SB(channel) (((channel) > 3 * CH_10MHZ_APART) ? ((channel) - 3 * CH_10MHZ_APART) : 0)
#define UU_20_SB(channel) (((channel) < (MAXCHANNEL - 3 * CH_10MHZ_APART)) ? \
((channel) + 3 * CH_10MHZ_APART) : 0)
#define LU_20_SB(channel) LOWER_20_SB(channel)
#define UL_20_SB(channel) UPPER_20_SB(channel)
#define LOWER_40_SB(channel) ((channel) - CH_20MHZ_APART)
#define UPPER_40_SB(channel) ((channel) + CH_20MHZ_APART)
#define CHSPEC_WLCBANDUNIT(chspec) (CHSPEC_IS5G(chspec) ? BAND_5G_INDEX : BAND_2G_INDEX)
#define CH20MHZ_CHSPEC(channel) (chanspec_t)((chanspec_t)(channel) | WL_CHANSPEC_BW_20 | \
(((channel) <= CH_MAX_2G_CHANNEL) ? \
WL_CHANSPEC_BAND_2G : WL_CHANSPEC_BAND_5G))
#define NEXT_20MHZ_CHAN(channel) (((channel) < (MAXCHANNEL - CH_20MHZ_APART)) ? \
((channel) + CH_20MHZ_APART) : 0)
#define CH40MHZ_CHSPEC(channel, ctlsb) (chanspec_t) \
((channel) | (ctlsb) | WL_CHANSPEC_BW_40 | \
((channel) <= CH_MAX_2G_CHANNEL ? WL_CHANSPEC_BAND_2G : \
WL_CHANSPEC_BAND_5G))
#define CH80MHZ_CHSPEC(channel, ctlsb) (chanspec_t) \
((channel) | (ctlsb) | \
WL_CHANSPEC_BW_80 | WL_CHANSPEC_BAND_5G)
#define CH160MHZ_CHSPEC(channel, ctlsb) (chanspec_t) \
((channel) | (ctlsb) | \
WL_CHANSPEC_BW_160 | WL_CHANSPEC_BAND_5G)
/* simple MACROs to get different fields of chanspec */
#define CHSPEC_CHANNEL(chspec) ((uint8)((chspec) & WL_CHANSPEC_CHAN_MASK))
#define CHSPEC_CHAN1(chspec) ((chspec) & WL_CHANSPEC_CHAN1_MASK)
#define CHSPEC_CHAN2(chspec) ((chspec) & WL_CHANSPEC_CHAN2_MASK)
#define CHSPEC_BAND(chspec) ((chspec) & WL_CHANSPEC_BAND_MASK)
#define CHSPEC_CTL_SB(chspec) ((chspec) & WL_CHANSPEC_CTL_SB_MASK)
#define CHSPEC_BW(chspec) ((chspec) & WL_CHANSPEC_BW_MASK)
#ifdef WL11N_20MHZONLY
#define CHSPEC_IS10(chspec) 0
#define CHSPEC_IS20(chspec) 1
#ifndef CHSPEC_IS40
#define CHSPEC_IS40(chspec) 0
#endif
#ifndef CHSPEC_IS80
#define CHSPEC_IS80(chspec) 0
#endif
#ifndef CHSPEC_IS160
#define CHSPEC_IS160(chspec) 0
#endif
#ifndef CHSPEC_IS8080
#define CHSPEC_IS8080(chspec) 0
#endif
#else /* !WL11N_20MHZONLY */
#define CHSPEC_IS10(chspec) (((chspec) & WL_CHANSPEC_BW_MASK) == WL_CHANSPEC_BW_10)
#define CHSPEC_IS20(chspec) (((chspec) & WL_CHANSPEC_BW_MASK) == WL_CHANSPEC_BW_20)
#ifndef CHSPEC_IS40
#define CHSPEC_IS40(chspec) (((chspec) & WL_CHANSPEC_BW_MASK) == WL_CHANSPEC_BW_40)
#endif
#ifndef CHSPEC_IS80
#define CHSPEC_IS80(chspec) (((chspec) & WL_CHANSPEC_BW_MASK) == WL_CHANSPEC_BW_80)
#endif
#ifndef CHSPEC_IS160
#define CHSPEC_IS160(chspec) (((chspec) & WL_CHANSPEC_BW_MASK) == WL_CHANSPEC_BW_160)
#endif
#ifndef CHSPEC_IS8080
#define CHSPEC_IS8080(chspec) (((chspec) & WL_CHANSPEC_BW_MASK) == WL_CHANSPEC_BW_8080)
#endif
#endif /* !WL11N_20MHZONLY */
#define CHSPEC_IS5G(chspec) (((chspec) & WL_CHANSPEC_BAND_MASK) == WL_CHANSPEC_BAND_5G)
#define CHSPEC_IS2G(chspec) (((chspec) & WL_CHANSPEC_BAND_MASK) == WL_CHANSPEC_BAND_2G)
#define CHSPEC_SB_UPPER(chspec) \
((((chspec) & WL_CHANSPEC_CTL_SB_MASK) == WL_CHANSPEC_CTL_SB_UPPER) && \
(((chspec) & WL_CHANSPEC_BW_MASK) == WL_CHANSPEC_BW_40))
#define CHSPEC_SB_LOWER(chspec) \
((((chspec) & WL_CHANSPEC_CTL_SB_MASK) == WL_CHANSPEC_CTL_SB_LOWER) && \
(((chspec) & WL_CHANSPEC_BW_MASK) == WL_CHANSPEC_BW_40))
#define CHSPEC2WLC_BAND(chspec) (CHSPEC_IS5G(chspec) ? WLC_BAND_5G : WLC_BAND_2G)
/**
* Number of chars needed for wf_chspec_ntoa() destination character buffer.
*/
#define CHANSPEC_STR_LEN 20
/* Legacy Chanspec defines
* These are the defines for the previous format of the chanspec_t
*/
#define WL_LCHANSPEC_CHAN_MASK 0x00ff
#define WL_LCHANSPEC_CHAN_SHIFT 0
#define WL_LCHANSPEC_CTL_SB_MASK 0x0300
#define WL_LCHANSPEC_CTL_SB_SHIFT 8
#define WL_LCHANSPEC_CTL_SB_LOWER 0x0100
#define WL_LCHANSPEC_CTL_SB_UPPER 0x0200
#define WL_LCHANSPEC_CTL_SB_NONE 0x0300
#define WL_LCHANSPEC_BW_MASK 0x0C00
#define WL_LCHANSPEC_BW_SHIFT 10
#define WL_LCHANSPEC_BW_10 0x0400
#define WL_LCHANSPEC_BW_20 0x0800
#define WL_LCHANSPEC_BW_40 0x0C00
#define WL_LCHANSPEC_BAND_MASK 0xf000
#define WL_LCHANSPEC_BAND_SHIFT 12
#define WL_LCHANSPEC_BAND_5G 0x1000
#define WL_LCHANSPEC_BAND_2G 0x2000
#define LCHSPEC_CHANNEL(chspec) ((uint8)((chspec) & WL_LCHANSPEC_CHAN_MASK))
#define LCHSPEC_BAND(chspec) ((chspec) & WL_LCHANSPEC_BAND_MASK)
#define LCHSPEC_CTL_SB(chspec) ((chspec) & WL_LCHANSPEC_CTL_SB_MASK)
#define LCHSPEC_BW(chspec) ((chspec) & WL_LCHANSPEC_BW_MASK)
#define LCHSPEC_IS10(chspec) (((chspec) & WL_LCHANSPEC_BW_MASK) == WL_LCHANSPEC_BW_10)
#define LCHSPEC_IS20(chspec) (((chspec) & WL_LCHANSPEC_BW_MASK) == WL_LCHANSPEC_BW_20)
#define LCHSPEC_IS40(chspec) (((chspec) & WL_LCHANSPEC_BW_MASK) == WL_LCHANSPEC_BW_40)
#define LCHSPEC_IS5G(chspec) (((chspec) & WL_LCHANSPEC_BAND_MASK) == WL_LCHANSPEC_BAND_5G)
#define LCHSPEC_IS2G(chspec) (((chspec) & WL_LCHANSPEC_BAND_MASK) == WL_LCHANSPEC_BAND_2G)
#define LCHSPEC_CREATE(chan, band, bw, sb) ((uint16)((chan) | (sb) | (bw) | (band)))
#endif /* D11AC_IOTYPES */
/*
* WF_CHAN_FACTOR_* constants are used to calculate channel frequency
* given a channel number.
* chan_freq = chan_factor * 500Mhz + chan_number * 5
*/
/**
* Channel Factor for the starting frequence of 2.4 GHz channels.
* The value corresponds to 2407 MHz.
*/
#define WF_CHAN_FACTOR_2_4_G 4814 /* 2.4 GHz band, 2407 MHz */
/**
* Channel Factor for the starting frequence of 5 GHz channels.
* The value corresponds to 5000 MHz.
*/
#define WF_CHAN_FACTOR_5_G 10000 /* 5 GHz band, 5000 MHz */
/**
* Channel Factor for the starting frequence of 4.9 GHz channels.
* The value corresponds to 4000 MHz.
*/
#define WF_CHAN_FACTOR_4_G 8000 /* 4.9 GHz band for Japan */
#define WLC_2G_25MHZ_OFFSET 5 /* 2.4GHz band channel offset */
/**
* Convert chanspec to ascii string
*
* @param chspec chanspec format
* @param buf ascii string of chanspec
*
* @return pointer to buf with room for at least CHANSPEC_STR_LEN bytes
*
* @see CHANSPEC_STR_LEN
*/
extern char * wf_chspec_ntoa(chanspec_t chspec, char *buf);
/**
* Convert ascii string to chanspec
*
* @param a pointer to input string
*
* @return >= 0 if successful or 0 otherwise
*/
extern chanspec_t wf_chspec_aton(const char *a);
/**
* Verify the chanspec fields are valid.
*
* Verify the chanspec is using a legal set field values, i.e. that the chanspec
* specified a band, bw, ctl_sb and channel and that the combination could be
* legal given some set of circumstances.
*
* @param chanspec input chanspec to verify
*
* @return TRUE if the chanspec is malformed, FALSE if it looks good.
*/
extern bool wf_chspec_malformed(chanspec_t chanspec);
/**
* Verify the chanspec specifies a valid channel according to 802.11.
*
* @param chanspec input chanspec to verify
*
* @return TRUE if the chanspec is a valid 802.11 channel
*/
extern bool wf_chspec_valid(chanspec_t chanspec);
/**
* Return the primary (control) channel.
*
* This function returns the channel number of the primary 20MHz channel. For
* 20MHz channels this is just the channel number. For 40MHz or wider channels
* it is the primary 20MHz channel specified by the chanspec.
*
* @param chspec input chanspec
*
* @return Returns the channel number of the primary 20MHz channel
*/
extern uint8 wf_chspec_ctlchan(chanspec_t chspec);
/**
* Return the primary (control) chanspec.
*
* This function returns the chanspec of the primary 20MHz channel. For 20MHz
* channels this is just the chanspec. For 40MHz or wider channels it is the
* chanspec of the primary 20MHZ channel specified by the chanspec.
*
* @param chspec input chanspec
*
* @return Returns the chanspec of the primary 20MHz channel
*/
extern chanspec_t wf_chspec_ctlchspec(chanspec_t chspec);
/**
* Return a channel number corresponding to a frequency.
*
* This function returns the chanspec for the primary 40MHz of an 80MHz channel.
* The control sideband specifies the same 20MHz channel that the 80MHz channel is using
* as the primary 20MHz channel.
*/
extern chanspec_t wf_chspec_primary40_chspec(chanspec_t chspec);
/*
* Return the channel number for a given frequency and base frequency.
* The returned channel number is relative to the given base frequency.
* If the given base frequency is zero, a base frequency of 5 GHz is assumed for
* frequencies from 5 - 6 GHz, and 2.407 GHz is assumed for 2.4 - 2.5 GHz.
*
* Frequency is specified in MHz.
* The base frequency is specified as (start_factor * 500 kHz).
* Constants WF_CHAN_FACTOR_2_4_G, WF_CHAN_FACTOR_5_G are defined for
* 2.4 GHz and 5 GHz bands.
*
* The returned channel will be in the range [1, 14] in the 2.4 GHz band
* and [0, 200] otherwise.
* -1 is returned if the start_factor is WF_CHAN_FACTOR_2_4_G and the
* frequency is not a 2.4 GHz channel, or if the frequency is not and even
* multiple of 5 MHz from the base frequency to the base plus 1 GHz.
*
* Reference 802.11 REVma, section 17.3.8.3, and 802.11B section 18.4.6.2
*
* @param freq frequency in MHz
* @param start_factor base frequency in 500 kHz units, e.g. 10000 for 5 GHz
*
* @return Returns a channel number
*
* @see WF_CHAN_FACTOR_2_4_G
* @see WF_CHAN_FACTOR_5_G
*/
extern int wf_mhz2channel(uint freq, uint start_factor);
/**
* Return the center frequency in MHz of the given channel and base frequency.
*
* Return the center frequency in MHz of the given channel and base frequency.
* The channel number is interpreted relative to the given base frequency.
*
* The valid channel range is [1, 14] in the 2.4 GHz band and [0, 200] otherwise.
* The base frequency is specified as (start_factor * 500 kHz).
* Constants WF_CHAN_FACTOR_2_4_G, WF_CHAN_FACTOR_5_G are defined for
* 2.4 GHz and 5 GHz bands.
* The channel range of [1, 14] is only checked for a start_factor of
* WF_CHAN_FACTOR_2_4_G (4814).
* Odd start_factors produce channels on .5 MHz boundaries, in which case
* the answer is rounded down to an integral MHz.
* -1 is returned for an out of range channel.
*
* Reference 802.11 REVma, section 17.3.8.3, and 802.11B section 18.4.6.2
*
* @param channel input channel number
* @param start_factor base frequency in 500 kHz units, e.g. 10000 for 5 GHz
*
* @return Returns a frequency in MHz
*
* @see WF_CHAN_FACTOR_2_4_G
* @see WF_CHAN_FACTOR_5_G
*/
extern int wf_channel2mhz(uint channel, uint start_factor);
/**
* Convert ctl chan and bw to chanspec
*
* @param ctl_ch channel
* @param bw bandwidth
*
* @return > 0 if successful or 0 otherwise
*
*/
extern uint16 wf_channel2chspec(uint ctl_ch, uint bw);
extern uint wf_channel2freq(uint channel);
extern uint wf_freq2channel(uint freq);
#endif /* _bcmwifi_channels_h_ */

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/*
* Indices for 802.11 a/b/g/n/ac 1-3 chain symmetric transmit rates
*
* $Copyright Open Broadcom Corporation$
*
* $Id: bcmwifi_rates.h 5187 2012-06-29 06:17:50Z fsherstyuk $
*/
#ifndef _bcmwifi_rates_h_
#define _bcmwifi_rates_h_
#ifdef __cplusplus
extern "C" {
#endif /* __cplusplus */
#define WL_RATESET_SZ_DSSS 4
#define WL_RATESET_SZ_OFDM 8
#define WL_RATESET_SZ_HT_MCS 8
#define WL_RATESET_SZ_VHT_MCS 10
#define WL_TX_CHAINS_MAX 3
#define WL_RATE_DISABLED (-128) /* Power value corresponding to unsupported rate */
/* Transmit channel bandwidths */
typedef enum wl_tx_bw {
WL_TX_BW_20,
WL_TX_BW_40,
WL_TX_BW_80,
WL_TX_BW_20IN40,
WL_TX_BW_20IN80,
WL_TX_BW_40IN80,
WL_TX_BW_ALL
} wl_tx_bw_t;
/*
* Transmit modes.
* Not all modes are listed here, only those required for disambiguation. e.g. SPEXP is not listed
*/
typedef enum wl_tx_mode {
WL_TX_MODE_NONE,
WL_TX_MODE_STBC,
WL_TX_MODE_CDD,
WL_TX_MODE_TXBF,
WL_NUM_TX_MODES
} wl_tx_mode_t;
/* Number of transmit chains */
typedef enum wl_tx_chains {
WL_TX_CHAINS_1 = 1,
WL_TX_CHAINS_2,
WL_TX_CHAINS_3
} wl_tx_chains_t;
/* Number of transmit streams */
typedef enum wl_tx_nss {
WL_TX_NSS_1 = 1,
WL_TX_NSS_2,
WL_TX_NSS_3
} wl_tx_nss_t;
typedef enum clm_rates {
/************
* 1 chain *
************
*/
/* 1 Stream */
WL_RATE_1X1_DSSS_1 = 0,
WL_RATE_1X1_DSSS_2 = 1,
WL_RATE_1X1_DSSS_5_5 = 2,
WL_RATE_1X1_DSSS_11 = 3,
WL_RATE_1X1_OFDM_6 = 4,
WL_RATE_1X1_OFDM_9 = 5,
WL_RATE_1X1_OFDM_12 = 6,
WL_RATE_1X1_OFDM_18 = 7,
WL_RATE_1X1_OFDM_24 = 8,
WL_RATE_1X1_OFDM_36 = 9,
WL_RATE_1X1_OFDM_48 = 10,
WL_RATE_1X1_OFDM_54 = 11,
WL_RATE_1X1_MCS0 = 12,
WL_RATE_1X1_MCS1 = 13,
WL_RATE_1X1_MCS2 = 14,
WL_RATE_1X1_MCS3 = 15,
WL_RATE_1X1_MCS4 = 16,
WL_RATE_1X1_MCS5 = 17,
WL_RATE_1X1_MCS6 = 18,
WL_RATE_1X1_MCS7 = 19,
WL_RATE_1X1_VHT0SS1 = 12,
WL_RATE_1X1_VHT1SS1 = 13,
WL_RATE_1X1_VHT2SS1 = 14,
WL_RATE_1X1_VHT3SS1 = 15,
WL_RATE_1X1_VHT4SS1 = 16,
WL_RATE_1X1_VHT5SS1 = 17,
WL_RATE_1X1_VHT6SS1 = 18,
WL_RATE_1X1_VHT7SS1 = 19,
WL_RATE_1X1_VHT8SS1 = 20,
WL_RATE_1X1_VHT9SS1 = 21,
/************
* 2 chains *
************
*/
/* 1 Stream expanded + 1 */
WL_RATE_1X2_DSSS_1 = 22,
WL_RATE_1X2_DSSS_2 = 23,
WL_RATE_1X2_DSSS_5_5 = 24,
WL_RATE_1X2_DSSS_11 = 25,
WL_RATE_1X2_CDD_OFDM_6 = 26,
WL_RATE_1X2_CDD_OFDM_9 = 27,
WL_RATE_1X2_CDD_OFDM_12 = 28,
WL_RATE_1X2_CDD_OFDM_18 = 29,
WL_RATE_1X2_CDD_OFDM_24 = 30,
WL_RATE_1X2_CDD_OFDM_36 = 31,
WL_RATE_1X2_CDD_OFDM_48 = 32,
WL_RATE_1X2_CDD_OFDM_54 = 33,
WL_RATE_1X2_CDD_MCS0 = 34,
WL_RATE_1X2_CDD_MCS1 = 35,
WL_RATE_1X2_CDD_MCS2 = 36,
WL_RATE_1X2_CDD_MCS3 = 37,
WL_RATE_1X2_CDD_MCS4 = 38,
WL_RATE_1X2_CDD_MCS5 = 39,
WL_RATE_1X2_CDD_MCS6 = 40,
WL_RATE_1X2_CDD_MCS7 = 41,
WL_RATE_1X2_VHT0SS1 = 34,
WL_RATE_1X2_VHT1SS1 = 35,
WL_RATE_1X2_VHT2SS1 = 36,
WL_RATE_1X2_VHT3SS1 = 37,
WL_RATE_1X2_VHT4SS1 = 38,
WL_RATE_1X2_VHT5SS1 = 39,
WL_RATE_1X2_VHT6SS1 = 40,
WL_RATE_1X2_VHT7SS1 = 41,
WL_RATE_1X2_VHT8SS1 = 42,
WL_RATE_1X2_VHT9SS1 = 43,
/* 2 Streams */
WL_RATE_2X2_STBC_MCS0 = 44,
WL_RATE_2X2_STBC_MCS1 = 45,
WL_RATE_2X2_STBC_MCS2 = 46,
WL_RATE_2X2_STBC_MCS3 = 47,
WL_RATE_2X2_STBC_MCS4 = 48,
WL_RATE_2X2_STBC_MCS5 = 49,
WL_RATE_2X2_STBC_MCS6 = 50,
WL_RATE_2X2_STBC_MCS7 = 51,
WL_RATE_2X2_STBC_VHT0SS1 = 44,
WL_RATE_2X2_STBC_VHT1SS1 = 45,
WL_RATE_2X2_STBC_VHT2SS1 = 46,
WL_RATE_2X2_STBC_VHT3SS1 = 47,
WL_RATE_2X2_STBC_VHT4SS1 = 48,
WL_RATE_2X2_STBC_VHT5SS1 = 49,
WL_RATE_2X2_STBC_VHT6SS1 = 50,
WL_RATE_2X2_STBC_VHT7SS1 = 51,
WL_RATE_2X2_STBC_VHT8SS1 = 52,
WL_RATE_2X2_STBC_VHT9SS1 = 53,
WL_RATE_2X2_SDM_MCS8 = 54,
WL_RATE_2X2_SDM_MCS9 = 55,
WL_RATE_2X2_SDM_MCS10 = 56,
WL_RATE_2X2_SDM_MCS11 = 57,
WL_RATE_2X2_SDM_MCS12 = 58,
WL_RATE_2X2_SDM_MCS13 = 59,
WL_RATE_2X2_SDM_MCS14 = 60,
WL_RATE_2X2_SDM_MCS15 = 61,
WL_RATE_2X2_VHT0SS2 = 54,
WL_RATE_2X2_VHT1SS2 = 55,
WL_RATE_2X2_VHT2SS2 = 56,
WL_RATE_2X2_VHT3SS2 = 57,
WL_RATE_2X2_VHT4SS2 = 58,
WL_RATE_2X2_VHT5SS2 = 59,
WL_RATE_2X2_VHT6SS2 = 60,
WL_RATE_2X2_VHT7SS2 = 61,
WL_RATE_2X2_VHT8SS2 = 62,
WL_RATE_2X2_VHT9SS2 = 63,
/************
* 3 chains *
************
*/
/* 1 Stream expanded + 2 */
WL_RATE_1X3_DSSS_1 = 64,
WL_RATE_1X3_DSSS_2 = 65,
WL_RATE_1X3_DSSS_5_5 = 66,
WL_RATE_1X3_DSSS_11 = 67,
WL_RATE_1X3_CDD_OFDM_6 = 68,
WL_RATE_1X3_CDD_OFDM_9 = 69,
WL_RATE_1X3_CDD_OFDM_12 = 70,
WL_RATE_1X3_CDD_OFDM_18 = 71,
WL_RATE_1X3_CDD_OFDM_24 = 72,
WL_RATE_1X3_CDD_OFDM_36 = 73,
WL_RATE_1X3_CDD_OFDM_48 = 74,
WL_RATE_1X3_CDD_OFDM_54 = 75,
WL_RATE_1X3_CDD_MCS0 = 76,
WL_RATE_1X3_CDD_MCS1 = 77,
WL_RATE_1X3_CDD_MCS2 = 78,
WL_RATE_1X3_CDD_MCS3 = 79,
WL_RATE_1X3_CDD_MCS4 = 80,
WL_RATE_1X3_CDD_MCS5 = 81,
WL_RATE_1X3_CDD_MCS6 = 82,
WL_RATE_1X3_CDD_MCS7 = 83,
WL_RATE_1X3_VHT0SS1 = 76,
WL_RATE_1X3_VHT1SS1 = 77,
WL_RATE_1X3_VHT2SS1 = 78,
WL_RATE_1X3_VHT3SS1 = 79,
WL_RATE_1X3_VHT4SS1 = 80,
WL_RATE_1X3_VHT5SS1 = 81,
WL_RATE_1X3_VHT6SS1 = 82,
WL_RATE_1X3_VHT7SS1 = 83,
WL_RATE_1X3_VHT8SS1 = 84,
WL_RATE_1X3_VHT9SS1 = 85,
/* 2 Streams expanded + 1 */
WL_RATE_2X3_STBC_MCS0 = 86,
WL_RATE_2X3_STBC_MCS1 = 87,
WL_RATE_2X3_STBC_MCS2 = 88,
WL_RATE_2X3_STBC_MCS3 = 89,
WL_RATE_2X3_STBC_MCS4 = 90,
WL_RATE_2X3_STBC_MCS5 = 91,
WL_RATE_2X3_STBC_MCS6 = 92,
WL_RATE_2X3_STBC_MCS7 = 93,
WL_RATE_2X3_STBC_VHT0SS1 = 86,
WL_RATE_2X3_STBC_VHT1SS1 = 87,
WL_RATE_2X3_STBC_VHT2SS1 = 88,
WL_RATE_2X3_STBC_VHT3SS1 = 89,
WL_RATE_2X3_STBC_VHT4SS1 = 90,
WL_RATE_2X3_STBC_VHT5SS1 = 91,
WL_RATE_2X3_STBC_VHT6SS1 = 92,
WL_RATE_2X3_STBC_VHT7SS1 = 93,
WL_RATE_2X3_STBC_VHT8SS1 = 94,
WL_RATE_2X3_STBC_VHT9SS1 = 95,
WL_RATE_2X3_SDM_MCS8 = 96,
WL_RATE_2X3_SDM_MCS9 = 97,
WL_RATE_2X3_SDM_MCS10 = 98,
WL_RATE_2X3_SDM_MCS11 = 99,
WL_RATE_2X3_SDM_MCS12 = 100,
WL_RATE_2X3_SDM_MCS13 = 101,
WL_RATE_2X3_SDM_MCS14 = 102,
WL_RATE_2X3_SDM_MCS15 = 103,
WL_RATE_2X3_VHT0SS2 = 96,
WL_RATE_2X3_VHT1SS2 = 97,
WL_RATE_2X3_VHT2SS2 = 98,
WL_RATE_2X3_VHT3SS2 = 99,
WL_RATE_2X3_VHT4SS2 = 100,
WL_RATE_2X3_VHT5SS2 = 101,
WL_RATE_2X3_VHT6SS2 = 102,
WL_RATE_2X3_VHT7SS2 = 103,
WL_RATE_2X3_VHT8SS2 = 104,
WL_RATE_2X3_VHT9SS2 = 105,
/* 3 Streams */
WL_RATE_3X3_SDM_MCS16 = 106,
WL_RATE_3X3_SDM_MCS17 = 107,
WL_RATE_3X3_SDM_MCS18 = 108,
WL_RATE_3X3_SDM_MCS19 = 109,
WL_RATE_3X3_SDM_MCS20 = 110,
WL_RATE_3X3_SDM_MCS21 = 111,
WL_RATE_3X3_SDM_MCS22 = 112,
WL_RATE_3X3_SDM_MCS23 = 113,
WL_RATE_3X3_VHT0SS3 = 106,
WL_RATE_3X3_VHT1SS3 = 107,
WL_RATE_3X3_VHT2SS3 = 108,
WL_RATE_3X3_VHT3SS3 = 109,
WL_RATE_3X3_VHT4SS3 = 110,
WL_RATE_3X3_VHT5SS3 = 111,
WL_RATE_3X3_VHT6SS3 = 112,
WL_RATE_3X3_VHT7SS3 = 113,
WL_RATE_3X3_VHT8SS3 = 114,
WL_RATE_3X3_VHT9SS3 = 115,
/****************************
* TX Beamforming, 2 chains *
****************************
*/
/* 1 Stream expanded + 1 */
WL_RATE_1X2_TXBF_OFDM_6 = 116,
WL_RATE_1X2_TXBF_OFDM_9 = 117,
WL_RATE_1X2_TXBF_OFDM_12 = 118,
WL_RATE_1X2_TXBF_OFDM_18 = 119,
WL_RATE_1X2_TXBF_OFDM_24 = 120,
WL_RATE_1X2_TXBF_OFDM_36 = 121,
WL_RATE_1X2_TXBF_OFDM_48 = 122,
WL_RATE_1X2_TXBF_OFDM_54 = 123,
WL_RATE_1X2_TXBF_MCS0 = 124,
WL_RATE_1X2_TXBF_MCS1 = 125,
WL_RATE_1X2_TXBF_MCS2 = 126,
WL_RATE_1X2_TXBF_MCS3 = 127,
WL_RATE_1X2_TXBF_MCS4 = 128,
WL_RATE_1X2_TXBF_MCS5 = 129,
WL_RATE_1X2_TXBF_MCS6 = 130,
WL_RATE_1X2_TXBF_MCS7 = 131,
WL_RATE_1X2_TXBF_VHT0SS1 = 124,
WL_RATE_1X2_TXBF_VHT1SS1 = 125,
WL_RATE_1X2_TXBF_VHT2SS1 = 126,
WL_RATE_1X2_TXBF_VHT3SS1 = 127,
WL_RATE_1X2_TXBF_VHT4SS1 = 128,
WL_RATE_1X2_TXBF_VHT5SS1 = 129,
WL_RATE_1X2_TXBF_VHT6SS1 = 130,
WL_RATE_1X2_TXBF_VHT7SS1 = 131,
WL_RATE_1X2_TXBF_VHT8SS1 = 132,
WL_RATE_1X2_TXBF_VHT9SS1 = 133,
/* 2 Streams */
WL_RATE_2X2_TXBF_SDM_MCS8 = 134,
WL_RATE_2X2_TXBF_SDM_MCS9 = 135,
WL_RATE_2X2_TXBF_SDM_MCS10 = 136,
WL_RATE_2X2_TXBF_SDM_MCS11 = 137,
WL_RATE_2X2_TXBF_SDM_MCS12 = 138,
WL_RATE_2X2_TXBF_SDM_MCS13 = 139,
WL_RATE_2X2_TXBF_SDM_MCS14 = 140,
WL_RATE_2X2_TXBF_SDM_MCS15 = 141,
WL_RATE_2X2_TXBF_VHT0SS2 = 134,
WL_RATE_2X2_TXBF_VHT1SS2 = 135,
WL_RATE_2X2_TXBF_VHT2SS2 = 136,
WL_RATE_2X2_TXBF_VHT3SS2 = 137,
WL_RATE_2X2_TXBF_VHT4SS2 = 138,
WL_RATE_2X2_TXBF_VHT5SS2 = 139,
WL_RATE_2X2_TXBF_VHT6SS2 = 140,
WL_RATE_2X2_TXBF_VHT7SS2 = 141,
/****************************
* TX Beamforming, 3 chains *
****************************
*/
/* 1 Stream expanded + 2 */
WL_RATE_1X3_TXBF_OFDM_6 = 142,
WL_RATE_1X3_TXBF_OFDM_9 = 143,
WL_RATE_1X3_TXBF_OFDM_12 = 144,
WL_RATE_1X3_TXBF_OFDM_18 = 145,
WL_RATE_1X3_TXBF_OFDM_24 = 146,
WL_RATE_1X3_TXBF_OFDM_36 = 147,
WL_RATE_1X3_TXBF_OFDM_48 = 148,
WL_RATE_1X3_TXBF_OFDM_54 = 149,
WL_RATE_1X3_TXBF_MCS0 = 150,
WL_RATE_1X3_TXBF_MCS1 = 151,
WL_RATE_1X3_TXBF_MCS2 = 152,
WL_RATE_1X3_TXBF_MCS3 = 153,
WL_RATE_1X3_TXBF_MCS4 = 154,
WL_RATE_1X3_TXBF_MCS5 = 155,
WL_RATE_1X3_TXBF_MCS6 = 156,
WL_RATE_1X3_TXBF_MCS7 = 157,
WL_RATE_1X3_TXBF_VHT0SS1 = 150,
WL_RATE_1X3_TXBF_VHT1SS1 = 151,
WL_RATE_1X3_TXBF_VHT2SS1 = 152,
WL_RATE_1X3_TXBF_VHT3SS1 = 153,
WL_RATE_1X3_TXBF_VHT4SS1 = 154,
WL_RATE_1X3_TXBF_VHT5SS1 = 155,
WL_RATE_1X3_TXBF_VHT6SS1 = 156,
WL_RATE_1X3_TXBF_VHT7SS1 = 157,
WL_RATE_1X3_TXBF_VHT8SS1 = 158,
WL_RATE_1X3_TXBF_VHT9SS1 = 159,
/* 2 Streams expanded + 1 */
WL_RATE_2X3_TXBF_SDM_MCS8 = 160,
WL_RATE_2X3_TXBF_SDM_MCS9 = 161,
WL_RATE_2X3_TXBF_SDM_MCS10 = 162,
WL_RATE_2X3_TXBF_SDM_MCS11 = 163,
WL_RATE_2X3_TXBF_SDM_MCS12 = 164,
WL_RATE_2X3_TXBF_SDM_MCS13 = 165,
WL_RATE_2X3_TXBF_SDM_MCS14 = 166,
WL_RATE_2X3_TXBF_SDM_MCS15 = 167,
WL_RATE_2X3_TXBF_VHT0SS2 = 160,
WL_RATE_2X3_TXBF_VHT1SS2 = 161,
WL_RATE_2X3_TXBF_VHT2SS2 = 162,
WL_RATE_2X3_TXBF_VHT3SS2 = 163,
WL_RATE_2X3_TXBF_VHT4SS2 = 164,
WL_RATE_2X3_TXBF_VHT5SS2 = 165,
WL_RATE_2X3_TXBF_VHT6SS2 = 166,
WL_RATE_2X3_TXBF_VHT7SS2 = 167,
WL_RATE_2X3_TXBF_VHT8SS2 = 168,
WL_RATE_2X3_TXBF_VHT9SS2 = 169,
/* 3 Streams */
WL_RATE_3X3_TXBF_SDM_MCS16 = 170,
WL_RATE_3X3_TXBF_SDM_MCS17 = 171,
WL_RATE_3X3_TXBF_SDM_MCS18 = 172,
WL_RATE_3X3_TXBF_SDM_MCS19 = 173,
WL_RATE_3X3_TXBF_SDM_MCS20 = 174,
WL_RATE_3X3_TXBF_SDM_MCS21 = 175,
WL_RATE_3X3_TXBF_SDM_MCS22 = 176,
WL_RATE_3X3_TXBF_SDM_MCS23 = 177,
WL_RATE_3X3_TXBF_VHT0SS3 = 170,
WL_RATE_3X3_TXBF_VHT1SS3 = 171,
WL_RATE_3X3_TXBF_VHT2SS3 = 172,
WL_RATE_3X3_TXBF_VHT3SS3 = 173,
WL_RATE_3X3_TXBF_VHT4SS3 = 174,
WL_RATE_3X3_TXBF_VHT5SS3 = 175,
WL_RATE_3X3_TXBF_VHT6SS3 = 176,
WL_RATE_3X3_TXBF_VHT7SS3 = 177
} clm_rates_t;
/* Number of rate codes */
#define WL_NUMRATES 178
#ifdef __cplusplus
}
#endif /* __cplusplus */
#endif /* _bcmwifi_rates_h_ */

523
external/cache/sources/wl/include/dbus.h vendored Normal file
View File

@ -0,0 +1,523 @@
/*
* Dongle BUS interface Abstraction layer
* target serial buses like USB, SDIO, SPI, etc.
*
* $Copyright Open 2008 Broadcom Corporation$
*
* $Id: dbus.h 394558 2013-04-03 00:11:01Z $
*/
#ifndef __DBUS_H__
#define __DBUS_H__
#include "typedefs.h"
#define DBUSTRACE(args)
#define DBUSERR(args)
#define DBUSINFO(args)
#define DBUSTRACE(args)
#define DBUSDBGLOCK(args)
#define BCM_OTP_SIZE_43236 84 /* number of 16 bit values */
#define BCM_OTP_SW_RGN_43236 24 /* start offset of SW config region */
#define BCM_OTP_ADDR_43236 0x18000800 /* address of otp base */
#define ERR_CBMASK_TXFAIL 0x00000001
#define ERR_CBMASK_RXFAIL 0x00000002
#define ERR_CBMASK_ALL 0xFFFFFFFF
#define DBUS_CBCTL_WRITE 0
#define DBUS_CBCTL_READ 1
#define DBUS_TX_RETRY_LIMIT 3 /* retries for failed txirb */
#define DBUS_TX_TIMEOUT_INTERVAL 250 /* timeout for txirb complete, in ms */
#define DBUS_BUFFER_SIZE_TX 32000
#define DBUS_BUFFER_SIZE_RX 24000
#define DBUS_BUFFER_SIZE_TX_NOAGG 2048
#define DBUS_BUFFER_SIZE_RX_NOAGG 2048
enum {
DBUS_OK = 0,
DBUS_ERR = -200,
DBUS_ERR_TIMEOUT,
DBUS_ERR_DISCONNECT,
DBUS_ERR_NODEVICE,
DBUS_ERR_UNSUPPORTED,
DBUS_ERR_PENDING,
DBUS_ERR_NOMEM,
DBUS_ERR_TXFAIL,
DBUS_ERR_TXTIMEOUT,
DBUS_ERR_TXDROP,
DBUS_ERR_RXFAIL,
DBUS_ERR_RXDROP,
DBUS_ERR_TXCTLFAIL,
DBUS_ERR_RXCTLFAIL,
DBUS_ERR_REG_PARAM,
DBUS_STATUS_CANCELLED,
DBUS_ERR_NVRAM,
DBUS_JUMBO_NOMATCH,
DBUS_JUMBO_BAD_FORMAT,
DBUS_NVRAM_NONTXT
};
/* DBUS types */
enum {
DBUS_USB,
DBUS_SDIO,
DBUS_SPI,
DBUS_UNKNOWN
};
enum dbus_state {
DBUS_STATE_DL_PENDING,
DBUS_STATE_DL_DONE,
DBUS_STATE_UP,
DBUS_STATE_DOWN,
DBUS_STATE_PNP_FWDL,
DBUS_STATE_DISCONNECT,
DBUS_STATE_SLEEP
};
enum dbus_pnp_state {
DBUS_PNP_DISCONNECT,
DBUS_PNP_SLEEP,
DBUS_PNP_RESUME
};
enum dbus_file {
DBUS_FIRMWARE,
DBUS_NVFILE
};
typedef enum _DEVICE_SPEED {
INVALID_SPEED = -1,
LOW_SPEED = 1, /* USB 1.1: 1.5 Mbps */
FULL_SPEED, /* USB 1.1: 12 Mbps */
HIGH_SPEED, /* USB 2.0: 480 Mbps */
SUPER_SPEED, /* USB 3.0: 4.8 Gbps */
} DEVICE_SPEED;
typedef struct {
int bustype;
int vid;
int pid;
int devid;
int chiprev; /* chip revsion number */
int mtu;
int nchan; /* Data Channels */
int has_2nd_bulk_in_ep;
} dbus_attrib_t;
/* FIX: Account for errors related to DBUS;
* Let upper layer account for packets/bytes
*/
typedef struct {
uint32 rx_errors;
uint32 tx_errors;
uint32 rx_dropped;
uint32 tx_dropped;
} dbus_stats_t;
/*
* Configurable BUS parameters
*/
typedef struct {
bool rxctl_deferrespok;
} dbus_config_t;
/*
* External Download Info
*/
typedef struct dbus_extdl {
uint8 *fw;
int fwlen;
uint8 *vars;
int varslen;
} dbus_extdl_t;
struct dbus_callbacks;
struct exec_parms;
typedef void *(*probe_cb_t)(void *arg, const char *desc, uint32 bustype, uint32 hdrlen);
typedef void (*disconnect_cb_t)(void *arg);
typedef void *(*exec_cb_t)(struct exec_parms *args);
/* Client callbacks registered during dbus_attach() */
typedef struct dbus_callbacks {
void (*send_complete)(void *cbarg, void *info, int status);
void (*recv_buf)(void *cbarg, uint8 *buf, int len);
void (*recv_pkt)(void *cbarg, void *pkt);
void (*txflowcontrol)(void *cbarg, bool onoff);
void (*errhandler)(void *cbarg, int err);
void (*ctl_complete)(void *cbarg, int type, int status);
void (*state_change)(void *cbarg, int state);
void *(*pktget)(void *cbarg, uint len, bool send);
void (*pktfree)(void *cbarg, void *p, bool send);
} dbus_callbacks_t;
struct dbus_pub;
struct bcmstrbuf;
struct dbus_irb;
struct dbus_irb_rx;
struct dbus_irb_tx;
struct dbus_intf_callbacks;
typedef struct {
void* (*attach)(struct dbus_pub *pub, void *cbarg, struct dbus_intf_callbacks *cbs);
void (*detach)(struct dbus_pub *pub, void *bus);
int (*up)(void *bus);
int (*down)(void *bus);
int (*send_irb)(void *bus, struct dbus_irb_tx *txirb);
int (*recv_irb)(void *bus, struct dbus_irb_rx *rxirb);
int (*cancel_irb)(void *bus, struct dbus_irb_tx *txirb);
int (*send_ctl)(void *bus, uint8 *buf, int len);
int (*recv_ctl)(void *bus, uint8 *buf, int len);
int (*get_stats)(void *bus, dbus_stats_t *stats);
int (*get_attrib)(void *bus, dbus_attrib_t *attrib);
int (*pnp)(void *bus, int evnt);
int (*remove)(void *bus);
int (*resume)(void *bus);
int (*suspend)(void *bus);
int (*stop)(void *bus);
int (*reset)(void *bus);
/* Access to bus buffers directly */
void *(*pktget)(void *bus, int len);
void (*pktfree)(void *bus, void *pkt);
int (*iovar_op)(void *bus, const char *name, void *params, int plen, void *arg, int len,
bool set);
void (*dump)(void *bus, struct bcmstrbuf *strbuf);
int (*set_config)(void *bus, dbus_config_t *config);
int (*get_config)(void *bus, dbus_config_t *config);
bool (*device_exists)(void *bus);
bool (*dlneeded)(void *bus);
int (*dlstart)(void *bus, uint8 *fw, int len);
int (*dlrun)(void *bus);
bool (*recv_needed)(void *bus);
void *(*exec_rxlock)(void *bus, exec_cb_t func, struct exec_parms *args);
void *(*exec_txlock)(void *bus, exec_cb_t func, struct exec_parms *args);
int (*tx_timer_init)(void *bus);
int (*tx_timer_start)(void *bus, uint timeout);
int (*tx_timer_stop)(void *bus);
int (*sched_dpc)(void *bus);
int (*lock)(void *bus);
int (*unlock)(void *bus);
int (*sched_probe_cb)(void *bus);
int (*shutdown)(void *bus);
int (*recv_stop)(void *bus);
int (*recv_resume)(void *bus);
int (*recv_irb_from_ep)(void *bus, struct dbus_irb_rx *rxirb, uint ep_idx);
int (*readreg)(void *bus, uint32 regaddr, int datalen, uint32 *value);
/* Add from the bottom */
} dbus_intf_t;
typedef struct dbus_pub {
struct osl_info *osh;
dbus_stats_t stats;
dbus_attrib_t attrib;
enum dbus_state busstate;
DEVICE_SPEED device_speed;
int ntxq, nrxq, rxsize;
void *bus;
struct shared_info *sh;
void *dev_info;
} dbus_pub_t;
#define BUS_INFO(bus, type) (((type *) bus)->pub->bus)
#define ALIGNED_LOCAL_VARIABLE(var, align) \
uint8 buffer[SDALIGN+64]; \
uint8 *var = (uint8 *)(((uintptr)&buffer[0]) & ~(align-1)) + align;
/* IO Request Block (IRB) */
typedef struct dbus_irb {
struct dbus_irb *next; /* it's casted from dbus_irb_tx or dbus_irb_rx struct */
} dbus_irb_t;
/* General info for all BUS */
typedef struct dbus_irbq {
dbus_irb_t *head;
dbus_irb_t *tail;
int cnt;
} dbus_irbq_t;
typedef struct dbus_irb_rx {
struct dbus_irb irb; /* Must be first */
uint8 *buf;
int buf_len;
int actual_len;
void *pkt;
void *info;
void *arg;
} dbus_irb_rx_t;
typedef struct dbus_irb_tx {
struct dbus_irb irb; /* Must be first */
uint8 *buf;
int len;
void *pkt;
int retry_count;
void *info;
void *arg;
void *send_buf; /* linear bufffer for LINUX when aggreagtion is enabled */
} dbus_irb_tx_t;
/* DBUS interface callbacks are different from user callbacks
* so, internally, different info can be passed to upper layer
*/
typedef struct dbus_intf_callbacks {
void (*send_irb_timeout)(void *cbarg, dbus_irb_tx_t *txirb);
void (*send_irb_complete)(void *cbarg, dbus_irb_tx_t *txirb, int status);
void (*recv_irb_complete)(void *cbarg, dbus_irb_rx_t *rxirb, int status);
void (*errhandler)(void *cbarg, int err);
void (*ctl_complete)(void *cbarg, int type, int status);
void (*state_change)(void *cbarg, int state);
bool (*isr)(void *cbarg, bool *wantdpc);
bool (*dpc)(void *cbarg, bool bounded);
void (*watchdog)(void *cbarg);
void *(*pktget)(void *cbarg, uint len, bool send);
void (*pktfree)(void *cbarg, void *p, bool send);
struct dbus_irb* (*getirb)(void *cbarg, bool send);
void (*rxerr_indicate)(void *cbarg, bool on);
} dbus_intf_callbacks_t;
#if defined(EHCI_FASTPATH_TX) || defined(EHCI_FASTPATH_RX)
#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 0))
/* Backward compatibility */
typedef unsigned int gfp_t;
#define dma_pool pci_pool
#define dma_pool_create(name, dev, size, align, alloc) \
pci_pool_create(name, dev, size, align, alloc, GFP_DMA | GFP_ATOMIC)
#define dma_pool_destroy(pool) pci_pool_destroy(pool)
#define dma_pool_alloc(pool, flags, handle) pci_pool_alloc(pool, flags, handle)
#define dma_pool_free(pool, vaddr, addr) pci_pool_free(pool, vaddr, addr)
#define dma_map_single(dev, addr, size, dir) pci_map_single(dev, addr, size, dir)
#define dma_unmap_single(dev, hnd, size, dir) pci_unmap_single(dev, hnd, size, dir)
#define DMA_FROM_DEVICE PCI_DMA_FROMDEVICE
#define DMA_TO_DEVICE PCI_DMA_TODEVICE
#endif /* (LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 0)) */
/* Availability of these functions varies (when present, they have two arguments) */
#ifndef hc32_to_cpu
#define hc32_to_cpu(x) le32_to_cpu(x)
#define cpu_to_hc32(x) cpu_to_le32(x)
typedef unsigned int __hc32;
#else
#error Two-argument functions needed
#endif
/* Private USB opcode base */
#define EHCI_FASTPATH 0x31
#define EHCI_SET_EP_BYPASS EHCI_FASTPATH
#define EHCI_SET_BYPASS_CB (EHCI_FASTPATH + 1)
#define EHCI_SET_BYPASS_DEV (EHCI_FASTPATH + 2)
#define EHCI_DUMP_STATE (EHCI_FASTPATH + 3)
#define EHCI_SET_BYPASS_POOL (EHCI_FASTPATH + 4)
#define EHCI_CLR_EP_BYPASS (EHCI_FASTPATH + 5)
/*
* EHCI QTD structure (hardware and extension)
* NOTE that is does not need to (and does not) match its kernel counterpart
*/
#define EHCI_QTD_NBUFFERS 5
#define EHCI_QTD_ALIGN 32
#define EHCI_BULK_PACKET_SIZE 512
#define EHCI_QTD_XACTERR_MAX 32
struct ehci_qtd {
/* Hardware map */
volatile uint32_t qtd_next;
volatile uint32_t qtd_altnext;
volatile uint32_t qtd_status;
#define EHCI_QTD_GET_BYTES(x) (((x)>>16) & 0x7fff)
#define EHCI_QTD_IOC 0x00008000
#define EHCI_QTD_GET_CERR(x) (((x)>>10) & 0x3)
#define EHCI_QTD_SET_CERR(x) ((x) << 10)
#define EHCI_QTD_GET_PID(x) (((x)>>8) & 0x3)
#define EHCI_QTD_SET_PID(x) ((x) << 8)
#define EHCI_QTD_ACTIVE 0x80
#define EHCI_QTD_HALTED 0x40
#define EHCI_QTD_BUFERR 0x20
#define EHCI_QTD_BABBLE 0x10
#define EHCI_QTD_XACTERR 0x08
#define EHCI_QTD_MISSEDMICRO 0x04
volatile uint32_t qtd_buffer[EHCI_QTD_NBUFFERS];
volatile uint32_t qtd_buffer_hi[EHCI_QTD_NBUFFERS];
/* Implementation extension */
dma_addr_t qtd_self; /* own hardware address */
struct ehci_qtd *obj_next; /* software link to the next QTD */
void *rpc; /* pointer to the rpc buffer */
size_t length; /* length of the data in the buffer */
void *buff; /* pointer to the reassembly buffer */
int xacterrs; /* retry counter for qtd xact error */
} __attribute__ ((aligned(EHCI_QTD_ALIGN)));
#define EHCI_NULL __constant_cpu_to_le32(1) /* HW null pointer shall be odd */
#define SHORT_READ_Q(token) (EHCI_QTD_GET_BYTES(token) != 0 && EHCI_QTD_GET_PID(token) == 1)
/* Queue Head */
/* NOTE This structure is slightly different from the one in the kernel; but needs to stay
* compatible
*/
struct ehci_qh {
/* Hardware map */
volatile uint32_t qh_link;
volatile uint32_t qh_endp;
volatile uint32_t qh_endphub;
volatile uint32_t qh_curqtd;
/* QTD overlay */
volatile uint32_t ow_next;
volatile uint32_t ow_altnext;
volatile uint32_t ow_status;
volatile uint32_t ow_buffer [EHCI_QTD_NBUFFERS];
volatile uint32_t ow_buffer_hi [EHCI_QTD_NBUFFERS];
/* Extension (should match the kernel layout) */
dma_addr_t unused0;
void *unused1;
struct list_head unused2;
struct ehci_qtd *dummy;
struct ehci_qh *unused3;
struct ehci_hcd *unused4;
#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 0))
struct kref unused5;
unsigned unused6;
uint8_t unused7;
/* periodic schedule info */
uint8_t unused8;
uint8_t unused9;
uint8_t unused10;
uint16_t unused11;
uint16_t unused12;
uint16_t unused13;
struct usb_device *unused14;
#else
unsigned unused5;
u8 unused6;
/* periodic schedule info */
u8 unused7;
u8 unused8;
u8 unused9;
unsigned short unused10;
unsigned short unused11;
#define NO_FRAME ((unsigned short)~0)
#ifdef EHCI_QUIRK_FIX
struct usb_device *unused12;
#endif /* EHCI_QUIRK_FIX */
#endif /* (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 0)) */
struct ehci_qtd *first_qtd;
/* Link to the first QTD; this is an optimized equivalent of the qtd_list field */
/* NOTE that ehci_qh in ehci.h shall reserve this word */
} __attribute__ ((aligned(EHCI_QTD_ALIGN)));
#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 0))
/* The corresponding structure in the kernel is used to get the QH */
struct hcd_dev { /* usb_device.hcpriv points to this */
struct list_head unused0;
struct list_head unused1;
/* array of QH pointers */
void *ep[32];
};
#endif /* (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 0)) */
#endif /* EHCI_FASTPATH_TX || EHCI_FASTPATH_RX */
/*
* Public Bus Function Interface
*/
extern int dbus_register(int vid, int pid, probe_cb_t prcb, disconnect_cb_t discb, void *prarg,
void *param1, void *param2);
extern int dbus_deregister(void);
extern dbus_pub_t *dbus_attach(struct osl_info *osh, int rxsize, int nrxq, int ntxq,
void *cbarg, dbus_callbacks_t *cbs, dbus_extdl_t *extdl, struct shared_info *sh);
extern void dbus_detach(dbus_pub_t *pub);
extern int dbus_up(dbus_pub_t *pub);
extern int dbus_down(dbus_pub_t *pub);
extern int dbus_stop(dbus_pub_t *pub);
extern int dbus_shutdown(dbus_pub_t *pub);
extern void dbus_flowctrl_rx(dbus_pub_t *pub, bool on);
extern int dbus_send_buf(dbus_pub_t *pub, uint8 *buf, int len, void *info);
extern int dbus_send_pkt(dbus_pub_t *pub, void *pkt, void *info);
extern int dbus_send_ctl(dbus_pub_t *pub, uint8 *buf, int len);
extern int dbus_recv_ctl(dbus_pub_t *pub, uint8 *buf, int len);
extern int dbus_recv_bulk(dbus_pub_t *pub, uint32 ep_idx);
extern int dbus_get_stats(dbus_pub_t *pub, dbus_stats_t *stats);
extern int dbus_get_attrib(dbus_pub_t *pub, dbus_attrib_t *attrib);
extern int dbus_get_device_speed(dbus_pub_t *pub);
extern int dbus_set_config(dbus_pub_t *pub, dbus_config_t *config);
extern int dbus_get_config(dbus_pub_t *pub, dbus_config_t *config);
extern void * dbus_get_devinfo(dbus_pub_t *pub);
extern void *dbus_pktget(dbus_pub_t *pub, int len);
extern void dbus_pktfree(dbus_pub_t *pub, void* pkt);
extern int dbus_set_errmask(dbus_pub_t *pub, uint32 mask);
extern int dbus_pnp_sleep(dbus_pub_t *pub);
extern int dbus_pnp_resume(dbus_pub_t *pub, int *fw_reload);
extern int dbus_pnp_disconnect(dbus_pub_t *pub);
extern int dbus_iovar_op(dbus_pub_t *pub, const char *name,
void *params, int plen, void *arg, int len, bool set);
extern void *dhd_dbus_txq(const dbus_pub_t *pub);
extern uint dhd_dbus_hdrlen(const dbus_pub_t *pub);
extern void dbus_flowctrl_tx(void *dbi, bool on);
#if defined(BCM_REQUEST_FW)
extern void *dbus_get_fw_nvfile(int devid, uint8 **fw, int *fwlen, int type,
uint16 boardtype, uint16 boardrev);
extern void dbus_release_fw_nvfile(void *firmware);
#endif /* #if defined(BCM_REQUEST_FW) */
/*
* Bus specific Interface
* Implemented by dbus_usb.c/dbus_sdio.c
*/
extern int dbus_bus_register(int vid, int pid, probe_cb_t prcb, disconnect_cb_t discb, void *prarg,
dbus_intf_t **intf, void *param1, void *param2);
extern int dbus_bus_deregister(void);
extern void dbus_bus_fw_get(void *bus, uint8 **fw, int *fwlen, int *decomp);
/*
* Bus-specific and OS-specific Interface
* Implemented by dbus_usb_[linux/ndis].c/dbus_sdio_[linux/ndis].c
*/
extern int dbus_bus_osl_register(int vid, int pid, probe_cb_t prcb, disconnect_cb_t discb,
void *prarg, dbus_intf_t **intf, void *param1, void *param2);
extern int dbus_bus_osl_deregister(void);
extern int dbus_bus_osl_hw_register(int vid, int pid, probe_cb_t prcb, disconnect_cb_t discb,
void *prarg, dbus_intf_t **intf);
extern int dbus_bus_osl_hw_deregister(void);
extern uint usbdev_bulkin_eps(void);
#if defined(EHCI_FASTPATH_TX) || defined(EHCI_FASTPATH_RX)
extern int optimize_qtd_fill_with_rpc(const dbus_pub_t *pub, int epn, struct ehci_qtd *qtd,
void *rpc, int token, int len);
extern int optimize_submit_async(struct ehci_qtd *qtd, int epn);
extern struct ehci_qtd *optimize_ehci_qtd_alloc(gfp_t flags);
extern void optimize_ehci_qtd_free(struct ehci_qtd *qtd);
extern void optimize_submit_rx_request(const dbus_pub_t *pub, int epn, struct ehci_qtd *qtd_in,
void *buf);
#endif /* EHCI_FASTPATH_TX || EHCI_FASTPATH_RX */
#endif /* __DBUS_H__ */

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/*
* Definitions for ioctls to access DHD iovars.
* Based on wlioctl.h (for Broadcom 802.11abg driver).
* (Moves towards generic ioctls for BCM drivers/iovars.)
*
* Definitions subject to change without notice.
*
* $Copyright Open Broadcom Corporation$
*
* $Id: dhdioctl.h 327775 2012-04-16 18:54:32Z $
*/
#ifndef _dhdioctl_h_
#define _dhdioctl_h_
#include <typedefs.h>
/* require default structure packing */
#define BWL_DEFAULT_PACKING
#include <packed_section_start.h>
/* Linux network driver ioctl encoding */
typedef struct dhd_ioctl {
uint cmd; /* common ioctl definition */
void *buf; /* pointer to user buffer */
uint len; /* length of user buffer */
bool set; /* get or set request (optional) */
uint used; /* bytes read or written (optional) */
uint needed; /* bytes needed (optional) */
uint driver; /* to identify target driver */
} dhd_ioctl_t;
/* Underlying BUS definition */
enum {
BUS_TYPE_USB = 0, /* for USB dongles */
BUS_TYPE_SDIO /* for SDIO dongles */
};
/* per-driver magic numbers */
#define DHD_IOCTL_MAGIC 0x00444944
/* bump this number if you change the ioctl interface */
#define DHD_IOCTL_VERSION 1
#define DHD_IOCTL_MAXLEN 8192 /* max length ioctl buffer required */
#define DHD_IOCTL_SMLEN 256 /* "small" length ioctl buffer required */
/* common ioctl definitions */
#define DHD_GET_MAGIC 0
#define DHD_GET_VERSION 1
#define DHD_GET_VAR 2
#define DHD_SET_VAR 3
/* message levels */
#define DHD_ERROR_VAL 0x0001
#define DHD_TRACE_VAL 0x0002
#define DHD_INFO_VAL 0x0004
#define DHD_DATA_VAL 0x0008
#define DHD_CTL_VAL 0x0010
#define DHD_TIMER_VAL 0x0020
#define DHD_HDRS_VAL 0x0040
#define DHD_BYTES_VAL 0x0080
#define DHD_INTR_VAL 0x0100
#define DHD_LOG_VAL 0x0200
#define DHD_GLOM_VAL 0x0400
#define DHD_EVENT_VAL 0x0800
#define DHD_BTA_VAL 0x1000
#if 0 && (NDISVER >= 0x0630) && 1
#define DHD_SCAN_VAL 0x2000
#else
#define DHD_ISCAN_VAL 0x2000
#endif
#define DHD_ARPOE_VAL 0x4000
#ifdef SDTEST
/* For pktgen iovar */
typedef struct dhd_pktgen {
uint version; /* To allow structure change tracking */
uint freq; /* Max ticks between tx/rx attempts */
uint count; /* Test packets to send/rcv each attempt */
uint print; /* Print counts every <print> attempts */
uint total; /* Total packets (or bursts) */
uint minlen; /* Minimum length of packets to send */
uint maxlen; /* Maximum length of packets to send */
uint numsent; /* Count of test packets sent */
uint numrcvd; /* Count of test packets received */
uint numfail; /* Count of test send failures */
uint mode; /* Test mode (type of test packets) */
uint stop; /* Stop after this many tx failures */
} dhd_pktgen_t;
/* Version in case structure changes */
#define DHD_PKTGEN_VERSION 2
/* Type of test packets to use */
#define DHD_PKTGEN_ECHO 1 /* Send echo requests */
#define DHD_PKTGEN_SEND 2 /* Send discard packets */
#define DHD_PKTGEN_RXBURST 3 /* Request dongle send N packets */
#define DHD_PKTGEN_RECV 4 /* Continuous rx from continuous tx dongle */
#endif /* SDTEST */
/* Enter idle immediately (no timeout) */
#define DHD_IDLE_IMMEDIATE (-1)
/* Values for idleclock iovar: other values are the sd_divisor to use when idle */
#define DHD_IDLE_ACTIVE 0 /* Do not request any SD clock change when idle */
#define DHD_IDLE_STOP (-1) /* Request SD clock be stopped (and use SD1 mode) */
/* require default structure packing */
#include <packed_section_end.h>
#endif /* _dhdioctl_h_ */

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/*
* $Copyright Open Broadcom Corporation$
*
* $Id: epivers.h.in,v 13.33 2010-09-08 22:08:53 csm Exp $
*
*/
#ifndef _epivers_h_
#define _epivers_h_
#define EPI_MAJOR_VERSION 6
#define EPI_MINOR_VERSION 37
#define EPI_RC_NUMBER 32
#define EPI_INCREMENTAL_NUMBER 0
#define EPI_BUILD_NUMBER 1
#define EPI_VERSION 6, 37, 32, 0
#define EPI_VERSION_NUM 0x06252000
#define EPI_VERSION_DEV 6.37.32
/* Driver Version String, ASCII, 32 chars max */
#ifdef BCMINTERNAL
#define EPI_VERSION_STR "6.37.32 (TOB) (r410874 BCMINT)"
#else
#ifdef WLTEST
#define EPI_VERSION_STR "6.37.32 (TOB) (r410874 WLTEST)"
#else
#define EPI_VERSION_STR "6.37.32 (TOB) (r410874)"
#endif
#endif /* BCMINTERNAL */
#endif /* _epivers_h_ */

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/*
* $Copyright Open Broadcom Corporation$
*
* $Id: epivers.h.in,v 13.33 2010-09-08 22:08:53 $
*
*/
#ifndef _epivers_h_
#define _epivers_h_
#define EPI_MAJOR_VERSION @EPI_MAJOR_VERSION@
#define EPI_MINOR_VERSION @EPI_MINOR_VERSION@
#define EPI_RC_NUMBER @EPI_RC_NUMBER@
#define EPI_INCREMENTAL_NUMBER @EPI_INCREMENTAL_NUMBER@
#define EPI_BUILD_NUMBER @EPI_BUILD_NUMBER@
#define EPI_VERSION @EPI_VERSION@
#define EPI_VERSION_NUM @EPI_VERSION_NUM@
#define EPI_VERSION_DEV @EPI_VERSION_DEV@
#define EPI_VERSION_STR "@EPI_VERSION_STR@@EPI_VERSION_TYPE@ (@VC_VERSION_NUM@)"
#endif

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#! /bin/bash
#
# Create the epivers.h file from epivers.h.in
#
# Epivers.h version support svn/sparse/gclient workspaces
#
# $Id: epivers.sh 389101 2013-03-05 17:23:14Z $
#
# Version generation works off of svn property HeadURL, if
# not set it keys its versions from current svn workspace or
# via .gclient_info deps contents
#
# GetCompVer.py return value and action needed
# i. trunk => use current date as version string
# ii. local => use SVNURL expanded by HeadURL keyword
# iii. <tag> => use it as as is
# (some components can override and say give me native ver)
# iv. empty =>
# a) If TAG is specified use it
# a) If no TAG is specified use date
#
# Contact: Prakash Dhavali
# Contact: hnd-software-scm-list
#
# If the version header file already exists, increment its build number.
# Otherwise, create a new file.
if [ -f epivers.h ]; then
# If REUSE_VERSION is set, epivers iteration is not incremented
# This can be used precommit and continuous integration projects
if [ -n "$REUSE_VERSION" ]; then
echo "Previous epivers.h exists. Skipping version increment"
exit 0
fi
build=$(grep EPI_BUILD_NUMBER epivers.h | sed -e "s,.*BUILD_NUMBER[ ]*,,")
build=$(expr ${build} + 1)
echo build=${build}
sed -e "s,.*_BUILD_NUMBER.*,#define EPI_BUILD_NUMBER ${build}," \
< epivers.h > epivers.h.new
cp -p epivers.h epivers.h.prev
mv epivers.h.new epivers.h
exit 0
else # epivers.h doesn't exist
SVNCMD=${SVNCMD:-"svn --non-interactive"}
SRCBASE=${SRCBASE:-..}
NULL=/dev/null
[ -z "$VERBOSE" ] || NULL=/dev/stderr
# Check for the in file, if not there we're in the wrong directory
if [ ! -f epivers.h.in ]; then
echo "ERROR: No epivers.h.in found"
exit 1
fi
# Following SVNURL should be expanded on checkout
SVNURL='$HeadURL: http://svn.sj.broadcom.com/svn/wlansvn/proj/tags/AARDVARK/AARDVARK_REL_6_30_254/src/include/epivers.sh $'
# .gclient_info is created by gclient checkout/sync steps
# and contains "DEPS='<deps-url1> <deps-url2> ..." entry
GCLIENT_INFO=${GCLIENT_INFO:-${SRCBASE}/../.gclient_info}
# In gclient, derive SVNURL from gclient_info file
if [ -s "${GCLIENT_INFO}" ]; then
source ${GCLIENT_INFO}
if [ -z "$DEPS" ]; then
echo "ERROR: DEPS entry missing in $GCLIENT_INFO"
exit 1
else
for dep in $DEPS; do
SVNURL=${SVNURL:-$dep}
# Set SVNURL to first DEPS with /tags/ (if any)
if [[ $dep == */tags/* ]]; then
SVNURL=$dep
echo "INFO: Found gclient DEPS: $SVNURL"
break
fi
done
fi
elif [ -f "${GCLIENT_INFO}" ]; then
echo "ERROR: $GCLIENT_INFO exists, but it is empty"
exit 1
fi
# If SVNURL isn't expanded, extract it from svn info
if echo "$SVNURL" | egrep -vq 'HeadURL.*epivers.sh.*|http://.*/DEPS'; then
[ -n "$VERBOSE" ] && \
echo "DBG: SVN URL ($SVNURL) wasn't expanded. Getting it from svn info"
SVNURL=$($SVNCMD info epivers.sh 2> $NULL | egrep "^URL:")
fi
if echo "${TAG}" | grep -q "_BRANCH_\|_TWIG_"; then
branchtag=$TAG
else
branchtag=""
fi
# If this is a tagged build, use the tag to supply the numbers
# Tag should be in the form
# <NAME>_REL_<MAJ>_<MINOR>
# or
# <NAME>_REL_<MAJ>_<MINOR>_RC<RCNUM>
# or
# <NAME>_REL_<MAJ>_<MINOR>_RC<RCNUM>_<INCREMENTAL>
MERGERLOG=${SRCBASE}/../merger_sources.log
GETCOMPVER=getcompver.py
GETCOMPVER_NET=/projects/hnd_software/gallery/src/tools/build/$GETCOMPVER
GETCOMPVER_NET_WIN=Z:${GETCOMPVER_NET}
#
# If there is a local copy GETCOMPVER use it ahead of network copy
#
if [ -s "$GETCOMPVER" ]; then
GETCOMPVER_PATH="$GETCOMPVER"
elif [ -s "${SRCBASE}/../src/tools/build/$GETCOMPVER" ]; then
GETCOMPVER_PATH="${SRCBASE}/../src/tools/build/$GETCOMPVER"
elif [ -s "$GETCOMPVER_NET" ]; then
GETCOMPVER_PATH="$GETCOMPVER_NET"
elif [ -s "$GETCOMPVER_NET_WIN" ]; then
GETCOMPVER_PATH="$GETCOMPVER_NET_WIN"
fi
#
# If $GETCOMPVER isn't found, fetch it from SVN
# (this should be very rare)
#
if [ ! -s "$GETCOMPVER_PATH" ]; then
[ -n "$VERBOSE" ] && \
echo "DBG: Fetching $GETCOMPVER from trunk"
$SVNCMD export -q \
^/proj/trunk/src/tools/build/${GETCOMPVER} \
${GETCOMPVER} 2> $NULL
GETCOMPVER_PATH=$GETCOMPVER
fi
# Now get tag for src/include from automerger log
[ -n "$VERBOSE" ] && \
echo "DBG: python $GETCOMPVER_PATH $MERGERLOG src/include"
COMPTAG=$(python $GETCOMPVER_PATH $MERGERLOG src/include 2> $NULL | sed -e 's/[[:space:]]*//g')
echo "DBG: Component Tag String Derived = $COMPTAG"
# Process COMPTAG values
# Rule:
# If trunk is returned, use date as component tag
# If LOCAL_COMPONENT is returned, use SVN URL to get native tag
# If component is returned or empty, assign it to SVNTAG
# GetCompVer.py return value and action needed
# i. trunk => use current date as version string
# ii. local => use SVNURL expanded by HeadURL keyword
# iii. <tag> => use it as as is
# iv. empty =>
# a) If TAG is specified use it
# a) If no TAG is specified use SVNURL from HeadURL
SVNURL_VER=false
if [ "$COMPTAG" == "" ]; then
SVNURL_VER=true
elif [ "$COMPTAG" == "LOCAL_COMPONENT" ]; then
SVNURL_VER=true
elif [ "$COMPTAG" == "trunk" ]; then
SVNTAG=$(date '+TRUNKCOMP_REL_%Y_%m_%d')
else
SVNTAG=$COMPTAG
fi
# Given SVNURL path conventions or naming conventions, derive SVNTAG
# TO-DO: SVNTAG derivation logic can move to a central common API
# TO-DO: ${SRCBASE}/tools/build/svnurl2tag.sh
if [ "$SVNURL_VER" == "true" ]; then
case "${SVNURL}" in
*_BRANCH_*)
SVNTAG=$(echo $SVNURL | tr '/' '\n' | awk '/_BRANCH_/{printf "%s",$1}')
;;
*_TWIG_*)
SVNTAG=$(echo $SVNURL | tr '/' '\n' | awk '/_TWIG_/{printf "%s",$1}')
;;
*_REL_*)
SVNTAG=$(echo $SVNURL | tr '/' '\n' | awk '/_REL_/{printf "%s",$1}')
;;
*/branches/*)
SVNTAG=${SVNURL#*/branches/}
SVNTAG=${SVNTAG%%/*}
;;
*/proj/tags/*|*/deps/tags/*)
SVNTAG=${SVNURL#*/tags/*/}
SVNTAG=${SVNTAG%%/*}
;;
*/trunk/*)
SVNTAG=$(date '+TRUNKURL_REL_%Y_%m_%d')
;;
*)
SVNTAG=$(date '+OTHER_REL_%Y_%m_%d')
;;
esac
echo "DBG: Native Tag String Derived from URL: $SVNTAG"
else
echo "DBG: Native Tag String Derived: $SVNTAG"
fi
TAG=${SVNTAG}
# Normalize the branch name portion to "D11" in case it has underscores in it
branch_name=$(expr match "$TAG" '\(.*\)_\(BRANCH\|TWIG\|REL\)_.*')
TAG=$(echo $TAG | sed -e "s%^$branch_name%D11%")
# Split the tag into an array on underbar or whitespace boundaries.
IFS="_ " tag=(${TAG})
unset IFS
tagged=1
if [ ${#tag[*]} -eq 0 ]; then
tag=($(date '+TOT REL %Y %m %d 0 %y'));
# reconstruct a TAG from the date
TAG=${tag[0]}_${tag[1]}_${tag[2]}_${tag[3]}_${tag[4]}_${tag[5]}
tagged=0
fi
# Allow environment variable to override values.
# Missing values default to 0
#
maj=${EPI_MAJOR_VERSION:-${tag[2]:-0}}
min=${EPI_MINOR_VERSION:-${tag[3]:-0}}
rcnum=${EPI_RC_NUMBER:-${tag[4]:-0}}
# If increment field is 0, set it to date suffix if on TOB
if [ -n "$branchtag" ]; then
[ "${tag[5]:-0}" -eq 0 ] && echo "Using date suffix for incr"
today=${EPI_DATE_STR:-$(date '+%Y%m%d')}
incremental=${EPI_INCREMENTAL_NUMBER:-${tag[5]:-${today:-0}}}
else
incremental=${EPI_INCREMENTAL_NUMBER:-${tag[5]:-0}}
fi
origincr=${EPI_INCREMENTAL_NUMBER:-${tag[5]:-0}}
build=${EPI_BUILD_NUMBER:-0}
# Strip 'RC' from front of rcnum if present
rcnum=${rcnum/#RC/}
# strip leading zero off the number (otherwise they look like octal)
maj=${maj/#0/}
min=${min/#0/}
rcnum=${rcnum/#0/}
incremental=${incremental/#0/}
origincr=${origincr/#0/}
build=${build/#0/}
# some numbers may now be null. replace with with zero.
maj=${maj:-0}
min=${min:-0}
rcnum=${rcnum:-0}
incremental=${incremental:-0}
origincr=${origincr:-0}
build=${build:-0}
if [ -n "$EPI_VERSION_NUM" ]; then
vernum=$EPI_VERSION_NUM
elif [ ${tagged} -eq 1 ]; then
# vernum is 32chars max
vernum=$(printf "0x%02x%02x%02x%02x" ${maj} ${min} ${rcnum} ${origincr})
else
vernum=$(printf "0x00%02x%02x%02x" ${tag[7]} ${min} ${rcnum})
fi
# make sure the size of vernum is under 32 bits.
# Otherwise, truncate. The string will keep full information.
vernum=${vernum:0:10}
# build the string directly from the tag, irrespective of its length
# remove the name , the tag type, then replace all _ by .
tag_ver_str=${TAG/${tag[0]}_}
tag_ver_str=${tag_ver_str/${tag[1]}_}
tag_ver_str=${tag_ver_str//_/.}
# record tag type
tagtype=
if [ "${tag[1]}" = "BRANCH" -o "${tag[1]}" = "TWIG" ]; then
tagtype=" (TOB)"
echo "tag type: $tagtype"
fi
echo "Effective version string: $tag_ver_str"
if [ "$(uname -s)" == "Darwin" ]; then
# Mac does not like 2-digit numbers so convert the number to single
# digit. 5.100 becomes 5.1
if [ $min -gt 99 ]; then
minmac=$(expr $min / 100)
else
minmac=$min
fi
epi_ver_dev="${maj}.${minmac}.0"
else
epi_ver_dev="${maj}.${min}.${rcnum}"
fi
# Finally get version control revision number of <SRCBASE> (if any)
vc_version_num=$($SVNCMD info ${SRCBASE} 2> $NULL | awk -F': ' '/^Last Changed Rev: /{printf "%s", $2}')
# OK, go do it
echo "maj=${maj}, min=${min}, rc=${rcnum}, inc=${incremental}, build=${build}"
sed \
-e "s;@EPI_MAJOR_VERSION@;${maj};" \
-e "s;@EPI_MINOR_VERSION@;${min};" \
-e "s;@EPI_RC_NUMBER@;${rcnum};" \
-e "s;@EPI_INCREMENTAL_NUMBER@;${incremental};" \
-e "s;@EPI_BUILD_NUMBER@;${build};" \
-e "s;@EPI_VERSION@;${maj}, ${min}, ${rcnum}, ${incremental};" \
-e "s;@EPI_VERSION_STR@;${tag_ver_str};" \
-e "s;@EPI_VERSION_TYPE@;${tagtype};" \
-e "s;@VERSION_TYPE@;${tagtype};" \
-e "s;@EPI_VERSION_NUM@;${vernum};" \
-e "s;@EPI_VERSION_DEV@;${epi_ver_dev};" \
-e "s;@VC_VERSION_NUM@;r${vc_version_num};" \
< epivers.h.in > epivers.h
# In shared workspaces across different platforms, ensure that
# windows generated file is made platform neutral without CRLF
if uname -s | egrep -i -q "cygwin"; then
dos2unix epivers.h > $NULL 2>&1
fi
fi # epivers.h

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external/cache/sources/wl/include/event_log.h vendored Normal file
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/*
* EVENT_LOG system definitions
*
* $Copyright Open Broadcom Corporation$
*
* $Id: event_log.h 241182 2011-02-17 21:50:03Z $
*/
#ifndef _EVENT_LOG_H_
#define _EVENT_LOG_H_
/* Set a maximum number of sets here. It is not dynamic for
* efficiency of the EVENT_LOG calls.
*/
#define NUM_EVENT_LOG_SETS 4
/* Define new event log tags here */
#define EVENT_LOG_TAG_NULL 0 /* Special null tag */
#define EVENT_LOG_TAG_TS 1 /* Special timestamp tag */
#define EVENT_LOG_TAG_BUS_OOB 2
#define EVENT_LOG_TAG_BUS_STATE 3
#define EVENT_LOG_TAG_BUS_PROTO 4
#define EVENT_LOG_TAG_BUS_CTL 5
#define EVENT_LOG_TAG_BUS_EVENT 6
#define EVENT_LOG_TAG_BUS_PKT 7
#define EVENT_LOG_TAG_BUS_FRAME 8
#define EVENT_LOG_TAG_BUS_DESC 9
#define EVENT_LOG_TAG_BUS_SETUP 10
#define EVENT_LOG_TAG_BUS_MISC 11
#define EVENT_LOG_TAG_MAX 11
/* Flags for tag control */
#define EVENT_LOG_TAG_FLAG_NONE 0
#define EVENT_LOG_TAG_FLAG_LOG 0x80
#define EVENT_LOG_TAG_FLAG_PRINT 0x40
#define EVENT_LOG_TAG_FLAG_MASK 0x3f
/* We make sure that the block size will fit in a single packet
* (allowing for a bit of overhead on each packet
*/
#define EVENT_LOG_MAX_BLOCK_SIZE 1400
/*
* There are multiple levels of objects define here:
* event_log_set - a set of buffers
* event log groups - every event log call is part of just one. All
* event log calls in a group are handled the
* same way. Each event log group is associated
* with an event log set or is off.
*/
#ifndef __ASSEMBLER__
/* On the external system where the dumper is we need to make sure
* that these types are the same size as they are on the ARM the
* produced them
*/
#ifdef EVENT_LOG_DUMPER
#define _EL_BLOCK_PTR uint32
#define _EL_TYPE_PTR uint32
#define _EL_SET_PTR uint32
#define _EL_TOP_PTR uint32
#else
#define _EL_BLOCK_PTR struct event_log_block *
#define _EL_TYPE_PTR uint32 *
#define _EL_SET_PTR struct event_log_set **
#define _EL_TOP_PTR struct event_log_top *
#endif /* EVENT_LOG_DUMPER */
/* Each event log entry has a type. The type is the LAST word of the
* event log. The printing code walks the event entries in reverse
* order to find the first entry.
*/
typedef union event_log_hdr {
struct {
uint8 tag; /* Event_log entry tag */
uint8 count; /* Count of 4-byte entries */
uint16 fmt_num; /* Format number */
};
uint32 t; /* Type cheat */
} event_log_hdr_t;
/* Event log sets (a logical circurlar buffer) consist of one or more
* event_log_blocks. The blocks themselves form a logical circular
* list. The log entries are placed in each event_log_block until it
* is full. Logging continues with the next event_log_block in the
* event_set until the last event_log_block is reached and then
* logging starts over with the first event_log_block in the
* event_set.
*/
typedef struct event_log_block {
_EL_BLOCK_PTR next_block;
_EL_BLOCK_PTR prev_block;
_EL_TYPE_PTR end_ptr;
/* Start of packet sent for log tracing */
uint16 pktlen; /* Size of rest of block */
uint16 count; /* Logtrace counter */
uint32 timestamp; /* Timestamp at start of use */
uint32 event_logs;
} event_log_block_t;
/* There can be multiple event_sets with each logging a set of
* associated events (i.e, "fast" and "slow" events).
*/
typedef struct event_log_set {
_EL_BLOCK_PTR first_block; /* Pointer to first event_log block */
_EL_BLOCK_PTR last_block; /* Pointer to last event_log block */
_EL_BLOCK_PTR logtrace_block; /* next block traced */
_EL_BLOCK_PTR cur_block; /* Pointer to current event_log block */
_EL_TYPE_PTR cur_ptr; /* Current event_log pointer */
uint32 blockcount; /* Number of blocks */
uint16 logtrace_count; /* Last count for logtrace */
uint16 blockfill_count; /* Fill count for logtrace */
uint32 timestamp; /* Last timestamp event */
uint32 cyclecount; /* Cycles at last timestamp event */
} event_log_set_t;
/* Top data structure for access to everything else */
typedef struct event_log_top {
uint32 magic;
#define EVENT_LOG_TOP_MAGIC 0x474C8669 /* 'EVLG' */
uint32 version;
#define EVENT_LOG_VERSION 1
uint32 num_sets;
uint32 logstrs_size; /* Size of lognums + logstrs area */
uint32 timestamp; /* Last timestamp event */
uint32 cyclecount; /* Cycles at last timestamp event */
_EL_SET_PTR sets; /* Ptr to array of <num_sets> set ptrs */
} event_log_top_t;
#ifndef EVENT_LOG_DUMPER
#ifndef EVENT_LOG_COMPILE
/* Null define if no tracing */
#define EVENT_LOG(format, ...)
#else /* EVENT_LOG_COMPILE */
/* The first few are special because they can be done more efficiently
* this way and they are the common case. Once there are too many
* parameters the code size starts to be an issue and a loop is better
*/
#define _EVENT_LOG0(tag, fmt_num) \
event_log0(tag, fmt_num)
#define _EVENT_LOG1(tag, fmt_num, t1) \
event_log1(tag, fmt_num, t1)
#define _EVENT_LOG2(tag, fmt_num, t1, t2) \
event_log2(tag, fmt_num, t1, t2)
#define _EVENT_LOG3(tag, fmt_num, t1, t2, t3) \
event_log3(tag, fmt_num, t1, t2, t3)
#define _EVENT_LOG4(tag, fmt_num, t1, t2, t3, t4) \
event_log4(tag, fmt_num, t1, t2, t3, t4)
/* The rest call the generic routine that takes a count */
#define _EVENT_LOG5(tag, fmt_num, ...) event_logn(5, tag, fmt_num, __VA_ARGS__)
#define _EVENT_LOG6(tag, fmt_num, ...) event_logn(6, tag, fmt_num, __VA_ARGS__)
#define _EVENT_LOG7(tag, fmt_num, ...) event_logn(7, tag, fmt_num, __VA_ARGS__)
#define _EVENT_LOG8(tag, fmt_num, ...) event_logn(8, tag, fmt_num, __VA_ARGS__)
#define _EVENT_LOG9(tag, fmt_num, ...) event_logn(9, tag, fmt_num, __VA_ARGS__)
#define _EVENT_LOGa(tag, fmt_num, ...) event_logn(10, tag, fmt_num, __VA_ARGS__)
#define _EVENT_LOGb(tag, fmt_num, ...) event_logn(11, tag, fmt_num, __VA_ARGS__)
#define _EVENT_LOGc(tag, fmt_num, ...) event_logn(12, tag, fmt_num, __VA_ARGS__)
#define _EVENT_LOGd(tag, fmt_num, ...) event_logn(13, tag, fmt_num, __VA_ARGS__)
#define _EVENT_LOGe(tag, fmt_num, ...) event_logn(14, tag, fmt_num, __VA_ARGS__)
#define _EVENT_LOGf(tag, fmt_num, ...) event_logn(15, tag, fmt_num, __VA_ARGS__)
/* Hack to make the proper routine call when variadic macros get
* passed. Note the max of 15 arguments. More than that can't be
* handled by the event_log entries anyways so best to catch it at compile
* time
*/
#define _EVENT_LOG_VA_NUM_ARGS(F, _1, _2, _3, _4, _5, _6, _7, _8, _9, \
_A, _B, _C, _D, _E, _F, N, ...) F ## N
#define _EVENT_LOG(tag, fmt, ...) \
static char logstr[] __attribute__ ((section(".logstrs"))) = fmt; \
static uint32 fmtnum __attribute__ ((section(".lognums"))) = (uint32) &logstr; \
_EVENT_LOG_VA_NUM_ARGS(_EVENT_LOG, ##__VA_ARGS__, \
F, E, D, C, B, A, 9, 8, \
7, 6, 5, 4, 3, 2, 1, 0) \
(tag, (int) &fmtnum , ## __VA_ARGS__); \
#define EVENT_LOG_FAST(tag, fmt, ...) \
if (event_log_tag_sets != NULL) { \
uint8 tag_flag = *(event_log_tag_sets + tag); \
if (tag_flag != 0) { \
_EVENT_LOG(tag, fmt , ## __VA_ARGS__); \
} \
}
#define EVENT_LOG_COMPACT(tag, fmt, ...) \
if (1) { \
_EVENT_LOG(tag, fmt , ## __VA_ARGS__); \
}
#define EVENT_LOG(tag, fmt, ...) EVENT_LOG_COMPACT(tag, fmt , ## __VA_ARGS__)
extern uint8 *event_log_tag_sets;
extern int event_log_init(si_t *sih);
extern int event_log_set_init(si_t *sih, int set_num, int size);
extern int event_log_set_expand(si_t *sih, int set_num, int size);
extern int event_log_set_shrink(si_t *sih, int set_num, int size);
extern int event_log_tag_start(int tag, int set_num, int flags);
extern int event_log_tag_stop(int tag);
extern int event_log_get(int set_num, int buflen, void *buf);
extern uint8 * event_log_next_logtrace(int set_num);
extern void event_log0(int tag, int fmtNum);
extern void event_log1(int tag, int fmtNum, uint32 t1);
extern void event_log2(int tag, int fmtNum, uint32 t1, uint32 t2);
extern void event_log3(int tag, int fmtNum, uint32 t1, uint32 t2, uint32 t3);
extern void event_log4(int tag, int fmtNum, uint32 t1, uint32 t2, uint32 t3, uint32 t4);
extern void event_logn(int num_args, int tag, int fmtNum, ...);
extern void event_log_time_sync(void);
#endif /* EVENT_LOG_DUMPER */
#endif /* EVENT_LOG_COMPILE */
#endif /* __ASSEMBLER__ */
#endif /* _EVENT_LOG_H */

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/*
* Generic Broadcom Home Networking Division (HND) DMA engine SW interface
* This supports the following chips: BCM42xx, 44xx, 47xx .
*
* $Copyright Open Broadcom Corporation$
*
* $Id: hnddma.h 365056 2012-10-26 12:00:34Z maheshd $
*/
#ifndef _hnddma_h_
#define _hnddma_h_
#ifndef _hnddma_pub_
#define _hnddma_pub_
typedef const struct hnddma_pub hnddma_t;
#endif /* _hnddma_pub_ */
/* range param for dma_getnexttxp() and dma_txreclaim */
typedef enum txd_range {
HNDDMA_RANGE_ALL = 1,
HNDDMA_RANGE_TRANSMITTED,
HNDDMA_RANGE_TRANSFERED
} txd_range_t;
/* dma function type */
typedef void (*di_detach_t)(hnddma_t *dmah);
typedef bool (*di_txreset_t)(hnddma_t *dmah);
typedef bool (*di_rxreset_t)(hnddma_t *dmah);
typedef bool (*di_rxidle_t)(hnddma_t *dmah);
typedef void (*di_txinit_t)(hnddma_t *dmah);
typedef bool (*di_txenabled_t)(hnddma_t *dmah);
typedef void (*di_rxinit_t)(hnddma_t *dmah);
typedef void (*di_txsuspend_t)(hnddma_t *dmah);
typedef void (*di_txresume_t)(hnddma_t *dmah);
typedef bool (*di_txsuspended_t)(hnddma_t *dmah);
typedef bool (*di_txsuspendedidle_t)(hnddma_t *dmah);
#ifdef WL_MULTIQUEUE
typedef void (*di_txflush_t)(hnddma_t *dmah);
typedef void (*di_txflush_clear_t)(hnddma_t *dmah);
#endif /* WL_MULTIQUEUE */
typedef int (*di_txfast_t)(hnddma_t *dmah, void *p, bool commit);
typedef int (*di_txunframed_t)(hnddma_t *dmah, void *p, uint len, bool commit);
typedef void* (*di_getpos_t)(hnddma_t *di, bool direction);
typedef void (*di_fifoloopbackenable_t)(hnddma_t *dmah);
typedef bool (*di_txstopped_t)(hnddma_t *dmah);
typedef bool (*di_rxstopped_t)(hnddma_t *dmah);
typedef bool (*di_rxenable_t)(hnddma_t *dmah);
typedef bool (*di_rxenabled_t)(hnddma_t *dmah);
typedef void* (*di_rx_t)(hnddma_t *dmah);
typedef bool (*di_rxfill_t)(hnddma_t *dmah);
typedef void (*di_txreclaim_t)(hnddma_t *dmah, txd_range_t range);
typedef void (*di_rxreclaim_t)(hnddma_t *dmah);
typedef uintptr (*di_getvar_t)(hnddma_t *dmah, const char *name);
typedef void* (*di_getnexttxp_t)(hnddma_t *dmah, txd_range_t range);
typedef void* (*di_getnextrxp_t)(hnddma_t *dmah, bool forceall);
typedef void* (*di_peeknexttxp_t)(hnddma_t *dmah);
typedef void* (*di_peekntxp_t)(hnddma_t *dmah, int *len, void *txps[], txd_range_t range);
typedef void* (*di_peeknextrxp_t)(hnddma_t *dmah);
typedef void (*di_rxparam_get_t)(hnddma_t *dmah, uint16 *rxoffset, uint16 *rxbufsize);
typedef void (*di_txblock_t)(hnddma_t *dmah);
typedef void (*di_txunblock_t)(hnddma_t *dmah);
typedef uint (*di_txactive_t)(hnddma_t *dmah);
typedef void (*di_txrotate_t)(hnddma_t *dmah);
typedef void (*di_counterreset_t)(hnddma_t *dmah);
typedef uint (*di_ctrlflags_t)(hnddma_t *dmah, uint mask, uint flags);
typedef char* (*di_dump_t)(hnddma_t *dmah, struct bcmstrbuf *b, bool dumpring);
typedef char* (*di_dumptx_t)(hnddma_t *dmah, struct bcmstrbuf *b, bool dumpring);
typedef char* (*di_dumprx_t)(hnddma_t *dmah, struct bcmstrbuf *b, bool dumpring);
typedef uint (*di_rxactive_t)(hnddma_t *dmah);
typedef uint (*di_txpending_t)(hnddma_t *dmah);
typedef uint (*di_txcommitted_t)(hnddma_t *dmah);
typedef int (*di_pktpool_set_t)(hnddma_t *dmah, pktpool_t *pool);
typedef bool (*di_rxtxerror_t)(hnddma_t *dmah, bool istx);
typedef void (*di_burstlen_set_t)(hnddma_t *dmah, uint8 rxburstlen, uint8 txburstlen);
typedef uint (*di_avoidancecnt_t)(hnddma_t *dmah);
typedef uint (*dma_active_rxbuf_t) (hnddma_t *dmah);
/* dma opsvec */
typedef struct di_fcn_s {
di_detach_t detach;
di_txinit_t txinit;
di_txreset_t txreset;
di_txenabled_t txenabled;
di_txsuspend_t txsuspend;
di_txresume_t txresume;
di_txsuspended_t txsuspended;
di_txsuspendedidle_t txsuspendedidle;
#ifdef WL_MULTIQUEUE
di_txflush_t txflush;
di_txflush_clear_t txflush_clear;
#endif /* WL_MULTIQUEUE */
di_txfast_t txfast;
di_txunframed_t txunframed;
di_getpos_t getpos;
di_txstopped_t txstopped;
di_txreclaim_t txreclaim;
di_getnexttxp_t getnexttxp;
di_peeknexttxp_t peeknexttxp;
di_peekntxp_t peekntxp;
di_txblock_t txblock;
di_txunblock_t txunblock;
di_txactive_t txactive;
di_txrotate_t txrotate;
di_rxinit_t rxinit;
di_rxreset_t rxreset;
di_rxidle_t rxidle;
di_rxstopped_t rxstopped;
di_rxenable_t rxenable;
di_rxenabled_t rxenabled;
di_rx_t rx;
di_rxfill_t rxfill;
di_rxreclaim_t rxreclaim;
di_getnextrxp_t getnextrxp;
di_peeknextrxp_t peeknextrxp;
di_rxparam_get_t rxparam_get;
di_fifoloopbackenable_t fifoloopbackenable;
di_getvar_t d_getvar;
di_counterreset_t counterreset;
di_ctrlflags_t ctrlflags;
di_dump_t dump;
di_dumptx_t dumptx;
di_dumprx_t dumprx;
di_rxactive_t rxactive;
di_txpending_t txpending;
di_txcommitted_t txcommitted;
di_pktpool_set_t pktpool_set;
di_rxtxerror_t rxtxerror;
di_burstlen_set_t burstlen_set;
di_avoidancecnt_t avoidancecnt;
#ifdef WL_RXBUFF_EARLY_RC
dma_active_rxbuf_t dma_activerxbuf;
#endif
uint endnum;
} di_fcn_t;
/*
* Exported data structure (read-only)
*/
/* export structure */
struct hnddma_pub {
const di_fcn_t *di_fn; /* DMA function pointers */
uint txavail; /* # free tx descriptors */
uint dmactrlflags; /* dma control flags */
/* rx error counters */
uint rxgiants; /* rx giant frames */
uint rxnobuf; /* rx out of dma descriptors */
/* tx error counters */
uint txnobuf; /* tx out of dma descriptors */
uint txnodesc; /* tx out of dma descriptors running count */
};
extern hnddma_t * dma_attach(osl_t *osh, const char *name, si_t *sih,
volatile void *dmaregstx, volatile void *dmaregsrx,
uint ntxd, uint nrxd, uint rxbufsize, int rxextheadroom, uint nrxpost,
uint rxoffset, uint *msg_level);
#ifdef BCMDMA32
#define dma_detach(di) ((di)->di_fn->detach(di))
#define dma_txreset(di) ((di)->di_fn->txreset(di))
#define dma_rxreset(di) ((di)->di_fn->rxreset(di))
#define dma_rxidle(di) ((di)->di_fn->rxidle(di))
#define dma_txinit(di) ((di)->di_fn->txinit(di))
#define dma_txenabled(di) ((di)->di_fn->txenabled(di))
#define dma_rxinit(di) ((di)->di_fn->rxinit(di))
#define dma_txsuspend(di) ((di)->di_fn->txsuspend(di))
#define dma_txresume(di) ((di)->di_fn->txresume(di))
#define dma_txsuspended(di) ((di)->di_fn->txsuspended(di))
#define dma_txsuspendedidle(di) ((di)->di_fn->txsuspendedidle(di))
#ifdef WL_MULTIQUEUE
#define dma_txflush(di) ((di)->di_fn->txflush(di))
#define dma_txflush_clear(di) ((di)->di_fn->txflush_clear(di))
#endif /* WL_MULTIQUEUE */
#define dma_txfast(di, p, commit) ((di)->di_fn->txfast(di, p, commit))
#define dma_fifoloopbackenable(di) ((di)->di_fn->fifoloopbackenable(di))
#define dma_txstopped(di) ((di)->di_fn->txstopped(di))
#define dma_rxstopped(di) ((di)->di_fn->rxstopped(di))
#define dma_rxenable(di) ((di)->di_fn->rxenable(di))
#define dma_rxenabled(di) ((di)->di_fn->rxenabled(di))
#define dma_rx(di) ((di)->di_fn->rx(di))
#define dma_rxfill(di) ((di)->di_fn->rxfill(di))
#define dma_txreclaim(di, range) ((di)->di_fn->txreclaim(di, range))
#define dma_rxreclaim(di) ((di)->di_fn->rxreclaim(di))
#define dma_getvar(di, name) ((di)->di_fn->d_getvar(di, name))
#define dma_getnexttxp(di, range) ((di)->di_fn->getnexttxp(di, range))
#define dma_getnextrxp(di, forceall) ((di)->di_fn->getnextrxp(di, forceall))
#define dma_peeknexttxp(di) ((di)->di_fn->peeknexttxp(di))
#define dma_peekntxp(di, l, t, r) ((di)->di_fn->peekntxp(di, l, t, r))
#define dma_peeknextrxp(di) ((di)->di_fn->peeknextrxp(di))
#define dma_rxparam_get(di, off, bufs) ((di)->di_fn->rxparam_get(di, off, bufs))
#define dma_txblock(di) ((di)->di_fn->txblock(di))
#define dma_txunblock(di) ((di)->di_fn->txunblock(di))
#define dma_txactive(di) ((di)->di_fn->txactive(di))
#define dma_rxactive(di) ((di)->di_fn->rxactive(di))
#define dma_txrotate(di) ((di)->di_fn->txrotate(di))
#define dma_counterreset(di) ((di)->di_fn->counterreset(di))
#define dma_ctrlflags(di, mask, flags) ((di)->di_fn->ctrlflags((di), (mask), (flags)))
#define dma_txpending(di) ((di)->di_fn->txpending(di))
#define dma_txcommitted(di) ((di)->di_fn->txcommitted(di))
#define dma_pktpool_set(di, pool) ((di)->di_fn->pktpool_set((di), (pool)))
#if defined(BCMDBG) || defined(BCMDBG_DUMP)
#define dma_dump(di, buf, dumpring) ((di)->di_fn->dump(di, buf, dumpring))
#define dma_dumptx(di, buf, dumpring) ((di)->di_fn->dumptx(di, buf, dumpring))
#define dma_dumprx(di, buf, dumpring) ((di)->di_fn->dumprx(di, buf, dumpring))
#endif /* defined(BCMDBG) || defined(BCMDBG_DUMP) */
#define dma_rxtxerror(di, istx) ((di)->di_fn->rxtxerror(di, istx))
#define dma_burstlen_set(di, rxlen, txlen) ((di)->di_fn->burstlen_set(di, rxlen, txlen))
#define dma_avoidance_cnt(di) ((di)->di_fn->avoidancecnt(di))
#else /* BCMDMA32 */
extern const di_fcn_t dma64proc;
#define dma_detach(di) (dma64proc.detach(di))
#define dma_txreset(di) (dma64proc.txreset(di))
#define dma_rxreset(di) (dma64proc.rxreset(di))
#define dma_rxidle(di) (dma64proc.rxidle(di))
#define dma_txinit(di) (dma64proc.txinit(di))
#define dma_txenabled(di) (dma64proc.txenabled(di))
#define dma_rxinit(di) (dma64proc.rxinit(di))
#define dma_txsuspend(di) (dma64proc.txsuspend(di))
#define dma_txresume(di) (dma64proc.txresume(di))
#define dma_txsuspended(di) (dma64proc.txsuspended(di))
#define dma_txsuspendedidle(di) (dma64proc.txsuspendedidle(di))
#ifdef WL_MULTIQUEUE
#define dma_txflush(di) (dma64proc.txflush(di))
#define dma_txflush_clear(di) (dma64proc.txflush_clear(di))
#endif /* WL_MULTIQUEUE */
#define dma_txfast(di, p, commit) (dma64proc.txfast(di, p, commit))
#define dma_txunframed(di, p, l, commit)(dma64proc.txunframed(di, p, l, commit))
#define dma_getpos(di, dir) (dma64proc.getpos(di, dir))
#define dma_fifoloopbackenable(di) (dma64proc.fifoloopbackenable(di))
#define dma_txstopped(di) (dma64proc.txstopped(di))
#define dma_rxstopped(di) (dma64proc.rxstopped(di))
#define dma_rxenable(di) (dma64proc.rxenable(di))
#define dma_rxenabled(di) (dma64proc.rxenabled(di))
#define dma_rx(di) (dma64proc.rx(di))
#define dma_rxfill(di) (dma64proc.rxfill(di))
#define dma_txreclaim(di, range) (dma64proc.txreclaim(di, range))
#define dma_rxreclaim(di) (dma64proc.rxreclaim(di))
#define dma_getvar(di, name) (dma64proc.d_getvar(di, name))
#define dma_getnexttxp(di, range) (dma64proc.getnexttxp(di, range))
#define dma_getnextrxp(di, forceall) (dma64proc.getnextrxp(di, forceall))
#define dma_peeknexttxp(di) (dma64proc.peeknexttxp(di))
#define dma_peekntxp(di, l, t, r) (dma64proc.peekntxp(di, l, t, r))
#define dma_peeknextrxp(di) (dma64proc.peeknextrxp(di))
#define dma_rxparam_get(di, off, bufs) (dma64proc.rxparam_get(di, off, bufs))
#define dma_txblock(di) (dma64proc.txblock(di))
#define dma_txunblock(di) (dma64proc.txunblock(di))
#define dma_txactive(di) (dma64proc.txactive(di))
#define dma_rxactive(di) (dma64proc.rxactive(di))
#define dma_txrotate(di) (dma64proc.txrotate(di))
#define dma_counterreset(di) (dma64proc.counterreset(di))
#define dma_ctrlflags(di, mask, flags) (dma64proc.ctrlflags((di), (mask), (flags)))
#define dma_txpending(di) (dma64proc.txpending(di))
#define dma_txcommitted(di) (dma64proc.txcommitted(di))
#define dma_pktpool_set(di, pool) (dma64proc.pktpool_set((di), (pool)))
#if defined(BCMDBG) || defined(BCMDBG_DUMP)
#define dma_dump(di, buf, dumpring) (dma64proc.dump(di, buf, dumpring))
#define dma_dumptx(di, buf, dumpring) (dma64proc.dumptx(di, buf, dumpring))
#define dma_dumprx(di, buf, dumpring) (dma64proc.dumprx(di, buf, dumpring))
#endif
#define dma_rxtxerror(di, istx) (dma64proc.rxtxerror(di, istx))
#define dma_burstlen_set(di, rxlen, txlen) (dma64proc.burstlen_set(di, rxlen, txlen))
#define dma_avoidance_cnt(di) (dma64proc.avoidancecnt(di))
#define dma_activerxbuf(di) (dma64proc.dma_activerxbuf(di))
#endif /* BCMDMA32 */
/* return addresswidth allowed
* This needs to be done after SB attach but before dma attach.
* SB attach provides ability to probe backplane and dma core capabilities
* This info is needed by DMA_ALLOC_CONSISTENT in dma attach
*/
extern uint dma_addrwidth(si_t *sih, void *dmaregs);
/* pio helpers */
extern void dma_txpioloopback(osl_t *osh, dma32regs_t *);
#endif /* _hnddma_h_ */

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/*
* HND SiliconBackplane PMU support.
*
* $Copyright Open Broadcom Corporation$
*
* $Id: hndpmu.h 393084 2013-03-26 07:34:45Z $
*/
#ifndef _hndpmu_h_
#define _hndpmu_h_
extern void si_pmu_otp_power(si_t *sih, osl_t *osh, bool on);
extern void si_sdiod_drive_strength_init(si_t *sih, osl_t *osh, uint32 drivestrength);
extern void si_pmu_minresmask_htavail_set(si_t *sih, osl_t *osh, bool set_clear);
#endif /* _hndpmu_h_ */

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/*
* HNDRTE arm trap handling.
*
* $Copyright Open Broadcom Corporation$
*
* $Id: hndrte_armtrap.h 261365 2011-05-24 20:42:23Z $
*/
#ifndef _hndrte_armtrap_h
#define _hndrte_armtrap_h
/* ARM trap handling */
/* Trap types defined by ARM (see arminc.h) */
/* Trap locations in lo memory */
#define TRAP_STRIDE 4
#define FIRST_TRAP TR_RST
#define LAST_TRAP (TR_FIQ * TRAP_STRIDE)
#if defined(__ARM_ARCH_4T__)
#define MAX_TRAP_TYPE (TR_FIQ + 1)
#elif defined(__ARM_ARCH_7M__)
#define MAX_TRAP_TYPE (TR_ISR + ARMCM3_NUMINTS)
#endif /* __ARM_ARCH_7M__ */
/* The trap structure is defined here as offsets for assembly */
#define TR_TYPE 0x00
#define TR_EPC 0x04
#define TR_CPSR 0x08
#define TR_SPSR 0x0c
#define TR_REGS 0x10
#define TR_REG(n) (TR_REGS + (n) * 4)
#define TR_SP TR_REG(13)
#define TR_LR TR_REG(14)
#define TR_PC TR_REG(15)
#define TRAP_T_SIZE 80
#ifndef _LANGUAGE_ASSEMBLY
#include <typedefs.h>
typedef struct _trap_struct {
uint32 type;
uint32 epc;
uint32 cpsr;
uint32 spsr;
uint32 r0; /* a1 */
uint32 r1; /* a2 */
uint32 r2; /* a3 */
uint32 r3; /* a4 */
uint32 r4; /* v1 */
uint32 r5; /* v2 */
uint32 r6; /* v3 */
uint32 r7; /* v4 */
uint32 r8; /* v5 */
uint32 r9; /* sb/v6 */
uint32 r10; /* sl/v7 */
uint32 r11; /* fp/v8 */
uint32 r12; /* ip */
uint32 r13; /* sp */
uint32 r14; /* lr */
uint32 pc; /* r15 */
} trap_t;
#endif /* !_LANGUAGE_ASSEMBLY */
#endif /* _hndrte_armtrap_h */

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/*
* Console support for hndrte.
*
* $Copyright Open Broadcom Corporation$
*
* $Id: hndrte_cons.h 383575 2013-02-07 03:10:23Z $
*/
#ifndef _HNDRTE_CONS_H
#define _HNDRTE_CONS_H
#include <typedefs.h>
#if defined(RWL_DONGLE) || defined(UART_REFLECTOR)
/* For Dongle uart tranport max cmd len is 256 bytes + header length (16 bytes)
* In case of ASD commands we are not sure about how much is the command size
* To be on the safe side, input buf len CBUF_LEN is increased to max (512) bytes.
*/
#define RWL_MAX_DATA_LEN (512 + 8) /* allow some extra bytes for '/n' termination */
#define CBUF_LEN (RWL_MAX_DATA_LEN + 64) /* allow 64 bytes for header ("rwl...") */
#else
#define CBUF_LEN (128)
#endif /* RWL_DONGLE || UART_REFLECTOR */
#define LOG_BUF_LEN 1024
typedef struct {
uint32 buf; /* Can't be pointer on (64-bit) hosts */
uint buf_size;
uint idx;
char *_buf_compat; /* redundant pointer for backward compat. */
} hndrte_log_t;
typedef struct {
/* Virtual UART
* When there is no UART (e.g. Quickturn), the host should write a complete
* input line directly into cbuf and then write the length into vcons_in.
* This may also be used when there is a real UART (at risk of conflicting with
* the real UART). vcons_out is currently unused.
*/
volatile uint vcons_in;
volatile uint vcons_out;
/* Output (logging) buffer
* Console output is written to a ring buffer log_buf at index log_idx.
* The host may read the output when it sees log_idx advance.
* Output will be lost if the output wraps around faster than the host polls.
*/
hndrte_log_t log;
/* Console input line buffer
* Characters are read one at a time into cbuf until <CR> is received, then
* the buffer is processed as a command line. Also used for virtual UART.
*/
uint cbuf_idx;
char cbuf[CBUF_LEN];
} hndrte_cons_t;
hndrte_cons_t *hndrte_get_active_cons_state(void);
#endif /* _HNDRTE_CONS_H */

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/*
* HND Run Time Environment debug info area
*
* $Copyright Open Broadcom Corporation$
*
* $Id: hndrte_debug.h 342211 2012-07-02 02:23:04Z $
*/
#ifndef _HNDRTE_DEBUG_H
#define _HNDRTE_DEBUG_H
/* Magic number at a magic location to find HNDRTE_DEBUG pointers */
#define HNDRTE_DEBUG_PTR_PTR_MAGIC 0x50504244 /* DBPP */
#ifndef _LANGUAGE_ASSEMBLY
/* Includes only when building dongle code */
#define NUM_EVENT_LOG_SETS 4
/* We use explicit sizes here since this gets included from different
* systems. The sizes must be the size of the creating system
* (currently 32 bit ARM) since this is gleaned from dump.
*/
/* Define pointers for use on other systems */
#define _HD_EVLOG_P uint32
#define _HD_CONS_P uint32
#define _HD_TRAP_P uint32
typedef struct hndrte_debug {
uint32 magic;
#define HNDRTE_DEBUG_MAGIC 0x47424544 /* 'DEBG' */
uint32 version; /* Debug struct version */
#define HNDRTE_DEBUG_VERSION 1
uint32 fwid; /* 4 bytes of fw info */
char epivers[32];
_HD_TRAP_P trap_ptr; /* trap_t data struct */
_HD_CONS_P console; /* Console */
uint32 ram_base;
uint32 ram_size;
uint32 rom_base;
uint32 rom_size;
_HD_EVLOG_P event_log_top;
} hndrte_debug_t;
/*
* timeval_t and prstatus_t are copies of the Linux structures.
* Included here because we need the definitions for the target processor
* (32 bits) and not the definition on the host this is running on
* (which could be 64 bits).
*/
typedef struct { /* Time value with microsecond resolution */
uint32 tv_sec; /* Seconds */
uint32 tv_usec; /* Microseconds */
} timeval_t;
/* Linux/ARM 32 prstatus for notes section */
typedef struct prstatus {
int32 si_signo; /* Signal number */
int32 si_code; /* Extra code */
int32 si_errno; /* Errno */
uint16 pr_cursig; /* Current signal. */
uint16 unused;
uint32 pr_sigpend; /* Set of pending signals. */
uint32 pr_sighold; /* Set of held signals. */
uint32 pr_pid;
uint32 pr_ppid;
uint32 pr_pgrp;
uint32 pr_sid;
timeval_t pr_utime; /* User time. */
timeval_t pr_stime; /* System time. */
timeval_t pr_cutime; /* Cumulative user time. */
timeval_t pr_cstime; /* Cumulative system time. */
uint32 uregs[18];
int32 pr_fpvalid; /* True if math copro being used. */
} prstatus_t;
#ifdef __GNUC__
extern hndrte_debug_t hndrte_debug_info __attribute__ ((weak));
#endif /* __GNUC__ */
#endif /* !LANGUAGE_ASSEMBLY */
#endif /* _HNDRTE_DEBUG_H */

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/*
* Broadcom HND chip & on-chip-interconnect-related definitions.
*
* $Copyright Open Broadcom Corporation$
*
* $Id: hndsoc.h 365038 2012-10-26 08:49:46Z $
*/
#ifndef _HNDSOC_H
#define _HNDSOC_H
/* Include the soci specific files */
#include <sbconfig.h>
#include <aidmp.h>
/*
* SOC Interconnect Address Map.
* All regions may not exist on all chips.
*/
#define SI_SDRAM_BASE 0x00000000 /* Physical SDRAM */
#define SI_PCI_MEM 0x08000000 /* Host Mode sb2pcitranslation0 (64 MB) */
#define SI_PCI_MEM_SZ (64 * 1024 * 1024)
#define SI_PCI_CFG 0x0c000000 /* Host Mode sb2pcitranslation1 (64 MB) */
#define SI_SDRAM_SWAPPED 0x10000000 /* Byteswapped Physical SDRAM */
#define SI_SDRAM_R2 0x80000000 /* Region 2 for sdram (512 MB) */
#define SI_ENUM_BASE 0x18000000 /* Enumeration space base */
#define SI_WRAP_BASE 0x18100000 /* Wrapper space base */
#define SI_CORE_SIZE 0x1000 /* each core gets 4Kbytes for registers */
#define SI_MAXCORES 32 /* NorthStar has more cores */
#define SI_FASTRAM 0x19000000 /* On-chip RAM on chips that also have DDR */
#define SI_FASTRAM_SWAPPED 0x19800000
#define SI_FLASH2 0x1c000000 /* Flash Region 2 (region 1 shadowed here) */
#define SI_FLASH2_SZ 0x02000000 /* Size of Flash Region 2 */
#define SI_ARMCM3_ROM 0x1e000000 /* ARM Cortex-M3 ROM */
#define SI_FLASH1 0x1fc00000 /* MIPS Flash Region 1 */
#define SI_FLASH1_SZ 0x00400000 /* MIPS Size of Flash Region 1 */
#define SI_FLASH_WINDOW 0x01000000 /* Flash XIP Window */
#define SI_NS_NANDFLASH 0x1c000000 /* NorthStar NAND flash base */
#define SI_NS_NORFLASH 0x1e000000 /* NorthStar NOR flash base */
#define SI_NS_ROM 0xfffd0000 /* NorthStar ROM */
#define SI_NS_FLASH_WINDOW 0x02000000 /* NorthStar Flash XIP Window */
#define SI_ARM7S_ROM 0x20000000 /* ARM7TDMI-S ROM */
#define SI_ARMCR4_ROM 0x000f0000 /* ARM Cortex-R4 ROM */
#define SI_ARMCM3_SRAM2 0x60000000 /* ARM Cortex-M3 SRAM Region 2 */
#define SI_ARM7S_SRAM2 0x80000000 /* ARM7TDMI-S SRAM Region 2 */
#define SI_ARM_FLASH1 0xffff0000 /* ARM Flash Region 1 */
#define SI_ARM_FLASH1_SZ 0x00010000 /* ARM Size of Flash Region 1 */
#define SI_PCI_DMA 0x40000000 /* Client Mode sb2pcitranslation2 (1 GB) */
#define SI_PCI_DMA2 0x80000000 /* Client Mode sb2pcitranslation2 (1 GB) */
#define SI_PCI_DMA_SZ 0x40000000 /* Client Mode sb2pcitranslation2 size in bytes */
#define SI_PCIE_DMA_L32 0x00000000 /* PCIE Client Mode sb2pcitranslation2
* (2 ZettaBytes), low 32 bits
*/
#define SI_PCIE_DMA_H32 0x80000000 /* PCIE Client Mode sb2pcitranslation2
* (2 ZettaBytes), high 32 bits
*/
/* core codes */
#define NODEV_CORE_ID 0x700 /* Invalid coreid */
#define CC_CORE_ID 0x800 /* chipcommon core */
#define ILINE20_CORE_ID 0x801 /* iline20 core */
#define SRAM_CORE_ID 0x802 /* sram core */
#define SDRAM_CORE_ID 0x803 /* sdram core */
#define PCI_CORE_ID 0x804 /* pci core */
#define MIPS_CORE_ID 0x805 /* mips core */
#define ENET_CORE_ID 0x806 /* enet mac core */
#define CODEC_CORE_ID 0x807 /* v90 codec core */
#define USB_CORE_ID 0x808 /* usb 1.1 host/device core */
#define ADSL_CORE_ID 0x809 /* ADSL core */
#define ILINE100_CORE_ID 0x80a /* iline100 core */
#define IPSEC_CORE_ID 0x80b /* ipsec core */
#define UTOPIA_CORE_ID 0x80c /* utopia core */
#define PCMCIA_CORE_ID 0x80d /* pcmcia core */
#define SOCRAM_CORE_ID 0x80e /* internal memory core */
#define MEMC_CORE_ID 0x80f /* memc sdram core */
#define OFDM_CORE_ID 0x810 /* OFDM phy core */
#define EXTIF_CORE_ID 0x811 /* external interface core */
#define D11_CORE_ID 0x812 /* 802.11 MAC core */
#define APHY_CORE_ID 0x813 /* 802.11a phy core */
#define BPHY_CORE_ID 0x814 /* 802.11b phy core */
#define GPHY_CORE_ID 0x815 /* 802.11g phy core */
#define MIPS33_CORE_ID 0x816 /* mips3302 core */
#define USB11H_CORE_ID 0x817 /* usb 1.1 host core */
#define USB11D_CORE_ID 0x818 /* usb 1.1 device core */
#define USB20H_CORE_ID 0x819 /* usb 2.0 host core */
#define USB20D_CORE_ID 0x81a /* usb 2.0 device core */
#define SDIOH_CORE_ID 0x81b /* sdio host core */
#define ROBO_CORE_ID 0x81c /* roboswitch core */
#define ATA100_CORE_ID 0x81d /* parallel ATA core */
#define SATAXOR_CORE_ID 0x81e /* serial ATA & XOR DMA core */
#define GIGETH_CORE_ID 0x81f /* gigabit ethernet core */
#define PCIE_CORE_ID 0x820 /* pci express core */
#define NPHY_CORE_ID 0x821 /* 802.11n 2x2 phy core */
#define SRAMC_CORE_ID 0x822 /* SRAM controller core */
#define MINIMAC_CORE_ID 0x823 /* MINI MAC/phy core */
#define ARM11_CORE_ID 0x824 /* ARM 1176 core */
#define ARM7S_CORE_ID 0x825 /* ARM7tdmi-s core */
#define LPPHY_CORE_ID 0x826 /* 802.11a/b/g phy core */
#define PMU_CORE_ID 0x827 /* PMU core */
#define SSNPHY_CORE_ID 0x828 /* 802.11n single-stream phy core */
#define SDIOD_CORE_ID 0x829 /* SDIO device core */
#define ARMCM3_CORE_ID 0x82a /* ARM Cortex M3 core */
#define HTPHY_CORE_ID 0x82b /* 802.11n 4x4 phy core */
#define MIPS74K_CORE_ID 0x82c /* mips 74k core */
#define GMAC_CORE_ID 0x82d /* Gigabit MAC core */
#define DMEMC_CORE_ID 0x82e /* DDR1/2 memory controller core */
#define PCIERC_CORE_ID 0x82f /* PCIE Root Complex core */
#define OCP_CORE_ID 0x830 /* OCP2OCP bridge core */
#define SC_CORE_ID 0x831 /* shared common core */
#define AHB_CORE_ID 0x832 /* OCP2AHB bridge core */
#define SPIH_CORE_ID 0x833 /* SPI host core */
#define I2S_CORE_ID 0x834 /* I2S core */
#define DMEMS_CORE_ID 0x835 /* SDR/DDR1 memory controller core */
#define DEF_SHIM_COMP 0x837 /* SHIM component in ubus/6362 */
#define ACPHY_CORE_ID 0x83b /* Dot11 ACPHY */
#define PCIE2_CORE_ID 0x83c /* pci express Gen2 core */
#define USB30D_CORE_ID 0x83d /* usb 3.0 device core */
#define ARMCR4_CORE_ID 0x83e /* ARM CR4 CPU */
#define APB_BRIDGE_CORE_ID 0x135 /* APB bridge core ID */
#define AXI_CORE_ID 0x301 /* AXI/GPV core ID */
#define EROM_CORE_ID 0x366 /* EROM core ID */
#define OOB_ROUTER_CORE_ID 0x367 /* OOB router core ID */
#define DEF_AI_COMP 0xfff /* Default component, in ai chips it maps all
* unused address ranges
*/
#define CC_4706_CORE_ID 0x500 /* chipcommon core */
#define NS_PCIEG2_CORE_ID 0x501 /* PCIE Gen 2 core */
#define NS_DMA_CORE_ID 0x502 /* DMA core */
#define NS_SDIO3_CORE_ID 0x503 /* SDIO3 core */
#define NS_USB20_CORE_ID 0x504 /* USB2.0 core */
#define NS_USB30_CORE_ID 0x505 /* USB3.0 core */
#define NS_A9JTAG_CORE_ID 0x506 /* ARM Cortex A9 JTAG core */
#define NS_DDR23_CORE_ID 0x507 /* Denali DDR2/DDR3 memory controller */
#define NS_ROM_CORE_ID 0x508 /* ROM core */
#define NS_NAND_CORE_ID 0x509 /* NAND flash controller core */
#define NS_QSPI_CORE_ID 0x50a /* SPI flash controller core */
#define NS_CCB_CORE_ID 0x50b /* ChipcommonB core */
#define SOCRAM_4706_CORE_ID 0x50e /* internal memory core */
#define NS_SOCRAM_CORE_ID SOCRAM_4706_CORE_ID
#define ARMCA9_CORE_ID 0x510 /* ARM Cortex A9 core (ihost) */
#define NS_IHOST_CORE_ID ARMCA9_CORE_ID /* ARM Cortex A9 core (ihost) */
#define GMAC_COMMON_4706_CORE_ID 0x5dc /* Gigabit MAC core */
#define GMAC_4706_CORE_ID 0x52d /* Gigabit MAC core */
#define AMEMC_CORE_ID 0x52e /* DDR1/2 memory controller core */
#define ALTA_CORE_ID 0x534 /* I2S core */
#define DDR23_PHY_CORE_ID 0x5dd
#define SI_PCI1_MEM 0x40000000 /* Host Mode sb2pcitranslation0 (64 MB) */
#define SI_PCI1_CFG 0x44000000 /* Host Mode sb2pcitranslation1 (64 MB) */
#define SI_PCIE1_DMA_H32 0xc0000000 /* PCIE Client Mode sb2pcitranslation2
* (2 ZettaBytes), high 32 bits
*/
#define CC_4706B0_CORE_REV 0x8000001f /* chipcommon core */
#define SOCRAM_4706B0_CORE_REV 0x80000005 /* internal memory core */
#define GMAC_4706B0_CORE_REV 0x80000000 /* Gigabit MAC core */
/* There are TWO constants on all HND chips: SI_ENUM_BASE above,
* and chipcommon being the first core:
*/
#define SI_CC_IDX 0
/* SOC Interconnect types (aka chip types) */
#define SOCI_SB 0
#define SOCI_AI 1
#define SOCI_UBUS 2
#define SOCI_NAI 3
/* Common core control flags */
#define SICF_BIST_EN 0x8000
#define SICF_PME_EN 0x4000
#define SICF_CORE_BITS 0x3ffc
#define SICF_FGC 0x0002
#define SICF_CLOCK_EN 0x0001
/* Common core status flags */
#define SISF_BIST_DONE 0x8000
#define SISF_BIST_ERROR 0x4000
#define SISF_GATED_CLK 0x2000
#define SISF_DMA64 0x1000
#define SISF_CORE_BITS 0x0fff
/* Norstar core status flags */
#define SISF_NS_BOOTDEV_MASK 0x0003 /* ROM core */
#define SISF_NS_BOOTDEV_NOR 0x0000 /* ROM core */
#define SISF_NS_BOOTDEV_NAND 0x0001 /* ROM core */
#define SISF_NS_BOOTDEV_ROM 0x0002 /* ROM core */
#define SISF_NS_BOOTDEV_OFFLOAD 0x0003 /* ROM core */
#define SISF_NS_SKUVEC_MASK 0x000c /* ROM core */
/* A register that is common to all cores to
* communicate w/PMU regarding clock control.
*/
#define SI_CLK_CTL_ST 0x1e0 /* clock control and status */
/* clk_ctl_st register */
#define CCS_FORCEALP 0x00000001 /* force ALP request */
#define CCS_FORCEHT 0x00000002 /* force HT request */
#define CCS_FORCEILP 0x00000004 /* force ILP request */
#define CCS_ALPAREQ 0x00000008 /* ALP Avail Request */
#define CCS_HTAREQ 0x00000010 /* HT Avail Request */
#define CCS_FORCEHWREQOFF 0x00000020 /* Force HW Clock Request Off */
#define CCS_HQCLKREQ 0x00000040 /* HQ Clock Required */
#define CCS_USBCLKREQ 0x00000100 /* USB Clock Req */
#define CCS_ERSRC_REQ_MASK 0x00000700 /* external resource requests */
#define CCS_ERSRC_REQ_SHIFT 8
#define CCS_ALPAVAIL 0x00010000 /* ALP is available */
#define CCS_HTAVAIL 0x00020000 /* HT is available */
#define CCS_BP_ON_APL 0x00040000 /* RO: Backplane is running on ALP clock */
#define CCS_BP_ON_HT 0x00080000 /* RO: Backplane is running on HT clock */
#define CCS_ERSRC_STS_MASK 0x07000000 /* external resource status */
#define CCS_ERSRC_STS_SHIFT 24
#define CCS0_HTAVAIL 0x00010000 /* HT avail in chipc and pcmcia on 4328a0 */
#define CCS0_ALPAVAIL 0x00020000 /* ALP avail in chipc and pcmcia on 4328a0 */
/* Not really related to SOC Interconnect, but a couple of software
* conventions for the use the flash space:
*/
/* Minumum amount of flash we support */
#define FLASH_MIN 0x00020000 /* Minimum flash size */
/* A boot/binary may have an embedded block that describes its size */
#define BISZ_OFFSET 0x3e0 /* At this offset into the binary */
#define BISZ_MAGIC 0x4249535a /* Marked with this value: 'BISZ' */
#define BISZ_MAGIC_IDX 0 /* Word 0: magic */
#define BISZ_TXTST_IDX 1 /* 1: text start */
#define BISZ_TXTEND_IDX 2 /* 2: text end */
#define BISZ_DATAST_IDX 3 /* 3: data start */
#define BISZ_DATAEND_IDX 4 /* 4: data end */
#define BISZ_BSSST_IDX 5 /* 5: bss start */
#define BISZ_BSSEND_IDX 6 /* 6: bss end */
#define BISZ_SIZE 7 /* descriptor size in 32-bit integers */
/* Boot/Kernel related defintion and functions */
#define SOC_BOOTDEV_ROM 0x00000001
#define SOC_BOOTDEV_PFLASH 0x00000002
#define SOC_BOOTDEV_SFLASH 0x00000004
#define SOC_BOOTDEV_NANDFLASH 0x00000008
#define SOC_KNLDEV_NORFLASH 0x00000002
#define SOC_KNLDEV_NANDFLASH 0x00000004
#ifndef _LANGUAGE_ASSEMBLY
int soc_boot_dev(void *sih);
int soc_knl_dev(void *sih);
#endif /* _LANGUAGE_ASSEMBLY */
#endif /* _HNDSOC_H */

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/*
* Linux OS Independent Layer
*
* $Copyright Open Broadcom Corporation$
*
* $Id: linux_osl.h 383331 2013-02-06 10:27:24Z $
*/
#ifndef _linux_osl_h_
#define _linux_osl_h_
#include <typedefs.h>
extern void * osl_os_open_image(char * filename);
extern int osl_os_get_image_block(char * buf, int len, void * image);
extern void osl_os_close_image(void * image);
extern int osl_os_image_size(void *image);
#ifdef BCMDRIVER
extern osl_t *osl_attach(void *pdev, uint bustype, bool pkttag);
extern void osl_detach(osl_t *osh);
extern uint32 g_assert_type;
#if defined(BCMASSERT_LOG)
#define ASSERT(exp) \
do { if (!(exp)) osl_assert(#exp, __FILE__, __LINE__); } while (0)
extern void osl_assert(const char *exp, const char *file, int line);
#else
#ifdef __GNUC__
#define GCC_VERSION \
(__GNUC__ * 10000 + __GNUC_MINOR__ * 100 + __GNUC_PATCHLEVEL__)
#if GCC_VERSION > 30100
#define ASSERT(exp) do {} while (0)
#else
#define ASSERT(exp)
#endif
#endif
#endif
#define OSL_DELAY(usec) osl_delay(usec)
extern void osl_delay(uint usec);
#define OSL_PCMCIA_READ_ATTR(osh, offset, buf, size) \
osl_pcmcia_read_attr((osh), (offset), (buf), (size))
#define OSL_PCMCIA_WRITE_ATTR(osh, offset, buf, size) \
osl_pcmcia_write_attr((osh), (offset), (buf), (size))
extern void osl_pcmcia_read_attr(osl_t *osh, uint offset, void *buf, int size);
extern void osl_pcmcia_write_attr(osl_t *osh, uint offset, void *buf, int size);
#define OSL_PCI_READ_CONFIG(osh, offset, size) \
osl_pci_read_config((osh), (offset), (size))
#define OSL_PCI_WRITE_CONFIG(osh, offset, size, val) \
osl_pci_write_config((osh), (offset), (size), (val))
extern uint32 osl_pci_read_config(osl_t *osh, uint offset, uint size);
extern void osl_pci_write_config(osl_t *osh, uint offset, uint size, uint val);
#define OSL_PCI_BUS(osh) osl_pci_bus(osh)
#define OSL_PCI_SLOT(osh) osl_pci_slot(osh)
extern uint osl_pci_bus(osl_t *osh);
extern uint osl_pci_slot(osl_t *osh);
extern struct pci_dev *osl_pci_device(osl_t *osh);
typedef struct {
bool pkttag;
bool mmbus;
pktfree_cb_fn_t tx_fn;
void *tx_ctx;
void *unused[3];
} osl_pubinfo_t;
#define PKTFREESETCB(osh, _tx_fn, _tx_ctx) \
do { \
((osl_pubinfo_t*)osh)->tx_fn = _tx_fn; \
((osl_pubinfo_t*)osh)->tx_ctx = _tx_ctx; \
} while (0)
#define BUS_SWAP32(v) (v)
#define MALLOC(osh, size) osl_malloc((osh), (size))
#define MFREE(osh, addr, size) osl_mfree((osh), (addr), (size))
#define MALLOCED(osh) osl_malloced((osh))
extern void *osl_malloc(osl_t *osh, uint size);
extern void osl_mfree(osl_t *osh, void *addr, uint size);
extern uint osl_malloced(osl_t *osh);
#define NATIVE_MALLOC(osh, size) kmalloc(size, GFP_ATOMIC)
#define NATIVE_MFREE(osh, addr, size) kfree(addr)
#define MALLOC_FAILED(osh) osl_malloc_failed((osh))
extern uint osl_malloc_failed(osl_t *osh);
#define DMA_CONSISTENT_ALIGN osl_dma_consistent_align()
#define DMA_ALLOC_CONSISTENT(osh, size, align, tot, pap, dmah) \
osl_dma_alloc_consistent((osh), (size), (align), (tot), (pap))
#define DMA_FREE_CONSISTENT(osh, va, size, pa, dmah) \
osl_dma_free_consistent((osh), (void*)(va), (size), (pa))
#define DMA_ALLOC_CONSISTENT_FORCE32(osh, size, align, tot, pap, dmah) \
osl_dma_alloc_consistent((osh), (size), (align), (tot), (pap))
#define DMA_FREE_CONSISTENT_FORCE32(osh, va, size, pa, dmah) \
osl_dma_free_consistent((osh), (void*)(va), (size), (pa))
extern uint osl_dma_consistent_align(void);
extern void *osl_dma_alloc_consistent(osl_t *osh, uint size, uint16 align, uint *tot, ulong *pap);
extern void osl_dma_free_consistent(osl_t *osh, void *va, uint size, ulong pa);
#define DMA_TX 1
#define DMA_RX 2
#define DMA_UNMAP(osh, pa, size, direction, p, dmah) \
osl_dma_unmap((osh), (pa), (size), (direction))
extern uint osl_dma_map(osl_t *osh, void *va, uint size, int direction, void *p,
hnddma_seg_map_t *txp_dmah);
extern void osl_dma_unmap(osl_t *osh, uint pa, uint size, int direction);
#define OSL_DMADDRWIDTH(osh, addrwidth) do {} while (0)
#include <bcmsdh.h>
#define OSL_WRITE_REG(osh, r, v) (bcmsdh_reg_write(NULL, (uintptr)(r), sizeof(*(r)), (v)))
#define OSL_READ_REG(osh, r) (bcmsdh_reg_read(NULL, (uintptr)(r), sizeof(*(r))))
#define SELECT_BUS_WRITE(osh, mmap_op, bus_op) if (((osl_pubinfo_t*)(osh))->mmbus) \
mmap_op else bus_op
#define SELECT_BUS_READ(osh, mmap_op, bus_op) (((osl_pubinfo_t*)(osh))->mmbus) ? \
mmap_op : bus_op
#define OSL_ERROR(bcmerror) osl_error(bcmerror)
extern int osl_error(int bcmerror);
#define PKTBUFSZ 2048
#include <linuxver.h>
#include <linux/kernel.h>
#include <linux/string.h>
#define OSL_SYSUPTIME() ((uint32)jiffies * (1000 / HZ))
#define printf(fmt, args...) printk(fmt , ## args)
#include <linux/kernel.h>
#include <linux/string.h>
#define bcopy(src, dst, len) memcpy((dst), (src), (len))
#define bcmp(b1, b2, len) memcmp((b1), (b2), (len))
#define bzero(b, len) memset((b), '\0', (len))
#define R_REG(osh, r) (\
SELECT_BUS_READ(osh, \
({ \
__typeof(*(r)) __osl_v; \
BCM_REFERENCE(osh); \
switch (sizeof(*(r))) { \
case sizeof(uint8): __osl_v = \
readb((volatile uint8*)(r)); break; \
case sizeof(uint16): __osl_v = \
readw((volatile uint16*)(r)); break; \
case sizeof(uint32): __osl_v = \
readl((volatile uint32*)(r)); break; \
} \
__osl_v; \
}), \
OSL_READ_REG(osh, r)) \
)
#define W_REG(osh, r, v) do { \
BCM_REFERENCE(osh); \
SELECT_BUS_WRITE(osh, \
switch (sizeof(*(r))) { \
case sizeof(uint8): writeb((uint8)(v), (volatile uint8*)(r)); break; \
case sizeof(uint16): writew((uint16)(v), (volatile uint16*)(r)); break; \
case sizeof(uint32): writel((uint32)(v), (volatile uint32*)(r)); break; \
}, \
(OSL_WRITE_REG(osh, r, v))); \
} while (0)
#define AND_REG(osh, r, v) W_REG(osh, (r), R_REG(osh, r) & (v))
#define OR_REG(osh, r, v) W_REG(osh, (r), R_REG(osh, r) | (v))
#define bcopy(src, dst, len) memcpy((dst), (src), (len))
#define bcmp(b1, b2, len) memcmp((b1), (b2), (len))
#define bzero(b, len) memset((b), '\0', (len))
#define OSL_UNCACHED(va) ((void *)va)
#define OSL_CACHED(va) ((void *)va)
#define OSL_CACHE_FLUSH(va, len)
#define OSL_PREF_RANGE_LD(va, sz)
#define OSL_PREF_RANGE_ST(va, sz)
#if defined(__i386__)
#define OSL_GETCYCLES(x) rdtscl((x))
#else
#define OSL_GETCYCLES(x) ((x) = 0)
#endif
#define BUSPROBE(val, addr) ({ (val) = R_REG(NULL, (addr)); 0; })
#if !defined(CONFIG_MMC_MSM7X00A)
#define REG_MAP(pa, size) ioremap_nocache((unsigned long)(pa), (unsigned long)(size))
#else
#define REG_MAP(pa, size) (void *)(0)
#endif
#define REG_UNMAP(va) iounmap((va))
#define R_SM(r) *(r)
#define W_SM(r, v) (*(r) = (v))
#define BZERO_SM(r, len) memset((r), '\0', (len))
#include <linuxver.h>
#ifdef BCMDBG_CTRACE
#define PKTGET(osh, len, send) osl_pktget((osh), (len), __LINE__, __FILE__)
#define PKTDUP(osh, skb) osl_pktdup((osh), (skb), __LINE__, __FILE__)
#else
#define PKTGET(osh, len, send) osl_pktget((osh), (len))
#define PKTDUP(osh, skb) osl_pktdup((osh), (skb))
#endif
#define PKTLIST_DUMP(osh, buf)
#define PKTDBG_TRACE(osh, pkt, bit)
#define PKTFREE(osh, skb, send) osl_pktfree((osh), (skb), (send))
#ifdef DHD_USE_STATIC_BUF
#define PKTGET_STATIC(osh, len, send) osl_pktget_static((osh), (len))
#define PKTFREE_STATIC(osh, skb, send) osl_pktfree_static((osh), (skb), (send))
#endif
#define PKTDATA(osh, skb) (((struct sk_buff*)(skb))->data)
#define PKTLEN(osh, skb) (((struct sk_buff*)(skb))->len)
#define PKTHEADROOM(osh, skb) (PKTDATA(osh, skb)-(((struct sk_buff*)(skb))->head))
#define PKTTAILROOM(osh, skb) skb_tailroom((struct sk_buff*)(skb))
#define PKTNEXT(osh, skb) (((struct sk_buff*)(skb))->next)
#define PKTSETNEXT(osh, skb, x) (((struct sk_buff*)(skb))->next = (struct sk_buff*)(x))
#define PKTSETLEN(osh, skb, len) __skb_trim((struct sk_buff*)(skb), (len))
#define PKTPUSH(osh, skb, bytes) skb_push((struct sk_buff*)(skb), (bytes))
#define PKTPULL(osh, skb, bytes) skb_pull((struct sk_buff*)(skb), (bytes))
#define PKTTAG(skb) ((void*)(((struct sk_buff*)(skb))->cb))
#define PKTSETPOOL(osh, skb, x, y) do {} while (0)
#define PKTPOOL(osh, skb) FALSE
#define PKTSHRINK(osh, m) (m)
#ifdef BCMDBG_CTRACE
#define DEL_CTRACE(zosh, zskb) { \
unsigned long zflags; \
spin_lock_irqsave(&(zosh)->ctrace_lock, zflags); \
list_del(&(zskb)->ctrace_list); \
(zosh)->ctrace_num--; \
(zskb)->ctrace_start = 0; \
(zskb)->ctrace_count = 0; \
spin_unlock_irqrestore(&(zosh)->ctrace_lock, zflags); \
}
#define UPDATE_CTRACE(zskb, zfile, zline) { \
struct sk_buff *_zskb = (struct sk_buff *)(zskb); \
if (_zskb->ctrace_count < CTRACE_NUM) { \
_zskb->func[_zskb->ctrace_count] = zfile; \
_zskb->line[_zskb->ctrace_count] = zline; \
_zskb->ctrace_count++; \
} \
else { \
_zskb->func[_zskb->ctrace_start] = zfile; \
_zskb->line[_zskb->ctrace_start] = zline; \
_zskb->ctrace_start++; \
if (_zskb->ctrace_start >= CTRACE_NUM) \
_zskb->ctrace_start = 0; \
} \
}
#define ADD_CTRACE(zosh, zskb, zfile, zline) { \
unsigned long zflags; \
spin_lock_irqsave(&(zosh)->ctrace_lock, zflags); \
list_add(&(zskb)->ctrace_list, &(zosh)->ctrace_list); \
(zosh)->ctrace_num++; \
UPDATE_CTRACE(zskb, zfile, zline); \
spin_unlock_irqrestore(&(zosh)->ctrace_lock, zflags); \
}
#define PKTCALLER(zskb) UPDATE_CTRACE((struct sk_buff *)zskb, (char *)__FUNCTION__, __LINE__)
#endif
#ifdef CTFPOOL
#define CTFPOOL_REFILL_THRESH 3
typedef struct ctfpool {
void *head;
spinlock_t lock;
uint max_obj;
uint curr_obj;
uint obj_size;
uint refills;
uint fast_allocs;
uint fast_frees;
uint slow_allocs;
} ctfpool_t;
#if LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 22)
#if LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 36)
#define FASTBUF (1 << 0)
#define CTFBUF (1 << 1)
#define PKTSETFAST(osh, skb) ((((struct sk_buff*)(skb))->pktc_flags) |= FASTBUF)
#define PKTCLRFAST(osh, skb) ((((struct sk_buff*)(skb))->pktc_flags) &= (~FASTBUF))
#define PKTSETCTF(osh, skb) ((((struct sk_buff*)(skb))->pktc_flags) |= CTFBUF)
#define PKTCLRCTF(osh, skb) ((((struct sk_buff*)(skb))->pktc_flags) &= (~CTFBUF))
#define PKTISFAST(osh, skb) ((((struct sk_buff*)(skb))->pktc_flags) & FASTBUF)
#define PKTISCTF(osh, skb) ((((struct sk_buff*)(skb))->pktc_flags) & CTFBUF)
#define PKTFAST(osh, skb) (((struct sk_buff*)(skb))->pktc_flags)
#else
#define FASTBUF (1 << 16)
#define CTFBUF (1 << 17)
#define PKTSETFAST(osh, skb) ((((struct sk_buff*)(skb))->mac_len) |= FASTBUF)
#define PKTCLRFAST(osh, skb) ((((struct sk_buff*)(skb))->mac_len) &= (~FASTBUF))
#define PKTSETCTF(osh, skb) ((((struct sk_buff*)(skb))->mac_len) |= CTFBUF)
#define PKTCLRCTF(osh, skb) ((((struct sk_buff*)(skb))->mac_len) &= (~CTFBUF))
#define PKTISFAST(osh, skb) ((((struct sk_buff*)(skb))->mac_len) & FASTBUF)
#define PKTISCTF(osh, skb) ((((struct sk_buff*)(skb))->mac_len) & CTFBUF)
#define PKTFAST(osh, skb) (((struct sk_buff*)(skb))->mac_len)
#endif
#else
#define FASTBUF (1 << 0)
#define CTFBUF (1 << 1)
#define PKTSETFAST(osh, skb) ((((struct sk_buff*)(skb))->__unused) |= FASTBUF)
#define PKTCLRFAST(osh, skb) ((((struct sk_buff*)(skb))->__unused) &= (~FASTBUF))
#define PKTSETCTF(osh, skb) ((((struct sk_buff*)(skb))->__unused) |= CTFBUF)
#define PKTCLRCTF(osh, skb) ((((struct sk_buff*)(skb))->__unused) &= (~CTFBUF))
#define PKTISFAST(osh, skb) ((((struct sk_buff*)(skb))->__unused) & FASTBUF)
#define PKTISCTF(osh, skb) ((((struct sk_buff*)(skb))->__unused) & CTFBUF)
#define PKTFAST(osh, skb) (((struct sk_buff*)(skb))->__unused)
#endif
#if LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 36)
#define CTFPOOLPTR(osh, skb) (((struct sk_buff*)(skb))->ctfpool)
#define CTFPOOLHEAD(osh, skb) (((ctfpool_t *)((struct sk_buff*)(skb))->ctfpool)->head)
#else
#define CTFPOOLPTR(osh, skb) (((struct sk_buff*)(skb))->sk)
#define CTFPOOLHEAD(osh, skb) (((ctfpool_t *)((struct sk_buff*)(skb))->sk)->head)
#endif
extern void *osl_ctfpool_add(osl_t *osh);
extern void osl_ctfpool_replenish(osl_t *osh, uint thresh);
extern int32 osl_ctfpool_init(osl_t *osh, uint numobj, uint size);
extern void osl_ctfpool_cleanup(osl_t *osh);
extern void osl_ctfpool_stats(osl_t *osh, void *b);
#endif
#ifdef HNDCTF
#if LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 22)
#if LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 36)
#define SKIPCT (1 << 2)
#define CHAINED (1 << 3)
#define PKTSETSKIPCT(osh, skb) (((struct sk_buff*)(skb))->pktc_flags |= SKIPCT)
#define PKTCLRSKIPCT(osh, skb) (((struct sk_buff*)(skb))->pktc_flags &= (~SKIPCT))
#define PKTSKIPCT(osh, skb) (((struct sk_buff*)(skb))->pktc_flags & SKIPCT)
#define PKTSETCHAINED(osh, skb) (((struct sk_buff*)(skb))->pktc_flags |= CHAINED)
#define PKTCLRCHAINED(osh, skb) (((struct sk_buff*)(skb))->pktc_flags &= (~CHAINED))
#define PKTISCHAINED(skb) (((struct sk_buff*)(skb))->pktc_flags & CHAINED)
#else
#define SKIPCT (1 << 18)
#define CHAINED (1 << 19)
#define PKTSETSKIPCT(osh, skb) (((struct sk_buff*)(skb))->mac_len |= SKIPCT)
#define PKTCLRSKIPCT(osh, skb) (((struct sk_buff*)(skb))->mac_len &= (~SKIPCT))
#define PKTSKIPCT(osh, skb) (((struct sk_buff*)(skb))->mac_len & SKIPCT)
#define PKTSETCHAINED(osh, skb) (((struct sk_buff*)(skb))->mac_len |= CHAINED)
#define PKTCLRCHAINED(osh, skb) (((struct sk_buff*)(skb))->mac_len &= (~CHAINED))
#define PKTISCHAINED(skb) (((struct sk_buff*)(skb))->mac_len & CHAINED)
#endif
#else
#define SKIPCT (1 << 2)
#define CHAINED (1 << 3)
#define PKTSETSKIPCT(osh, skb) (((struct sk_buff*)(skb))->__unused |= SKIPCT)
#define PKTCLRSKIPCT(osh, skb) (((struct sk_buff*)(skb))->__unused &= (~SKIPCT))
#define PKTSKIPCT(osh, skb) (((struct sk_buff*)(skb))->__unused & SKIPCT)
#define PKTSETCHAINED(osh, skb) (((struct sk_buff*)(skb))->__unused |= CHAINED)
#define PKTCLRCHAINED(osh, skb) (((struct sk_buff*)(skb))->__unused &= (~CHAINED))
#define PKTISCHAINED(skb) (((struct sk_buff*)(skb))->__unused & CHAINED)
#endif
typedef struct ctf_mark {
uint32 value;
} ctf_mark_t;
#define CTF_MARK(m) (m.value)
#else
#define PKTSETSKIPCT(osh, skb)
#define PKTCLRSKIPCT(osh, skb)
#define PKTSKIPCT(osh, skb)
#define CTF_MARK(m) 0
#endif
extern void osl_pktfree(osl_t *osh, void *skb, bool send);
extern void *osl_pktget_static(osl_t *osh, uint len);
extern void osl_pktfree_static(osl_t *osh, void *skb, bool send);
#ifdef BCMDBG_CTRACE
#define PKT_CTRACE_DUMP(osh, b) osl_ctrace_dump((osh), (b))
extern void *osl_pktget(osl_t *osh, uint len, int line, char *file);
extern void *osl_pkt_frmnative(osl_t *osh, void *skb, int line, char *file);
extern int osl_pkt_is_frmnative(osl_t *osh, struct sk_buff *pkt);
extern void *osl_pktdup(osl_t *osh, void *skb, int line, char *file);
struct bcmstrbuf;
extern void osl_ctrace_dump(osl_t *osh, struct bcmstrbuf *b);
#else
extern void *osl_pkt_frmnative(osl_t *osh, void *skb);
extern void *osl_pktget(osl_t *osh, uint len);
extern void *osl_pktdup(osl_t *osh, void *skb);
#endif
extern struct sk_buff *osl_pkt_tonative(osl_t *osh, void *pkt);
#ifdef BCMDBG_CTRACE
#define PKTFRMNATIVE(osh, skb) osl_pkt_frmnative(((osl_t *)osh), \
(struct sk_buff*)(skb), __LINE__, __FILE__)
#define PKTISFRMNATIVE(osh, skb) osl_pkt_is_frmnative((osl_t *)(osh), (struct sk_buff *)(skb))
#else
#define PKTFRMNATIVE(osh, skb) osl_pkt_frmnative(((osl_t *)osh), (struct sk_buff*)(skb))
#endif
#define PKTTONATIVE(osh, pkt) osl_pkt_tonative((osl_t *)(osh), (pkt))
#define PKTLINK(skb) (((struct sk_buff*)(skb))->prev)
#define PKTSETLINK(skb, x) (((struct sk_buff*)(skb))->prev = (struct sk_buff*)(x))
#define PKTPRIO(skb) (((struct sk_buff*)(skb))->priority)
#define PKTSETPRIO(skb, x) (((struct sk_buff*)(skb))->priority = (x))
#define PKTSUMNEEDED(skb) (((struct sk_buff*)(skb))->ip_summed == CHECKSUM_HW)
#define PKTSETSUMGOOD(skb, x) (((struct sk_buff*)(skb))->ip_summed = \
((x) ? CHECKSUM_UNNECESSARY : CHECKSUM_NONE))
#define PKTSHARED(skb) (((struct sk_buff*)(skb))->cloned)
#ifdef CONFIG_NF_CONNTRACK_MARK
#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 0))
#define PKTMARK(p) (((struct sk_buff *)(p))->mark)
#define PKTSETMARK(p, m) ((struct sk_buff *)(p))->mark = (m)
#else
#define PKTMARK(p) (((struct sk_buff *)(p))->nfmark)
#define PKTSETMARK(p, m) ((struct sk_buff *)(p))->nfmark = (m)
#endif
#else
#define PKTMARK(p) 0
#define PKTSETMARK(p, m)
#endif
#define PKTALLOCED(osh) osl_pktalloced(osh)
extern uint osl_pktalloced(osl_t *osh);
#define DMA_MAP(osh, va, size, direction, p, dmah) \
osl_dma_map((osh), (va), (size), (direction), (p), (dmah))
#ifdef PKTC
struct chain_node {
struct sk_buff *link;
unsigned int flags:3, pkts:9, bytes:20;
};
#define CHAIN_NODE(skb) ((struct chain_node*)(((struct sk_buff*)skb)->pktc_cb))
#define PKTCSETATTR(s, f, p, b) ({CHAIN_NODE(s)->flags = (f); CHAIN_NODE(s)->pkts = (p); \
CHAIN_NODE(s)->bytes = (b);})
#define PKTCCLRATTR(s) ({CHAIN_NODE(s)->flags = CHAIN_NODE(s)->pkts = \
CHAIN_NODE(s)->bytes = 0;})
#define PKTCGETATTR(s) (CHAIN_NODE(s)->flags << 29 | CHAIN_NODE(s)->pkts << 20 | \
CHAIN_NODE(s)->bytes)
#define PKTCCNT(skb) (CHAIN_NODE(skb)->pkts)
#define PKTCLEN(skb) (CHAIN_NODE(skb)->bytes)
#define PKTCGETFLAGS(skb) (CHAIN_NODE(skb)->flags)
#define PKTCSETFLAGS(skb, f) (CHAIN_NODE(skb)->flags = (f))
#define PKTCCLRFLAGS(skb) (CHAIN_NODE(skb)->flags = 0)
#define PKTCFLAGS(skb) (CHAIN_NODE(skb)->flags)
#define PKTCSETCNT(skb, c) (CHAIN_NODE(skb)->pkts = (c))
#define PKTCINCRCNT(skb) (CHAIN_NODE(skb)->pkts++)
#define PKTCADDCNT(skb, c) (CHAIN_NODE(skb)->pkts += (c))
#define PKTCSETLEN(skb, l) (CHAIN_NODE(skb)->bytes = (l))
#define PKTCADDLEN(skb, l) (CHAIN_NODE(skb)->bytes += (l))
#define PKTCSETFLAG(skb, fb) (CHAIN_NODE(skb)->flags |= (fb))
#define PKTCCLRFLAG(skb, fb) (CHAIN_NODE(skb)->flags &= ~(fb))
#define PKTCLINK(skb) (CHAIN_NODE(skb)->link)
#define PKTSETCLINK(skb, x) (CHAIN_NODE(skb)->link = (struct sk_buff*)(x))
#define FOREACH_CHAINED_PKT(skb, nskb) \
for (; (skb) != NULL; (skb) = (nskb)) \
if ((nskb) = (PKTISCHAINED(skb) ? PKTCLINK(skb) : NULL), \
PKTSETCLINK((skb), NULL), 1)
#define PKTCFREE(osh, skb, send) \
do { \
void *nskb; \
ASSERT((skb) != NULL); \
FOREACH_CHAINED_PKT((skb), nskb) { \
PKTCLRCHAINED((osh), (skb)); \
PKTCCLRFLAGS((skb)); \
PKTFREE((osh), (skb), (send)); \
} \
} while (0)
#define PKTCENQTAIL(h, t, p) \
do { \
if ((t) == NULL) { \
(h) = (t) = (p); \
} else { \
PKTSETCLINK((t), (p)); \
(t) = (p); \
} \
} while (0)
#endif
#else
#define ASSERT(exp) do {} while (0)
#define MALLOC(o, l) malloc(l)
#define MFREE(o, p, l) free(p)
#include <stdlib.h>
#include <string.h>
#include <stdio.h>
extern void bcopy(const void *src, void *dst, size_t len);
extern int bcmp(const void *b1, const void *b2, size_t len);
extern void bzero(void *b, size_t len);
#endif
#endif

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external/cache/sources/wl/include/linuxver.h vendored Normal file
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/*
* Linux-specific abstractions to gain some independence from linux kernel versions.
* Pave over some 2.2 versus 2.4 versus 2.6 kernel differences.
*
* $Copyright Open Broadcom Corporation$
*
* $Id: linuxver.h 372519 2012-12-04 01:21:16Z $
*/
#ifndef _linuxver_h_
#define _linuxver_h_
#include <linux/version.h>
#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 0))
#include <linux/config.h>
#else
#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 33))
#include <generated/autoconf.h>
#else
#include <linux/autoconf.h>
#endif
#endif
#if (LINUX_VERSION_CODE >= KERNEL_VERSION(3, 1, 0))
#include <linux/kconfig.h>
#endif
#include <linux/module.h>
#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 3, 0))
#ifdef __UNDEF_NO_VERSION__
#undef __NO_VERSION__
#else
#define __NO_VERSION__
#endif
#endif
#if LINUX_VERSION_CODE < KERNEL_VERSION(2, 5, 0)
#define module_param(_name_, _type_, _perm_) MODULE_PARM(_name_, "i")
#define module_param_string(_name_, _string_, _size_, _perm_) \
MODULE_PARM(_string_, "c" __MODULE_STRING(_size_))
#endif
#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 4, 9))
#include <linux/malloc.h>
#else
#include <linux/slab.h>
#endif
#include <linux/types.h>
#include <linux/init.h>
#include <linux/mm.h>
#include <linux/string.h>
#include <linux/pci.h>
#include <linux/interrupt.h>
#include <linux/netdevice.h>
#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 27))
#include <linux/semaphore.h>
#else
#include <asm/semaphore.h>
#endif
#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 28))
#undef IP_TOS
#endif
#include <asm/io.h>
#if (LINUX_VERSION_CODE > KERNEL_VERSION(2, 5, 41))
#include <linux/workqueue.h>
#else
#include <linux/tqueue.h>
#ifndef work_struct
#define work_struct tq_struct
#endif
#ifndef INIT_WORK
#define INIT_WORK(_work, _func, _data) INIT_TQUEUE((_work), (_func), (_data))
#endif
#ifndef schedule_work
#define schedule_work(_work) schedule_task((_work))
#endif
#ifndef flush_scheduled_work
#define flush_scheduled_work() flush_scheduled_tasks()
#endif
#endif
#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 0))
#define DAEMONIZE(a) daemonize(a); \
allow_signal(SIGKILL); \
allow_signal(SIGTERM);
#else
#define RAISE_RX_SOFTIRQ() \
cpu_raise_softirq(smp_processor_id(), NET_RX_SOFTIRQ)
#define DAEMONIZE(a) daemonize(); \
do { if (a) \
strncpy(current->comm, a, MIN(sizeof(current->comm), (strlen(a)))); \
} while (0);
#endif
#if LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 19)
#define MY_INIT_WORK(_work, _func) INIT_WORK(_work, _func)
#else
#define MY_INIT_WORK(_work, _func) INIT_WORK(_work, _func, _work)
#if !(LINUX_VERSION_CODE == KERNEL_VERSION(2, 6, 18) && defined(RHEL_MAJOR) && \
(RHEL_MAJOR == 5))
typedef void (*work_func_t)(void *work);
#endif
#endif
#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 0))
#ifndef IRQ_NONE
typedef void irqreturn_t;
#define IRQ_NONE
#define IRQ_HANDLED
#define IRQ_RETVAL(x)
#endif
#else
typedef irqreturn_t(*FN_ISR) (int irq, void *dev_id, struct pt_regs *ptregs);
#endif
#if LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 18)
#define IRQF_SHARED SA_SHIRQ
#endif
#if LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 17)
#ifdef CONFIG_NET_RADIO
#define CONFIG_WIRELESS_EXT
#endif
#endif
#if LINUX_VERSION_CODE >= KERNEL_VERSION(2, 5, 67)
#define MOD_INC_USE_COUNT
#define MOD_DEC_USE_COUNT
#endif
#if LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 32)
#include <linux/sched.h>
#endif
#if LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 29)
#include <net/lib80211.h>
#endif
#if LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 29)
#include <linux/ieee80211.h>
#else
#if LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 14)
#include <net/ieee80211.h>
#endif
#endif
#ifdef CUSTOMER_HW4
#include <linux/kthread.h>
#endif
#ifndef __exit
#define __exit
#endif
#ifndef __devexit
#define __devexit
#endif
#ifndef __devinit
#define __devinit __init
#endif
#ifndef __devinitdata
#define __devinitdata
#endif
#ifndef __devexit_p
#define __devexit_p(x) x
#endif
#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 4, 0))
#define pci_get_drvdata(dev) (dev)->sysdata
#define pci_set_drvdata(dev, value) (dev)->sysdata = (value)
struct pci_device_id {
unsigned int vendor, device;
unsigned int subvendor, subdevice;
unsigned int class, class_mask;
unsigned long driver_data;
};
struct pci_driver {
struct list_head node;
char *name;
const struct pci_device_id *id_table;
int (*probe)(struct pci_dev *dev,
const struct pci_device_id *id);
void (*remove)(struct pci_dev *dev);
void (*suspend)(struct pci_dev *dev);
void (*resume)(struct pci_dev *dev);
};
#define MODULE_DEVICE_TABLE(type, name)
#define PCI_ANY_ID (~0)
#define pci_module_init pci_register_driver
extern int pci_register_driver(struct pci_driver *drv);
extern void pci_unregister_driver(struct pci_driver *drv);
#endif
#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 18))
#define pci_module_init pci_register_driver
#endif
#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 2, 18))
#ifdef MODULE
#define module_init(x) int init_module(void) { return x(); }
#define module_exit(x) void cleanup_module(void) { x(); }
#else
#define module_init(x) __initcall(x);
#define module_exit(x) __exitcall(x);
#endif
#endif
#if LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 31)
#define WL_USE_NETDEV_OPS
#else
#undef WL_USE_NETDEV_OPS
#endif
#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 31)) && defined(CONFIG_RFKILL)
#define WL_CONFIG_RFKILL
#else
#undef WL_CONFIG_RFKILL
#endif
#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 3, 48))
#define list_for_each(pos, head) \
for (pos = (head)->next; pos != (head); pos = pos->next)
#endif
#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 3, 13))
#define pci_resource_start(dev, bar) ((dev)->base_address[(bar)])
#elif (LINUX_VERSION_CODE < KERNEL_VERSION(2, 3, 44))
#define pci_resource_start(dev, bar) ((dev)->resource[(bar)].start)
#endif
#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 3, 23))
#define pci_enable_device(dev) do { } while (0)
#endif
#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 3, 14))
#define net_device device
#endif
#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 3, 42))
#ifndef PCI_DMA_TODEVICE
#define PCI_DMA_TODEVICE 1
#define PCI_DMA_FROMDEVICE 2
#endif
typedef u32 dma_addr_t;
static inline int get_order(unsigned long size)
{
int order;
size = (size-1) >> (PAGE_SHIFT-1);
order = -1;
do {
size >>= 1;
order++;
} while (size);
return order;
}
static inline void *pci_alloc_consistent(struct pci_dev *hwdev, size_t size,
dma_addr_t *dma_handle)
{
void *ret;
int gfp = GFP_ATOMIC | GFP_DMA;
ret = (void *)__get_free_pages(gfp, get_order(size));
if (ret != NULL) {
memset(ret, 0, size);
*dma_handle = virt_to_bus(ret);
}
return ret;
}
static inline void pci_free_consistent(struct pci_dev *hwdev, size_t size,
void *vaddr, dma_addr_t dma_handle)
{
free_pages((unsigned long)vaddr, get_order(size));
}
#define pci_map_single(cookie, address, size, dir) virt_to_bus(address)
#define pci_unmap_single(cookie, address, size, dir)
#endif
#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 3, 43))
#define dev_kfree_skb_any(a) dev_kfree_skb(a)
#define netif_down(dev) do { (dev)->start = 0; } while (0)
#ifndef _COMPAT_NETDEVICE_H
#define dev_kfree_skb_irq(a) dev_kfree_skb(a)
#define netif_wake_queue(dev) \
do { clear_bit(0, &(dev)->tbusy); mark_bh(NET_BH); } while (0)
#define netif_stop_queue(dev) set_bit(0, &(dev)->tbusy)
static inline void netif_start_queue(struct net_device *dev)
{
dev->tbusy = 0;
dev->interrupt = 0;
dev->start = 1;
}
#define netif_queue_stopped(dev) (dev)->tbusy
#define netif_running(dev) (dev)->start
#endif
#define netif_device_attach(dev) netif_start_queue(dev)
#define netif_device_detach(dev) netif_stop_queue(dev)
#define tasklet_struct tq_struct
static inline void tasklet_schedule(struct tasklet_struct *tasklet)
{
queue_task(tasklet, &tq_immediate);
mark_bh(IMMEDIATE_BH);
}
static inline void tasklet_init(struct tasklet_struct *tasklet,
void (*func)(unsigned long),
unsigned long data)
{
tasklet->next = NULL;
tasklet->sync = 0;
tasklet->routine = (void (*)(void *))func;
tasklet->data = (void *)data;
}
#define tasklet_kill(tasklet) { do {} while (0); }
#define del_timer_sync(timer) del_timer(timer)
#else
#define netif_down(dev)
#endif
#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 4, 3))
#define PREPARE_TQUEUE(_tq, _routine, _data) \
do { \
(_tq)->routine = _routine; \
(_tq)->data = _data; \
} while (0)
#define INIT_TQUEUE(_tq, _routine, _data) \
do { \
INIT_LIST_HEAD(&(_tq)->list); \
(_tq)->sync = 0; \
PREPARE_TQUEUE((_tq), (_routine), (_data)); \
} while (0)
#endif
#if LINUX_VERSION_CODE > KERNEL_VERSION(2, 6, 9)
#define PCI_SAVE_STATE(a, b) pci_save_state(a)
#define PCI_RESTORE_STATE(a, b) pci_restore_state(a)
#else
#define PCI_SAVE_STATE(a, b) pci_save_state(a, b)
#define PCI_RESTORE_STATE(a, b) pci_restore_state(a, b)
#endif
#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 4, 6))
static inline int
pci_save_state(struct pci_dev *dev, u32 *buffer)
{
int i;
if (buffer) {
for (i = 0; i < 16; i++)
pci_read_config_dword(dev, i * 4, &buffer[i]);
}
return 0;
}
static inline int
pci_restore_state(struct pci_dev *dev, u32 *buffer)
{
int i;
if (buffer) {
for (i = 0; i < 16; i++)
pci_write_config_dword(dev, i * 4, buffer[i]);
}
else {
for (i = 0; i < 6; i ++)
pci_write_config_dword(dev,
PCI_BASE_ADDRESS_0 + (i * 4),
pci_resource_start(dev, i));
pci_write_config_byte(dev, PCI_INTERRUPT_LINE, dev->irq);
}
return 0;
}
#endif
#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 4, 19))
#define read_c0_count() read_32bit_cp0_register(CP0_COUNT)
#endif
#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 24))
#ifndef SET_MODULE_OWNER
#define SET_MODULE_OWNER(dev) do {} while (0)
#define OLD_MOD_INC_USE_COUNT MOD_INC_USE_COUNT
#define OLD_MOD_DEC_USE_COUNT MOD_DEC_USE_COUNT
#else
#define OLD_MOD_INC_USE_COUNT do {} while (0)
#define OLD_MOD_DEC_USE_COUNT do {} while (0)
#endif
#else
#ifndef SET_MODULE_OWNER
#define SET_MODULE_OWNER(dev) do {} while (0)
#endif
#ifndef MOD_INC_USE_COUNT
#define MOD_INC_USE_COUNT do {} while (0)
#endif
#ifndef MOD_DEC_USE_COUNT
#define MOD_DEC_USE_COUNT do {} while (0)
#endif
#define OLD_MOD_INC_USE_COUNT MOD_INC_USE_COUNT
#define OLD_MOD_DEC_USE_COUNT MOD_DEC_USE_COUNT
#endif
#ifndef SET_NETDEV_DEV
#define SET_NETDEV_DEV(net, pdev) do {} while (0)
#endif
#ifndef HAVE_FREE_NETDEV
#define free_netdev(dev) kfree(dev)
#endif
#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 0))
#define af_packet_priv data
#endif
#if LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 11)
#define DRV_SUSPEND_STATE_TYPE pm_message_t
#else
#define DRV_SUSPEND_STATE_TYPE uint32
#endif
#if LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 19)
#define CHECKSUM_HW CHECKSUM_PARTIAL
#endif
typedef struct {
void *parent;
struct task_struct *p_task;
long thr_pid;
int prio;
struct semaphore sema;
int terminated;
struct completion completed;
} tsk_ctl_t;
#ifdef DHD_DEBUG
#define DBG_THR(x) printk x
#else
#define DBG_THR(x)
#endif
#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 0))
#define SMP_RD_BARRIER_DEPENDS(x) smp_read_barrier_depends(x)
#else
#define SMP_RD_BARRIER_DEPENDS(x) smp_rmb(x)
#endif
#define PROC_START(thread_func, owner, tsk_ctl, flags) \
{ \
sema_init(&((tsk_ctl)->sema), 0); \
init_completion(&((tsk_ctl)->completed)); \
(tsk_ctl)->parent = owner; \
(tsk_ctl)->terminated = FALSE; \
(tsk_ctl)->thr_pid = kernel_thread(thread_func, tsk_ctl, flags); \
if ((tsk_ctl)->thr_pid > 0) \
wait_for_completion(&((tsk_ctl)->completed)); \
DBG_THR(("%s thr:%lx started\n", __FUNCTION__, (tsk_ctl)->thr_pid)); \
}
#ifdef USE_KTHREAD_API
#define PROC_START2(thread_func, owner, tsk_ctl, flags, name) \
{ \
sema_init(&((tsk_ctl)->sema), 0); \
init_completion(&((tsk_ctl)->completed)); \
(tsk_ctl)->parent = owner; \
(tsk_ctl)->terminated = FALSE; \
(tsk_ctl)->p_task = kthread_run(thread_func, tsk_ctl, (char*)name); \
(tsk_ctl)->thr_pid = (tsk_ctl)->p_task->pid; \
DBG_THR(("%s thr:%lx created\n", __FUNCTION__, (tsk_ctl)->thr_pid)); \
}
#endif
#define PROC_STOP(tsk_ctl) \
{ \
(tsk_ctl)->terminated = TRUE; \
smp_wmb(); \
up(&((tsk_ctl)->sema)); \
wait_for_completion(&((tsk_ctl)->completed)); \
DBG_THR(("%s thr:%lx terminated OK\n", __FUNCTION__, (tsk_ctl)->thr_pid)); \
(tsk_ctl)->thr_pid = -1; \
}
#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 31))
#define KILL_PROC(nr, sig) \
{ \
struct task_struct *tsk; \
struct pid *pid; \
pid = find_get_pid((pid_t)nr); \
tsk = pid_task(pid, PIDTYPE_PID); \
if (tsk) send_sig(sig, tsk, 1); \
}
#else
#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 27)) && (LINUX_VERSION_CODE <= \
KERNEL_VERSION(2, 6, 30))
#define KILL_PROC(pid, sig) \
{ \
struct task_struct *tsk; \
tsk = find_task_by_vpid(pid); \
if (tsk) send_sig(sig, tsk, 1); \
}
#else
#define KILL_PROC(pid, sig) \
{ \
kill_proc(pid, sig, 1); \
}
#endif
#endif
#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 0))
#include <linux/time.h>
#include <linux/wait.h>
#else
#include <linux/sched.h>
#define __wait_event_interruptible_timeout(wq, condition, ret) \
do { \
wait_queue_t __wait; \
init_waitqueue_entry(&__wait, current); \
\
add_wait_queue(&wq, &__wait); \
for (;;) { \
set_current_state(TASK_INTERRUPTIBLE); \
if (condition) \
break; \
if (!signal_pending(current)) { \
ret = schedule_timeout(ret); \
if (!ret) \
break; \
continue; \
} \
ret = -ERESTARTSYS; \
break; \
} \
current->state = TASK_RUNNING; \
remove_wait_queue(&wq, &__wait); \
} while (0)
#define wait_event_interruptible_timeout(wq, condition, timeout) \
({ \
long __ret = timeout; \
if (!(condition)) \
__wait_event_interruptible_timeout(wq, condition, __ret); \
__ret; \
})
#endif
#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 24))
#define DEV_PRIV(dev) (dev->priv)
#else
#define DEV_PRIV(dev) netdev_priv(dev)
#endif
#if LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 20)
#define WL_ISR(i, d, p) wl_isr((i), (d))
#else
#define WL_ISR(i, d, p) wl_isr((i), (d), (p))
#endif
#if (LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 0))
#define netdev_priv(dev) dev->priv
#endif
#endif

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/*
* Trace log blocks sent over HBUS
*
* $Copyright Open Broadcom Corporation$
*
* $Id: logtrace.h 333856 2012-05-17 23:43:07Z $
*/
#ifndef _LOGTRACE_H
#define _LOGTRACE_H
#include <msgtrace.h>
extern void logtrace_start(void);
extern void logtrace_stop(void);
extern int logtrace_sent(void);
extern void logtrace_trigger(void);
extern void logtrace_init(void *hdl1, void *hdl2, msgtrace_func_send_t func_send);
extern bool logtrace_event_enabled(void);
#endif /* _LOGTRACE_H */

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external/cache/sources/wl/include/miniopt.h vendored Normal file
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/*
* Command line options parser.
*
* $Copyright Open Broadcom Corporation$
* $Id: miniopt.h 241182 2011-02-17 21:50:03Z gmo $
*/
#ifndef MINI_OPT_H
#define MINI_OPT_H
#ifdef __cplusplus
extern "C" {
#endif
/* ---- Include Files ---------------------------------------------------- */
/* ---- Constants and Types ---------------------------------------------- */
#define MINIOPT_MAXKEY 128 /* Max options */
typedef struct miniopt {
/* These are persistent after miniopt_init() */
const char* name; /* name for prompt in error strings */
const char* flags; /* option chars that take no args */
bool longflags; /* long options may be flags */
bool opt_end; /* at end of options (passed a "--") */
/* These are per-call to miniopt() */
int consumed; /* number of argv entries cosumed in
* the most recent call to miniopt()
*/
bool positional;
bool good_int; /* 'val' member is the result of a sucessful
* strtol conversion of the option value
*/
char opt;
char key[MINIOPT_MAXKEY];
char* valstr; /* positional param, or value for the option,
* or null if the option had
* no accompanying value
*/
uint uval; /* strtol translation of valstr */
int val; /* strtol translation of valstr */
} miniopt_t;
void miniopt_init(miniopt_t *t, const char* name, const char* flags, bool longflags);
int miniopt(miniopt_t *t, char **argv);
/* ---- Variable Externs ------------------------------------------------- */
/* ---- Function Prototypes ---------------------------------------------- */
#ifdef __cplusplus
}
#endif
#endif /* MINI_OPT_H */

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external/cache/sources/wl/include/msgtrace.h vendored Normal file
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/*
* Trace messages sent over HBUS
*
* $Copyright Open Broadcom Corporation$
*
* $Id: msgtrace.h 370068 2012-11-20 21:40:05Z $
*/
#ifndef _MSGTRACE_H
#define _MSGTRACE_H
#ifndef _TYPEDEFS_H_
#include <typedefs.h>
#endif
/* This marks the start of a packed structure section. */
#include <packed_section_start.h>
#define MSGTRACE_VERSION 1
/* Message trace header */
typedef BWL_PRE_PACKED_STRUCT struct msgtrace_hdr {
uint8 version;
uint8 trace_type;
#define MSGTRACE_HDR_TYPE_MSG 0
#define MSGTRACE_HDR_TYPE_LOG 1
uint16 len; /* Len of the trace */
uint32 seqnum; /* Sequence number of message. Useful if the messsage has been lost
* because of DMA error or a bus reset (ex: SDIO Func2)
*/
/* Msgtrace type only */
uint32 discarded_bytes; /* Number of discarded bytes because of trace overflow */
uint32 discarded_printf; /* Number of discarded printf because of trace overflow */
} BWL_POST_PACKED_STRUCT msgtrace_hdr_t;
#define MSGTRACE_HDRLEN sizeof(msgtrace_hdr_t)
/* The hbus driver generates traces when sending a trace message. This causes endless traces.
* This flag must be set to TRUE in any hbus traces. The flag is reset in the function msgtrace_put.
* This prevents endless traces but generates hasardous lost of traces only in bus device code.
* It is recommendat to set this flag in macro SD_TRACE but not in SD_ERROR for avoiding missing
* hbus error traces. hbus error trace should not generates endless traces.
*/
extern bool msgtrace_hbus_trace;
typedef void (*msgtrace_func_send_t)(void *hdl1, void *hdl2, uint8 *hdr,
uint16 hdrlen, uint8 *buf, uint16 buflen);
extern void msgtrace_start(void);
extern void msgtrace_stop(void);
extern int msgtrace_sent(void);
extern void msgtrace_put(char *buf, int count);
extern void msgtrace_init(void *hdl1, void *hdl2, msgtrace_func_send_t func_send);
extern bool msgtrace_event_enabled(void);
/* This marks the end of a packed structure section. */
#include <packed_section_end.h>
#endif /* _MSGTRACE_H */

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/*
* OS Abstraction Layer
*
* $Copyright Open Broadcom Corporation$
*
* $Id: osl.h 382794 2013-02-04 17:34:08Z $
*/
#ifndef _osl_h_
#define _osl_h_
typedef struct osl_info osl_t;
typedef struct osl_dmainfo osldma_t;
#define OSL_PKTTAG_SZ 32
typedef void (*pktfree_cb_fn_t)(void *ctx, void *pkt, unsigned int status);
typedef unsigned int (*osl_rreg_fn_t)(void *ctx, volatile void *reg, unsigned int size);
typedef void (*osl_wreg_fn_t)(void *ctx, volatile void *reg, unsigned int val, unsigned int size);
#include <linux_osl.h>
#ifndef PKTDBG_TRACE
#define PKTDBG_TRACE(osh, pkt, bit)
#endif
#define PKTCTFMAP(osh, p)
#define SET_REG(osh, r, mask, val) W_REG((osh), (r), ((R_REG((osh), r) & ~(mask)) | (val)))
#ifndef AND_REG
#define AND_REG(osh, r, v) W_REG(osh, (r), R_REG(osh, r) & (v))
#endif
#ifndef OR_REG
#define OR_REG(osh, r, v) W_REG(osh, (r), R_REG(osh, r) | (v))
#endif
#if !defined(OSL_SYSUPTIME)
#define OSL_SYSUPTIME() (0)
#define OSL_SYSUPTIME_SUPPORT FALSE
#else
#define OSL_SYSUPTIME_SUPPORT TRUE
#endif
#if !defined(PKTC) && !defined(PKTC_DONGLE)
#define PKTCGETATTR(s) (0)
#define PKTCSETATTR(skb, f, p, b)
#define PKTCCLRATTR(skb)
#define PKTCCNT(skb) (1)
#define PKTCLEN(skb) PKTLEN(NULL, skb)
#define PKTCGETFLAGS(skb) (0)
#define PKTCSETFLAGS(skb, f)
#define PKTCCLRFLAGS(skb)
#define PKTCFLAGS(skb) (0)
#define PKTCSETCNT(skb, c)
#define PKTCINCRCNT(skb)
#define PKTCADDCNT(skb, c)
#define PKTCSETLEN(skb, l)
#define PKTCADDLEN(skb, l)
#define PKTCSETFLAG(skb, fb)
#define PKTCCLRFLAG(skb, fb)
#define PKTCLINK(skb) NULL
#define PKTSETCLINK(skb, x)
#define FOREACH_CHAINED_PKT(skb, nskb) \
for ((nskb) = NULL; (skb) != NULL; (skb) = (nskb))
#define PKTCFREE PKTFREE
#endif
#ifndef HNDCTF
#define PKTSETCHAINED(osh, skb)
#define PKTCLRCHAINED(osh, skb)
#define PKTISCHAINED(skb) (FALSE)
#endif
#endif

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/*
* Declare directives for structure packing. No padding will be provided
* between the members of packed structures, and therefore, there is no
* guarantee that structure members will be aligned.
*
* Declaring packed structures is compiler specific. In order to handle all
* cases, packed structures should be delared as:
*
* #include <packed_section_start.h>
*
* typedef BWL_PRE_PACKED_STRUCT struct foobar_t {
* some_struct_members;
* } BWL_POST_PACKED_STRUCT foobar_t;
*
* #include <packed_section_end.h>
*
*
* $Copyright Open Broadcom Corporation$
* $Id: packed_section_end.h 397846 2013-04-21 22:11:16Z ishen $
*/
/* Error check - BWL_PACKED_SECTION is defined in packed_section_start.h
* and undefined in packed_section_end.h. If it is NOT defined at this
* point, then there is a missing include of packed_section_start.h.
*/
#ifdef BWL_PACKED_SECTION
#undef BWL_PACKED_SECTION
#else
#error "BWL_PACKED_SECTION is NOT defined!"
#endif
#if defined(_MSC_VER)
/* Disable compiler warning about pragma pack changing alignment. */
#pragma warning(disable:4103)
/* The Microsoft compiler uses pragmas for structure packing. Other
* compilers use structure attribute modifiers. Refer to
* BWL_PRE_PACKED_STRUCT and BWL_POST_PACKED_STRUCT defined in
* typedefs.h
*/
#if defined(BWL_DEFAULT_PACKING)
/* require default structure packing */
#pragma pack(pop)
#undef BWL_DEFAULT_PACKING
#else /* BWL_PACKED_SECTION */
#pragma pack()
#endif /* BWL_PACKED_SECTION */
#endif /* _MSC_VER */
#if defined(__GNUC__) && defined(EFI)
#pragma pack(pop)
#endif
/* Compiler-specific directives for structure packing are declared in
* packed_section_start.h. This marks the end of the structure packing section,
* so, undef them here.
*/
#undef BWL_PRE_PACKED_STRUCT
#undef BWL_POST_PACKED_STRUCT

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/*
* Declare directives for structure packing. No padding will be provided
* between the members of packed structures, and therefore, there is no
* guarantee that structure members will be aligned.
*
* Declaring packed structures is compiler specific. In order to handle all
* cases, packed structures should be delared as:
*
* #include <packed_section_start.h>
*
* typedef BWL_PRE_PACKED_STRUCT struct foobar_t {
* some_struct_members;
* } BWL_POST_PACKED_STRUCT foobar_t;
*
* #include <packed_section_end.h>
*
*
* $Copyright Open Broadcom Corporation$
* $Id: packed_section_start.h 397846 2013-04-21 22:11:16Z ishen $
*/
/* Error check - BWL_PACKED_SECTION is defined in packed_section_start.h
* and undefined in packed_section_end.h. If it is already defined at this
* point, then there is a missing include of packed_section_end.h.
*/
#ifdef BWL_PACKED_SECTION
#error "BWL_PACKED_SECTION is already defined!"
#else
#define BWL_PACKED_SECTION
#endif
#if defined(_MSC_VER)
/* Disable compiler warning about pragma pack changing alignment. */
#pragma warning(disable:4103)
/* The Microsoft compiler uses pragmas for structure packing. Other
* compilers use structure attribute modifiers. Refer to
* BWL_PRE_PACKED_STRUCT and BWL_POST_PACKED_STRUCT defined below.
*/
#if defined(BWL_DEFAULT_PACKING)
/* Default structure packing */
#pragma pack(push, 8)
#else /* BWL_PACKED_SECTION */
#pragma pack(1)
#endif /* BWL_PACKED_SECTION */
#endif /* _MSC_VER */
#if defined(__GNUC__) && defined(EFI)
#pragma pack(push)
#pragma pack(1)
#endif
/* Declare compiler-specific directives for structure packing. */
#if defined(_MSC_VER)
#define BWL_PRE_PACKED_STRUCT
#define BWL_POST_PACKED_STRUCT
#elif defined(__GNUC__) || defined(__lint)
#define BWL_PRE_PACKED_STRUCT
#define BWL_POST_PACKED_STRUCT __attribute__ ((packed))
#elif defined(__CC_ARM)
#define BWL_PRE_PACKED_STRUCT __packed
#define BWL_POST_PACKED_STRUCT
#else
#error "Unknown compiler!"
#endif

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/*
* pcicfg.h: PCI configuration constants and structures.
*
* $Copyright Open Broadcom Corporation$
*
* $Id: pcicfg.h 316716 2012-02-23 04:39:13Z $
*/
#ifndef _h_pcicfg_
#define _h_pcicfg_
#ifndef LINUX_POSTMOGRIFY_REMOVAL
#ifndef PCI_MAX_BUS
#define PCI_MAX_BUS 0x100
#endif
#ifndef PCI_MAX_DEVICES
#define PCI_MAX_DEVICES 0x20
#endif
#ifndef PCI_MAX_FUNCTION
#define PCI_MAX_FUNCTION 0x8
#endif
#ifndef PCI_INVALID_VENDORID
#define PCI_INVALID_VENDORID 0xffff
#endif
#ifndef PCI_INVALID_DEVICEID
#define PCI_INVALID_DEVICEID 0xffff
#endif
#define PCICFG_BUS_SHIFT 16
#define PCICFG_SLOT_SHIFT 11
#define PCICFG_FUN_SHIFT 8
#define PCICFG_OFF_SHIFT 0
#define PCICFG_BUS_MASK 0xff
#define PCICFG_SLOT_MASK 0x1f
#define PCICFG_FUN_MASK 7
#define PCICFG_OFF_MASK 0xff
#define PCI_CONFIG_ADDR(b, s, f, o) \
((((b) & PCICFG_BUS_MASK) << PCICFG_BUS_SHIFT) \
| (((s) & PCICFG_SLOT_MASK) << PCICFG_SLOT_SHIFT) \
| (((f) & PCICFG_FUN_MASK) << PCICFG_FUN_SHIFT) \
| (((o) & PCICFG_OFF_MASK) << PCICFG_OFF_SHIFT))
#define PCI_CONFIG_BUS(a) (((a) >> PCICFG_BUS_SHIFT) & PCICFG_BUS_MASK)
#define PCI_CONFIG_SLOT(a) (((a) >> PCICFG_SLOT_SHIFT) & PCICFG_SLOT_MASK)
#define PCI_CONFIG_FUN(a) (((a) >> PCICFG_FUN_SHIFT) & PCICFG_FUN_MASK)
#define PCI_CONFIG_OFF(a) (((a) >> PCICFG_OFF_SHIFT) & PCICFG_OFF_MASK)
#define PCIECFG_BUS_SHIFT 24
#define PCIECFG_SLOT_SHIFT 19
#define PCIECFG_FUN_SHIFT 16
#define PCIECFG_OFF_SHIFT 0
#define PCIECFG_BUS_MASK 0xff
#define PCIECFG_SLOT_MASK 0x1f
#define PCIECFG_FUN_MASK 7
#define PCIECFG_OFF_MASK 0xfff
#define PCIE_CONFIG_ADDR(b, s, f, o) \
((((b) & PCIECFG_BUS_MASK) << PCIECFG_BUS_SHIFT) \
| (((s) & PCIECFG_SLOT_MASK) << PCIECFG_SLOT_SHIFT) \
| (((f) & PCIECFG_FUN_MASK) << PCIECFG_FUN_SHIFT) \
| (((o) & PCIECFG_OFF_MASK) << PCIECFG_OFF_SHIFT))
#define PCIE_CONFIG_BUS(a) (((a) >> PCIECFG_BUS_SHIFT) & PCIECFG_BUS_MASK)
#define PCIE_CONFIG_SLOT(a) (((a) >> PCIECFG_SLOT_SHIFT) & PCIECFG_SLOT_MASK)
#define PCIE_CONFIG_FUN(a) (((a) >> PCIECFG_FUN_SHIFT) & PCIECFG_FUN_MASK)
#define PCIE_CONFIG_OFF(a) (((a) >> PCIECFG_OFF_SHIFT) & PCIECFG_OFF_MASK)
#define PCI_BAR_MAX 6
#define PCI_ROM_BAR 8
#define PCR_RSVDA_MAX 2
#define PCIBAR_FLAGS 0xf
#define PCIBAR_IO 0x1
#define PCIBAR_MEM1M 0x2
#define PCIBAR_MEM64 0x4
#define PCIBAR_PREFETCH 0x8
#define PCIBAR_MEM32_MASK 0xFFFFFF80
#define PCI_CAPPTR_PRESENT 0x0010
typedef struct _pci_config_regs {
uint16 vendor;
uint16 device;
uint16 command;
uint16 status;
uint8 rev_id;
uint8 prog_if;
uint8 sub_class;
uint8 base_class;
uint8 cache_line_size;
uint8 latency_timer;
uint8 header_type;
uint8 bist;
uint32 base[PCI_BAR_MAX];
uint32 cardbus_cis;
uint16 subsys_vendor;
uint16 subsys_id;
uint32 baserom;
uint32 rsvd_a[PCR_RSVDA_MAX];
uint8 int_line;
uint8 int_pin;
uint8 min_gnt;
uint8 max_lat;
uint8 dev_dep[192];
} pci_config_regs;
#define SZPCR (sizeof (pci_config_regs))
#define MINSZPCR 64
#endif
#define PCI_CFG_VID 0
#define PCI_CFG_DID 2
#define PCI_CFG_CMD 4
#define PCI_CFG_STAT 6
#define PCI_CFG_REV 8
#define PCI_CFG_PROGIF 9
#define PCI_CFG_SUBCL 0xa
#define PCI_CFG_BASECL 0xb
#define PCI_CFG_CLSZ 0xc
#define PCI_CFG_LATTIM 0xd
#define PCI_CFG_HDR 0xe
#define PCI_CFG_BIST 0xf
#define PCI_CFG_BAR0 0x10
#define PCI_CFG_BAR1 0x14
#define PCI_CFG_BAR2 0x18
#define PCI_CFG_BAR3 0x1c
#define PCI_CFG_BAR4 0x20
#define PCI_CFG_BAR5 0x24
#define PCI_CFG_CIS 0x28
#define PCI_CFG_SVID 0x2c
#define PCI_CFG_SSID 0x2e
#define PCI_CFG_ROMBAR 0x30
#define PCI_CFG_CAPPTR 0x34
#define PCI_CFG_INT 0x3c
#define PCI_CFG_PIN 0x3d
#define PCI_CFG_MINGNT 0x3e
#define PCI_CFG_MAXLAT 0x3f
#define PCI_CFG_DEVCTRL 0xd8
#ifndef LINUX_POSTMOGRIFY_REMOVAL
typedef enum {
PCI_CLASS_OLD = 0,
PCI_CLASS_DASDI,
PCI_CLASS_NET,
PCI_CLASS_DISPLAY,
PCI_CLASS_MMEDIA,
PCI_CLASS_MEMORY,
PCI_CLASS_BRIDGE,
PCI_CLASS_COMM,
PCI_CLASS_BASE,
PCI_CLASS_INPUT,
PCI_CLASS_DOCK,
PCI_CLASS_CPU,
PCI_CLASS_SERIAL,
PCI_CLASS_INTELLIGENT = 0xe,
PCI_CLASS_SATELLITE,
PCI_CLASS_CRYPT,
PCI_CLASS_DSP,
PCI_CLASS_XOR = 0xfe
} pci_classes;
typedef enum {
PCI_DASDI_SCSI,
PCI_DASDI_IDE,
PCI_DASDI_FLOPPY,
PCI_DASDI_IPI,
PCI_DASDI_RAID,
PCI_DASDI_OTHER = 0x80
} pci_dasdi_subclasses;
typedef enum {
PCI_NET_ETHER,
PCI_NET_TOKEN,
PCI_NET_FDDI,
PCI_NET_ATM,
PCI_NET_OTHER = 0x80
} pci_net_subclasses;
typedef enum {
PCI_DISPLAY_VGA,
PCI_DISPLAY_XGA,
PCI_DISPLAY_3D,
PCI_DISPLAY_OTHER = 0x80
} pci_display_subclasses;
typedef enum {
PCI_MMEDIA_VIDEO,
PCI_MMEDIA_AUDIO,
PCI_MMEDIA_PHONE,
PCI_MEDIA_OTHER = 0x80
} pci_mmedia_subclasses;
typedef enum {
PCI_MEMORY_RAM,
PCI_MEMORY_FLASH,
PCI_MEMORY_OTHER = 0x80
} pci_memory_subclasses;
typedef enum {
PCI_BRIDGE_HOST,
PCI_BRIDGE_ISA,
PCI_BRIDGE_EISA,
PCI_BRIDGE_MC,
PCI_BRIDGE_PCI,
PCI_BRIDGE_PCMCIA,
PCI_BRIDGE_NUBUS,
PCI_BRIDGE_CARDBUS,
PCI_BRIDGE_RACEWAY,
PCI_BRIDGE_OTHER = 0x80
} pci_bridge_subclasses;
typedef enum {
PCI_COMM_UART,
PCI_COMM_PARALLEL,
PCI_COMM_MULTIUART,
PCI_COMM_MODEM,
PCI_COMM_OTHER = 0x80
} pci_comm_subclasses;
typedef enum {
PCI_BASE_PIC,
PCI_BASE_DMA,
PCI_BASE_TIMER,
PCI_BASE_RTC,
PCI_BASE_PCI_HOTPLUG,
PCI_BASE_OTHER = 0x80
} pci_base_subclasses;
typedef enum {
PCI_INPUT_KBD,
PCI_INPUT_PEN,
PCI_INPUT_MOUSE,
PCI_INPUT_SCANNER,
PCI_INPUT_GAMEPORT,
PCI_INPUT_OTHER = 0x80
} pci_input_subclasses;
typedef enum {
PCI_DOCK_GENERIC,
PCI_DOCK_OTHER = 0x80
} pci_dock_subclasses;
typedef enum {
PCI_CPU_386,
PCI_CPU_486,
PCI_CPU_PENTIUM,
PCI_CPU_ALPHA = 0x10,
PCI_CPU_POWERPC = 0x20,
PCI_CPU_MIPS = 0x30,
PCI_CPU_COPROC = 0x40,
PCI_CPU_OTHER = 0x80
} pci_cpu_subclasses;
typedef enum {
PCI_SERIAL_IEEE1394,
PCI_SERIAL_ACCESS,
PCI_SERIAL_SSA,
PCI_SERIAL_USB,
PCI_SERIAL_FIBER,
PCI_SERIAL_SMBUS,
PCI_SERIAL_OTHER = 0x80
} pci_serial_subclasses;
typedef enum {
PCI_INTELLIGENT_I2O
} pci_intelligent_subclasses;
typedef enum {
PCI_SATELLITE_TV,
PCI_SATELLITE_AUDIO,
PCI_SATELLITE_VOICE,
PCI_SATELLITE_DATA,
PCI_SATELLITE_OTHER = 0x80
} pci_satellite_subclasses;
typedef enum {
PCI_CRYPT_NETWORK,
PCI_CRYPT_ENTERTAINMENT,
PCI_CRYPT_OTHER = 0x80
} pci_crypt_subclasses;
typedef enum {
PCI_DSP_DPIO,
PCI_DSP_OTHER = 0x80
} pci_dsp_subclasses;
typedef enum {
PCI_XOR_QDMA,
PCI_XOR_OTHER = 0x80
} pci_xor_subclasses;
#define PCI_HEADER_MULTI 0x80
#define PCI_HEADER_MASK 0x7f
typedef enum {
PCI_HEADER_NORMAL,
PCI_HEADER_BRIDGE,
PCI_HEADER_CARDBUS
} pci_header_types;
#define PPB_RSVDA_MAX 2
#define PPB_RSVDD_MAX 8
typedef struct _ppb_config_regs {
uint16 vendor;
uint16 device;
uint16 command;
uint16 status;
uint8 rev_id;
uint8 prog_if;
uint8 sub_class;
uint8 base_class;
uint8 cache_line_size;
uint8 latency_timer;
uint8 header_type;
uint8 bist;
uint32 rsvd_a[PPB_RSVDA_MAX];
uint8 prim_bus;
uint8 sec_bus;
uint8 sub_bus;
uint8 sec_lat;
uint8 io_base;
uint8 io_lim;
uint16 sec_status;
uint16 mem_base;
uint16 mem_lim;
uint16 pf_mem_base;
uint16 pf_mem_lim;
uint32 pf_mem_base_hi;
uint32 pf_mem_lim_hi;
uint16 io_base_hi;
uint16 io_lim_hi;
uint16 subsys_vendor;
uint16 subsys_id;
uint32 rsvd_b;
uint8 rsvd_c;
uint8 int_pin;
uint16 bridge_ctrl;
uint8 chip_ctrl;
uint8 diag_ctrl;
uint16 arb_ctrl;
uint32 rsvd_d[PPB_RSVDD_MAX];
uint8 dev_dep[192];
} ppb_config_regs;
#define PCI_CAP_POWERMGMTCAP_ID 0x01
#define PCI_CAP_MSICAP_ID 0x05
#define PCI_CAP_VENDSPEC_ID 0x09
#define PCI_CAP_PCIECAP_ID 0x10
typedef struct _pciconfig_cap_msi {
uint8 capID;
uint8 nextptr;
uint16 msgctrl;
uint32 msgaddr;
} pciconfig_cap_msi;
typedef struct _pciconfig_cap_pwrmgmt {
uint8 capID;
uint8 nextptr;
uint16 pme_cap;
uint16 pme_sts_ctrl;
uint8 pme_bridge_ext;
uint8 data;
} pciconfig_cap_pwrmgmt;
#define PME_CAP_PM_STATES (0x1f << 27)
#define PME_CSR_OFFSET 0x4
#define PME_CSR_PME_EN (1 << 8)
#define PME_CSR_PME_STAT (1 << 15)
typedef struct _pciconfig_cap_pcie {
uint8 capID;
uint8 nextptr;
uint16 pcie_cap;
uint32 dev_cap;
uint16 dev_ctrl;
uint16 dev_status;
uint32 link_cap;
uint16 link_ctrl;
uint16 link_status;
uint32 slot_cap;
uint16 slot_ctrl;
uint16 slot_status;
uint16 root_ctrl;
uint16 root_cap;
uint32 root_status;
} pciconfig_cap_pcie;
#define PCIE_EXTCFG_OFFSET 0x100
#define PCIE_ADVERRREP_CAPID 0x0001
#define PCIE_VC_CAPID 0x0002
#define PCIE_DEVSNUM_CAPID 0x0003
#define PCIE_PWRBUDGET_CAPID 0x0004
#define PCIE_ADV_CORR_ERR_MASK 0x114
#define CORR_ERR_RE (1 << 0)
#define CORR_ERR_BT (1 << 6)
#define CORR_ERR_BD (1 << 7)
#define CORR_ERR_RR (1 << 8)
#define CORR_ERR_RT (1 << 12)
#define ALL_CORR_ERRORS (CORR_ERR_RE | CORR_ERR_BT | CORR_ERR_BD | \
CORR_ERR_RR | CORR_ERR_RT)
#define PCIE_RC_CORR_SERR_EN 0x0001
#define PCIE_RC_NONFATAL_SERR_EN 0x0002
#define PCIE_RC_FATAL_SERR_EN 0x0004
#define PCIE_RC_PME_INT_EN 0x0008
#define PCIE_RC_CRS_EN 0x0010
#define PCIE_RC_CRS_VISIBILITY 0x0001
typedef struct _pcie_enhanced_caphdr {
uint16 capID;
uint16 cap_ver : 4;
uint16 next_ptr : 12;
} pcie_enhanced_caphdr;
#define cap_list rsvd_a[0]
#define bar0_window dev_dep[0x80 - 0x40]
#define bar1_window dev_dep[0x84 - 0x40]
#define sprom_control dev_dep[0x88 - 0x40]
#endif
#define PCI_BAR0_WIN 0x80
#define PCI_BAR1_WIN 0x84
#define PCI_SPROM_CONTROL 0x88
#define PCI_BAR1_CONTROL 0x8c
#define PCI_INT_STATUS 0x90
#define PCI_INT_MASK 0x94
#define PCI_TO_SB_MB 0x98
#define PCI_BACKPLANE_ADDR 0xa0
#define PCI_BACKPLANE_DATA 0xa4
#define PCI_CLK_CTL_ST 0xa8
#define PCI_BAR0_WIN2 0xac
#define PCI_GPIO_IN 0xb0
#define PCI_GPIO_OUT 0xb4
#define PCI_GPIO_OUTEN 0xb8
#define PCI_BAR0_SHADOW_OFFSET (2 * 1024)
#define PCI_BAR0_SPROM_OFFSET (4 * 1024)
#define PCI_BAR0_PCIREGS_OFFSET (6 * 1024)
#define PCI_BAR0_PCISBR_OFFSET (4 * 1024)
#define PCIE2_BAR0_WIN2 0x70
#define PCIE2_BAR0_CORE2_WIN 0x74
#define PCIE2_BAR0_CORE2_WIN2 0x78
#define PCI_BAR0_WINSZ (16 * 1024)
#define PCI_16KB0_PCIREGS_OFFSET (8 * 1024)
#define PCI_16KB0_CCREGS_OFFSET (12 * 1024)
#define PCI_16KBB0_WINSZ (16 * 1024)
#ifndef LINUX_POSTMOGRIFY_REMOVAL
#define PCI_16KB0_WIN2_OFFSET (4 * 1024)
#define PCI_SBIM_STATUS_SERR 0x4
#define PCI_SBIM_SHIFT 8
#define PCI_SBIM_MASK 0xff00
#define PCI_SBIM_MASK_SERR 0x4
#ifndef LINUX_POSTMOGRIFY_REMOVAL
#define SPROM_SZ_MSK 0x02
#define SPROM_LOCKED 0x08
#define SPROM_BLANK 0x04
#define SPROM_WRITEEN 0x10
#define SPROM_BOOTROM_WE 0x20
#define SPROM_BACKPLANE_EN 0x40
#define SPROM_OTPIN_USE 0x80
#endif
#define PCI_CMD_IO 0x00000001
#define PCI_CMD_MEMORY 0x00000002
#define PCI_CMD_MASTER 0x00000004
#define PCI_CMD_SPECIAL 0x00000008
#define PCI_CMD_INVALIDATE 0x00000010
#define PCI_CMD_VGA_PAL 0x00000040
#define PCI_STAT_TA 0x08000000
#endif
#define PCI_CONFIG_SPACE_SIZE 256
#endif

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/*
* BT-AMP (BlueTooth Alternate Mac and Phy) 802.11 PAL (Protocol Adaptation Layer)
*
* $Copyright Open Broadcom Corporation$
*
* $Id: 802.11_bta.h 294267 2011-11-04 23:41:52Z $
*/
#ifndef _802_11_BTA_H_
#define _802_11_BTA_H_
#define BT_SIG_SNAP_MPROT "\xAA\xAA\x03\x00\x19\x58"
/* BT-AMP 802.11 PAL Protocols */
#define BTA_PROT_L2CAP 1
#define BTA_PROT_ACTIVITY_REPORT 2
#define BTA_PROT_SECURITY 3
#define BTA_PROT_LINK_SUPERVISION_REQUEST 4
#define BTA_PROT_LINK_SUPERVISION_REPLY 5
/* BT-AMP 802.11 PAL AMP_ASSOC Type IDs */
#define BTA_TYPE_ID_MAC_ADDRESS 1
#define BTA_TYPE_ID_PREFERRED_CHANNELS 2
#define BTA_TYPE_ID_CONNECTED_CHANNELS 3
#define BTA_TYPE_ID_CAPABILITIES 4
#define BTA_TYPE_ID_VERSION 5
#endif /* _802_11_bta_h_ */

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/*
* 802.11e protocol header file
*
* $Copyright Open Broadcom Corporation$
*
* $Id: 802.11e.h 365823 2012-10-31 04:24:30Z jerryko $
*/
#ifndef _802_11e_H_
#define _802_11e_H_
#ifndef _TYPEDEFS_H_
#include <typedefs.h>
#endif
/* This marks the start of a packed structure section. */
#include <packed_section_start.h>
#ifdef BCMDBG
extern const char * const aci_names[];
#endif /* BCMDBG */
/* WME Traffic Specification (TSPEC) element */
#define WME_TSPEC_HDR_LEN 2 /* WME TSPEC header length */
#define WME_TSPEC_BODY_OFF 2 /* WME TSPEC body offset */
#define WME_CATEGORY_CODE_OFFSET 0 /* WME Category code offset */
#define WME_ACTION_CODE_OFFSET 1 /* WME Action code offset */
#define WME_TOKEN_CODE_OFFSET 2 /* WME Token code offset */
#define WME_STATUS_CODE_OFFSET 3 /* WME Status code offset */
BWL_PRE_PACKED_STRUCT struct tsinfo {
uint8 octets[3];
} BWL_POST_PACKED_STRUCT;
typedef struct tsinfo tsinfo_t;
/* 802.11e TSPEC IE */
typedef BWL_PRE_PACKED_STRUCT struct tspec {
uint8 oui[DOT11_OUI_LEN]; /* WME_OUI */
uint8 type; /* WME_TYPE */
uint8 subtype; /* WME_SUBTYPE_TSPEC */
uint8 version; /* WME_VERSION */
tsinfo_t tsinfo; /* TS Info bit field */
uint16 nom_msdu_size; /* (Nominal or fixed) MSDU Size (bytes) */
uint16 max_msdu_size; /* Maximum MSDU Size (bytes) */
uint32 min_srv_interval; /* Minimum Service Interval (us) */
uint32 max_srv_interval; /* Maximum Service Interval (us) */
uint32 inactivity_interval; /* Inactivity Interval (us) */
uint32 suspension_interval; /* Suspension Interval (us) */
uint32 srv_start_time; /* Service Start Time (us) */
uint32 min_data_rate; /* Minimum Data Rate (bps) */
uint32 mean_data_rate; /* Mean Data Rate (bps) */
uint32 peak_data_rate; /* Peak Data Rate (bps) */
uint32 max_burst_size; /* Maximum Burst Size (bytes) */
uint32 delay_bound; /* Delay Bound (us) */
uint32 min_phy_rate; /* Minimum PHY Rate (bps) */
uint16 surplus_bw; /* Surplus Bandwidth Allowance (range 1.0-8.0) */
uint16 medium_time; /* Medium Time (32 us/s periods) */
} BWL_POST_PACKED_STRUCT tspec_t;
#define WME_TSPEC_LEN (sizeof(tspec_t)) /* not including 2-bytes of header */
/* ts_info */
/* 802.1D priority is duplicated - bits 13-11 AND bits 3-1 */
#define TS_INFO_TID_SHIFT 1 /* TS info. TID shift */
#define TS_INFO_TID_MASK (0xf << TS_INFO_TID_SHIFT) /* TS info. TID mask */
#define TS_INFO_CONTENTION_SHIFT 7 /* TS info. contention shift */
#define TS_INFO_CONTENTION_MASK (0x1 << TS_INFO_CONTENTION_SHIFT) /* TS info. contention mask */
#define TS_INFO_DIRECTION_SHIFT 5 /* TS info. direction shift */
#define TS_INFO_DIRECTION_MASK (0x3 << TS_INFO_DIRECTION_SHIFT) /* TS info. direction mask */
#define TS_INFO_PSB_SHIFT 2 /* TS info. PSB bit Shift */
#define TS_INFO_PSB_MASK (1 << TS_INFO_PSB_SHIFT) /* TS info. PSB mask */
#define TS_INFO_UPLINK (0 << TS_INFO_DIRECTION_SHIFT) /* TS info. uplink */
#define TS_INFO_DOWNLINK (1 << TS_INFO_DIRECTION_SHIFT) /* TS info. downlink */
#define TS_INFO_BIDIRECTIONAL (3 << TS_INFO_DIRECTION_SHIFT) /* TS info. bidirectional */
#define TS_INFO_USER_PRIO_SHIFT 3 /* TS info. user priority shift */
/* TS info. user priority mask */
#define TS_INFO_USER_PRIO_MASK (0x7 << TS_INFO_USER_PRIO_SHIFT)
/* Macro to get/set bit(s) field in TSINFO */
#define WLC_CAC_GET_TID(pt) ((((pt).octets[0]) & TS_INFO_TID_MASK) >> TS_INFO_TID_SHIFT)
#define WLC_CAC_GET_DIR(pt) ((((pt).octets[0]) & \
TS_INFO_DIRECTION_MASK) >> TS_INFO_DIRECTION_SHIFT)
#define WLC_CAC_GET_PSB(pt) ((((pt).octets[1]) & TS_INFO_PSB_MASK) >> TS_INFO_PSB_SHIFT)
#define WLC_CAC_GET_USER_PRIO(pt) ((((pt).octets[1]) & \
TS_INFO_USER_PRIO_MASK) >> TS_INFO_USER_PRIO_SHIFT)
#define WLC_CAC_SET_TID(pt, id) ((((pt).octets[0]) & (~TS_INFO_TID_MASK)) | \
((id) << TS_INFO_TID_SHIFT))
#define WLC_CAC_SET_USER_PRIO(pt, prio) ((((pt).octets[0]) & (~TS_INFO_USER_PRIO_MASK)) | \
((prio) << TS_INFO_USER_PRIO_SHIFT))
/* 802.11e QBSS Load IE */
#define QBSS_LOAD_IE_LEN 5 /* QBSS Load IE length */
#define QBSS_LOAD_AAC_OFF 3 /* AAC offset in IE */
#define CAC_ADDTS_RESP_TIMEOUT 1000 /* default ADDTS response timeout in ms */
/* DEFVAL dot11ADDTSResponseTimeout = 1s */
/* 802.11e ADDTS status code */
#define DOT11E_STATUS_ADMISSION_ACCEPTED 0 /* TSPEC Admission accepted status */
#define DOT11E_STATUS_ADDTS_INVALID_PARAM 1 /* TSPEC invalid parameter status */
#define DOT11E_STATUS_ADDTS_REFUSED_NSBW 3 /* ADDTS refused (non-sufficient BW) */
#define DOT11E_STATUS_ADDTS_REFUSED_AWHILE 47 /* ADDTS refused but could retry later */
#ifdef BCMCCX
#define CCX_STATUS_ASSOC_DENIED_UNKNOWN 0xc8 /* unspecified QoS related failure */
#define CCX_STATUS_ASSOC_DENIED_AP_POLICY 0xc9 /* TSPEC refused due to AP policy */
#define CCX_STATUS_ASSOC_DENIED_NO_BW 0xca /* Assoc denied due to AP insufficient BW */
#define CCX_STATUS_ASSOC_DENIED_BAD_PARAM 0xcb /* one or more TSPEC with invalid parameter */
#endif /* BCMCCX */
/* 802.11e DELTS status code */
#define DOT11E_STATUS_QSTA_LEAVE_QBSS 36 /* STA leave QBSS */
#define DOT11E_STATUS_END_TS 37 /* END TS */
#define DOT11E_STATUS_UNKNOWN_TS 38 /* UNKNOWN TS */
#define DOT11E_STATUS_QSTA_REQ_TIMEOUT 39 /* STA ADDTS request timeout */
/* This marks the end of a packed structure section. */
#include <packed_section_end.h>
#endif /* _802_11e_CAC_H_ */

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/*
* $Copyright Open Broadcom Corporation$
*
* Fundamental types and constants relating to 802.1D
*
* $Id: 802.1d.h 241182 2011-02-17 21:50:03Z gmo $
*/
#ifndef _802_1_D_
#define _802_1_D_
/* 802.1D priority defines */
#define PRIO_8021D_NONE 2 /* None = - */
#define PRIO_8021D_BK 1 /* BK - Background */
#define PRIO_8021D_BE 0 /* BE - Best-effort */
#define PRIO_8021D_EE 3 /* EE - Excellent-effort */
#define PRIO_8021D_CL 4 /* CL - Controlled Load */
#define PRIO_8021D_VI 5 /* Vi - Video */
#define PRIO_8021D_VO 6 /* Vo - Voice */
#define PRIO_8021D_NC 7 /* NC - Network Control */
#define MAXPRIO 7 /* 0-7 */
#define NUMPRIO (MAXPRIO + 1)
#define ALLPRIO -1 /* All prioirty */
/* Converts prio to precedence since the numerical value of
* PRIO_8021D_BE and PRIO_8021D_NONE are swapped.
*/
#define PRIO2PREC(prio) \
(((prio) == PRIO_8021D_NONE || (prio) == PRIO_8021D_BE) ? ((prio^2)) : (prio))
#endif /* _802_1_D__ */

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/*
* Broadcom Ethernettype protocol definitions
*
* $Copyright Open Broadcom Corporation$
*
* $Id: bcmeth.h 294352 2011-11-06 19:23:00Z hharte $
*/
/*
* Broadcom Ethernet protocol defines
*/
#ifndef _BCMETH_H_
#define _BCMETH_H_
#ifndef _TYPEDEFS_H_
#include <typedefs.h>
#endif
/* This marks the start of a packed structure section. */
#include <packed_section_start.h>
/* ETHER_TYPE_BRCM is defined in ethernet.h */
/*
* Following the 2byte BRCM ether_type is a 16bit BRCM subtype field
* in one of two formats: (only subtypes 32768-65535 are in use now)
*
* subtypes 0-32767:
* 8 bit subtype (0-127)
* 8 bit length in bytes (0-255)
*
* subtypes 32768-65535:
* 16 bit big-endian subtype
* 16 bit big-endian length in bytes (0-65535)
*
* length is the number of additional bytes beyond the 4 or 6 byte header
*
* Reserved values:
* 0 reserved
* 5-15 reserved for iLine protocol assignments
* 17-126 reserved, assignable
* 127 reserved
* 32768 reserved
* 32769-65534 reserved, assignable
* 65535 reserved
*/
/*
* While adding the subtypes and their specific processing code make sure
* bcmeth_bcm_hdr_t is the first data structure in the user specific data structure definition
*/
#define BCMILCP_SUBTYPE_RATE 1
#define BCMILCP_SUBTYPE_LINK 2
#define BCMILCP_SUBTYPE_CSA 3
#define BCMILCP_SUBTYPE_LARQ 4
#define BCMILCP_SUBTYPE_VENDOR 5
#define BCMILCP_SUBTYPE_FLH 17
#define BCMILCP_SUBTYPE_VENDOR_LONG 32769
#define BCMILCP_SUBTYPE_CERT 32770
#define BCMILCP_SUBTYPE_SES 32771
#define BCMILCP_BCM_SUBTYPE_RESERVED 0
#define BCMILCP_BCM_SUBTYPE_EVENT 1
#define BCMILCP_BCM_SUBTYPE_SES 2
/*
* The EAPOL type is not used anymore. Instead EAPOL messages are now embedded
* within BCMILCP_BCM_SUBTYPE_EVENT type messages
*/
/* #define BCMILCP_BCM_SUBTYPE_EAPOL 3 */
#define BCMILCP_BCM_SUBTYPE_DPT 4
#define BCMILCP_BCM_SUBTYPEHDR_MINLENGTH 8
#define BCMILCP_BCM_SUBTYPEHDR_VERSION 0
/* These fields are stored in network order */
typedef BWL_PRE_PACKED_STRUCT struct bcmeth_hdr
{
uint16 subtype; /* Vendor specific..32769 */
uint16 length;
uint8 version; /* Version is 0 */
uint8 oui[3]; /* Broadcom OUI */
/* user specific Data */
uint16 usr_subtype;
} BWL_POST_PACKED_STRUCT bcmeth_hdr_t;
/* This marks the end of a packed structure section. */
#include <packed_section_end.h>
#endif /* _BCMETH_H_ */

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/*
* Broadcom Event protocol definitions
*
* $Copyright Open Broadcom Corporation$
*
* Dependencies: proto/bcmeth.h
*
* $Id: bcmevent.h 410874 2013-07-03 18:07:25Z ryeh $
*
*/
/*
* Broadcom Ethernet Events protocol defines
*
*/
#ifndef _BCMEVENT_H_
#define _BCMEVENT_H_
#ifndef _TYPEDEFS_H_
#include <typedefs.h>
#endif
/* #include <ethernet.h> -- TODO: req., excluded to overwhelming coupling (break up ethernet.h) */
#include <proto/bcmeth.h>
/* This marks the start of a packed structure section. */
#include <packed_section_start.h>
#define BCM_EVENT_MSG_VERSION 2 /* wl_event_msg_t struct version */
#define BCM_MSG_IFNAME_MAX 16 /* max length of interface name */
/* flags */
#define WLC_EVENT_MSG_LINK 0x01 /* link is up */
#define WLC_EVENT_MSG_FLUSHTXQ 0x02 /* flush tx queue on MIC error */
#define WLC_EVENT_MSG_GROUP 0x04 /* group MIC error */
#define WLC_EVENT_MSG_UNKBSS 0x08 /* unknown source bsscfg */
#define WLC_EVENT_MSG_UNKIF 0x10 /* unknown source OS i/f */
/* these fields are stored in network order */
/* version 1 */
typedef BWL_PRE_PACKED_STRUCT struct
{
uint16 version;
uint16 flags; /* see flags below */
uint32 event_type; /* Message (see below) */
uint32 status; /* Status code (see below) */
uint32 reason; /* Reason code (if applicable) */
uint32 auth_type; /* WLC_E_AUTH */
uint32 datalen; /* data buf */
struct ether_addr addr; /* Station address (if applicable) */
char ifname[BCM_MSG_IFNAME_MAX]; /* name of the packet incoming interface */
} BWL_POST_PACKED_STRUCT wl_event_msg_v1_t;
/* the current version */
typedef BWL_PRE_PACKED_STRUCT struct
{
uint16 version;
uint16 flags; /* see flags below */
uint32 event_type; /* Message (see below) */
uint32 status; /* Status code (see below) */
uint32 reason; /* Reason code (if applicable) */
uint32 auth_type; /* WLC_E_AUTH */
uint32 datalen; /* data buf */
struct ether_addr addr; /* Station address (if applicable) */
char ifname[BCM_MSG_IFNAME_MAX]; /* name of the packet incoming interface */
uint8 ifidx; /* destination OS i/f index */
uint8 bsscfgidx; /* source bsscfg index */
} BWL_POST_PACKED_STRUCT wl_event_msg_t;
/* used by driver msgs */
typedef BWL_PRE_PACKED_STRUCT struct bcm_event {
struct ether_header eth;
bcmeth_hdr_t bcm_hdr;
wl_event_msg_t event;
/* data portion follows */
} BWL_POST_PACKED_STRUCT bcm_event_t;
#define BCM_MSG_LEN (sizeof(bcm_event_t) - sizeof(bcmeth_hdr_t) - sizeof(struct ether_header))
/* Event messages */
#define WLC_E_SET_SSID 0 /* indicates status of set SSID */
#define WLC_E_JOIN 1 /* differentiates join IBSS from found (WLC_E_START) IBSS */
#define WLC_E_START 2 /* STA founded an IBSS or AP started a BSS */
#define WLC_E_AUTH 3 /* 802.11 AUTH request */
#define WLC_E_AUTH_IND 4 /* 802.11 AUTH indication */
#define WLC_E_DEAUTH 5 /* 802.11 DEAUTH request */
#define WLC_E_DEAUTH_IND 6 /* 802.11 DEAUTH indication */
#define WLC_E_ASSOC 7 /* 802.11 ASSOC request */
#define WLC_E_ASSOC_IND 8 /* 802.11 ASSOC indication */
#define WLC_E_REASSOC 9 /* 802.11 REASSOC request */
#define WLC_E_REASSOC_IND 10 /* 802.11 REASSOC indication */
#define WLC_E_DISASSOC 11 /* 802.11 DISASSOC request */
#define WLC_E_DISASSOC_IND 12 /* 802.11 DISASSOC indication */
#define WLC_E_QUIET_START 13 /* 802.11h Quiet period started */
#define WLC_E_QUIET_END 14 /* 802.11h Quiet period ended */
#define WLC_E_BEACON_RX 15 /* BEACONS received/lost indication */
#define WLC_E_LINK 16 /* generic link indication */
#define WLC_E_MIC_ERROR 17 /* TKIP MIC error occurred */
#define WLC_E_NDIS_LINK 18 /* NDIS style link indication */
#define WLC_E_ROAM 19 /* roam attempt occurred: indicate status & reason */
#define WLC_E_TXFAIL 20 /* change in dot11FailedCount (txfail) */
#define WLC_E_PMKID_CACHE 21 /* WPA2 pmkid cache indication */
#define WLC_E_RETROGRADE_TSF 22 /* current AP's TSF value went backward */
#define WLC_E_PRUNE 23 /* AP was pruned from join list for reason */
#define WLC_E_AUTOAUTH 24 /* report AutoAuth table entry match for join attempt */
#define WLC_E_EAPOL_MSG 25 /* Event encapsulating an EAPOL message */
#define WLC_E_SCAN_COMPLETE 26 /* Scan results are ready or scan was aborted */
#define WLC_E_ADDTS_IND 27 /* indicate to host addts fail/success */
#define WLC_E_DELTS_IND 28 /* indicate to host delts fail/success */
#define WLC_E_BCNSENT_IND 29 /* indicate to host of beacon transmit */
#define WLC_E_BCNRX_MSG 30 /* Send the received beacon up to the host */
#define WLC_E_BCNLOST_MSG 31 /* indicate to host loss of beacon */
#define WLC_E_ROAM_PREP 32 /* before attempting to roam */
#define WLC_E_PFN_NET_FOUND 33 /* PFN network found event */
#define WLC_E_PFN_NET_LOST 34 /* PFN network lost event */
#define WLC_E_RESET_COMPLETE 35
#define WLC_E_JOIN_START 36
#define WLC_E_ROAM_START 37
#define WLC_E_ASSOC_START 38
#define WLC_E_IBSS_ASSOC 39
#define WLC_E_RADIO 40
#define WLC_E_PSM_WATCHDOG 41 /* PSM microcode watchdog fired */
#if defined(BCMCCX) && defined(CCX_SDK)
#define WLC_E_CCX_ASSOC_START 42 /* CCX association start */
#define WLC_E_CCX_ASSOC_ABORT 43 /* CCX association abort */
#endif /* BCMCCX && CCX_SDK */
#define WLC_E_PROBREQ_MSG 44 /* probe request received */
#define WLC_E_SCAN_CONFIRM_IND 45
#define WLC_E_PSK_SUP 46 /* WPA Handshake fail */
#define WLC_E_COUNTRY_CODE_CHANGED 47
#define WLC_E_EXCEEDED_MEDIUM_TIME 48 /* WMMAC excedded medium time */
#define WLC_E_ICV_ERROR 49 /* WEP ICV error occurred */
#define WLC_E_UNICAST_DECODE_ERROR 50 /* Unsupported unicast encrypted frame */
#define WLC_E_MULTICAST_DECODE_ERROR 51 /* Unsupported multicast encrypted frame */
#define WLC_E_TRACE 52
#ifdef WLBTAMP
#define WLC_E_BTA_HCI_EVENT 53 /* BT-AMP HCI event */
#endif
#define WLC_E_IF 54 /* I/F change (for dongle host notification) */
#define WLC_E_P2P_DISC_LISTEN_COMPLETE 55 /* listen state expires */
#define WLC_E_RSSI 56 /* indicate RSSI change based on configured levels */
#define WLC_E_PFN_SCAN_COMPLETE 57 /* PFN completed scan of network list */
#define WLC_E_EXTLOG_MSG 58
#define WLC_E_ACTION_FRAME 59 /* Action frame Rx */
#define WLC_E_ACTION_FRAME_COMPLETE 60 /* Action frame Tx complete */
#define WLC_E_PRE_ASSOC_IND 61 /* assoc request received */
#define WLC_E_PRE_REASSOC_IND 62 /* re-assoc request received */
#define WLC_E_CHANNEL_ADOPTED 63 /* channel adopted (xxx: obsoleted) */
#define WLC_E_AP_STARTED 64 /* AP started */
#define WLC_E_DFS_AP_STOP 65 /* AP stopped due to DFS */
#define WLC_E_DFS_AP_RESUME 66 /* AP resumed due to DFS */
#define WLC_E_WAI_STA_EVENT 67 /* WAI stations event */
#define WLC_E_WAI_MSG 68 /* event encapsulating an WAI message */
#define WLC_E_ESCAN_RESULT 69 /* escan result event */
#define WLC_E_ACTION_FRAME_OFF_CHAN_COMPLETE 70 /* action frame off channel complete */
#define WLC_E_PROBRESP_MSG 71 /* probe response received */
#define WLC_E_P2P_PROBREQ_MSG 72 /* P2P Probe request received */
#define WLC_E_DCS_REQUEST 73
/* XXX: will enable this after proptxstatus code is merged back to ToT */
#define WLC_E_FIFO_CREDIT_MAP 74 /* credits for D11 FIFOs. [AC0,AC1,AC2,AC3,BC_MC,ATIM] */
#define WLC_E_ACTION_FRAME_RX 75 /* Received action frame event WITH
* wl_event_rx_frame_data_t header
*/
#define WLC_E_WAKE_EVENT 76 /* Wake Event timer fired, used for wake WLAN test mode */
#define WLC_E_RM_COMPLETE 77 /* Radio measurement complete */
#define WLC_E_HTSFSYNC 78 /* Synchronize TSF with the host */
#define WLC_E_OVERLAY_REQ 79 /* request an overlay IOCTL/iovar from the host */
#define WLC_E_CSA_COMPLETE_IND 80 /* 802.11 CHANNEL SWITCH ACTION completed */
#define WLC_E_EXCESS_PM_WAKE_EVENT 81 /* excess PM Wake Event to inform host */
#define WLC_E_PFN_SCAN_NONE 82 /* no PFN networks around */
#define WLC_E_PFN_SCAN_ALLGONE 83 /* last found PFN network gets lost */
#define WLC_E_GTK_PLUMBED 84
#define WLC_E_ASSOC_IND_NDIS 85 /* 802.11 ASSOC indication for NDIS only */
#define WLC_E_REASSOC_IND_NDIS 86 /* 802.11 REASSOC indication for NDIS only */
#define WLC_E_ASSOC_REQ_IE 87
#define WLC_E_ASSOC_RESP_IE 88
#define WLC_E_ASSOC_RECREATED 89 /* association recreated on resume */
#define WLC_E_ACTION_FRAME_RX_NDIS 90 /* rx action frame event for NDIS only */
#define WLC_E_AUTH_REQ 91 /* authentication request received */
#define WLC_E_TDLS_PEER_EVENT 92 /* discovered peer, connected/disconnected peer */
#define WLC_E_SPEEDY_RECREATE_FAIL 93 /* fast assoc recreation failed */
#define WLC_E_NATIVE 94 /* port-specific event and payload (e.g. NDIS) */
#define WLC_E_PKTDELAY_IND 95 /* event for tx pkt delay suddently jump */
#define WLC_E_AWDL_AW 96 /* AWDL AW period starts */
#define WLC_E_AWDL_ROLE 97 /* AWDL Master/Slave/NE master role event */
#define WLC_E_AWDL_EVENT 98 /* Generic AWDL event */
#ifdef WLNIC
#define WLC_E_NIC_AF_TXS 99 /* NIC AF txstatus */
#define WLC_E_NIC_NIC_REPORT 100 /* NIC period report */
#endif
#define WLC_E_BEACON_FRAME_RX 101
#define WLC_E_SERVICE_FOUND 102 /* desired service found */
#define WLC_E_GAS_FRAGMENT_RX 103 /* GAS fragment received */
#define WLC_E_GAS_COMPLETE 104 /* GAS sessions all complete */
#define WLC_E_P2PO_ADD_DEVICE 105 /* New device found by p2p offload */
#define WLC_E_P2PO_DEL_DEVICE 106 /* device has been removed by p2p offload */
#define WLC_E_WNM_STA_SLEEP 107 /* WNM event to notify STA enter sleep mode */
#define WLC_E_TXFAIL_THRESH 108 /* Indication of MAC tx failures (exhaustion of
* 802.11 retries) exceeding threshold(s)
*/
#define WLC_E_PROXD 109 /* Proximity Detection event */
#define WLC_E_IBSS_COALESCE 110 /* IBSS Coalescing */
#define WLC_E_AWDL_AW_EXT_END 111 /* AWDL extended period ends */
#define WLC_E_AWDL_AW_EXT_START 112 /* SWDL AW extension start */
#define WLC_E_AWDL_AW_START 113 /* AWDL start Event to inform host */
#define WLC_E_AWDL_RADIO_OFF 114 /* Radio Off */
#define WLC_E_AWDL_PEER_STATE 115 /* AWDL peer state open/close */
#define WLC_E_AWDL_SYNC_STATE_CHANGED 116 /* AWDL sync role changed */
#define WLC_E_AWDL_CHIP_RESET 117 /* infroms the interface of a chip rest */
#define WLC_E_AWDL_INTERLEAVED_SCAN_START 118
#define WLC_E_AWDL_INTERLEAVED_SCAN_STOP 119
#define WLC_E_AWDL_PEER_CACHE_CONTROL 120
#define WLC_E_CSA_START_IND 121
#define WLC_E_CSA_DONE_IND 122
#define WLC_E_CSA_FAILURE_IND 123
#define WLC_E_CCA_CHAN_QUAL 124 /* CCA based channel quality report */
#define WLC_E_BSSID 125 /* to report change in BSSID while roaming */
#define WLC_E_TX_STAT_ERROR 126 /* tx error indication */
#define WLC_E_BCMC_CREDIT_SUPPORT 127 /* credit check for BCMC supported */
#define WLC_E_PSTA_PRIMARY_INTF_IND 128 /* psta primary interface indication */
#define WLC_E_CCX_S69_RESP_RX 129 /* CCX S69 response received */
#define WLC_E_LAST 130 /* highest val + 1 for range checking */
/* xxx:
* Please do not insert/delete events in the middle causing renumbering.
* It is a problem for host-device compatibility, especially with ROMmed chips.
*/
/* Table of event name strings for UIs and debugging dumps */
typedef struct {
uint event;
const char *name;
} bcmevent_name_t;
extern const bcmevent_name_t bcmevent_names[];
extern const int bcmevent_names_size;
/* XXX Translate between internal and exported status codes */
/* Event status codes */
#define WLC_E_STATUS_SUCCESS 0 /* operation was successful */
#define WLC_E_STATUS_FAIL 1 /* operation failed */
#define WLC_E_STATUS_TIMEOUT 2 /* operation timed out */
#define WLC_E_STATUS_NO_NETWORKS 3 /* failed due to no matching network found */
#define WLC_E_STATUS_ABORT 4 /* operation was aborted */
#define WLC_E_STATUS_NO_ACK 5 /* protocol failure: packet not ack'd */
#define WLC_E_STATUS_UNSOLICITED 6 /* AUTH or ASSOC packet was unsolicited */
#define WLC_E_STATUS_ATTEMPT 7 /* attempt to assoc to an auto auth configuration */
#define WLC_E_STATUS_PARTIAL 8 /* scan results are incomplete */
#define WLC_E_STATUS_NEWSCAN 9 /* scan aborted by another scan */
#define WLC_E_STATUS_NEWASSOC 10 /* scan aborted due to assoc in progress */
#define WLC_E_STATUS_11HQUIET 11 /* 802.11h quiet period started */
#define WLC_E_STATUS_SUPPRESS 12 /* user disabled scanning (WLC_SET_SCANSUPPRESS) */
#define WLC_E_STATUS_NOCHANS 13 /* no allowable channels to scan */
#ifdef BCMCCX
#define WLC_E_STATUS_CCXFASTRM 14 /* scan aborted due to CCX fast roam */
#endif /* BCMCCX */
#define WLC_E_STATUS_CS_ABORT 15 /* abort channel select */
#define WLC_E_STATUS_ERROR 16 /* request failed due to error */
/* roam reason codes */
#define WLC_E_REASON_INITIAL_ASSOC 0 /* initial assoc */
#define WLC_E_REASON_LOW_RSSI 1 /* roamed due to low RSSI */
#define WLC_E_REASON_DEAUTH 2 /* roamed due to DEAUTH indication */
#define WLC_E_REASON_DISASSOC 3 /* roamed due to DISASSOC indication */
#define WLC_E_REASON_BCNS_LOST 4 /* roamed due to lost beacons */
/* Roam codes used primarily by CCX */
#define WLC_E_REASON_FAST_ROAM_FAILED 5 /* roamed due to fast roam failure */
#define WLC_E_REASON_DIRECTED_ROAM 6 /* roamed due to request by AP */
#define WLC_E_REASON_TSPEC_REJECTED 7 /* roamed due to TSPEC rejection */
#define WLC_E_REASON_BETTER_AP 8 /* roamed due to finding better AP */
#define WLC_E_REASON_MINTXRATE 9 /* roamed because at mintxrate for too long */
#define WLC_E_REASON_TXFAIL 10 /* We can hear AP, but AP can't hear us */
#define WLC_E_REASON_REQUESTED_ROAM 11 /* roamed due to BSS Mgmt Transition request by AP */
/* prune reason codes */
#define WLC_E_PRUNE_ENCR_MISMATCH 1 /* encryption mismatch */
#define WLC_E_PRUNE_BCAST_BSSID 2 /* AP uses a broadcast BSSID */
#define WLC_E_PRUNE_MAC_DENY 3 /* STA's MAC addr is in AP's MAC deny list */
#define WLC_E_PRUNE_MAC_NA 4 /* STA's MAC addr is not in AP's MAC allow list */
#define WLC_E_PRUNE_REG_PASSV 5 /* AP not allowed due to regulatory restriction */
#define WLC_E_PRUNE_SPCT_MGMT 6 /* AP does not support STA locale spectrum mgmt */
#define WLC_E_PRUNE_RADAR 7 /* AP is on a radar channel of STA locale */
#define WLC_E_RSN_MISMATCH 8 /* STA does not support AP's RSN */
#define WLC_E_PRUNE_NO_COMMON_RATES 9 /* No rates in common with AP */
#define WLC_E_PRUNE_BASIC_RATES 10 /* STA does not support all basic rates of BSS */
#ifdef BCMCCX
#define WLC_E_PRUNE_CCXFAST_PREVAP 11 /* CCX FAST ROAM: prune previous AP */
#endif /* def BCMCCX */
#define WLC_E_PRUNE_CIPHER_NA 12 /* BSS's cipher not supported */
#define WLC_E_PRUNE_KNOWN_STA 13 /* AP is already known to us as a STA */
#ifdef BCMCCX
#define WLC_E_PRUNE_CCXFAST_DROAM 14 /* CCX FAST ROAM: prune unqualified AP */
#endif /* def BCMCCX */
#define WLC_E_PRUNE_WDS_PEER 15 /* AP is already known to us as a WDS peer */
#define WLC_E_PRUNE_QBSS_LOAD 16 /* QBSS LOAD - AAC is too low */
#define WLC_E_PRUNE_HOME_AP 17 /* prune home AP */
#ifdef BCMCCX
#define WLC_E_PRUNE_AP_BLOCKED 18 /* prune blocked AP */
#define WLC_E_PRUNE_NO_DIAG_SUPPORT 19 /* prune due to diagnostic mode not supported */
#endif /* BCMCCX */
/* WPA failure reason codes carried in the WLC_E_PSK_SUP event */
#define WLC_E_SUP_OTHER 0 /* Other reason */
#define WLC_E_SUP_DECRYPT_KEY_DATA 1 /* Decryption of key data failed */
#define WLC_E_SUP_BAD_UCAST_WEP128 2 /* Illegal use of ucast WEP128 */
#define WLC_E_SUP_BAD_UCAST_WEP40 3 /* Illegal use of ucast WEP40 */
#define WLC_E_SUP_UNSUP_KEY_LEN 4 /* Unsupported key length */
#define WLC_E_SUP_PW_KEY_CIPHER 5 /* Unicast cipher mismatch in pairwise key */
#define WLC_E_SUP_MSG3_TOO_MANY_IE 6 /* WPA IE contains > 1 RSN IE in key msg 3 */
#define WLC_E_SUP_MSG3_IE_MISMATCH 7 /* WPA IE mismatch in key message 3 */
#define WLC_E_SUP_NO_INSTALL_FLAG 8 /* INSTALL flag unset in 4-way msg */
#define WLC_E_SUP_MSG3_NO_GTK 9 /* encapsulated GTK missing from msg 3 */
#define WLC_E_SUP_GRP_KEY_CIPHER 10 /* Multicast cipher mismatch in group key */
#define WLC_E_SUP_GRP_MSG1_NO_GTK 11 /* encapsulated GTK missing from group msg 1 */
#define WLC_E_SUP_GTK_DECRYPT_FAIL 12 /* GTK decrypt failure */
#define WLC_E_SUP_SEND_FAIL 13 /* message send failure */
#define WLC_E_SUP_DEAUTH 14 /* received FC_DEAUTH */
#define WLC_E_SUP_WPA_PSK_TMO 15 /* WPA PSK 4-way handshake timeout */
/* Event data for events that include frames received over the air */
/* WLC_E_PROBRESP_MSG
* WLC_E_P2P_PROBREQ_MSG
* WLC_E_ACTION_FRAME_RX
*/
#ifdef WLAWDL
#define WLC_E_AWDL_SCAN_START 1 /* Scan start indication to host */
#define WLC_E_AWDL_SCAN_DONE 0 /* Scan Done indication to host */
#define WLC_E_AWDL_RX_ACT_FRAME 1
#define WLC_E_AWDL_RX_PRB_RESP 2
#endif
typedef BWL_PRE_PACKED_STRUCT struct wl_event_rx_frame_data {
uint16 version;
uint16 channel; /* Matches chanspec_t format from bcmwifi_channels.h */
int32 rssi;
uint32 mactime;
uint32 rate;
} BWL_POST_PACKED_STRUCT wl_event_rx_frame_data_t;
#define BCM_RX_FRAME_DATA_VERSION 1
/* WLC_E_IF event data */
typedef struct wl_event_data_if {
uint8 ifidx; /* RTE virtual device index (for dongle) */
uint8 opcode; /* see I/F opcode */
uint8 reserved; /* bit mask (WLC_E_IF_FLAGS_XXX ) */
uint8 bssidx; /* bsscfg index */
uint8 role; /* see I/F role */
} wl_event_data_if_t;
/* opcode in WLC_E_IF event */
#define WLC_E_IF_ADD 1 /* bsscfg add */
#define WLC_E_IF_DEL 2 /* bsscfg delete */
#define WLC_E_IF_CHANGE 3 /* bsscfg role change */
/* I/F role code in WLC_E_IF event */
#define WLC_E_IF_ROLE_STA 0 /* Infra STA */
#define WLC_E_IF_ROLE_AP 1 /* Access Point */
#define WLC_E_IF_ROLE_WDS 2 /* WDS link */
#define WLC_E_IF_ROLE_P2P_GO 3 /* P2P Group Owner */
#define WLC_E_IF_ROLE_P2P_CLIENT 4 /* P2P Client */
#ifdef WLBTAMP
#define WLC_E_IF_ROLE_BTA_CREATOR 5 /* BT-AMP Creator */
#define WLC_E_IF_ROLE_BTA_ACCEPTOR 6 /* BT-AMP Acceptor */
#endif
/* WLC_E_RSSI event data */
typedef struct wl_event_data_rssi {
int32 rssi;
int32 snr;
int32 noise;
} wl_event_data_rssi_t;
/* WLC_E_IF flag */
#define WLC_E_IF_FLAGS_BSSCFG_NOIF 0x1 /* no host I/F creation needed */
/* Reason codes for LINK */
#define WLC_E_LINK_BCN_LOSS 1 /* Link down because of beacon loss */
#define WLC_E_LINK_DISASSOC 2 /* Link down because of disassoc */
#define WLC_E_LINK_ASSOC_REC 3 /* Link down because assoc recreate failed */
#define WLC_E_LINK_BSSCFG_DIS 4 /* Link down due to bsscfg down */
/* reason codes for WLC_E_OVERLAY_REQ event */
#define WLC_E_OVL_DOWNLOAD 0 /* overlay download request */
#define WLC_E_OVL_UPDATE_IND 1 /* device indication of host overlay update */
/* reason codes for WLC_E_TDLS_PEER_EVENT event */
#define WLC_E_TDLS_PEER_DISCOVERED 0 /* peer is ready to establish TDLS */
#define WLC_E_TDLS_PEER_CONNECTED 1
#define WLC_E_TDLS_PEER_DISCONNECTED 2
#ifdef WLAWDL
/* WLC_E_AWDL_EVENT subtypes */
#define WLC_E_AWDL_SCAN_STATUS 0
#define WLC_E_AWDL_RX_ACT_FRAME 1
#define WLC_E_AWDL_RX_PRB_RESP 2
#define WLC_E_AWDL_PHYCAL_STATUS 3
#define WLC_E_AWDL_WOWL_NULLPKT 4
#define WLC_E_AWDL_OOB_AF_STATUS 5
/* WLC_E_AWDL_SCAN_STATUS status values */
#define WLC_E_AWDL_SCAN_START 1 /* Scan start indication to host */
#define WLC_E_AWDL_SCAN_DONE 0 /* Scan Done indication to host */
#define WLC_E_AWDL_PHYCAL_START 1 /* Phy calibration start indication to host */
#define WLC_E_AWDL_PHYCAL_DONE 0 /* Phy calibration done indication to host */
#endif
/* GAS event data */
typedef BWL_PRE_PACKED_STRUCT struct wl_event_gas {
uint16 channel; /* channel of GAS protocol */
uint8 dialog_token; /* GAS dialog token */
uint8 fragment_id; /* fragment id */
uint16 status_code; /* status code on GAS completion */
uint16 data_len; /* length of data to follow */
uint8 data[1]; /* variable length specified by data_len */
} BWL_POST_PACKED_STRUCT wl_event_gas_t;
/* service discovery TLV */
typedef BWL_PRE_PACKED_STRUCT struct wl_sd_tlv {
uint16 length; /* length of response_data */
uint8 protocol; /* service protocol type */
uint8 transaction_id; /* service transaction id */
uint8 status_code; /* status code */
uint8 data[1]; /* response data */
} BWL_POST_PACKED_STRUCT wl_sd_tlv_t;
/* service discovery event data */
typedef BWL_PRE_PACKED_STRUCT struct wl_event_sd {
uint16 channel; /* channel */
uint8 count; /* number of tlvs */
wl_sd_tlv_t tlv[1]; /* service discovery TLV */
} BWL_POST_PACKED_STRUCT wl_event_sd_t;
/* Reason codes for WLC_E_PROXD */
#define WLC_E_PROXD_FOUND 1 /* Found a proximity device */
#define WLC_E_PROXD_GONE 2 /* Lost a proximity device */
/* WLC_E_AWDL_AW event data */
typedef BWL_PRE_PACKED_STRUCT struct awdl_aws_event_data {
uint32 fw_time; /* firmware PMU time */
struct ether_addr current_master; /* Current master Mac addr */
uint16 aw_counter; /* AW seq# */
uint8 aw_ext_count; /* AW extension count */
uint8 aw_role; /* AW role */
uint8 flags; /* AW event flag */
uint16 aw_chan;
uint8 infra_rssi; /* rssi on the infra channel */
uint32 infra_rxbcn_count; /* number of beacons received */
} BWL_POST_PACKED_STRUCT awdl_aws_event_data_t;
/* For awdl_aws_event_data_t.flags */
#define AWDL_AW_LAST_EXT 0x01
/* WLC_E_AWDL_OOB_AF_STATUS event data */
typedef BWL_PRE_PACKED_STRUCT struct awdl_oob_af_status_data {
uint32 tx_time_diff;
uint16 pkt_tag;
uint8 tx_chan;
} BWL_POST_PACKED_STRUCT awdl_oob_af_status_data_t;
/* Video Traffic Interference Monitor Event */
#define INTFER_EVENT_VERSION 1
#define INTFER_STREAM_TYPE_NONTCP 1
#define INTFER_STREAM_TYPE_TCP 2
#define WLINTFER_STATS_NSMPLS 4
typedef struct wl_intfer_event {
uint16 version; /* version */
uint16 status; /* status */
uint8 txfail_histo[WLINTFER_STATS_NSMPLS]; /* txfail histo */
} wl_intfer_event_t;
/* WLC_E_PSTA_PRIMARY_INTF_IND event data */
typedef struct wl_psta_primary_intf_event {
struct ether_addr prim_ea; /* primary intf ether addr */
} wl_psta_primary_intf_event_t;
/* This marks the end of a packed structure section. */
#include <packed_section_end.h>
#endif /* _BCMEVENT_H_ */

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/*
* $Copyright Open Broadcom Corporation$
*
* Fundamental constants relating to IP Protocol
*
* $Id: bcmip.h 407107 2013-06-11 19:39:14Z esawma $
*/
#ifndef _bcmip_h_
#define _bcmip_h_
#ifndef _TYPEDEFS_H_
#include <typedefs.h>
#endif
/* This marks the start of a packed structure section. */
#include <packed_section_start.h>
/* IPV4 and IPV6 common */
#define IP_VER_OFFSET 0x0 /* offset to version field */
#define IP_VER_MASK 0xf0 /* version mask */
#define IP_VER_SHIFT 4 /* version shift */
#define IP_VER_4 4 /* version number for IPV4 */
#define IP_VER_6 6 /* version number for IPV6 */
#define IP_VER(ip_body) \
((((uint8 *)(ip_body))[IP_VER_OFFSET] & IP_VER_MASK) >> IP_VER_SHIFT)
#define IP_PROT_ICMP 0x1 /* ICMP protocol */
#define IP_PROT_IGMP 0x2 /* IGMP protocol */
#define IP_PROT_TCP 0x6 /* TCP protocol */
#define IP_PROT_UDP 0x11 /* UDP protocol type */
#define IP_PROT_ICMP6 0x3a /* ICMPv6 protocol type */
/* IPV4 field offsets */
#define IPV4_VER_HL_OFFSET 0 /* version and ihl byte offset */
#define IPV4_TOS_OFFSET 1 /* type of service offset */
#define IPV4_PKTLEN_OFFSET 2 /* packet length offset */
#define IPV4_PKTFLAG_OFFSET 6 /* more-frag,dont-frag flag offset */
#define IPV4_PROT_OFFSET 9 /* protocol type offset */
#define IPV4_CHKSUM_OFFSET 10 /* IP header checksum offset */
#define IPV4_SRC_IP_OFFSET 12 /* src IP addr offset */
#define IPV4_DEST_IP_OFFSET 16 /* dest IP addr offset */
#define IPV4_OPTIONS_OFFSET 20 /* IP options offset */
#define IPV4_MIN_HEADER_LEN 20 /* Minimum size for an IP header (no options) */
/* IPV4 field decodes */
#define IPV4_VER_MASK 0xf0 /* IPV4 version mask */
#define IPV4_VER_SHIFT 4 /* IPV4 version shift */
#define IPV4_HLEN_MASK 0x0f /* IPV4 header length mask */
#define IPV4_HLEN(ipv4_body) (4 * (((uint8 *)(ipv4_body))[IPV4_VER_HL_OFFSET] & IPV4_HLEN_MASK))
#define IPV4_ADDR_LEN 4 /* IPV4 address length */
#define IPV4_ADDR_NULL(a) ((((uint8 *)(a))[0] | ((uint8 *)(a))[1] | \
((uint8 *)(a))[2] | ((uint8 *)(a))[3]) == 0)
#define IPV4_ADDR_BCAST(a) ((((uint8 *)(a))[0] & ((uint8 *)(a))[1] & \
((uint8 *)(a))[2] & ((uint8 *)(a))[3]) == 0xff)
#define IPV4_TOS_DSCP_MASK 0xfc /* DiffServ codepoint mask */
#define IPV4_TOS_DSCP_SHIFT 2 /* DiffServ codepoint shift */
#define IPV4_TOS(ipv4_body) (((uint8 *)(ipv4_body))[IPV4_TOS_OFFSET])
#define IPV4_TOS_PREC_MASK 0xe0 /* Historical precedence mask */
#define IPV4_TOS_PREC_SHIFT 5 /* Historical precedence shift */
#define IPV4_TOS_LOWDELAY 0x10 /* Lowest delay requested */
#define IPV4_TOS_THROUGHPUT 0x8 /* Best throughput requested */
#define IPV4_TOS_RELIABILITY 0x4 /* Most reliable delivery requested */
#define IPV4_PROT(ipv4_body) (((uint8 *)(ipv4_body))[IPV4_PROT_OFFSET])
#define IPV4_FRAG_RESV 0x8000 /* Reserved */
#define IPV4_FRAG_DONT 0x4000 /* Don't fragment */
#define IPV4_FRAG_MORE 0x2000 /* More fragments */
#define IPV4_FRAG_OFFSET_MASK 0x1fff /* Fragment offset */
#define IPV4_ADDR_STR_LEN 16 /* Max IP address length in string format */
/* IPV4 packet formats */
BWL_PRE_PACKED_STRUCT struct ipv4_addr {
uint8 addr[IPV4_ADDR_LEN];
} BWL_POST_PACKED_STRUCT;
BWL_PRE_PACKED_STRUCT struct ipv4_hdr {
uint8 version_ihl; /* Version and Internet Header Length */
uint8 tos; /* Type Of Service */
uint16 tot_len; /* Number of bytes in packet (max 65535) */
uint16 id;
uint16 frag; /* 3 flag bits and fragment offset */
uint8 ttl; /* Time To Live */
uint8 prot; /* Protocol */
uint16 hdr_chksum; /* IP header checksum */
uint8 src_ip[IPV4_ADDR_LEN]; /* Source IP Address */
uint8 dst_ip[IPV4_ADDR_LEN]; /* Destination IP Address */
} BWL_POST_PACKED_STRUCT;
/* IPV6 field offsets */
#define IPV6_PAYLOAD_LEN_OFFSET 4 /* payload length offset */
#define IPV6_NEXT_HDR_OFFSET 6 /* next header/protocol offset */
#define IPV6_HOP_LIMIT_OFFSET 7 /* hop limit offset */
#define IPV6_SRC_IP_OFFSET 8 /* src IP addr offset */
#define IPV6_DEST_IP_OFFSET 24 /* dst IP addr offset */
/* IPV6 field decodes */
#define IPV6_TRAFFIC_CLASS(ipv6_body) \
(((((uint8 *)(ipv6_body))[0] & 0x0f) << 4) | \
((((uint8 *)(ipv6_body))[1] & 0xf0) >> 4))
#define IPV6_FLOW_LABEL(ipv6_body) \
(((((uint8 *)(ipv6_body))[1] & 0x0f) << 16) | \
(((uint8 *)(ipv6_body))[2] << 8) | \
(((uint8 *)(ipv6_body))[3]))
#define IPV6_PAYLOAD_LEN(ipv6_body) \
((((uint8 *)(ipv6_body))[IPV6_PAYLOAD_LEN_OFFSET + 0] << 8) | \
((uint8 *)(ipv6_body))[IPV6_PAYLOAD_LEN_OFFSET + 1])
#define IPV6_NEXT_HDR(ipv6_body) \
(((uint8 *)(ipv6_body))[IPV6_NEXT_HDR_OFFSET])
#define IPV6_PROT(ipv6_body) IPV6_NEXT_HDR(ipv6_body)
#define IPV6_ADDR_LEN 16 /* IPV6 address length */
/* IPV4 TOS or IPV6 Traffic Classifier or 0 */
#define IP_TOS46(ip_body) \
(IP_VER(ip_body) == IP_VER_4 ? IPV4_TOS(ip_body) : \
IP_VER(ip_body) == IP_VER_6 ? IPV6_TRAFFIC_CLASS(ip_body) : 0)
#define IP_DSCP46(ip_body) (IP_TOS46(ip_body) >> IPV4_TOS_DSCP_SHIFT);
/* IPV6 extension headers (options) */
#define IPV6_EXTHDR_HOP 0
#define IPV6_EXTHDR_ROUTING 43
#define IPV6_EXTHDR_FRAGMENT 44
#define IPV6_EXTHDR_AUTH 51
#define IPV6_EXTHDR_NONE 59
#define IPV6_EXTHDR_DEST 60
#define IPV6_EXTHDR(prot) (((prot) == IPV6_EXTHDR_HOP) || \
((prot) == IPV6_EXTHDR_ROUTING) || \
((prot) == IPV6_EXTHDR_FRAGMENT) || \
((prot) == IPV6_EXTHDR_AUTH) || \
((prot) == IPV6_EXTHDR_NONE) || \
((prot) == IPV6_EXTHDR_DEST))
#define IPV6_MIN_HLEN 40
#define IPV6_EXTHDR_LEN(eh) ((((struct ipv6_exthdr *)(eh))->hdrlen + 1) << 3)
BWL_PRE_PACKED_STRUCT struct ipv6_exthdr {
uint8 nexthdr;
uint8 hdrlen;
} BWL_POST_PACKED_STRUCT;
BWL_PRE_PACKED_STRUCT struct ipv6_exthdr_frag {
uint8 nexthdr;
uint8 rsvd;
uint16 frag_off;
uint32 ident;
} BWL_POST_PACKED_STRUCT;
static INLINE int32
ipv6_exthdr_len(uint8 *h, uint8 *proto)
{
uint16 len = 0, hlen;
struct ipv6_exthdr *eh = (struct ipv6_exthdr *)h;
while (IPV6_EXTHDR(eh->nexthdr)) {
if (eh->nexthdr == IPV6_EXTHDR_NONE)
return -1;
else if (eh->nexthdr == IPV6_EXTHDR_FRAGMENT)
hlen = 8;
else if (eh->nexthdr == IPV6_EXTHDR_AUTH)
hlen = (eh->hdrlen + 2) << 2;
else
hlen = IPV6_EXTHDR_LEN(eh);
len += hlen;
eh = (struct ipv6_exthdr *)(h + len);
}
*proto = eh->nexthdr;
return len;
}
#define IPV4_ISMULTI(a) (((a) & 0xf0000000) == 0xe0000000)
#define IPV4_MCAST_TO_ETHER_MCAST(ipv4, ether) \
{ \
ether[0] = 0x01; \
ether[1] = 0x00; \
ether[2] = 0x5E; \
ether[3] = (ipv4 & 0x7f0000) >> 16; \
ether[4] = (ipv4 & 0xff00) >> 8; \
ether[5] = (ipv4 & 0xff); \
}
/* This marks the end of a packed structure section. */
#include <packed_section_end.h>
#endif /* _bcmip_h_ */

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/*
* $Copyright Open Broadcom Corporation$
*
* Fundamental constants relating to Neighbor Discovery Protocol
*
* $Id: bcmipv6.h 399481 2013-04-30 09:24:20Z cylee $
*/
#ifndef _bcmipv6_h_
#define _bcmipv6_h_
#ifndef _TYPEDEFS_H_
#include <typedefs.h>
#endif
/* This marks the start of a packed structure section. */
#include <packed_section_start.h>
/* Extension headers */
#define IPV6_EXT_HOP 0
#define IPV6_EXT_ROUTE 43
#define IPV6_EXT_FRAG 44
#define IPV6_EXT_DEST 60
#define IPV6_EXT_ESEC 50
#define IPV6_EXT_AUTH 51
/* Minimum size (extension header "word" length) */
#define IPV6_EXT_WORD 8
/* Offsets for most extension headers */
#define IPV6_EXT_NEXTHDR 0
#define IPV6_EXT_HDRLEN 1
/* Constants specific to fragmentation header */
#define IPV6_FRAG_MORE_MASK 0x0001
#define IPV6_FRAG_MORE_SHIFT 0
#define IPV6_FRAG_OFFS_MASK 0xfff8
#define IPV6_FRAG_OFFS_SHIFT 3
/* For icmpv6 */
#define ICMPV6_HEADER_TYPE 0x3A
#define ICMPV6_PKT_TYPE_NS 135
#define ICMPV6_PKT_TYPE_NA 136
#define ICMPV6_ND_OPT_TYPE_TARGET_MAC 2
#define ICMPV6_ND_OPT_TYPE_SRC_MAC 1
#define ICMPV6_ND_OPT_LEN_LINKADDR 1
#define ICMPV6_ND_OPT_LEN_LINKADDR 1
#define IPV6_VERSION 6
#define IPV6_HOP_LIMIT 255
#define IPV6_ADDR_NULL(a) ((a[0] | a[1] | a[2] | a[3] | a[4] | \
a[5] | a[6] | a[7] | a[8] | a[9] | \
a[10] | a[11] | a[12] | a[13] | \
a[14] | a[15]) == 0)
#define IPV6_ADDR_LOCAL(a) (((a[0] == 0xfe) && (a[1] & 0x80))? TRUE: FALSE)
/* IPV6 address */
BWL_PRE_PACKED_STRUCT struct ipv6_addr {
uint8 addr[16];
} BWL_POST_PACKED_STRUCT;
/* XXX use masks, htonl instead of bit fileds */
#ifndef IL_BIGENDIAN
/* ICMPV6 Header */
BWL_PRE_PACKED_STRUCT struct icmp6_hdr {
uint8 icmp6_type;
uint8 icmp6_code;
uint16 icmp6_cksum;
BWL_PRE_PACKED_STRUCT union {
uint32 reserved;
BWL_PRE_PACKED_STRUCT struct nd_advt {
uint32 reserved1:5,
override:1,
solicited:1,
router:1,
reserved2:24;
} BWL_POST_PACKED_STRUCT nd_advt;
} BWL_POST_PACKED_STRUCT opt;
} BWL_POST_PACKED_STRUCT;
/* Ipv6 Header Format */
BWL_PRE_PACKED_STRUCT struct ipv6_hdr {
uint8 priority:4,
version:4;
uint8 flow_lbl[3];
uint16 payload_len;
uint8 nexthdr;
uint8 hop_limit;
struct ipv6_addr saddr;
struct ipv6_addr daddr;
} BWL_POST_PACKED_STRUCT;
/* Neighbor Advertisement/Solicitation Packet Structure */
BWL_PRE_PACKED_STRUCT struct nd_msg {
struct icmp6_hdr icmph;
struct ipv6_addr target;
} BWL_POST_PACKED_STRUCT;
/* Neighibor Solicitation/Advertisement Optional Structure */
BWL_PRE_PACKED_STRUCT struct nd_msg_opt {
uint8 type;
uint8 len;
uint8 mac_addr[ETHER_ADDR_LEN];
} BWL_POST_PACKED_STRUCT;
/* Ipv6 Fragmentation Header */
BWL_PRE_PACKED_STRUCT struct ipv6_frag {
uint8 nexthdr;
uint8 reserved;
uint16 frag_offset;
uint32 ident;
} BWL_POST_PACKED_STRUCT;
#endif /* IL_BIGENDIAN */
/* This marks the end of a packed structure section. */
#include <packed_section_end.h>
static const struct ipv6_addr all_node_ipv6_maddr = {
{ 0xff, 0x2, 0, 0,
0, 0, 0, 0,
0, 0, 0, 0,
0, 0, 0, 1
}};
#define IPV6_ISMULTI(a) (a[0] == 0xff)
#define IPV6_MCAST_TO_ETHER_MCAST(ipv6, ether) \
{ \
ether[0] = 0x33; \
ether[1] = 0x33; \
ether[2] = ipv6[12]; \
ether[3] = ipv6[13]; \
ether[4] = ipv6[14]; \
ether[5] = ipv6[15]; \
}
#endif /* !defined(_bcmipv6_h_) */

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/*
* BT-AMP (BlueTooth Alternate Mac and Phy) HCI (Host/Controller Interface)
*
* $Copyright Open Broadcom Corporation$
*
* $Id: bt_amp_hci.h 294267 2011-11-04 23:41:52Z $
*/
#ifndef _bt_amp_hci_h
#define _bt_amp_hci_h
/* This marks the start of a packed structure section. */
#include <packed_section_start.h>
/* AMP HCI CMD packet format */
typedef BWL_PRE_PACKED_STRUCT struct amp_hci_cmd {
uint16 opcode;
uint8 plen;
uint8 parms[1];
} BWL_POST_PACKED_STRUCT amp_hci_cmd_t;
#define HCI_CMD_PREAMBLE_SIZE OFFSETOF(amp_hci_cmd_t, parms)
#define HCI_CMD_DATA_SIZE 255
/* AMP HCI CMD opcode layout */
#define HCI_CMD_OPCODE(ogf, ocf) ((((ogf) & 0x3F) << 10) | ((ocf) & 0x03FF))
#define HCI_CMD_OGF(opcode) ((uint8)(((opcode) >> 10) & 0x3F))
#define HCI_CMD_OCF(opcode) ((opcode) & 0x03FF)
/* AMP HCI command opcodes */
#define HCI_Read_Failed_Contact_Counter HCI_CMD_OPCODE(0x05, 0x0001)
#define HCI_Reset_Failed_Contact_Counter HCI_CMD_OPCODE(0x05, 0x0002)
#define HCI_Read_Link_Quality HCI_CMD_OPCODE(0x05, 0x0003)
#define HCI_Read_Local_AMP_Info HCI_CMD_OPCODE(0x05, 0x0009)
#define HCI_Read_Local_AMP_ASSOC HCI_CMD_OPCODE(0x05, 0x000A)
#define HCI_Write_Remote_AMP_ASSOC HCI_CMD_OPCODE(0x05, 0x000B)
#define HCI_Create_Physical_Link HCI_CMD_OPCODE(0x01, 0x0035)
#define HCI_Accept_Physical_Link_Request HCI_CMD_OPCODE(0x01, 0x0036)
#define HCI_Disconnect_Physical_Link HCI_CMD_OPCODE(0x01, 0x0037)
#define HCI_Create_Logical_Link HCI_CMD_OPCODE(0x01, 0x0038)
#define HCI_Accept_Logical_Link HCI_CMD_OPCODE(0x01, 0x0039)
#define HCI_Disconnect_Logical_Link HCI_CMD_OPCODE(0x01, 0x003A)
#define HCI_Logical_Link_Cancel HCI_CMD_OPCODE(0x01, 0x003B)
#define HCI_Flow_Spec_Modify HCI_CMD_OPCODE(0x01, 0x003C)
#define HCI_Write_Flow_Control_Mode HCI_CMD_OPCODE(0x01, 0x0067)
#define HCI_Read_Best_Effort_Flush_Timeout HCI_CMD_OPCODE(0x01, 0x0069)
#define HCI_Write_Best_Effort_Flush_Timeout HCI_CMD_OPCODE(0x01, 0x006A)
#define HCI_Short_Range_Mode HCI_CMD_OPCODE(0x01, 0x006B)
#define HCI_Reset HCI_CMD_OPCODE(0x03, 0x0003)
#define HCI_Read_Connection_Accept_Timeout HCI_CMD_OPCODE(0x03, 0x0015)
#define HCI_Write_Connection_Accept_Timeout HCI_CMD_OPCODE(0x03, 0x0016)
#define HCI_Read_Link_Supervision_Timeout HCI_CMD_OPCODE(0x03, 0x0036)
#define HCI_Write_Link_Supervision_Timeout HCI_CMD_OPCODE(0x03, 0x0037)
#define HCI_Enhanced_Flush HCI_CMD_OPCODE(0x03, 0x005F)
#define HCI_Read_Logical_Link_Accept_Timeout HCI_CMD_OPCODE(0x03, 0x0061)
#define HCI_Write_Logical_Link_Accept_Timeout HCI_CMD_OPCODE(0x03, 0x0062)
#define HCI_Set_Event_Mask_Page_2 HCI_CMD_OPCODE(0x03, 0x0063)
#define HCI_Read_Location_Data_Command HCI_CMD_OPCODE(0x03, 0x0064)
#define HCI_Write_Location_Data_Command HCI_CMD_OPCODE(0x03, 0x0065)
#define HCI_Read_Local_Version_Info HCI_CMD_OPCODE(0x04, 0x0001)
#define HCI_Read_Local_Supported_Commands HCI_CMD_OPCODE(0x04, 0x0002)
#define HCI_Read_Buffer_Size HCI_CMD_OPCODE(0x04, 0x0005)
#define HCI_Read_Data_Block_Size HCI_CMD_OPCODE(0x04, 0x000A)
/* AMP HCI command parameters */
typedef BWL_PRE_PACKED_STRUCT struct read_local_cmd_parms {
uint8 plh;
uint8 offset[2]; /* length so far */
uint8 max_remote[2];
} BWL_POST_PACKED_STRUCT read_local_cmd_parms_t;
typedef BWL_PRE_PACKED_STRUCT struct write_remote_cmd_parms {
uint8 plh;
uint8 offset[2];
uint8 len[2];
uint8 frag[1];
} BWL_POST_PACKED_STRUCT write_remote_cmd_parms_t;
typedef BWL_PRE_PACKED_STRUCT struct phy_link_cmd_parms {
uint8 plh;
uint8 key_length;
uint8 key_type;
uint8 key[1];
} BWL_POST_PACKED_STRUCT phy_link_cmd_parms_t;
typedef BWL_PRE_PACKED_STRUCT struct dis_phy_link_cmd_parms {
uint8 plh;
uint8 reason;
} BWL_POST_PACKED_STRUCT dis_phy_link_cmd_parms_t;
typedef BWL_PRE_PACKED_STRUCT struct log_link_cmd_parms {
uint8 plh;
uint8 txflow[16];
uint8 rxflow[16];
} BWL_POST_PACKED_STRUCT log_link_cmd_parms_t;
typedef BWL_PRE_PACKED_STRUCT struct ext_flow_spec {
uint8 id;
uint8 service_type;
uint8 max_sdu[2];
uint8 sdu_ia_time[4];
uint8 access_latency[4];
uint8 flush_timeout[4];
} BWL_POST_PACKED_STRUCT ext_flow_spec_t;
typedef BWL_PRE_PACKED_STRUCT struct log_link_cancel_cmd_parms {
uint8 plh;
uint8 tx_fs_ID;
} BWL_POST_PACKED_STRUCT log_link_cancel_cmd_parms_t;
typedef BWL_PRE_PACKED_STRUCT struct flow_spec_mod_cmd_parms {
uint8 llh[2];
uint8 txflow[16];
uint8 rxflow[16];
} BWL_POST_PACKED_STRUCT flow_spec_mod_cmd_parms_t;
typedef BWL_PRE_PACKED_STRUCT struct plh_pad {
uint8 plh;
uint8 pad;
} BWL_POST_PACKED_STRUCT plh_pad_t;
typedef BWL_PRE_PACKED_STRUCT union hci_handle {
uint16 bredr;
plh_pad_t amp;
} BWL_POST_PACKED_STRUCT hci_handle_t;
typedef BWL_PRE_PACKED_STRUCT struct ls_to_cmd_parms {
hci_handle_t handle;
uint8 timeout[2];
} BWL_POST_PACKED_STRUCT ls_to_cmd_parms_t;
typedef BWL_PRE_PACKED_STRUCT struct befto_cmd_parms {
uint8 llh[2];
uint8 befto[4];
} BWL_POST_PACKED_STRUCT befto_cmd_parms_t;
typedef BWL_PRE_PACKED_STRUCT struct srm_cmd_parms {
uint8 plh;
uint8 srm;
} BWL_POST_PACKED_STRUCT srm_cmd_parms_t;
typedef BWL_PRE_PACKED_STRUCT struct ld_cmd_parms {
uint8 ld_aware;
uint8 ld[2];
uint8 ld_opts;
uint8 l_opts;
} BWL_POST_PACKED_STRUCT ld_cmd_parms_t;
typedef BWL_PRE_PACKED_STRUCT struct eflush_cmd_parms {
uint8 llh[2];
uint8 packet_type;
} BWL_POST_PACKED_STRUCT eflush_cmd_parms_t;
/* Generic AMP extended flow spec service types */
#define EFS_SVCTYPE_NO_TRAFFIC 0
#define EFS_SVCTYPE_BEST_EFFORT 1
#define EFS_SVCTYPE_GUARANTEED 2
/* AMP HCI event packet format */
typedef BWL_PRE_PACKED_STRUCT struct amp_hci_event {
uint8 ecode;
uint8 plen;
uint8 parms[1];
} BWL_POST_PACKED_STRUCT amp_hci_event_t;
#define HCI_EVT_PREAMBLE_SIZE OFFSETOF(amp_hci_event_t, parms)
/* AMP HCI event codes */
#define HCI_Command_Complete 0x0E
#define HCI_Command_Status 0x0F
#define HCI_Flush_Occurred 0x11
#define HCI_Enhanced_Flush_Complete 0x39
#define HCI_Physical_Link_Complete 0x40
#define HCI_Channel_Select 0x41
#define HCI_Disconnect_Physical_Link_Complete 0x42
#define HCI_Logical_Link_Complete 0x45
#define HCI_Disconnect_Logical_Link_Complete 0x46
#define HCI_Flow_Spec_Modify_Complete 0x47
#define HCI_Number_of_Completed_Data_Blocks 0x48
#define HCI_Short_Range_Mode_Change_Complete 0x4C
#define HCI_Status_Change_Event 0x4D
#define HCI_Vendor_Specific 0xFF
/* AMP HCI event mask bit positions */
#define HCI_Physical_Link_Complete_Event_Mask 0x0001
#define HCI_Channel_Select_Event_Mask 0x0002
#define HCI_Disconnect_Physical_Link_Complete_Event_Mask 0x0004
#define HCI_Logical_Link_Complete_Event_Mask 0x0020
#define HCI_Disconnect_Logical_Link_Complete_Event_Mask 0x0040
#define HCI_Flow_Spec_Modify_Complete_Event_Mask 0x0080
#define HCI_Number_of_Completed_Data_Blocks_Event_Mask 0x0100
#define HCI_Short_Range_Mode_Change_Complete_Event_Mask 0x1000
#define HCI_Status_Change_Event_Mask 0x2000
#define HCI_All_Event_Mask 0x31e7
/* AMP HCI event parameters */
typedef BWL_PRE_PACKED_STRUCT struct cmd_status_parms {
uint8 status;
uint8 cmdpkts;
uint16 opcode;
} BWL_POST_PACKED_STRUCT cmd_status_parms_t;
typedef BWL_PRE_PACKED_STRUCT struct cmd_complete_parms {
uint8 cmdpkts;
uint16 opcode;
uint8 parms[1];
} BWL_POST_PACKED_STRUCT cmd_complete_parms_t;
typedef BWL_PRE_PACKED_STRUCT struct flush_occurred_evt_parms {
uint16 handle;
} BWL_POST_PACKED_STRUCT flush_occurred_evt_parms_t;
typedef BWL_PRE_PACKED_STRUCT struct write_remote_evt_parms {
uint8 status;
uint8 plh;
} BWL_POST_PACKED_STRUCT write_remote_evt_parms_t;
typedef BWL_PRE_PACKED_STRUCT struct read_local_evt_parms {
uint8 status;
uint8 plh;
uint16 len;
uint8 frag[1];
} BWL_POST_PACKED_STRUCT read_local_evt_parms_t;
typedef BWL_PRE_PACKED_STRUCT struct read_local_info_evt_parms {
uint8 status;
uint8 AMP_status;
uint32 bandwidth;
uint32 gbandwidth;
uint32 latency;
uint32 PDU_size;
uint8 ctrl_type;
uint16 PAL_cap;
uint16 AMP_ASSOC_len;
uint32 max_flush_timeout;
uint32 be_flush_timeout;
} BWL_POST_PACKED_STRUCT read_local_info_evt_parms_t;
typedef BWL_PRE_PACKED_STRUCT struct log_link_evt_parms {
uint8 status;
uint16 llh;
uint8 plh;
uint8 tx_fs_ID;
} BWL_POST_PACKED_STRUCT log_link_evt_parms_t;
typedef BWL_PRE_PACKED_STRUCT struct disc_log_link_evt_parms {
uint8 status;
uint16 llh;
uint8 reason;
} BWL_POST_PACKED_STRUCT disc_log_link_evt_parms_t;
typedef BWL_PRE_PACKED_STRUCT struct log_link_cancel_evt_parms {
uint8 status;
uint8 plh;
uint8 tx_fs_ID;
} BWL_POST_PACKED_STRUCT log_link_cancel_evt_parms_t;
typedef BWL_PRE_PACKED_STRUCT struct flow_spec_mod_evt_parms {
uint8 status;
uint16 llh;
} BWL_POST_PACKED_STRUCT flow_spec_mod_evt_parms_t;
typedef BWL_PRE_PACKED_STRUCT struct phy_link_evt_parms {
uint8 status;
uint8 plh;
} BWL_POST_PACKED_STRUCT phy_link_evt_parms_t;
typedef BWL_PRE_PACKED_STRUCT struct dis_phy_link_evt_parms {
uint8 status;
uint8 plh;
uint8 reason;
} BWL_POST_PACKED_STRUCT dis_phy_link_evt_parms_t;
typedef BWL_PRE_PACKED_STRUCT struct read_ls_to_evt_parms {
uint8 status;
hci_handle_t handle;
uint16 timeout;
} BWL_POST_PACKED_STRUCT read_ls_to_evt_parms_t;
typedef BWL_PRE_PACKED_STRUCT struct read_lla_ca_to_evt_parms {
uint8 status;
uint16 timeout;
} BWL_POST_PACKED_STRUCT read_lla_ca_to_evt_parms_t;
typedef BWL_PRE_PACKED_STRUCT struct read_data_block_size_evt_parms {
uint8 status;
uint16 ACL_pkt_len;
uint16 data_block_len;
uint16 data_block_num;
} BWL_POST_PACKED_STRUCT read_data_block_size_evt_parms_t;
typedef BWL_PRE_PACKED_STRUCT struct data_blocks {
uint16 handle;
uint16 pkts;
uint16 blocks;
} BWL_POST_PACKED_STRUCT data_blocks_t;
typedef BWL_PRE_PACKED_STRUCT struct num_completed_data_blocks_evt_parms {
uint16 num_blocks;
uint8 num_handles;
data_blocks_t completed[1];
} BWL_POST_PACKED_STRUCT num_completed_data_blocks_evt_parms_t;
typedef BWL_PRE_PACKED_STRUCT struct befto_evt_parms {
uint8 status;
uint32 befto;
} BWL_POST_PACKED_STRUCT befto_evt_parms_t;
typedef BWL_PRE_PACKED_STRUCT struct srm_evt_parms {
uint8 status;
uint8 plh;
uint8 srm;
} BWL_POST_PACKED_STRUCT srm_evt_parms_t;
typedef BWL_PRE_PACKED_STRUCT struct contact_counter_evt_parms {
uint8 status;
uint8 llh[2];
uint16 counter;
} BWL_POST_PACKED_STRUCT contact_counter_evt_parms_t;
typedef BWL_PRE_PACKED_STRUCT struct contact_counter_reset_evt_parms {
uint8 status;
uint8 llh[2];
} BWL_POST_PACKED_STRUCT contact_counter_reset_evt_parms_t;
typedef BWL_PRE_PACKED_STRUCT struct read_linkq_evt_parms {
uint8 status;
hci_handle_t handle;
uint8 link_quality;
} BWL_POST_PACKED_STRUCT read_linkq_evt_parms_t;
typedef BWL_PRE_PACKED_STRUCT struct ld_evt_parms {
uint8 status;
uint8 ld_aware;
uint8 ld[2];
uint8 ld_opts;
uint8 l_opts;
} BWL_POST_PACKED_STRUCT ld_evt_parms_t;
typedef BWL_PRE_PACKED_STRUCT struct eflush_complete_evt_parms {
uint16 handle;
} BWL_POST_PACKED_STRUCT eflush_complete_evt_parms_t;
typedef BWL_PRE_PACKED_STRUCT struct vendor_specific_evt_parms {
uint8 len;
uint8 parms[1];
} BWL_POST_PACKED_STRUCT vendor_specific_evt_parms_t;
typedef BWL_PRE_PACKED_STRUCT struct local_version_info_evt_parms {
uint8 status;
uint8 hci_version;
uint16 hci_revision;
uint8 pal_version;
uint16 mfg_name;
uint16 pal_subversion;
} BWL_POST_PACKED_STRUCT local_version_info_evt_parms_t;
#define MAX_SUPPORTED_CMD_BYTE 64
typedef BWL_PRE_PACKED_STRUCT struct local_supported_cmd_evt_parms {
uint8 status;
uint8 cmd[MAX_SUPPORTED_CMD_BYTE];
} BWL_POST_PACKED_STRUCT local_supported_cmd_evt_parms_t;
typedef BWL_PRE_PACKED_STRUCT struct status_change_evt_parms {
uint8 status;
uint8 amp_status;
} BWL_POST_PACKED_STRUCT status_change_evt_parms_t;
/* AMP HCI error codes */
#define HCI_SUCCESS 0x00
#define HCI_ERR_ILLEGAL_COMMAND 0x01
#define HCI_ERR_NO_CONNECTION 0x02
#define HCI_ERR_MEMORY_FULL 0x07
#define HCI_ERR_CONNECTION_TIMEOUT 0x08
#define HCI_ERR_MAX_NUM_OF_CONNECTIONS 0x09
#define HCI_ERR_CONNECTION_EXISTS 0x0B
#define HCI_ERR_CONNECTION_DISALLOWED 0x0C
#define HCI_ERR_CONNECTION_ACCEPT_TIMEOUT 0x10
#define HCI_ERR_UNSUPPORTED_VALUE 0x11
#define HCI_ERR_ILLEGAL_PARAMETER_FMT 0x12
#define HCI_ERR_CONN_TERM_BY_LOCAL_HOST 0x16
#define HCI_ERR_UNSPECIFIED 0x1F
#define HCI_ERR_UNIT_KEY_USED 0x26
#define HCI_ERR_QOS_REJECTED 0x2D
#define HCI_ERR_PARAM_OUT_OF_RANGE 0x30
#define HCI_ERR_NO_SUITABLE_CHANNEL 0x39
#define HCI_ERR_CHANNEL_MOVE 0xFF
/* AMP HCI ACL Data packet format */
typedef BWL_PRE_PACKED_STRUCT struct amp_hci_ACL_data {
uint16 handle; /* 12-bit connection handle + 2-bit PB and 2-bit BC flags */
uint16 dlen; /* data total length */
uint8 data[1];
} BWL_POST_PACKED_STRUCT amp_hci_ACL_data_t;
#define HCI_ACL_DATA_PREAMBLE_SIZE OFFSETOF(amp_hci_ACL_data_t, data)
#define HCI_ACL_DATA_BC_FLAGS (0x0 << 14)
#define HCI_ACL_DATA_PB_FLAGS (0x3 << 12)
#define HCI_ACL_DATA_HANDLE(handle) ((handle) & 0x0fff)
#define HCI_ACL_DATA_FLAGS(handle) ((handle) >> 12)
/* AMP Activity Report packet formats */
typedef BWL_PRE_PACKED_STRUCT struct amp_hci_activity_report {
uint8 ScheduleKnown;
uint8 NumReports;
uint8 data[1];
} BWL_POST_PACKED_STRUCT amp_hci_activity_report_t;
typedef BWL_PRE_PACKED_STRUCT struct amp_hci_activity_report_triple {
uint32 StartTime;
uint32 Duration;
uint32 Periodicity;
} BWL_POST_PACKED_STRUCT amp_hci_activity_report_triple_t;
#define HCI_AR_SCHEDULE_KNOWN 0x01
/* This marks the end of a packed structure section. */
#include <packed_section_end.h>
#endif /* _bt_amp_hci_h_ */

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/*
* 802.1x EAPOL definitions
*
* See
* IEEE Std 802.1X-2001
* IEEE 802.1X RADIUS Usage Guidelines
*
* Copyright (C) 2002 Broadcom Corporation
*
* $Id: eapol.h 241182 2011-02-17 21:50:03Z $
*/
#ifndef _eapol_h_
#define _eapol_h_
#ifndef _TYPEDEFS_H_
#include <typedefs.h>
#endif
/* This marks the start of a packed structure section. */
#include <packed_section_start.h>
#include <bcmcrypto/aeskeywrap.h>
/* EAPOL for 802.3/Ethernet */
typedef BWL_PRE_PACKED_STRUCT struct {
struct ether_header eth; /* 802.3/Ethernet header */
unsigned char version; /* EAPOL protocol version */
unsigned char type; /* EAPOL type */
unsigned short length; /* Length of body */
unsigned char body[1]; /* Body (optional) */
} BWL_POST_PACKED_STRUCT eapol_header_t;
#define EAPOL_HEADER_LEN 18
typedef struct {
unsigned char version; /* EAPOL protocol version */
unsigned char type; /* EAPOL type */
unsigned short length; /* Length of body */
} eapol_hdr_t;
#define EAPOL_HDR_LEN 4
/* EAPOL version */
#define WPA2_EAPOL_VERSION 2
#define WPA_EAPOL_VERSION 1
#define LEAP_EAPOL_VERSION 1
#define SES_EAPOL_VERSION 1
/* EAPOL types */
#define EAP_PACKET 0
#define EAPOL_START 1
#define EAPOL_LOGOFF 2
#define EAPOL_KEY 3
#define EAPOL_ASF 4
/* EAPOL-Key types */
#define EAPOL_RC4_KEY 1
#define EAPOL_WPA2_KEY 2 /* 802.11i/WPA2 */
#define EAPOL_WPA_KEY 254 /* WPA */
/* RC4 EAPOL-Key header field sizes */
#define EAPOL_KEY_REPLAY_LEN 8
#define EAPOL_KEY_IV_LEN 16
#define EAPOL_KEY_SIG_LEN 16
/* RC4 EAPOL-Key */
typedef BWL_PRE_PACKED_STRUCT struct {
unsigned char type; /* Key Descriptor Type */
unsigned short length; /* Key Length (unaligned) */
unsigned char replay[EAPOL_KEY_REPLAY_LEN]; /* Replay Counter */
unsigned char iv[EAPOL_KEY_IV_LEN]; /* Key IV */
unsigned char index; /* Key Flags & Index */
unsigned char signature[EAPOL_KEY_SIG_LEN]; /* Key Signature */
unsigned char key[1]; /* Key (optional) */
} BWL_POST_PACKED_STRUCT eapol_key_header_t;
#define EAPOL_KEY_HEADER_LEN 44
/* RC4 EAPOL-Key flags */
#define EAPOL_KEY_FLAGS_MASK 0x80
#define EAPOL_KEY_BROADCAST 0
#define EAPOL_KEY_UNICAST 0x80
/* RC4 EAPOL-Key index */
#define EAPOL_KEY_INDEX_MASK 0x7f
/* WPA/802.11i/WPA2 EAPOL-Key header field sizes */
#define EAPOL_WPA_KEY_REPLAY_LEN 8
#define EAPOL_WPA_KEY_NONCE_LEN 32
#define EAPOL_WPA_KEY_IV_LEN 16
#define EAPOL_WPA_KEY_RSC_LEN 8
#define EAPOL_WPA_KEY_ID_LEN 8
#define EAPOL_WPA_KEY_MIC_LEN 16
#define EAPOL_WPA_KEY_DATA_LEN (EAPOL_WPA_MAX_KEY_SIZE + AKW_BLOCK_LEN)
#define EAPOL_WPA_MAX_KEY_SIZE 32
/* WPA EAPOL-Key */
typedef BWL_PRE_PACKED_STRUCT struct {
unsigned char type; /* Key Descriptor Type */
unsigned short key_info; /* Key Information (unaligned) */
unsigned short key_len; /* Key Length (unaligned) */
unsigned char replay[EAPOL_WPA_KEY_REPLAY_LEN]; /* Replay Counter */
unsigned char nonce[EAPOL_WPA_KEY_NONCE_LEN]; /* Nonce */
unsigned char iv[EAPOL_WPA_KEY_IV_LEN]; /* Key IV */
unsigned char rsc[EAPOL_WPA_KEY_RSC_LEN]; /* Key RSC */
unsigned char id[EAPOL_WPA_KEY_ID_LEN]; /* WPA:Key ID, 802.11i/WPA2: Reserved */
unsigned char mic[EAPOL_WPA_KEY_MIC_LEN]; /* Key MIC */
unsigned short data_len; /* Key Data Length */
unsigned char data[EAPOL_WPA_KEY_DATA_LEN]; /* Key data */
} BWL_POST_PACKED_STRUCT eapol_wpa_key_header_t;
#define EAPOL_WPA_KEY_LEN 95
/* WPA/802.11i/WPA2 KEY KEY_INFO bits */
#define WPA_KEY_DESC_V1 0x01
#define WPA_KEY_DESC_V2 0x02
#define WPA_KEY_DESC_V3 0x03
#define WPA_KEY_PAIRWISE 0x08
#define WPA_KEY_INSTALL 0x40
#define WPA_KEY_ACK 0x80
#define WPA_KEY_MIC 0x100
#define WPA_KEY_SECURE 0x200
#define WPA_KEY_ERROR 0x400
#define WPA_KEY_REQ 0x800
#define WPA_KEY_DESC_V2_OR_V3 WPA_KEY_DESC_V2
/* WPA-only KEY KEY_INFO bits */
#define WPA_KEY_INDEX_0 0x00
#define WPA_KEY_INDEX_1 0x10
#define WPA_KEY_INDEX_2 0x20
#define WPA_KEY_INDEX_3 0x30
#define WPA_KEY_INDEX_MASK 0x30
#define WPA_KEY_INDEX_SHIFT 0x04
/* 802.11i/WPA2-only KEY KEY_INFO bits */
#define WPA_KEY_ENCRYPTED_DATA 0x1000
/* Key Data encapsulation */
typedef BWL_PRE_PACKED_STRUCT struct {
uint8 type;
uint8 length;
uint8 oui[3];
uint8 subtype;
uint8 data[1];
} BWL_POST_PACKED_STRUCT eapol_wpa2_encap_data_t;
#define EAPOL_WPA2_ENCAP_DATA_HDR_LEN 6
#define WPA2_KEY_DATA_SUBTYPE_GTK 1
#define WPA2_KEY_DATA_SUBTYPE_STAKEY 2
#define WPA2_KEY_DATA_SUBTYPE_MAC 3
#define WPA2_KEY_DATA_SUBTYPE_PMKID 4
#define WPA2_KEY_DATA_SUBTYPE_IGTK 9
/* GTK encapsulation */
typedef BWL_PRE_PACKED_STRUCT struct {
uint8 flags;
uint8 reserved;
uint8 gtk[EAPOL_WPA_MAX_KEY_SIZE];
} BWL_POST_PACKED_STRUCT eapol_wpa2_key_gtk_encap_t;
#define EAPOL_WPA2_KEY_GTK_ENCAP_HDR_LEN 2
#define WPA2_GTK_INDEX_MASK 0x03
#define WPA2_GTK_INDEX_SHIFT 0x00
#define WPA2_GTK_TRANSMIT 0x04
/* IGTK encapsulation */
typedef BWL_PRE_PACKED_STRUCT struct {
uint16 key_id;
uint8 ipn[6];
uint8 key[EAPOL_WPA_MAX_KEY_SIZE];
} BWL_POST_PACKED_STRUCT eapol_wpa2_key_igtk_encap_t;
#define EAPOL_WPA2_KEY_IGTK_ENCAP_HDR_LEN 8
/* STAKey encapsulation */
typedef BWL_PRE_PACKED_STRUCT struct {
uint8 reserved[2];
uint8 mac[ETHER_ADDR_LEN];
uint8 stakey[EAPOL_WPA_MAX_KEY_SIZE];
} BWL_POST_PACKED_STRUCT eapol_wpa2_key_stakey_encap_t;
#define WPA2_KEY_DATA_PAD 0xdd
/* This marks the end of a packed structure section. */
#include <packed_section_end.h>
#endif /* _eapol_h_ */

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/*
* From FreeBSD 2.2.7: Fundamental constants relating to ethernet.
*
* $Copyright Open Broadcom Corporation$
*
* $Id: ethernet.h 401759 2013-05-13 16:08:08Z sudhirbs $
*/
#ifndef _NET_ETHERNET_H_ /* use native BSD ethernet.h when available */
#define _NET_ETHERNET_H_
#ifndef _TYPEDEFS_H_
#include "typedefs.h"
#endif
/* This marks the start of a packed structure section. */
#include <packed_section_start.h>
/*
* The number of bytes in an ethernet (MAC) address.
*/
#define ETHER_ADDR_LEN 6
/*
* The number of bytes in the type field.
*/
#define ETHER_TYPE_LEN 2
/*
* The number of bytes in the trailing CRC field.
*/
#define ETHER_CRC_LEN 4
/*
* The length of the combined header.
*/
#define ETHER_HDR_LEN (ETHER_ADDR_LEN * 2 + ETHER_TYPE_LEN)
/*
* The minimum packet length.
*/
#define ETHER_MIN_LEN 64
/*
* The minimum packet user data length.
*/
#define ETHER_MIN_DATA 46
/*
* The maximum packet length.
*/
#define ETHER_MAX_LEN 1518
/*
* The maximum packet user data length.
*/
#define ETHER_MAX_DATA 1500
/* ether types */
#define ETHER_TYPE_MIN 0x0600 /* Anything less than MIN is a length */
#define ETHER_TYPE_IP 0x0800 /* IP */
#define ETHER_TYPE_ARP 0x0806 /* ARP */
#define ETHER_TYPE_8021Q 0x8100 /* 802.1Q */
#define ETHER_TYPE_IPV6 0x86dd /* IPv6 */
#define ETHER_TYPE_BRCM 0x886c /* Broadcom Corp. */
#define ETHER_TYPE_802_1X 0x888e /* 802.1x */
#ifdef PLC
#define ETHER_TYPE_88E1 0x88e1 /* GIGLE */
#define ETHER_TYPE_8912 0x8912 /* GIGLE */
#define ETHER_TYPE_GIGLED 0xffff /* GIGLE */
#endif /* PLC */
#define ETHER_TYPE_802_1X_PREAUTH 0x88c7 /* 802.1x preauthentication */
#define ETHER_TYPE_WAI 0x88b4 /* WAI */
#define ETHER_TYPE_89_0D 0x890d /* 89-0d frame for TDLS */
#define ETHER_TYPE_PPP_SES 0x8864 /* PPPoE Session */
#define ETHER_TYPE_IAPP_L2_UPDATE 0x6 /* IAPP L2 update frame */
/* Broadcom subtype follows ethertype; First 2 bytes are reserved; Next 2 are subtype; */
#define ETHER_BRCM_SUBTYPE_LEN 4 /* Broadcom 4 byte subtype */
/* ether header */
#define ETHER_DEST_OFFSET (0 * ETHER_ADDR_LEN) /* dest address offset */
#define ETHER_SRC_OFFSET (1 * ETHER_ADDR_LEN) /* src address offset */
#define ETHER_TYPE_OFFSET (2 * ETHER_ADDR_LEN) /* ether type offset */
/*
* A macro to validate a length with
*/
#define ETHER_IS_VALID_LEN(foo) \
((foo) >= ETHER_MIN_LEN && (foo) <= ETHER_MAX_LEN)
#define ETHER_FILL_MCAST_ADDR_FROM_IP(ea, mgrp_ip) { \
((uint8 *)ea)[0] = 0x01; \
((uint8 *)ea)[1] = 0x00; \
((uint8 *)ea)[2] = 0x5e; \
((uint8 *)ea)[3] = ((mgrp_ip) >> 16) & 0x7f; \
((uint8 *)ea)[4] = ((mgrp_ip) >> 8) & 0xff; \
((uint8 *)ea)[5] = ((mgrp_ip) >> 0) & 0xff; \
}
#ifndef __INCif_etherh /* Quick and ugly hack for VxWorks */
/*
* Structure of a 10Mb/s Ethernet header.
*/
BWL_PRE_PACKED_STRUCT struct ether_header {
uint8 ether_dhost[ETHER_ADDR_LEN];
uint8 ether_shost[ETHER_ADDR_LEN];
uint16 ether_type;
} BWL_POST_PACKED_STRUCT;
/*
* Structure of a 48-bit Ethernet address.
*/
BWL_PRE_PACKED_STRUCT struct ether_addr {
uint8 octet[ETHER_ADDR_LEN];
} BWL_POST_PACKED_STRUCT;
#elif defined(VX_BSD4_3) && VX_BSD4_3
/*
* Structure of a 48-bit Ethernet address.
*/
BWL_PRE_PACKED_STRUCT struct ether_addr {
uint8 octet[ETHER_ADDR_LEN];
} BWL_POST_PACKED_STRUCT;
#endif /* !__INCif_etherh Quick and ugly hack for VxWorks */
/*
* Takes a pointer, set, test, clear, toggle locally admininistered
* address bit in the 48-bit Ethernet address.
*/
#define ETHER_SET_LOCALADDR(ea) (((uint8 *)(ea))[0] = (((uint8 *)(ea))[0] | 2))
#define ETHER_IS_LOCALADDR(ea) (((uint8 *)(ea))[0] & 2)
#define ETHER_CLR_LOCALADDR(ea) (((uint8 *)(ea))[0] = (((uint8 *)(ea))[0] & 0xfd))
#define ETHER_TOGGLE_LOCALADDR(ea) (((uint8 *)(ea))[0] = (((uint8 *)(ea))[0] ^ 2))
/* Takes a pointer, marks unicast address bit in the MAC address */
#define ETHER_SET_UNICAST(ea) (((uint8 *)(ea))[0] = (((uint8 *)(ea))[0] & ~1))
/*
* Takes a pointer, returns true if a 48-bit multicast address
* (including broadcast, since it is all ones)
*/
#define ETHER_ISMULTI(ea) (((const uint8 *)(ea))[0] & 1)
/* compare two ethernet addresses - assumes the pointers can be referenced as shorts */
#define eacmp(a, b) ((((const uint16 *)(a))[0] ^ ((const uint16 *)(b))[0]) | \
(((const uint16 *)(a))[1] ^ ((const uint16 *)(b))[1]) | \
(((const uint16 *)(a))[2] ^ ((const uint16 *)(b))[2]))
#define ether_cmp(a, b) eacmp(a, b)
/* copy an ethernet address - assumes the pointers can be referenced as shorts */
#define eacopy(s, d) \
do { \
((uint16 *)(d))[0] = ((const uint16 *)(s))[0]; \
((uint16 *)(d))[1] = ((const uint16 *)(s))[1]; \
((uint16 *)(d))[2] = ((const uint16 *)(s))[2]; \
} while (0)
#define ether_copy(s, d) eacopy(s, d)
/* Copy an ethernet address in reverse order */
#define ether_rcopy(s, d) \
do { \
((uint16 *)(d))[2] = ((uint16 *)(s))[2]; \
((uint16 *)(d))[1] = ((uint16 *)(s))[1]; \
((uint16 *)(d))[0] = ((uint16 *)(s))[0]; \
} while (0)
#ifdef _HNDRTE_
/* Dongles use bcmutils functions instead of macros.
* Possibly slower but saves over 800 bytes off THUMB dongle image.
*/
extern const struct ether_addr ether_bcast;
extern const struct ether_addr ether_null;
extern const struct ether_addr ether_ipv6_mcast;
extern int ether_isbcast(const void *ea);
extern int ether_isnulladdr(const void *ea);
#define ETHER_ISBCAST(ea) ether_isbcast(ea)
#define ETHER_ISNULLADDR(ea) ether_isnulladdr(ea)
#else /* !_HNDRTE_ */
static const struct ether_addr ether_bcast = {{255, 255, 255, 255, 255, 255}};
static const struct ether_addr ether_null = {{0, 0, 0, 0, 0, 0}};
static const struct ether_addr ether_ipv6_mcast = {{0x33, 0x33, 0x00, 0x00, 0x00, 0x01}};
#define ETHER_ISBCAST(ea) ((((const uint8 *)(ea))[0] & \
((const uint8 *)(ea))[1] & \
((const uint8 *)(ea))[2] & \
((const uint8 *)(ea))[3] & \
((const uint8 *)(ea))[4] & \
((const uint8 *)(ea))[5]) == 0xff)
#define ETHER_ISNULLADDR(ea) ((((const uint8 *)(ea))[0] | \
((const uint8 *)(ea))[1] | \
((const uint8 *)(ea))[2] | \
((const uint8 *)(ea))[3] | \
((const uint8 *)(ea))[4] | \
((const uint8 *)(ea))[5]) == 0)
#endif /* !_HNDRTE_ */
#define ETHER_ISNULLDEST(da) ((((const uint16 *)(da))[0] | \
((const uint16 *)(da))[1] | \
((const uint16 *)(da))[2]) == 0)
#define ETHER_ISNULLSRC(sa) ETHER_ISNULLDEST(sa)
#define ETHER_MOVE_HDR(d, s) \
do { \
struct ether_header t; \
t = *(struct ether_header *)(s); \
*(struct ether_header *)(d) = t; \
} while (0)
#define ETHER_ISUCAST(ea) ((((uint8 *)(ea))[0] & 0x01) == 0)
/* This marks the end of a packed structure section. */
#include <packed_section_end.h>
#endif /* _NET_ETHERNET_H_ */

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/*
* $Copyright Open Broadcom Corporation$
*
* Fundamental types and constants relating to WFA P2P (aka WiFi Direct)
*
* $Id: p2p.h 338828 2012-06-14 17:24:45Z harveysm $
*/
#ifndef _P2P_H_
#define _P2P_H_
#ifndef _TYPEDEFS_H_
#include <typedefs.h>
#endif
#include <wlioctl.h>
#include <proto/802.11.h>
/* This marks the start of a packed structure section. */
#include <packed_section_start.h>
/* WiFi P2P OUI values */
#define P2P_OUI WFA_OUI /* WiFi P2P OUI */
#define P2P_VER WFA_OUI_TYPE_P2P /* P2P version: 9=WiFi P2P v1.0 */
#define P2P_IE_ID 0xdd /* P2P IE element ID */
/* WiFi P2P IE */
BWL_PRE_PACKED_STRUCT struct wifi_p2p_ie {
uint8 id; /* IE ID: 0xDD */
uint8 len; /* IE length */
uint8 OUI[3]; /* WiFi P2P specific OUI: P2P_OUI */
uint8 oui_type; /* Identifies P2P version: P2P_VER */
uint8 subelts[1]; /* variable length subelements */
} BWL_POST_PACKED_STRUCT;
typedef struct wifi_p2p_ie wifi_p2p_ie_t;
#define P2P_IE_FIXED_LEN 6
#define P2P_ATTR_ID_OFF 0
#define P2P_ATTR_LEN_OFF 1
#define P2P_ATTR_DATA_OFF 3
#define P2P_ATTR_HDR_LEN 3 /* ID + 2-byte length field spec 1.02 */
/* P2P IE Subelement IDs from WiFi P2P Technical Spec 1.00 */
#define P2P_SEID_STATUS 0 /* Status */
#define P2P_SEID_MINOR_RC 1 /* Minor Reason Code */
#define P2P_SEID_P2P_INFO 2 /* P2P Capability (capabilities info) */
#define P2P_SEID_DEV_ID 3 /* P2P Device ID */
#define P2P_SEID_INTENT 4 /* Group Owner Intent */
#define P2P_SEID_CFG_TIMEOUT 5 /* Configuration Timeout */
#define P2P_SEID_CHANNEL 6 /* Listen channel */
#define P2P_SEID_GRP_BSSID 7 /* P2P Group BSSID */
#define P2P_SEID_XT_TIMING 8 /* Extended Listen Timing */
#define P2P_SEID_INTINTADDR 9 /* Intended P2P Interface Address */
#define P2P_SEID_P2P_MGBTY 10 /* P2P Manageability */
#define P2P_SEID_CHAN_LIST 11 /* Channel List */
#define P2P_SEID_ABSENCE 12 /* Notice of Absence */
#define P2P_SEID_DEV_INFO 13 /* Device Info */
#define P2P_SEID_GROUP_INFO 14 /* Group Info */
#define P2P_SEID_GROUP_ID 15 /* Group ID */
#define P2P_SEID_P2P_IF 16 /* P2P Interface */
#define P2P_SEID_OP_CHANNEL 17 /* Operating channel */
#define P2P_SEID_INVITE_FLAGS 18 /* Invitation flags */
#define P2P_SEID_VNDR 221 /* Vendor-specific subelement */
#define P2P_SE_VS_ID_SERVICES 0x1b /* BRCM proprietary subel: L2 Services */
/* WiFi P2P IE subelement: P2P Capability (capabilities info) */
BWL_PRE_PACKED_STRUCT struct wifi_p2p_info_se_s {
uint8 eltId; /* SE ID: P2P_SEID_P2P_INFO */
uint8 len[2]; /* SE length not including eltId, len fields */
uint8 dev; /* Device Capability Bitmap */
uint8 group; /* Group Capability Bitmap */
} BWL_POST_PACKED_STRUCT;
typedef struct wifi_p2p_info_se_s wifi_p2p_info_se_t;
/* P2P Capability subelement's Device Capability Bitmap bit values */
#define P2P_CAPSE_DEV_SERVICE_DIS 0x1 /* Service Discovery */
#define P2P_CAPSE_DEV_CLIENT_DIS 0x2 /* Client Discoverability */
#define P2P_CAPSE_DEV_CONCURRENT 0x4 /* Concurrent Operation */
#define P2P_CAPSE_DEV_INFRA_MAN 0x8 /* P2P Infrastructure Managed */
#define P2P_CAPSE_DEV_LIMIT 0x10 /* P2P Device Limit */
#define P2P_CAPSE_INVITE_PROC 0x20 /* P2P Invitation Procedure */
/* P2P Capability subelement's Group Capability Bitmap bit values */
#define P2P_CAPSE_GRP_OWNER 0x1 /* P2P Group Owner */
#define P2P_CAPSE_PERSIST_GRP 0x2 /* Persistent P2P Group */
#define P2P_CAPSE_GRP_LIMIT 0x4 /* P2P Group Limit */
#define P2P_CAPSE_GRP_INTRA_BSS 0x8 /* Intra-BSS Distribution */
#define P2P_CAPSE_GRP_X_CONNECT 0x10 /* Cross Connection */
#define P2P_CAPSE_GRP_PERSISTENT 0x20 /* Persistent Reconnect */
#define P2P_CAPSE_GRP_FORMATION 0x40 /* Group Formation */
/* WiFi P2P IE subelement: Group Owner Intent */
BWL_PRE_PACKED_STRUCT struct wifi_p2p_intent_se_s {
uint8 eltId; /* SE ID: P2P_SEID_INTENT */
uint8 len[2]; /* SE length not including eltId, len fields */
uint8 intent; /* Intent Value 0...15 (0=legacy 15=master only) */
} BWL_POST_PACKED_STRUCT;
typedef struct wifi_p2p_intent_se_s wifi_p2p_intent_se_t;
/* WiFi P2P IE subelement: Configuration Timeout */
BWL_PRE_PACKED_STRUCT struct wifi_p2p_cfg_tmo_se_s {
uint8 eltId; /* SE ID: P2P_SEID_CFG_TIMEOUT */
uint8 len[2]; /* SE length not including eltId, len fields */
uint8 go_tmo; /* GO config timeout in units of 10 ms */
uint8 client_tmo; /* Client config timeout in units of 10 ms */
} BWL_POST_PACKED_STRUCT;
typedef struct wifi_p2p_cfg_tmo_se_s wifi_p2p_cfg_tmo_se_t;
/* WiFi P2P IE subelement: Status */
BWL_PRE_PACKED_STRUCT struct wifi_p2p_status_se_s {
uint8 eltId; /* SE ID: P2P_SEID_STATUS */
uint8 len[2]; /* SE length not including eltId, len fields */
uint8 status; /* Status Code: P2P_STATSE_* */
} BWL_POST_PACKED_STRUCT;
typedef struct wifi_p2p_status_se_s wifi_p2p_status_se_t;
/* Status subelement Status Code definitions */
#define P2P_STATSE_SUCCESS 0
/* Success */
#define P2P_STATSE_FAIL_INFO_CURR_UNAVAIL 1
/* Failed, information currently unavailable */
#define P2P_STATSE_PASSED_UP P2P_STATSE_FAIL_INFO_CURR_UNAVAIL
/* Old name for above in P2P spec 1.08 and older */
#define P2P_STATSE_FAIL_INCOMPAT_PARAMS 2
/* Failed, incompatible parameters */
#define P2P_STATSE_FAIL_LIMIT_REACHED 3
/* Failed, limit reached */
#define P2P_STATSE_FAIL_INVALID_PARAMS 4
/* Failed, invalid parameters */
#define P2P_STATSE_FAIL_UNABLE_TO_ACCOM 5
/* Failed, unable to accomodate request */
#define P2P_STATSE_FAIL_PROTO_ERROR 6
/* Failed, previous protocol error or disruptive behaviour */
#define P2P_STATSE_FAIL_NO_COMMON_CHAN 7
/* Failed, no common channels */
#define P2P_STATSE_FAIL_UNKNOWN_GROUP 8
/* Failed, unknown P2P Group */
#define P2P_STATSE_FAIL_INTENT 9
/* Failed, both peers indicated Intent 15 in GO Negotiation */
#define P2P_STATSE_FAIL_INCOMPAT_PROVIS 10
/* Failed, incompatible provisioning method */
#define P2P_STATSE_FAIL_USER_REJECT 11
/* Failed, rejected by user */
/* WiFi P2P IE attribute: Extended Listen Timing */
BWL_PRE_PACKED_STRUCT struct wifi_p2p_ext_se_s {
uint8 eltId; /* ID: P2P_SEID_EXT_TIMING */
uint8 len[2]; /* length not including eltId, len fields */
uint8 avail[2]; /* availibility period */
uint8 interval[2]; /* availibility interval */
} BWL_POST_PACKED_STRUCT;
typedef struct wifi_p2p_ext_se_s wifi_p2p_ext_se_t;
#define P2P_EXT_MIN 10 /* minimum 10ms */
/* WiFi P2P IE subelement: Intended P2P Interface Address */
BWL_PRE_PACKED_STRUCT struct wifi_p2p_intintad_se_s {
uint8 eltId; /* SE ID: P2P_SEID_INTINTADDR */
uint8 len[2]; /* SE length not including eltId, len fields */
uint8 mac[6]; /* intended P2P interface MAC address */
} BWL_POST_PACKED_STRUCT;
typedef struct wifi_p2p_intintad_se_s wifi_p2p_intintad_se_t;
/* WiFi P2P IE subelement: Channel */
BWL_PRE_PACKED_STRUCT struct wifi_p2p_channel_se_s {
uint8 eltId; /* SE ID: P2P_SEID_STATUS */
uint8 len[2]; /* SE length not including eltId, len fields */
uint8 band; /* Regulatory Class (band) */
uint8 channel; /* Channel */
} BWL_POST_PACKED_STRUCT;
typedef struct wifi_p2p_channel_se_s wifi_p2p_channel_se_t;
/* Channel Entry structure within the Channel List SE */
BWL_PRE_PACKED_STRUCT struct wifi_p2p_chanlist_entry_s {
uint8 band; /* Regulatory Class (band) */
uint8 num_channels; /* # of channels in the channel list */
uint8 channels[WL_NUMCHANNELS]; /* Channel List */
} BWL_POST_PACKED_STRUCT;
typedef struct wifi_p2p_chanlist_entry_s wifi_p2p_chanlist_entry_t;
#define WIFI_P2P_CHANLIST_SE_MAX_ENTRIES 2
/* WiFi P2P IE subelement: Channel List */
BWL_PRE_PACKED_STRUCT struct wifi_p2p_chanlist_se_s {
uint8 eltId; /* SE ID: P2P_SEID_STATUS */
uint8 len[2]; /* SE length not including eltId, len fields */
uint8 country[3]; /* Country String */
uint8 num_entries; /* # of channel entries */
wifi_p2p_chanlist_entry_t entries[WIFI_P2P_CHANLIST_SE_MAX_ENTRIES];
/* Channel Entry List */
} BWL_POST_PACKED_STRUCT;
typedef struct wifi_p2p_chanlist_se_s wifi_p2p_chanlist_se_t;
/* WiFi P2P IE's Device Info subelement */
BWL_PRE_PACKED_STRUCT struct wifi_p2p_devinfo_se_s {
uint8 eltId; /* SE ID: P2P_SEID_DEVINFO */
uint8 len[2]; /* SE length not including eltId, len fields */
uint8 mac[6]; /* P2P Device MAC address */
uint16 wps_cfg_meths; /* Config Methods: reg_prototlv.h WPS_CONFMET_* */
uint8 pri_devtype[8]; /* Primary Device Type */
} BWL_POST_PACKED_STRUCT;
typedef struct wifi_p2p_devinfo_se_s wifi_p2p_devinfo_se_t;
#define P2P_DEV_TYPE_LEN 8
/* WiFi P2P IE's Group Info subelement Client Info Descriptor */
BWL_PRE_PACKED_STRUCT struct wifi_p2p_cid_fixed_s {
uint8 len;
uint8 devaddr[ETHER_ADDR_LEN]; /* P2P Device Address */
uint8 ifaddr[ETHER_ADDR_LEN]; /* P2P Interface Address */
uint8 devcap; /* Device Capability */
uint8 cfg_meths[2]; /* Config Methods: reg_prototlv.h WPS_CONFMET_* */
uint8 pridt[P2P_DEV_TYPE_LEN]; /* Primary Device Type */
uint8 secdts; /* Number of Secondary Device Types */
} BWL_POST_PACKED_STRUCT;
typedef struct wifi_p2p_cid_fixed_s wifi_p2p_cid_fixed_t;
/* WiFi P2P IE's Device ID subelement */
BWL_PRE_PACKED_STRUCT struct wifi_p2p_devid_se_s {
uint8 eltId;
uint8 len[2];
struct ether_addr addr; /* P2P Device MAC address */
} BWL_POST_PACKED_STRUCT;
typedef struct wifi_p2p_devid_se_s wifi_p2p_devid_se_t;
/* WiFi P2P IE subelement: P2P Manageability */
BWL_PRE_PACKED_STRUCT struct wifi_p2p_mgbt_se_s {
uint8 eltId; /* SE ID: P2P_SEID_P2P_MGBTY */
uint8 len[2]; /* SE length not including eltId, len fields */
uint8 mg_bitmap; /* manageability bitmap */
} BWL_POST_PACKED_STRUCT;
typedef struct wifi_p2p_mgbt_se_s wifi_p2p_mgbt_se_t;
/* mg_bitmap field bit values */
#define P2P_MGBTSE_P2PDEVMGMT_FLAG 0x1 /* AP supports Managed P2P Device */
/* WiFi P2P IE subelement: Group Info */
BWL_PRE_PACKED_STRUCT struct wifi_p2p_grpinfo_se_s {
uint8 eltId; /* SE ID: P2P_SEID_GROUP_INFO */
uint8 len[2]; /* SE length not including eltId, len fields */
} BWL_POST_PACKED_STRUCT;
typedef struct wifi_p2p_grpinfo_se_s wifi_p2p_grpinfo_se_t;
/* WiFi P2P Action Frame */
BWL_PRE_PACKED_STRUCT struct wifi_p2p_action_frame {
uint8 category; /* P2P_AF_CATEGORY */
uint8 OUI[3]; /* OUI - P2P_OUI */
uint8 type; /* OUI Type - P2P_VER */
uint8 subtype; /* OUI Subtype - P2P_AF_* */
uint8 dialog_token; /* nonzero, identifies req/resp tranaction */
uint8 elts[1]; /* Variable length information elements. Max size =
* ACTION_FRAME_SIZE - sizeof(this structure) - 1
*/
} BWL_POST_PACKED_STRUCT;
typedef struct wifi_p2p_action_frame wifi_p2p_action_frame_t;
#define P2P_AF_CATEGORY 0x7f
#define P2P_AF_FIXED_LEN 7
/* WiFi P2P Action Frame OUI Subtypes */
#define P2P_AF_NOTICE_OF_ABSENCE 0 /* Notice of Absence */
#define P2P_AF_PRESENCE_REQ 1 /* P2P Presence Request */
#define P2P_AF_PRESENCE_RSP 2 /* P2P Presence Response */
#define P2P_AF_GO_DISC_REQ 3 /* GO Discoverability Request */
/* WiFi P2P Public Action Frame */
BWL_PRE_PACKED_STRUCT struct wifi_p2p_pub_act_frame {
uint8 category; /* P2P_PUB_AF_CATEGORY */
uint8 action; /* P2P_PUB_AF_ACTION */
uint8 oui[3]; /* P2P_OUI */
uint8 oui_type; /* OUI type - P2P_VER */
uint8 subtype; /* OUI subtype - P2P_TYPE_* */
uint8 dialog_token; /* nonzero, identifies req/rsp transaction */
uint8 elts[1]; /* Variable length information elements. Max size =
* ACTION_FRAME_SIZE - sizeof(this structure) - 1
*/
} BWL_POST_PACKED_STRUCT;
typedef struct wifi_p2p_pub_act_frame wifi_p2p_pub_act_frame_t;
#define P2P_PUB_AF_FIXED_LEN 8
#define P2P_PUB_AF_CATEGORY 0x04
#define P2P_PUB_AF_ACTION 0x09
/* WiFi P2P Public Action Frame OUI Subtypes */
#define P2P_PAF_GON_REQ 0 /* Group Owner Negotiation Req */
#define P2P_PAF_GON_RSP 1 /* Group Owner Negotiation Rsp */
#define P2P_PAF_GON_CONF 2 /* Group Owner Negotiation Confirm */
#define P2P_PAF_INVITE_REQ 3 /* P2P Invitation Request */
#define P2P_PAF_INVITE_RSP 4 /* P2P Invitation Response */
#define P2P_PAF_DEVDIS_REQ 5 /* Device Discoverability Request */
#define P2P_PAF_DEVDIS_RSP 6 /* Device Discoverability Response */
#define P2P_PAF_PROVDIS_REQ 7 /* Provision Discovery Request */
#define P2P_PAF_PROVDIS_RSP 8 /* Provision Discovery Request */
/* TODO: Stop using these obsolete aliases for P2P_PAF_GON_* */
#define P2P_TYPE_MNREQ P2P_PAF_GON_REQ
#define P2P_TYPE_MNRSP P2P_PAF_GON_RSP
#define P2P_TYPE_MNCONF P2P_PAF_GON_CONF
/* WiFi P2P IE subelement: Notice of Absence */
BWL_PRE_PACKED_STRUCT struct wifi_p2p_noa_desc {
uint8 cnt_type; /* Count/Type */
uint32 duration; /* Duration */
uint32 interval; /* Interval */
uint32 start; /* Start Time */
} BWL_POST_PACKED_STRUCT;
typedef struct wifi_p2p_noa_desc wifi_p2p_noa_desc_t;
BWL_PRE_PACKED_STRUCT struct wifi_p2p_noa_se {
uint8 eltId; /* Subelement ID */
uint8 len[2]; /* Length */
uint8 index; /* Index */
uint8 ops_ctw_parms; /* CTWindow and OppPS Parameters */
wifi_p2p_noa_desc_t desc[1]; /* Notice of Absence Descriptor(s) */
} BWL_POST_PACKED_STRUCT;
typedef struct wifi_p2p_noa_se wifi_p2p_noa_se_t;
#define P2P_NOA_SE_FIXED_LEN 5
/* cnt_type field values */
#define P2P_NOA_DESC_CNT_RESERVED 0 /* reserved and should not be used */
#define P2P_NOA_DESC_CNT_REPEAT 255 /* continuous schedule */
#define P2P_NOA_DESC_TYPE_PREFERRED 1 /* preferred values */
#define P2P_NOA_DESC_TYPE_ACCEPTABLE 2 /* acceptable limits */
/* ctw_ops_parms field values */
#define P2P_NOA_CTW_MASK 0x7f
#define P2P_NOA_OPS_MASK 0x80
#define P2P_NOA_OPS_SHIFT 7
#define P2P_CTW_MIN 10 /* minimum 10TU */
/*
* P2P Service Discovery related
*/
#define P2PSD_ACTION_CATEGORY 0x04
/* Public action frame */
#define P2PSD_ACTION_ID_GAS_IREQ 0x0a
/* Action value for GAS Initial Request AF */
#define P2PSD_ACTION_ID_GAS_IRESP 0x0b
/* Action value for GAS Initial Response AF */
#define P2PSD_ACTION_ID_GAS_CREQ 0x0c
/* Action value for GAS Comback Request AF */
#define P2PSD_ACTION_ID_GAS_CRESP 0x0d
/* Action value for GAS Comback Response AF */
#define P2PSD_AD_EID 0x6c
/* Advertisement Protocol IE ID */
#define P2PSD_ADP_TUPLE_QLMT_PAMEBI 0x00
/* Query Response Length Limit 7 bits plus PAME-BI 1 bit */
#define P2PSD_ADP_PROTO_ID 0x00
/* Advertisement Protocol ID. Always 0 for P2P SD */
#define P2PSD_GAS_OUI P2P_OUI
/* WFA OUI */
#define P2PSD_GAS_OUI_SUBTYPE P2P_VER
/* OUI Subtype for GAS IE */
#define P2PSD_GAS_NQP_INFOID 0xDDDD
/* NQP Query Info ID: 56797 */
#define P2PSD_GAS_COMEBACKDEALY 0x00
/* Not used in the Native GAS protocol */
/* Service Protocol Type */
typedef enum p2psd_svc_protype {
SVC_RPOTYPE_ALL = 0,
SVC_RPOTYPE_BONJOUR = 1,
SVC_RPOTYPE_UPNP = 2,
SVC_RPOTYPE_WSD = 3,
SVC_RPOTYPE_VENDOR = 255
} p2psd_svc_protype_t;
/* Service Discovery response status code */
typedef enum {
P2PSD_RESP_STATUS_SUCCESS = 0,
P2PSD_RESP_STATUS_PROTYPE_NA = 1,
P2PSD_RESP_STATUS_DATA_NA = 2,
P2PSD_RESP_STATUS_BAD_REQUEST = 3
} p2psd_resp_status_t;
/* Advertisement Protocol IE tuple field */
BWL_PRE_PACKED_STRUCT struct wifi_p2psd_adp_tpl {
uint8 llm_pamebi; /* Query Response Length Limit bit 0-6, set to 0 plus
* Pre-Associated Message Exchange BSSID Independent bit 7, set to 0
*/
uint8 adp_id; /* Advertisement Protocol ID: 0 for NQP Native Query Protocol */
} BWL_POST_PACKED_STRUCT;
typedef struct wifi_p2psd_adp_tpl wifi_p2psd_adp_tpl_t;
/* Advertisement Protocol IE */
BWL_PRE_PACKED_STRUCT struct wifi_p2psd_adp_ie {
uint8 id; /* IE ID: 0x6c - 108 */
uint8 len; /* IE length */
wifi_p2psd_adp_tpl_t adp_tpl; /* Advertisement Protocol Tuple field. Only one
* tuple is defined for P2P Service Discovery
*/
} BWL_POST_PACKED_STRUCT;
typedef struct wifi_p2psd_adp_ie wifi_p2psd_adp_ie_t;
/* NQP Vendor-specific Content */
BWL_PRE_PACKED_STRUCT struct wifi_p2psd_nqp_query_vsc {
uint8 oui_subtype; /* OUI Subtype: 0x09 */
uint16 svc_updi; /* Service Update Indicator */
uint8 svc_tlvs[1]; /* wifi_p2psd_qreq_tlv_t type for service request,
* wifi_p2psd_qresp_tlv_t type for service response
*/
} BWL_POST_PACKED_STRUCT;
typedef struct wifi_p2psd_nqp_query_vsc wifi_p2psd_nqp_query_vsc_t;
/* Service Request TLV */
BWL_PRE_PACKED_STRUCT struct wifi_p2psd_qreq_tlv {
uint16 len; /* Length: 5 plus size of Query Data */
uint8 svc_prot; /* Service Protocol Type */
uint8 svc_tscid; /* Service Transaction ID */
uint8 query_data[1]; /* Query Data, passed in from above Layer 2 */
} BWL_POST_PACKED_STRUCT;
typedef struct wifi_p2psd_qreq_tlv wifi_p2psd_qreq_tlv_t;
/* Query Request Frame, defined in generic format, instead of NQP specific */
BWL_PRE_PACKED_STRUCT struct wifi_p2psd_qreq_frame {
uint16 info_id; /* Info ID: 0xDDDD */
uint16 len; /* Length of service request TLV, 5 plus the size of request data */
uint8 oui[3]; /* WFA OUI: 0x0050F2 */
uint8 qreq_vsc[1]; /* Vendor-specific Content: wifi_p2psd_nqp_query_vsc_t type for NQP */
} BWL_POST_PACKED_STRUCT;
typedef struct wifi_p2psd_qreq_frame wifi_p2psd_qreq_frame_t;
/* GAS Initial Request AF body, "elts" in wifi_p2p_pub_act_frame */
BWL_PRE_PACKED_STRUCT struct wifi_p2psd_gas_ireq_frame {
wifi_p2psd_adp_ie_t adp_ie; /* Advertisement Protocol IE */
uint16 qreq_len; /* Query Request Length */
uint8 qreq_frm[1]; /* Query Request Frame wifi_p2psd_qreq_frame_t */
} BWL_POST_PACKED_STRUCT;
typedef struct wifi_p2psd_gas_ireq_frame wifi_p2psd_gas_ireq_frame_t;
/* Service Response TLV */
BWL_PRE_PACKED_STRUCT struct wifi_p2psd_qresp_tlv {
uint16 len; /* Length: 5 plus size of Query Data */
uint8 svc_prot; /* Service Protocol Type */
uint8 svc_tscid; /* Service Transaction ID */
uint8 status; /* Value defined in Table 57 of P2P spec. */
uint8 query_data[1]; /* Response Data, passed in from above Layer 2 */
} BWL_POST_PACKED_STRUCT;
typedef struct wifi_p2psd_qresp_tlv wifi_p2psd_qresp_tlv_t;
/* Query Response Frame, defined in generic format, instead of NQP specific */
BWL_PRE_PACKED_STRUCT struct wifi_p2psd_qresp_frame {
uint16 info_id; /* Info ID: 0xDDDD */
uint16 len; /* Lenth of service response TLV, 6 plus the size of resp data */
uint8 oui[3]; /* WFA OUI: 0x0050F2 */
uint8 qresp_vsc[1]; /* Vendor-specific Content: wifi_p2psd_qresp_tlv_t type for NQP */
} BWL_POST_PACKED_STRUCT;
typedef struct wifi_p2psd_qresp_frame wifi_p2psd_qresp_frame_t;
/* GAS Initial Response AF body, "elts" in wifi_p2p_pub_act_frame */
BWL_PRE_PACKED_STRUCT struct wifi_p2psd_gas_iresp_frame {
uint16 status; /* Value defined in Table 7-23 of IEEE P802.11u */
uint16 cb_delay; /* GAS Comeback Delay */
wifi_p2psd_adp_ie_t adp_ie; /* Advertisement Protocol IE */
uint16 qresp_len; /* Query Response Length */
uint8 qresp_frm[1]; /* Query Response Frame wifi_p2psd_qresp_frame_t */
} BWL_POST_PACKED_STRUCT;
typedef struct wifi_p2psd_gas_iresp_frame wifi_p2psd_gas_iresp_frame_t;
/* GAS Comeback Response AF body, "elts" in wifi_p2p_pub_act_frame */
BWL_PRE_PACKED_STRUCT struct wifi_p2psd_gas_cresp_frame {
uint16 status; /* Value defined in Table 7-23 of IEEE P802.11u */
uint8 fragment_id; /* Fragmentation ID */
uint16 cb_delay; /* GAS Comeback Delay */
wifi_p2psd_adp_ie_t adp_ie; /* Advertisement Protocol IE */
uint16 qresp_len; /* Query Response Length */
uint8 qresp_frm[1]; /* Query Response Frame wifi_p2psd_qresp_frame_t */
} BWL_POST_PACKED_STRUCT;
typedef struct wifi_p2psd_gas_cresp_frame wifi_p2psd_gas_cresp_frame_t;
/* Wi-Fi GAS Public Action Frame */
BWL_PRE_PACKED_STRUCT struct wifi_p2psd_gas_pub_act_frame {
uint8 category; /* 0x04 Public Action Frame */
uint8 action; /* 0x6c Advertisement Protocol */
uint8 dialog_token; /* nonzero, identifies req/rsp transaction */
uint8 query_data[1]; /* Query Data. wifi_p2psd_gas_ireq_frame_t
* or wifi_p2psd_gas_iresp_frame_t format
*/
} BWL_POST_PACKED_STRUCT;
typedef struct wifi_p2psd_gas_pub_act_frame wifi_p2psd_gas_pub_act_frame_t;
/* This marks the end of a packed structure section. */
#include <packed_section_end.h>
#endif /* _P2P_H_ */

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/*
* SD-SPI Protocol Standard
*
* $ Copyright Open Broadcom Corporation $
*
* $Id: sdspi.h 241182 2011-02-17 21:50:03Z $
*/
#ifndef _SD_SPI_H
#define _SD_SPI_H
#define SPI_START_M BITFIELD_MASK(1) /* Bit [31] - Start Bit */
#define SPI_START_S 31
#define SPI_DIR_M BITFIELD_MASK(1) /* Bit [30] - Direction */
#define SPI_DIR_S 30
#define SPI_CMD_INDEX_M BITFIELD_MASK(6) /* Bits [29:24] - Command number */
#define SPI_CMD_INDEX_S 24
#define SPI_RW_M BITFIELD_MASK(1) /* Bit [23] - Read=0, Write=1 */
#define SPI_RW_S 23
#define SPI_FUNC_M BITFIELD_MASK(3) /* Bits [22:20] - Function Number */
#define SPI_FUNC_S 20
#define SPI_RAW_M BITFIELD_MASK(1) /* Bit [19] - Read After Wr */
#define SPI_RAW_S 19
#define SPI_STUFF_M BITFIELD_MASK(1) /* Bit [18] - Stuff bit */
#define SPI_STUFF_S 18
#define SPI_BLKMODE_M BITFIELD_MASK(1) /* Bit [19] - Blockmode 1=blk */
#define SPI_BLKMODE_S 19
#define SPI_OPCODE_M BITFIELD_MASK(1) /* Bit [18] - OP Code */
#define SPI_OPCODE_S 18
#define SPI_ADDR_M BITFIELD_MASK(17) /* Bits [17:1] - Address */
#define SPI_ADDR_S 1
#define SPI_STUFF0_M BITFIELD_MASK(1) /* Bit [0] - Stuff bit */
#define SPI_STUFF0_S 0
#define SPI_RSP_START_M BITFIELD_MASK(1) /* Bit [7] - Start Bit (always 0) */
#define SPI_RSP_START_S 7
#define SPI_RSP_PARAM_ERR_M BITFIELD_MASK(1) /* Bit [6] - Parameter Error */
#define SPI_RSP_PARAM_ERR_S 6
#define SPI_RSP_RFU5_M BITFIELD_MASK(1) /* Bit [5] - RFU (Always 0) */
#define SPI_RSP_RFU5_S 5
#define SPI_RSP_FUNC_ERR_M BITFIELD_MASK(1) /* Bit [4] - Function number error */
#define SPI_RSP_FUNC_ERR_S 4
#define SPI_RSP_CRC_ERR_M BITFIELD_MASK(1) /* Bit [3] - COM CRC Error */
#define SPI_RSP_CRC_ERR_S 3
#define SPI_RSP_ILL_CMD_M BITFIELD_MASK(1) /* Bit [2] - Illegal Command error */
#define SPI_RSP_ILL_CMD_S 2
#define SPI_RSP_RFU1_M BITFIELD_MASK(1) /* Bit [1] - RFU (Always 0) */
#define SPI_RSP_RFU1_S 1
#define SPI_RSP_IDLE_M BITFIELD_MASK(1) /* Bit [0] - In idle state */
#define SPI_RSP_IDLE_S 0
/* SD-SPI Protocol Definitions */
#define SDSPI_COMMAND_LEN 6 /* Number of bytes in an SD command */
#define SDSPI_START_BLOCK 0xFE /* SD Start Block Token */
#define SDSPI_IDLE_PAD 0xFF /* SD-SPI idle value for MOSI */
#define SDSPI_START_BIT_MASK 0x80
#endif /* _SD_SPI_H */

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/*
* 802.1Q VLAN protocol definitions
*
* $Copyright Open Broadcom Corporation$
*
* $Id: vlan.h 352279 2012-08-22 07:21:57Z cylee $
*/
#ifndef _vlan_h_
#define _vlan_h_
#ifndef _TYPEDEFS_H_
#include <typedefs.h>
#endif
/* This marks the start of a packed structure section. */
#include <packed_section_start.h>
#ifndef VLAN_VID_MASK
#define VLAN_VID_MASK 0xfff /* low 12 bits are vlan id */
#endif
#define VLAN_CFI_SHIFT 12 /* canonical format indicator bit */
#define VLAN_PRI_SHIFT 13 /* user priority */
#define VLAN_PRI_MASK 7 /* 3 bits of priority */
#define VLAN_TPID_OFFSET 12 /* offset of tag protocol id field */
#define VLAN_TCI_OFFSET 14 /* offset of tag ctrl info field */
#define VLAN_TAG_LEN 4
#define VLAN_TAG_OFFSET (2 * ETHER_ADDR_LEN) /* offset in Ethernet II packet only */
#define VLAN_TPID 0x8100 /* VLAN ethertype/Tag Protocol ID */
struct vlan_header {
uint16 vlan_type; /* 0x8100 */
uint16 vlan_tag; /* priority, cfi and vid */
};
struct ethervlan_header {
uint8 ether_dhost[ETHER_ADDR_LEN];
uint8 ether_shost[ETHER_ADDR_LEN];
uint16 vlan_type; /* 0x8100 */
uint16 vlan_tag; /* priority, cfi and vid */
uint16 ether_type;
};
struct dot3_mac_llc_snapvlan_header {
uint8 ether_dhost[ETHER_ADDR_LEN]; /* dest mac */
uint8 ether_shost[ETHER_ADDR_LEN]; /* src mac */
uint16 length; /* frame length incl header */
uint8 dsap; /* always 0xAA */
uint8 ssap; /* always 0xAA */
uint8 ctl; /* always 0x03 */
uint8 oui[3]; /* RFC1042: 0x00 0x00 0x00
* Bridge-Tunnel: 0x00 0x00 0xF8
*/
uint16 vlan_type; /* 0x8100 */
uint16 vlan_tag; /* priority, cfi and vid */
uint16 ether_type; /* ethertype */
};
#define ETHERVLAN_HDR_LEN (ETHER_HDR_LEN + VLAN_TAG_LEN)
/* This marks the end of a packed structure section. */
#include <packed_section_end.h>
#define ETHERVLAN_MOVE_HDR(d, s) \
do { \
struct ethervlan_header t; \
t = *(struct ethervlan_header *)(s); \
*(struct ethervlan_header *)(d) = t; \
} while (0)
#endif /* _vlan_h_ */

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/*
* Fundamental types and constants relating to WPA
*
* $Copyright Open Broadcom Corporation$
*
* $Id: wpa.h 367468 2012-11-08 05:49:44Z cylee $
*/
#ifndef _proto_wpa_h_
#define _proto_wpa_h_
#include <typedefs.h>
#include <proto/ethernet.h>
/* This marks the start of a packed structure section. */
#include <packed_section_start.h>
/* Reason Codes */
/* 13 through 23 taken from IEEE Std 802.11i-2004 */
#define DOT11_RC_INVALID_WPA_IE 13 /* Invalid info. element */
#define DOT11_RC_MIC_FAILURE 14 /* Michael failure */
#define DOT11_RC_4WH_TIMEOUT 15 /* 4-way handshake timeout */
#define DOT11_RC_GTK_UPDATE_TIMEOUT 16 /* Group key update timeout */
#define DOT11_RC_WPA_IE_MISMATCH 17 /* WPA IE in 4-way handshake differs from
* (re-)assoc. request/probe response
*/
#define DOT11_RC_INVALID_MC_CIPHER 18 /* Invalid multicast cipher */
#define DOT11_RC_INVALID_UC_CIPHER 19 /* Invalid unicast cipher */
#define DOT11_RC_INVALID_AKMP 20 /* Invalid authenticated key management protocol */
#define DOT11_RC_BAD_WPA_VERSION 21 /* Unsupported WPA version */
#define DOT11_RC_INVALID_WPA_CAP 22 /* Invalid WPA IE capabilities */
#define DOT11_RC_8021X_AUTH_FAIL 23 /* 802.1X authentication failure */
#define WPA2_PMKID_LEN 16
/* WPA IE fixed portion */
typedef BWL_PRE_PACKED_STRUCT struct
{
uint8 tag; /* TAG */
uint8 length; /* TAG length */
uint8 oui[3]; /* IE OUI */
uint8 oui_type; /* OUI type */
BWL_PRE_PACKED_STRUCT struct {
uint8 low;
uint8 high;
} BWL_POST_PACKED_STRUCT version; /* IE version */
} BWL_POST_PACKED_STRUCT wpa_ie_fixed_t;
#define WPA_IE_OUITYPE_LEN 4
#define WPA_IE_FIXED_LEN 8
#define WPA_IE_TAG_FIXED_LEN 6
typedef BWL_PRE_PACKED_STRUCT struct {
uint8 tag; /* TAG */
uint8 length; /* TAG length */
BWL_PRE_PACKED_STRUCT struct {
uint8 low;
uint8 high;
} BWL_POST_PACKED_STRUCT version; /* IE version */
} BWL_POST_PACKED_STRUCT wpa_rsn_ie_fixed_t;
#define WPA_RSN_IE_FIXED_LEN 4
#define WPA_RSN_IE_TAG_FIXED_LEN 2
typedef uint8 wpa_pmkid_t[WPA2_PMKID_LEN];
/* WPA suite/multicast suite */
typedef BWL_PRE_PACKED_STRUCT struct
{
uint8 oui[3];
uint8 type;
} BWL_POST_PACKED_STRUCT wpa_suite_t, wpa_suite_mcast_t;
#define WPA_SUITE_LEN 4
/* WPA unicast suite list/key management suite list */
typedef BWL_PRE_PACKED_STRUCT struct
{
BWL_PRE_PACKED_STRUCT struct {
uint8 low;
uint8 high;
} BWL_POST_PACKED_STRUCT count;
wpa_suite_t list[1];
} BWL_POST_PACKED_STRUCT wpa_suite_ucast_t, wpa_suite_auth_key_mgmt_t;
#define WPA_IE_SUITE_COUNT_LEN 2
typedef BWL_PRE_PACKED_STRUCT struct
{
BWL_PRE_PACKED_STRUCT struct {
uint8 low;
uint8 high;
} BWL_POST_PACKED_STRUCT count;
wpa_pmkid_t list[1];
} BWL_POST_PACKED_STRUCT wpa_pmkid_list_t;
/* WPA cipher suites */
#define WPA_CIPHER_NONE 0 /* None */
#define WPA_CIPHER_WEP_40 1 /* WEP (40-bit) */
#define WPA_CIPHER_TKIP 2 /* TKIP: default for WPA */
#define WPA_CIPHER_AES_OCB 3 /* AES (OCB) */
#define WPA_CIPHER_AES_CCM 4 /* AES (CCM) */
#define WPA_CIPHER_WEP_104 5 /* WEP (104-bit) */
#define WPA_CIPHER_BIP 6 /* WEP (104-bit) */
#define WPA_CIPHER_TPK 7 /* Group addressed traffic not allowed */
#ifdef BCMCCX
#define WPA_CIPHER_CKIP 8 /* KP with no MIC */
#define WPA_CIPHER_CKIP_MMH 9 /* KP with MIC ("CKIP/MMH", "CKIP+CMIC") */
#define WPA_CIPHER_WEP_MMH 10 /* MIC with no KP ("WEP/MMH", "CMIC") */
#define IS_CCX_CIPHER(cipher) ((cipher) == WPA_CIPHER_CKIP || \
(cipher) == WPA_CIPHER_CKIP_MMH || \
(cipher) == WPA_CIPHER_WEP_MMH)
#endif
#ifdef BCMWAPI_WAI
#define WAPI_CIPHER_NONE WPA_CIPHER_NONE
#define WAPI_CIPHER_SMS4 11
#define WAPI_CSE_WPI_SMS4 1
#endif /* BCMWAPI_WAI */
#define IS_WPA_CIPHER(cipher) ((cipher) == WPA_CIPHER_NONE || \
(cipher) == WPA_CIPHER_WEP_40 || \
(cipher) == WPA_CIPHER_WEP_104 || \
(cipher) == WPA_CIPHER_TKIP || \
(cipher) == WPA_CIPHER_AES_OCB || \
(cipher) == WPA_CIPHER_AES_CCM || \
(cipher) == WPA_CIPHER_TPK)
#ifdef BCMWAPI_WAI
#define IS_WAPI_CIPHER(cipher) ((cipher) == WAPI_CIPHER_NONE || \
(cipher) == WAPI_CSE_WPI_SMS4)
/* convert WAPI_CSE_WPI_XXX to WAPI_CIPHER_XXX */
#define WAPI_CSE_WPI_2_CIPHER(cse) ((cse) == WAPI_CSE_WPI_SMS4 ? \
WAPI_CIPHER_SMS4 : WAPI_CIPHER_NONE)
#define WAPI_CIPHER_2_CSE_WPI(cipher) ((cipher) == WAPI_CIPHER_SMS4 ? \
WAPI_CSE_WPI_SMS4 : WAPI_CIPHER_NONE)
#endif /* BCMWAPI_WAI */
/* WPA TKIP countermeasures parameters */
#define WPA_TKIP_CM_DETECT 60 /* multiple MIC failure window (seconds) */
#define WPA_TKIP_CM_BLOCK 60 /* countermeasures active window (seconds) */
/* RSN IE defines */
#define RSN_CAP_LEN 2 /* Length of RSN capabilities field (2 octets) */
/* RSN Capabilities defined in 802.11i */
#define RSN_CAP_PREAUTH 0x0001
#define RSN_CAP_NOPAIRWISE 0x0002
#define RSN_CAP_PTK_REPLAY_CNTR_MASK 0x000C
#define RSN_CAP_PTK_REPLAY_CNTR_SHIFT 2
#define RSN_CAP_GTK_REPLAY_CNTR_MASK 0x0030
#define RSN_CAP_GTK_REPLAY_CNTR_SHIFT 4
#define RSN_CAP_1_REPLAY_CNTR 0
#define RSN_CAP_2_REPLAY_CNTRS 1
#define RSN_CAP_4_REPLAY_CNTRS 2
#define RSN_CAP_16_REPLAY_CNTRS 3
#define RSN_CAP_MFPR 0x0040
#define RSN_CAP_MFPC 0x0080
#define RSN_CAP_SPPC 0x0400
#define RSN_CAP_SPPR 0x0800
/* WPA capabilities defined in 802.11i */
#define WPA_CAP_4_REPLAY_CNTRS RSN_CAP_4_REPLAY_CNTRS
#define WPA_CAP_16_REPLAY_CNTRS RSN_CAP_16_REPLAY_CNTRS
#define WPA_CAP_REPLAY_CNTR_SHIFT RSN_CAP_PTK_REPLAY_CNTR_SHIFT
#define WPA_CAP_REPLAY_CNTR_MASK RSN_CAP_PTK_REPLAY_CNTR_MASK
/* WPA capabilities defined in 802.11zD9.0 */
#define WPA_CAP_PEER_KEY_ENABLE (0x1 << 1) /* bit 9 */
/* WPA Specific defines */
#define WPA_CAP_LEN RSN_CAP_LEN /* Length of RSN capabilities in RSN IE (2 octets) */
#define WPA_PMKID_CNT_LEN 2 /* Length of RSN PMKID count (2 octests) */
#define WPA_CAP_WPA2_PREAUTH RSN_CAP_PREAUTH
#define WPA2_PMKID_COUNT_LEN 2
#ifdef BCMWAPI_WAI
#define WAPI_CAP_PREAUTH RSN_CAP_PREAUTH
/* Other WAI definition */
#define WAPI_WAI_REQUEST 0x00F1
#define WAPI_UNICAST_REKEY 0x00F2
#define WAPI_STA_AGING 0x00F3
#define WAPI_MUTIL_REKEY 0x00F4
#define WAPI_STA_STATS 0x00F5
#define WAPI_USK_REKEY_COUNT 0x4000000 /* 0xA00000 */
#define WAPI_MSK_REKEY_COUNT 0x4000000 /* 0xA00000 */
#endif /* BCMWAPI_WAI */
/* This marks the end of a packed structure section. */
#include <packed_section_end.h>
#endif /* _proto_wpa_h_ */

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/*
* WPS IE definitions
*
* $Copyright Open Broadcom Corporation$
*
* $Id$
*/
#ifndef _WPS_
#define _WPS_
#ifdef __cplusplus
extern "C" {
#endif
/* Data Element Definitions */
#define WPS_ID_AP_CHANNEL 0x1001
#define WPS_ID_ASSOC_STATE 0x1002
#define WPS_ID_AUTH_TYPE 0x1003
#define WPS_ID_AUTH_TYPE_FLAGS 0x1004
#define WPS_ID_AUTHENTICATOR 0x1005
#define WPS_ID_CONFIG_METHODS 0x1008
#define WPS_ID_CONFIG_ERROR 0x1009
#define WPS_ID_CONF_URL4 0x100A
#define WPS_ID_CONF_URL6 0x100B
#define WPS_ID_CONN_TYPE 0x100C
#define WPS_ID_CONN_TYPE_FLAGS 0x100D
#define WPS_ID_CREDENTIAL 0x100E
#define WPS_ID_DEVICE_NAME 0x1011
#define WPS_ID_DEVICE_PWD_ID 0x1012
#define WPS_ID_E_HASH1 0x1014
#define WPS_ID_E_HASH2 0x1015
#define WPS_ID_E_SNONCE1 0x1016
#define WPS_ID_E_SNONCE2 0x1017
#define WPS_ID_ENCR_SETTINGS 0x1018
#define WPS_ID_ENCR_TYPE 0x100F
#define WPS_ID_ENCR_TYPE_FLAGS 0x1010
#define WPS_ID_ENROLLEE_NONCE 0x101A
#define WPS_ID_FEATURE_ID 0x101B
#define WPS_ID_IDENTITY 0x101C
#define WPS_ID_IDENTITY_PROOF 0x101D
#define WPS_ID_KEY_WRAP_AUTH 0x101E
#define WPS_ID_KEY_IDENTIFIER 0x101F
#define WPS_ID_MAC_ADDR 0x1020
#define WPS_ID_MANUFACTURER 0x1021
#define WPS_ID_MSG_TYPE 0x1022
#define WPS_ID_MODEL_NAME 0x1023
#define WPS_ID_MODEL_NUMBER 0x1024
#define WPS_ID_NW_INDEX 0x1026
#define WPS_ID_NW_KEY 0x1027
#define WPS_ID_NW_KEY_INDEX 0x1028
#define WPS_ID_NEW_DEVICE_NAME 0x1029
#define WPS_ID_NEW_PWD 0x102A
#define WPS_ID_OOB_DEV_PWD 0x102C
#define WPS_ID_OS_VERSION 0x102D
#define WPS_ID_POWER_LEVEL 0x102F
#define WPS_ID_PSK_CURRENT 0x1030
#define WPS_ID_PSK_MAX 0x1031
#define WPS_ID_PUBLIC_KEY 0x1032
#define WPS_ID_RADIO_ENABLED 0x1033
#define WPS_ID_REBOOT 0x1034
#define WPS_ID_REGISTRAR_CURRENT 0x1035
#define WPS_ID_REGISTRAR_ESTBLSHD 0x1036
#define WPS_ID_REGISTRAR_LIST 0x1037
#define WPS_ID_REGISTRAR_MAX 0x1038
#define WPS_ID_REGISTRAR_NONCE 0x1039
#define WPS_ID_REQ_TYPE 0x103A
#define WPS_ID_RESP_TYPE 0x103B
#define WPS_ID_RF_BAND 0x103C
#define WPS_ID_R_HASH1 0x103D
#define WPS_ID_R_HASH2 0x103E
#define WPS_ID_R_SNONCE1 0x103F
#define WPS_ID_R_SNONCE2 0x1040
#define WPS_ID_SEL_REGISTRAR 0x1041
#define WPS_ID_SERIAL_NUM 0x1042
#define WPS_ID_SC_STATE 0x1044
#define WPS_ID_SSID 0x1045
#define WPS_ID_TOT_NETWORKS 0x1046
#define WPS_ID_UUID_E 0x1047
#define WPS_ID_UUID_R 0x1048
#define WPS_ID_VENDOR_EXT 0x1049
#define WPS_ID_VERSION 0x104A
#define WPS_ID_X509_CERT_REQ 0x104B
#define WPS_ID_X509_CERT 0x104C
#define WPS_ID_EAP_IDENTITY 0x104D
#define WPS_ID_MSG_COUNTER 0x104E
#define WPS_ID_PUBKEY_HASH 0x104F
#define WPS_ID_REKEY_KEY 0x1050
#define WPS_ID_KEY_LIFETIME 0x1051
#define WPS_ID_PERM_CFG_METHODS 0x1052
#define WPS_ID_SEL_REG_CFG_METHODS 0x1053
#define WPS_ID_PRIM_DEV_TYPE 0x1054
#define WPS_ID_SEC_DEV_TYPE_LIST 0x1055
#define WPS_ID_PORTABLE_DEVICE 0x1056
#define WPS_ID_AP_SETUP_LOCKED 0x1057
#define WPS_ID_APP_LIST 0x1058
#define WPS_ID_EAP_TYPE 0x1059
#define WPS_ID_INIT_VECTOR 0x1060
#define WPS_ID_KEY_PROVIDED_AUTO 0x1061
#define WPS_ID_8021X_ENABLED 0x1062
#define WPS_ID_WEP_TRANSMIT_KEY 0x1064
#define WPS_ID_REQ_DEV_TYPE 0x106A
/* WSC 2.0, WFA Vendor Extension Subelements */
#define WFA_VENDOR_EXT_ID "\x00\x37\x2A"
#define WPS_WFA_SUBID_VERSION2 0x00
#define WPS_WFA_SUBID_AUTHORIZED_MACS 0x01
#define WPS_WFA_SUBID_NW_KEY_SHAREABLE 0x02
#define WPS_WFA_SUBID_REQ_TO_ENROLL 0x03
#define WPS_WFA_SUBID_SETTINGS_DELAY_TIME 0x04
/* WCN-NET Windows Rally Vertical Pairing Vendor Extensions */
#define MS_VENDOR_EXT_ID "\x00\x01\x37"
#define WPS_MS_ID_VPI 0x1001 /* Vertical Pairing Identifier TLV */
#define WPS_MS_ID_TRANSPORT_UUID 0x1002 /* Transport UUID TLV */
/* Vertical Pairing Identifier TLV Definitions */
#define WPS_MS_VPI_TRANSPORT_NONE 0x00 /* None */
#define WPS_MS_VPI_TRANSPORT_DPWS 0x01 /* Devices Profile for Web Services */
#define WPS_MS_VPI_TRANSPORT_UPNP 0x02 /* uPnP */
#define WPS_MS_VPI_TRANSPORT_SDNWS 0x03 /* Secure Devices Profile for Web Services */
#define WPS_MS_VPI_NO_PROFILE_REQ 0x00 /* Wi-Fi profile not requested.
* Not supported in Windows 7
*/
#define WPS_MS_VPI_PROFILE_REQ 0x01 /* Wi-Fi profile requested. */
/* sizes of the fixed size elements */
#define WPS_ID_AP_CHANNEL_S 2
#define WPS_ID_ASSOC_STATE_S 2
#define WPS_ID_AUTH_TYPE_S 2
#define WPS_ID_AUTH_TYPE_FLAGS_S 2
#define WPS_ID_AUTHENTICATOR_S 8
#define WPS_ID_CONFIG_METHODS_S 2
#define WPS_ID_CONFIG_ERROR_S 2
#define WPS_ID_CONN_TYPE_S 1
#define WPS_ID_CONN_TYPE_FLAGS_S 1
#define WPS_ID_DEVICE_PWD_ID_S 2
#define WPS_ID_ENCR_TYPE_S 2
#define WPS_ID_ENCR_TYPE_FLAGS_S 2
#define WPS_ID_FEATURE_ID_S 4
#define WPS_ID_MAC_ADDR_S 6
#define WPS_ID_MSG_TYPE_S 1
#define WPS_ID_SC_STATE_S 1
#define WPS_ID_RF_BAND_S 1
#define WPS_ID_OS_VERSION_S 4
#define WPS_ID_VERSION_S 1
#define WPS_ID_SEL_REGISTRAR_S 1
#define WPS_ID_SEL_REG_CFG_METHODS_S 2
#define WPS_ID_REQ_TYPE_S 1
#define WPS_ID_RESP_TYPE_S 1
#define WPS_ID_AP_SETUP_LOCKED_S 1
/* WSC 2.0, WFA Vendor Extension Subelements */
#define WPS_WFA_SUBID_VERSION2_S 1
#define WPS_WFA_SUBID_NW_KEY_SHAREABLE_S 1
#define WPS_WFA_SUBID_REQ_TO_ENROLL_S 1
#define WPS_WFA_SUBID_SETTINGS_DELAY_TIME_S 1
/* Association states */
#define WPS_ASSOC_NOT_ASSOCIATED 0
#define WPS_ASSOC_CONN_SUCCESS 1
#define WPS_ASSOC_CONFIG_FAIL 2
#define WPS_ASSOC_ASSOC_FAIL 3
#define WPS_ASSOC_IP_FAIL 4
/* Authentication types */
#define WPS_AUTHTYPE_OPEN 0x0001
#define WPS_AUTHTYPE_WPAPSK 0x0002 /* Deprecated in WSC 2.0 */
#define WPS_AUTHTYPE_SHARED 0x0004 /* Deprecated in WSC 2.0 */
#define WPS_AUTHTYPE_WPA 0x0008 /* Deprecated in WSC 2.0 */
#define WPS_AUTHTYPE_WPA2 0x0010
#define WPS_AUTHTYPE_WPA2PSK 0x0020
/* Config methods */
#define WPS_CONFMET_USBA 0x0001 /* Deprecated in WSC 2.0 */
#define WPS_CONFMET_ETHERNET 0x0002 /* Deprecated in WSC 2.0 */
#define WPS_CONFMET_LABEL 0x0004
#define WPS_CONFMET_DISPLAY 0x0008
#define WPS_CONFMET_EXT_NFC_TOK 0x0010
#define WPS_CONFMET_INT_NFC_TOK 0x0020
#define WPS_CONFMET_NFC_INTF 0x0040
#define WPS_CONFMET_PBC 0x0080
#define WPS_CONFMET_KEYPAD 0x0100
/* WSC 2.0 */
#define WPS_CONFMET_VIRT_PBC 0x0280
#define WPS_CONFMET_PHY_PBC 0x0480
#define WPS_CONFMET_VIRT_DISPLAY 0x2008
#define WPS_CONFMET_PHY_DISPLAY 0x4008
/* WPS error messages */
#define WPS_ERROR_NO_ERROR 0
#define WPS_ERROR_OOB_INT_READ_ERR 1
#define WPS_ERROR_DECRYPT_CRC_FAIL 2
#define WPS_ERROR_CHAN24_NOT_SUPP 3
#define WPS_ERROR_CHAN50_NOT_SUPP 4
#define WPS_ERROR_SIGNAL_WEAK 5 /* Deprecated in WSC 2.0 */
#define WPS_ERROR_NW_AUTH_FAIL 6 /* Deprecated in WSC 2.0 */
#define WPS_ERROR_NW_ASSOC_FAIL 7 /* Deprecated in WSC 2.0 */
#define WPS_ERROR_NO_DHCP_RESP 8 /* Deprecated in WSC 2.0 */
#define WPS_ERROR_FAILED_DHCP_CONF 9 /* Deprecated in WSC 2.0 */
#define WPS_ERROR_IP_ADDR_CONFLICT 10 /* Deprecated in WSC 2.0 */
#define WPS_ERROR_FAIL_CONN_REGISTRAR 11
#define WPS_ERROR_MULTI_PBC_DETECTED 12
#define WPS_ERROR_ROGUE_SUSPECTED 13
#define WPS_ERROR_DEVICE_BUSY 14
#define WPS_ERROR_SETUP_LOCKED 15
#define WPS_ERROR_MSG_TIMEOUT 16 /* Deprecated in WSC 2.0 */
#define WPS_ERROR_REG_SESSION_TIMEOUT 17 /* Deprecated in WSC 2.0 */
#define WPS_ERROR_DEV_PWD_AUTH_FAIL 18
/* Connection types */
#define WPS_CONNTYPE_ESS 0x01
#define WPS_CONNTYPE_IBSS 0x02
/* Device password ID */
#define WPS_DEVICEPWDID_DEFAULT 0x0000
#define WPS_DEVICEPWDID_USER_SPEC 0x0001
#define WPS_DEVICEPWDID_MACHINE_SPEC 0x0002
#define WPS_DEVICEPWDID_REKEY 0x0003
#define WPS_DEVICEPWDID_PUSH_BTN 0x0004
#define WPS_DEVICEPWDID_REG_SPEC 0x0005
/* Encryption type */
#define WPS_ENCRTYPE_NONE 0x0001
#define WPS_ENCRTYPE_WEP 0x0002 /* Deprecated in WSC 2.0 */
#define WPS_ENCRTYPE_TKIP 0x0004 /* Deprecated in version 2.0. TKIP can only
* be advertised on the AP when Mixed Mode
* is enabled (Encryption Type is 0x000c).
*/
#define WPS_ENCRTYPE_AES 0x0008
/* WPS Message Types */
#define WPS_ID_BEACON 0x01
#define WPS_ID_PROBE_REQ 0x02
#define WPS_ID_PROBE_RESP 0x03
#define WPS_ID_MESSAGE_M1 0x04
#define WPS_ID_MESSAGE_M2 0x05
#define WPS_ID_MESSAGE_M2D 0x06
#define WPS_ID_MESSAGE_M3 0x07
#define WPS_ID_MESSAGE_M4 0x08
#define WPS_ID_MESSAGE_M5 0x09
#define WPS_ID_MESSAGE_M6 0x0A
#define WPS_ID_MESSAGE_M7 0x0B
#define WPS_ID_MESSAGE_M8 0x0C
#define WPS_ID_MESSAGE_ACK 0x0D
#define WPS_ID_MESSAGE_NACK 0x0E
#define WPS_ID_MESSAGE_DONE 0x0F
/* WSP private ID for local use */
#define WPS_PRIVATE_ID_IDENTITY (WPS_ID_MESSAGE_DONE + 1)
#define WPS_PRIVATE_ID_WPS_START (WPS_ID_MESSAGE_DONE + 2)
#define WPS_PRIVATE_ID_FAILURE (WPS_ID_MESSAGE_DONE + 3)
#define WPS_PRIVATE_ID_FRAG (WPS_ID_MESSAGE_DONE + 4)
#define WPS_PRIVATE_ID_FRAG_ACK (WPS_ID_MESSAGE_DONE + 5)
#define WPS_PRIVATE_ID_EAPOL_START (WPS_ID_MESSAGE_DONE + 6)
/* Device Type categories for primary and secondary device types */
#define WPS_DEVICE_TYPE_CAT_COMPUTER 1
#define WPS_DEVICE_TYPE_CAT_INPUT_DEVICE 2
#define WPS_DEVICE_TYPE_CAT_PRINTER 3
#define WPS_DEVICE_TYPE_CAT_CAMERA 4
#define WPS_DEVICE_TYPE_CAT_STORAGE 5
#define WPS_DEVICE_TYPE_CAT_NW_INFRA 6
#define WPS_DEVICE_TYPE_CAT_DISPLAYS 7
#define WPS_DEVICE_TYPE_CAT_MM_DEVICES 8
#define WPS_DEVICE_TYPE_CAT_GAME_DEVICES 9
#define WPS_DEVICE_TYPE_CAT_TELEPHONE 10
#define WPS_DEVICE_TYPE_CAT_AUDIO_DEVICES 11 /* WSC 2.0 */
/* Device Type sub categories for primary and secondary device types */
#define WPS_DEVICE_TYPE_SUB_CAT_COMP_PC 1
#define WPS_DEVICE_TYPE_SUB_CAT_COMP_SERVER 2
#define WPS_DEVICE_TYPE_SUB_CAT_COMP_MEDIA_CTR 3
#define WPS_DEVICE_TYPE_SUB_CAT_COMP_UM_PC 4 /* WSC 2.0 */
#define WPS_DEVICE_TYPE_SUB_CAT_COMP_NOTEBOOK 5 /* WSC 2.0 */
#define WPS_DEVICE_TYPE_SUB_CAT_COMP_DESKTOP 6 /* WSC 2.0 */
#define WPS_DEVICE_TYPE_SUB_CAT_COMP_MID 7 /* WSC 2.0 */
#define WPS_DEVICE_TYPE_SUB_CAT_COMP_NETBOOK 8 /* WSC 2.0 */
#define WPS_DEVICE_TYPE_SUB_CAT_INP_Keyboard 1 /* WSC 2.0 */
#define WPS_DEVICE_TYPE_SUB_CAT_INP_MOUSE 2 /* WSC 2.0 */
#define WPS_DEVICE_TYPE_SUB_CAT_INP_JOYSTICK 3 /* WSC 2.0 */
#define WPS_DEVICE_TYPE_SUB_CAT_INP_TRACKBALL 4 /* WSC 2.0 */
#define WPS_DEVICE_TYPE_SUB_CAT_INP_GAM_CTRL 5 /* WSC 2.0 */
#define WPS_DEVICE_TYPE_SUB_CAT_INP_REMOTE 6 /* WSC 2.0 */
#define WPS_DEVICE_TYPE_SUB_CAT_INP_TOUCHSCREEN 7 /* WSC 2.0 */
#define WPS_DEVICE_TYPE_SUB_CAT_INP_BIO_READER 8 /* WSC 2.0 */
#define WPS_DEVICE_TYPE_SUB_CAT_INP_BAR_READER 9 /* WSC 2.0 */
#define WPS_DEVICE_TYPE_SUB_CAT_PRTR_PRINTER 1
#define WPS_DEVICE_TYPE_SUB_CAT_PRTR_SCANNER 2
#define WPS_DEVICE_TYPE_SUB_CAT_PRTR_FAX 3 /* WSC 2.0 */
#define WPS_DEVICE_TYPE_SUB_CAT_PRTR_COPIER 4 /* WSC 2.0 */
#define WPS_DEVICE_TYPE_SUB_CAT_PRTR_ALLINONE 5 /* WSC 2.0 */
#define WPS_DEVICE_TYPE_SUB_CAT_CAM_DGTL_STILL 1
#define WPS_DEVICE_TYPE_SUB_CAT_CAM_VIDEO_CAM 2 /* WSC 2.0 */
#define WPS_DEVICE_TYPE_SUB_CAT_CAM_WEB_CAM 3 /* WSC 2.0 */
#define WPS_DEVICE_TYPE_SUB_CAT_CAM_SECU_CAM 4 /* WSC 2.0 */
#define WPS_DEVICE_TYPE_SUB_CAT_STOR_NAS 1
#define WPS_DEVICE_TYPE_SUB_CAT_NW_AP 1
#define WPS_DEVICE_TYPE_SUB_CAT_NW_ROUTER 2
#define WPS_DEVICE_TYPE_SUB_CAT_NW_SWITCH 3
#define WPS_DEVICE_TYPE_SUB_CAT_NW_GATEWAY 4 /* WSC 2.0 */
#define WPS_DEVICE_TYPE_SUB_CAT_NW_BRIDGE 5 /* WSC 2.0 */
#define WPS_DEVICE_TYPE_SUB_CAT_DISP_TV 1
#define WPS_DEVICE_TYPE_SUB_CAT_DISP_PIC_FRAME 2
#define WPS_DEVICE_TYPE_SUB_CAT_DISP_PROJECTOR 3
#define WPS_DEVICE_TYPE_SUB_CAT_DISP_MONITOR 4 /* WSC 2.0 */
#define WPS_DEVICE_TYPE_SUB_CAT_MM_DAR 1
#define WPS_DEVICE_TYPE_SUB_CAT_MM_PVR 2
#define WPS_DEVICE_TYPE_SUB_CAT_MM_MCX 3
#define WPS_DEVICE_TYPE_SUB_CAT_MM_STB 4 /* WSC 2.0 */
#define WPS_DEVICE_TYPE_SUB_CAT_MM_MS_ME 5 /* WSC 2.0 */
#define WPS_DEVICE_TYPE_SUB_CAT_MM_PVP 6 /* WSC 2.0 */
#define WPS_DEVICE_TYPE_SUB_CAT_GAM_XBOX 1
#define WPS_DEVICE_TYPE_SUB_CAT_GAM_XBOX_360 2
#define WPS_DEVICE_TYPE_SUB_CAT_GAM_PS 3
#define WPS_DEVICE_TYPE_SUB_CAT_GAM_GC 4 /* WSC 2.0 */
#define WPS_DEVICE_TYPE_SUB_CAT_GAM_PGD 5 /* WSC 2.0 */
#define WPS_DEVICE_TYPE_SUB_CAT_PHONE_WM 1
#define WPS_DEVICE_TYPE_SUB_CAT_PHONE_PSM 2 /* WSC 2.0 */
#define WPS_DEVICE_TYPE_SUB_CAT_PHONE_PDM 3 /* WSC 2.0 */
#define WPS_DEVICE_TYPE_SUB_CAT_PHONE_SSM 4 /* WSC 2.0 */
#define WPS_DEVICE_TYPE_SUB_CAT_PHONE_SDM 5 /* WSC 2.0 */
#define WPS_DEVICE_TYPE_SUB_CAT_AUDIO_TUNER 1 /* WSC 2.0 */
#define WPS_DEVICE_TYPE_SUB_CAT_AUDIO_SPEAKERS 2 /* WSC 2.0 */
#define WPS_DEVICE_TYPE_SUB_CAT_AUDIO_PMP 3 /* WSC 2.0 */
#define WPS_DEVICE_TYPE_SUB_CAT_AUDIO_HEADSET 4 /* WSC 2.0 */
#define WPS_DEVICE_TYPE_SUB_CAT_AUDIO_HPHONE 5 /* WSC 2.0 */
#define WPS_DEVICE_TYPE_SUB_CAT_AUDIO_MPHONE 6 /* WSC 2.0 */
#define WPS_DEVICE_TYPE_SUB_CAT_AUDIO_HTS 7 /* WSC 2.0 */
/* Device request/response type */
#define WPS_MSGTYPE_ENROLLEE_INFO_ONLY 0x00
#define WPS_MSGTYPE_ENROLLEE_OPEN_8021X 0x01
#define WPS_MSGTYPE_REGISTRAR 0x02
#define WPS_MSGTYPE_AP_WLAN_MGR 0x03
/* RF Band */
#define WPS_RFBAND_24GHZ 0x01
#define WPS_RFBAND_50GHZ 0x02
/* Simple Config state */
#define WPS_SCSTATE_UNCONFIGURED 0x01
#define WPS_SCSTATE_CONFIGURED 0x02
#define WPS_SCSTATE_OFF 11
/* WPS Vendor extension key */
#define WPS_OUI_HEADER_LEN 2
#define WPS_OUI_HEADER_SIZE 4
#define WPS_OUI_FIXED_HEADER_OFF 16
#define WPS_WFA_SUBID_V2_OFF 3
#define WPS_WFA_V2_OFF 5
#ifdef __cplusplus
}
#endif
#endif /* _WPS_ */

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/*
* RWL definitions of
* Broadcom 802.11bang Networking Device Driver
*
* $ Copyright Broadcom Corporation $
*
* $Id: rwl_wifi.h 393460 2013-03-27 19:43:28Z fengwang $
*
*/
#ifndef _rwl_wifi_h_
#define _rwl_wifi_h_
#if defined(RWL_WIFI) || defined(WIFI_REFLECTOR) || defined(RFAWARE)
#define RWL_ACTION_WIFI_CATEGORY 127 /* Vendor-specific category value for WiFi */
#define RWL_WIFI_OUI_BYTE0 0x00 /* BRCM-specific public OUI */
#define RWL_WIFI_OUI_BYTE1 0x90
#define RWL_WIFI_OUI_BYTE2 0x4c
#define RWL_WIFI_ACTION_FRAME_SIZE sizeof(struct dot11_action_wifi_vendor_specific)
/*
* Information about the action frame data fields in the dot11_action_wifi_vendor_specific
* cdc structure (1 to 16). This does not include the status flag. Since this
* is not directly visible to the driver code, we can't use sizeof(struct cdc_ioctl).
* Hence Ref MAC address offset starts from byte 17.
* REF MAC ADDR (6 bytes (MAC Address len) from byte 17 to 22)
* DUT MAC ADDR (6 bytes after the REF MAC Address byte 23 to 28)
* unused (byte 29 to 49)
* REF/Client Channel offset (50)
* DUT/Server channel offset (51)
* ---------------------------------------------------------------------------------------
* cdc struct|REF MAC ADDR|DUT_MAC_ADDR|un used|REF Channel|DUT channel|Action frame Data|
* 1---------17-----------23-------------------50----------51----------52----------------1040
* REF MAC addr after CDC struct without status flag (status flag not used by wifi)
*/
#define RWL_REF_MAC_ADDRESS_OFFSET 17
#define RWL_DUT_MAC_ADDRESS_OFFSET 23
#define RWL_WIFI_CLIENT_CHANNEL_OFFSET 50
#define RWL_WIFI_SERVER_CHANNEL_OFFSET 51
#ifdef WIFI_REFLECTOR
#include <bcmcdc.h>
#define REMOTE_FINDSERVER_CMD 16
#define RWL_WIFI_ACTION_CMD "wifiaction"
#define RWL_WIFI_ACTION_CMD_LEN 11 /* With the NULL terminator */
#define REMOTE_SET_CMD 1
#define REMOTE_GET_CMD 2
#define REMOTE_REPLY 4
#define RWL_WIFI_DEFAULT_TYPE 0x00
#define RWL_WIFI_DEFAULT_SUBTYPE 0x00
#define RWL_ACTION_FRAME_DATA_SIZE 1024 /* fixed size for the wifi frame data */
#define RWL_WIFI_CDC_HEADER_OFFSET 0
#define RWL_WIFI_FRAG_DATA_SIZE 960 /* max size of the frag data */
#define RWL_DEFAULT_WIFI_FRAG_COUNT 127 /* maximum fragment count */
#define RWL_WIFI_RETRY 5 /* CMD retry count for wifi */
#define RWL_WIFI_SEND 5 /* WIFI frame sent count */
#define RWL_WIFI_SEND_DELAY 100 /* delay between two frames */
#define MICROSEC_CONVERTOR_VAL 1000
#ifndef IFNAMSIZ
#define IFNAMSIZ 16
#endif
typedef struct rem_packet {
rem_ioctl_t rem_cdc;
uchar message [RWL_ACTION_FRAME_DATA_SIZE];
} rem_packet_t;
struct send_packet {
char command [RWL_WIFI_ACTION_CMD_LEN];
dot11_action_wifi_vendor_specific_t response;
} PACKED;
typedef struct send_packet send_packet_t;
#define REMOTE_SIZE sizeof(rem_ioctl_t)
#endif /* WIFI_REFLECTOR */
typedef struct rwl_request {
struct rwl_request* next_request;
struct dot11_action_wifi_vendor_specific action_frame;
} rwl_request_t;
#endif /* defined(RWL_WIFI) || defined(WIFI_REFLECTOR) */
#endif /* _rwl_wifi_h_ */

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/*
* Header file for save-restore functionality in driver
*
* Copyright (C) 2012, Broadcom Corporation
* All Rights Reserved.
*
* This is UNPUBLISHED PROPRIETARY SOURCE CODE of Broadcom Corporation;
* the contents of this file may not be disclosed to third parties, copied
* or duplicated in any form, in whole or in part, without the prior
* written permission of Broadcom Corporation.
*
* $Id: Exp $
*/
#ifndef _SAVERESTORE_H
#define _SAVERESTORE_H
/* WL_ENAB_RUNTIME_CHECK may be set based upon the #define below (for ROM builds). It may also
* be defined via makefiles (e.g. ROM auto abandon unoptimized compiles).
*/
#if defined(BCMROMBUILD)
#ifndef WL_ENAB_RUNTIME_CHECK
#define WL_ENAB_RUNTIME_CHECK
#endif
#endif /* BCMROMBUILD */
/* SAVERESTORE Support */
#ifdef SAVERESTORE
extern bool _sr;
#if defined(WL_ENAB_RUNTIME_CHECK) || !defined(DONGLEBUILD)
#define SR_ENAB() (_sr)
#elif defined(SAVERESTORE_DISABLED)
#define SR_ENAB() (0)
#else
#define SR_ENAB() (1)
#endif
#else
#define SR_ENAB() (0)
#endif /* SAVERESTORE */
/* BANK size is calculated in the units of 32bit WORDS */
#define SRCTL_BANK_SIZE(sr_cntrl) ((((sr_cntrl & 0x7F0) >> 4) + 1) << 8)
#define SRCTL_BANK_NUM(sr_cntrl) (sr_cntrl & 0xF)
#define SRCTL_EXP_MEM_SIZE(chipid) (chipid == BCM43239_CHIP_ID ? (24 << 8) : (48 << 8))
#define SR_HOST 0
#define SR_ENGINE 1
#ifdef SAVERESTORE
typedef enum {
SR_HSIC_OOB_SHALLOW_WAKE_MODE = 0,
SR_HSIC_OOB_SHALLOW_SLEEP_MODE
} hsic_sr_module_t;
bool hsic_sr_save(void *arg);
#endif /* defined(SAVERESTORE) */
extern CONST uint32 sr_source_code[];
extern CONST uint sr_source_codesz;
typedef bool (*sr_save_callback_t)(void* arg);
typedef void (*sr_restore_callback_t)(void* arg);
/* Function prototypes */
void sr_download_firmware(si_t *si_h);
int sr_engine_enable(si_t *si_h, bool oper, bool enable);
int sr_pll_toggle(si_t *si_h, bool enable);
int sr_update_srfast_dependency(si_t *sih, bool enable);
uint32 sr_chipcontrol(si_t *si_h, uint32 mask, uint32 val);
void sr_save_restore_init(si_t *si_h);
uint32 sr_mem_access(si_t *sih, int op, uint32 addr, uint32 data);
uint32 sr_register_save(si_t *sih, sr_save_callback_t cb, void *arg);
uint32 sr_register_restore(si_t *sih, sr_restore_callback_t cb, void *arg);
void sr_process_save(si_t *sih);
void sr_process_restore(si_t *sih);
int sr_gpio_oobwake(si_t *si_h, bool enable);
int sr_uart_oobwake(si_t *si_h, bool enable);
int sr_uart_oobwake_irq_ack(si_t *sih);
void sr_wakeup_workaround(si_t *sih);
uint32 sr_get_cur_minresmask(si_t *sih);
#ifdef SAVERESTORE
bool sr_cap(si_t *sih);
bool sr_is_wakeup_from_deep_sleep(void);
bool sr_is_wakeup_from_deep_sleep_bit28_check(void);
void sr_wokeup_from_deep_sleep(bool state);
void sr_force_deep_sleep_bit28_check(bool state);
#else
#define sr_cap(a) (FALSE)
#define sr_is_wakeup_from_deep_sleep() (FALSE)
#define sr_is_wakeup_from_deep_sleep_bit28_check() (FALSE)
#define sr_wokeup_from_deep_sleep(state) (FALSE)
#define sr_force_deep_sleep_bit28_check(state) (FALSE)
#endif
#endif /* _SAVERESTORE_H */

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/*
* Broadcom SiliconBackplane hardware register definitions.
*
* $Copyright Open Broadcom Corporation$
*
* $Id: sbconfig.h 241182 2011-02-17 21:50:03Z $
*/
#ifndef _SBCONFIG_H
#define _SBCONFIG_H
#ifndef PAD
#define _PADLINE(line) pad ## line
#define _XSTR(line) _PADLINE(line)
#define PAD _XSTR(__LINE__)
#endif
#define SB_BUS_SIZE 0x10000
#define SB_BUS_BASE(b) (SI_ENUM_BASE + (b) * SB_BUS_SIZE)
#define SB_BUS_MAXCORES (SB_BUS_SIZE / SI_CORE_SIZE)
#define SBCONFIGOFF 0xf00
#define SBCONFIGSIZE 256
#define SBIPSFLAG 0x08
#define SBTPSFLAG 0x18
#define SBTMERRLOGA 0x48
#define SBTMERRLOG 0x50
#define SBADMATCH3 0x60
#define SBADMATCH2 0x68
#define SBADMATCH1 0x70
#define SBIMSTATE 0x90
#define SBINTVEC 0x94
#define SBTMSTATELOW 0x98
#define SBTMSTATEHIGH 0x9c
#define SBBWA0 0xa0
#define SBIMCONFIGLOW 0xa8
#define SBIMCONFIGHIGH 0xac
#define SBADMATCH0 0xb0
#define SBTMCONFIGLOW 0xb8
#define SBTMCONFIGHIGH 0xbc
#define SBBCONFIG 0xc0
#define SBBSTATE 0xc8
#define SBACTCNFG 0xd8
#define SBFLAGST 0xe8
#define SBIDLOW 0xf8
#define SBIDHIGH 0xfc
#define SBIMERRLOGA 0xea8
#define SBIMERRLOG 0xeb0
#define SBTMPORTCONNID0 0xed8
#define SBTMPORTLOCK0 0xef8
#ifndef _LANGUAGE_ASSEMBLY
typedef volatile struct _sbconfig {
uint32 PAD[2];
uint32 sbipsflag;
uint32 PAD[3];
uint32 sbtpsflag;
uint32 PAD[11];
uint32 sbtmerrloga;
uint32 PAD;
uint32 sbtmerrlog;
uint32 PAD[3];
uint32 sbadmatch3;
uint32 PAD;
uint32 sbadmatch2;
uint32 PAD;
uint32 sbadmatch1;
uint32 PAD[7];
uint32 sbimstate;
uint32 sbintvec;
uint32 sbtmstatelow;
uint32 sbtmstatehigh;
uint32 sbbwa0;
uint32 PAD;
uint32 sbimconfiglow;
uint32 sbimconfighigh;
uint32 sbadmatch0;
uint32 PAD;
uint32 sbtmconfiglow;
uint32 sbtmconfighigh;
uint32 sbbconfig;
uint32 PAD;
uint32 sbbstate;
uint32 PAD[3];
uint32 sbactcnfg;
uint32 PAD[3];
uint32 sbflagst;
uint32 PAD[3];
uint32 sbidlow;
uint32 sbidhigh;
} sbconfig_t;
#endif
#define SBIPS_INT1_MASK 0x3f
#define SBIPS_INT1_SHIFT 0
#define SBIPS_INT2_MASK 0x3f00
#define SBIPS_INT2_SHIFT 8
#define SBIPS_INT3_MASK 0x3f0000
#define SBIPS_INT3_SHIFT 16
#define SBIPS_INT4_MASK 0x3f000000
#define SBIPS_INT4_SHIFT 24
#define SBTPS_NUM0_MASK 0x3f
#define SBTPS_F0EN0 0x40
#define SBTMEL_CM 0x00000007
#define SBTMEL_CI 0x0000ff00
#define SBTMEL_EC 0x0f000000
#define SBTMEL_ME 0x80000000
#define SBIM_PC 0xf
#define SBIM_AP_MASK 0x30
#define SBIM_AP_BOTH 0x00
#define SBIM_AP_TS 0x10
#define SBIM_AP_TK 0x20
#define SBIM_AP_RSV 0x30
#define SBIM_IBE 0x20000
#define SBIM_TO 0x40000
#define SBIM_BY 0x01800000
#define SBIM_RJ 0x02000000
#define SBTML_RESET 0x0001
#define SBTML_REJ_MASK 0x0006
#define SBTML_REJ 0x0002
#define SBTML_TMPREJ 0x0004
#define SBTML_SICF_SHIFT 16
#define SBTMH_SERR 0x0001
#define SBTMH_INT 0x0002
#define SBTMH_BUSY 0x0004
#define SBTMH_TO 0x0020
#define SBTMH_SISF_SHIFT 16
#define SBBWA_TAB0_MASK 0xffff
#define SBBWA_TAB1_MASK 0xffff
#define SBBWA_TAB1_SHIFT 16
#define SBIMCL_STO_MASK 0x7
#define SBIMCL_RTO_MASK 0x70
#define SBIMCL_RTO_SHIFT 4
#define SBIMCL_CID_MASK 0xff0000
#define SBIMCL_CID_SHIFT 16
#define SBIMCH_IEM_MASK 0xc
#define SBIMCH_TEM_MASK 0x30
#define SBIMCH_TEM_SHIFT 4
#define SBIMCH_BEM_MASK 0xc0
#define SBIMCH_BEM_SHIFT 6
#define SBAM_TYPE_MASK 0x3
#define SBAM_AD64 0x4
#define SBAM_ADINT0_MASK 0xf8
#define SBAM_ADINT0_SHIFT 3
#define SBAM_ADINT1_MASK 0x1f8
#define SBAM_ADINT1_SHIFT 3
#define SBAM_ADINT2_MASK 0x1f8
#define SBAM_ADINT2_SHIFT 3
#define SBAM_ADEN 0x400
#define SBAM_ADNEG 0x800
#define SBAM_BASE0_MASK 0xffffff00
#define SBAM_BASE0_SHIFT 8
#define SBAM_BASE1_MASK 0xfffff000
#define SBAM_BASE1_SHIFT 12
#define SBAM_BASE2_MASK 0xffff0000
#define SBAM_BASE2_SHIFT 16
#define SBTMCL_CD_MASK 0xff
#define SBTMCL_CO_MASK 0xf800
#define SBTMCL_CO_SHIFT 11
#define SBTMCL_IF_MASK 0xfc0000
#define SBTMCL_IF_SHIFT 18
#define SBTMCL_IM_MASK 0x3000000
#define SBTMCL_IM_SHIFT 24
#define SBTMCH_BM_MASK 0x3
#define SBTMCH_RM_MASK 0x3
#define SBTMCH_RM_SHIFT 2
#define SBTMCH_SM_MASK 0x30
#define SBTMCH_SM_SHIFT 4
#define SBTMCH_EM_MASK 0x300
#define SBTMCH_EM_SHIFT 8
#define SBTMCH_IM_MASK 0xc00
#define SBTMCH_IM_SHIFT 10
#define SBBC_LAT_MASK 0x3
#define SBBC_MAX0_MASK 0xf0000
#define SBBC_MAX0_SHIFT 16
#define SBBC_MAX1_MASK 0xf00000
#define SBBC_MAX1_SHIFT 20
#define SBBS_SRD 0x1
#define SBBS_HRD 0x2
#define SBIDL_CS_MASK 0x3
#define SBIDL_AR_MASK 0x38
#define SBIDL_AR_SHIFT 3
#define SBIDL_SYNCH 0x40
#define SBIDL_INIT 0x80
#define SBIDL_MINLAT_MASK 0xf00
#define SBIDL_MINLAT_SHIFT 8
#define SBIDL_MAXLAT 0xf000
#define SBIDL_MAXLAT_SHIFT 12
#define SBIDL_FIRST 0x10000
#define SBIDL_CW_MASK 0xc0000
#define SBIDL_CW_SHIFT 18
#define SBIDL_TP_MASK 0xf00000
#define SBIDL_TP_SHIFT 20
#define SBIDL_IP_MASK 0xf000000
#define SBIDL_IP_SHIFT 24
#define SBIDL_RV_MASK 0xf0000000
#define SBIDL_RV_SHIFT 28
#define SBIDL_RV_2_2 0x00000000
#define SBIDL_RV_2_3 0x10000000
#define SBIDH_RC_MASK 0x000f
#define SBIDH_RCE_MASK 0x7000
#define SBIDH_RCE_SHIFT 8
#define SBCOREREV(sbidh) \
((((sbidh) & SBIDH_RCE_MASK) >> SBIDH_RCE_SHIFT) | ((sbidh) & SBIDH_RC_MASK))
#define SBIDH_CC_MASK 0x8ff0
#define SBIDH_CC_SHIFT 4
#define SBIDH_VC_MASK 0xffff0000
#define SBIDH_VC_SHIFT 16
#define SB_COMMIT 0xfd8
#define SB_VEND_BCM 0x4243
#endif

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/*
* Generic Broadcom Home Networking Division (HND) DMA engine HW interface
* This supports the following chips: BCM42xx, 44xx, 47xx .
*
* $Copyright Open Broadcom Corporation$
*
* $Id: sbhnddma.h 345316 2012-07-17 17:46:04Z $
*/
#ifndef _sbhnddma_h_
#define _sbhnddma_h_
typedef volatile struct {
uint32 control;
uint32 addr;
uint32 ptr;
uint32 status;
} dma32regs_t;
typedef volatile struct {
dma32regs_t xmt;
dma32regs_t rcv;
} dma32regp_t;
typedef volatile struct {
uint32 fifoaddr;
uint32 fifodatalow;
uint32 fifodatahigh;
uint32 pad;
} dma32diag_t;
typedef volatile struct {
uint32 ctrl;
uint32 addr;
} dma32dd_t;
#define D32RINGALIGN_BITS 12
#define D32MAXRINGSZ (1 << D32RINGALIGN_BITS)
#define D32RINGALIGN (1 << D32RINGALIGN_BITS)
#define D32MAXDD (D32MAXRINGSZ / sizeof (dma32dd_t))
#define XC_XE ((uint32)1 << 0)
#define XC_SE ((uint32)1 << 1)
#define XC_LE ((uint32)1 << 2)
#define XC_FL ((uint32)1 << 4)
#define XC_MR_MASK 0x000000C0
#define XC_MR_SHIFT 6
#define XC_PD ((uint32)1 << 11)
#define XC_AE ((uint32)3 << 16)
#define XC_AE_SHIFT 16
#define XC_BL_MASK 0x001C0000
#define XC_BL_SHIFT 18
#define XC_PC_MASK 0x00E00000
#define XC_PC_SHIFT 21
#define XC_PT_MASK 0x03000000
#define XC_PT_SHIFT 24
#define DMA_MR_1 0
#define DMA_MR_2 1
#define DMA_BL_16 0
#define DMA_BL_32 1
#define DMA_BL_64 2
#define DMA_BL_128 3
#define DMA_BL_256 4
#define DMA_BL_512 5
#define DMA_BL_1024 6
#define DMA_PC_0 0
#define DMA_PC_4 1
#define DMA_PC_8 2
#define DMA_PC_16 3
#define DMA_PT_1 0
#define DMA_PT_2 1
#define DMA_PT_4 2
#define DMA_PT_8 3
#define XP_LD_MASK 0xfff
#define XS_CD_MASK 0x0fff
#define XS_XS_MASK 0xf000
#define XS_XS_SHIFT 12
#define XS_XS_DISABLED 0x0000
#define XS_XS_ACTIVE 0x1000
#define XS_XS_IDLE 0x2000
#define XS_XS_STOPPED 0x3000
#define XS_XS_SUSP 0x4000
#define XS_XE_MASK 0xf0000
#define XS_XE_SHIFT 16
#define XS_XE_NOERR 0x00000
#define XS_XE_DPE 0x10000
#define XS_XE_DFU 0x20000
#define XS_XE_BEBR 0x30000
#define XS_XE_BEDA 0x40000
#define XS_AD_MASK 0xfff00000
#define XS_AD_SHIFT 20
#define RC_RE ((uint32)1 << 0)
#define RC_RO_MASK 0xfe
#define RC_RO_SHIFT 1
#define RC_FM ((uint32)1 << 8)
#define RC_SH ((uint32)1 << 9)
#define RC_OC ((uint32)1 << 10)
#define RC_PD ((uint32)1 << 11)
#define RC_AE ((uint32)3 << 16)
#define RC_AE_SHIFT 16
#define RC_BL_MASK 0x001C0000
#define RC_BL_SHIFT 18
#define RC_PC_MASK 0x00E00000
#define RC_PC_SHIFT 21
#define RC_PT_MASK 0x03000000
#define RC_PT_SHIFT 24
#define RP_LD_MASK 0xfff
#define RS_CD_MASK 0x0fff
#define RS_RS_MASK 0xf000
#define RS_RS_SHIFT 12
#define RS_RS_DISABLED 0x0000
#define RS_RS_ACTIVE 0x1000
#define RS_RS_IDLE 0x2000
#define RS_RS_STOPPED 0x3000
#define RS_RE_MASK 0xf0000
#define RS_RE_SHIFT 16
#define RS_RE_NOERR 0x00000
#define RS_RE_DPE 0x10000
#define RS_RE_DFO 0x20000
#define RS_RE_BEBW 0x30000
#define RS_RE_BEDA 0x40000
#define RS_AD_MASK 0xfff00000
#define RS_AD_SHIFT 20
#define FA_OFF_MASK 0xffff
#define FA_SEL_MASK 0xf0000
#define FA_SEL_SHIFT 16
#define FA_SEL_XDD 0x00000
#define FA_SEL_XDP 0x10000
#define FA_SEL_RDD 0x40000
#define FA_SEL_RDP 0x50000
#define FA_SEL_XFD 0x80000
#define FA_SEL_XFP 0x90000
#define FA_SEL_RFD 0xc0000
#define FA_SEL_RFP 0xd0000
#define FA_SEL_RSD 0xe0000
#define FA_SEL_RSP 0xf0000
#define CTRL_BC_MASK 0x00001fff
#define CTRL_AE ((uint32)3 << 16)
#define CTRL_AE_SHIFT 16
#define CTRL_PARITY ((uint32)3 << 18)
#define CTRL_EOT ((uint32)1 << 28)
#define CTRL_IOC ((uint32)1 << 29)
#define CTRL_EOF ((uint32)1 << 30)
#define CTRL_SOF ((uint32)1 << 31)
#define CTRL_CORE_MASK 0x0ff00000
typedef volatile struct {
uint32 control;
uint32 ptr;
uint32 addrlow;
uint32 addrhigh;
uint32 status0;
uint32 status1;
} dma64regs_t;
typedef volatile struct {
dma64regs_t tx;
dma64regs_t rx;
} dma64regp_t;
typedef volatile struct {
uint32 fifoaddr;
uint32 fifodatalow;
uint32 fifodatahigh;
uint32 pad;
} dma64diag_t;
typedef volatile struct {
uint32 ctrl1;
uint32 ctrl2;
uint32 addrlow;
uint32 addrhigh;
} dma64dd_t;
#define D64RINGALIGN_BITS 13
#define D64MAXRINGSZ (1 << D64RINGALIGN_BITS)
#define D64RINGBOUNDARY (1 << D64RINGALIGN_BITS)
#define D64MAXDD (D64MAXRINGSZ / sizeof (dma64dd_t))
#define D64MAXDD_LARGE ((1 << 16) / sizeof (dma64dd_t))
#define D64RINGBOUNDARY_LARGE (1 << 16)
#define D64_DEF_USBBURSTLEN 2
#define D64_DEF_SDIOBURSTLEN 1
#ifndef D64_USBBURSTLEN
#define D64_USBBURSTLEN DMA_BL_64
#endif
#ifndef D64_SDIOBURSTLEN
#define D64_SDIOBURSTLEN DMA_BL_32
#endif
#define D64_XC_XE 0x00000001
#define D64_XC_SE 0x00000002
#define D64_XC_LE 0x00000004
#define D64_XC_FL 0x00000010
#define D64_XC_MR_MASK 0x000000C0
#define D64_XC_MR_SHIFT 6
#define D64_XC_PD 0x00000800
#define D64_XC_AE 0x00030000
#define D64_XC_AE_SHIFT 16
#define D64_XC_BL_MASK 0x001C0000
#define D64_XC_BL_SHIFT 18
#define D64_XC_PC_MASK 0x00E00000
#define D64_XC_PC_SHIFT 21
#define D64_XC_PT_MASK 0x03000000
#define D64_XC_PT_SHIFT 24
#define D64_XP_LD_MASK 0x00001fff
#define D64_XS0_CD_MASK (di->d64_xs0_cd_mask)
#define D64_XS0_XS_MASK 0xf0000000
#define D64_XS0_XS_SHIFT 28
#define D64_XS0_XS_DISABLED 0x00000000
#define D64_XS0_XS_ACTIVE 0x10000000
#define D64_XS0_XS_IDLE 0x20000000
#define D64_XS0_XS_STOPPED 0x30000000
#define D64_XS0_XS_SUSP 0x40000000
#define D64_XS1_AD_MASK (di->d64_xs1_ad_mask)
#define D64_XS1_XE_MASK 0xf0000000
#define D64_XS1_XE_SHIFT 28
#define D64_XS1_XE_NOERR 0x00000000
#define D64_XS1_XE_DPE 0x10000000
#define D64_XS1_XE_DFU 0x20000000
#define D64_XS1_XE_DTE 0x30000000
#define D64_XS1_XE_DESRE 0x40000000
#define D64_XS1_XE_COREE 0x50000000
#define D64_RC_RE 0x00000001
#define D64_RC_RO_MASK 0x000000fe
#define D64_RC_RO_SHIFT 1
#define D64_RC_FM 0x00000100
#define D64_RC_SH 0x00000200
#define D64_RC_OC 0x00000400
#define D64_RC_PD 0x00000800
#define D64_RC_GE 0x00004000
#define D64_RC_AE 0x00030000
#define D64_RC_AE_SHIFT 16
#define D64_RC_BL_MASK 0x001C0000
#define D64_RC_BL_SHIFT 18
#define D64_RC_PC_MASK 0x00E00000
#define D64_RC_PC_SHIFT 21
#define D64_RC_PT_MASK 0x03000000
#define D64_RC_PT_SHIFT 24
#define DMA_CTRL_PEN (1 << 0)
#define DMA_CTRL_ROC (1 << 1)
#define DMA_CTRL_RXMULTI (1 << 2)
#define DMA_CTRL_UNFRAMED (1 << 3)
#define DMA_CTRL_USB_BOUNDRY4KB_WAR (1 << 4)
#define DMA_CTRL_DMA_AVOIDANCE_WAR (1 << 5)
#define D64_RP_LD_MASK 0x00001fff
#define D64_RS0_CD_MASK (di->d64_rs0_cd_mask)
#define D64_RS0_RS_MASK 0xf0000000
#define D64_RS0_RS_SHIFT 28
#define D64_RS0_RS_DISABLED 0x00000000
#define D64_RS0_RS_ACTIVE 0x10000000
#define D64_RS0_RS_IDLE 0x20000000
#define D64_RS0_RS_STOPPED 0x30000000
#define D64_RS0_RS_SUSP 0x40000000
#define D64_RS1_AD_MASK 0x0001ffff
#define D64_RS1_RE_MASK 0xf0000000
#define D64_RS1_RE_SHIFT 28
#define D64_RS1_RE_NOERR 0x00000000
#define D64_RS1_RE_DPO 0x10000000
#define D64_RS1_RE_DFU 0x20000000
#define D64_RS1_RE_DTE 0x30000000
#define D64_RS1_RE_DESRE 0x40000000
#define D64_RS1_RE_COREE 0x50000000
#define D64_FA_OFF_MASK 0xffff
#define D64_FA_SEL_MASK 0xf0000
#define D64_FA_SEL_SHIFT 16
#define D64_FA_SEL_XDD 0x00000
#define D64_FA_SEL_XDP 0x10000
#define D64_FA_SEL_RDD 0x40000
#define D64_FA_SEL_RDP 0x50000
#define D64_FA_SEL_XFD 0x80000
#define D64_FA_SEL_XFP 0x90000
#define D64_FA_SEL_RFD 0xc0000
#define D64_FA_SEL_RFP 0xd0000
#define D64_FA_SEL_RSD 0xe0000
#define D64_FA_SEL_RSP 0xf0000
#define D64_CTRL_COREFLAGS 0x0ff00000
#define D64_CTRL1_EOT ((uint32)1 << 28)
#define D64_CTRL1_IOC ((uint32)1 << 29)
#define D64_CTRL1_EOF ((uint32)1 << 30)
#define D64_CTRL1_SOF ((uint32)1 << 31)
#define D64_CTRL2_BC_MASK 0x00007fff
#define D64_CTRL2_AE 0x00030000
#define D64_CTRL2_AE_SHIFT 16
#define D64_CTRL2_PARITY 0x00040000
#define D64_CTRL_CORE_MASK 0x0ff00000
#define D64_RX_FRM_STS_LEN 0x0000ffff
#define D64_RX_FRM_STS_OVFL 0x00800000
#define D64_RX_FRM_STS_DSCRCNT 0x0f000000
#define D64_RX_FRM_STS_DATATYPE 0xf0000000
typedef volatile struct {
uint16 len;
uint16 flags;
} dma_rxh_t;
#endif

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/*
* BCM43XX Sonics SiliconBackplane PCMCIA core hardware definitions.
*
* $Copyright Open Broadcom Corporation$
*
* $Id: sbpcmcia.h 401759 2013-05-13 16:08:08Z sudhirbs $
*/
#ifndef _SBPCMCIA_H
#define _SBPCMCIA_H
/* All the addresses that are offsets in attribute space are divided
* by two to account for the fact that odd bytes are invalid in
* attribute space and our read/write routines make the space appear
* as if they didn't exist. Still we want to show the original numbers
* as documented in the hnd_pcmcia core manual.
*/
/* PCMCIA Function Configuration Registers */
#define PCMCIA_FCR (0x700 / 2)
#define FCR0_OFF 0
#define FCR1_OFF (0x40 / 2)
#define FCR2_OFF (0x80 / 2)
#define FCR3_OFF (0xc0 / 2)
#define PCMCIA_FCR0 (0x700 / 2)
#define PCMCIA_FCR1 (0x740 / 2)
#define PCMCIA_FCR2 (0x780 / 2)
#define PCMCIA_FCR3 (0x7c0 / 2)
/* Standard PCMCIA FCR registers */
#define PCMCIA_COR 0
#define COR_RST 0x80
#define COR_LEV 0x40
#define COR_IRQEN 0x04
#define COR_BLREN 0x01
#define COR_FUNEN 0x01
#define PCICIA_FCSR (2 / 2)
#define PCICIA_PRR (4 / 2)
#define PCICIA_SCR (6 / 2)
#define PCICIA_ESR (8 / 2)
#define PCM_MEMOFF 0x0000
#define F0_MEMOFF 0x1000
#define F1_MEMOFF 0x2000
#define F2_MEMOFF 0x3000
#define F3_MEMOFF 0x4000
/* Memory base in the function fcr's */
#define MEM_ADDR0 (0x728 / 2)
#define MEM_ADDR1 (0x72a / 2)
#define MEM_ADDR2 (0x72c / 2)
/* PCMCIA base plus Srom access in fcr0: */
#define PCMCIA_ADDR0 (0x072e / 2)
#define PCMCIA_ADDR1 (0x0730 / 2)
#define PCMCIA_ADDR2 (0x0732 / 2)
#define MEM_SEG (0x0734 / 2)
#define SROM_CS (0x0736 / 2)
#define SROM_DATAL (0x0738 / 2)
#define SROM_DATAH (0x073a / 2)
#define SROM_ADDRL (0x073c / 2)
#define SROM_ADDRH (0x073e / 2)
#define SROM_INFO2 (0x0772 / 2) /* Corerev >= 2 && <= 5 */
#define SROM_INFO (0x07be / 2) /* Corerev >= 6 */
/* Values for srom_cs: */
#define SROM_IDLE 0
#define SROM_WRITE 1
#define SROM_READ 2
#define SROM_WEN 4
#define SROM_WDS 7
#define SROM_DONE 8
/* Fields in srom_info: */
#define SRI_SZ_MASK 0x03
#define SRI_BLANK 0x04
#define SRI_OTP 0x80
#if !defined(LINUX_POSTMOGRIFY_REMOVAL)
/* CIS stuff */
/* The CIS stops where the FCRs start */
#define CIS_SIZE PCMCIA_FCR
/* CIS tuple length field max */
#define CIS_TUPLE_LEN_MAX 0xff
/* Standard tuples we know about */
#define CISTPL_NULL 0x00
#define CISTPL_VERS_1 0x15 /* CIS ver, manf, dev & ver strings */
#define CISTPL_MANFID 0x20 /* Manufacturer and device id */
#define CISTPL_FUNCID 0x21 /* Function identification */
#define CISTPL_FUNCE 0x22 /* Function extensions */
#define CISTPL_CFTABLE 0x1b /* Config table entry */
#define CISTPL_END 0xff /* End of the CIS tuple chain */
/* Function identifier provides context for the function extentions tuple */
#define CISTPL_FID_SDIO 0x0c /* Extensions defined by SDIO spec */
/* Function extensions for LANs (assumed for extensions other than SDIO) */
#define LAN_TECH 1 /* Technology type */
#define LAN_SPEED 2 /* Raw bit rate */
#define LAN_MEDIA 3 /* Transmission media */
#define LAN_NID 4 /* Node identification (aka MAC addr) */
#define LAN_CONN 5 /* Connector standard */
/* CFTable */
#define CFTABLE_REGWIN_2K 0x08 /* 2k reg windows size */
#define CFTABLE_REGWIN_4K 0x10 /* 4k reg windows size */
#define CFTABLE_REGWIN_8K 0x20 /* 8k reg windows size */
/* Vendor unique tuples are 0x80-0x8f. Within Broadcom we'll
* take one for HNBU, and use "extensions" (a la FUNCE) within it.
*/
#define CISTPL_BRCM_HNBU 0x80
/* Subtypes of BRCM_HNBU: */
#define HNBU_SROMREV 0x00 /* A byte with sromrev, 1 if not present */
#define HNBU_CHIPID 0x01 /* Two 16bit values: PCI vendor & device id */
#define HNBU_BOARDREV 0x02 /* One byte board revision */
#define HNBU_PAPARMS 0x03 /* PA parameters: 8 (sromrev == 1)
* or 9 (sromrev > 1) bytes
*/
#define HNBU_OEM 0x04 /* Eight bytes OEM data (sromrev == 1) */
#define HNBU_CC 0x05 /* Default country code (sromrev == 1) */
#define HNBU_AA 0x06 /* Antennas available */
#define HNBU_AG 0x07 /* Antenna gain */
#define HNBU_BOARDFLAGS 0x08 /* board flags (2 or 4 bytes) */
#define HNBU_LEDS 0x09 /* LED set */
#define HNBU_CCODE 0x0a /* Country code (2 bytes ascii + 1 byte cctl)
* in rev 2
*/
#define HNBU_CCKPO 0x0b /* 2 byte cck power offsets in rev 3 */
#define HNBU_OFDMPO 0x0c /* 4 byte 11g ofdm power offsets in rev 3 */
#define HNBU_GPIOTIMER 0x0d /* 2 bytes with on/off values in rev 3 */
#define HNBU_PAPARMS5G 0x0e /* 5G PA params */
#define HNBU_ANT5G 0x0f /* 4328 5G antennas available/gain */
#define HNBU_RDLID 0x10 /* 2 byte USB remote downloader (RDL) product Id */
#define HNBU_RSSISMBXA2G 0x11 /* 4328 2G RSSI mid pt sel & board switch arch,
* 2 bytes, rev 3.
*/
#define HNBU_RSSISMBXA5G 0x12 /* 4328 5G RSSI mid pt sel & board switch arch,
* 2 bytes, rev 3.
*/
#define HNBU_XTALFREQ 0x13 /* 4 byte Crystal frequency in kilohertz */
#define HNBU_TRI2G 0x14 /* 4328 2G TR isolation, 1 byte */
#define HNBU_TRI5G 0x15 /* 4328 5G TR isolation, 3 bytes */
#define HNBU_RXPO2G 0x16 /* 4328 2G RX power offset, 1 byte */
#define HNBU_RXPO5G 0x17 /* 4328 5G RX power offset, 1 byte */
#define HNBU_BOARDNUM 0x18 /* board serial number, independent of mac addr */
#define HNBU_MACADDR 0x19 /* mac addr override for the standard CIS LAN_NID */
#define HNBU_RDLSN 0x1a /* 2 bytes; serial # advertised in USB descriptor */
#define HNBU_BOARDTYPE 0x1b /* 2 bytes; boardtype */
#define HNBU_LEDDC 0x1c /* 2 bytes; LED duty cycle */
#define HNBU_HNBUCIS 0x1d /* what follows is proprietary HNBU CIS format */
#define HNBU_PAPARMS_SSLPNPHY 0x1e /* SSLPNPHY PA params */
#define HNBU_RSSISMBXA2G_SSLPNPHY 0x1f /* SSLPNPHY RSSI mid pt sel & board switch arch */
#define HNBU_RDLRNDIS 0x20 /* 1 byte; 1 = RDL advertises RNDIS config */
#define HNBU_CHAINSWITCH 0x21 /* 2 byte; txchain, rxchain */
#define HNBU_REGREV 0x22 /* 1 byte; */
#define HNBU_FEM 0x23 /* 2 or 4 byte: 11n frontend specification */
#define HNBU_PAPARMS_C0 0x24 /* 8 or 30 bytes: 11n pa paramater for chain 0 */
#define HNBU_PAPARMS_C1 0x25 /* 8 or 30 bytes: 11n pa paramater for chain 1 */
#define HNBU_PAPARMS_C2 0x26 /* 8 or 30 bytes: 11n pa paramater for chain 2 */
#define HNBU_PAPARMS_C3 0x27 /* 8 or 30 bytes: 11n pa paramater for chain 3 */
#define HNBU_PO_CCKOFDM 0x28 /* 6 or 18 bytes: cck2g/ofdm2g/ofdm5g power offset */
#define HNBU_PO_MCS2G 0x29 /* 8 bytes: mcs2g power offset */
#define HNBU_PO_MCS5GM 0x2a /* 8 bytes: mcs5g mid band power offset */
#define HNBU_PO_MCS5GLH 0x2b /* 16 bytes: mcs5g low-high band power offset */
#define HNBU_PO_CDD 0x2c /* 2 bytes: cdd2g/5g power offset */
#define HNBU_PO_STBC 0x2d /* 2 bytes: stbc2g/5g power offset */
#define HNBU_PO_40M 0x2e /* 2 bytes: 40Mhz channel 2g/5g power offset */
#define HNBU_PO_40MDUP 0x2f /* 2 bytes: 40Mhz channel dup 2g/5g power offset */
#define HNBU_RDLRWU 0x30 /* 1 byte; 1 = RDL advertises Remote Wake-up */
#define HNBU_WPS 0x31 /* 1 byte; GPIO pin for WPS button */
#define HNBU_USBFS 0x32 /* 1 byte; 1 = USB advertises FS mode only */
#define HNBU_BRMIN 0x33 /* 4 byte bootloader min resource mask */
#define HNBU_BRMAX 0x34 /* 4 byte bootloader max resource mask */
#define HNBU_PATCH 0x35 /* bootloader patch addr(2b) & data(4b) pair */
#define HNBU_CCKFILTTYPE 0x36 /* CCK digital filter selection options */
#define HNBU_OFDMPO5G 0x37 /* 4 * 3 = 12 byte 11a ofdm power offsets in rev 3 */
#define HNBU_ELNA2G 0x38
#define HNBU_ELNA5G 0x39
#define HNBU_TEMPTHRESH 0x3A /* 2 bytes
* byte1 tempthresh
* byte2 period(msb 4 bits) | hysterisis(lsb 4 bits)
*/
#define HNBU_UUID 0x3B /* 16 Bytes Hex */
#define HNBU_USBEPNUM 0x40 /* USB endpoint numbers */
/* POWER PER RATE for SROM V9 */
#define HNBU_CCKBW202GPO 0x41 /* 2 bytes each
* CCK Power offsets for 20 MHz rates (11, 5.5, 2, 1Mbps)
* cckbw202gpo cckbw20ul2gpo
*/
#define HNBU_LEGOFDMBW202GPO 0x42 /* 4 bytes each
* OFDM power offsets for 20 MHz Legacy rates
* (54, 48, 36, 24, 18, 12, 9, 6 Mbps)
* legofdmbw202gpo legofdmbw20ul2gpo
*/
#define HNBU_LEGOFDMBW205GPO 0x43 /* 4 bytes each
* 5G band: OFDM power offsets for 20 MHz Legacy rates
* (54, 48, 36, 24, 18, 12, 9, 6 Mbps)
* low subband : legofdmbw205glpo legofdmbw20ul2glpo
* mid subband :legofdmbw205gmpo legofdmbw20ul2gmpo
* high subband :legofdmbw205ghpo legofdmbw20ul2ghpo
*/
#define HNBU_MCS2GPO 0x44 /* 4 bytes each
* mcs 0-7 power-offset. LSB nibble: m0, MSB nibble: m7
* mcsbw202gpo mcsbw20ul2gpo mcsbw402gpo
*/
#define HNBU_MCS5GLPO 0x45 /* 4 bytes each
* 5G low subband mcs 0-7 power-offset.
* LSB nibble: m0, MSB nibble: m7
* mcsbw205glpo mcsbw20ul5glpo mcsbw405glpo
*/
#define HNBU_MCS5GMPO 0x46 /* 4 bytes each
* 5G mid subband mcs 0-7 power-offset.
* LSB nibble: m0, MSB nibble: m7
* mcsbw205gmpo mcsbw20ul5gmpo mcsbw405gmpo
*/
#define HNBU_MCS5GHPO 0x47 /* 4 bytes each
* 5G high subband mcs 0-7 power-offset.
* LSB nibble: m0, MSB nibble: m7
* mcsbw205ghpo mcsbw20ul5ghpo mcsbw405ghpo
*/
#define HNBU_MCS32PO 0x48 /* 2 bytes total
* mcs-32 power offset for each band/subband.
* LSB nibble: 2G band, MSB nibble:
* mcs322ghpo, mcs325gmpo, mcs325glpo, mcs322gpo
*/
#define HNBU_LEG40DUPPO 0x49 /* 2 bytes total
* Additional power offset for Legacy Dup40 transmissions.
* Applied in addition to legofdmbw20ulXpo, X=2g, 5gl, 5gm, or 5gh.
* LSB nibble: 2G band, MSB nibble: 5G band high subband.
* leg40dup5ghpo, leg40dup5gmpo, leg40dup5glpo, leg40dup2gpo
*/
#define HNBU_PMUREGS 0x4a /* Variable length (5 bytes for each register)
* The setting of the ChipCtrl, PLL, RegulatorCtrl, Up/Down Timer and
* ResourceDependency Table registers.
*/
#define HNBU_PATCH2 0x4b /* bootloader TCAM patch addr(4b) & data(4b) pair .
* This is required for socram rev 15 onwards.
*/
#define HNBU_USBRDY 0x4c /* Variable length (upto 5 bytes)
* This is to indicate the USB/HSIC host controller
* that the device is ready for enumeration.
*/
#define HNBU_USBREGS 0x4d /* Variable length
* The setting of the devcontrol, HSICPhyCtrl1 and HSICPhyCtrl2
* registers during the USB initialization.
*/
#define HNBU_BLDR_TIMEOUT 0x4e /* 2 bytes used for HSIC bootloader to reset chip
* on connect timeout.
* The Delay after USBConnect for timeout till dongle receives
* get_descriptor request.
*/
#define HNBU_USBFLAGS 0x4f
#define HNBU_PATCH_AUTOINC 0x50
#define HNBU_MDIO_REGLIST 0x51
#define HNBU_MDIOEX_REGLIST 0x52
/* Unified OTP: tupple to embed USB manfid inside SDIO CIS */
#define HNBU_UMANFID 0x53
#define HNBU_PUBKEY 0x54 /* 128 byte; publick key to validate downloaded FW */
#define HNBU_MUXENAB 0x56 /* 1 byte to enable mux options */
#define HNBU_GCI_CCR 0x57 /* GCI Chip control register */
#define HNBU_FEM_CFG 0x58 /* FEM config */
#define HNBU_ACPA_C0 0x59 /* ACPHY PA parameters: chain 0 */
#define HNBU_ACPA_C1 0x5a /* ACPHY PA parameters: chain 1 */
#define HNBU_ACPA_C2 0x5b /* ACPHY PA parameters: chain 2 */
#define HNBU_MEAS_PWR 0x5c
#define HNBU_PDOFF 0x5d
#define HNBU_ACPPR_2GPO 0x5e /* ACPHY Power-per-rate 2gpo */
#define HNBU_ACPPR_5GPO 0x5f /* ACPHY Power-per-rate 5gpo */
#define HNBU_ACPPR_SBPO 0x60 /* ACPHY Power-per-rate sbpo */
#define HNBU_NOISELVL 0x61
#define HNBU_RXGAIN_ERR 0x62
#define HNBU_AGBGA 0x63
#define HNBU_USBDESC_COMPOSITE 0x64 /* USB WLAN/BT composite descriptor */
#define HNBU_PATCH_AUTOINC8 0x65 /* Auto increment patch entry for 8 byte patching */
#define HNBU_PATCH8 0x66 /* Patch entry for 8 byte patching */
#define HNBU_ACRXGAINS_C0 0x67 /* ACPHY rxgains: chain 0 */
#define HNBU_ACRXGAINS_C1 0x68 /* ACPHY rxgains: chain 1 */
#define HNBU_ACRXGAINS_C2 0x69 /* ACPHY rxgains: chain 2 */
#define HNBU_TXDUTY 0x6a /* Tx duty cycle for ACPHY 5g 40/80 Mhz */
#define HNBU_USBUTMI_CTL 0x6b /* 2 byte USB UTMI/LDO Control */
#define HNBU_PDOFF_2G 0x6c
#define HNBU_USBSSPHY_UTMI_CTL0 0x6d /* 4 byte USB SSPHY UTMI Control */
#define HNBU_USBSSPHY_UTMI_CTL1 0x6e /* 4 byte USB SSPHY UTMI Control */
#define HNBU_USBSSPHY_UTMI_CTL2 0x6f /* 4 byte USB SSPHY UTMI Control */
#define HNBU_USBSSPHY_SLEEP0 0x70 /* 2 byte USB SSPHY sleep */
#define HNBU_USBSSPHY_SLEEP1 0x71 /* 2 byte USB SSPHY sleep */
#define HNBU_USBSSPHY_SLEEP2 0x72 /* 2 byte USB SSPHY sleep */
#define HNBU_USBSSPHY_SLEEP3 0x73 /* 2 byte USB SSPHY sleep */
#define HNBU_USBSSPHY_MDIO 0x74 /* USB SSPHY INIT regs setting */
#define HNBU_USB30PHY_NOSS 0x75 /* USB30 NO Super Speed */
#define HNBU_USB30PHY_U1U2 0x76 /* USB30 PHY U1U2 Enable */
#define HNBU_USB30PHY_REGS 0x77 /* USB30 PHY REGs update */
#define HNBU_SROM3SWRGN 0x80 /* 78 bytes; srom rev 3 s/w region without crc8
* plus extra info appended.
*/
#define HNBU_RESERVED 0x81 /* Reserved for non-BRCM post-mfg additions */
/* XXX Added for 'Olympic' OTP management */
#define HNBU_CUSTOM1 0x82 /* 4 byte; For non-BRCM post-mfg additions */
#define HNBU_CUSTOM2 0x83 /* Reserved; For non-BRCM post-mfg additions */
#define HNBU_ACPAPARAM 0x84 /* ACPHY PAPARAM */
#define HNBU_ACPA_CCK 0x86 /* ACPHY PA trimming parameters: CCK */
#define HNBU_ACPA_40 0x87 /* ACPHY PA trimming parameters: 40 */
#define HNBU_ACPA_80 0x88 /* ACPHY PA trimming parameters: 80 */
#define HNBU_ACPA_4080 0x89 /* ACPHY PA trimming parameters: 40/80 */
#define HNBU_SUBBAND5GVER 0x8a /* subband5gver */
#define HNBU_PAPARAMBWVER 0x8b /* paparambwver */
/* XXX IMPORTANT XXX
* Please update CisTuples twiki page when you define new tuples
*/
#endif /* !defined(LINUX_POSTMOGRIFY_REMOVAL) */
/* sbtmstatelow */
#define SBTML_INT_ACK 0x40000 /* ack the sb interrupt */
#define SBTML_INT_EN 0x20000 /* enable sb interrupt */
/* sbtmstatehigh */
#define SBTMH_INT_STATUS 0x40000 /* sb interrupt status */
#endif /* _SBPCMCIA_H */

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/*
* BCM43XX Sonics SiliconBackplane PCMCIA core hardware definitions.
*
* Copyright (C) 1999-2012, Broadcom Corporation
*
* Unless you and Broadcom execute a separate written software license
* agreement governing use of this software, this software is licensed to you
* under the terms of the GNU General Public License version 2 (the "GPL"),
* available at http://www.broadcom.com/licenses/GPLv2.php, with the
* following added to such license:
*
* As a special exception, the copyright holders of this software give you
* permission to link this software with independent modules, and to copy and
* distribute the resulting executable under terms of your choice, provided that
* you also meet, for each linked independent module, the terms and conditions of
* the license of that module. An independent module is a module which is not
* derived from this software. The special exception does not apply to any
* modifications of the software.
*
* Notwithstanding the above, under no circumstances may you combine this
* software in any way with any other Broadcom software provided under a license
* other than the GPL, without Broadcom's express prior written consent.
*
* $Id: sbpcmcia.h 326494 2012-04-09 13:29:57Z $
*/
#ifndef _SBPCMCIA_H
#define _SBPCMCIA_H
#define PCMCIA_FCR (0x700 / 2)
#define FCR0_OFF 0
#define FCR1_OFF (0x40 / 2)
#define FCR2_OFF (0x80 / 2)
#define FCR3_OFF (0xc0 / 2)
#define PCMCIA_FCR0 (0x700 / 2)
#define PCMCIA_FCR1 (0x740 / 2)
#define PCMCIA_FCR2 (0x780 / 2)
#define PCMCIA_FCR3 (0x7c0 / 2)
#define PCMCIA_COR 0
#define COR_RST 0x80
#define COR_LEV 0x40
#define COR_IRQEN 0x04
#define COR_BLREN 0x01
#define COR_FUNEN 0x01
#define PCICIA_FCSR (2 / 2)
#define PCICIA_PRR (4 / 2)
#define PCICIA_SCR (6 / 2)
#define PCICIA_ESR (8 / 2)
#define PCM_MEMOFF 0x0000
#define F0_MEMOFF 0x1000
#define F1_MEMOFF 0x2000
#define F2_MEMOFF 0x3000
#define F3_MEMOFF 0x4000
#define MEM_ADDR0 (0x728 / 2)
#define MEM_ADDR1 (0x72a / 2)
#define MEM_ADDR2 (0x72c / 2)
#define PCMCIA_ADDR0 (0x072e / 2)
#define PCMCIA_ADDR1 (0x0730 / 2)
#define PCMCIA_ADDR2 (0x0732 / 2)
#define MEM_SEG (0x0734 / 2)
#define SROM_CS (0x0736 / 2)
#define SROM_DATAL (0x0738 / 2)
#define SROM_DATAH (0x073a / 2)
#define SROM_ADDRL (0x073c / 2)
#define SROM_ADDRH (0x073e / 2)
#define SROM_INFO2 (0x0772 / 2)
#define SROM_INFO (0x07be / 2)
#define SROM_IDLE 0
#define SROM_WRITE 1
#define SROM_READ 2
#define SROM_WEN 4
#define SROM_WDS 7
#define SROM_DONE 8
#define SRI_SZ_MASK 0x03
#define SRI_BLANK 0x04
#define SRI_OTP 0x80
#define SBTML_INT_ACK 0x40000
#define SBTML_INT_EN 0x20000
#define SBTMH_INT_STATUS 0x40000
#endif

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/*
* SDIO device core hardware definitions.
* sdio is a portion of the pcmcia core in core rev 3 - rev 8
*
* SDIO core support 1bit, 4 bit SDIO mode as well as SPI mode.
*
* $Copyright Open 2003 Broadcom Corporation$
*
* $Id: sbsdio.h 241182 2011-02-17 21:50:03Z $
*/
#ifndef _SBSDIO_H
#define _SBSDIO_H
#define SBSDIO_NUM_FUNCTION 3 /* as of sdiod rev 0, supports 3 functions */
/* function 1 miscellaneous registers */
#define SBSDIO_SPROM_CS 0x10000 /* sprom command and status */
#define SBSDIO_SPROM_INFO 0x10001 /* sprom info register */
#define SBSDIO_SPROM_DATA_LOW 0x10002 /* sprom indirect access data byte 0 */
#define SBSDIO_SPROM_DATA_HIGH 0x10003 /* sprom indirect access data byte 1 */
#define SBSDIO_SPROM_ADDR_LOW 0x10004 /* sprom indirect access addr byte 0 */
#define SBSDIO_SPROM_ADDR_HIGH 0x10005 /* sprom indirect access addr byte 0 */
#define SBSDIO_CHIP_CTRL_DATA 0x10006 /* xtal_pu (gpio) output */
#define SBSDIO_CHIP_CTRL_EN 0x10007 /* xtal_pu (gpio) enable */
#define SBSDIO_WATERMARK 0x10008 /* rev < 7, watermark for sdio device */
#define SBSDIO_DEVICE_CTL 0x10009 /* control busy signal generation */
/* registers introduced in rev 8, some content (mask/bits) defs in sbsdpcmdev.h */
#define SBSDIO_FUNC1_SBADDRLOW 0x1000A /* SB Address Window Low (b15) */
#define SBSDIO_FUNC1_SBADDRMID 0x1000B /* SB Address Window Mid (b23:b16) */
#define SBSDIO_FUNC1_SBADDRHIGH 0x1000C /* SB Address Window High (b31:b24) */
#define SBSDIO_FUNC1_FRAMECTRL 0x1000D /* Frame Control (frame term/abort) */
#define SBSDIO_FUNC1_CHIPCLKCSR 0x1000E /* ChipClockCSR (ALP/HT ctl/status) */
#define SBSDIO_FUNC1_SDIOPULLUP 0x1000F /* SdioPullUp (on cmd, d0-d2) */
#define SBSDIO_FUNC1_WFRAMEBCLO 0x10019 /* Write Frame Byte Count Low */
#define SBSDIO_FUNC1_WFRAMEBCHI 0x1001A /* Write Frame Byte Count High */
#define SBSDIO_FUNC1_RFRAMEBCLO 0x1001B /* Read Frame Byte Count Low */
#define SBSDIO_FUNC1_RFRAMEBCHI 0x1001C /* Read Frame Byte Count High */
#define SBSDIO_FUNC1_MISC_REG_START 0x10000 /* f1 misc register start */
#define SBSDIO_FUNC1_MISC_REG_LIMIT 0x1001C /* f1 misc register end */
/* Sdio Core Rev 12 */
#define SBSDIO_FUNC1_WAKEUPCTRL 0x1001E
#define SBSDIO_FUNC1_SLEEPCSR 0x1001F
#define SBSDIO_FUNC1_SLEEPCSR_KSO_MASK 0x1
#define SBSDIO_FUNC1_SLEEPCSR_KSO_SHIFT 0
#define SBSDIO_FUNC1_SLEEPCSR_KSO_EN 1
#define SBSDIO_FUNC1_SLEEPCSR_DEVON_MASK 0x2
#define SBSDIO_FUNC1_SLEEPCSR_DEVON_SHIFT 1
/* SBSDIO_SPROM_CS */
#define SBSDIO_SPROM_IDLE 0
#define SBSDIO_SPROM_WRITE 1
#define SBSDIO_SPROM_READ 2
#define SBSDIO_SPROM_WEN 4
#define SBSDIO_SPROM_WDS 7
#define SBSDIO_SPROM_DONE 8
/* SBSDIO_SPROM_INFO */
#define SROM_SZ_MASK 0x03 /* SROM size, 1: 4k, 2: 16k */
#define SROM_BLANK 0x04 /* depreciated in corerev 6 */
#define SROM_OTP 0x80 /* OTP present */
/* SBSDIO_CHIP_CTRL */
#define SBSDIO_CHIP_CTRL_XTAL 0x01 /* or'd with onchip xtal_pu,
* 1: power on oscillator
* (for 4318 only)
*/
/* SBSDIO_WATERMARK */
#define SBSDIO_WATERMARK_MASK 0x7f /* number of words - 1 for sd device
* to wait before sending data to host
*/
/* SBSDIO_DEVICE_CTL */
#define SBSDIO_DEVCTL_SETBUSY 0x01 /* 1: device will assert busy signal when
* receiving CMD53
*/
#define SBSDIO_DEVCTL_SPI_INTR_SYNC 0x02 /* 1: assertion of sdio interrupt is
* synchronous to the sdio clock
*/
#define SBSDIO_DEVCTL_CA_INT_ONLY 0x04 /* 1: mask all interrupts to host
* except the chipActive (rev 8)
*/
#define SBSDIO_DEVCTL_PADS_ISO 0x08 /* 1: isolate internal sdio signals, put
* external pads in tri-state; requires
* sdio bus power cycle to clear (rev 9)
*/
#define SBSDIO_DEVCTL_SB_RST_CTL 0x30 /* Force SD->SB reset mapping (rev 11) */
#define SBSDIO_DEVCTL_RST_CORECTL 0x00 /* Determined by CoreControl bit */
#define SBSDIO_DEVCTL_RST_BPRESET 0x10 /* Force backplane reset */
#define SBSDIO_DEVCTL_RST_NOBPRESET 0x20 /* Force no backplane reset */
/* SBSDIO_FUNC1_CHIPCLKCSR */
#define SBSDIO_FORCE_ALP 0x01 /* Force ALP request to backplane */
#define SBSDIO_FORCE_HT 0x02 /* Force HT request to backplane */
#define SBSDIO_FORCE_ILP 0x04 /* Force ILP request to backplane */
#define SBSDIO_ALP_AVAIL_REQ 0x08 /* Make ALP ready (power up xtal) */
#define SBSDIO_HT_AVAIL_REQ 0x10 /* Make HT ready (power up PLL) */
#define SBSDIO_FORCE_HW_CLKREQ_OFF 0x20 /* Squelch clock requests from HW */
#define SBSDIO_ALP_AVAIL 0x40 /* Status: ALP is ready */
#define SBSDIO_HT_AVAIL 0x80 /* Status: HT is ready */
/* In rev8, actual avail bits followed original docs */
#define SBSDIO_Rev8_HT_AVAIL 0x40
#define SBSDIO_Rev8_ALP_AVAIL 0x80
#define SBSDIO_AVBITS (SBSDIO_HT_AVAIL | SBSDIO_ALP_AVAIL)
#define SBSDIO_ALPAV(regval) ((regval) & SBSDIO_AVBITS)
#define SBSDIO_HTAV(regval) (((regval) & SBSDIO_AVBITS) == SBSDIO_AVBITS)
#define SBSDIO_ALPONLY(regval) (SBSDIO_ALPAV(regval) && !SBSDIO_HTAV(regval))
#define SBSDIO_CLKAV(regval, alponly) (SBSDIO_ALPAV(regval) && \
(alponly ? 1 : SBSDIO_HTAV(regval)))
/* SBSDIO_FUNC1_SDIOPULLUP */
#define SBSDIO_PULLUP_D0 0x01 /* Enable D0/MISO pullup */
#define SBSDIO_PULLUP_D1 0x02 /* Enable D1/INT# pullup */
#define SBSDIO_PULLUP_D2 0x04 /* Enable D2 pullup */
#define SBSDIO_PULLUP_CMD 0x08 /* Enable CMD/MOSI pullup */
#define SBSDIO_PULLUP_ALL 0x0f /* All valid bits */
/* function 1 OCP space */
#define SBSDIO_SB_OFT_ADDR_MASK 0x07FFF /* sb offset addr is <= 15 bits, 32k */
#define SBSDIO_SB_OFT_ADDR_LIMIT 0x08000
#define SBSDIO_SB_ACCESS_2_4B_FLAG 0x08000 /* with b15, maps to 32-bit SB access */
/* some duplication with sbsdpcmdev.h here */
/* valid bits in SBSDIO_FUNC1_SBADDRxxx regs */
#define SBSDIO_SBADDRLOW_MASK 0x80 /* Valid bits in SBADDRLOW */
#define SBSDIO_SBADDRMID_MASK 0xff /* Valid bits in SBADDRMID */
#define SBSDIO_SBADDRHIGH_MASK 0xffU /* Valid bits in SBADDRHIGH */
#define SBSDIO_SBWINDOW_MASK 0xffff8000 /* Address bits from SBADDR regs */
/* direct(mapped) cis space */
#define SBSDIO_CIS_BASE_COMMON 0x1000 /* MAPPED common CIS address */
#ifdef BCMSPI
#define SBSDIO_CIS_SIZE_LIMIT 0x100 /* maximum bytes in one spi CIS */
#else
#define SBSDIO_CIS_SIZE_LIMIT 0x200 /* maximum bytes in one CIS */
#endif /* !BCMSPI */
#define SBSDIO_OTP_CIS_SIZE_LIMIT 0x078 /* maximum bytes OTP CIS */
#define SBSDIO_CIS_OFT_ADDR_MASK 0x1FFFF /* cis offset addr is < 17 bits */
#define SBSDIO_CIS_MANFID_TUPLE_LEN 6 /* manfid tuple length, include tuple,
* link bytes
*/
/* indirect cis access (in sprom) */
#define SBSDIO_SPROM_CIS_OFFSET 0x8 /* 8 control bytes first, CIS starts from
* 8th byte
*/
#define SBSDIO_BYTEMODE_DATALEN_MAX 64 /* sdio byte mode: maximum length of one
* data comamnd
*/
#define SBSDIO_CORE_ADDR_MASK 0x1FFFF /* sdio core function one address mask */
#endif /* _SBSDIO_H */

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/*
* BRCM SDIOH (host controller) core hardware definitions.
*
* SDIOH support 1bit, 4 bit SDIO mode as well as SPI mode.
*
* $Id: sbsdioh.h 241182 2011-02-17 21:50:03Z gmo $
* Copyright(c) 2003 Broadcom Corporation
*/
#ifndef _SBSDIOH_H
#define _SBSDIOH_H
/* cpp contortions to concatenate w/arg prescan */
#ifndef PAD
#define _PADLINE(line) pad ## line
#define _XSTR(line) _PADLINE(line)
#define PAD _XSTR(__LINE__)
#endif /* PAD */
typedef volatile struct {
uint32 devcontrol; /* device control */
uint32 PAD[15]; /* PADDING old codec registers */
/* sdioh registers */
uint32 mode; /* 0x40: sd mode: SDIO1/SDIO4/SPI */
uint32 delay; /* 0x44: various clock config */
uint32 rdto; /* 0x48: read timeout value before SDERROR.ReadTimeOut
* is generated
*/
uint32 rbto; /* 0x4c: response busy timeout value before SDERROR.BusyTimeOut
* is generated
*/
uint32 test; /* 0x50: test register to force bad CRC */
uint32 arvm; /* 0x54: auto response value and mask */
uint32 error; /* 0x58: Error */
uint32 errormask; /* 0x5c: Error mask */
uint32 cmddat; /* 0x60: SDIO CMD data */
uint32 cmdl; /* 0x64: SDIO CMD argument */
uint32 fifodata; /* 0x68: SDIO fifo data, little endian, changable
* in mode register
*/
uint32 respq; /* 0x6c: response queue */
uint32 ct_cmddat; /* 0x70: SDIO CMD data for cutthrough commands */
uint32 ct_cmdl; /* 0x74: SDIO CMD argument for cutthrough commands */
uint32 ct_fifodata; /* 0x78: SDIO fifo data for cutthrough commands,
* little endian only
*/
uint32 PAD;
uint32 ap_cmddat; /* 0x80: SDIO CMD data for append commands */
uint32 ap_cmdl; /* 0x84: SDIO CMD argument for append commands */
uint32 ap_fifodata; /* 0x88: SDIO fifo data for append commands, little endian only */
uint32 PAD;
uint32 intstatus; /* 0x90: interrupt status */
uint32 intmask; /* 0x94: interrupt mask */
uint32 PAD;
uint32 debuginfo; /* 0x9c: debug register */
uint32 fifoctl; /* 0xa0: fifo control */
uint32 blocksize; /* 0xa4: cmd53 block mode block size */
uint32 PAD[86];
dma32regp_t dmaregs; /* 0x200 - 0x21C */
} sdioh_regs_t;
/* devcontrol */
#define CODEC_DEVCTRL_SDIOH 0x4000 /* 1: config codec to SDIOH mode,
* 0: normal codec mode
*/
/* mode */
#define MODE_DONT_WAIT_DMA 0x2000 /* diag only: in receive DMA mode, Cmdatadone
* will be generated when data transfer done
*/
#define MODE_BIG_ENDIAN 0x1000 /* 1: big endian, 0: small endian */
#define MODE_STOP_ALL_CLK 0x0800 /* diag only: 1: stop all SD clock */
#define MODE_PRECMD_CNT_EN 0x0400 /* 1: enable precmd count,
* 0: disable precmd count
*/
#define MODE_CLK_OUT_EN 0x0200 /* 0/1: en/disable the clock output to sdio bus */
#define MODE_USE_EXT_CLK 0x0100 /* use external clock or not */
#define MODE_CLK_DIV_MASK 0x00f0 /* divide host clock by 2*this field */
#define MODE_OP_MASK 0x000f /* mode is [3:0] bits */
#define MODE_OP_SDIO4BIT 2 /* SDIO 4 bit mode */
#define MODE_OP_SDIO1BIT 1 /* SDIO 1 bit mode */
#define MODE_OP_SPI 0 /* SPI mode */
#define MODE_HIGHSPEED_EN 0x10000 /* Enable High-Speed clocking Mode. */
/* delay */
#define DLY_CLK_COUNT_PRE_M 0x0000ffff /* dynamic clock: pre clock on cycles before tx */
#define DLY_CLK_COUNT_PRE_O 0
#define DLY_TX_START_COUNT_M 0xffff0000 /* DMA mode only: wait cycle before transferring
* non-empty fifo
*/
#define DLY_TX_START_COUNT_O 23
/* test */
#define TEST_BAD_CMD_CRC 0x1 /* force bad CMD crc */
#define TEST_BAD_DAT_CRC 0x2 /* force bad DAT crc */
/* arvm */
#define AR_MASK_OFT 8 /* CMD53 auto response mask */
#define AR_VAL 0x00ff /* CMD53 expected value of auto response,
* after mask
*/
/* cmd dat */
#define CMDAT_INDEX_M 0x0000003f /* command index */
#define CMDAT_EXP_RSPTYPE_M 0x000001c0 /* expected response type */
#define CMDAT_EXP_RSPTYPE_O 6
#define CMDAT_DAT_EN_M 0x00000200 /* data command flag */
#define CMDAT_DAT_EN_O 9
#define CMDAT_DAT_WR_M 0x00000400 /* 0: read from SD device,
* 1: write to SD device
*/
#define CMDAT_DAT_WR_O 10
#define CMDAT_DMA_MODE_M 0x00000800 /* 0: pio, 1: dma */
#define CMDAT_DMA_MODE_O 11
#define CMDAT_ARC_EN_M 0x00001000 /* auto response check enable/disable */
#define CMDAT_ARC_EN_O 12
#define CMDAT_EXP_BUSY_M 0x00002000 /* R1b only: expect busy after response */
#define CMDAT_EXP_BUSY_O 13
#define CMDAT_NO_RSP_CRC_CHK_M 0x00004000 /* disable response crc checking */
#define CMDAT_NO_RSP_CRC_CHK_O 14
#define CMDAT_NO_RSP_CDX_CHK_M 0x00008000 /* disable response command index checking */
#define CMDAT_NO_RSP_CDX_CHK_O 15
#define CMDAT_DAT_TX_CNT_M 0x1fff0000 /* total number of bytes to transfer */
#define CMDAT_DAT_TX_CNT_O 16
#define CMDAT_DATLEN_PIO 64 /* data length limit for pio mode */
#define CMDAT_DATLEN_DMA_NON53 512 /* data length limit for DMA mode non cmd53 */
#define CMDAT_DATLEN_DMA_53 8096 /* data length limit for DMA mode cmd53 */
#define CMDAT_APPEND_EN_M 0x20000000 /* enable sdioh to append a command */
#define CMDAT_APPEND_EN_O 29
#define CMDAT_ABORT_M 0x40000000 /* abort data */
#define CMDAT_ABORT_O 30
#define CMDAT_BLK_EN_M 0x80000000 /* use block mode */
#define CMDAT_BLK_EN_O 31
/* error and error_mask */
#define ERROR_RSP_CRC 0x0001 /* response crc error */
#define ERROR_RSP_TIME 0x0002 /* response time error */
#define ERROR_RSP_DBIT 0x0004 /* response D bit error */
#define ERROR_RSP_EBIT 0x0008 /* response E bit error */
#define ERROR_DAT_CRC 0x0010 /* data r/w crc error */
#define ERROR_DAT_SBIT 0x0020 /* receive data START bir error */
#define ERROR_DAT_EBIT 0x0040 /* receive data END bit error */
#define ERROR_DAT_RSP_S 0x0080 /* data crc response START bit error */
#define ERROR_DAT_RSP_E 0x0100 /* data crc response END bit error */
#define ERROR_DAT_RSP_UNKNOWN 0x0200 /* data response unknown, not 101 or 010 */
#define ERROR_DAT_RSP_TURNARD 0x0400 /* no 2 turnaround cycle between WRITE and
* CRC reponse
*/
#define ERROR_DAT_READ_TO 0x0800 /* data read timeout */
#define ERROR_SPI_TOKEN_UNK 0x1000 /* SPI token unknown */
#define ERROR_SPI_TOKEN_BAD 0x2000 /* SPI error token received */
#define ERROR_SPI_ET_OUTRANGE 0x4000 /* SPI error token: out of range */
#define ERROR_SPI_ET_ECC 0x8000 /* SPI error token: ECC failed */
#define ERROR_SPI_ET_CC 0x010000 /* SPI error token: cc error */
#define ERROR_SPI_ET_ERR 0x020000 /* SPI error token: error */
#define ERROR_AUTO_RSP_CHK 0x040000 /* auto response check error */
#define ERROR_RSP_BUSY_TO 0x080000 /* busy timeout for RBTO */
#define ERROR_RSP_CMDIDX_BAD 0x100000 /* response command index error */
/* intstatus and intmask */
#define INT_CMD_DAT_DONE 0x0001 /* sticky, sdio command/data xfer done */
#define INT_HOST_BUSY 0x0002 /* host busy */
#define INT_DEV_INT 0x0004 /* sdio card interrupt recieved */
#define INT_ERROR_SUM 0x0008 /* logic OR of Error register masked by ErrorMask */
#define INT_CARD_INS 0x0010 /* card inserted */
#define INT_CARD_GONE 0x0020 /* card removed */
#define INT_CMDBUSY_CUTTHRU 0x0040 /* sdioh is busy writing to cmdl_cutthru register */
#define INT_CMDBUSY_APPEND 0x0080 /* this bit is clear when writing cmdl,
* and set when APPEND starts
*/
#define INT_CARD_PRESENT 0x0100 /* card is present */
#define INT_STD_PCI_DESC 0x0400 /* standard DMA engine definition */
#define INT_STD_PCI_DATA 0x0800 /* standard DMA engine definition */
#define INT_STD_DESC_ERR 0x1000 /* standard DMA engine definition */
#define INT_STD_RCV_DESC_UF 0x2000 /* standard DMA engine definition */
#define INT_STD_RCV_FIFO_OF 0x4000 /* standard DMA engine definition */
#define INT_STD_XMT_FIFO_UF 0x8000 /* standard DMA engine definition */
#define INT_RCV_INT 0x00010000 /* standard DMA engine definition */
#define INT_XMT_INT 0x01000000 /* standard DMA engine definition */
/* debuginfo */
#define DBGI_REMAIN_COUNT 0x00001fff /* remaining count for data comand,
* change on the fly
*/
#define DBGI_CUR_ADDR 0xCfffE000 /* current address of CDM53 */
#define DBGI_CARD_WASBUSY 0x40000000 /* receive card busy signal on data line */
#define DBGI_R1B_DETECTED 0x80000000 /* R1B detected, overwritten by next cmd's status */
/* fifoctl(rcv/xmt) */
#define FIFO_RCV_BUF_RDY 0x10 /* HW set 1 when data are ready and avaiable in
* FIFO, write 1 before read RCVFIFODATA
*/
#define FIFO_XMT_BYTE_VALID 0x0f /* which bit is valid in all subsequent writes to
* xmtfifodata
*/
#define FIFO_VALID_BYTE1 0x01 /* byte 0 valid */
#define FIFO_VALID_BYTE2 0x02 /* byte 1 valid */
#define FIFO_VALID_BYTE3 0x04 /* byte 2 valid */
#define FIFO_VALID_BYTE4 0x08 /* byte 3 valid */
#define FIFO_VALID_ALL 0x0f /* all four bytes are valid */
#define SDIOH_MODE_PIO 0 /* pio mode */
#define SDIOH_MODE_DMA 1 /* dma mode */
#define SDIOH_CMDTYPE_NORMAL 0 /* normal command */
#define SDIOH_CMDTYPE_APPEND 1 /* append command */
#define SDIOH_CMDTYPE_CUTTHRU 2 /* cut through command */
#define SDIOH_DMA_START_EARLY 0
#define SDIOH_DMA_START_LATE 1
#define SDIOH_DMA_TX 1
#define SDIOH_DMA_RX 2
#define SDIOH_BLOCK_SIZE_MIN 4
#define SDIOH_BLOCK_SIZE_MAX 0x200
#define SDIOH_SB_ENUM_OFFSET 0x1000 /* sdioh-codec core SB address inside pci-sdioh
* controller
*/
#define SDIOH_HOST_SUPPORT_OCR 0xfff000 /* supported OCR by host controller */
#define RESP_TYPE_NONE 0
#define RESP_TYPE_R1 1
#define RESP_TYPE_R2 2
#define RESP_TYPE_R3 3
#define RESP_TYPE_R4 4
#define RESP_TYPE_R5 5
#define RESP_TYPE_R6 6
/* SDCMDAT Register */
#define SDIOH_CMD_INDEX_M BITFIELD_MASK(6) /* Bits [5:0] - Command number */
#define SDIOH_CMD_INDEX_S 0
#define SDIOH_CMD_RESP_TYPE_M BITFIELD_MASK(3) /* Bits [8:6] - Response type */
#define SDIOH_CMD_RESP_TYPE_S 6
#define SDIOH_CMD_DATA_EN_M BITFIELD_MASK(1) /* Bit 9 - Using DAT line */
#define SDIOH_CMD_DATA_EN_S 9
#define SDIOH_CMD_DATWR_M BITFIELD_MASK(1) /* Bit 10 - Data Write */
#define SDIOH_CMD_DATWR_S 10
#define SDIOH_CMD_DMAMODE_M BITFIELD_MASK(1) /* Bit 11 - DMA Mode */
#define SDIOH_CMD_DMAMODE_S 11
#define SDIOH_CMD_ARC_EN_M BITFIELD_MASK(1) /* Bit 12 - Auto Response Checking */
#define SDIOH_CMD_ARC_EN_S 12
#define SDIOH_CMD_EXP_BSY_M BITFIELD_MASK(1) /* Bit 13 - Expect Busy (R1b) */
#define SDIOH_CMD_EXP_BSY_S 13
#define SDIOH_CMD_CRC_DIS_M BITFIELD_MASK(1) /* Bit 14 - CRC disable */
#define SDIOH_CMD_CRC_DIS_S 14
#define SDIOH_CMD_INDEX_DIS_M BITFIELD_MASK(1) /* Bit 15 - Disable index checking */
#define SDIOH_CMD_INDEX_DIS_S 15
#define SDIOH_CMD_TR_COUNT_M BITFIELD_MASK(13) /* Bits [28:16] - Transfer Count */
#define SDIOH_CMD_TR_COUNT_S 16
#define SDIOH_CMD_APPEND_EN_M BITFIELD_MASK(1) /* Bit 29 - Append enable */
#define SDIOH_CMD_APPEND_EN_S 29
#define SDIOH_CMD_ABORT_EN_M BITFIELD_MASK(1) /* Bit 30 - Abort enable */
#define SDIOH_CMD_ABORT_EN_S 30
#define SDIOH_CMD_BLKMODE_EN_M BITFIELD_MASK(1) /* Bit 31 - Blockmode enable */
#define SDIOH_CMD_BLKMODE_EN_S 31
/* intstatus and intmask */
#define INT_CMD_DAT_DONE_M BITFIELD_MASK(1) /* Bit 0: sticky,
* sdio command/data xfer done
*/
#define INT_CMD_DAT_DONE_S 0
#define INT_HOST_BUSY_M BITFIELD_MASK(1) /* Bit 1: host busy */
#define INT_HOST_BUSY_S 1
#define INT_DEV_INT_M BITFIELD_MASK(1) /* Bit 2: sdio dev interrupt recieved */
#define INT_DEV_INT_S 2
#define INT_ERROR_SUM_M BITFIELD_MASK(1) /* Bit 3: OR of Error reg
* masked by ErrorMask
*/
#define INT_ERROR_SUM_S 3
#define INT_CARD_INS_M BITFIELD_MASK(1) /* Bit 4: dev inserted */
#define INT_CARD_INS_S 4
#define INT_CARD_GONE_M BITFIELD_MASK(1) /* Bit 5: dev removed */
#define INT_CARD_GONE_S 5
#define INT_CMDBUSY_CUTTHRU_M BITFIELD_MASK(1) /* sdioh is busy writing to cmdl_cutthru reg
*/
#define INT_CMDBUSY_CUTTHRU_S 6
#define INT_CMDBUSY_APPEND_M BITFIELD_MASK(1) /* this bit is clear when writing cmdl, */
#define INT_CMDBUSY_APPEND_S 7 /* and set when APPEND starts */
#define INT_RCV_INT_M BITFIELD_MASK(1) /* Receive DMA Interrupt */
#define INT_RCV_INT_S 16
#define INT_XMT_INT_M BITFIELD_MASK(1) /* Transmit DMA Interrupt */
#define INT_XMT_INT_S 24
/* SDBLOCK Register */
#define SDBLOCK_M BITFIELD_MASK(10) /* Bits [9:0] Blocksize */
#define SDBLOCK_S 0
#define SD1_MODE 0x1 /* SD Host Cntrlr Spec */
#define SD4_MODE 0x2 /* SD Host Cntrlr Spec */
#endif /* _SBSDIOH_H */

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/*
* Broadcom SiliconBackplane SDIO/PCMCIA hardware-specific
* device core support
*
* $Copyright Open 2005 Broadcom Corporation$
*
* $Id: sbsdpcmdev.h 391685 2013-03-19 03:39:02Z $
*/
#ifndef _sbsdpcmdev_h_
#define _sbsdpcmdev_h_
/* cpp contortions to concatenate w/arg prescan */
#ifndef PAD
#define _PADLINE(line) pad ## line
#define _XSTR(line) _PADLINE(line)
#define PAD _XSTR(__LINE__)
#endif /* PAD */
typedef volatile struct {
dma64regs_t xmt; /* dma tx */
uint32 PAD[2];
dma64regs_t rcv; /* dma rx */
uint32 PAD[2];
} dma64p_t;
/* dma64 sdiod corerev >= 1 */
typedef volatile struct {
dma64p_t dma64regs[2];
dma64diag_t dmafifo; /* DMA Diagnostic Regs, 0x280-0x28c */
uint32 PAD[92];
} sdiodma64_t;
/* dma32 sdiod corerev == 0 */
typedef volatile struct {
dma32regp_t dma32regs[2]; /* dma tx & rx, 0x200-0x23c */
dma32diag_t dmafifo; /* DMA Diagnostic Regs, 0x240-0x24c */
uint32 PAD[108];
} sdiodma32_t;
/* dma32 regs for pcmcia core */
typedef volatile struct {
dma32regp_t dmaregs; /* DMA Regs, 0x200-0x21c, rev8 */
dma32diag_t dmafifo; /* DMA Diagnostic Regs, 0x220-0x22c */
uint32 PAD[116];
} pcmdma32_t;
/* core registers */
typedef volatile struct {
uint32 corecontrol; /* CoreControl, 0x000, rev8 */
uint32 corestatus; /* CoreStatus, 0x004, rev8 */
uint32 PAD[1];
uint32 biststatus; /* BistStatus, 0x00c, rev8 */
/* PCMCIA access */
uint16 pcmciamesportaladdr; /* PcmciaMesPortalAddr, 0x010, rev8 */
uint16 PAD[1];
uint16 pcmciamesportalmask; /* PcmciaMesPortalMask, 0x014, rev8 */
uint16 PAD[1];
uint16 pcmciawrframebc; /* PcmciaWrFrameBC, 0x018, rev8 */
uint16 PAD[1];
uint16 pcmciaunderflowtimer; /* PcmciaUnderflowTimer, 0x01c, rev8 */
uint16 PAD[1];
/* interrupt */
uint32 intstatus; /* IntStatus, 0x020, rev8 */
uint32 hostintmask; /* IntHostMask, 0x024, rev8 */
uint32 intmask; /* IntSbMask, 0x028, rev8 */
uint32 sbintstatus; /* SBIntStatus, 0x02c, rev8 */
uint32 sbintmask; /* SBIntMask, 0x030, rev8 */
uint32 funcintmask; /* SDIO Function Interrupt Mask, SDIO rev4 */
uint32 PAD[2];
uint32 tosbmailbox; /* ToSBMailbox, 0x040, rev8 */
uint32 tohostmailbox; /* ToHostMailbox, 0x044, rev8 */
uint32 tosbmailboxdata; /* ToSbMailboxData, 0x048, rev8 */
uint32 tohostmailboxdata; /* ToHostMailboxData, 0x04c, rev8 */
/* synchronized access to registers in SDIO clock domain */
uint32 sdioaccess; /* SdioAccess, 0x050, rev8 */
uint32 PAD[3];
/* PCMCIA frame control */
uint8 pcmciaframectrl; /* pcmciaFrameCtrl, 0x060, rev8 */
uint8 PAD[3];
uint8 pcmciawatermark; /* pcmciaWaterMark, 0x064, rev8 */
uint8 PAD[155];
/* interrupt batching control */
uint32 intrcvlazy; /* IntRcvLazy, 0x100, rev8 */
uint32 PAD[3];
/* counters */
uint32 cmd52rd; /* Cmd52RdCount, 0x110, rev8, SDIO: cmd52 reads */
uint32 cmd52wr; /* Cmd52WrCount, 0x114, rev8, SDIO: cmd52 writes */
uint32 cmd53rd; /* Cmd53RdCount, 0x118, rev8, SDIO: cmd53 reads */
uint32 cmd53wr; /* Cmd53WrCount, 0x11c, rev8, SDIO: cmd53 writes */
uint32 abort; /* AbortCount, 0x120, rev8, SDIO: aborts */
uint32 datacrcerror; /* DataCrcErrorCount, 0x124, rev8, SDIO: frames w/bad CRC */
uint32 rdoutofsync; /* RdOutOfSyncCount, 0x128, rev8, SDIO/PCMCIA: Rd Frm OOS */
uint32 wroutofsync; /* RdOutOfSyncCount, 0x12c, rev8, SDIO/PCMCIA: Wr Frm OOS */
uint32 writebusy; /* WriteBusyCount, 0x130, rev8, SDIO: dev asserted "busy" */
uint32 readwait; /* ReadWaitCount, 0x134, rev8, SDIO: read: no data avail */
uint32 readterm; /* ReadTermCount, 0x138, rev8, SDIO: rd frm terminates */
uint32 writeterm; /* WriteTermCount, 0x13c, rev8, SDIO: wr frm terminates */
uint32 PAD[40];
uint32 clockctlstatus; /* ClockCtlStatus, 0x1e0, rev8 */
uint32 PAD[7];
/* DMA engines */
volatile union {
pcmdma32_t pcm32;
sdiodma32_t sdiod32;
sdiodma64_t sdiod64;
} dma;
/* SDIO/PCMCIA CIS region */
char cis[512]; /* 512 byte CIS, 0x400-0x5ff, rev6 */
/* PCMCIA function control registers */
char pcmciafcr[256]; /* PCMCIA FCR, 0x600-6ff, rev6 */
uint16 PAD[55];
/* PCMCIA backplane access */
uint16 backplanecsr; /* BackplaneCSR, 0x76E, rev6 */
uint16 backplaneaddr0; /* BackplaneAddr0, 0x770, rev6 */
uint16 backplaneaddr1; /* BackplaneAddr1, 0x772, rev6 */
uint16 backplaneaddr2; /* BackplaneAddr2, 0x774, rev6 */
uint16 backplaneaddr3; /* BackplaneAddr3, 0x776, rev6 */
uint16 backplanedata0; /* BackplaneData0, 0x778, rev6 */
uint16 backplanedata1; /* BackplaneData1, 0x77a, rev6 */
uint16 backplanedata2; /* BackplaneData2, 0x77c, rev6 */
uint16 backplanedata3; /* BackplaneData3, 0x77e, rev6 */
uint16 PAD[31];
/* sprom "size" & "blank" info */
uint16 spromstatus; /* SPROMStatus, 0x7BE, rev2 */
uint16 PAD[32];
uint32 f3corectl; /* F3(BT) Core control, 0x800, rev8 */
uint32 f3corestatus; /* F3 Core Status, 0x804, rev8 */
uint32 f3intstatus; /* F3 Interrupt Status, 0x808, rev8 */
uint32 btinten; /* Bt interrupt enable, 0x80c, rev8 */
uint32 PAD[9];
uint32 btintrcvlazy;
uint32 PAD[430];
/* Sonics SiliconBackplane registers */
sbconfig_t sbconfig; /* SbConfig Regs, 0xf00-0xfff, rev8 */
} sdpcmd_regs_t;
/* corecontrol */
#define CC_CISRDY (1 << 0) /* CIS Ready */
#define CC_BPRESEN (1 << 1) /* CCCR RES signal causes backplane reset */
#define CC_F2RDY (1 << 2) /* set CCCR IOR2 bit */
#define CC_CLRPADSISO (1 << 3) /* clear SDIO pads isolation bit (rev 11) */
#define CC_XMTDATAAVAIL_MODE (1 << 4) /* data avail generates an interrupt */
#define CC_XMTDATAAVAIL_CTRL (1 << 5) /* data avail interrupt ctrl */
/* corestatus */
#define CS_PCMCIAMODE (1 << 0) /* Device Mode; 0=SDIO, 1=PCMCIA */
#define CS_SMARTDEV (1 << 1) /* 1=smartDev enabled */
#define CS_F2ENABLED (1 << 2) /* 1=host has enabled the device */
#define PCMCIA_MES_PA_MASK 0x7fff /* PCMCIA Message Portal Address Mask */
#define PCMCIA_MES_PM_MASK 0x7fff /* PCMCIA Message Portal Mask Mask */
#define PCMCIA_WFBC_MASK 0xffff /* PCMCIA Write Frame Byte Count Mask */
#define PCMCIA_UT_MASK 0x07ff /* PCMCIA Underflow Timer Mask */
/* intstatus */
#define I_SMB_SW0 (1 << 0) /* To SB Mail S/W interrupt 0 */
#define I_SMB_SW1 (1 << 1) /* To SB Mail S/W interrupt 1 */
#define I_SMB_SW2 (1 << 2) /* To SB Mail S/W interrupt 2 */
#define I_SMB_SW3 (1 << 3) /* To SB Mail S/W interrupt 3 */
#define I_SMB_SW_MASK 0x0000000f /* To SB Mail S/W interrupts mask */
#define I_SMB_SW_SHIFT 0 /* To SB Mail S/W interrupts shift */
#define I_HMB_SW0 (1 << 4) /* To Host Mail S/W interrupt 0 */
#define I_HMB_SW1 (1 << 5) /* To Host Mail S/W interrupt 1 */
#define I_HMB_SW2 (1 << 6) /* To Host Mail S/W interrupt 2 */
#define I_HMB_SW3 (1 << 7) /* To Host Mail S/W interrupt 3 */
#define I_HMB_SW_MASK 0x000000f0 /* To Host Mail S/W interrupts mask */
#define I_HMB_SW_SHIFT 4 /* To Host Mail S/W interrupts shift */
#define I_WR_OOSYNC (1 << 8) /* Write Frame Out Of Sync */
#define I_RD_OOSYNC (1 << 9) /* Read Frame Out Of Sync */
#define I_PC (1 << 10) /* descriptor error */
#define I_PD (1 << 11) /* data error */
#define I_DE (1 << 12) /* Descriptor protocol Error */
#define I_RU (1 << 13) /* Receive descriptor Underflow */
#define I_RO (1 << 14) /* Receive fifo Overflow */
#define I_XU (1 << 15) /* Transmit fifo Underflow */
#define I_RI (1 << 16) /* Receive Interrupt */
#define I_BUSPWR (1 << 17) /* SDIO Bus Power Change (rev 9) */
#define I_XMTDATA_AVAIL (1 << 23) /* bits in fifo */
#define I_XI (1 << 24) /* Transmit Interrupt */
#define I_RF_TERM (1 << 25) /* Read Frame Terminate */
#define I_WF_TERM (1 << 26) /* Write Frame Terminate */
#define I_PCMCIA_XU (1 << 27) /* PCMCIA Transmit FIFO Underflow */
#define I_SBINT (1 << 28) /* sbintstatus Interrupt */
#define I_CHIPACTIVE (1 << 29) /* chip transitioned from doze to active state */
#define I_SRESET (1 << 30) /* CCCR RES interrupt */
#define I_IOE2 (1U << 31) /* CCCR IOE2 Bit Changed */
#define I_ERRORS (I_PC | I_PD | I_DE | I_RU | I_RO | I_XU) /* DMA Errors */
#define I_DMA (I_RI | I_XI | I_ERRORS)
/* sbintstatus */
#define I_SB_SERR (1 << 8) /* Backplane SError (write) */
#define I_SB_RESPERR (1 << 9) /* Backplane Response Error (read) */
#define I_SB_SPROMERR (1 << 10) /* Error accessing the sprom */
/* sdioaccess */
#define SDA_DATA_MASK 0x000000ff /* Read/Write Data Mask */
#define SDA_ADDR_MASK 0x000fff00 /* Read/Write Address Mask */
#define SDA_ADDR_SHIFT 8 /* Read/Write Address Shift */
#define SDA_WRITE 0x01000000 /* Write bit */
#define SDA_READ 0x00000000 /* Write bit cleared for Read */
#define SDA_BUSY 0x80000000 /* Busy bit */
/* sdioaccess-accessible register address spaces */
#define SDA_CCCR_SPACE 0x000 /* sdioAccess CCCR register space */
#define SDA_F1_FBR_SPACE 0x100 /* sdioAccess F1 FBR register space */
#define SDA_F2_FBR_SPACE 0x200 /* sdioAccess F2 FBR register space */
#define SDA_F1_REG_SPACE 0x300 /* sdioAccess F1 core-specific register space */
/* SDA_F1_REG_SPACE sdioaccess-accessible F1 reg space register offsets */
#define SDA_CHIPCONTROLDATA 0x006 /* ChipControlData */
#define SDA_CHIPCONTROLENAB 0x007 /* ChipControlEnable */
#define SDA_F2WATERMARK 0x008 /* Function 2 Watermark */
#define SDA_DEVICECONTROL 0x009 /* DeviceControl */
#define SDA_SBADDRLOW 0x00a /* SbAddrLow */
#define SDA_SBADDRMID 0x00b /* SbAddrMid */
#define SDA_SBADDRHIGH 0x00c /* SbAddrHigh */
#define SDA_FRAMECTRL 0x00d /* FrameCtrl */
#define SDA_CHIPCLOCKCSR 0x00e /* ChipClockCSR */
#define SDA_SDIOPULLUP 0x00f /* SdioPullUp */
#define SDA_SDIOWRFRAMEBCLOW 0x019 /* SdioWrFrameBCLow */
#define SDA_SDIOWRFRAMEBCHIGH 0x01a /* SdioWrFrameBCHigh */
#define SDA_SDIORDFRAMEBCLOW 0x01b /* SdioRdFrameBCLow */
#define SDA_SDIORDFRAMEBCHIGH 0x01c /* SdioRdFrameBCHigh */
/* SDA_F2WATERMARK */
#define SDA_F2WATERMARK_MASK 0x7f /* F2Watermark Mask */
/* SDA_SBADDRLOW */
#define SDA_SBADDRLOW_MASK 0x80 /* SbAddrLow Mask */
/* SDA_SBADDRMID */
#define SDA_SBADDRMID_MASK 0xff /* SbAddrMid Mask */
/* SDA_SBADDRHIGH */
#define SDA_SBADDRHIGH_MASK 0xff /* SbAddrHigh Mask */
/* SDA_FRAMECTRL */
#define SFC_RF_TERM (1 << 0) /* Read Frame Terminate */
#define SFC_WF_TERM (1 << 1) /* Write Frame Terminate */
#define SFC_CRC4WOOS (1 << 2) /* HW reports CRC error for write out of sync */
#define SFC_ABORTALL (1 << 3) /* Abort cancels all in-progress frames */
/* pcmciaframectrl */
#define PFC_RF_TERM (1 << 0) /* Read Frame Terminate */
#define PFC_WF_TERM (1 << 1) /* Write Frame Terminate */
/* intrcvlazy */
#define IRL_TO_MASK 0x00ffffff /* timeout */
#define IRL_FC_MASK 0xff000000 /* frame count */
#define IRL_FC_SHIFT 24 /* frame count */
/* rx header */
typedef volatile struct {
uint16 len;
uint16 flags;
} sdpcmd_rxh_t;
/* rx header flags */
#define RXF_CRC 0x0001 /* CRC error detected */
#define RXF_WOOS 0x0002 /* write frame out of sync */
#define RXF_WF_TERM 0x0004 /* write frame terminated */
#define RXF_ABORT 0x0008 /* write frame aborted */
#define RXF_DISCARD (RXF_CRC | RXF_WOOS | RXF_WF_TERM | RXF_ABORT) /* bad frame */
/* HW frame tag */
#define SDPCM_FRAMETAG_LEN 4 /* HW frametag: 2 bytes len, 2 bytes check val */
/* HW Extention tag for glomming */
/* 2 byte Pkt len, Frame channel, Frame Flags, 2byte hdr len, 2 byte pad len */
#define SDPCM_HWEXT_LEN 8
#endif /* _sbsdpcmdev_h_ */

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/*
* BCM47XX Sonics SiliconBackplane embedded ram core
*
* $Copyright Open Broadcom Corporation$
*
* $Id: sbsocram.h 271781 2011-07-13 20:00:06Z $
*/
#ifndef _SBSOCRAM_H
#define _SBSOCRAM_H
#ifndef _LANGUAGE_ASSEMBLY
#ifndef PAD
#define _PADLINE(line) pad ## line
#define _XSTR(line) _PADLINE(line)
#define PAD _XSTR(__LINE__)
#endif
typedef volatile struct sbsocramregs {
uint32 coreinfo;
uint32 bwalloc;
uint32 extracoreinfo;
uint32 biststat;
uint32 bankidx;
uint32 standbyctrl;
uint32 errlogstatus;
uint32 errlogaddr;
uint32 cambankidx;
uint32 cambankstandbyctrl;
uint32 cambankpatchctrl;
uint32 cambankpatchtblbaseaddr;
uint32 cambankcmdreg;
uint32 cambankdatareg;
uint32 cambankmaskreg;
uint32 PAD[1];
uint32 bankinfo;
uint32 PAD[15];
uint32 extmemconfig;
uint32 extmemparitycsr;
uint32 extmemparityerrdata;
uint32 extmemparityerrcnt;
uint32 extmemwrctrlandsize;
uint32 PAD[84];
uint32 workaround;
uint32 pwrctl;
uint32 PAD[133];
uint32 sr_control;
uint32 sr_status;
uint32 sr_address;
uint32 sr_data;
} sbsocramregs_t;
#endif
#define SR_COREINFO 0x00
#define SR_BWALLOC 0x04
#define SR_BISTSTAT 0x0c
#define SR_BANKINDEX 0x10
#define SR_BANKSTBYCTL 0x14
#define SR_PWRCTL 0x1e8
#define SRCI_PT_MASK 0x00070000
#define SRCI_PT_SHIFT 16
#define SRCI_PT_OCP_OCP 0
#define SRCI_PT_AXI_OCP 1
#define SRCI_PT_ARM7AHB_OCP 2
#define SRCI_PT_CM3AHB_OCP 3
#define SRCI_PT_AXI_AXI 4
#define SRCI_PT_AHB_AXI 5
#define SRCI_LSS_MASK 0x00f00000
#define SRCI_LSS_SHIFT 20
#define SRCI_LRS_MASK 0x0f000000
#define SRCI_LRS_SHIFT 24
#define SRCI_MS0_MASK 0xf
#define SR_MS0_BASE 16
#define SRCI_ROMNB_MASK 0xf000
#define SRCI_ROMNB_SHIFT 12
#define SRCI_ROMBSZ_MASK 0xf00
#define SRCI_ROMBSZ_SHIFT 8
#define SRCI_SRNB_MASK 0xf0
#define SRCI_SRNB_SHIFT 4
#define SRCI_SRBSZ_MASK 0xf
#define SRCI_SRBSZ_SHIFT 0
#define SR_BSZ_BASE 14
#define SRSC_SBYOVR_MASK 0x80000000
#define SRSC_SBYOVR_SHIFT 31
#define SRSC_SBYOVRVAL_MASK 0x60000000
#define SRSC_SBYOVRVAL_SHIFT 29
#define SRSC_SBYEN_MASK 0x01000000
#define SRSC_SBYEN_SHIFT 24
#define SRPC_PMU_STBYDIS_MASK 0x00000010
#define SRPC_PMU_STBYDIS_SHIFT 4
#define SRPC_STBYOVRVAL_MASK 0x00000008
#define SRPC_STBYOVRVAL_SHIFT 3
#define SRPC_STBYOVR_MASK 0x00000007
#define SRPC_STBYOVR_SHIFT 0
#define SRECC_NUM_BANKS_MASK 0x000000F0
#define SRECC_NUM_BANKS_SHIFT 4
#define SRECC_BANKSIZE_MASK 0x0000000F
#define SRECC_BANKSIZE_SHIFT 0
#define SRECC_BANKSIZE(value) (1 << (value))
#define SRCBPC_PATCHENABLE 0x80000000
#define SRP_ADDRESS 0x0001FFFC
#define SRP_VALID 0x8000
#define SRCMD_WRITE 0x00020000
#define SRCMD_READ 0x00010000
#define SRCMD_DONE 0x80000000
#define SRCMD_DONE_DLY 1000
#define SOCRAM_BANKINFO_SZMASK 0x7f
#define SOCRAM_BANKIDX_ROM_MASK 0x100
#define SOCRAM_BANKIDX_MEMTYPE_SHIFT 8
#define SOCRAM_MEMTYPE_RAM 0
#define SOCRAM_MEMTYPE_R0M 1
#define SOCRAM_MEMTYPE_DEVRAM 2
#define SOCRAM_BANKINFO_REG 0x40
#define SOCRAM_BANKIDX_REG 0x10
#define SOCRAM_BANKINFO_STDBY_MASK 0x400
#define SOCRAM_BANKINFO_STDBY_TIMER 0x800
#define SOCRAM_BANKINFO_DEVRAMSEL_SHIFT 13
#define SOCRAM_BANKINFO_DEVRAMSEL_MASK 0x2000
#define SOCRAM_BANKINFO_DEVRAMPRO_SHIFT 14
#define SOCRAM_BANKINFO_DEVRAMPRO_MASK 0x4000
#define SOCRAM_BANKINFO_SLPSUPP_SHIFT 15
#define SOCRAM_BANKINFO_SLPSUPP_MASK 0x8000
#define SOCRAM_BANKINFO_RETNTRAM_SHIFT 16
#define SOCRAM_BANKINFO_RETNTRAM_MASK 0x00010000
#define SOCRAM_BANKINFO_PDASZ_SHIFT 17
#define SOCRAM_BANKINFO_PDASZ_MASK 0x003E0000
#define SOCRAM_BANKINFO_DEVRAMREMAP_SHIFT 24
#define SOCRAM_BANKINFO_DEVRAMREMAP_MASK 0x01000000
#define SOCRAM_DEVRAMBANK_MASK 0xF000
#define SOCRAM_DEVRAMBANK_SHIFT 12
#define SOCRAM_BANKINFO_SZBASE 8192
#define SOCRAM_BANKSIZE_SHIFT 13
#endif

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/*
* SPROM format definitions for the Broadcom 47xx and 43xx chip family.
*
* $Id: sbsprom.h 241182 2011-02-17 21:50:03Z gmo $
* Copyright(c) 2002 Broadcom Corporation
*/
#ifndef _SBSPROM_H
#define _SBSPROM_H
#include "typedefs.h"
#include "bcmdevs.h"
/* A word is this many bytes */
#define SRW 2
/* offset into PCI config space for write enable bit */
#define CFG_SROM_WRITABLE_OFFSET 0x88
#define SROM_WRITEABLE 0x10
/* enumeration space consists of N contiguous 4Kbyte core register sets */
#define SBCORES_BASE 0x18000000
#define SBCORES_EACH 0x1000
/* offset from BAR0 for srom space */
#define SROM_BASE 4096
/* number of 2-byte words in srom */
#define SROM_SIZE 64
#define SROM_BYTES (SROM_SIZE * SRW)
#define MAX_FN 4
/* Word 0, Hardware control */
#define SROM_HWCTL 0
#define HW_FUNMSK 0x000f
#define HW_FCLK 0x0200
#define HW_CBM 0x0400
#define HW_PIMSK 0xf000
#define HW_PISHIFT 12
#define HW_4301PISHIFT 13
#define HW_PI4402 0x2
#define HW_FUN4401 0x0001
#define HW_FCLK4402 0x0000
/* Word 1, common-power/boot-rom */
#define SROM_COMMPW 1
/* boot rom present bit */
#define BR_PRESSHIFT 8
/* 15:9 for n; boot rom size is 2^(14 + n) bytes */
#define BR_SIZESHIFT 9
/* Word 2, SubsystemId */
#define SROM_SSID 2
/* Word 3, VendorId */
#define SROM_VID 3
/* Function 0 info, function info length */
#define SROM_FN0 4
#define SROM_FNSZ 8
/* Within each function: */
/* Word 0, deviceID */
#define SRFN_DID 0
/* Words 1-2, ClassCode */
#define SRFN_CCL 1
/* Word 2, D0 Power */
#define SRFN_CCHD0 2
/* Word 3, PME and D1D2D3 power */
#define SRFN_PMED123 3
#define PME_IL 0
#define PME_ENET0 1
#define PME_ENET1 2
#define PME_CODEC 3
#define PME_4402_ENET 0
#define PME_4402_CODEC 1
#define PME_4301_WL 2
#define PMEREP_4402_ENET (PMERD3CV | PMERD3CA | PMERD3H | PMERD2 | PMERD1 | PMERD0 | PME)
/* Word 4, Bar1 enable, pme reports */
#define SRFN_B1PMER 4
#define B1E 1
#define B1SZMSK 0xe
#define B1SZSH 1
#define PMERMSK 0x0ff0
#define PME 0x0010
#define PMERD0 0x0020
#define PMERD1 0x0040
#define PMERD2 0x0080
#define PMERD3H 0x0100
#define PMERD3CA 0x0200
#define PMERD3CV 0x0400
#define IGNCLKRR 0x0800
#define B0LMSK 0xf000
/* Words 4-5, Bar0 Sonics value */
#define SRFN_B0H 5
/* Words 6-7, CIS Pointer */
#define SRFN_CISL 6
#define SRFN_CISH 7
/* Words 36-38: iLine MAC address */
#define SROM_I_MACHI 36
#define SROM_I_MACMID 37
#define SROM_I_MACLO 38
/* Words 36-38: wireless0 MAC address on 43xx */
#define SROM_W0_MACHI 36
#define SROM_W0_MACMID 37
#define SROM_W0_MACLO 38
/* Words 39-41: enet0 MAC address */
#define SROM_E0_MACHI 39
#define SROM_E0_MACMID 40
#define SROM_E0_MACLO 41
/* Words 42-44: enet1 MAC address */
#define SROM_E1_MACHI 42
#define SROM_E1_MACMID 43
#define SROM_E1_MACLO 44
/* Words 42-44: wireless1 MAC address on 4309 */
#define SROM_W1_MACHI 42
#define SROM_W1_MACMID 43
#define SROM_W1_MACLO 44
#define SROM_EPHY 45
/* Word 46: BdRev & Antennas0/1 & ccLock for 430x */
#define SROM_REV_AA_LOCK 46
/* Words 47-51 wl0 PA bx */
#define SROM_WL0_PAB0 47
#define SROM_WL0_PAB1 48
#define SROM_WL0_PAB2 49
#define SROM_WL0_PAB3 50
#define SROM_WL0_PAB4 51
/* Word 52: wl0/wl1 MaxPower */
#define SROM_WL_MAXPWR 52
/* Words 53-55 wl1 PA bx */
#define SROM_WL1_PAB0 53
#define SROM_WL1_PAB1 54
#define SROM_WL1_PAB2 55
/* Woprd 56: itt */
#define SROM_ITT 56
/* Words 59-62: OEM Space */
#define SROM_WL_OEM 59
#define SROM_OEM_SIZE 4
/* Contents for the srom */
#define BU4710_SSID 0x0400
#define VSIM4710_SSID 0x0401
#define QT4710_SSID 0x0402
#define BU4610_SSID 0x0403
#define VSIM4610_SSID 0x0404
#define BU4307_SSID 0x0405
#define BCM94301CB_SSID 0x0406
#define BCM94301MP_SSID 0x0407
#define BCM94307MP_SSID 0x0408
#define AP4307_SSID 0x0409
#define BU4309_SSID 0x040a
#define BCM94309CB_SSID 0x040b
#define BCM94309MP_SSID 0x040c
#define AP4309_SSID 0x040d
#define BU4312_SSID 0x048a
#define BU4402_SSID 0x4402
#define CLASS_OTHER 0x8000
#define CLASS_ETHER 0x0000
#define CLASS_NET 0x0002
#define CLASS_COMM 0x0007
#define CLASS_MODEM 0x0300
#define CLASS_MIPS 0x3000
#define CLASS_PROC 0x000b
#define CLASS_FLASH 0x0100
#define CLASS_MEM 0x0005
#define CLASS_SERIALBUS 0x000c
#define CLASS_OHCI 0x0310
/* Broadcom IEEE MAC addresses are 00:90:4c:xx:xx:xx */
#define MACHI 0x90
#define MACMID_BU4710I 0x4c17
#define MACMID_BU4710E0 0x4c18
#define MACMID_BU4710E1 0x4c19
#define MACMID_94710R1I 0x4c1a
#define MACMID_94710R1E0 0x4c1b
#define MACMID_94710R1E1 0x4c1c
#define MACMID_94710R4I 0x4c1d
#define MACMID_94710R4E0 0x4c1e
#define MACMID_94710R4E1 0x4c1f
#define MACMID_94710DEVI 0x4c20
#define MACMID_94710DEVE0 0x4c21
#define MACMID_94710DEVE1 0x4c22
#define MACMID_BU4402 0x4c23
#define MACMID_BU4610I 0x4c24
#define MACMID_BU4610E0 0x4c25
#define MACMID_BU4610E1 0x4c26
#define MACMID_BU4307W 0x4c27
#define MACMID_BU4307E 0x4c28
#define MACMID_94301CB 0x4c29
#define MACMID_94301MP 0x4c2a
#define MACMID_94307MPW 0x4c2b
#define MACMID_94307MPE 0x4c2c
#define MACMID_AP4307W 0x4c2d
#define MACMID_AP4307E 0x4c2e
#define MACMID_BU4309W0 0x4c2f
#define MACMID_BU4309W1 0x4c30
#define MACMID_BU4309E 0x4c31
#define MACMID_94309CBW0 0x4c32
#define MACMID_94309CBW1 0x4c33
#define MACMID_94309MPW0 0x4c34
#define MACMID_94309MPW1 0x4c35
#define MACMID_94309MPE 0x4c36
#define MACMID_BU4401 0x4c37
/* Enet phy settings one or two singles or a dual */
/* Bits 4-0 : MII address for enet0 (0x1f for not there */
/* Bits 9-5 : MII address for enet1 (0x1f for not there */
/* Bit 14 : Mdio for enet0 */
/* Bit 15 : Mdio for enet1 */
/* bu4710 with only one phy on enet1 with address 7: */
#define SROM_EPHY_ONE 0x80ff
/* bu4710 with two individual phys, at 6 and 7, */
/* each mdio connected to its own mac: */
#define SROM_EPHY_TWO 0x80e6
/* bu4710 with a dual phy addresses 0 & 1, mdio-connected to enet0 */
#define SROM_EPHY_DUAL 0x0001
/* r1 board with a dual phy at 0, 1 (NOT swapped and mdc0 */
#define SROM_EPHY_R1 0x0010
/* r4 board with a single phy on enet0 at address 5 and a switch */
/* chip on enet1 (speciall case: 0x1e */
#define SROM_EPHY_R4 0x83e5
/* 4402 uses an internal phy at phyaddr 1; want mdcport == coreunit == 0 */
#define SROM_EPHY_INTERNAL 0x0001
/* 4307 uses an external phy at phyaddr 0; want mdcport == coreunit == 0 */
#define SROM_EPHY_ZERO 0x0000
#define SROM_VERS 0x0001
#endif /* _SBSPROM_H */

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/*
* SDIO spec header file
* Protocol and standard (common) device definitions
*
* $Copyright Open Broadcom Corporation$
*
* $Id: sdio.h 288543 2011-10-07 12:15:31Z $
*/
#ifndef _SDIO_H
#define _SDIO_H
/* CCCR structure for function 0 */
typedef volatile struct {
uint8 cccr_sdio_rev; /* RO, cccr and sdio revision */
uint8 sd_rev; /* RO, sd spec revision */
uint8 io_en; /* I/O enable */
uint8 io_rdy; /* I/O ready reg */
uint8 intr_ctl; /* Master and per function interrupt enable control */
uint8 intr_status; /* RO, interrupt pending status */
uint8 io_abort; /* read/write abort or reset all functions */
uint8 bus_inter; /* bus interface control */
uint8 capability; /* RO, card capability */
uint8 cis_base_low; /* 0x9 RO, common CIS base address, LSB */
uint8 cis_base_mid;
uint8 cis_base_high; /* 0xB RO, common CIS base address, MSB */
/* suspend/resume registers */
uint8 bus_suspend; /* 0xC */
uint8 func_select; /* 0xD */
uint8 exec_flag; /* 0xE */
uint8 ready_flag; /* 0xF */
uint8 fn0_blk_size[2]; /* 0x10(LSB), 0x11(MSB) */
uint8 power_control; /* 0x12 (SDIO version 1.10) */
uint8 speed_control; /* 0x13 */
} sdio_regs_t;
/* SDIO Device CCCR offsets */
#define SDIOD_CCCR_REV 0x00
#define SDIOD_CCCR_SDREV 0x01
#define SDIOD_CCCR_IOEN 0x02
#define SDIOD_CCCR_IORDY 0x03
#define SDIOD_CCCR_INTEN 0x04
#define SDIOD_CCCR_INTPEND 0x05
#define SDIOD_CCCR_IOABORT 0x06
#define SDIOD_CCCR_BICTRL 0x07
#define SDIOD_CCCR_CAPABLITIES 0x08
#define SDIOD_CCCR_CISPTR_0 0x09
#define SDIOD_CCCR_CISPTR_1 0x0A
#define SDIOD_CCCR_CISPTR_2 0x0B
#define SDIOD_CCCR_BUSSUSP 0x0C
#define SDIOD_CCCR_FUNCSEL 0x0D
#define SDIOD_CCCR_EXECFLAGS 0x0E
#define SDIOD_CCCR_RDYFLAGS 0x0F
#define SDIOD_CCCR_BLKSIZE_0 0x10
#define SDIOD_CCCR_BLKSIZE_1 0x11
#define SDIOD_CCCR_POWER_CONTROL 0x12
#define SDIOD_CCCR_SPEED_CONTROL 0x13
#define SDIOD_CCCR_UHSI_SUPPORT 0x14
#define SDIOD_CCCR_DRIVER_STRENGTH 0x15
#define SDIOD_CCCR_INTR_EXTN 0x16
/* Broadcom extensions (corerev >= 1) */
#define SDIOD_CCCR_BRCM_SEPINT 0xf2
/* cccr_sdio_rev */
#define SDIO_REV_SDIOID_MASK 0xf0 /* SDIO spec revision number */
#define SDIO_REV_CCCRID_MASK 0x0f /* CCCR format version number */
/* sd_rev */
#define SD_REV_PHY_MASK 0x0f /* SD format version number */
/* io_en */
#define SDIO_FUNC_ENABLE_1 0x02 /* function 1 I/O enable */
#define SDIO_FUNC_ENABLE_2 0x04 /* function 2 I/O enable */
/* io_rdys */
#define SDIO_FUNC_READY_1 0x02 /* function 1 I/O ready */
#define SDIO_FUNC_READY_2 0x04 /* function 2 I/O ready */
/* intr_ctl */
#define INTR_CTL_MASTER_EN 0x1 /* interrupt enable master */
#define INTR_CTL_FUNC1_EN 0x2 /* interrupt enable for function 1 */
#define INTR_CTL_FUNC2_EN 0x4 /* interrupt enable for function 2 */
/* intr_status */
#define INTR_STATUS_FUNC1 0x2 /* interrupt pending for function 1 */
#define INTR_STATUS_FUNC2 0x4 /* interrupt pending for function 2 */
/* io_abort */
#define IO_ABORT_RESET_ALL 0x08 /* I/O card reset */
#define IO_ABORT_FUNC_MASK 0x07 /* abort selction: function x */
/* bus_inter */
#define BUS_CARD_DETECT_DIS 0x80 /* Card Detect disable */
#define BUS_SPI_CONT_INTR_CAP 0x40 /* support continuous SPI interrupt */
#define BUS_SPI_CONT_INTR_EN 0x20 /* continuous SPI interrupt enable */
#define BUS_SD_DATA_WIDTH_MASK 0x03 /* bus width mask */
#define BUS_SD_DATA_WIDTH_4BIT 0x02 /* bus width 4-bit mode */
#define BUS_SD_DATA_WIDTH_1BIT 0x00 /* bus width 1-bit mode */
/* capability */
#define SDIO_CAP_4BLS 0x80 /* 4-bit support for low speed card */
#define SDIO_CAP_LSC 0x40 /* low speed card */
#define SDIO_CAP_E4MI 0x20 /* enable interrupt between block of data in 4-bit mode */
#define SDIO_CAP_S4MI 0x10 /* support interrupt between block of data in 4-bit mode */
#define SDIO_CAP_SBS 0x08 /* support suspend/resume */
#define SDIO_CAP_SRW 0x04 /* support read wait */
#define SDIO_CAP_SMB 0x02 /* support multi-block transfer */
#define SDIO_CAP_SDC 0x01 /* Support Direct commands during multi-byte transfer */
/* power_control */
#define SDIO_POWER_SMPC 0x01 /* supports master power control (RO) */
#define SDIO_POWER_EMPC 0x02 /* enable master power control (allow > 200mA) (RW) */
/* speed_control (control device entry into high-speed clocking mode) */
#define SDIO_SPEED_SHS 0x01 /* supports high-speed [clocking] mode (RO) */
#define SDIO_SPEED_EHS 0x02 /* enable high-speed [clocking] mode (RW) */
/* for setting bus speed in card: 0x13h */
#define SDIO_BUS_SPEED_UHSISEL_M BITFIELD_MASK(3)
#define SDIO_BUS_SPEED_UHSISEL_S 1
/* for getting bus speed cap in card: 0x14h */
#define SDIO_BUS_SPEED_UHSICAP_M BITFIELD_MASK(3)
#define SDIO_BUS_SPEED_UHSICAP_S 0
/* for getting driver type CAP in card: 0x15h */
#define SDIO_BUS_DRVR_TYPE_CAP_M BITFIELD_MASK(3)
#define SDIO_BUS_DRVR_TYPE_CAP_S 0
/* for setting driver type selection in card: 0x15h */
#define SDIO_BUS_DRVR_TYPE_SEL_M BITFIELD_MASK(2)
#define SDIO_BUS_DRVR_TYPE_SEL_S 4
/* for getting async int support in card: 0x16h */
#define SDIO_BUS_ASYNCINT_CAP_M BITFIELD_MASK(1)
#define SDIO_BUS_ASYNCINT_CAP_S 0
/* for setting async int selection in card: 0x16h */
#define SDIO_BUS_ASYNCINT_SEL_M BITFIELD_MASK(1)
#define SDIO_BUS_ASYNCINT_SEL_S 1
/* brcm sepint */
#define SDIO_SEPINT_MASK 0x01 /* route sdpcmdev intr onto separate pad (chip-specific) */
#define SDIO_SEPINT_OE 0x02 /* 1 asserts output enable for above pad */
#define SDIO_SEPINT_ACT_HI 0x04 /* use active high interrupt level instead of active low */
/* FBR structure for function 1-7, FBR addresses and register offsets */
typedef volatile struct {
uint8 devctr; /* device interface, CSA control */
uint8 ext_dev; /* extended standard I/O device type code */
uint8 pwr_sel; /* power selection support */
uint8 PAD[6]; /* reserved */
uint8 cis_low; /* CIS LSB */
uint8 cis_mid;
uint8 cis_high; /* CIS MSB */
uint8 csa_low; /* code storage area, LSB */
uint8 csa_mid;
uint8 csa_high; /* code storage area, MSB */
uint8 csa_dat_win; /* data access window to function */
uint8 fnx_blk_size[2]; /* block size, little endian */
} sdio_fbr_t;
/* Maximum number of I/O funcs */
#define SDIOD_MAX_FUNCS 8
#define SDIOD_MAX_IOFUNCS 7
/* SDIO Device FBR Start Address */
#define SDIOD_FBR_STARTADDR 0x100
/* SDIO Device FBR Size */
#define SDIOD_FBR_SIZE 0x100
/* Macro to calculate FBR register base */
#define SDIOD_FBR_BASE(n) ((n) * 0x100)
/* Function register offsets */
#define SDIOD_FBR_DEVCTR 0x00 /* basic info for function */
#define SDIOD_FBR_EXT_DEV 0x01 /* extended I/O device code */
#define SDIOD_FBR_PWR_SEL 0x02 /* power selection bits */
/* SDIO Function CIS ptr offset */
#define SDIOD_FBR_CISPTR_0 0x09
#define SDIOD_FBR_CISPTR_1 0x0A
#define SDIOD_FBR_CISPTR_2 0x0B
/* Code Storage Area pointer */
#define SDIOD_FBR_CSA_ADDR_0 0x0C
#define SDIOD_FBR_CSA_ADDR_1 0x0D
#define SDIOD_FBR_CSA_ADDR_2 0x0E
#define SDIOD_FBR_CSA_DATA 0x0F
/* SDIO Function I/O Block Size */
#define SDIOD_FBR_BLKSIZE_0 0x10
#define SDIOD_FBR_BLKSIZE_1 0x11
/* devctr */
#define SDIOD_FBR_DEVCTR_DIC 0x0f /* device interface code */
#define SDIOD_FBR_DECVTR_CSA 0x40 /* CSA support flag */
#define SDIOD_FBR_DEVCTR_CSA_EN 0x80 /* CSA enabled */
/* interface codes */
#define SDIOD_DIC_NONE 0 /* SDIO standard interface is not supported */
#define SDIOD_DIC_UART 1
#define SDIOD_DIC_BLUETOOTH_A 2
#define SDIOD_DIC_BLUETOOTH_B 3
#define SDIOD_DIC_GPS 4
#define SDIOD_DIC_CAMERA 5
#define SDIOD_DIC_PHS 6
#define SDIOD_DIC_WLAN 7
#define SDIOD_DIC_EXT 0xf /* extended device interface, read ext_dev register */
/* pwr_sel */
#define SDIOD_PWR_SEL_SPS 0x01 /* supports power selection */
#define SDIOD_PWR_SEL_EPS 0x02 /* enable power selection (low-current mode) */
/* misc defines */
#define SDIO_FUNC_0 0
#define SDIO_FUNC_1 1
#define SDIO_FUNC_2 2
#define SDIO_FUNC_3 3
#define SDIO_FUNC_4 4
#define SDIO_FUNC_5 5
#define SDIO_FUNC_6 6
#define SDIO_FUNC_7 7
#define SD_CARD_TYPE_UNKNOWN 0 /* bad type or unrecognized */
#define SD_CARD_TYPE_IO 1 /* IO only card */
#define SD_CARD_TYPE_MEMORY 2 /* memory only card */
#define SD_CARD_TYPE_COMBO 3 /* IO and memory combo card */
#define SDIO_MAX_BLOCK_SIZE 2048 /* maximum block size for block mode operation */
#define SDIO_MIN_BLOCK_SIZE 1 /* minimum block size for block mode operation */
/* Card registers: status bit position */
#define CARDREG_STATUS_BIT_OUTOFRANGE 31
#define CARDREG_STATUS_BIT_COMCRCERROR 23
#define CARDREG_STATUS_BIT_ILLEGALCOMMAND 22
#define CARDREG_STATUS_BIT_ERROR 19
#define CARDREG_STATUS_BIT_IOCURRENTSTATE3 12
#define CARDREG_STATUS_BIT_IOCURRENTSTATE2 11
#define CARDREG_STATUS_BIT_IOCURRENTSTATE1 10
#define CARDREG_STATUS_BIT_IOCURRENTSTATE0 9
#define CARDREG_STATUS_BIT_FUN_NUM_ERROR 4
#define SD_CMD_GO_IDLE_STATE 0 /* mandatory for SDIO */
#define SD_CMD_SEND_OPCOND 1
#define SD_CMD_MMC_SET_RCA 3
#define SD_CMD_IO_SEND_OP_COND 5 /* mandatory for SDIO */
#define SD_CMD_SELECT_DESELECT_CARD 7
#define SD_CMD_SEND_CSD 9
#define SD_CMD_SEND_CID 10
#define SD_CMD_STOP_TRANSMISSION 12
#define SD_CMD_SEND_STATUS 13
#define SD_CMD_GO_INACTIVE_STATE 15
#define SD_CMD_SET_BLOCKLEN 16
#define SD_CMD_READ_SINGLE_BLOCK 17
#define SD_CMD_READ_MULTIPLE_BLOCK 18
#define SD_CMD_WRITE_BLOCK 24
#define SD_CMD_WRITE_MULTIPLE_BLOCK 25
#define SD_CMD_PROGRAM_CSD 27
#define SD_CMD_SET_WRITE_PROT 28
#define SD_CMD_CLR_WRITE_PROT 29
#define SD_CMD_SEND_WRITE_PROT 30
#define SD_CMD_ERASE_WR_BLK_START 32
#define SD_CMD_ERASE_WR_BLK_END 33
#define SD_CMD_ERASE 38
#define SD_CMD_LOCK_UNLOCK 42
#define SD_CMD_IO_RW_DIRECT 52 /* mandatory for SDIO */
#define SD_CMD_IO_RW_EXTENDED 53 /* mandatory for SDIO */
#define SD_CMD_APP_CMD 55
#define SD_CMD_GEN_CMD 56
#define SD_CMD_READ_OCR 58
#define SD_CMD_CRC_ON_OFF 59 /* mandatory for SDIO */
#define SD_ACMD_SD_STATUS 13
#define SD_ACMD_SEND_NUM_WR_BLOCKS 22
#define SD_ACMD_SET_WR_BLOCK_ERASE_CNT 23
#define SD_ACMD_SD_SEND_OP_COND 41
#define SD_ACMD_SET_CLR_CARD_DETECT 42
#define SD_ACMD_SEND_SCR 51
/* argument for SD_CMD_IO_RW_DIRECT and SD_CMD_IO_RW_EXTENDED */
#define SD_IO_OP_READ 0 /* Read_Write: Read */
#define SD_IO_OP_WRITE 1 /* Read_Write: Write */
#define SD_IO_RW_NORMAL 0 /* no RAW */
#define SD_IO_RW_RAW 1 /* RAW */
#define SD_IO_BYTE_MODE 0 /* Byte Mode */
#define SD_IO_BLOCK_MODE 1 /* BlockMode */
#define SD_IO_FIXED_ADDRESS 0 /* fix Address */
#define SD_IO_INCREMENT_ADDRESS 1 /* IncrementAddress */
/* build SD_CMD_IO_RW_DIRECT Argument */
#define SDIO_IO_RW_DIRECT_ARG(rw, raw, func, addr, data) \
((((rw) & 1) << 31) | (((func) & 0x7) << 28) | (((raw) & 1) << 27) | \
(((addr) & 0x1FFFF) << 9) | ((data) & 0xFF))
/* build SD_CMD_IO_RW_EXTENDED Argument */
#define SDIO_IO_RW_EXTENDED_ARG(rw, blk, func, addr, inc_addr, count) \
((((rw) & 1) << 31) | (((func) & 0x7) << 28) | (((blk) & 1) << 27) | \
(((inc_addr) & 1) << 26) | (((addr) & 0x1FFFF) << 9) | ((count) & 0x1FF))
/* SDIO response parameters */
#define SD_RSP_NO_NONE 0
#define SD_RSP_NO_1 1
#define SD_RSP_NO_2 2
#define SD_RSP_NO_3 3
#define SD_RSP_NO_4 4
#define SD_RSP_NO_5 5
#define SD_RSP_NO_6 6
/* Modified R6 response (to CMD3) */
#define SD_RSP_MR6_COM_CRC_ERROR 0x8000
#define SD_RSP_MR6_ILLEGAL_COMMAND 0x4000
#define SD_RSP_MR6_ERROR 0x2000
/* Modified R1 in R4 Response (to CMD5) */
#define SD_RSP_MR1_SBIT 0x80
#define SD_RSP_MR1_PARAMETER_ERROR 0x40
#define SD_RSP_MR1_RFU5 0x20
#define SD_RSP_MR1_FUNC_NUM_ERROR 0x10
#define SD_RSP_MR1_COM_CRC_ERROR 0x08
#define SD_RSP_MR1_ILLEGAL_COMMAND 0x04
#define SD_RSP_MR1_RFU1 0x02
#define SD_RSP_MR1_IDLE_STATE 0x01
/* R5 response (to CMD52 and CMD53) */
#define SD_RSP_R5_COM_CRC_ERROR 0x80
#define SD_RSP_R5_ILLEGAL_COMMAND 0x40
#define SD_RSP_R5_IO_CURRENTSTATE1 0x20
#define SD_RSP_R5_IO_CURRENTSTATE0 0x10
#define SD_RSP_R5_ERROR 0x08
#define SD_RSP_R5_RFU 0x04
#define SD_RSP_R5_FUNC_NUM_ERROR 0x02
#define SD_RSP_R5_OUT_OF_RANGE 0x01
#define SD_RSP_R5_ERRBITS 0xCB
/* ------------------------------------------------
* SDIO Commands and responses
*
* I/O only commands are:
* CMD0, CMD3, CMD5, CMD7, CMD14, CMD15, CMD52, CMD53
* ------------------------------------------------
*/
/* SDIO Commands */
#define SDIOH_CMD_0 0
#define SDIOH_CMD_3 3
#define SDIOH_CMD_5 5
#define SDIOH_CMD_7 7
#define SDIOH_CMD_11 11
#define SDIOH_CMD_14 14
#define SDIOH_CMD_15 15
#define SDIOH_CMD_19 19
#define SDIOH_CMD_52 52
#define SDIOH_CMD_53 53
#define SDIOH_CMD_59 59
/* SDIO Command Responses */
#define SDIOH_RSP_NONE 0
#define SDIOH_RSP_R1 1
#define SDIOH_RSP_R2 2
#define SDIOH_RSP_R3 3
#define SDIOH_RSP_R4 4
#define SDIOH_RSP_R5 5
#define SDIOH_RSP_R6 6
/*
* SDIO Response Error flags
*/
#define SDIOH_RSP5_ERROR_FLAGS 0xCB
/* ------------------------------------------------
* SDIO Command structures. I/O only commands are:
*
* CMD0, CMD3, CMD5, CMD7, CMD15, CMD52, CMD53
* ------------------------------------------------
*/
#define CMD5_OCR_M BITFIELD_MASK(24)
#define CMD5_OCR_S 0
#define CMD5_S18R_M BITFIELD_MASK(1)
#define CMD5_S18R_S 24
#define CMD7_RCA_M BITFIELD_MASK(16)
#define CMD7_RCA_S 16
#define CMD14_RCA_M BITFIELD_MASK(16)
#define CMD14_RCA_S 16
#define CMD14_SLEEP_M BITFIELD_MASK(1)
#define CMD14_SLEEP_S 15
#define CMD_15_RCA_M BITFIELD_MASK(16)
#define CMD_15_RCA_S 16
#define CMD52_DATA_M BITFIELD_MASK(8) /* Bits [7:0] - Write Data/Stuff bits of CMD52
*/
#define CMD52_DATA_S 0
#define CMD52_REG_ADDR_M BITFIELD_MASK(17) /* Bits [25:9] - register address */
#define CMD52_REG_ADDR_S 9
#define CMD52_RAW_M BITFIELD_MASK(1) /* Bit 27 - Read after Write flag */
#define CMD52_RAW_S 27
#define CMD52_FUNCTION_M BITFIELD_MASK(3) /* Bits [30:28] - Function number */
#define CMD52_FUNCTION_S 28
#define CMD52_RW_FLAG_M BITFIELD_MASK(1) /* Bit 31 - R/W flag */
#define CMD52_RW_FLAG_S 31
#define CMD53_BYTE_BLK_CNT_M BITFIELD_MASK(9) /* Bits [8:0] - Byte/Block Count of CMD53 */
#define CMD53_BYTE_BLK_CNT_S 0
#define CMD53_REG_ADDR_M BITFIELD_MASK(17) /* Bits [25:9] - register address */
#define CMD53_REG_ADDR_S 9
#define CMD53_OP_CODE_M BITFIELD_MASK(1) /* Bit 26 - R/W Operation Code */
#define CMD53_OP_CODE_S 26
#define CMD53_BLK_MODE_M BITFIELD_MASK(1) /* Bit 27 - Block Mode */
#define CMD53_BLK_MODE_S 27
#define CMD53_FUNCTION_M BITFIELD_MASK(3) /* Bits [30:28] - Function number */
#define CMD53_FUNCTION_S 28
#define CMD53_RW_FLAG_M BITFIELD_MASK(1) /* Bit 31 - R/W flag */
#define CMD53_RW_FLAG_S 31
/* ------------------------------------------------------
* SDIO Command Response structures for SD1 and SD4 modes
* -----------------------------------------------------
*/
#define RSP4_IO_OCR_M BITFIELD_MASK(24) /* Bits [23:0] - Card's OCR Bits [23:0] */
#define RSP4_IO_OCR_S 0
#define RSP4_S18A_M BITFIELD_MASK(1) /* Bits [23:0] - Card's OCR Bits [23:0] */
#define RSP4_S18A_S 24
#define RSP4_STUFF_M BITFIELD_MASK(3) /* Bits [26:24] - Stuff bits */
#define RSP4_STUFF_S 24
#define RSP4_MEM_PRESENT_M BITFIELD_MASK(1) /* Bit 27 - Memory present */
#define RSP4_MEM_PRESENT_S 27
#define RSP4_NUM_FUNCS_M BITFIELD_MASK(3) /* Bits [30:28] - Number of I/O funcs */
#define RSP4_NUM_FUNCS_S 28
#define RSP4_CARD_READY_M BITFIELD_MASK(1) /* Bit 31 - SDIO card ready */
#define RSP4_CARD_READY_S 31
#define RSP6_STATUS_M BITFIELD_MASK(16) /* Bits [15:0] - Card status bits [19,22,23,12:0]
*/
#define RSP6_STATUS_S 0
#define RSP6_IO_RCA_M BITFIELD_MASK(16) /* Bits [31:16] - RCA bits[31-16] */
#define RSP6_IO_RCA_S 16
#define RSP1_AKE_SEQ_ERROR_M BITFIELD_MASK(1) /* Bit 3 - Authentication seq error */
#define RSP1_AKE_SEQ_ERROR_S 3
#define RSP1_APP_CMD_M BITFIELD_MASK(1) /* Bit 5 - Card expects ACMD */
#define RSP1_APP_CMD_S 5
#define RSP1_READY_FOR_DATA_M BITFIELD_MASK(1) /* Bit 8 - Ready for data (buff empty) */
#define RSP1_READY_FOR_DATA_S 8
#define RSP1_CURR_STATE_M BITFIELD_MASK(4) /* Bits [12:9] - State of card
* when Cmd was received
*/
#define RSP1_CURR_STATE_S 9
#define RSP1_EARSE_RESET_M BITFIELD_MASK(1) /* Bit 13 - Erase seq cleared */
#define RSP1_EARSE_RESET_S 13
#define RSP1_CARD_ECC_DISABLE_M BITFIELD_MASK(1) /* Bit 14 - Card ECC disabled */
#define RSP1_CARD_ECC_DISABLE_S 14
#define RSP1_WP_ERASE_SKIP_M BITFIELD_MASK(1) /* Bit 15 - Partial blocks erased due to W/P */
#define RSP1_WP_ERASE_SKIP_S 15
#define RSP1_CID_CSD_OVERW_M BITFIELD_MASK(1) /* Bit 16 - Illegal write to CID or R/O bits
* of CSD
*/
#define RSP1_CID_CSD_OVERW_S 16
#define RSP1_ERROR_M BITFIELD_MASK(1) /* Bit 19 - General/Unknown error */
#define RSP1_ERROR_S 19
#define RSP1_CC_ERROR_M BITFIELD_MASK(1) /* Bit 20 - Internal Card Control error */
#define RSP1_CC_ERROR_S 20
#define RSP1_CARD_ECC_FAILED_M BITFIELD_MASK(1) /* Bit 21 - Card internal ECC failed
* to correct data
*/
#define RSP1_CARD_ECC_FAILED_S 21
#define RSP1_ILLEGAL_CMD_M BITFIELD_MASK(1) /* Bit 22 - Cmd not legal for the card state */
#define RSP1_ILLEGAL_CMD_S 22
#define RSP1_COM_CRC_ERROR_M BITFIELD_MASK(1) /* Bit 23 - CRC check of previous command failed
*/
#define RSP1_COM_CRC_ERROR_S 23
#define RSP1_LOCK_UNLOCK_FAIL_M BITFIELD_MASK(1) /* Bit 24 - Card lock-unlock Cmd Seq error */
#define RSP1_LOCK_UNLOCK_FAIL_S 24
#define RSP1_CARD_LOCKED_M BITFIELD_MASK(1) /* Bit 25 - Card locked by the host */
#define RSP1_CARD_LOCKED_S 25
#define RSP1_WP_VIOLATION_M BITFIELD_MASK(1) /* Bit 26 - Attempt to program
* write-protected blocks
*/
#define RSP1_WP_VIOLATION_S 26
#define RSP1_ERASE_PARAM_M BITFIELD_MASK(1) /* Bit 27 - Invalid erase blocks */
#define RSP1_ERASE_PARAM_S 27
#define RSP1_ERASE_SEQ_ERR_M BITFIELD_MASK(1) /* Bit 28 - Erase Cmd seq error */
#define RSP1_ERASE_SEQ_ERR_S 28
#define RSP1_BLK_LEN_ERR_M BITFIELD_MASK(1) /* Bit 29 - Block length error */
#define RSP1_BLK_LEN_ERR_S 29
#define RSP1_ADDR_ERR_M BITFIELD_MASK(1) /* Bit 30 - Misaligned address */
#define RSP1_ADDR_ERR_S 30
#define RSP1_OUT_OF_RANGE_M BITFIELD_MASK(1) /* Bit 31 - Cmd arg was out of range */
#define RSP1_OUT_OF_RANGE_S 31
#define RSP5_DATA_M BITFIELD_MASK(8) /* Bits [0:7] - data */
#define RSP5_DATA_S 0
#define RSP5_FLAGS_M BITFIELD_MASK(8) /* Bit [15:8] - Rsp flags */
#define RSP5_FLAGS_S 8
#define RSP5_STUFF_M BITFIELD_MASK(16) /* Bits [31:16] - Stuff bits */
#define RSP5_STUFF_S 16
/* ----------------------------------------------
* SDIO Command Response structures for SPI mode
* ----------------------------------------------
*/
#define SPIRSP4_IO_OCR_M BITFIELD_MASK(16) /* Bits [15:0] - Card's OCR Bits [23:8] */
#define SPIRSP4_IO_OCR_S 0
#define SPIRSP4_STUFF_M BITFIELD_MASK(3) /* Bits [18:16] - Stuff bits */
#define SPIRSP4_STUFF_S 16
#define SPIRSP4_MEM_PRESENT_M BITFIELD_MASK(1) /* Bit 19 - Memory present */
#define SPIRSP4_MEM_PRESENT_S 19
#define SPIRSP4_NUM_FUNCS_M BITFIELD_MASK(3) /* Bits [22:20] - Number of I/O funcs */
#define SPIRSP4_NUM_FUNCS_S 20
#define SPIRSP4_CARD_READY_M BITFIELD_MASK(1) /* Bit 23 - SDIO card ready */
#define SPIRSP4_CARD_READY_S 23
#define SPIRSP4_IDLE_STATE_M BITFIELD_MASK(1) /* Bit 24 - idle state */
#define SPIRSP4_IDLE_STATE_S 24
#define SPIRSP4_ILLEGAL_CMD_M BITFIELD_MASK(1) /* Bit 26 - Illegal Cmd error */
#define SPIRSP4_ILLEGAL_CMD_S 26
#define SPIRSP4_COM_CRC_ERROR_M BITFIELD_MASK(1) /* Bit 27 - COM CRC error */
#define SPIRSP4_COM_CRC_ERROR_S 27
#define SPIRSP4_FUNC_NUM_ERROR_M BITFIELD_MASK(1) /* Bit 28 - Function number error
*/
#define SPIRSP4_FUNC_NUM_ERROR_S 28
#define SPIRSP4_PARAM_ERROR_M BITFIELD_MASK(1) /* Bit 30 - Parameter Error Bit */
#define SPIRSP4_PARAM_ERROR_S 30
#define SPIRSP4_START_BIT_M BITFIELD_MASK(1) /* Bit 31 - Start Bit */
#define SPIRSP4_START_BIT_S 31
#define SPIRSP5_DATA_M BITFIELD_MASK(8) /* Bits [23:16] - R/W Data */
#define SPIRSP5_DATA_S 16
#define SPIRSP5_IDLE_STATE_M BITFIELD_MASK(1) /* Bit 24 - Idle state */
#define SPIRSP5_IDLE_STATE_S 24
#define SPIRSP5_ILLEGAL_CMD_M BITFIELD_MASK(1) /* Bit 26 - Illegal Cmd error */
#define SPIRSP5_ILLEGAL_CMD_S 26
#define SPIRSP5_COM_CRC_ERROR_M BITFIELD_MASK(1) /* Bit 27 - COM CRC error */
#define SPIRSP5_COM_CRC_ERROR_S 27
#define SPIRSP5_FUNC_NUM_ERROR_M BITFIELD_MASK(1) /* Bit 28 - Function number error
*/
#define SPIRSP5_FUNC_NUM_ERROR_S 28
#define SPIRSP5_PARAM_ERROR_M BITFIELD_MASK(1) /* Bit 30 - Parameter Error Bit */
#define SPIRSP5_PARAM_ERROR_S 30
#define SPIRSP5_START_BIT_M BITFIELD_MASK(1) /* Bit 31 - Start Bit */
#define SPIRSP5_START_BIT_S 31
/* RSP6 card status format; Pg 68 Physical Layer spec v 1.10 */
#define RSP6STAT_AKE_SEQ_ERROR_M BITFIELD_MASK(1) /* Bit 3 - Authentication seq error
*/
#define RSP6STAT_AKE_SEQ_ERROR_S 3
#define RSP6STAT_APP_CMD_M BITFIELD_MASK(1) /* Bit 5 - Card expects ACMD */
#define RSP6STAT_APP_CMD_S 5
#define RSP6STAT_READY_FOR_DATA_M BITFIELD_MASK(1) /* Bit 8 - Ready for data
* (buff empty)
*/
#define RSP6STAT_READY_FOR_DATA_S 8
#define RSP6STAT_CURR_STATE_M BITFIELD_MASK(4) /* Bits [12:9] - Card state at
* Cmd reception
*/
#define RSP6STAT_CURR_STATE_S 9
#define RSP6STAT_ERROR_M BITFIELD_MASK(1) /* Bit 13 - General/Unknown error Bit 19
*/
#define RSP6STAT_ERROR_S 13
#define RSP6STAT_ILLEGAL_CMD_M BITFIELD_MASK(1) /* Bit 14 - Illegal cmd for
* card state Bit 22
*/
#define RSP6STAT_ILLEGAL_CMD_S 14
#define RSP6STAT_COM_CRC_ERROR_M BITFIELD_MASK(1) /* Bit 15 - CRC previous command
* failed Bit 23
*/
#define RSP6STAT_COM_CRC_ERROR_S 15
#define SDIOH_XFER_TYPE_READ SD_IO_OP_READ
#define SDIOH_XFER_TYPE_WRITE SD_IO_OP_WRITE
/* command issue options */
#define CMD_OPTION_DEFAULT 0
#define CMD_OPTION_TUNING 1
#endif /* _SDIO_H */

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/*
* SDIO Host Controller Spec header file
* Register map and definitions for the Standard Host Controller
*
* $Copyright Open Broadcom Corporation$
*
* $Id: sdioh.h 299859 2011-12-01 03:53:27Z $
*/
#ifndef _SDIOH_H
#define _SDIOH_H
#define SD_SysAddr 0x000
#define SD_BlockSize 0x004
#define SD_BlockCount 0x006
#define SD_Arg0 0x008
#define SD_Arg1 0x00A
#define SD_TransferMode 0x00C
#define SD_Command 0x00E
#define SD_Response0 0x010
#define SD_Response1 0x012
#define SD_Response2 0x014
#define SD_Response3 0x016
#define SD_Response4 0x018
#define SD_Response5 0x01A
#define SD_Response6 0x01C
#define SD_Response7 0x01E
#define SD_BufferDataPort0 0x020
#define SD_BufferDataPort1 0x022
#define SD_PresentState 0x024
#define SD_HostCntrl 0x028
#define SD_PwrCntrl 0x029
#define SD_BlockGapCntrl 0x02A
#define SD_WakeupCntrl 0x02B
#define SD_ClockCntrl 0x02C
#define SD_TimeoutCntrl 0x02E
#define SD_SoftwareReset 0x02F
#define SD_IntrStatus 0x030
#define SD_ErrorIntrStatus 0x032
#define SD_IntrStatusEnable 0x034
#define SD_ErrorIntrStatusEnable 0x036
#define SD_IntrSignalEnable 0x038
#define SD_ErrorIntrSignalEnable 0x03A
#define SD_CMD12ErrorStatus 0x03C
#define SD_Capabilities 0x040
#define SD_Capabilities3 0x044
#define SD_MaxCurCap 0x048
#define SD_MaxCurCap_Reserved 0x04C
#define SD_ADMA_ErrStatus 0x054
#define SD_ADMA_SysAddr 0x58
#define SD_SlotInterruptStatus 0x0FC
#define SD_HostControllerVersion 0x0FE
#define SD_GPIO_Reg 0x100
#define SD_GPIO_OE 0x104
#define SD_GPIO_Enable 0x108
/* SD specific registers in PCI config space */
#define SD_SlotInfo 0x40
/* HC 3.0 specific registers and offsets */
#define SD3_HostCntrl2 0x03E
/* preset regsstart and count */
#define SD3_PresetValStart 0x060
#define SD3_PresetValCount 8
/* preset-indiv regs */
#define SD3_PresetVal_init 0x060
#define SD3_PresetVal_default 0x062
#define SD3_PresetVal_HS 0x064
#define SD3_PresetVal_SDR12 0x066
#define SD3_PresetVal_SDR25 0x068
#define SD3_PresetVal_SDR50 0x06a
#define SD3_PresetVal_SDR104 0x06c
#define SD3_PresetVal_DDR50 0x06e
/* preset value indices */
#define SD3_PRESETVAL_INITIAL_IX 0
#define SD3_PRESETVAL_DESPEED_IX 1
#define SD3_PRESETVAL_HISPEED_IX 2
#define SD3_PRESETVAL_SDR12_IX 3
#define SD3_PRESETVAL_SDR25_IX 4
#define SD3_PRESETVAL_SDR50_IX 5
#define SD3_PRESETVAL_SDR104_IX 6
#define SD3_PRESETVAL_DDR50_IX 7
/* SD_Capabilities reg (0x040) */
#define CAP_TO_CLKFREQ_M BITFIELD_MASK(6)
#define CAP_TO_CLKFREQ_S 0
#define CAP_TO_CLKUNIT_M BITFIELD_MASK(1)
#define CAP_TO_CLKUNIT_S 7
/* Note: for sdio-2.0 case, this mask has to be 6 bits, but msb 2
bits are reserved. going ahead with 8 bits, as it is req for 3.0
*/
#define CAP_BASECLK_M BITFIELD_MASK(8)
#define CAP_BASECLK_S 8
#define CAP_MAXBLOCK_M BITFIELD_MASK(2)
#define CAP_MAXBLOCK_S 16
#define CAP_ADMA2_M BITFIELD_MASK(1)
#define CAP_ADMA2_S 19
#define CAP_ADMA1_M BITFIELD_MASK(1)
#define CAP_ADMA1_S 20
#define CAP_HIGHSPEED_M BITFIELD_MASK(1)
#define CAP_HIGHSPEED_S 21
#define CAP_DMA_M BITFIELD_MASK(1)
#define CAP_DMA_S 22
#define CAP_SUSPEND_M BITFIELD_MASK(1)
#define CAP_SUSPEND_S 23
#define CAP_VOLT_3_3_M BITFIELD_MASK(1)
#define CAP_VOLT_3_3_S 24
#define CAP_VOLT_3_0_M BITFIELD_MASK(1)
#define CAP_VOLT_3_0_S 25
#define CAP_VOLT_1_8_M BITFIELD_MASK(1)
#define CAP_VOLT_1_8_S 26
#define CAP_64BIT_HOST_M BITFIELD_MASK(1)
#define CAP_64BIT_HOST_S 28
#define SDIO_OCR_READ_FAIL (2)
#define CAP_ASYNCINT_SUP_M BITFIELD_MASK(1)
#define CAP_ASYNCINT_SUP_S 29
#define CAP_SLOTTYPE_M BITFIELD_MASK(2)
#define CAP_SLOTTYPE_S 30
#define CAP3_MSBits_OFFSET (32)
/* note: following are caps MSB32 bits.
So the bits start from 0, instead of 32. that is why
CAP3_MSBits_OFFSET is subtracted.
*/
#define CAP3_SDR50_SUP_M BITFIELD_MASK(1)
#define CAP3_SDR50_SUP_S (32 - CAP3_MSBits_OFFSET)
#define CAP3_SDR104_SUP_M BITFIELD_MASK(1)
#define CAP3_SDR104_SUP_S (33 - CAP3_MSBits_OFFSET)
#define CAP3_DDR50_SUP_M BITFIELD_MASK(1)
#define CAP3_DDR50_SUP_S (34 - CAP3_MSBits_OFFSET)
/* for knowing the clk caps in a single read */
#define CAP3_30CLKCAP_M BITFIELD_MASK(3)
#define CAP3_30CLKCAP_S (32 - CAP3_MSBits_OFFSET)
#define CAP3_DRIVTYPE_A_M BITFIELD_MASK(1)
#define CAP3_DRIVTYPE_A_S (36 - CAP3_MSBits_OFFSET)
#define CAP3_DRIVTYPE_C_M BITFIELD_MASK(1)
#define CAP3_DRIVTYPE_C_S (37 - CAP3_MSBits_OFFSET)
#define CAP3_DRIVTYPE_D_M BITFIELD_MASK(1)
#define CAP3_DRIVTYPE_D_S (38 - CAP3_MSBits_OFFSET)
#define CAP3_RETUNING_TC_M BITFIELD_MASK(4)
#define CAP3_RETUNING_TC_S (40 - CAP3_MSBits_OFFSET)
#define CAP3_TUNING_SDR50_M BITFIELD_MASK(1)
#define CAP3_TUNING_SDR50_S (45 - CAP3_MSBits_OFFSET)
#define CAP3_RETUNING_MODES_M BITFIELD_MASK(2)
#define CAP3_RETUNING_MODES_S (46 - CAP3_MSBits_OFFSET)
#define CAP3_CLK_MULT_M BITFIELD_MASK(8)
#define CAP3_CLK_MULT_S (48 - CAP3_MSBits_OFFSET)
#define PRESET_DRIVR_SELECT_M BITFIELD_MASK(2)
#define PRESET_DRIVR_SELECT_S 14
#define PRESET_CLK_DIV_M BITFIELD_MASK(10)
#define PRESET_CLK_DIV_S 0
/* SD_MaxCurCap reg (0x048) */
#define CAP_CURR_3_3_M BITFIELD_MASK(8)
#define CAP_CURR_3_3_S 0
#define CAP_CURR_3_0_M BITFIELD_MASK(8)
#define CAP_CURR_3_0_S 8
#define CAP_CURR_1_8_M BITFIELD_MASK(8)
#define CAP_CURR_1_8_S 16
/* SD_SysAddr: Offset 0x0000, Size 4 bytes */
/* SD_BlockSize: Offset 0x004, Size 2 bytes */
#define BLKSZ_BLKSZ_M BITFIELD_MASK(12)
#define BLKSZ_BLKSZ_S 0
#define BLKSZ_BNDRY_M BITFIELD_MASK(3)
#define BLKSZ_BNDRY_S 12
/* SD_BlockCount: Offset 0x006, size 2 bytes */
/* SD_Arg0: Offset 0x008, size = 4 bytes */
/* SD_TransferMode Offset 0x00C, size = 2 bytes */
#define XFER_DMA_ENABLE_M BITFIELD_MASK(1)
#define XFER_DMA_ENABLE_S 0
#define XFER_BLK_COUNT_EN_M BITFIELD_MASK(1)
#define XFER_BLK_COUNT_EN_S 1
#define XFER_CMD_12_EN_M BITFIELD_MASK(1)
#define XFER_CMD_12_EN_S 2
#define XFER_DATA_DIRECTION_M BITFIELD_MASK(1)
#define XFER_DATA_DIRECTION_S 4
#define XFER_MULTI_BLOCK_M BITFIELD_MASK(1)
#define XFER_MULTI_BLOCK_S 5
/* SD_Command: Offset 0x00E, size = 2 bytes */
/* resp_type field */
#define RESP_TYPE_NONE 0
#define RESP_TYPE_136 1
#define RESP_TYPE_48 2
#define RESP_TYPE_48_BUSY 3
/* type field */
#define CMD_TYPE_NORMAL 0
#define CMD_TYPE_SUSPEND 1
#define CMD_TYPE_RESUME 2
#define CMD_TYPE_ABORT 3
#define CMD_RESP_TYPE_M BITFIELD_MASK(2) /* Bits [0-1] - Response type */
#define CMD_RESP_TYPE_S 0
#define CMD_CRC_EN_M BITFIELD_MASK(1) /* Bit 3 - CRC enable */
#define CMD_CRC_EN_S 3
#define CMD_INDEX_EN_M BITFIELD_MASK(1) /* Bit 4 - Enable index checking */
#define CMD_INDEX_EN_S 4
#define CMD_DATA_EN_M BITFIELD_MASK(1) /* Bit 5 - Using DAT line */
#define CMD_DATA_EN_S 5
#define CMD_TYPE_M BITFIELD_MASK(2) /* Bit [6-7] - Normal, abort, resume, etc
*/
#define CMD_TYPE_S 6
#define CMD_INDEX_M BITFIELD_MASK(6) /* Bits [8-13] - Command number */
#define CMD_INDEX_S 8
/* SD_BufferDataPort0 : Offset 0x020, size = 2 or 4 bytes */
/* SD_BufferDataPort1 : Offset 0x022, size = 2 bytes */
/* SD_PresentState : Offset 0x024, size = 4 bytes */
#define PRES_CMD_INHIBIT_M BITFIELD_MASK(1) /* Bit 0 May use CMD */
#define PRES_CMD_INHIBIT_S 0
#define PRES_DAT_INHIBIT_M BITFIELD_MASK(1) /* Bit 1 May use DAT */
#define PRES_DAT_INHIBIT_S 1
#define PRES_DAT_BUSY_M BITFIELD_MASK(1) /* Bit 2 DAT is busy */
#define PRES_DAT_BUSY_S 2
#define PRES_PRESENT_RSVD_M BITFIELD_MASK(5) /* Bit [3-7] rsvd */
#define PRES_PRESENT_RSVD_S 3
#define PRES_WRITE_ACTIVE_M BITFIELD_MASK(1) /* Bit 8 Write is active */
#define PRES_WRITE_ACTIVE_S 8
#define PRES_READ_ACTIVE_M BITFIELD_MASK(1) /* Bit 9 Read is active */
#define PRES_READ_ACTIVE_S 9
#define PRES_WRITE_DATA_RDY_M BITFIELD_MASK(1) /* Bit 10 Write buf is avail */
#define PRES_WRITE_DATA_RDY_S 10
#define PRES_READ_DATA_RDY_M BITFIELD_MASK(1) /* Bit 11 Read buf data avail */
#define PRES_READ_DATA_RDY_S 11
#define PRES_CARD_PRESENT_M BITFIELD_MASK(1) /* Bit 16 Card present - debounced */
#define PRES_CARD_PRESENT_S 16
#define PRES_CARD_STABLE_M BITFIELD_MASK(1) /* Bit 17 Debugging */
#define PRES_CARD_STABLE_S 17
#define PRES_CARD_PRESENT_RAW_M BITFIELD_MASK(1) /* Bit 18 Not debounced */
#define PRES_CARD_PRESENT_RAW_S 18
#define PRES_WRITE_ENABLED_M BITFIELD_MASK(1) /* Bit 19 Write protected? */
#define PRES_WRITE_ENABLED_S 19
#define PRES_DAT_SIGNAL_M BITFIELD_MASK(4) /* Bit [20-23] Debugging */
#define PRES_DAT_SIGNAL_S 20
#define PRES_CMD_SIGNAL_M BITFIELD_MASK(1) /* Bit 24 Debugging */
#define PRES_CMD_SIGNAL_S 24
/* SD_HostCntrl: Offset 0x028, size = 1 bytes */
#define HOST_LED_M BITFIELD_MASK(1) /* Bit 0 LED On/Off */
#define HOST_LED_S 0
#define HOST_DATA_WIDTH_M BITFIELD_MASK(1) /* Bit 1 4 bit enable */
#define HOST_DATA_WIDTH_S 1
#define HOST_HI_SPEED_EN_M BITFIELD_MASK(1) /* Bit 2 High speed vs low speed */
#define HOST_DMA_SEL_S 3
#define HOST_DMA_SEL_M BITFIELD_MASK(2) /* Bit 4:3 DMA Select */
#define HOST_HI_SPEED_EN_S 2
/* Host Control2: */
#define HOSTCtrl2_PRESVAL_EN_M BITFIELD_MASK(1) /* 1 bit */
#define HOSTCtrl2_PRESVAL_EN_S 15 /* bit# */
#define HOSTCtrl2_ASYINT_EN_M BITFIELD_MASK(1) /* 1 bit */
#define HOSTCtrl2_ASYINT_EN_S 14 /* bit# */
#define HOSTCtrl2_SAMPCLK_SEL_M BITFIELD_MASK(1) /* 1 bit */
#define HOSTCtrl2_SAMPCLK_SEL_S 7 /* bit# */
#define HOSTCtrl2_EXEC_TUNING_M BITFIELD_MASK(1) /* 1 bit */
#define HOSTCtrl2_EXEC_TUNING_S 6 /* bit# */
#define HOSTCtrl2_DRIVSTRENGTH_SEL_M BITFIELD_MASK(2) /* 2 bit */
#define HOSTCtrl2_DRIVSTRENGTH_SEL_S 4 /* bit# */
#define HOSTCtrl2_1_8SIG_EN_M BITFIELD_MASK(1) /* 1 bit */
#define HOSTCtrl2_1_8SIG_EN_S 3 /* bit# */
#define HOSTCtrl2_UHSMODE_SEL_M BITFIELD_MASK(3) /* 3 bit */
#define HOSTCtrl2_UHSMODE_SEL_S 0 /* bit# */
#define HOST_CONTR_VER_2 (1)
#define HOST_CONTR_VER_3 (2)
/* misc defines */
#define SD1_MODE 0x1 /* SD Host Cntrlr Spec */
#define SD4_MODE 0x2 /* SD Host Cntrlr Spec */
/* SD_PwrCntrl: Offset 0x029, size = 1 bytes */
#define PWR_BUS_EN_M BITFIELD_MASK(1) /* Bit 0 Power the bus */
#define PWR_BUS_EN_S 0
#define PWR_VOLTS_M BITFIELD_MASK(3) /* Bit [1-3] Voltage Select */
#define PWR_VOLTS_S 1
/* SD_SoftwareReset: Offset 0x02F, size = 1 byte */
#define SW_RESET_ALL_M BITFIELD_MASK(1) /* Bit 0 Reset All */
#define SW_RESET_ALL_S 0
#define SW_RESET_CMD_M BITFIELD_MASK(1) /* Bit 1 CMD Line Reset */
#define SW_RESET_CMD_S 1
#define SW_RESET_DAT_M BITFIELD_MASK(1) /* Bit 2 DAT Line Reset */
#define SW_RESET_DAT_S 2
/* SD_IntrStatus: Offset 0x030, size = 2 bytes */
/* Defs also serve SD_IntrStatusEnable and SD_IntrSignalEnable */
#define INTSTAT_CMD_COMPLETE_M BITFIELD_MASK(1) /* Bit 0 */
#define INTSTAT_CMD_COMPLETE_S 0
#define INTSTAT_XFER_COMPLETE_M BITFIELD_MASK(1)
#define INTSTAT_XFER_COMPLETE_S 1
#define INTSTAT_BLOCK_GAP_EVENT_M BITFIELD_MASK(1)
#define INTSTAT_BLOCK_GAP_EVENT_S 2
#define INTSTAT_DMA_INT_M BITFIELD_MASK(1)
#define INTSTAT_DMA_INT_S 3
#define INTSTAT_BUF_WRITE_READY_M BITFIELD_MASK(1)
#define INTSTAT_BUF_WRITE_READY_S 4
#define INTSTAT_BUF_READ_READY_M BITFIELD_MASK(1)
#define INTSTAT_BUF_READ_READY_S 5
#define INTSTAT_CARD_INSERTION_M BITFIELD_MASK(1)
#define INTSTAT_CARD_INSERTION_S 6
#define INTSTAT_CARD_REMOVAL_M BITFIELD_MASK(1)
#define INTSTAT_CARD_REMOVAL_S 7
#define INTSTAT_CARD_INT_M BITFIELD_MASK(1)
#define INTSTAT_CARD_INT_S 8
#define INTSTAT_RETUNING_INT_M BITFIELD_MASK(1) /* Bit 12 */
#define INTSTAT_RETUNING_INT_S 12
#define INTSTAT_ERROR_INT_M BITFIELD_MASK(1) /* Bit 15 */
#define INTSTAT_ERROR_INT_S 15
/* SD_ErrorIntrStatus: Offset 0x032, size = 2 bytes */
/* Defs also serve SD_ErrorIntrStatusEnable and SD_ErrorIntrSignalEnable */
#define ERRINT_CMD_TIMEOUT_M BITFIELD_MASK(1)
#define ERRINT_CMD_TIMEOUT_S 0
#define ERRINT_CMD_CRC_M BITFIELD_MASK(1)
#define ERRINT_CMD_CRC_S 1
#define ERRINT_CMD_ENDBIT_M BITFIELD_MASK(1)
#define ERRINT_CMD_ENDBIT_S 2
#define ERRINT_CMD_INDEX_M BITFIELD_MASK(1)
#define ERRINT_CMD_INDEX_S 3
#define ERRINT_DATA_TIMEOUT_M BITFIELD_MASK(1)
#define ERRINT_DATA_TIMEOUT_S 4
#define ERRINT_DATA_CRC_M BITFIELD_MASK(1)
#define ERRINT_DATA_CRC_S 5
#define ERRINT_DATA_ENDBIT_M BITFIELD_MASK(1)
#define ERRINT_DATA_ENDBIT_S 6
#define ERRINT_CURRENT_LIMIT_M BITFIELD_MASK(1)
#define ERRINT_CURRENT_LIMIT_S 7
#define ERRINT_AUTO_CMD12_M BITFIELD_MASK(1)
#define ERRINT_AUTO_CMD12_S 8
#define ERRINT_VENDOR_M BITFIELD_MASK(4)
#define ERRINT_VENDOR_S 12
#define ERRINT_ADMA_M BITFIELD_MASK(1)
#define ERRINT_ADMA_S 9
/* Also provide definitions in "normal" form to allow combined masks */
#define ERRINT_CMD_TIMEOUT_BIT 0x0001
#define ERRINT_CMD_CRC_BIT 0x0002
#define ERRINT_CMD_ENDBIT_BIT 0x0004
#define ERRINT_CMD_INDEX_BIT 0x0008
#define ERRINT_DATA_TIMEOUT_BIT 0x0010
#define ERRINT_DATA_CRC_BIT 0x0020
#define ERRINT_DATA_ENDBIT_BIT 0x0040
#define ERRINT_CURRENT_LIMIT_BIT 0x0080
#define ERRINT_AUTO_CMD12_BIT 0x0100
#define ERRINT_ADMA_BIT 0x0200
/* Masks to select CMD vs. DATA errors */
#define ERRINT_CMD_ERRS (ERRINT_CMD_TIMEOUT_BIT | ERRINT_CMD_CRC_BIT |\
ERRINT_CMD_ENDBIT_BIT | ERRINT_CMD_INDEX_BIT)
#define ERRINT_DATA_ERRS (ERRINT_DATA_TIMEOUT_BIT | ERRINT_DATA_CRC_BIT |\
ERRINT_DATA_ENDBIT_BIT | ERRINT_ADMA_BIT)
#define ERRINT_TRANSFER_ERRS (ERRINT_CMD_ERRS | ERRINT_DATA_ERRS)
/* SD_WakeupCntr_BlockGapCntrl : Offset 0x02A , size = bytes */
/* SD_ClockCntrl : Offset 0x02C , size = bytes */
/* SD_SoftwareReset_TimeoutCntrl : Offset 0x02E , size = bytes */
/* SD_IntrStatus : Offset 0x030 , size = bytes */
/* SD_ErrorIntrStatus : Offset 0x032 , size = bytes */
/* SD_IntrStatusEnable : Offset 0x034 , size = bytes */
/* SD_ErrorIntrStatusEnable : Offset 0x036 , size = bytes */
/* SD_IntrSignalEnable : Offset 0x038 , size = bytes */
/* SD_ErrorIntrSignalEnable : Offset 0x03A , size = bytes */
/* SD_CMD12ErrorStatus : Offset 0x03C , size = bytes */
/* SD_Capabilities : Offset 0x040 , size = bytes */
/* SD_MaxCurCap : Offset 0x048 , size = bytes */
/* SD_MaxCurCap_Reserved: Offset 0x04C , size = bytes */
/* SD_SlotInterruptStatus: Offset 0x0FC , size = bytes */
/* SD_HostControllerVersion : Offset 0x0FE , size = bytes */
/* SDIO Host Control Register DMA Mode Definitions */
#define SDIOH_SDMA_MODE 0
#define SDIOH_ADMA1_MODE 1
#define SDIOH_ADMA2_MODE 2
#define SDIOH_ADMA2_64_MODE 3
#define ADMA2_ATTRIBUTE_VALID (1 << 0) /* ADMA Descriptor line valid */
#define ADMA2_ATTRIBUTE_END (1 << 1) /* End of Descriptor */
#define ADMA2_ATTRIBUTE_INT (1 << 2) /* Interrupt when line is done */
#define ADMA2_ATTRIBUTE_ACT_NOP (0 << 4) /* Skip current line, go to next. */
#define ADMA2_ATTRIBUTE_ACT_RSV (1 << 4) /* Same as NOP */
#define ADMA1_ATTRIBUTE_ACT_SET (1 << 4) /* ADMA1 Only - set transfer length */
#define ADMA2_ATTRIBUTE_ACT_TRAN (2 << 4) /* Transfer Data of one descriptor line. */
#define ADMA2_ATTRIBUTE_ACT_LINK (3 << 4) /* Link Descriptor */
/* ADMA2 Descriptor Table Entry for 32-bit Address */
typedef struct adma2_dscr_32b {
uint32 len_attr;
uint32 phys_addr;
} adma2_dscr_32b_t;
/* ADMA1 Descriptor Table Entry */
typedef struct adma1_dscr {
uint32 phys_addr_attr;
} adma1_dscr_t;
#endif /* _SDIOH_H */

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external/cache/sources/wl/include/sdiovar.h vendored Normal file
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/*
* Structure used by apps whose drivers access SDIO drivers.
* Pulled out separately so dhdu and wlu can both use it.
*
* $ Copyright Open Broadcom Corporation $
*
* $Id: sdiovar.h 241182 2011-02-17 21:50:03Z $
*/
#ifndef _sdiovar_h_
#define _sdiovar_h_
#include <typedefs.h>
/* require default structure packing */
#define BWL_DEFAULT_PACKING
#include <packed_section_start.h>
typedef struct sdreg {
int func;
int offset;
int value;
} sdreg_t;
/* Common msglevel constants */
#define SDH_ERROR_VAL 0x0001 /* Error */
#define SDH_TRACE_VAL 0x0002 /* Trace */
#define SDH_INFO_VAL 0x0004 /* Info */
#define SDH_DEBUG_VAL 0x0008 /* Debug */
#define SDH_DATA_VAL 0x0010 /* Data */
#define SDH_CTRL_VAL 0x0020 /* Control Regs */
#define SDH_LOG_VAL 0x0040 /* Enable bcmlog */
#define SDH_DMA_VAL 0x0080 /* DMA */
#define NUM_PREV_TRANSACTIONS 16
#ifdef BCMSPI
/* Error statistics for gSPI */
struct spierrstats_t {
uint32 dna; /* The requested data is not available. */
uint32 rdunderflow; /* FIFO underflow happened due to current (F2, F3) rd command */
uint32 wroverflow; /* FIFO underflow happened due to current (F1, F2, F3) wr command */
uint32 f2interrupt; /* OR of all F2 related intr status bits. */
uint32 f3interrupt; /* OR of all F3 related intr status bits. */
uint32 f2rxnotready; /* F2 FIFO is not ready to receive data (FIFO empty) */
uint32 f3rxnotready; /* F3 FIFO is not ready to receive data (FIFO empty) */
uint32 hostcmddataerr; /* Error in command or host data, detected by CRC/checksum
* (optional)
*/
uint32 f2pktavailable; /* Packet is available in F2 TX FIFO */
uint32 f3pktavailable; /* Packet is available in F2 TX FIFO */
uint32 dstatus[NUM_PREV_TRANSACTIONS]; /* dstatus bits of last 16 gSPI transactions */
uint32 spicmd[NUM_PREV_TRANSACTIONS];
};
#endif /* BCMSPI */
#include <packed_section_end.h>
#endif /* _sdiovar_h_ */

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/*
* Misc utility routines for accessing the SOC Interconnects
* of Broadcom HNBU chips.
*
* $Copyright Open Broadcom Corporation$
*
* $Id: siutils.h 395358 2013-04-06 07:45:27Z $
*/
#ifndef _siutils_h_
#define _siutils_h_
#include <bcmutils.h>
struct si_pub {
uint socitype;
uint bustype;
uint buscoretype;
uint buscorerev;
uint buscoreidx;
int ccrev;
uint32 cccaps;
uint32 cccaps_ext;
int pmurev;
uint32 pmucaps;
uint boardtype;
uint boardrev;
uint boardvendor;
uint boardflags;
uint boardflags2;
uint chip;
uint chiprev;
uint chippkg;
uint32 chipst;
bool issim;
uint socirev;
bool pci_pr32414;
};
typedef const struct si_pub si_t;
#define SI_OSH NULL
#define BADIDX (SI_MAXCORES + 1)
#define XTAL 0x1
#define PLL 0x2
#define CLK_FAST 0
#define CLK_DYNAMIC 2
#define GPIO_DRV_PRIORITY 0
#define GPIO_APP_PRIORITY 1
#define GPIO_HI_PRIORITY 2
#define GPIO_PULLUP 0
#define GPIO_PULLDN 1
#define GPIO_REGEVT 0
#define GPIO_REGEVT_INTMSK 1
#define GPIO_REGEVT_INTPOL 2
#define SI_DEVPATH_BUFSZ 16
#define SI_DOATTACH 1
#define SI_PCIDOWN 2
#define SI_PCIUP 3
#define ISSIM_ENAB(sih) FALSE
#if defined(BCMPMUCTL)
#define PMUCTL_ENAB(sih) (BCMPMUCTL)
#else
#define PMUCTL_ENAB(sih) ((sih)->cccaps & CC_CAP_PMU)
#endif
#if defined(BCMPMUCTL) && BCMPMUCTL
#define CCCTL_ENAB(sih) (0)
#define CCPLL_ENAB(sih) (0)
#else
#define CCCTL_ENAB(sih) ((sih)->cccaps & CC_CAP_PWR_CTL)
#define CCPLL_ENAB(sih) ((sih)->cccaps & CC_CAP_PLL_MASK)
#endif
typedef void (*gpio_handler_t)(uint32 stat, void *arg);
#define CC_BTCOEX_EN_MASK 0x01
#define GPIO_CTRL_EPA_EN_MASK 0x40
#define GPIO_CTRL_5_6_EN_MASK 0x60
#define GPIO_CTRL_7_6_EN_MASK 0xC0
#define GPIO_OUT_7_EN_MASK 0x80
#define SI_CR4_CAP (0x04)
#define SI_CR4_BANKIDX (0x40)
#define SI_CR4_BANKINFO (0x44)
#define ARMCR4_TCBBNB_MASK 0xf0
#define ARMCR4_TCBBNB_SHIFT 4
#define ARMCR4_TCBANB_MASK 0xf
#define ARMCR4_TCBANB_SHIFT 0
#define SICF_CPUHALT (0x0020)
#define ARMCR4_BSZ_MASK 0x3f
#define ARMCR4_BSZ_MULT 8192
extern si_t *si_attach(uint pcidev, osl_t *osh, void *regs, uint bustype,
void *sdh, char **vars, uint *varsz);
extern si_t *si_kattach(osl_t *osh);
extern void si_detach(si_t *sih);
extern bool si_pci_war16165(si_t *sih);
extern uint si_corelist(si_t *sih, uint coreid[]);
extern uint si_coreid(si_t *sih);
extern uint si_flag(si_t *sih);
extern uint si_flag_alt(si_t *sih);
extern uint si_intflag(si_t *sih);
extern uint si_coreidx(si_t *sih);
extern uint si_coreunit(si_t *sih);
extern uint si_corevendor(si_t *sih);
extern uint si_corerev(si_t *sih);
extern void *si_osh(si_t *sih);
extern void si_setosh(si_t *sih, osl_t *osh);
extern uint si_corereg(si_t *sih, uint coreidx, uint regoff, uint mask, uint val);
extern void *si_coreregs(si_t *sih);
extern uint si_wrapperreg(si_t *sih, uint32 offset, uint32 mask, uint32 val);
extern uint si_core_wrapperreg(si_t *sih, uint32 coreidx, uint32 offset, uint32 mask, uint32 val);
extern void *si_wrapperregs(si_t *sih);
extern uint32 si_core_cflags(si_t *sih, uint32 mask, uint32 val);
extern void si_core_cflags_wo(si_t *sih, uint32 mask, uint32 val);
extern uint32 si_core_sflags(si_t *sih, uint32 mask, uint32 val);
extern bool si_iscoreup(si_t *sih);
extern uint si_findcoreidx(si_t *sih, uint coreid, uint coreunit);
extern void *si_setcoreidx(si_t *sih, uint coreidx);
extern void *si_setcore(si_t *sih, uint coreid, uint coreunit);
extern void *si_switch_core(si_t *sih, uint coreid, uint *origidx, uint *intr_val);
extern void si_restore_core(si_t *sih, uint coreid, uint intr_val);
extern int si_numaddrspaces(si_t *sih);
extern uint32 si_addrspace(si_t *sih, uint asidx);
extern uint32 si_addrspacesize(si_t *sih, uint asidx);
extern void si_coreaddrspaceX(si_t *sih, uint asidx, uint32 *addr, uint32 *size);
extern int si_corebist(si_t *sih);
extern void si_core_reset(si_t *sih, uint32 bits, uint32 resetbits);
extern void si_core_disable(si_t *sih, uint32 bits);
extern uint32 si_clock_rate(uint32 pll_type, uint32 n, uint32 m);
extern uint si_chip_hostif(si_t *sih);
extern bool si_read_pmu_autopll(si_t *sih);
extern uint32 si_clock(si_t *sih);
extern uint32 si_alp_clock(si_t *sih);
extern uint32 si_ilp_clock(si_t *sih);
extern void si_pci_setup(si_t *sih, uint coremask);
extern void si_pcmcia_init(si_t *sih);
extern void si_setint(si_t *sih, int siflag);
extern bool si_backplane64(si_t *sih);
extern void si_register_intr_callback(si_t *sih, void *intrsoff_fn, void *intrsrestore_fn,
void *intrsenabled_fn, void *intr_arg);
extern void si_deregister_intr_callback(si_t *sih);
extern void si_clkctl_init(si_t *sih);
extern uint16 si_clkctl_fast_pwrup_delay(si_t *sih);
extern bool si_clkctl_cc(si_t *sih, uint mode);
extern int si_clkctl_xtal(si_t *sih, uint what, bool on);
extern uint32 si_gpiotimerval(si_t *sih, uint32 mask, uint32 val);
extern void si_btcgpiowar(si_t *sih);
extern bool si_deviceremoved(si_t *sih);
extern uint32 si_socram_size(si_t *sih);
extern uint32 si_socdevram_size(si_t *sih);
extern void si_socdevram(si_t *sih, bool set, uint8 *ennable, uint8 *protect, uint8 *remap);
extern bool si_socdevram_pkg(si_t *sih);
extern bool si_socdevram_remap_isenb(si_t *sih);
extern uint32 si_socdevram_remap_size(si_t *sih);
extern void si_watchdog(si_t *sih, uint ticks);
extern void si_watchdog_ms(si_t *sih, uint32 ms);
extern uint32 si_watchdog_msticks(void);
extern void *si_gpiosetcore(si_t *sih);
extern uint32 si_gpiocontrol(si_t *sih, uint32 mask, uint32 val, uint8 priority);
extern uint32 si_gpioouten(si_t *sih, uint32 mask, uint32 val, uint8 priority);
extern uint32 si_gpioout(si_t *sih, uint32 mask, uint32 val, uint8 priority);
extern uint32 si_gpioin(si_t *sih);
extern uint32 si_gpiointpolarity(si_t *sih, uint32 mask, uint32 val, uint8 priority);
extern uint32 si_gpiointmask(si_t *sih, uint32 mask, uint32 val, uint8 priority);
extern uint32 si_gpioled(si_t *sih, uint32 mask, uint32 val);
extern uint32 si_gpioreserve(si_t *sih, uint32 gpio_num, uint8 priority);
extern uint32 si_gpiorelease(si_t *sih, uint32 gpio_num, uint8 priority);
extern uint32 si_gpiopull(si_t *sih, bool updown, uint32 mask, uint32 val);
extern uint32 si_gpioevent(si_t *sih, uint regtype, uint32 mask, uint32 val);
extern uint32 si_gpio_int_enable(si_t *sih, bool enable);
extern void *si_gpio_handler_register(si_t *sih, uint32 e, bool lev, gpio_handler_t cb, void *arg);
extern void si_gpio_handler_unregister(si_t *sih, void* gpioh);
extern void si_gpio_handler_process(si_t *sih);
extern bool si_pci_pmecap(si_t *sih);
struct osl_info;
extern bool si_pci_fastpmecap(struct osl_info *osh);
extern bool si_pci_pmestat(si_t *sih);
extern void si_pci_pmeclr(si_t *sih);
extern void si_pci_pmeen(si_t *sih);
extern void si_pci_pmestatclr(si_t *sih);
extern uint si_pcie_readreg(void *sih, uint addrtype, uint offset);
extern uint si_pcie_writereg(void *sih, uint addrtype, uint offset, uint val);
extern void si_sdio_init(si_t *sih);
extern uint16 si_d11_devid(si_t *sih);
extern int si_corepciid(si_t *sih, uint func, uint16 *pcivendor, uint16 *pcidevice,
uint8 *pciclass, uint8 *pcisubclass, uint8 *pciprogif, uint8 *pciheader);
#define si_eci(sih) 0
static INLINE void * si_eci_init(si_t *sih) {return NULL;}
#define si_eci_notify_bt(sih, type, val) (0)
#define si_seci(sih) 0
#define si_seci_upd(sih, a) do {} while (0)
static INLINE void * si_seci_init(si_t *sih, uint8 use_seci) {return NULL;}
static INLINE void * si_gci_init(si_t *sih) {return NULL;}
#define si_seci_down(sih) do {} while (0)
#define si_gci(sih) 0
extern bool si_is_otp_disabled(si_t *sih);
extern bool si_is_otp_powered(si_t *sih);
extern void si_otp_power(si_t *sih, bool on);
extern bool si_is_sprom_available(si_t *sih);
extern bool si_is_sprom_enabled(si_t *sih);
extern void si_sprom_enable(si_t *sih, bool enable);
extern int si_cis_source(si_t *sih);
#define CIS_DEFAULT 0
#define CIS_SROM 1
#define CIS_OTP 2
#define DEFAULT_FAB 0x0
#define CSM_FAB7 0x1
#define TSMC_FAB12 0x2
#define SMIC_FAB4 0x3
extern int BCMINITFN(si_otp_fabid)(si_t *sih, uint16 *fabid, bool rw);
extern uint16 BCMATTACHFN(si_fabid)(si_t *sih);
extern int si_devpath(si_t *sih, char *path, int size);
extern char *si_getdevpathvar(si_t *sih, const char *name);
extern int si_getdevpathintvar(si_t *sih, const char *name);
extern char *si_coded_devpathvar(si_t *sih, char *varname, int var_len, const char *name);
extern uint8 si_pcieclkreq(si_t *sih, uint32 mask, uint32 val);
extern uint32 si_pcielcreg(si_t *sih, uint32 mask, uint32 val);
extern uint8 si_pcieltrenable(si_t *sih, uint32 mask, uint32 val);
extern uint8 si_pcieobffenable(si_t *sih, uint32 mask, uint32 val);
extern uint32 si_pcieltr_reg(si_t *sih, uint32 reg, uint32 mask, uint32 val);
extern uint32 si_pcieltrspacing_reg(si_t *sih, uint32 mask, uint32 val);
extern uint32 si_pcieltrhysteresiscnt_reg(si_t *sih, uint32 mask, uint32 val);
extern void si_pcie_set_error_injection(si_t *sih, uint32 mode);
extern void si_pcie_set_L1substate(si_t *sih, uint32 substate);
extern uint32 si_pcie_get_L1substate(si_t *sih);
extern void si_war42780_clkreq(si_t *sih, bool clkreq);
extern void si_pci_down(si_t *sih);
extern void si_pci_up(si_t *sih);
extern void si_pci_sleep(si_t *sih);
extern void si_pcie_war_ovr_update(si_t *sih, uint8 aspm);
extern void si_pcie_power_save_enable(si_t *sih, bool enable);
extern void si_pcie_extendL1timer(si_t *sih, bool extend);
extern int si_pci_fixcfg(si_t *sih);
extern void si_chippkg_set(si_t *sih, uint);
extern void si_chipcontrl_btshd0_4331(si_t *sih, bool on);
extern void si_chipcontrl_restore(si_t *sih, uint32 val);
extern uint32 si_chipcontrl_read(si_t *sih);
extern void si_chipcontrl_epa4331(si_t *sih, bool on);
extern void si_chipcontrl_epa4331_wowl(si_t *sih, bool enter_wowl);
extern void si_chipcontrl_srom4360(si_t *sih, bool on);
extern void si_epa_4313war(si_t *sih);
extern void si_btc_enable_chipcontrol(si_t *sih);
extern void si_btcombo_p250_4313_war(si_t *sih);
extern void si_btcombo_43228_war(si_t *sih);
extern void si_clk_pmu_htavail_set(si_t *sih, bool set_clear);
extern void si_pmu_synth_pwrsw_4313_war(si_t *sih);
extern uint si_pll_reset(si_t *sih);
extern bool si_taclear(si_t *sih, bool details);
extern uint32 si_ccreg(si_t *sih, uint32 offset, uint32 mask, uint32 val);
extern uint32 si_pciereg(si_t *sih, uint32 offset, uint32 mask, uint32 val, uint type);
extern uint32 write_ccreg(si_t *sih, uint32 offset, uint32 mask, uint32 val);
extern uint32 si_pcieserdesreg(si_t *sih, uint32 mdioslave, uint32 offset, uint32 mask, uint32 val);
extern void si_pcie_set_request_size(si_t *sih, uint16 size);
extern uint16 si_pcie_get_request_size(si_t *sih);
extern void si_pcie_set_maxpayload_size(si_t *sih, uint16 size);
extern uint16 si_pcie_get_maxpayload_size(si_t *sih);
extern uint16 si_pcie_get_ssid(si_t *sih);
extern uint32 si_pcie_get_bar0(si_t *sih);
extern int si_pcie_configspace_cache(si_t *sih);
extern int si_pcie_configspace_restore(si_t *sih);
extern int si_pcie_configspace_get(si_t *sih, uint8 *buf, uint size);
char *si_getnvramflvar(si_t *sih, const char *name);
extern uint32 si_tcm_size(si_t *sih);
extern bool si_has_flops(si_t *sih);
extern uint32 si_gci_direct(si_t *sih, uint offset, uint32 mask, uint32 val);
extern uint32 si_gci_indirect(si_t *sih, uint regidx, uint offset, uint32 mask, uint32 val);
extern uint32 si_gci_output(si_t *sih, uint reg, uint32 mask, uint32 val);
extern uint32 si_gci_input(si_t *sih, uint reg);
extern uint32 si_gci_int_enable(si_t *sih, bool enable);
extern void si_gci_reset(si_t *sih);
extern void si_ercx_init(si_t *sih);
extern void si_wci2_init(si_t *sih);
extern void si_gci_seci_init(si_t *sih);
extern void si_gci_set_functionsel(si_t *sih, uint32 pin, uint8 fnsel);
extern uint8 si_gci_get_chipctrlreg_idx(uint32 pin, uint32 *regidx, uint32 *pos);
extern uint32 si_gci_chipcontrol(si_t *sih, uint reg, uint32 mask, uint32 val);
extern int si_set_sromctl(si_t *sih, uint32 value);
extern uint32 si_get_sromctl(si_t *sih);
extern uint16 si_cc_get_reg16(uint32 reg_offs);
extern uint32 si_cc_get_reg32(uint32 reg_offs);
extern uint32 si_cc_set_reg32(uint32 reg_offs, uint32 val);
extern uint32 si_gci_preinit_upd_indirect(uint32 regidx, uint32 setval, uint32 mask);
extern uint si_chipid_override(si_t *sih);
extern uint si_chiprev_override(si_t *sih);
#define CHIPCTRLREG1 0x1
#define CHIPCTRLREG2 0x2
#define CHIPCTRLREG3 0x3
#define CHIPCTRLREG4 0x4
#define CHIPCTRLREG5 0x5
#define REGCTRLREG4 0x4
#define MINRESMASKREG 0x618
#define MAXRESMASKREG 0x61c
#define CHIPCTRLADDR 0x650
#define CHIPCTRLDATA 0x654
#define RSRCTABLEADDR 0x620
#define RSRCUPDWNTIME 0x628
#define PMUREG_RESREQ_MASK 0x68c
extern void si_update_masks(si_t *sih);
extern void si_force_islanding(si_t *sih, bool enable);
extern uint32 si_pmu_res_req_timer_clr(si_t *sih);
extern void si_pmu_rfldo(si_t *sih, bool on);
#endif

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/*
* SPI device spec header file
*
* Copyright (C) 2013, Broadcom Corporation
* All Rights Reserved.
*
* This is UNPUBLISHED PROPRIETARY SOURCE CODE of Broadcom Corporation;
* the contents of this file may not be disclosed to third parties, copied
* or duplicated in any form, in whole or in part, without the prior
* written permission of Broadcom Corporation.
*
* $Id: spid.h 241182 2011-02-17 21:50:03Z $
*/
#ifndef _SPI_H
#define _SPI_H
/*
* Brcm SPI Device Register Map.
*
*/
typedef volatile struct {
uint8 config; /* 0x00, len, endian, clock, speed, polarity, wakeup */
uint8 response_delay; /* 0x01, read response delay in bytes (corerev < 3) */
uint8 status_enable; /* 0x02, status-enable, intr with status, response_delay
* function selection, command/data error check
*/
uint8 reset_bp; /* 0x03, reset on wlan/bt backplane reset (corerev >= 1) */
uint16 intr_reg; /* 0x04, Intr status register */
uint16 intr_en_reg; /* 0x06, Intr mask register */
uint32 status_reg; /* 0x08, RO, Status bits of last spi transfer */
uint16 f1_info_reg; /* 0x0c, RO, enabled, ready for data transfer, blocksize */
uint16 f2_info_reg; /* 0x0e, RO, enabled, ready for data transfer, blocksize */
uint16 f3_info_reg; /* 0x10, RO, enabled, ready for data transfer, blocksize */
uint32 test_read; /* 0x14, RO 0xfeedbead signature */
uint32 test_rw; /* 0x18, RW */
uint8 resp_delay_f0; /* 0x1c, read resp delay bytes for F0 (corerev >= 3) */
uint8 resp_delay_f1; /* 0x1d, read resp delay bytes for F1 (corerev >= 3) */
uint8 resp_delay_f2; /* 0x1e, read resp delay bytes for F2 (corerev >= 3) */
uint8 resp_delay_f3; /* 0x1f, read resp delay bytes for F3 (corerev >= 3) */
} spi_regs_t;
/* SPI device register offsets */
#define SPID_CONFIG 0x00
#define SPID_RESPONSE_DELAY 0x01
#define SPID_STATUS_ENABLE 0x02
#define SPID_RESET_BP 0x03 /* (corerev >= 1) */
#define SPID_INTR_REG 0x04 /* 16 bits - Interrupt status */
#define SPID_INTR_EN_REG 0x06 /* 16 bits - Interrupt mask */
#define SPID_STATUS_REG 0x08 /* 32 bits */
#define SPID_F1_INFO_REG 0x0C /* 16 bits */
#define SPID_F2_INFO_REG 0x0E /* 16 bits */
#define SPID_F3_INFO_REG 0x10 /* 16 bits */
#define SPID_TEST_READ 0x14 /* 32 bits */
#define SPID_TEST_RW 0x18 /* 32 bits */
#define SPID_RESP_DELAY_F0 0x1c /* 8 bits (corerev >= 3) */
#define SPID_RESP_DELAY_F1 0x1d /* 8 bits (corerev >= 3) */
#define SPID_RESP_DELAY_F2 0x1e /* 8 bits (corerev >= 3) */
#define SPID_RESP_DELAY_F3 0x1f /* 8 bits (corerev >= 3) */
/* Bit masks for SPID_CONFIG device register */
#define WORD_LENGTH_32 0x1 /* 0/1 16/32 bit word length */
#define ENDIAN_BIG 0x2 /* 0/1 Little/Big Endian */
#define CLOCK_PHASE 0x4 /* 0/1 clock phase delay */
#define CLOCK_POLARITY 0x8 /* 0/1 Idle state clock polarity is low/high */
#define HIGH_SPEED_MODE 0x10 /* 1/0 High Speed mode / Normal mode */
#define INTR_POLARITY 0x20 /* 1/0 Interrupt active polarity is high/low */
#define WAKE_UP 0x80 /* 0/1 Wake-up command from Host to WLAN */
/* Bit mask for SPID_RESPONSE_DELAY device register */
#define RESPONSE_DELAY_MASK 0xFF /* Configurable rd response delay in multiples of 8 bits */
/* Bit mask for SPID_STATUS_ENABLE device register */
#define STATUS_ENABLE 0x1 /* 1/0 Status sent/not sent to host after read/write */
#define INTR_WITH_STATUS 0x2 /* 0/1 Do-not / do-interrupt if status is sent */
#define RESP_DELAY_ALL 0x4 /* Applicability of resp delay to F1 or all func's read */
#define DWORD_PKT_LEN_EN 0x8 /* Packet len denoted in dwords instead of bytes */
#define CMD_ERR_CHK_EN 0x20 /* Command error check enable */
#define DATA_ERR_CHK_EN 0x40 /* Data error check enable */
/* Bit mask for SPID_RESET_BP device register */
#define RESET_ON_WLAN_BP_RESET 0x4 /* enable reset for WLAN backplane */
#define RESET_ON_BT_BP_RESET 0x8 /* enable reset for BT backplane */
#define RESET_SPI 0x80 /* reset the above enabled logic */
/* Bit mask for SPID_INTR_REG device register */
#define DATA_UNAVAILABLE 0x0001 /* Requested data not available; Clear by writing a "1" */
#define F2_F3_FIFO_RD_UNDERFLOW 0x0002
#define F2_F3_FIFO_WR_OVERFLOW 0x0004
#define COMMAND_ERROR 0x0008 /* Cleared by writing 1 */
#define DATA_ERROR 0x0010 /* Cleared by writing 1 */
#define F2_PACKET_AVAILABLE 0x0020
#define F3_PACKET_AVAILABLE 0x0040
#define F1_OVERFLOW 0x0080 /* Due to last write. Bkplane has pending write requests */
#define MISC_INTR0 0x0100
#define MISC_INTR1 0x0200
#define MISC_INTR2 0x0400
#define MISC_INTR3 0x0800
#define MISC_INTR4 0x1000
#define F1_INTR 0x2000
#define F2_INTR 0x4000
#define F3_INTR 0x8000
/* Bit mask for 32bit SPID_STATUS_REG device register */
#define STATUS_DATA_NOT_AVAILABLE 0x00000001
#define STATUS_UNDERFLOW 0x00000002
#define STATUS_OVERFLOW 0x00000004
#define STATUS_F2_INTR 0x00000008
#define STATUS_F3_INTR 0x00000010
#define STATUS_F2_RX_READY 0x00000020
#define STATUS_F3_RX_READY 0x00000040
#define STATUS_HOST_CMD_DATA_ERR 0x00000080
#define STATUS_F2_PKT_AVAILABLE 0x00000100
#define STATUS_F2_PKT_LEN_MASK 0x000FFE00
#define STATUS_F2_PKT_LEN_SHIFT 9
#define STATUS_F3_PKT_AVAILABLE 0x00100000
#define STATUS_F3_PKT_LEN_MASK 0xFFE00000
#define STATUS_F3_PKT_LEN_SHIFT 21
/* Bit mask for 16 bits SPID_F1_INFO_REG device register */
#define F1_ENABLED 0x0001
#define F1_RDY_FOR_DATA_TRANSFER 0x0002
#define F1_MAX_PKT_SIZE 0x01FC
/* Bit mask for 16 bits SPID_F2_INFO_REG device register */
#define F2_ENABLED 0x0001
#define F2_RDY_FOR_DATA_TRANSFER 0x0002
#define F2_MAX_PKT_SIZE 0x3FFC
/* Bit mask for 16 bits SPID_F3_INFO_REG device register */
#define F3_ENABLED 0x0001
#define F3_RDY_FOR_DATA_TRANSFER 0x0002
#define F3_MAX_PKT_SIZE 0x3FFC
/* Bit mask for 32 bits SPID_TEST_READ device register read in 16bit LE mode */
#define TEST_RO_DATA_32BIT_LE 0xFEEDBEAD
/* Maximum number of I/O funcs */
#define SPI_MAX_IOFUNCS 4
#define SPI_MAX_PKT_LEN (2048*4)
/* Misc defines */
#define SPI_FUNC_0 0
#define SPI_FUNC_1 1
#define SPI_FUNC_2 2
#define SPI_FUNC_3 3
#define WAIT_F2RXFIFORDY 100
#define WAIT_F2RXFIFORDY_DELAY 20
#endif /* _SPI_H */

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/*
* TRX image file header format.
*
* $Copyright Open Broadcom Corporation$
*
* $Id: trxhdr.h 314841 2012-02-14 18:28:33Z chandrum $
*/
#ifndef _TRX_HDR_H
#define _TRX_HDR_H
#include <typedefs.h>
#define TRX_MAGIC 0x30524448 /* "HDR0" */
#define TRX_MAX_LEN 0x3B0000 /* Max length */
#define TRX_NO_HEADER 1 /* Do not write TRX header */
#define TRX_GZ_FILES 0x2 /* Contains up to TRX_MAX_OFFSET individual gzip files */
#define TRX_EMBED_UCODE 0x8 /* Trx contains embedded ucode image */
#define TRX_ROMSIM_IMAGE 0x10 /* Trx contains ROM simulation image */
#define TRX_UNCOMP_IMAGE 0x20 /* Trx contains uncompressed rtecdc.bin image */
#define TRX_BOOTLOADER 0x40 /* the image is a bootloader */
#define TRX_V1 1
#define TRX_V1_MAX_OFFSETS 3 /* V1: Max number of individual files */
#ifndef BCMTRXV2
#define TRX_VERSION TRX_V1 /* Version 1 */
#define TRX_MAX_OFFSET TRX_V1_MAX_OFFSETS
#endif
/* BMAC Host driver/application like bcmdl need to support both Ver 1 as well as
* Ver 2 of trx header. To make it generic, trx_header is structure is modified
* as below where size of "offsets" field will vary as per the TRX version.
* Currently, BMAC host driver and bcmdl are modified to support TRXV2 as well.
* To make sure, other applications like "dhdl" which are yet to be enhanced to support
* TRXV2 are not broken, new macro and structure defintion take effect only when BCMTRXV2
* is defined.
*/
struct trx_header {
uint32 magic; /* "HDR0" */
uint32 len; /* Length of file including header */
uint32 crc32; /* 32-bit CRC from flag_version to end of file */
uint32 flag_version; /* 0:15 flags, 16:31 version */
#ifndef BCMTRXV2
uint32 offsets[TRX_MAX_OFFSET]; /* Offsets of partitions from start of header */
#else
uint32 offsets[1]; /* Offsets of partitions from start of header */
#endif
};
#ifdef BCMTRXV2
#define TRX_VERSION TRX_V2 /* Version 2 */
#define TRX_MAX_OFFSET TRX_V2_MAX_OFFSETS
#define TRX_V2 2
/* V2: Max number of individual files
* To support SDR signature + Config data region
*/
#define TRX_V2_MAX_OFFSETS 5
#define SIZEOF_TRXHDR_V1 (sizeof(struct trx_header)+(TRX_V1_MAX_OFFSETS-1)*sizeof(uint32))
#define SIZEOF_TRXHDR_V2 (sizeof(struct trx_header)+(TRX_V2_MAX_OFFSETS-1)*sizeof(uint32))
#define TRX_VER(trx) (trx->flag_version>>16)
#define ISTRX_V1(trx) (TRX_VER(trx) == TRX_V1)
#define ISTRX_V2(trx) (TRX_VER(trx) == TRX_V2)
/* For V2, return size of V2 size: others, return V1 size */
#define SIZEOF_TRX(trx) (ISTRX_V2(trx) ? SIZEOF_TRXHDR_V2: SIZEOF_TRXHDR_V1)
#else
#define SIZEOF_TRX(trx) (sizeof(struct trx_header))
#endif /* BCMTRXV2 */
/* Compatibility */
typedef struct trx_header TRXHDR, *PTRXHDR;
#endif /* _TRX_HDR_H */

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/*
* $Copyright Open Broadcom Corporation$
* $Id: typedefs.h 401759 2013-05-13 16:08:08Z sudhirbs $
*/
#ifndef _TYPEDEFS_H_
#define _TYPEDEFS_H_
#ifdef SITE_TYPEDEFS
/*
* Define SITE_TYPEDEFS in the compile to include a site-specific
* typedef file "site_typedefs.h".
*
* If SITE_TYPEDEFS is not defined, then the code section below makes
* inferences about the compile environment based on defined symbols and
* possibly compiler pragmas.
*
* Following these two sections is the Default Typedefs section.
* This section is only processed if USE_TYPEDEF_DEFAULTS is
* defined. This section has a default set of typedefs and a few
* preprocessor symbols (TRUE, FALSE, NULL, ...).
*/
#include "site_typedefs.h"
#else
/*
* Infer the compile environment based on preprocessor symbols and pragmas.
* Override type definitions as needed, and include configuration-dependent
* header files to define types.
*/
#ifdef __cplusplus
#define TYPEDEF_BOOL
#ifndef FALSE
#define FALSE false
#endif
#ifndef TRUE
#define TRUE true
#endif
#else /* ! __cplusplus */
#if defined(_WIN32)
#define TYPEDEF_BOOL
typedef unsigned char bool; /* consistent w/BOOL */
#endif /* _WIN32 */
#endif /* ! __cplusplus */
#if defined(_WIN64) && !defined(EFI)
/* use the Windows ULONG_PTR type when compiling for 64 bit */
#include <basetsd.h>
#define TYPEDEF_UINTPTR
typedef ULONG_PTR uintptr;
#elif defined(__x86_64__)
#define TYPEDEF_UINTPTR
typedef unsigned long long int uintptr;
#endif
#if defined(_HNDRTE_) && !defined(_HNDRTE_SIM_)
#define _NEED_SIZE_T_
#endif
#if defined(_MINOSL_)
#define _NEED_SIZE_T_
#endif
#if defined(EFI) && !defined(_WIN64)
#define _NEED_SIZE_T_
#endif
#if defined(TARGETOS_nucleus)
/* for 'size_t' type */
#include <stddef.h>
/* float_t types conflict with the same typedefs from the standard ANSI-C
** math.h header file. Don't re-typedef them here.
*/
#define TYPEDEF_FLOAT_T
#endif /* TARGETOS_nucleus */
#if defined(_NEED_SIZE_T_)
typedef long unsigned int size_t;
#endif
#ifdef _MSC_VER /* Microsoft C */
#define TYPEDEF_INT64
#define TYPEDEF_UINT64
typedef signed __int64 int64;
typedef unsigned __int64 uint64;
#endif
#if defined(MACOSX)
#define TYPEDEF_BOOL
#endif /* MACOSX */
#if defined(__NetBSD__)
#ifndef _KERNEL
#include <stdbool.h>
#endif
#define TYPEDEF_BOOL
#define TYPEDEF_UINT
#define TYPEDEF_USHORT
#define TYPEDEF_ULONG
#endif /* NetBSD */
#if defined(__sparc__)
#define TYPEDEF_ULONG
#endif
#if defined(vxworks)
#define TYPEDEF_USHORT
typedef unsigned int socklen_t;
#endif
#ifdef linux
/*
* If this is either a Linux hybrid build or the per-port code of a hybrid build
* then use the Linux header files to get some of the typedefs. Otherwise, define
* them entirely in this file. We can't always define the types because we get
* a duplicate typedef error; there is no way to "undefine" a typedef.
* We know when it's per-port code because each file defines LINUX_PORT at the top.
*/
#if !defined(LINUX_HYBRID) || defined(LINUX_PORT)
#define TYPEDEF_UINT
#ifndef TARGETENV_android
#define TYPEDEF_USHORT
#define TYPEDEF_ULONG
#endif /* TARGETENV_android */
#ifdef __KERNEL__
#include <linux/version.h>
#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 19))
#define TYPEDEF_BOOL
#endif /* >= 2.6.19 */
/* special detection for 2.6.18-128.7.1.0.1.el5 */
#if (LINUX_VERSION_CODE == KERNEL_VERSION(2, 6, 18))
#include <linux/compiler.h>
#ifdef noinline_for_stack
#define TYPEDEF_BOOL
#endif
#endif /* == 2.6.18 */
#endif /* __KERNEL__ */
#endif /* !defined(LINUX_HYBRID) || defined(LINUX_PORT) */
#endif /* linux */
#if defined(__ECOS)
#define TYPEDEF_UCHAR
#define TYPEDEF_UINT
#define TYPEDEF_USHORT
#define TYPEDEF_ULONG
#define TYPEDEF_BOOL
#endif
#if !defined(linux) && !defined(vxworks) && !defined(_WIN32) && !defined(_CFE_) && \
!defined(_HNDRTE_) && !defined(_MINOSL_) && !defined(__DJGPP__) && \
!defined(__IOPOS__) && !defined(__ECOS) && !defined(__BOB__) && \
!defined(TARGETOS_nucleus) && !defined(EFI) && !defined(__FreeBSD__)
#define TYPEDEF_UINT
#define TYPEDEF_USHORT
#endif
#if defined(vxworks)
/* Do not support the int64 type in VxWorks */
#define TYPEDEF_INT64
#endif
/* Do not support the (u)int64 types with strict ansi for GNU C */
#if defined(__GNUC__) && defined(__STRICT_ANSI__)
#define TYPEDEF_INT64
#define TYPEDEF_UINT64
#endif
/* ICL accepts unsigned 64 bit type only, and complains in ANSI mode
* for signed or unsigned
*/
#if defined(__ICL)
#define TYPEDEF_INT64
#if defined(__STDC__)
#define TYPEDEF_UINT64
#endif
#endif /* __ICL */
#if !defined(_WIN32) && !defined(_CFE_) && !defined(_HNDRTE_) && !defined(_MINOSL_) && \
!defined(__DJGPP__) && !defined(__IOPOS__) && !defined(__BOB__) && \
!defined(TARGETOS_nucleus) && !defined(EFI)
/* pick up ushort & uint from standard types.h */
#if defined(linux) && defined(__KERNEL__)
/* See note above */
#if !defined(LINUX_HYBRID) || defined(LINUX_PORT)
#ifdef USER_MODE
#include <sys/types.h>
#else
#include <linux/types.h> /* sys/types.h and linux/types.h are oil and water */
#endif /* USER_MODE */
#endif /* !defined(LINUX_HYBRID) || defined(LINUX_PORT) */
#else
#if defined(__ECOS)
#include <pkgconf/infra.h>
#include <cyg/infra/cyg_type.h>
#include <stdarg.h>
#endif
#include <sys/types.h>
#endif /* linux && __KERNEL__ */
#endif /* !_WIN32 && !PMON && !_CFE_ && !_HNDRTE_ && !_MINOSL_ && !__DJGPP__ */
#if defined(MACOSX)
#ifdef __BIG_ENDIAN__
#define IL_BIGENDIAN
#else
#ifdef IL_BIGENDIAN
#error "IL_BIGENDIAN was defined for a little-endian compile"
#endif
#endif /* __BIG_ENDIAN__ */
#if !defined(__cplusplus)
#if defined (__i386__)
typedef unsigned char bool;
#else
typedef unsigned int bool;
#endif
#define TYPE_BOOL 1
enum {
false = 0,
true = 1
};
#if defined(KERNEL)
#include <IOKit/IOTypes.h>
#endif /* KERNEL */
#endif /* __cplusplus */
#endif /* MACOSX */
#if defined(vxworks)
#include <private/cplusLibP.h>
#endif
/* use the default typedefs in the next section of this file */
#define USE_TYPEDEF_DEFAULTS
#endif /* SITE_TYPEDEFS */
/*
* Default Typedefs
*/
#ifdef USE_TYPEDEF_DEFAULTS
#undef USE_TYPEDEF_DEFAULTS
#ifndef TYPEDEF_BOOL
typedef /* @abstract@ */ unsigned char bool;
#endif
/* define uchar, ushort, uint, ulong */
#ifndef TYPEDEF_UCHAR
typedef unsigned char uchar;
#endif
#ifndef TYPEDEF_USHORT
typedef unsigned short ushort;
#endif
#ifndef TYPEDEF_UINT
typedef unsigned int uint;
#endif
#ifndef TYPEDEF_ULONG
typedef unsigned long ulong;
#endif
/* define [u]int8/16/32/64, uintptr */
#ifndef TYPEDEF_UINT8
typedef unsigned char uint8;
#endif
#ifndef TYPEDEF_UINT16
typedef unsigned short uint16;
#endif
#ifndef TYPEDEF_UINT32
typedef unsigned int uint32;
#endif
#ifndef TYPEDEF_UINT64
typedef unsigned long long uint64;
#endif
#ifndef TYPEDEF_UINTPTR
typedef unsigned int uintptr;
#endif
#ifndef TYPEDEF_INT8
typedef signed char int8;
#endif
#ifndef TYPEDEF_INT16
typedef signed short int16;
#endif
#ifndef TYPEDEF_INT32
typedef signed int int32;
#endif
#ifndef TYPEDEF_INT64
typedef signed long long int64;
#endif
/* define float32/64, float_t */
#ifndef TYPEDEF_FLOAT32
typedef float float32;
#endif
#ifndef TYPEDEF_FLOAT64
typedef double float64;
#endif
/*
* abstracted floating point type allows for compile time selection of
* single or double precision arithmetic. Compiling with -DFLOAT32
* selects single precision; the default is double precision.
*/
#ifndef TYPEDEF_FLOAT_T
#if defined(FLOAT32)
typedef float32 float_t;
#else /* default to double precision floating point */
typedef float64 float_t;
#endif
#endif /* TYPEDEF_FLOAT_T */
/* define macro values */
#ifndef FALSE
#define FALSE 0
#endif
#ifndef TRUE
#define TRUE 1 /* TRUE */
#endif
#ifndef NULL
#define NULL 0
#endif
#ifndef OFF
#define OFF 0
#endif
#ifndef ON
#define ON 1 /* ON = 1 */
#endif
#define AUTO (-1) /* Auto = -1 */
/* define PTRSZ, INLINE */
#ifndef PTRSZ
#define PTRSZ sizeof(char*)
#endif
/* Detect compiler type. */
#ifdef _MSC_VER
#define BWL_COMPILER_MICROSOFT
#elif defined(__GNUC__) || defined(__lint)
#define BWL_COMPILER_GNU
#elif defined(__CC_ARM) && __CC_ARM
#define BWL_COMPILER_ARMCC
#else
#error "Unknown compiler!"
#endif /* _MSC_VER */
#ifndef INLINE
#if defined(BWL_COMPILER_MICROSOFT)
#define INLINE __inline
#elif defined(BWL_COMPILER_GNU)
#define INLINE __inline__
#elif defined(BWL_COMPILER_ARMCC)
#define INLINE __inline
#else
#define INLINE
#endif /* _MSC_VER */
#endif /* INLINE */
#undef TYPEDEF_BOOL
#undef TYPEDEF_UCHAR
#undef TYPEDEF_USHORT
#undef TYPEDEF_UINT
#undef TYPEDEF_ULONG
#undef TYPEDEF_UINT8
#undef TYPEDEF_UINT16
#undef TYPEDEF_UINT32
#undef TYPEDEF_UINT64
#undef TYPEDEF_UINTPTR
#undef TYPEDEF_INT8
#undef TYPEDEF_INT16
#undef TYPEDEF_INT32
#undef TYPEDEF_INT64
#undef TYPEDEF_FLOAT32
#undef TYPEDEF_FLOAT64
#undef TYPEDEF_FLOAT_T
#endif /* USE_TYPEDEF_DEFAULTS */
/* Suppress unused parameter warning */
#define UNUSED_PARAMETER(x) (void)(x)
/* Avoid warning for discarded const or volatile qualifier in special cases (-Wcast-qual) */
#define DISCARD_QUAL(ptr, type) ((type *)(uintptr)(ptr))
/*
* Including the bcmdefs.h here, to make sure everyone including typedefs.h
* gets this automatically
*/
#include <bcmdefs.h>
#endif /* _TYPEDEFS_H_ */

205
external/cache/sources/wl/include/usbrdl.h vendored Normal file
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/*
* Broadcom USB remote download definitions
*
* $Copyright Open Broadcom Corporation$
*
* $Id: usbrdl.h 394558 2013-04-03 00:11:01Z kadavath $
*/
#ifndef _USB_RDL_H
#define _USB_RDL_H
/* Control messages: bRequest values */
#define DL_GETSTATE 0 /* returns the rdl_state_t struct */
#define DL_CHECK_CRC 1 /* currently unused */
#define DL_GO 2 /* execute downloaded image */
#define DL_START 3 /* initialize dl state */
#define DL_REBOOT 4 /* reboot the device in 2 seconds */
#define DL_GETVER 5 /* returns the bootrom_id_t struct */
#define DL_GO_PROTECTED 6 /* execute the downloaded code and set reset event
* to occur in 2 seconds. It is the responsibility
* of the downloaded code to clear this event
*/
#define DL_EXEC 7 /* jump to a supplied address */
#define DL_RESETCFG 8 /* To support single enum on dongle
* - Not used by bootloader
*/
#define DL_DEFER_RESP_OK 9 /* Potentially defer the response to setup
* if resp unavailable
*/
#define DL_HWCMD_MASK 0xfc /* Mask for hardware read commands: */
#define DL_RDHW 0x10 /* Read a hardware address (Ctl-in) */
#define DL_RDHW32 0x10 /* Read a 32 bit word */
#define DL_RDHW16 0x11 /* Read 16 bits */
#define DL_RDHW8 0x12 /* Read an 8 bit byte */
#define DL_WRHW 0x14 /* Write a hardware address (Ctl-out) */
#define DL_WRHW_BLK 0x13 /* Block write to hardware access */
#define DL_CMD_RDHW 1 /* read data from a backplane address */
#define DL_CMD_WRHW 2 /* write data to a backplane address */
#ifndef LINUX_POSTMOGRIFY_REMOVAL
#define DL_JTCONF 0x15 /* Get JTAG configuration (Ctl_in)
* Set JTAG configuration (Ctl-out)
*/
#define DL_JTON 0x16 /* Turn on jtag master (Ctl-in) */
#define DL_JTOFF 0x17 /* Turn on jtag master (Ctl-in) */
#define DL_RDRJT 0x18 /* Read a JTAG register (Ctl-in) */
#define DL_WRJT 0x19 /* Write a hardware address over JTAG (Ctl/Bulk-out) */
#define DL_WRRJT 0x1a /* Write a JTAG register (Ctl/Bulk-out) */
#define DL_JTRST 0x1b /* Reset jtag fsm on jtag DUT (Ctl-in) */
#define DL_RDJT 0x1c /* Read a hardware address over JTAG (Ctl-in) */
#define DL_RDJT32 0x1c /* Read 32 bits */
#define DL_RDJT16 0x1e /* Read 16 bits (sz = 4 - low bits) */
#define DL_RDJT8 0x1f /* Read 8 bits */
#define DL_MRDJT 0x20 /* Multiple read over JTAG (Ctl-out+Bulk-in) */
#define DL_MRDJT32 0x20 /* M-read 32 bits */
#define DL_MRDJT16 0x22 /* M-read 16 bits (sz = 4 - low bits) */
#define DL_MRDJT6 0x23 /* M-read 8 bits */
#define DL_MRDIJT 0x24 /* M-read over JTAG (Ctl-out+Bulk-in) with auto-increment */
#define DL_MRDIJT32 0x24 /* M-read 32 bits w/ai */
#define DL_MRDIJT16 0x26 /* M-read 16 bits w/ai (sz = 4 - low bits) */
#define DL_MRDIJT8 0x27 /* M-read 8 bits w/ai */
#define DL_MRDDJT 0x28 /* M-read over JTAG (Ctl-out+Bulk-in) with auto-decrement */
#define DL_MRDDJT32 0x28 /* M-read 32 bits w/ad */
#define DL_MRDDJT16 0x2a /* M-read 16 bits w/ad (sz = 4 - low bits) */
#define DL_MRDDJT8 0x2b /* M-read 8 bits w/ad */
#define DL_MWRJT 0x2c /* Multiple write over JTAG (Bulk-out) */
#define DL_MWRIJT 0x2d /* With auto-increment */
#define DL_MWRDJT 0x2e /* With auto-decrement */
#define DL_VRDJT 0x2f /* Vector read over JTAG (Bulk-out+Bulk-in) */
#define DL_VWRJT 0x30 /* Vector write over JTAG (Bulk-out+Bulk-in) */
#define DL_SCJT 0x31 /* Jtag scan (Bulk-out+Bulk-in) */
#define DL_CFRD 0x33 /* Reserved for dmamem use */
#define DL_CFWR 0x34 /* Reserved for dmamem use */
#define DL_GET_NVRAM 0x35 /* Query nvram parameter */
#define DL_DBGTRIG 0xFF /* Trigger bRequest type to aid debug */
#define DL_JTERROR 0x80000000
#endif /* LINUX_POSTMOGRIFY_REMOVAL */
/* states */
#define DL_WAITING 0 /* waiting to rx first pkt that includes the hdr info */
#define DL_READY 1 /* hdr was good, waiting for more of the compressed image */
#define DL_BAD_HDR 2 /* hdr was corrupted */
#define DL_BAD_CRC 3 /* compressed image was corrupted */
#define DL_RUNNABLE 4 /* download was successful, waiting for go cmd */
#define DL_START_FAIL 5 /* failed to initialize correctly */
#define DL_NVRAM_TOOBIG 6 /* host specified nvram data exceeds DL_NVRAM value */
#define DL_IMAGE_TOOBIG 7 /* download image too big (exceeds DATA_START for rdl) */
#define TIMEOUT 5000 /* Timeout for usb commands */
struct bcm_device_id {
char *name;
uint32 vend;
uint32 prod;
};
typedef struct {
uint32 state;
uint32 bytes;
} rdl_state_t;
typedef struct {
uint32 chip; /* Chip id */
uint32 chiprev; /* Chip rev */
uint32 ramsize; /* Size of RAM */
uint32 remapbase; /* Current remap base address */
uint32 boardtype; /* Type of board */
uint32 boardrev; /* Board revision */
} bootrom_id_t;
/* struct for backplane & jtag accesses */
typedef struct {
uint32 cmd; /* tag to identify the cmd */
uint32 addr; /* backplane address for write */
uint32 len; /* length of data: 1, 2, 4 bytes */
uint32 data; /* data to write */
} hwacc_t;
/* struct for backplane */
typedef struct {
uint32 cmd; /* tag to identify the cmd */
uint32 addr; /* backplane address for write */
uint32 len; /* length of data: 1, 2, 4 bytes */
uint8 data[1]; /* data to write */
} hwacc_blk_t;
#ifndef LINUX_POSTMOGRIFY_REMOVAL
typedef struct {
uint32 chip; /* Chip id */
uint32 chiprev; /* Chip rev */
uint32 ccrev; /* Chipcommon core rev */
uint32 siclock; /* Backplane clock */
} jtagd_id_t;
/* Jtag configuration structure */
typedef struct {
uint32 cmd; /* tag to identify the cmd */
uint8 clkd; /* Jtag clock divisor */
uint8 disgpio; /* Gpio to disable external driver */
uint8 irsz; /* IR size for readreg/writereg */
uint8 drsz; /* DR size for readreg/writereg */
uint8 bigend; /* Big endian */
uint8 mode; /* Current mode */
uint16 delay; /* Delay between jtagm "simple commands" */
uint32 retries; /* Number of retries for jtagm operations */
uint32 ctrl; /* Jtag control reg copy */
uint32 ir_lvbase; /* Bits to add to IR values in LV tap */
uint32 dretries; /* Number of retries for dma operations */
} jtagconf_t;
/* struct for jtag scan */
#define MAX_USB_IR_BITS 256
#define MAX_USB_DR_BITS 3072
#define USB_IR_WORDS (MAX_USB_IR_BITS / 32)
#define USB_DR_WORDS (MAX_USB_DR_BITS / 32)
typedef struct {
uint32 cmd; /* tag to identify the cmd */
uint32 irsz; /* IR size in bits */
uint32 drsz; /* DR size in bits */
uint32 ts; /* Terminal state (def, pause, rti) */
uint32 data[USB_IR_WORDS + USB_DR_WORDS]; /* IR & DR data */
} scjt_t;
#endif /* LINUX_POSTMOGRIFY_REMOVAL */
/* struct for querying nvram params from bootloader */
#define QUERY_STRING_MAX 32
typedef struct {
uint32 cmd; /* tag to identify the cmd */
char var[QUERY_STRING_MAX]; /* param name */
} nvparam_t;
typedef void (*exec_fn_t)(void *sih);
#define USB_CTRL_IN (USB_TYPE_VENDOR | 0x80 | USB_RECIP_INTERFACE)
#define USB_CTRL_OUT (USB_TYPE_VENDOR | 0 | USB_RECIP_INTERFACE)
#define USB_CTRL_EP_TIMEOUT 500 /* Timeout used in USB control_msg transactions. */
#define RDL_CHUNK 1500 /* size of each dl transfer */
/* bootloader makes special use of trx header "offsets" array */
#define TRX_OFFSETS_DLFWLEN_IDX 0 /* Size of the fw; used in uncompressed case */
#define TRX_OFFSETS_JUMPTO_IDX 1 /* RAM address for jumpto after download */
#define TRX_OFFSETS_NVM_LEN_IDX 2 /* Length of appended NVRAM data */
#ifdef BCMTRXV2
/* The NVRAM region part of trx will be digitally signed in SDR image,
* so is the need for new cfg region which could pass parameters
* which dones not need to be digitally signed
*/
#define TRX_OFFSETS_DSG_LEN_IDX 3 /* Length of digital signature for the first image */
#define TRX_OFFSETS_CFG_LEN_IDX 4 /* Length of config region, which is not digitally signed */
#endif /* BCMTRXV2 */
#define TRX_OFFSETS_DLBASE_IDX 0 /* RAM start address for download */
#endif /* _USB_RDL_H */

218
external/cache/sources/wl/include/wlc_clm_rates.h vendored Normal file
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/*
* Indices for 802.11 a/b/g/n 1-3 chain symmetric transmit rates
* Copyright (C) 2012, Broadcom Corporation
* All Rights Reserved.
*
* This is UNPUBLISHED PROPRIETARY SOURCE CODE of Broadcom Corporation;
* the contents of this file may not be disclosed to third parties, copied
* or duplicated in any form, in whole or in part, without the prior
* written permission of Broadcom Corporation.
*
* $Id: wlc_clm_rates.h 252708 2011-04-12 06:45:56Z fnejati $
*/
#ifndef _WLC_CLM_RATES_H_
#define _WLC_CLM_RATES_H_
#ifdef __cplusplus
extern "C" {
#endif /* __cplusplus */
#define CHSPEC_IS80(x) FALSE
#define WL_RATESET_SZ_DSSS 4
#define WL_RATESET_SZ_OFDM 8
#define WL_RATESET_SZ_HT_MCS 8
#define WL_RATESET_SZ_VHT_MCS 10
#define WL_TX_CHAINS_MAX 3
#define WL_RATE_DISABLED (-128) /* Power value corresponding to unsupported rate */
/* Transmit channel bandwidths */
typedef enum wl_tx_bw {
WL_TX_BW_20,
WL_TX_BW_40,
WL_TX_BW_80,
WL_TX_BW_20IN40,
WL_TX_BW_20IN80,
WL_TX_BW_40IN80,
WL_TX_BW_ALL
} wl_tx_bw_t;
/*
* Transmit modes.
* Not all modes are listed here, only those required for disambiguation. e.g. SPEXP is not listed
*/
typedef enum wl_tx_mode {
WL_TX_MODE_NONE,
WL_TX_MODE_STBC,
WL_TX_MODE_CDD,
WL_TX_MODE_TXBF,
WL_NUM_TX_MODES
} wl_tx_mode_t;
/* Number of transmit chains */
typedef enum wl_tx_chains {
WL_TX_CHAINS_1 = 1,
WL_TX_CHAINS_2,
WL_TX_CHAINS_3
} wl_tx_chains_t;
/* Number of transmit streams */
typedef enum wl_tx_nss {
WL_TX_NSS_1 = 1,
WL_TX_NSS_2,
WL_TX_NSS_3
} wl_tx_nss_t;
typedef enum clm_rates {
/************
* 1 chain *
************
*/
CLM_RATE_1X1_DSSS_1 = 0,
CLM_RATE_1X1_DSSS_2 = 1,
CLM_RATE_1X1_DSSS_5_5 = 2,
CLM_RATE_1X1_DSSS_11 = 3,
CLM_RATE_1X1_OFDM_6 = 4,
CLM_RATE_1X1_OFDM_9 = 5,
CLM_RATE_1X1_OFDM_12 = 6,
CLM_RATE_1X1_OFDM_18 = 7,
CLM_RATE_1X1_OFDM_24 = 8,
CLM_RATE_1X1_OFDM_36 = 9,
CLM_RATE_1X1_OFDM_48 = 10,
CLM_RATE_1X1_OFDM_54 = 11,
CLM_RATE_1X1_MCS0 = 12,
CLM_RATE_1X1_MCS1 = 13,
CLM_RATE_1X1_MCS2 = 14,
CLM_RATE_1X1_MCS3 = 15,
CLM_RATE_1X1_MCS4 = 16,
CLM_RATE_1X1_MCS5 = 17,
CLM_RATE_1X1_MCS6 = 18,
CLM_RATE_1X1_MCS7 = 19,
/************
* 2 chains *
************
*/
/* 1 Stream expanded + 1 */
CLM_RATE_1X2_DSSS_1 = 20,
CLM_RATE_1X2_DSSS_2 = 21,
CLM_RATE_1X2_DSSS_5_5 = 22,
CLM_RATE_1X2_DSSS_11 = 23,
CLM_RATE_1X2_CDD_OFDM_6 = 24,
CLM_RATE_1X2_CDD_OFDM_9 = 25,
CLM_RATE_1X2_CDD_OFDM_12 = 26,
CLM_RATE_1X2_CDD_OFDM_18 = 27,
CLM_RATE_1X2_CDD_OFDM_24 = 28,
CLM_RATE_1X2_CDD_OFDM_36 = 29,
CLM_RATE_1X2_CDD_OFDM_48 = 30,
CLM_RATE_1X2_CDD_OFDM_54 = 31,
CLM_RATE_1X2_CDD_MCS0 = 32,
CLM_RATE_1X2_CDD_MCS1 = 33,
CLM_RATE_1X2_CDD_MCS2 = 34,
CLM_RATE_1X2_CDD_MCS3 = 35,
CLM_RATE_1X2_CDD_MCS4 = 36,
CLM_RATE_1X2_CDD_MCS5 = 37,
CLM_RATE_1X2_CDD_MCS6 = 38,
CLM_RATE_1X2_CDD_MCS7 = 39,
/* 2 Streams */
CLM_RATE_2X2_STBC_MCS0 = 40,
CLM_RATE_2X2_STBC_MCS1 = 41,
CLM_RATE_2X2_STBC_MCS2 = 42,
CLM_RATE_2X2_STBC_MCS3 = 43,
CLM_RATE_2X2_STBC_MCS4 = 44,
CLM_RATE_2X2_STBC_MCS5 = 45,
CLM_RATE_2X2_STBC_MCS6 = 46,
CLM_RATE_2X2_STBC_MCS7 = 47,
CLM_RATE_2X2_SDM_MCS8 = 48,
CLM_RATE_2X2_SDM_MCS9 = 49,
CLM_RATE_2X2_SDM_MCS10 = 50,
CLM_RATE_2X2_SDM_MCS11 = 51,
CLM_RATE_2X2_SDM_MCS12 = 52,
CLM_RATE_2X2_SDM_MCS13 = 53,
CLM_RATE_2X2_SDM_MCS14 = 54,
CLM_RATE_2X2_SDM_MCS15 = 55,
/************
* 3 chains *
************
*/
/* 1 Stream expanded + 2 */
CLM_RATE_1X3_DSSS_1 = 56,
CLM_RATE_1X3_DSSS_2 = 57,
CLM_RATE_1X3_DSSS_5_5 = 58,
CLM_RATE_1X3_DSSS_11 = 59,
CLM_RATE_1X3_CDD_OFDM_6 = 60,
CLM_RATE_1X3_CDD_OFDM_9 = 61,
CLM_RATE_1X3_CDD_OFDM_12 = 62,
CLM_RATE_1X3_CDD_OFDM_18 = 63,
CLM_RATE_1X3_CDD_OFDM_24 = 64,
CLM_RATE_1X3_CDD_OFDM_36 = 65,
CLM_RATE_1X3_CDD_OFDM_48 = 66,
CLM_RATE_1X3_CDD_OFDM_54 = 67,
CLM_RATE_1X3_CDD_MCS0 = 68,
CLM_RATE_1X3_CDD_MCS1 = 69,
CLM_RATE_1X3_CDD_MCS2 = 70,
CLM_RATE_1X3_CDD_MCS3 = 71,
CLM_RATE_1X3_CDD_MCS4 = 72,
CLM_RATE_1X3_CDD_MCS5 = 73,
CLM_RATE_1X3_CDD_MCS6 = 74,
CLM_RATE_1X3_CDD_MCS7 = 75,
/* 2 Streams expanded + 1 */
CLM_RATE_2X3_STBC_MCS0 = 76,
CLM_RATE_2X3_STBC_MCS1 = 77,
CLM_RATE_2X3_STBC_MCS2 = 78,
CLM_RATE_2X3_STBC_MCS3 = 79,
CLM_RATE_2X3_STBC_MCS4 = 80,
CLM_RATE_2X3_STBC_MCS5 = 81,
CLM_RATE_2X3_STBC_MCS6 = 82,
CLM_RATE_2X3_STBC_MCS7 = 83,
CLM_RATE_2X3_SDM_MCS8 = 84,
CLM_RATE_2X3_SDM_MCS9 = 85,
CLM_RATE_2X3_SDM_MCS10 = 86,
CLM_RATE_2X3_SDM_MCS11 = 87,
CLM_RATE_2X3_SDM_MCS12 = 88,
CLM_RATE_2X3_SDM_MCS13 = 89,
CLM_RATE_2X3_SDM_MCS14 = 90,
CLM_RATE_2X3_SDM_MCS15 = 91,
/* 3 Streams */
CLM_RATE_3X3_SDM_MCS16 = 92,
CLM_RATE_3X3_SDM_MCS17 = 93,
CLM_RATE_3X3_SDM_MCS18 = 94,
CLM_RATE_3X3_SDM_MCS19 = 95,
CLM_RATE_3X3_SDM_MCS20 = 96,
CLM_RATE_3X3_SDM_MCS21 = 97,
CLM_RATE_3X3_SDM_MCS22 = 98,
CLM_RATE_3X3_SDM_MCS23 = 99
/* Number of rate codes */
} clm_rates_t;
#define CLM_NUMRATES 100
#ifdef __cplusplus
}
#endif /* __cplusplus */
#endif /* _WLC_CLM_RATES_H_ */

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