PM / devfreq: rockchip_dmc: add support for rk3128 dmc
This adds the necessary data for handling dmcfreq on the rk3128. Change-Id: I6aeae7103c1eaed0b4515d8d11863c4b190b6918 Signed-off-by: Liang Chen <cl@rock-chips.com>
This commit is contained in:
Liang Chen
Huang, Tao
parent
0d5567697f
commit
400617b950
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@ -2,6 +2,7 @@
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Required properties:
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- compatible: Should be one of the following.
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- "rockchip,rk3128-dmc" - for RK3128 SoCs.
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- "rockchip,rk3288-dmc" - for RK3288 SoCs.
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- "rockchip,rk3368-dmc" - for RK3368 SoCs.
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- "rockchip,rk3399-dmc" - for RK3399 SoCs.
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@ -217,10 +217,10 @@ static struct rockchip_clk_branch common_clk_branches[] __initdata = {
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RK2928_CLKGATE_CON(0), 2, GFLAGS),
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GATE(0, "gpll_div2_ddr", "gpll_div2", CLK_IGNORE_UNUSED,
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RK2928_CLKGATE_CON(0), 2, GFLAGS),
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COMPOSITE_NOGATE(0, "ddrphy2x", mux_ddrphy_p, CLK_IGNORE_UNUSED,
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RK2928_CLKSEL_CON(26), 8, 2, MFLAGS, 0, 2, DFLAGS | CLK_DIVIDER_POWER_OF_TWO),
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FACTOR(SCLK_DDRC, "clk_ddrc", "ddrphy2x", 0, 1, 2),
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FACTOR(0, "clk_ddrphy", "ddrphy2x", 0, 1, 2),
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COMPOSITE_DDRCLK(SCLK_DDRC, "clk_ddrc", mux_ddrphy_p, 0,
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RK2928_CLKSEL_CON(26), 8, 2, 0, 2,
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ROCKCHIP_DDRCLK_SIP_V2),
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FACTOR(0, "clk_ddrphy", "clk_ddrc", 0, 1, 2),
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/* PD_CORE */
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GATE(0, "apll_core", "apll", CLK_IGNORE_UNUSED,
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@ -89,6 +89,53 @@ struct share_params {
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static struct share_params *ddr_psci_param;
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static const char *rk3128_dts_timing[] = {
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"ddr3_speed_bin",
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"pd_idle",
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"sr_idle",
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"auto_pd_dis_freq",
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"auto_sr_dis_freq",
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"ddr3_dll_dis_freq",
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"lpddr2_dll_dis_freq",
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"phy_dll_dis_freq",
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"ddr3_odt_dis_freq",
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"phy_ddr3_odt_disb_freq",
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"ddr3_drv",
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"ddr3_odt",
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"phy_ddr3_clk_drv",
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"phy_ddr3_cmd_drv",
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"phy_ddr3_dqs_drv",
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"phy_ddr3_odt",
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"lpddr2_drv",
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"phy_lpddr2_clk_drv",
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"phy_lpddr2_cmd_drv",
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"phy_lpddr2_dqs_drv"
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};
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struct rk3128_ddr_dts_config_timing {
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u32 ddr3_speed_bin;
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u32 pd_idle;
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u32 sr_idle;
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u32 auto_pd_dis_freq;
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u32 auto_sr_dis_freq;
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u32 ddr3_dll_dis_freq;
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u32 lpddr2_dll_dis_freq;
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u32 phy_dll_dis_freq;
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u32 ddr3_odt_dis_freq;
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u32 phy_ddr3_odt_disb_freq;
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u32 ddr3_drv;
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u32 ddr3_odt;
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u32 phy_ddr3_clk_drv;
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u32 phy_ddr3_cmd_drv;
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u32 phy_ddr3_dqs_drv;
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u32 phy_ddr3_odt;
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u32 lpddr2_drv;
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u32 phy_lpddr2_clk_drv;
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u32 phy_lpddr2_cmd_drv;
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u32 phy_lpddr2_dqs_drv;
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u32 available;
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};
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char *rk3288_dts_timing[] = {
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"ddr3_speed_bin",
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"pd_idle",
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@ -493,6 +540,46 @@ static int rockchip_dmcfreq_init_freq_table(struct device *dev,
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return 0;
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}
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static void of_get_rk3128_timings(struct device *dev,
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struct device_node *np, uint32_t *timing)
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{
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struct device_node *np_tim;
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u32 *p;
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struct rk3128_ddr_dts_config_timing *dts_timing;
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struct share_params *init_timing;
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int ret = 0;
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u32 i;
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init_timing = (struct share_params *)timing;
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if (of_property_read_u32(np, "vop-dclk-mode",
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&init_timing->vop_dclk_mode))
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init_timing->vop_dclk_mode = 0;
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p = timing + DTS_PAR_OFFSET / 4;
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np_tim = of_parse_phandle(np, "rockchip,ddr_timing", 0);
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if (!np_tim) {
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ret = -EINVAL;
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goto end;
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}
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for (i = 0; i < ARRAY_SIZE(rk3128_dts_timing); i++) {
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ret |= of_property_read_u32(np_tim, rk3128_dts_timing[i],
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p + i);
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}
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end:
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dts_timing =
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(struct rk3128_ddr_dts_config_timing *)(timing +
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DTS_PAR_OFFSET / 4);
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if (!ret) {
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dts_timing->available = 1;
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} else {
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dts_timing->available = 0;
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dev_err(dev, "of_get_ddr_timings: fail\n");
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}
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of_node_put(np_tim);
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}
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static void of_get_rk3288_timings(struct device *dev,
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struct device_node *np, uint32_t *timing)
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{
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@ -652,6 +739,44 @@ static int rockchip_ddr_set_auto_self_refresh(uint32_t en)
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return res.a0;
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}
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static int rk3128_dmc_init(struct platform_device *pdev,
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struct rockchip_dmcfreq *dmcfreq)
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{
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struct arm_smccc_res res;
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struct drm_device *drm = drm_device_get_by_name("rockchip");
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if (!drm) {
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dev_err(&pdev->dev, "Get drm_device fail\n");
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return -EPROBE_DEFER;
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}
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res = sip_smc_request_share_mem(DIV_ROUND_UP(sizeof(
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struct rk3128_ddr_dts_config_timing),
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4096) + 1, SHARE_PAGE_TYPE_DDR);
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if (res.a0) {
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dev_err(&pdev->dev, "no ATF memory for init\n");
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return -ENOMEM;
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}
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ddr_psci_param = (struct share_params *)res.a1;
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of_get_rk3128_timings(&pdev->dev, pdev->dev.of_node,
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(uint32_t *)ddr_psci_param);
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ddr_psci_param->hz = 0;
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ddr_psci_param->lcdc_type = rk_drm_get_lcdc_type();
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res = sip_smc_dram(SHARE_PAGE_TYPE_DDR, 0,
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ROCKCHIP_SIP_CONFIG_DRAM_INIT);
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if (res.a0) {
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dev_err(&pdev->dev, "rockchip_sip_config_dram_init error:%lx\n",
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res.a0);
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return -ENOMEM;
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}
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dmcfreq->set_auto_self_refresh = rockchip_ddr_set_auto_self_refresh;
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return 0;
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}
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static int rk3288_dmc_init(struct platform_device *pdev,
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struct rockchip_dmcfreq *dmcfreq)
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{
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@ -951,6 +1076,7 @@ static int rk3399_dmc_init(struct platform_device *pdev)
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}
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static const struct of_device_id rockchip_dmcfreq_of_match[] = {
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{ .compatible = "rockchip,rk3128-dmc", .data = rk3128_dmc_init },
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{ .compatible = "rockchip,rk3288-dmc", .data = rk3288_dmc_init },
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{ .compatible = "rockchip,rk3368-dmc", .data = rk3368_dmc_init },
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{ .compatible = "rockchip,rk3399-dmc", .data = rk3399_dmc_init },
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@ -0,0 +1,95 @@
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/*
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* Copyright (c) 2017 Fuzhou Rockchip Electronics Co., Ltd
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*
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* This file is dual-licensed: you can use it either under the terms
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* of the GPL or the X11 license, at your option. Note that this dual
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* licensing only applies to this file, and not this project as a
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* whole.
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*
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* a) This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of the
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* License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* Or, alternatively,
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*
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* b) Permission is hereby granted, free of charge, to any person
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* obtaining a copy of this software and associated documentation
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* files (the "Software"), to deal in the Software without
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* restriction, including without limitation the rights to use,
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* copy, modify, merge, publish, distribute, sublicense, and/or
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* sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following
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* conditions:
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*
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* The above copyright notice and this permission notice shall be
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* included in all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
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* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
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* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
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* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*/
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#ifndef _DT_BINDINGS_DRAM_ROCKCHIP_RK3128_H
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#define _DT_BINDINGS_DRAM_ROCKCHIP_RK3128_H
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#define BIT(nr) (1UL << (nr))
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#define DDR3_DS_34ohm BIT(1)
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#define DDR3_DS_40ohm (0x0)
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#define LP2_DS_34ohm (0x1)
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#define LP2_DS_40ohm (0x2)
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#define LP2_DS_48ohm (0x3)
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#define LP2_DS_60ohm (0x4)
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#define LP2_DS_68_6ohm (0x5) /* optional */
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#define LP2_DS_80ohm (0x6)
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#define LP2_DS_120ohm (0x7) /* optional */
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#define DDR3_ODT_DIS (0)
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#define DDR3_ODT_40ohm (BIT(2) | BIT(6))
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#define DDR3_ODT_60ohm BIT(2)
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#define DDR3_ODT_120ohm BIT(6)
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#define PHY_RON_DISABLE (0)
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#define PHY_RON_309ohm (1)
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#define PHY_RON_155ohm (2)
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#define PHY_RON_103ohm (3)
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#define PHY_RON_77ohm (4)
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#define PHY_RON_63ohm (5)
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#define PHY_RON_52ohm (6)
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#define PHY_RON_45ohm (7)
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#define PHY_RON_62ohm (9)
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#define PHY_RON_44ohm (11)
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#define PHY_RON_39ohm (12)
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#define PHY_RON_34ohm (13)
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#define PHY_RON_31ohm (14)
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#define PHY_RON_28ohm (15)
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#define PHY_RTT_DISABLE (0)
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#define PHY_RTT_816ohm (1)
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#define PHY_RTT_431ohm (2)
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#define PHY_RTT_287ohm (3)
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#define PHY_RTT_216ohm (4)
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#define PHY_RTT_172ohm (5)
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#define PHY_RTT_145ohm (6)
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#define PHY_RTT_124ohm (7)
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#define PHY_RTT_215ohm (8)
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#define PHY_RTT_144ohm (10)
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#define PHY_RTT_123ohm (11)
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#define PHY_RTT_108ohm (12)
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#define PHY_RTT_96ohm (13)
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#define PHY_RTT_86ohm (14)
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#define PHY_RTT_78ohm (15)
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#endif /* _DT_BINDINGS_DRAM_ROCKCHIP_RK3128_H */
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