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ASoC: rockchip: rk817-codec: Be stable PLL status during switch sample rate and mclk 

Change-Id: I5f01035efb68fac9800fb62388221210bdb12d93
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
This commit is contained in:
Xing Zheng 2023-05-22 16:26:29 +08:00 committed by Tao Huang
parent 666bac0de5
commit 5110d5de6d
1 changed files with 6 additions and 0 deletions
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6
sound/soc/codecs/rk817_codec.c
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@ -954,6 +954,12 @@ static int rk817_hw_params(struct snd_pcm_substream *substream,
DACSRT_MASK, dtop_digen_sr_lmt0);
snd_soc_component_update_bits(component, RK817_CODEC_DTOP_DIGEN_CLKE,
dtop_digen_clke, dtop_digen_clke);
snd_soc_component_update_bits(component, RK817_CODEC_APLL_CFG5,
PLL_PW_DOWN, PLL_PW_DOWN);
usleep_range(50, 60);
snd_soc_component_update_bits(component, RK817_CODEC_APLL_CFG5,
PLL_PW_DOWN, PLL_PW_UP);
usleep_range(500, 600);
}
switch (params_format(params)) {