From 5110d5de6d188e4517a791878b73de33f344ce83 Mon Sep 17 00:00:00 2001 From: Xing Zheng Date: Mon, 22 May 2023 16:26:29 +0800 Subject: [PATCH] ASoC: rockchip: rk817-codec: Be stable PLL status during switch sample rate and mclk Change-Id: I5f01035efb68fac9800fb62388221210bdb12d93 Signed-off-by: Xing Zheng --- sound/soc/codecs/rk817_codec.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/sound/soc/codecs/rk817_codec.c b/sound/soc/codecs/rk817_codec.c index dcc85f4e4280..e8c4d602322a 100644 --- a/sound/soc/codecs/rk817_codec.c +++ b/sound/soc/codecs/rk817_codec.c @@ -954,6 +954,12 @@ static int rk817_hw_params(struct snd_pcm_substream *substream, DACSRT_MASK, dtop_digen_sr_lmt0); snd_soc_component_update_bits(component, RK817_CODEC_DTOP_DIGEN_CLKE, dtop_digen_clke, dtop_digen_clke); + snd_soc_component_update_bits(component, RK817_CODEC_APLL_CFG5, + PLL_PW_DOWN, PLL_PW_DOWN); + usleep_range(50, 60); + snd_soc_component_update_bits(component, RK817_CODEC_APLL_CFG5, + PLL_PW_DOWN, PLL_PW_UP); + usleep_range(500, 600); } switch (params_format(params)) {