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arm64: dts: rockchip: combine dcphy tx/rx for rk3588 

Signed-off-by: Zefa Chen <zefa.chen@rock-chips.com>
Change-Id: I3c4f3f539cc906258ad36e7627575da6a78c6e23
This commit is contained in:
Zefa Chen 2021-12-11 17:11:06 +08:00 committed by Tao Huang
parent 4764cd7c19
commit 58b77814a2
8 changed files with 49 additions and 70 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

16
arch/arm64/boot/dts/rockchip/rk3588-evb1-cam-6x.dtsi
View File

@ -4,14 +4,6 @@
*
*/
&csi2_dcphy0_hw {
status = "okay";
};
&csi2_dcphy1_hw {
status = "okay";
};
&csi2_dcphy0 {
status = "okay";
@ -350,6 +342,14 @@
};
};
&mipi_dcphy0 {
status = "okay";
};
&mipi_dcphy1 {
status = "okay";
};
&mipi0_csi2 {
status = "okay";

8
arch/arm64/boot/dts/rockchip/rk3588-evb1-imx415.dtsi
View File

@ -45,10 +45,6 @@
};
};
&csi2_dcphy0_hw {
status = "okay";
};
&i2c5 {
status = "okay";
@ -76,6 +72,10 @@
};
};
&mipi_dcphy0 {
status = "okay";
};
&mipi0_csi2 {
status = "okay";

4
arch/arm64/boot/dts/rockchip/rk3588-evb1-lp4-v10-ipc-6x-linux.dts
View File

@ -123,10 +123,6 @@
status = "disabled";
};
&mipi_dcphy0 {
status = "disabled";
};
&pcie2x1l0 {
status = "disabled";
};

9
arch/arm64/boot/dts/rockchip/rk3588-toybrick-imx258.dtsi
View File

@ -150,10 +150,6 @@
};
};
};
// use dcphy0 isp1
&csi2_dcphy0_hw {
status = "okay";
};
&csi2_dcphy0 {
status = "okay";
@ -227,6 +223,11 @@
};
};
// use dcphy0 isp1
&mipi_dcphy0 {
status = "okay";
};
&mipi0_csi2 {
status = "okay";
ports {

16
arch/arm64/boot/dts/rockchip/rk3588s-evb1-lp4x-v10-camera.dtsi
View File

@ -40,10 +40,6 @@
};
};
&csi2_dcphy0_hw {
status = "okay";
};
&csi2_dcphy1 {
status = "okay";
@ -74,10 +70,6 @@
};
};
&csi2_dcphy1_hw {
status = "okay";
};
&i2c6 {
status = "okay";
pinctrl-names = "default";
@ -203,6 +195,14 @@
};
};
&mipi_dcphy0 {
status = "okay";
};
&mipi_dcphy1 {
status = "okay";
};
&mipi0_csi2 {
status = "okay";

8
arch/arm64/boot/dts/rockchip/rk3588s-tablet-rk806-single-camera.dtsi
View File

@ -46,10 +46,6 @@
};
};
&csi2_dcphy0_hw {
status = "okay";
};
&i2c6 {
status = "okay";
pinctrl-names = "default";
@ -88,6 +84,10 @@
};
};
&mipi_dcphy0 {
status = "okay";
};
&mipi0_csi2 {
status = "okay";

16
arch/arm64/boot/dts/rockchip/rk3588s-tablet.dtsi
View File

@ -547,14 +547,6 @@
};
};
&csi2_dcphy0_hw {
status = "okay";
};
&csi2_dcphy1_hw {
status = "okay";
};
&csi2_dcphy0 {
status = "okay";
@ -615,6 +607,14 @@
};
};
&mipi_dcphy0 {
status = "okay";
};
&mipi_dcphy1 {
status = "okay";
};
&mipi0_csi2 {
status = "okay";

42
arch/arm64/boot/dts/rockchip/rk3588s.dtsi
View File

@ -1039,13 +1039,15 @@
csi2_dcphy0: csi2-dcphy0 {
compatible = "rockchip,rk3588-csi2-dcphy";
rockchip,hw = <&csi2_dcphy0_hw>;
phys = <&mipi_dcphy0>;
phy-names = "dcphy";
status = "disabled";
};
csi2_dcphy1: csi2-dcphy1 {
compatible = "rockchip,rk3588-csi2-dcphy";
rockchip,hw = <&csi2_dcphy1_hw>;
phys = <&mipi_dcphy1>;
phy-names = "dcphy";
status = "disabled";
};
@ -5411,56 +5413,36 @@
mipi_dcphy0: phy@feda0000 {
compatible = "rockchip,rk3588-mipi-dcphy";
reg = <0x0 0xfeda0000 0x0 0xb00>;
reg = <0x0 0xfeda0000 0x0 0x10000>;
rockchip,grf = <&mipidcphy0_grf>;
clocks = <&cru PCLK_MIPI_DCPHY0>,
<&cru CLK_USBDPPHY_MIPIDCPPHY_REF>;
clock-names = "pclk", "ref";
resets = <&cru SRST_M_MIPI_DCPHY0>,
<&cru SRST_P_MIPI_DCPHY0>,
<&cru SRST_P_MIPI_DCPHY0_GRF>;
reset-names = "phy", "apb", "grf";
<&cru SRST_P_MIPI_DCPHY0_GRF>,
<&cru SRST_S_MIPI_DCPHY0>;
reset-names = "m_phy", "apb", "grf", "s_phy";
#phy-cells = <0>;
status = "disabled";
};
csi2_dcphy0_hw: csi2-dcphy0-hw@feda0b00 {
compatible = "rockchip,rk3588-csi2-dcphy-hw";
reg = <0x0 0xfeda0b00 0x0 0xf500>;
clocks = <&cru PCLK_MIPI_DCPHY0>;
clock-names = "pclk";
resets = <&cru SRST_S_MIPI_DCPHY0>;
reset-names = "phy";
rockchip,grf = <&mipidcphy0_grf>;
status = "disabled";
};
mipi_dcphy1: phy@fedb0000 {
compatible = "rockchip,rk3588-mipi-dcphy";
reg = <0x0 0xfedb0000 0x0 0xb00>;
reg = <0x0 0xfedb0000 0x0 0x10000>;
rockchip,grf = <&mipidcphy1_grf>;
clocks = <&cru PCLK_MIPI_DCPHY1>,
<&cru CLK_USBDPPHY_MIPIDCPPHY_REF>;
clock-names = "pclk", "ref";
resets = <&cru SRST_M_MIPI_DCPHY1>,
<&cru SRST_P_MIPI_DCPHY1>,
<&cru SRST_P_MIPI_DCPHY1_GRF>;
reset-names = "phy", "apb", "grf";
<&cru SRST_P_MIPI_DCPHY1_GRF>,
<&cru SRST_S_MIPI_DCPHY1>;
reset-names = "m_phy", "apb", "grf", "s_phy";
#phy-cells = <0>;
status = "disabled";
};
csi2_dcphy1_hw: csi2-dcphy1-hw@fedb0b00 {
compatible = "rockchip,rk3588-csi2-dcphy-hw";
reg = <0x0 0xfedb0b00 0x0 0xf500>;
clocks = <&cru PCLK_MIPI_DCPHY1>;
clock-names = "pclk";
resets = <&cru SRST_S_MIPI_DCPHY1>;
reset-names = "phy";
rockchip,grf = <&mipidcphy1_grf>;
status = "disabled";
};
csi2_dphy0_hw: csi2-dphy0-hw@fedc0000 {
compatible = "rockchip,rk3588-csi2-dphy-hw";
reg = <0x0 0xfedc0000 0x0 0x8000>;