phy: rockchip: inno-usb2: add usb2 phy support for rk3562
RK3652 has one USB2.0 PHY with two ports, the OTG port support OTG and BC1.2, the SoC provide USB GRF and APB to access the registers. This adds vbus detection function control and make the below tuning to enhance the usb2-phy SQ for RK3562 SoC. - enable pre-emphasis during non-chirp phase - set HS eye height to 425mv - turn off differential receiver by default to save power Signed-off-by: Frank Wang <frank.wang@rock-chips.com> Signed-off-by: William Wu <william.wu@rock-chips.com> Change-Id: If93c3a072be4c532aa823cf3cd9f05fe9414f727
This commit is contained in:
Frank Wang
Tao Huang
parent
36c9d7fd8f
commit
63f30f7541
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@ -2741,6 +2741,34 @@ static int rk3528_usb2phy_tuning(struct rockchip_usb2phy *rphy)
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return ret;
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}
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static int rk3562_usb2phy_tuning(struct rockchip_usb2phy *rphy)
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{
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int ret = 0;
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/* Turn off differential receiver by default to save power */
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phy_clear_bits(rphy->phy_base + 0x0030, BIT(2));
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phy_clear_bits(rphy->phy_base + 0x0430, BIT(2));
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/* Enable pre-emphasis during non-chirp phase */
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phy_update_bits(rphy->phy_base, GENMASK(2, 0), 0x04);
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phy_update_bits(rphy->phy_base + 0x0400, GENMASK(2, 0), 0x04);
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/* Set HS eye height to 425mv(default is 400mv) */
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phy_update_bits(rphy->phy_base + 0x0030, GENMASK(6, 4), (0x05 << 4));
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phy_update_bits(rphy->phy_base + 0x0430, GENMASK(6, 4), (0x05 << 4));
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/* Set the bvalid filter time to 10ms based on the u2phy grf pclk 100MHz */
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ret |= regmap_write(rphy->grf, 0x0138, FILTER_COUNTER);
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/* Set the id filter time to 10ms based on the u2phy grf pclk 100MHz */
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ret |= regmap_write(rphy->grf, 0x013c, FILTER_COUNTER);
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/* Enable host port wakeup irq */
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ret |= regmap_write(rphy->grf, 0x010c, 0x80008000);
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return ret;
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}
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static int rk3568_usb2phy_tuning(struct rockchip_usb2phy *rphy)
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{
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int ret = 0;
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@ -3626,6 +3654,65 @@ static const struct rockchip_usb2phy_cfg rk3528_phy_cfgs[] = {
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}
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};
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static const struct rockchip_usb2phy_cfg rk3562_phy_cfgs[] = {
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{
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.reg = 0xff740000,
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.num_ports = 2,
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.phy_tuning = rk3562_usb2phy_tuning,
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.vbus_detect = rockchip_usb2phy_vbus_det_control,
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.clkout_ctl = { 0x0108, 4, 4, 1, 0 },
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.ls_filter_con = { 0x0130, 19, 0, 0x30100, 0x00020 },
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.port_cfgs = {
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[USB2PHY_PORT_OTG] = {
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.phy_sus = { 0x0100, 8, 0, 0, 0x1d1 },
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.bvalid_det_en = { 0x0110, 2, 2, 0, 1 },
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.bvalid_det_st = { 0x0114, 2, 2, 0, 1 },
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.bvalid_det_clr = { 0x0118, 2, 2, 0, 1 },
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.bvalid_grf_sel = { 0x0108, 15, 14, 0, 3 },
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.bypass_dm_en = { 0x0108, 2, 2, 0, 1},
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.bypass_sel = { 0x0108, 3, 3, 0, 1},
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.iddig_output = { 0x0100, 10, 10, 0, 1 },
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.iddig_en = { 0x0100, 9, 9, 0, 1 },
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.idfall_det_en = { 0x0110, 5, 5, 0, 1 },
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.idfall_det_st = { 0x0114, 5, 5, 0, 1 },
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.idfall_det_clr = { 0x0118, 5, 5, 0, 1 },
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.idrise_det_en = { 0x0110, 4, 4, 0, 1 },
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.idrise_det_st = { 0x0114, 4, 4, 0, 1 },
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.idrise_det_clr = { 0x0118, 4, 4, 0, 1 },
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.ls_det_en = { 0x0110, 0, 0, 0, 1 },
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.ls_det_st = { 0x0114, 0, 0, 0, 1 },
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.ls_det_clr = { 0x0118, 0, 0, 0, 1 },
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.utmi_avalid = { 0x0120, 10, 10, 0, 1 },
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.utmi_bvalid = { 0x0120, 9, 9, 0, 1 },
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.utmi_iddig = { 0x0120, 6, 6, 0, 1 },
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.utmi_ls = { 0x0120, 5, 4, 0, 1 },
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.vbus_det_en = { 0x003c, 7, 7, 0, 1 },
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},
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[USB2PHY_PORT_HOST] = {
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.phy_sus = { 0x0104, 8, 0, 0x1d2, 0x1d1 },
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.ls_det_en = { 0x0110, 1, 1, 0, 1 },
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.ls_det_st = { 0x0114, 1, 1, 0, 1 },
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.ls_det_clr = { 0x0118, 1, 1, 0, 1 },
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.utmi_ls = { 0x0120, 17, 16, 0, 1 },
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.utmi_hstdet = { 0x0120, 19, 19, 0, 1 }
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}
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},
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.chg_det = {
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.chg_mode = { 0x0100, 8, 0, 0, 0x1d7 },
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.cp_det = { 0x0120, 24, 24, 0, 1 },
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.dcp_det = { 0x0120, 23, 23, 0, 1 },
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.dp_det = { 0x0120, 25, 25, 0, 1 },
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.idm_sink_en = { 0x0108, 8, 8, 0, 1 },
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.idp_sink_en = { 0x0108, 7, 7, 0, 1 },
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.idp_src_en = { 0x0108, 9, 9, 0, 1 },
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.rdm_pdwn_en = { 0x0108, 10, 10, 0, 1 },
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.vdm_src_en = { 0x0108, 12, 12, 0, 1 },
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.vdp_src_en = { 0x0108, 11, 11, 0, 1 },
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},
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},
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{ /* sentinel */ }
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};
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static const struct rockchip_usb2phy_cfg rk3568_phy_cfgs[] = {
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{
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.reg = 0xfe8a0000,
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@ -3986,6 +4073,9 @@ static const struct of_device_id rockchip_usb2phy_dt_match[] = {
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#ifdef CONFIG_CPU_RK3528
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{ .compatible = "rockchip,rk3528-usb2phy", .data = &rk3528_phy_cfgs },
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#endif
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#ifdef CONFIG_CPU_RK3562
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{ .compatible = "rockchip,rk3562-usb2phy", .data = &rk3562_phy_cfgs },
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#endif
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#ifdef CONFIG_CPU_RK3568
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{ .compatible = "rockchip,rk3568-usb2phy", .data = &rk3568_phy_cfgs },
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#endif
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