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sound: codecs: aw87xxx: Update to v2.14.0

This commit is contained in:
leeboby 2024-07-23 16:04:21 +08:00
parent 982b78438c
commit 84cd3bced9
24 changed files with 11309 additions and 993 deletions
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1126
sound/soc/codecs/aw87xxx/aw87xxx.c
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38
sound/soc/codecs/aw87xxx/aw87xxx.h
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@ -1,4 +1,17 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/* SPDX-License-Identifier: GPL-2.0
*
* aw87xxx.h aw87xxx pa module
*
* Copyright (c) 2021 AWINIC Technology CO., LTD
*
* Author: Barry <zhaozhongbo@awinic.com>
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*
*/
#ifndef __AW87XXX_H__
#define __AW87XXX_H__
@ -17,7 +30,8 @@
#define AW87XXX_NO_OFF_BIN (0)
#define AW87XXX_OFF_BIN_OK (1)
#define AW87XXX_KCONTROL_NUM (2)
#define AW87XXX_PRIVATE_KCONTROL_NUM (3)
#define AW87XXX_PUBLIC_KCONTROL_NUM (3)
#define AW_I2C_RETRIES (5)
#define AW_I2C_RETRY_DELAY (2)
@ -39,10 +53,22 @@
* aw87xxx codec control compatible with kernel 4.19
*
***********************************************************/
#if LINUX_VERSION_CODE >= KERNEL_VERSION(4, 19, 1)
#if KERNEL_VERSION(4, 19, 1) <= LINUX_VERSION_CODE
#define AW_KERNEL_VER_OVER_4_19_1
#endif
#if KERNEL_VERSION(5, 4, 0) <= LINUX_VERSION_CODE
#define AW_KERNEL_VER_OVER_5_4_0
#endif
#if KERNEL_VERSION(5, 10, 0) <= LINUX_VERSION_CODE
#define AW_KERNEL_VER_OVER_5_10_0
#endif
#if KERNEL_VERSION(6, 1, 0) <= LINUX_VERSION_CODE
#define AW_KERNEL_VER_OVER_6_1_0
#endif
#ifdef AW_KERNEL_VER_OVER_4_19_1
typedef struct snd_soc_component aw_snd_soc_codec_t;
#else
@ -101,6 +127,7 @@ struct aw87xxx {
char prof_off_name[AW_PROFILE_STR_MAX];
uint32_t off_bin_status;
struct device *dev;
bool is_suspend;
struct mutex reg_lock;
struct aw_device aw_dev;
@ -114,9 +141,12 @@ struct aw87xxx {
struct list_head list;
struct aw_monitor monitor;
#ifdef AW_ALGO_AUTH_DSP
struct delayed_work auth_work;
#endif
};
int aw87xxx_update_profile(struct aw87xxx *aw87xxx, char *profile);
int aw87xxx_esd_update_profile(struct aw87xxx *aw87xxx, char *profile);
int aw87xxx_update_profile_esd(struct aw87xxx *aw87xxx, char *profile);
#endif

14
sound/soc/codecs/aw87xxx/aw87xxx_pid_18_reg.h
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@ -1,4 +1,15 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/* SPDX-License-Identifier: GPL-2.0
* aw87xxx_pid_18_reg.h
*
* Copyright (c) 2021 AWINIC Technology CO., LTD
*
* Author: Barry <zhaozhongbo@awinic.com>
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*/
#ifndef __AW87XXX_PID_18_REG_H__
#define __AW87XXX_PID_18_REG_H__
@ -2315,3 +2326,4 @@ const unsigned char aw87xxx_pid_18_reg_access[AW87XXX_PID_18_REG_MAX] = {
/* detail information of registers end */
#endif /* #ifndef __AW87XXX_PID_18_REG_H__ */

13
sound/soc/codecs/aw87xxx/aw87xxx_pid_39_reg.h
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@ -1,4 +1,15 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/* SPDX-License-Identifier: GPL-2.0
* aw87xxx_pid_39_reg.h
*
* Copyright (c) 2021 AWINIC Technology CO., LTD
*
* Author: Barry <zhaozhongbo@awinic.com>
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*/
#ifndef __AW87XXX_PID_39_REG_H__
#define __AW87XXX_PID_39_REG_H__

20
sound/soc/codecs/aw87xxx/aw87xxx_pid_59_3x9_reg.h
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@ -1,12 +1,16 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* @Descripttion: Header file of AW87XXX_PID_59_3X9_REG
* @version: V1.33
* @Author: zhaozhongbo
* @Date: 2021-03-10
* @LastEditors: Please set LastEditors
* @LastEditTime: 2021-03-10
/* SPDX-License-Identifier: GPL-2.0
* aw87xxx_pid_59_3x9_reg.h
*
* Copyright (c) 2021 AWINIC Technology CO., LTD
*
* Author: Barry <zhaozhongbo@awinic.com>
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*/
#ifndef __AW87XXX_PID_59_3X9_REG_H__
#define __AW87XXX_PID_59_3X9_REG_H__

20
sound/soc/codecs/aw87xxx/aw87xxx_pid_59_5x9_reg.h
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@ -1,12 +1,16 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* @Descripttion: Header file of AW87XXX_PID_59_5X9_REG
* @version: V1.33
* @Author: zhaozhongbo
* @Date: 2021-03-10
* @LastEditors: Please set LastEditors
* @LastEditTime: 2021-03-10
/* SPDX-License-Identifier: GPL-2.0
* aw87xxx_pid_59_5x9_reg.h
*
* Copyright (c) 2021 AWINIC Technology CO., LTD
*
* Author: Barry <zhaozhongbo@awinic.com>
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*/
#ifndef __AW87XXX_PID_59_5X9_REG_H__
#define __AW87XXX_PID_59_5X9_REG_H__

94
sound/soc/codecs/aw87xxx/aw87xxx_pid_5a_reg.h
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@ -1,12 +1,16 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* @Descripttion: Header file of AW87XXX_PID_5A_REG
* @version: V1.4
* @Author: zhaozhongbo
* @Date: 2021-03-10
* @LastEditors: Please set LastEditors
* @LastEditTime: 2021-03-10
/* SPDX-License-Identifier: GPL-2.0
* aw87xxx_pid_5a_reg.h
*
* Copyright (c) 2021 AWINIC Technology CO., LTD
*
* Author: Barry <zhaozhongbo@awinic.com>
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*/
#ifndef __AW87XXX_PID_5A_REG_H__
#define __AW87XXX_PID_5A_REG_H__
@ -486,8 +490,8 @@ const unsigned char aw87xxx_pid_5a_reg_access[AW87XXX_PID_5A_REG_MAX] = {
#define AW87XXX_PID_5A_REG_BURST_HYS_SELA_8P3MV_VALUE \
(AW87XXX_PID_5A_REG_BURST_HYS_SELA_8P3MV << AW87XXX_PID_5A_REG_BURST_HYS_SELA_START_BIT)
/*
#define AW87XXX_PID_5A_REG_BURST_HYS_SELA_8P3MV (3)
#define AW87XXX_PID_5A_REG_BURST_HYS_SELA_8P3MV_VALUE \
*#define AW87XXX_PID_5A_REG_BURST_HYS_SELA_8P3MV (3)
*#define AW87XXX_PID_5A_REG_BURST_HYS_SELA_8P3MV_VALUE \
(AW87XXX_PID_5A_REG_BURST_HYS_SELA_8P3MV << AW87XXX_PID_5A_REG_BURST_HYS_SELA_START_BIT)
*/
#define AW87XXX_PID_5A_REG_BURST_HYS_SELA_DEFAULT_VALUE (0)
@ -592,8 +596,8 @@ const unsigned char aw87xxx_pid_5a_reg_access[AW87XXX_PID_5A_REG_MAX] = {
#define AW87XXX_PID_5A_REG_BURST_HYS_SEL_8P3MV_VALUE \
(AW87XXX_PID_5A_REG_BURST_HYS_SEL_8P3MV << AW87XXX_PID_5A_REG_BURST_HYS_SEL_START_BIT)
/*
#define AW87XXX_PID_5A_REG_BURST_HYS_SEL_8P3MV (3)
#define AW87XXX_PID_5A_REG_BURST_HYS_SEL_8P3MV_VALUE \
*#define AW87XXX_PID_5A_REG_BURST_HYS_SEL_8P3MV (3)
*#define AW87XXX_PID_5A_REG_BURST_HYS_SEL_8P3MV_VALUE \
(AW87XXX_PID_5A_REG_BURST_HYS_SEL_8P3MV << AW87XXX_PID_5A_REG_BURST_HYS_SEL_START_BIT)
*/
#define AW87XXX_PID_5A_REG_BURST_HYS_SEL_DEFAULT_VALUE (0x0)
@ -1290,9 +1294,9 @@ const unsigned char aw87xxx_pid_5a_reg_access[AW87XXX_PID_5A_REG_MAX] = {
#define AW87XXX_PID_5A_REG_AGC1_ATT_TIME_0P005MSDB_VALUE \
(AW87XXX_PID_5A_REG_AGC1_ATT_TIME_0P005MSDB << AW87XXX_PID_5A_REG_AGC1_ATT_TIME_START_BIT)
/*
#define AW87XXX_PID_5A_REG_AGC1_ATT_TIME_0P005MSDB (7)
#define AW87XXX_PID_5A_REG_AGC1_ATT_TIME_0P005MSDB_VALUE \
(AW87XXX_PID_5A_REG_AGC1_ATT_TIME_0P005MSDB << AW87XXX_PID_5A_REG_AGC1_ATT_TIME_START_BIT)
*#define AW87XXX_PID_5A_REG_AGC1_ATT_TIME_0P005MSDB (7)
*#define AW87XXX_PID_5A_REG_AGC1_ATT_TIME_0P005MSDB_VALUE \
* (AW87XXX_PID_5A_REG_AGC1_ATT_TIME_0P005MSDB << AW87XXX_PID_5A_REG_AGC1_ATT_TIME_START_BIT)
*/
#define AW87XXX_PID_5A_REG_AGC1_ATT_TIME_DEFAULT_VALUE (0x1)
#define AW87XXX_PID_5A_REG_AGC1_ATT_TIME_DEFAULT \
@ -1354,9 +1358,9 @@ const unsigned char aw87xxx_pid_5a_reg_access[AW87XXX_PID_5A_REG_MAX] = {
#define AW87XXX_PID_5A_REG_AGC1_ATT_TIMEA_0P005MSDB_VALUE \
(AW87XXX_PID_5A_REG_AGC1_ATT_TIMEA_0P005MSDB << AW87XXX_PID_5A_REG_AGC1_ATT_TIMEA_START_BIT)
/*
#define AW87XXX_PID_5A_REG_AGC1_ATT_TIMEA_0P005MSDB (7)
#define AW87XXX_PID_5A_REG_AGC1_ATT_TIMEA_0P005MSDB_VALUE \
(AW87XXX_PID_5A_REG_AGC1_ATT_TIMEA_0P005MSDB << AW87XXX_PID_5A_REG_AGC1_ATT_TIMEA_START_BIT)
*#define AW87XXX_PID_5A_REG_AGC1_ATT_TIMEA_0P005MSDB (7)
*#define AW87XXX_PID_5A_REG_AGC1_ATT_TIMEA_0P005MSDB_VALUE \
* (AW87XXX_PID_5A_REG_AGC1_ATT_TIMEA_0P005MSDB << AW87XXX_PID_5A_REG_AGC1_ATT_TIMEA_START_BIT)
*/
#define AW87XXX_PID_5A_REG_AGC1_ATT_TIMEA_DEFAULT_VALUE (0)
#define AW87XXX_PID_5A_REG_AGC1_ATT_TIMEA_DEFAULT \
@ -1396,9 +1400,9 @@ const unsigned char aw87xxx_pid_5a_reg_access[AW87XXX_PID_5A_REG_MAX] = {
#define AW87XXX_PID_5A_REG_ADPBOOST_MODE_MD5_VALUE \
(AW87XXX_PID_5A_REG_ADPBOOST_MODE_MD5 << AW87XXX_PID_5A_REG_ADPBOOST_MODE_START_BIT)
/*
#define AW87XXX_PID_5A_REG_ADPBOOST_MODE_MD2 (7)
#define AW87XXX_PID_5A_REG_ADPBOOST_MODE_MD2_VALUE \
(AW87XXX_PID_5A_REG_ADPBOOST_MODE_MD2 << AW87XXX_PID_5A_REG_ADPBOOST_MODE_START_BIT)
*#define AW87XXX_PID_5A_REG_ADPBOOST_MODE_MD2 (7)
*#define AW87XXX_PID_5A_REG_ADPBOOST_MODE_MD2_VALUE \
* (AW87XXX_PID_5A_REG_ADPBOOST_MODE_MD2 << AW87XXX_PID_5A_REG_ADPBOOST_MODE_START_BIT)
*/
#define AW87XXX_PID_5A_REG_ADPBOOST_MODE_DEFAULT_VALUE (0x3)
#define AW87XXX_PID_5A_REG_ADPBOOST_MODE_DEFAULT \
@ -1772,9 +1776,9 @@ const unsigned char aw87xxx_pid_5a_reg_access[AW87XXX_PID_5A_REG_MAX] = {
#define AW87XXX_PID_5A_REG_SET_BOOST_VTH2_2P4W_VALUE \
(AW87XXX_PID_5A_REG_SET_BOOST_VTH2_2P4W << AW87XXX_PID_5A_REG_SET_BOOST_VTH2_START_BIT)
/*
#define AW87XXX_PID_5A_REG_SET_BOOST_VTH2_2P4W (7)
#define AW87XXX_PID_5A_REG_SET_BOOST_VTH2_2P4W_VALUE \
(AW87XXX_PID_5A_REG_SET_BOOST_VTH2_2P4W << AW87XXX_PID_5A_REG_SET_BOOST_VTH2_START_BIT)
*#define AW87XXX_PID_5A_REG_SET_BOOST_VTH2_2P4W (7)
*#define AW87XXX_PID_5A_REG_SET_BOOST_VTH2_2P4W_VALUE \
* (AW87XXX_PID_5A_REG_SET_BOOST_VTH2_2P4W << AW87XXX_PID_5A_REG_SET_BOOST_VTH2_START_BIT)
*/
#define AW87XXX_PID_5A_REG_SET_BOOST_VTH2_DEFAULT_VALUE (0x4)
#define AW87XXX_PID_5A_REG_SET_BOOST_VTH2_DEFAULT \
@ -1810,13 +1814,13 @@ const unsigned char aw87xxx_pid_5a_reg_access[AW87XXX_PID_5A_REG_MAX] = {
#define AW87XXX_PID_5A_REG_SET_BOOST_VTH1_0P6W_VALUE \
(AW87XXX_PID_5A_REG_SET_BOOST_VTH1_0P6W << AW87XXX_PID_5A_REG_SET_BOOST_VTH1_START_BIT)
/*
#define AW87XXX_PID_5A_REG_SET_BOOST_VTH1_0P6W (6)
#define AW87XXX_PID_5A_REG_SET_BOOST_VTH1_0P6W_VALUE \
(AW87XXX_PID_5A_REG_SET_BOOST_VTH1_0P6W << AW87XXX_PID_5A_REG_SET_BOOST_VTH1_START_BIT)
*#define AW87XXX_PID_5A_REG_SET_BOOST_VTH1_0P6W (6)
*#define AW87XXX_PID_5A_REG_SET_BOOST_VTH1_0P6W_VALUE \
* (AW87XXX_PID_5A_REG_SET_BOOST_VTH1_0P6W << AW87XXX_PID_5A_REG_SET_BOOST_VTH1_START_BIT)
#define AW87XXX_PID_5A_REG_SET_BOOST_VTH1_0P6W (7)
#define AW87XXX_PID_5A_REG_SET_BOOST_VTH1_0P6W_VALUE \
(AW87XXX_PID_5A_REG_SET_BOOST_VTH1_0P6W << AW87XXX_PID_5A_REG_SET_BOOST_VTH1_START_BIT)
*#define AW87XXX_PID_5A_REG_SET_BOOST_VTH1_0P6W (7)
*#define AW87XXX_PID_5A_REG_SET_BOOST_VTH1_0P6W_VALUE \
* (AW87XXX_PID_5A_REG_SET_BOOST_VTH1_0P6W << AW87XXX_PID_5A_REG_SET_BOOST_VTH1_START_BIT)
*/
#define AW87XXX_PID_5A_REG_SET_BOOST_VTH1_DEFAULT_VALUE (0x3)
#define AW87XXX_PID_5A_REG_SET_BOOST_VTH1_DEFAULT \
@ -2726,9 +2730,9 @@ const unsigned char aw87xxx_pid_5a_reg_access[AW87XXX_PID_5A_REG_MAX] = {
#define AW87XXX_PID_5A_REG_BST_LOOPR_480K_VALUE \
(AW87XXX_PID_5A_REG_BST_LOOPR_480K << AW87XXX_PID_5A_REG_BST_LOOPR_START_BIT)
/*
#define AW87XXX_PID_5A_REG_BST_LOOPR_320K (3)
#define AW87XXX_PID_5A_REG_BST_LOOPR_320K_VALUE \
(AW87XXX_PID_5A_REG_BST_LOOPR_320K << AW87XXX_PID_5A_REG_BST_LOOPR_START_BIT)
*#define AW87XXX_PID_5A_REG_BST_LOOPR_320K (3)
*#define AW87XXX_PID_5A_REG_BST_LOOPR_320K_VALUE \
* (AW87XXX_PID_5A_REG_BST_LOOPR_320K << AW87XXX_PID_5A_REG_BST_LOOPR_START_BIT)
*/
#define AW87XXX_PID_5A_REG_BST_LOOPR_DEFAULT_VALUE (0x2)
#define AW87XXX_PID_5A_REG_BST_LOOPR_DEFAULT \
@ -2882,9 +2886,9 @@ const unsigned char aw87xxx_pid_5a_reg_access[AW87XXX_PID_5A_REG_MAX] = {
#define AW87XXX_PID_5A_REG_AGC1_VTH_SEL_RAMP_GEN_AND_THGEN_VALUE \
(AW87XXX_PID_5A_REG_AGC1_VTH_SEL_RAMP_GEN_AND_THGEN << AW87XXX_PID_5A_REG_AGC1_VTH_SEL_START_BIT)
/*
#define AW87XXX_PID_5A_REG_AGC1_VTH_SEL_RAMP_GEN_AND_THGEN (3)
#define AW87XXX_PID_5A_REG_AGC1_VTH_SEL_RAMP_GEN_AND_THGEN_VALUE \
(AW87XXX_PID_5A_REG_AGC1_VTH_SEL_RAMP_GEN_AND_THGEN << AW87XXX_PID_5A_REG_AGC1_VTH_SEL_START_BIT)
*#define AW87XXX_PID_5A_REG_AGC1_VTH_SEL_RAMP_GEN_AND_THGEN (3)
*#define AW87XXX_PID_5A_REG_AGC1_VTH_SEL_RAMP_GEN_AND_THGEN_VALUE \
* (AW87XXX_PID_5A_REG_AGC1_VTH_SEL_RAMP_GEN_AND_THGEN << AW87XXX_PID_5A_REG_AGC1_VTH_SEL_START_BIT)
*/
#define AW87XXX_PID_5A_REG_AGC1_VTH_SEL_DEFAULT_VALUE (0x2)
#define AW87XXX_PID_5A_REG_AGC1_VTH_SEL_DEFAULT \
@ -3815,17 +3819,17 @@ const unsigned char aw87xxx_pid_5a_reg_access[AW87XXX_PID_5A_REG_MAX] = {
#define AW87XXX_PID_5A_REG_BST_SLOPE_LIMIT_1P25SLOPE_VALUE \
(AW87XXX_PID_5A_REG_BST_SLOPE_LIMIT_1P25SLOPE << AW87XXX_PID_5A_REG_BST_SLOPE_LIMIT_START_BIT)
/*
#define AW87XXX_PID_5A_REG_BST_SLOPE_LIMIT_0P5SLOPE (4)
#define AW87XXX_PID_5A_REG_BST_SLOPE_LIMIT_0P5SLOPE_VALUE \
(AW87XXX_PID_5A_REG_BST_SLOPE_LIMIT_0P5SLOPE << AW87XXX_PID_5A_REG_BST_SLOPE_LIMIT_START_BIT)
*#define AW87XXX_PID_5A_REG_BST_SLOPE_LIMIT_0P5SLOPE (4)
*#define AW87XXX_PID_5A_REG_BST_SLOPE_LIMIT_0P5SLOPE_VALUE \
* (AW87XXX_PID_5A_REG_BST_SLOPE_LIMIT_0P5SLOPE << AW87XXX_PID_5A_REG_BST_SLOPE_LIMIT_START_BIT)
*/
#define AW87XXX_PID_5A_REG_BST_SLOPE_LIMIT_0P75SLOPE (5)
#define AW87XXX_PID_5A_REG_BST_SLOPE_LIMIT_0P75SLOPE_VALUE \
(AW87XXX_PID_5A_REG_BST_SLOPE_LIMIT_0P75SLOPE << AW87XXX_PID_5A_REG_BST_SLOPE_LIMIT_START_BIT)
/*
#define AW87XXX_PID_5A_REG_BST_SLOPE_LIMIT_1P25SLOPE (6)
#define AW87XXX_PID_5A_REG_BST_SLOPE_LIMIT_1P25SLOPE_VALUE \
(AW87XXX_PID_5A_REG_BST_SLOPE_LIMIT_1P25SLOPE << AW87XXX_PID_5A_REG_BST_SLOPE_LIMIT_START_BIT)
*#define AW87XXX_PID_5A_REG_BST_SLOPE_LIMIT_1P25SLOPE (6)
*#define AW87XXX_PID_5A_REG_BST_SLOPE_LIMIT_1P25SLOPE_VALUE \
* (AW87XXX_PID_5A_REG_BST_SLOPE_LIMIT_1P25SLOPE << AW87XXX_PID_5A_REG_BST_SLOPE_LIMIT_START_BIT)
*/
#define AW87XXX_PID_5A_REG_BST_SLOPE_LIMIT_1P75SLOPE (7)
#define AW87XXX_PID_5A_REG_BST_SLOPE_LIMIT_1P75SLOPE_VALUE \
@ -4047,9 +4051,9 @@ const unsigned char aw87xxx_pid_5a_reg_access[AW87XXX_PID_5A_REG_MAX] = {
#define AW87XXX_PID_5A_REG_SS_CONTROL_SW20000_VALUE \
(AW87XXX_PID_5A_REG_SS_CONTROL_SW20000 << AW87XXX_PID_5A_REG_SS_CONTROL_START_BIT)
/*
#define AW87XXX_PID_5A_REG_SS_CONTROL_SW20111 (3)
#define AW87XXX_PID_5A_REG_SS_CONTROL_SW20111_VALUE \
(AW87XXX_PID_5A_REG_SS_CONTROL_SW20111 << AW87XXX_PID_5A_REG_SS_CONTROL_START_BIT)
*#define AW87XXX_PID_5A_REG_SS_CONTROL_SW20111 (3)
*#define AW87XXX_PID_5A_REG_SS_CONTROL_SW20111_VALUE \
* (AW87XXX_PID_5A_REG_SS_CONTROL_SW20111 << AW87XXX_PID_5A_REG_SS_CONTROL_START_BIT)
*/
#define AW87XXX_PID_5A_REG_SS_CONTROL_DEFAULT_VALUE (0x0)
#define AW87XXX_PID_5A_REG_SS_CONTROL_DEFAULT \

5259
sound/soc/codecs/aw87xxx/aw87xxx_pid_60_reg.h Normal file
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14
sound/soc/codecs/aw87xxx/aw87xxx_pid_76_reg.h
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@ -1,4 +1,16 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/* SPDX-License-Identifier: GPL-2.0
* aw87xxx_pid_76_reg.h
*
* Copyright (c) 2021 AWINIC Technology CO., LTD
*
* Author: Barry <zhaozhongbo@awinic.com>
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*/
#ifndef __AW87XXX_PID_76_REG_H__
#define __AW87XXX_PID_76_REG_H__

13
sound/soc/codecs/aw87xxx/aw87xxx_pid_9b_reg.h
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@ -1,4 +1,15 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/* SPDX-License-Identifier: GPL-2.0
* aw87xxx_pid_9b_reg.h
*
* Copyright (c) 2021 AWINIC Technology CO., LTD
*
* Author: Barry <zhaozhongbo@awinic.com>
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*/
#ifndef __AW87XXX_PID_9B_REG_H__
#define __AW87XXX_PID_9B_REG_H__

698
sound/soc/codecs/aw87xxx/aw87xxx_pid_c1_reg.h Normal file
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@ -0,0 +1,698 @@
/* SPDX-License-Identifier: GPL-2.0
* aw87xxx_pid_c1_reg.h
*
* Copyright (c) 2021 AWINIC Technology CO., LTD
*
* Author: Barry <zhaozhongbo@awinic.com>
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*/
#ifndef __AW87XXX_PID_C1_REG_H__
#define __AW87XXX_PID_C1_REG_H__
/* registers list */
#define AW87XXX_PID_C1_ID_REG (0x00)
#define AW87XXX_PID_C1_SYSCTRL_REG (0x01)
#define AW87XXX_PID_C1_CP_REG (0x02)
#define AW87XXX_PID_C1_PAG_REG (0x03)
#define AW87XXX_PID_C1_AGCPO_REG (0x04)
#define AW87XXX_PID_C1_AGC2PA_REG (0x05)
#define AW87XXX_PID_C1_SYSST_REG (0x06)
#define AW87XXX_PID_C1_SYSINT_REG (0x07)
#define AW87XXX_PID_C1_DFT_SYSCTRL0_REG (0x5D)
#define AW87XXX_PID_C1_DFT_SYSCTRL1_REG (0x5E)
#define AW87XXX_PID_C1_DFT_CP_REG (0x5F)
#define AW87XXX_PID_C1_DFT_TRIM0_REG (0x60)
#define AW87XXX_PID_C1_DFT_TRIM1_REG (0x61)
#define AW87XXX_PID_C1_DFT_OC_REG (0x62)
#define AW87XXX_PID_C1_DFT_THGEN0_REG (0x63)
#define AW87XXX_PID_C1_DFT_THGEN1_REG (0x64)
#define AW87XXX_PID_C1_DFT_AGC_REG (0x65)
#define AW87XXX_PID_C1_DFT_LPMODE_REG (0x66)
#define AW87XXX_PID_C1_DFT_RAMPGEN_REG (0x67)
#define AW87XXX_PID_C1_DFT_BIAS_REG (0x68)
#define AW87XXX_PID_C1_OPTION_STATUS0_REG (0x69)
#define AW87XXX_PID_C1_OPTION_STATUS1_REG (0x6A)
#define AW87XXX_PID_C1_OPTION_STATUS2_REG (0x6B)
#define AW87XXX_PID_C1_OPTION_STATUS3_REG (0x6C)
#define AW87XXX_PID_C1_TESTCTRL0_REG (0x6E)
#define AW87XXX_PID_C1_TESTCTRL1_REG (0x6F)
#define AW87XXX_PID_C1_EFWH_REG (0x70)
#define AW87XXX_PID_C1_EFWL_REG (0x71)
#define AW87XXX_PID_C1_EFCTRL1_REG (0x72)
#define AW87XXX_PID_C1_EFCTRL2_REG (0x73)
#define AW87XXX_PID_C1_EFCTRL3_REG (0x74)
#define AW87XXX_PID_C1_EFCTRL4_REG (0x75)
#define AW87XXX_PID_C1_EFRH2_REG (0x76)
#define AW87XXX_PID_C1_EFRH1_REG (0x77)
#define AW87XXX_PID_C1_EFRL2_REG (0x78)
#define AW87XXX_PID_C1_EFRL1_REG (0x79)
#define AW87XXX_PID_C1_TM_REG (0x7A)
#define AW87XXX_PID_C1_TESTIN_REG (0x7B)
#define AW87XXX_PID_C1_TESTIN1_REG (0x7C)
#define AW87XXX_PID_C1_TESTIN2_REG (0x7D)
#define AW87XXX_PID_C1_TESTOUT1_REG (0x7E)
#define AW87XXX_PID_C1_TESTOUT2_REG (0x7F)
#define AW87XXX_PID_C1_DFT_THGEN1_CHECK (0x0a)
/********************************************
* soft control info
* If you need to update this file, add this information manually
*******************************************/
unsigned char aw87xxx_pid_c1_softrst_access[2] = {0x00, 0xaa};
/********************************************
* Register Access
*******************************************/
#define AW87XXX_PID_C1_REG_MAX (0x80)
#define REG_NONE_ACCESS (0)
#define REG_RD_ACCESS (1 << 0)
#define REG_WR_ACCESS (1 << 1)
const unsigned char aw87xxx_pid_c1_reg_access[AW87XXX_PID_C1_REG_MAX] = {
[AW87XXX_PID_C1_ID_REG] = (REG_RD_ACCESS),
[AW87XXX_PID_C1_SYSCTRL_REG] = (REG_RD_ACCESS | REG_WR_ACCESS),
[AW87XXX_PID_C1_CP_REG] = (REG_RD_ACCESS | REG_WR_ACCESS),
[AW87XXX_PID_C1_PAG_REG] = (REG_RD_ACCESS | REG_WR_ACCESS),
[AW87XXX_PID_C1_AGCPO_REG] = (REG_RD_ACCESS | REG_WR_ACCESS),
[AW87XXX_PID_C1_AGC2PA_REG] = (REG_RD_ACCESS | REG_WR_ACCESS),
[AW87XXX_PID_C1_SYSST_REG] = (REG_RD_ACCESS),
[AW87XXX_PID_C1_SYSINT_REG] = (REG_RD_ACCESS),
[AW87XXX_PID_C1_DFT_SYSCTRL0_REG] = (REG_RD_ACCESS | REG_WR_ACCESS),
[AW87XXX_PID_C1_DFT_SYSCTRL1_REG] = (REG_RD_ACCESS | REG_WR_ACCESS),
[AW87XXX_PID_C1_DFT_CP_REG] = (REG_RD_ACCESS | REG_WR_ACCESS),
[AW87XXX_PID_C1_DFT_TRIM0_REG] = (REG_RD_ACCESS | REG_WR_ACCESS),
[AW87XXX_PID_C1_DFT_TRIM1_REG] = (REG_RD_ACCESS | REG_WR_ACCESS),
[AW87XXX_PID_C1_DFT_OC_REG] = (REG_RD_ACCESS | REG_WR_ACCESS),
[AW87XXX_PID_C1_DFT_THGEN0_REG] = (REG_RD_ACCESS | REG_WR_ACCESS),
[AW87XXX_PID_C1_DFT_THGEN1_REG] = (REG_RD_ACCESS | REG_WR_ACCESS),
[AW87XXX_PID_C1_DFT_AGC_REG] = (REG_RD_ACCESS | REG_WR_ACCESS),
[AW87XXX_PID_C1_DFT_LPMODE_REG] = (REG_RD_ACCESS | REG_WR_ACCESS),
[AW87XXX_PID_C1_DFT_RAMPGEN_REG] = (REG_RD_ACCESS | REG_WR_ACCESS),
[AW87XXX_PID_C1_DFT_BIAS_REG] = (REG_RD_ACCESS | REG_WR_ACCESS),
[AW87XXX_PID_C1_OPTION_STATUS0_REG] = (REG_RD_ACCESS),
[AW87XXX_PID_C1_OPTION_STATUS1_REG] = (REG_RD_ACCESS),
[AW87XXX_PID_C1_OPTION_STATUS2_REG] = (REG_RD_ACCESS),
[AW87XXX_PID_C1_OPTION_STATUS3_REG] = (REG_RD_ACCESS),
[AW87XXX_PID_C1_TESTCTRL0_REG] = (REG_RD_ACCESS | REG_WR_ACCESS),
[AW87XXX_PID_C1_TESTCTRL1_REG] = (REG_RD_ACCESS | REG_WR_ACCESS),
[AW87XXX_PID_C1_EFWH_REG] = (REG_RD_ACCESS | REG_WR_ACCESS),
[AW87XXX_PID_C1_EFWL_REG] = (REG_RD_ACCESS | REG_WR_ACCESS),
[AW87XXX_PID_C1_EFCTRL1_REG] = (REG_RD_ACCESS | REG_WR_ACCESS),
[AW87XXX_PID_C1_EFCTRL2_REG] = (REG_RD_ACCESS | REG_WR_ACCESS),
[AW87XXX_PID_C1_EFCTRL3_REG] = (REG_RD_ACCESS | REG_WR_ACCESS),
[AW87XXX_PID_C1_EFCTRL4_REG] = (REG_RD_ACCESS | REG_WR_ACCESS),
[AW87XXX_PID_C1_EFRH2_REG] = (REG_RD_ACCESS),
[AW87XXX_PID_C1_EFRH1_REG] = (REG_RD_ACCESS),
[AW87XXX_PID_C1_EFRL2_REG] = (REG_RD_ACCESS),
[AW87XXX_PID_C1_EFRL1_REG] = (REG_RD_ACCESS),
[AW87XXX_PID_C1_TM_REG] = (REG_NONE_ACCESS),
[AW87XXX_PID_C1_TESTIN_REG] = (REG_RD_ACCESS | REG_WR_ACCESS),
[AW87XXX_PID_C1_TESTIN1_REG] = (REG_RD_ACCESS | REG_WR_ACCESS),
[AW87XXX_PID_C1_TESTIN2_REG] = (REG_RD_ACCESS | REG_WR_ACCESS),
[AW87XXX_PID_C1_TESTOUT1_REG] = (REG_RD_ACCESS),
[AW87XXX_PID_C1_TESTOUT2_REG] = (REG_RD_ACCESS),
};
/* detail information of registers begin */
/* ID (0x00) detail */
/* IDCODE bit 7:0 (ID 0x00) */
#define AW87XXX_PID_C1_IDCODE_START_BIT (0)
#define AW87XXX_PID_C1_IDCODE_BITS_LEN (8)
#define AW87XXX_PID_C1_IDCODE_MASK \
(~(((1<<AW87XXX_PID_C1_IDCODE_BITS_LEN)-1) << AW87XXX_PID_C1_IDCODE_START_BIT))
#define AW87XXX_PID_C1_IDCODE_DEFAULT (0xC1)
#define AW87XXX_PID_C1_IDCODE_DEFAULT_VALUE \
(AW87XXX_PID_C1_IDCODE_DEFAULT << AW87XXX_PID_C1_IDCODE_START_BIT)
/* default value of ID (0x00) */
/* #define AW87XXX_PID_C1_ID_DEFAULT (0xC1) */
/* SYSCTRL (0x01) detail */
/* REG_VER_SEL bit 7:6 (SYSCTRL 0x01) */
#define AW87XXX_PID_C1_REG_VER_SEL_START_BIT (6)
#define AW87XXX_PID_C1_REG_VER_SEL_BITS_LEN (2)
#define AW87XXX_PID_C1_REG_VER_SEL_MASK \
(~(((1<<AW87XXX_PID_C1_REG_VER_SEL_BITS_LEN)-1) << AW87XXX_PID_C1_REG_VER_SEL_START_BIT))
#define AW87XXX_PID_C1_REG_VER_SEL_LOW_NOISE_VERSION (0)
#define AW87XXX_PID_C1_REG_VER_SEL_LOW_NOISE_VERSION_VALUE \
(AW87XXX_PID_C1_REG_VER_SEL_LOW_NOISE_VERSION << AW87XXX_PID_C1_REG_VER_SEL_START_BIT)
#define AW87XXX_PID_C1_REG_VER_SEL_NORMAL_VERSIONBOM_COMPACT (1)
#define AW87XXX_PID_C1_REG_VER_SEL_NORMAL_VERSIONBOM_COMPACT_VALUE \
(AW87XXX_PID_C1_REG_VER_SEL_NORMAL_VERSIONBOM_COMPACT << AW87XXX_PID_C1_REG_VER_SEL_START_BIT)
#define AW87XXX_PID_C1_REG_VER_SEL_SUPER_RCV_MODE_NOTE_ONLY_ENSPK0_VALID (2)
#define AW87XXX_PID_C1_REG_VER_SEL_SUPER_RCV_MODE_NOTE_ONLY_ENSPK0_VALID_VALUE \
(AW87XXX_PID_C1_REG_VER_SEL_SUPER_RCV_MODE_NOTE_ONLY_ENSPK0_VALID << AW87XXX_PID_C1_REG_VER_SEL_START_BIT)
#define AW87XXX_PID_C1_REG_VER_SEL_TURN_TO_01 (3)
#define AW87XXX_PID_C1_REG_VER_SEL_TURN_TO_01_VALUE \
(AW87XXX_PID_C1_REG_VER_SEL_TURN_TO_01 << AW87XXX_PID_C1_REG_VER_SEL_START_BIT)
#define AW87XXX_PID_C1_REG_VER_SEL_DEFAULT (0x0)
#define AW87XXX_PID_C1_REG_VER_SEL_DEFAULT_VALUE \
(AW87XXX_PID_C1_REG_VER_SEL_DEFAULT << AW87XXX_PID_C1_REG_VER_SEL_START_BIT)
/* REG_EN_ADAP bit 5 (SYSCTRL 0x01) */
#define AW87XXX_PID_C1_REG_EN_ADAP_START_BIT (5)
#define AW87XXX_PID_C1_REG_EN_ADAP_BITS_LEN (1)
#define AW87XXX_PID_C1_REG_EN_ADAP_MASK \
(~(((1<<AW87XXX_PID_C1_REG_EN_ADAP_BITS_LEN)-1) << AW87XXX_PID_C1_REG_EN_ADAP_START_BIT))
#define AW87XXX_PID_C1_REG_EN_ADAP_ADP_DISABLE (0)
#define AW87XXX_PID_C1_REG_EN_ADAP_ADP_DISABLE_VALUE \
(AW87XXX_PID_C1_REG_EN_ADAP_ADP_DISABLE << AW87XXX_PID_C1_REG_EN_ADAP_START_BIT)
#define AW87XXX_PID_C1_REG_EN_ADAP_ADP_ENABLE (1)
#define AW87XXX_PID_C1_REG_EN_ADAP_ADP_ENABLE_VALUE \
(AW87XXX_PID_C1_REG_EN_ADAP_ADP_ENABLE << AW87XXX_PID_C1_REG_EN_ADAP_START_BIT)
#define AW87XXX_PID_C1_REG_EN_ADAP_DEFAULT (0x1)
#define AW87XXX_PID_C1_REG_EN_ADAP_DEFAULT_VALUE \
(AW87XXX_PID_C1_REG_EN_ADAP_DEFAULT << AW87XXX_PID_C1_REG_EN_ADAP_START_BIT)
/* REG_EN_2X bit 4 (SYSCTRL 0x01) */
#define AW87XXX_PID_C1_REG_EN_2X_START_BIT (4)
#define AW87XXX_PID_C1_REG_EN_2X_BITS_LEN (1)
#define AW87XXX_PID_C1_REG_EN_2X_MASK \
(~(((1<<AW87XXX_PID_C1_REG_EN_2X_BITS_LEN)-1) << AW87XXX_PID_C1_REG_EN_2X_START_BIT))
#define AW87XXX_PID_C1_REG_EN_2X_2X_CHARGE_PUMP_MODE_DISABLE_1X_DIRECT_THROUGH_MODE_ENABLE (0)
#define AW87XXX_PID_C1_REG_EN_2X_2X_CHARGE_PUMP_MODE_DISABLE_1X_DIRECT_THROUGH_MODE_ENABLE_VALUE \
(AW87XXX_PID_C1_REG_EN_2X_2X_CHARGE_PUMP_MODE_DISABLE_1X_DIRECT_THROUGH_MODE_ENABLE << AW87XXX_PID_C1_REG_EN_2X_START_BIT)
#define AW87XXX_PID_C1_REG_EN_2X_2X_CHARGE_PUMP_MODE_ENABLE_1X_DIRECT_THROUGH_MODE_DISABLE (1)
#define AW87XXX_PID_C1_REG_EN_2X_2X_CHARGE_PUMP_MODE_ENABLE_1X_DIRECT_THROUGH_MODE_DISABLE_VALUE \
(AW87XXX_PID_C1_REG_EN_2X_2X_CHARGE_PUMP_MODE_ENABLE_1X_DIRECT_THROUGH_MODE_DISABLE << AW87XXX_PID_C1_REG_EN_2X_START_BIT)
#define AW87XXX_PID_C1_REG_EN_2X_DEFAULT (0x1)
#define AW87XXX_PID_C1_REG_EN_2X_DEFAULT_VALUE \
(AW87XXX_PID_C1_REG_EN_2X_DEFAULT << AW87XXX_PID_C1_REG_EN_2X_START_BIT)
/* EN_SPK bit 3 (SYSCTRL 0x01) */
#define AW87XXX_PID_C1_EN_SPK_START_BIT (3)
#define AW87XXX_PID_C1_EN_SPK_BITS_LEN (1)
#define AW87XXX_PID_C1_EN_SPK_MASK \
(~(((1<<AW87XXX_PID_C1_EN_SPK_BITS_LEN)-1) << AW87XXX_PID_C1_EN_SPK_START_BIT))
#define AW87XXX_PID_C1_EN_SPK_SPK_MODE_DISABLE (0)
#define AW87XXX_PID_C1_EN_SPK_SPK_MODE_DISABLE_VALUE \
(AW87XXX_PID_C1_EN_SPK_SPK_MODE_DISABLE << AW87XXX_PID_C1_EN_SPK_START_BIT)
#define AW87XXX_PID_C1_EN_SPK_SPK_MODE_ENABLE (1)
#define AW87XXX_PID_C1_EN_SPK_SPK_MODE_ENABLE_VALUE \
(AW87XXX_PID_C1_EN_SPK_SPK_MODE_ENABLE << AW87XXX_PID_C1_EN_SPK_START_BIT)
#define AW87XXX_PID_C1_EN_SPK_DEFAULT (0x1)
#define AW87XXX_PID_C1_EN_SPK_DEFAULT_VALUE \
(AW87XXX_PID_C1_EN_SPK_DEFAULT << AW87XXX_PID_C1_EN_SPK_START_BIT)
/* EN_PA bit 2 (SYSCTRL 0x01) */
#define AW87XXX_PID_C1_EN_PA_START_BIT (2)
#define AW87XXX_PID_C1_EN_PA_BITS_LEN (1)
#define AW87XXX_PID_C1_EN_PA_MASK \
(~(((1<<AW87XXX_PID_C1_EN_PA_BITS_LEN)-1) << AW87XXX_PID_C1_EN_PA_START_BIT))
#define AW87XXX_PID_C1_EN_PA_POWER_AMPLIFIER_DISABLE (0)
#define AW87XXX_PID_C1_EN_PA_POWER_AMPLIFIER_DISABLE_VALUE \
(AW87XXX_PID_C1_EN_PA_POWER_AMPLIFIER_DISABLE << AW87XXX_PID_C1_EN_PA_START_BIT)
#define AW87XXX_PID_C1_EN_PA_POWER_AMPLIFIER_ENABLE (1)
#define AW87XXX_PID_C1_EN_PA_POWER_AMPLIFIER_ENABLE_VALUE \
(AW87XXX_PID_C1_EN_PA_POWER_AMPLIFIER_ENABLE << AW87XXX_PID_C1_EN_PA_START_BIT)
#define AW87XXX_PID_C1_EN_PA_DEFAULT (0x1)
#define AW87XXX_PID_C1_EN_PA_DEFAULT_VALUE \
(AW87XXX_PID_C1_EN_PA_DEFAULT << AW87XXX_PID_C1_EN_PA_START_BIT)
/* REG_EN_CP bit 1 (SYSCTRL 0x01) */
#define AW87XXX_PID_C1_REG_EN_CP_START_BIT (1)
#define AW87XXX_PID_C1_REG_EN_CP_BITS_LEN (1)
#define AW87XXX_PID_C1_REG_EN_CP_MASK \
(~(((1<<AW87XXX_PID_C1_REG_EN_CP_BITS_LEN)-1) << AW87XXX_PID_C1_REG_EN_CP_START_BIT))
#define AW87XXX_PID_C1_REG_EN_CP_CHARGE_PUMP_DISABLE_PVDD0 (0)
#define AW87XXX_PID_C1_REG_EN_CP_CHARGE_PUMP_DISABLE_PVDD0_VALUE \
(AW87XXX_PID_C1_REG_EN_CP_CHARGE_PUMP_DISABLE_PVDD0 << AW87XXX_PID_C1_REG_EN_CP_START_BIT)
#define AW87XXX_PID_C1_REG_EN_CP_CHARGE_PUMP_ENABLE_THE_CP_WORKING_MODE_DEPENDS_ON_EN2X (1)
#define AW87XXX_PID_C1_REG_EN_CP_CHARGE_PUMP_ENABLE_THE_CP_WORKING_MODE_DEPENDS_ON_EN2X_VALUE \
(AW87XXX_PID_C1_REG_EN_CP_CHARGE_PUMP_ENABLE_THE_CP_WORKING_MODE_DEPENDS_ON_EN2X << AW87XXX_PID_C1_REG_EN_CP_START_BIT)
#define AW87XXX_PID_C1_REG_EN_CP_DEFAULT (0x1)
#define AW87XXX_PID_C1_REG_EN_CP_DEFAULT_VALUE \
(AW87XXX_PID_C1_REG_EN_CP_DEFAULT << AW87XXX_PID_C1_REG_EN_CP_START_BIT)
/* EN_SW bit 0 (SYSCTRL 0x01) */
#define AW87XXX_PID_C1_EN_SW_START_BIT (0)
#define AW87XXX_PID_C1_EN_SW_BITS_LEN (1)
#define AW87XXX_PID_C1_EN_SW_MASK \
(~(((1<<AW87XXX_PID_C1_EN_SW_BITS_LEN)-1) << AW87XXX_PID_C1_EN_SW_START_BIT))
#define AW87XXX_PID_C1_EN_SW_SOFTWARE_DISABLE (0)
#define AW87XXX_PID_C1_EN_SW_SOFTWARE_DISABLE_VALUE \
(AW87XXX_PID_C1_EN_SW_SOFTWARE_DISABLE << AW87XXX_PID_C1_EN_SW_START_BIT)
#define AW87XXX_PID_C1_EN_SW_SOFTWARE_ENABLE (1)
#define AW87XXX_PID_C1_EN_SW_SOFTWARE_ENABLE_VALUE \
(AW87XXX_PID_C1_EN_SW_SOFTWARE_ENABLE << AW87XXX_PID_C1_EN_SW_START_BIT)
#define AW87XXX_PID_C1_EN_SW_DEFAULT (0x0)
#define AW87XXX_PID_C1_EN_SW_DEFAULT_VALUE \
(AW87XXX_PID_C1_EN_SW_DEFAULT << AW87XXX_PID_C1_EN_SW_START_BIT)
/* default value of SYSCTRL (0x01) */
/* #define AW87XXX_PID_C1_SYSCTRL_DEFAULT (0x3E) */
/* CP (0x02) detail */
/* REG_CP_PEAK_CUR bit 7:6 (CP 0x02) */
#define AW87XXX_PID_C1_REG_CP_PEAK_CUR_START_BIT (6)
#define AW87XXX_PID_C1_REG_CP_PEAK_CUR_BITS_LEN (2)
#define AW87XXX_PID_C1_REG_CP_PEAK_CUR_MASK \
(~(((1<<AW87XXX_PID_C1_REG_CP_PEAK_CUR_BITS_LEN)-1) << AW87XXX_PID_C1_REG_CP_PEAK_CUR_START_BIT))
#define AW87XXX_PID_C1_REG_CP_PEAK_CUR_DEFAULT (0x1)
#define AW87XXX_PID_C1_REG_CP_PEAK_CUR_DEFAULT_VALUE \
(AW87XXX_PID_C1_REG_CP_PEAK_CUR_DEFAULT << AW87XXX_PID_C1_REG_CP_PEAK_CUR_START_BIT)
/* REG_CP_SOFT_CUR bit 5:4 (CP 0x02) */
#define AW87XXX_PID_C1_REG_CP_SOFT_CUR_START_BIT (4)
#define AW87XXX_PID_C1_REG_CP_SOFT_CUR_BITS_LEN (2)
#define AW87XXX_PID_C1_REG_CP_SOFT_CUR_MASK \
(~(((1<<AW87XXX_PID_C1_REG_CP_SOFT_CUR_BITS_LEN)-1) << AW87XXX_PID_C1_REG_CP_SOFT_CUR_START_BIT))
#define AW87XXX_PID_C1_REG_CP_SOFT_CUR_DEFAULT (0x1)
#define AW87XXX_PID_C1_REG_CP_SOFT_CUR_DEFAULT_VALUE \
(AW87XXX_PID_C1_REG_CP_SOFT_CUR_DEFAULT << AW87XXX_PID_C1_REG_CP_SOFT_CUR_START_BIT)
/* REG_CP_OVP bit 3:0 (CP 0x02) */
#define AW87XXX_PID_C1_REG_CP_OVP_START_BIT (0)
#define AW87XXX_PID_C1_REG_CP_OVP_BITS_LEN (4)
#define AW87XXX_PID_C1_REG_CP_OVP_MASK \
(~(((1<<AW87XXX_PID_C1_REG_CP_OVP_BITS_LEN)-1) << AW87XXX_PID_C1_REG_CP_OVP_START_BIT))
#define AW87XXX_PID_C1_REG_CP_OVP_DEFAULT (0x8)
#define AW87XXX_PID_C1_REG_CP_OVP_DEFAULT_VALUE \
(AW87XXX_PID_C1_REG_CP_OVP_DEFAULT << AW87XXX_PID_C1_REG_CP_OVP_START_BIT)
/* default value of CP (0x02) */
/* #define AW87XXX_PID_C1_CP_DEFAULT (0x58) */
/* PAG (0x03) detail */
/* GAIN bit 2:0 (PAG 0x03) */
#define AW87XXX_PID_C1_GAIN_START_BIT (0)
#define AW87XXX_PID_C1_GAIN_BITS_LEN (3)
#define AW87XXX_PID_C1_GAIN_MASK \
(~(((1<<AW87XXX_PID_C1_GAIN_BITS_LEN)-1) << AW87XXX_PID_C1_GAIN_START_BIT))
#define AW87XXX_PID_C1_GAIN_DEFAULT (0x2)
#define AW87XXX_PID_C1_GAIN_DEFAULT_VALUE \
(AW87XXX_PID_C1_GAIN_DEFAULT << AW87XXX_PID_C1_GAIN_START_BIT)
/* default value of PAG (0x03) */
/* #define AW87XXX_PID_C1_PAG_DEFAULT (0x02) */
/* AGCPO (0x04) detail */
/* AK1_S bit 6:5 (AGCPO 0x04) */
#define AW87XXX_PID_C1_AK1_S_START_BIT (5)
#define AW87XXX_PID_C1_AK1_S_BITS_LEN (2)
#define AW87XXX_PID_C1_AK1_S_MASK \
(~(((1<<AW87XXX_PID_C1_AK1_S_BITS_LEN)-1) << AW87XXX_PID_C1_AK1_S_START_BIT))
#define AW87XXX_PID_C1_AK1_S_0P04MSDB (0)
#define AW87XXX_PID_C1_AK1_S_0P04MSDB_VALUE \
(AW87XXX_PID_C1_AK1_S_0P04MSDB << AW87XXX_PID_C1_AK1_S_START_BIT)
#define AW87XXX_PID_C1_AK1_S_0P08MSDB (1)
#define AW87XXX_PID_C1_AK1_S_0P08MSDB_VALUE \
(AW87XXX_PID_C1_AK1_S_0P08MSDB << AW87XXX_PID_C1_AK1_S_START_BIT)
#define AW87XXX_PID_C1_AK1_S_0P16MSDB (2)
#define AW87XXX_PID_C1_AK1_S_0P16MSDB_VALUE \
(AW87XXX_PID_C1_AK1_S_0P16MSDB << AW87XXX_PID_C1_AK1_S_START_BIT)
#define AW87XXX_PID_C1_AK1_S_0P32MSDB (3)
#define AW87XXX_PID_C1_AK1_S_0P32MSDB_VALUE \
(AW87XXX_PID_C1_AK1_S_0P32MSDB << AW87XXX_PID_C1_AK1_S_START_BIT)
#define AW87XXX_PID_C1_AK1_S_DEFAULT (0x1)
#define AW87XXX_PID_C1_AK1_S_DEFAULT_VALUE \
(AW87XXX_PID_C1_AK1_S_DEFAULT << AW87XXX_PID_C1_AK1_S_START_BIT)
/* PD_AGC1 bit 4 (AGCPO 0x04) */
#define AW87XXX_PID_C1_PD_AGC1_START_BIT (4)
#define AW87XXX_PID_C1_PD_AGC1_BITS_LEN (1)
#define AW87XXX_PID_C1_PD_AGC1_MASK \
(~(((1<<AW87XXX_PID_C1_PD_AGC1_BITS_LEN)-1) << AW87XXX_PID_C1_PD_AGC1_START_BIT))
#define AW87XXX_PID_C1_PD_AGC1_AGC1_FUNCTION_POWERMINUSUP (0)
#define AW87XXX_PID_C1_PD_AGC1_AGC1_FUNCTION_POWERMINUSUP_VALUE \
(AW87XXX_PID_C1_PD_AGC1_AGC1_FUNCTION_POWERMINUSUP << AW87XXX_PID_C1_PD_AGC1_START_BIT)
#define AW87XXX_PID_C1_PD_AGC1_AGC1_FUNCTION_POWERMINUSDOWN (1)
#define AW87XXX_PID_C1_PD_AGC1_AGC1_FUNCTION_POWERMINUSDOWN_VALUE \
(AW87XXX_PID_C1_PD_AGC1_AGC1_FUNCTION_POWERMINUSDOWN << AW87XXX_PID_C1_PD_AGC1_START_BIT)
#define AW87XXX_PID_C1_PD_AGC1_DEFAULT (0x0)
#define AW87XXX_PID_C1_PD_AGC1_DEFAULT_VALUE \
(AW87XXX_PID_C1_PD_AGC1_DEFAULT << AW87XXX_PID_C1_PD_AGC1_START_BIT)
/* AGC2PO bit 3:0 (AGCPO 0x04) */
#define AW87XXX_PID_C1_AGC2PO_START_BIT (0)
#define AW87XXX_PID_C1_AGC2PO_BITS_LEN (4)
#define AW87XXX_PID_C1_AGC2PO_MASK \
(~(((1<<AW87XXX_PID_C1_AGC2PO_BITS_LEN)-1) << AW87XXX_PID_C1_AGC2PO_START_BIT))
#define AW87XXX_PID_C1_AGC2PO_0P5W8 (0)
#define AW87XXX_PID_C1_AGC2PO_0P5W8_VALUE \
(AW87XXX_PID_C1_AGC2PO_0P5W8 << AW87XXX_PID_C1_AGC2PO_START_BIT)
#define AW87XXX_PID_C1_AGC2PO_0P6W8 (1)
#define AW87XXX_PID_C1_AGC2PO_0P6W8_VALUE \
(AW87XXX_PID_C1_AGC2PO_0P6W8 << AW87XXX_PID_C1_AGC2PO_START_BIT)
#define AW87XXX_PID_C1_AGC2PO_0P7W8 (2)
#define AW87XXX_PID_C1_AGC2PO_0P7W8_VALUE \
(AW87XXX_PID_C1_AGC2PO_0P7W8 << AW87XXX_PID_C1_AGC2PO_START_BIT)
#define AW87XXX_PID_C1_AGC2PO_0P8W8 (3)
#define AW87XXX_PID_C1_AGC2PO_0P8W8_VALUE \
(AW87XXX_PID_C1_AGC2PO_0P8W8 << AW87XXX_PID_C1_AGC2PO_START_BIT)
#define AW87XXX_PID_C1_AGC2PO_0P9W8 (4)
#define AW87XXX_PID_C1_AGC2PO_0P9W8_VALUE \
(AW87XXX_PID_C1_AGC2PO_0P9W8 << AW87XXX_PID_C1_AGC2PO_START_BIT)
#define AW87XXX_PID_C1_AGC2PO_1P0W8 (5)
#define AW87XXX_PID_C1_AGC2PO_1P0W8_VALUE \
(AW87XXX_PID_C1_AGC2PO_1P0W8 << AW87XXX_PID_C1_AGC2PO_START_BIT)
#define AW87XXX_PID_C1_AGC2PO_1P1W8 (6)
#define AW87XXX_PID_C1_AGC2PO_1P1W8_VALUE \
(AW87XXX_PID_C1_AGC2PO_1P1W8 << AW87XXX_PID_C1_AGC2PO_START_BIT)
#define AW87XXX_PID_C1_AGC2PO_1P2W8 (7)
#define AW87XXX_PID_C1_AGC2PO_1P2W8_VALUE \
(AW87XXX_PID_C1_AGC2PO_1P2W8 << AW87XXX_PID_C1_AGC2PO_START_BIT)
#define AW87XXX_PID_C1_AGC2PO_1P3W8 (8)
#define AW87XXX_PID_C1_AGC2PO_1P3W8_VALUE \
(AW87XXX_PID_C1_AGC2PO_1P3W8 << AW87XXX_PID_C1_AGC2PO_START_BIT)
#define AW87XXX_PID_C1_AGC2PO_1P4W8 (9)
#define AW87XXX_PID_C1_AGC2PO_1P4W8_VALUE \
(AW87XXX_PID_C1_AGC2PO_1P4W8 << AW87XXX_PID_C1_AGC2PO_START_BIT)
#define AW87XXX_PID_C1_AGC2PO_1P5W8 (10)
#define AW87XXX_PID_C1_AGC2PO_1P5W8_VALUE \
(AW87XXX_PID_C1_AGC2PO_1P5W8 << AW87XXX_PID_C1_AGC2PO_START_BIT)
#define AW87XXX_PID_C1_AGC2PO_1P6W8 (11)
#define AW87XXX_PID_C1_AGC2PO_1P6W8_VALUE \
(AW87XXX_PID_C1_AGC2PO_1P6W8 << AW87XXX_PID_C1_AGC2PO_START_BIT)
#define AW87XXX_PID_C1_AGC2PO_AGC2_OFF (15)
#define AW87XXX_PID_C1_AGC2PO_AGC2_OFF_VALUE \
(AW87XXX_PID_C1_AGC2PO_AGC2_OFF << AW87XXX_PID_C1_AGC2PO_START_BIT)
#define AW87XXX_PID_C1_AGC2PO_DEFAULT (0x7)
#define AW87XXX_PID_C1_AGC2PO_DEFAULT_VALUE \
(AW87XXX_PID_C1_AGC2PO_DEFAULT << AW87XXX_PID_C1_AGC2PO_START_BIT)
/* default value of AGCPO (0x04) */
/* #define AW87XXX_PID_C1_AGCPO_DEFAULT (0x27) */
/* AGC2PA (0x05) detail */
/* RK_S bit 7:5 (AGC2PA 0x05) */
#define AW87XXX_PID_C1_RK_S_START_BIT (5)
#define AW87XXX_PID_C1_RK_S_BITS_LEN (3)
#define AW87XXX_PID_C1_RK_S_MASK \
(~(((1<<AW87XXX_PID_C1_RK_S_BITS_LEN)-1) << AW87XXX_PID_C1_RK_S_START_BIT))
#define AW87XXX_PID_C1_RK_S_5P12MSDB (0)
#define AW87XXX_PID_C1_RK_S_5P12MSDB_VALUE \
(AW87XXX_PID_C1_RK_S_5P12MSDB << AW87XXX_PID_C1_RK_S_START_BIT)
#define AW87XXX_PID_C1_RK_S_10P24MSDB (1)
#define AW87XXX_PID_C1_RK_S_10P24MSDB_VALUE \
(AW87XXX_PID_C1_RK_S_10P24MSDB << AW87XXX_PID_C1_RK_S_START_BIT)
#define AW87XXX_PID_C1_RK_S_20P48MSDB (2)
#define AW87XXX_PID_C1_RK_S_20P48MSDB_VALUE \
(AW87XXX_PID_C1_RK_S_20P48MSDB << AW87XXX_PID_C1_RK_S_START_BIT)
#define AW87XXX_PID_C1_RK_S_41MSDB (3)
#define AW87XXX_PID_C1_RK_S_41MSDB_VALUE \
(AW87XXX_PID_C1_RK_S_41MSDB << AW87XXX_PID_C1_RK_S_START_BIT)
#define AW87XXX_PID_C1_RK_S_82MSDB (4)
#define AW87XXX_PID_C1_RK_S_82MSDB_VALUE \
(AW87XXX_PID_C1_RK_S_82MSDB << AW87XXX_PID_C1_RK_S_START_BIT)
#define AW87XXX_PID_C1_RK_S_164MSDB (5)
#define AW87XXX_PID_C1_RK_S_164MSDB_VALUE \
(AW87XXX_PID_C1_RK_S_164MSDB << AW87XXX_PID_C1_RK_S_START_BIT)
#define AW87XXX_PID_C1_RK_S_328MSDB (6)
#define AW87XXX_PID_C1_RK_S_328MSDB_VALUE \
(AW87XXX_PID_C1_RK_S_328MSDB << AW87XXX_PID_C1_RK_S_START_BIT)
#define AW87XXX_PID_C1_RK_S_656MSDB (7)
#define AW87XXX_PID_C1_RK_S_656MSDB_VALUE \
(AW87XXX_PID_C1_RK_S_656MSDB << AW87XXX_PID_C1_RK_S_START_BIT)
#define AW87XXX_PID_C1_RK_S_DEFAULT (0x2)
#define AW87XXX_PID_C1_RK_S_DEFAULT_VALUE \
(AW87XXX_PID_C1_RK_S_DEFAULT << AW87XXX_PID_C1_RK_S_START_BIT)
/* AK2_S bit 4:2 (AGC2PA 0x05) */
#define AW87XXX_PID_C1_AK2_S_START_BIT (2)
#define AW87XXX_PID_C1_AK2_S_BITS_LEN (3)
#define AW87XXX_PID_C1_AK2_S_MASK \
(~(((1<<AW87XXX_PID_C1_AK2_S_BITS_LEN)-1) << AW87XXX_PID_C1_AK2_S_START_BIT))
#define AW87XXX_PID_C1_AK2_S_1P28MSDB (0)
#define AW87XXX_PID_C1_AK2_S_1P28MSDB_VALUE \
(AW87XXX_PID_C1_AK2_S_1P28MSDB << AW87XXX_PID_C1_AK2_S_START_BIT)
#define AW87XXX_PID_C1_AK2_S_2P56MSDB (1)
#define AW87XXX_PID_C1_AK2_S_2P56MSDB_VALUE \
(AW87XXX_PID_C1_AK2_S_2P56MSDB << AW87XXX_PID_C1_AK2_S_START_BIT)
#define AW87XXX_PID_C1_AK2_S_10P24MSDB (2)
#define AW87XXX_PID_C1_AK2_S_10P24MSDB_VALUE \
(AW87XXX_PID_C1_AK2_S_10P24MSDB << AW87XXX_PID_C1_AK2_S_START_BIT)
#define AW87XXX_PID_C1_AK2_S_41MSDB (3)
#define AW87XXX_PID_C1_AK2_S_41MSDB_VALUE \
(AW87XXX_PID_C1_AK2_S_41MSDB << AW87XXX_PID_C1_AK2_S_START_BIT)
#define AW87XXX_PID_C1_AK2_S_82MSDB (4)
#define AW87XXX_PID_C1_AK2_S_82MSDB_VALUE \
(AW87XXX_PID_C1_AK2_S_82MSDB << AW87XXX_PID_C1_AK2_S_START_BIT)
#define AW87XXX_PID_C1_AK2_S_164MSDB (5)
#define AW87XXX_PID_C1_AK2_S_164MSDB_VALUE \
(AW87XXX_PID_C1_AK2_S_164MSDB << AW87XXX_PID_C1_AK2_S_START_BIT)
#define AW87XXX_PID_C1_AK2_S_328MSDB (6)
#define AW87XXX_PID_C1_AK2_S_328MSDB_VALUE \
(AW87XXX_PID_C1_AK2_S_328MSDB << AW87XXX_PID_C1_AK2_S_START_BIT)
#define AW87XXX_PID_C1_AK2_S_656MSDB (7)
#define AW87XXX_PID_C1_AK2_S_656MSDB_VALUE \
(AW87XXX_PID_C1_AK2_S_656MSDB << AW87XXX_PID_C1_AK2_S_START_BIT)
#define AW87XXX_PID_C1_AK2_S_DEFAULT (0x3)
#define AW87XXX_PID_C1_AK2_S_DEFAULT_VALUE \
(AW87XXX_PID_C1_AK2_S_DEFAULT << AW87XXX_PID_C1_AK2_S_START_BIT)
/* AK2F_S bit 1:0 (AGC2PA 0x05) */
#define AW87XXX_PID_C1_AK2F_S_START_BIT (0)
#define AW87XXX_PID_C1_AK2F_S_BITS_LEN (2)
#define AW87XXX_PID_C1_AK2F_S_MASK \
(~(((1<<AW87XXX_PID_C1_AK2F_S_BITS_LEN)-1) << AW87XXX_PID_C1_AK2F_S_START_BIT))
#define AW87XXX_PID_C1_AK2F_S_10P24MSDB (0)
#define AW87XXX_PID_C1_AK2F_S_10P24MSDB_VALUE \
(AW87XXX_PID_C1_AK2F_S_10P24MSDB << AW87XXX_PID_C1_AK2F_S_START_BIT)
#define AW87XXX_PID_C1_AK2F_S_20P48MSDB (1)
#define AW87XXX_PID_C1_AK2F_S_20P48MSDB_VALUE \
(AW87XXX_PID_C1_AK2F_S_20P48MSDB << AW87XXX_PID_C1_AK2F_S_START_BIT)
#define AW87XXX_PID_C1_AK2F_S_41MSDB (2)
#define AW87XXX_PID_C1_AK2F_S_41MSDB_VALUE \
(AW87XXX_PID_C1_AK2F_S_41MSDB << AW87XXX_PID_C1_AK2F_S_START_BIT)
#define AW87XXX_PID_C1_AK2F_S_82MSDB (3)
#define AW87XXX_PID_C1_AK2F_S_82MSDB_VALUE \
(AW87XXX_PID_C1_AK2F_S_82MSDB << AW87XXX_PID_C1_AK2F_S_START_BIT)
#define AW87XXX_PID_C1_AK2F_S_DEFAULT (0x2)
#define AW87XXX_PID_C1_AK2F_S_DEFAULT_VALUE \
(AW87XXX_PID_C1_AK2F_S_DEFAULT << AW87XXX_PID_C1_AK2F_S_START_BIT)
/* default value of AGC2PA (0x05) */
/* #define AW87XXX_PID_C1_AGC2PA_DEFAULT (0x4E) */
/* SYSST (0x06) detail */
/* UVLO bit 7 (SYSST 0x06) */
#define AW87XXX_PID_C1_UVLO_START_BIT (7)
#define AW87XXX_PID_C1_UVLO_BITS_LEN (1)
#define AW87XXX_PID_C1_UVLO_MASK \
(~(((1<<AW87XXX_PID_C1_UVLO_BITS_LEN)-1) << AW87XXX_PID_C1_UVLO_START_BIT))
#define AW87XXX_PID_C1_UVLO_DEFAULT (0x0)
#define AW87XXX_PID_C1_UVLO_DEFAULT_VALUE \
(AW87XXX_PID_C1_UVLO_DEFAULT << AW87XXX_PID_C1_UVLO_START_BIT)
/* OTN bit 6 (SYSST 0x06) */
#define AW87XXX_PID_C1_OTN_START_BIT (6)
#define AW87XXX_PID_C1_OTN_BITS_LEN (1)
#define AW87XXX_PID_C1_OTN_MASK \
(~(((1<<AW87XXX_PID_C1_OTN_BITS_LEN)-1) << AW87XXX_PID_C1_OTN_START_BIT))
#define AW87XXX_PID_C1_OTN_DEFAULT (0x1)
#define AW87XXX_PID_C1_OTN_DEFAULT_VALUE \
(AW87XXX_PID_C1_OTN_DEFAULT << AW87XXX_PID_C1_OTN_START_BIT)
/* OC_FLAG bit 5 (SYSST 0x06) */
#define AW87XXX_PID_C1_OC_FLAG_START_BIT (5)
#define AW87XXX_PID_C1_OC_FLAG_BITS_LEN (1)
#define AW87XXX_PID_C1_OC_FLAG_MASK \
(~(((1<<AW87XXX_PID_C1_OC_FLAG_BITS_LEN)-1) << AW87XXX_PID_C1_OC_FLAG_START_BIT))
#define AW87XXX_PID_C1_OC_FLAG_DEFAULT (0x0)
#define AW87XXX_PID_C1_OC_FLAG_DEFAULT_VALUE \
(AW87XXX_PID_C1_OC_FLAG_DEFAULT << AW87XXX_PID_C1_OC_FLAG_START_BIT)
/* ADAP_CP bit 4 (SYSST 0x06) */
#define AW87XXX_PID_C1_ADAP_CP_START_BIT (4)
#define AW87XXX_PID_C1_ADAP_CP_BITS_LEN (1)
#define AW87XXX_PID_C1_ADAP_CP_MASK \
(~(((1<<AW87XXX_PID_C1_ADAP_CP_BITS_LEN)-1) << AW87XXX_PID_C1_ADAP_CP_START_BIT))
#define AW87XXX_PID_C1_ADAP_CP_DEFAULT (0x1)
#define AW87XXX_PID_C1_ADAP_CP_DEFAULT_VALUE \
(AW87XXX_PID_C1_ADAP_CP_DEFAULT << AW87XXX_PID_C1_ADAP_CP_START_BIT)
/* STARTOK bit 3 (SYSST 0x06) */
#define AW87XXX_PID_C1_STARTOK_START_BIT (3)
#define AW87XXX_PID_C1_STARTOK_BITS_LEN (1)
#define AW87XXX_PID_C1_STARTOK_MASK \
(~(((1<<AW87XXX_PID_C1_STARTOK_BITS_LEN)-1) << AW87XXX_PID_C1_STARTOK_START_BIT))
#define AW87XXX_PID_C1_STARTOK_DEFAULT (0x0)
#define AW87XXX_PID_C1_STARTOK_DEFAULT_VALUE \
(AW87XXX_PID_C1_STARTOK_DEFAULT << AW87XXX_PID_C1_STARTOK_START_BIT)
/* CP_OVP bit 2 (SYSST 0x06) */
#define AW87XXX_PID_C1_CP_OVP_START_BIT (2)
#define AW87XXX_PID_C1_CP_OVP_BITS_LEN (1)
#define AW87XXX_PID_C1_CP_OVP_MASK \
(~(((1<<AW87XXX_PID_C1_CP_OVP_BITS_LEN)-1) << AW87XXX_PID_C1_CP_OVP_START_BIT))
#define AW87XXX_PID_C1_CP_OVP_DEFAULT (0x0)
#define AW87XXX_PID_C1_CP_OVP_DEFAULT_VALUE \
(AW87XXX_PID_C1_CP_OVP_DEFAULT << AW87XXX_PID_C1_CP_OVP_START_BIT)
/* PORN bit 1 (SYSST 0x06) */
#define AW87XXX_PID_C1_PORN_START_BIT (1)
#define AW87XXX_PID_C1_PORN_BITS_LEN (1)
#define AW87XXX_PID_C1_PORN_MASK \
(~(((1<<AW87XXX_PID_C1_PORN_BITS_LEN)-1) << AW87XXX_PID_C1_PORN_START_BIT))
#define AW87XXX_PID_C1_PORN_DEFAULT (0x0)
#define AW87XXX_PID_C1_PORN_DEFAULT_VALUE \
(AW87XXX_PID_C1_PORN_DEFAULT << AW87XXX_PID_C1_PORN_START_BIT)
/* default value of SYSST (0x06) */
/* #define AW87XXX_PID_C1_SYSST_DEFAULT (0x50) */
/* SYSINT (0x07) detail */
/* UVLOI bit 7 (SYSINT 0x07) */
#define AW87XXX_PID_C1_UVLOI_START_BIT (7)
#define AW87XXX_PID_C1_UVLOI_BITS_LEN (1)
#define AW87XXX_PID_C1_UVLOI_MASK \
(~(((1<<AW87XXX_PID_C1_UVLOI_BITS_LEN)-1) << AW87XXX_PID_C1_UVLOI_START_BIT))
#define AW87XXX_PID_C1_UVLOI_DEFAULT (0x0)
#define AW87XXX_PID_C1_UVLOI_DEFAULT_VALUE \
(AW87XXX_PID_C1_UVLOI_DEFAULT << AW87XXX_PID_C1_UVLOI_START_BIT)
/* OTNI bit 6 (SYSINT 0x07) */
#define AW87XXX_PID_C1_OTNI_START_BIT (6)
#define AW87XXX_PID_C1_OTNI_BITS_LEN (1)
#define AW87XXX_PID_C1_OTNI_MASK \
(~(((1<<AW87XXX_PID_C1_OTNI_BITS_LEN)-1) << AW87XXX_PID_C1_OTNI_START_BIT))
#define AW87XXX_PID_C1_OTNI_DEFAULT (0x1)
#define AW87XXX_PID_C1_OTNI_DEFAULT_VALUE \
(AW87XXX_PID_C1_OTNI_DEFAULT << AW87XXX_PID_C1_OTNI_START_BIT)
/* OC_FLAGI bit 5 (SYSINT 0x07) */
#define AW87XXX_PID_C1_OC_FLAGI_START_BIT (5)
#define AW87XXX_PID_C1_OC_FLAGI_BITS_LEN (1)
#define AW87XXX_PID_C1_OC_FLAGI_MASK \
(~(((1<<AW87XXX_PID_C1_OC_FLAGI_BITS_LEN)-1) << AW87XXX_PID_C1_OC_FLAGI_START_BIT))
#define AW87XXX_PID_C1_OC_FLAGI_DEFAULT (0x0)
#define AW87XXX_PID_C1_OC_FLAGI_DEFAULT_VALUE \
(AW87XXX_PID_C1_OC_FLAGI_DEFAULT << AW87XXX_PID_C1_OC_FLAGI_START_BIT)
/* ADAP_CPI bit 4 (SYSINT 0x07) */
#define AW87XXX_PID_C1_ADAP_CPI_START_BIT (4)
#define AW87XXX_PID_C1_ADAP_CPI_BITS_LEN (1)
#define AW87XXX_PID_C1_ADAP_CPI_MASK \
(~(((1<<AW87XXX_PID_C1_ADAP_CPI_BITS_LEN)-1) << AW87XXX_PID_C1_ADAP_CPI_START_BIT))
#define AW87XXX_PID_C1_ADAP_CPI_DEFAULT (0x1)
#define AW87XXX_PID_C1_ADAP_CPI_DEFAULT_VALUE \
(AW87XXX_PID_C1_ADAP_CPI_DEFAULT << AW87XXX_PID_C1_ADAP_CPI_START_BIT)
/* STARTOKI bit 3 (SYSINT 0x07) */
#define AW87XXX_PID_C1_STARTOKI_START_BIT (3)
#define AW87XXX_PID_C1_STARTOKI_BITS_LEN (1)
#define AW87XXX_PID_C1_STARTOKI_MASK \
(~(((1<<AW87XXX_PID_C1_STARTOKI_BITS_LEN)-1) << AW87XXX_PID_C1_STARTOKI_START_BIT))
#define AW87XXX_PID_C1_STARTOKI_DEFAULT (0x0)
#define AW87XXX_PID_C1_STARTOKI_DEFAULT_VALUE \
(AW87XXX_PID_C1_STARTOKI_DEFAULT << AW87XXX_PID_C1_STARTOKI_START_BIT)
/* CP_OVPI bit 2 (SYSINT 0x07) */
#define AW87XXX_PID_C1_CP_OVPI_START_BIT (2)
#define AW87XXX_PID_C1_CP_OVPI_BITS_LEN (1)
#define AW87XXX_PID_C1_CP_OVPI_MASK \
(~(((1<<AW87XXX_PID_C1_CP_OVPI_BITS_LEN)-1) << AW87XXX_PID_C1_CP_OVPI_START_BIT))
#define AW87XXX_PID_C1_CP_OVPI_DEFAULT (0x0)
#define AW87XXX_PID_C1_CP_OVPI_DEFAULT_VALUE \
(AW87XXX_PID_C1_CP_OVPI_DEFAULT << AW87XXX_PID_C1_CP_OVPI_START_BIT)
/* PORNI bit 1 (SYSINT 0x07) */
#define AW87XXX_PID_C1_PORNI_START_BIT (1)
#define AW87XXX_PID_C1_PORNI_BITS_LEN (1)
#define AW87XXX_PID_C1_PORNI_MASK \
(~(((1<<AW87XXX_PID_C1_PORNI_BITS_LEN)-1) << AW87XXX_PID_C1_PORNI_START_BIT))
#define AW87XXX_PID_C1_PORNI_DEFAULT (0x0)
#define AW87XXX_PID_C1_PORNI_DEFAULT_VALUE \
(AW87XXX_PID_C1_PORNI_DEFAULT << AW87XXX_PID_C1_PORNI_START_BIT)
/* default value of SYSINT (0x07) */
/* #define AW87XXX_PID_C1_SYSINT_DEFAULT (0x50) */
/* detail information of registers end */
#endif /* #ifndef __AW87XXX_PID_C1_REG_H__ */

1758
sound/soc/codecs/aw87xxx/aw87xxx_pid_c2_reg.h Normal file
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File diff suppressed because it is too large Load Diff

281
sound/soc/codecs/aw87xxx/aw_acf_bin.c
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@ -1,5 +1,5 @@
/*
* aw_acf_bin.c
// SPDX-License-Identifier: GPL-2.0
/* aw87xxx_acf_bin.c
*
* Copyright (c) 2021 AWINIC Technology CO., LTD
*
@ -12,7 +12,7 @@
*/
#include <linux/module.h>
#include <asm/uaccess.h>
#include <linux/uaccess.h>
#include <linux/delay.h>
#include <linux/slab.h>
#include <linux/kernel.h>
@ -26,6 +26,52 @@
#include "aw_log.h"
#include "aw_bin_parse.h"
/*************************************************************************
*
*Table corresponding to customized profile ids to profile names
*
*************************************************************************/
enum aw_customers_profile_id {
AW_CTOS_PROFILE_OFF = 0,
AW_CTOS_PROFILE_MUSIC,
AW_CTOS_PROFILE_VOICE,
AW_CTOS_PROFILE_VOIP,
AW_CTOS_PROFILE_RINGTONE,
AW_CTOS_PROFILE_RINGTONE_HS,
AW_CTOS_PROFILE_LOWPOWER,
AW_CTOS_PROFILE_BYPASS,
AW_CTOS_PROFILE_MMI,
AW_CTOS_PROFILE_FM,
AW_CTOS_PROFILE_NOTIFICATION,
AW_CTOS_PROFILE_RECEIVER,
AW_CTOS_PROFILE_MAX,
};
static char *g_ctos_profile_name[AW_PROFILE_MAX] = {
[AW_CTOS_PROFILE_OFF] = "Off",
[AW_CTOS_PROFILE_MUSIC] = "Music",
[AW_CTOS_PROFILE_VOICE] = "Voice",
[AW_CTOS_PROFILE_VOIP] = "Voip",
[AW_CTOS_PROFILE_RINGTONE] = "Ringtone",
[AW_CTOS_PROFILE_RINGTONE_HS] = "Ringtone_hs",
[AW_CTOS_PROFILE_LOWPOWER] = "Lowpower",
[AW_CTOS_PROFILE_BYPASS] = "Bypass",
[AW_CTOS_PROFILE_MMI] = "Mmi",
[AW_CTOS_PROFILE_FM] = "Fm",
[AW_CTOS_PROFILE_NOTIFICATION] = "Notification",
[AW_CTOS_PROFILE_RECEIVER] = "Receiver",
};
char *aw87xxx_ctos_get_prof_name(int profile_id)
{
if (profile_id < 0 || profile_id >= AW_CTOS_PROFILE_MAX)
return NULL;
else
return g_ctos_profile_name[profile_id];
}
static char *g_profile_name[] = {"Music", "Voice", "Voip",
"Ringtone", "Ringtone_hs", "Lowpower", "Bypass", "Mmi",
"Fm", "Notification", "Receiver", "Off"};
@ -132,7 +178,6 @@ static int aw_check_data_size_v_0_0_0_1(struct device *dev,
AW_DEV_LOGE(dev, "acf dde[%d].data_size[%d],dev_name[%s],data_type[%d], data_size check failed",
i, acf_dde[i].data_size, acf_dde[i].dev_name,
acf_dde[i].data_type);
return -EINVAL;
}
data_size += acf_dde[i].data_size;
}
@ -412,7 +457,7 @@ static int aw_parse_reg_with_hdr(struct device *dev, uint8_t *data,
aw_bin->info.len = data_len;
memcpy(aw_bin->info.data, data, data_len);
ret = aw_parsing_bin_file(aw_bin);
ret = aw87xxx_parsing_bin_file(aw_bin);
if (ret < 0) {
AW_DEV_LOGE(dev, "parse bin failed");
goto parse_bin_failed;
@ -440,6 +485,51 @@ parse_bin_failed:
return ret;
}
static int aw_dev_prof_parse_multi_bin(struct device *dev,
uint8_t *data, uint32_t data_len, struct aw_prof_desc *prof_desc)
{
struct aw_bin *aw_bin = NULL;
int i;
int ret;
aw_bin = devm_kzalloc(dev,
data_len + sizeof(struct aw_bin), GFP_KERNEL);
if (aw_bin == NULL)
return -ENOMEM;
aw_bin->info.len = data_len;
memcpy(aw_bin->info.data, data, data_len);
ret = aw87xxx_parsing_bin_file(aw_bin);
if (ret < 0) {
AW_DEV_LOGE(dev, "parse bin failed");
goto parse_bin_failed;
}
for (i = 0; i < aw_bin->all_bin_parse_num; i++) {
if (aw_bin->header_info[i].bin_data_type == DATA_TYPE_REGISTER) {
prof_desc->data_container.len = aw_bin->header_info[i].valid_data_len;
prof_desc->data_container.data = data + aw_bin->header_info[i].valid_data_addr;
break;
}
}
if (i == aw_bin->all_bin_parse_num) {
AW_DEV_LOGE(dev, "the expected data type was not found,pls check");
goto parse_bin_failed;
}
devm_kfree(dev, aw_bin);
aw_bin = NULL;
prof_desc->prof_st = AW_PROFILE_OK;
return 0;
parse_bin_failed:
devm_kfree(dev, aw_bin);
aw_bin = NULL;
return ret;
}
static int aw_parse_monitor_config(struct device *dev,
char *monitor_data, uint32_t data_len)
{
@ -450,7 +540,7 @@ static int aw_parse_monitor_config(struct device *dev,
return -EBFONT;
}
ret = aw_monitor_bin_parse(dev, monitor_data, data_len);
ret = aw87xxx_monitor_bin_parse(dev, monitor_data, data_len);
if (ret < 0) {
AW_DEV_LOGE(dev, "monitor_config parse failed");
return ret;
@ -484,7 +574,7 @@ static int aw_check_product_name_v_0_0_0_1(struct device *dev,
int i = 0;
for (i = 0; i < acf_info->product_cnt; i++) {
if (0 == strcmp(acf_info->product_tab[i], prof_hdr->dev_name)) {
if (strcmp(acf_info->product_tab[i], prof_hdr->dev_name) == 0) {
AW_DEV_LOGD(dev, "bin_dev_name:%s",
prof_hdr->dev_name);
return 0;
@ -533,11 +623,15 @@ static int aw_parse_data_by_sec_type_v_0_0_0_1(struct device *dev,
prof_hdr->data_size,
profile_prof_desc);
break;
case AW_MONITOR:
AW_DEV_LOGD(dev, "parse monitor type data enter");
ret = aw_parse_monitor_config(dev, cfg_data,
prof_hdr->data_size);
break;
case AW_BIN_TYPE_MUTLBIN:
snprintf(profile_prof_desc->dev_name, sizeof(prof_hdr->dev_name),
"%s", prof_hdr->dev_name);
profile_prof_desc->prof_name = aw_get_prof_name(prof_hdr->dev_profile);
AW_DEV_LOGD(dev, "parse mutil type data enter,profile=%s",
aw_get_prof_name(prof_hdr->dev_profile));
ret = aw_dev_prof_parse_multi_bin(dev, cfg_data,
prof_hdr->data_size,
profile_prof_desc);
}
return ret;
@ -549,7 +643,7 @@ static int aw_parse_dev_type_v_0_0_0_1(struct device *dev,
int i = 0;
int ret = -1;
int sec_num = 0;
uint8_t soft_off_enable = acf_info->aw_dev->soft_off_enable;
char *cfg_data = NULL;
struct aw_prof_desc *prof_desc = NULL;
struct aw_acf_dde *acf_dde =
(struct aw_acf_dde *)(acf_info->fw_data + acf_info->acf_hdr.ddt_offset);
@ -567,16 +661,14 @@ static int aw_parse_dev_type_v_0_0_0_1(struct device *dev,
ret = aw_check_data_type_is_monitor_v_0_0_0_1(dev, &acf_dde[i]);
if (ret == 0) {
prof_desc = NULL;
} else {
cfg_data = acf_info->fw_data + acf_dde[i].data_offset;
ret = aw_parse_monitor_config(dev, cfg_data, acf_dde[i].data_size);
if (ret < 0)
return ret;
continue;
}
prof_desc = &all_prof_info->prof_desc[acf_dde[i].dev_profile];
}
if (acf_dde[i].dev_profile == AW_PROFILE_OFF && !soft_off_enable) {
AW_DEV_LOGE(dev, "profile off is not allowed");
return -EINVAL;
}
ret = aw_parse_data_by_sec_type_v_0_0_0_1(dev, acf_info, &acf_dde[i],
prof_desc);
if (ret < 0) {
@ -602,7 +694,7 @@ static int aw_parse_default_type_v_0_0_0_1(struct device *dev,
int i = 0;
int ret = -1;
int sec_num = 0;
uint8_t soft_off_enable = acf_info->aw_dev->soft_off_enable;
char *cfg_data = NULL;
struct aw_prof_desc *prof_desc = NULL;
struct aw_acf_dde *acf_dde =
(struct aw_acf_dde *)(acf_info->fw_data + acf_info->acf_hdr.ddt_offset);
@ -619,16 +711,14 @@ static int aw_parse_default_type_v_0_0_0_1(struct device *dev,
ret = aw_check_data_type_is_monitor_v_0_0_0_1(dev, &acf_dde[i]);
if (ret == 0) {
prof_desc = NULL;
} else {
cfg_data = acf_info->fw_data + acf_dde[i].data_offset;
ret = aw_parse_monitor_config(dev, cfg_data, acf_dde[i].data_size);
if (ret < 0)
return ret;
continue;
}
prof_desc = &all_prof_info->prof_desc[acf_dde[i].dev_profile];
}
if (acf_dde[i].dev_profile == AW_PROFILE_OFF && !soft_off_enable) {
AW_DEV_LOGE(dev, "profile off is not allowed");
return -EINVAL;
}
ret = aw_parse_data_by_sec_type_v_0_0_0_1(dev, acf_info, &acf_dde[i],
prof_desc);
if (ret < 0) {
@ -654,23 +744,14 @@ static int aw_get_prof_count_v_0_0_0_1(struct device *dev,
{
int i = 0;
int prof_count = 0;
uint8_t soft_off_enable = acf_info->aw_dev->soft_off_enable;
struct aw_prof_desc *prof_desc = all_prof_info->prof_desc;
for (i = 0; i < AW_PROFILE_MAX; i++) {
if (i == AW_PROFILE_OFF) {
if (!soft_off_enable && prof_desc[i].prof_st == AW_PROFILE_OK) {
AW_DEV_LOGE(dev, "profile_off is not allowed");
return -EINVAL;
} else if (soft_off_enable && prof_desc[i].prof_st == AW_PROFILE_WAIT) {
AW_DEV_LOGE(dev, "profile [Off] is necessary,but not found");
return -EINVAL;
} else {
if (prof_desc[i].prof_st == AW_PROFILE_OK) {
prof_count++;
}
} else {
if (prof_desc[i].prof_st == AW_PROFILE_OK)
} else if (i == AW_PROFILE_OFF) {
prof_count++;
AW_DEV_LOGI(dev, "not found profile [Off], set default");
}
}
@ -683,7 +764,6 @@ static int aw_set_prof_off_info_v_0_0_0_1(struct device *dev,
struct aw_all_prof_info *all_prof_info,
int index)
{
uint8_t soft_off_enable = acf_info->aw_dev->soft_off_enable;
struct aw_prof_desc *prof_desc = all_prof_info->prof_desc;
struct aw_prof_info *prof_info = &acf_info->prof_info;
@ -693,20 +773,17 @@ static int aw_set_prof_off_info_v_0_0_0_1(struct device *dev,
return -EINVAL;
}
if (soft_off_enable && prof_desc[AW_PROFILE_OFF].prof_st == AW_PROFILE_OK) {
if (prof_desc[AW_PROFILE_OFF].prof_st == AW_PROFILE_OK) {
prof_info->prof_desc[index] = prof_desc[AW_PROFILE_OFF];
AW_DEV_LOGI(dev, "product=[%s]----profile=[%s]",
prof_info->prof_desc[index].dev_name,
aw_get_prof_name(AW_PROFILE_OFF));
} else if (!soft_off_enable) {
} else {
memset(&prof_info->prof_desc[index].data_container, 0,
sizeof(struct aw_data_container));
prof_info->prof_desc[index].prof_st = AW_PROFILE_WAIT;
prof_info->prof_desc[index].prof_name = aw_get_prof_name(AW_PROFILE_OFF);
AW_DEV_LOGI(dev, "set default power_off with no data to profile");
} else {
AW_DEV_LOGE(dev, "not init default power_off config");
return -EINVAL;
}
return 0;
@ -807,7 +884,7 @@ static int aw_parse_acf_v_0_0_0_1(struct device *dev,
ret = aw_get_vaild_prof_v_0_0_0_1(dev, acf_info, &all_prof_info);
if (ret < 0) {
aw_acf_profile_free(dev, acf_info);
aw87xxx_acf_profile_free(dev, acf_info);
AW_DEV_LOGE(dev, "hdr_cersion[0x%x] parse failed",
acf_info->acf_hdr.hdr_version);
return ret;
@ -815,7 +892,7 @@ static int aw_parse_acf_v_0_0_0_1(struct device *dev,
ret = aw_set_prof_name_list_v_0_0_0_1(dev, acf_info);
if (ret < 0) {
aw_acf_profile_free(dev, acf_info);
aw87xxx_acf_profile_free(dev, acf_info);
AW_DEV_LOGE(dev, "creat prof_id_and_name_list failed");
return ret;
}
@ -835,7 +912,7 @@ static int aw_check_product_name_v_1_0_0_0(struct device *dev,
int i = 0;
for (i = 0; i < acf_info->product_cnt; i++) {
if (0 == strcmp(acf_info->product_tab[i], prof_hdr->dev_name)) {
if (strcmp(acf_info->product_tab[i], prof_hdr->dev_name) == 0) {
AW_DEV_LOGI(dev, "bin_dev_name:%s", prof_hdr->dev_name);
return 0;
}
@ -844,14 +921,6 @@ static int aw_check_product_name_v_1_0_0_0(struct device *dev,
return -ENXIO;
}
static void aw_print_prof_off_name_can_support_v_1_0_0_0(struct device *dev)
{
int i = 0;
for (i = 0; i < AW_POWER_OFF_NAME_SUPPORT_COUNT; i++)
AW_DEV_LOGI(dev, "support prof_off_name have string:[%s]", g_power_off_name[i]);
}
static int aw_get_dde_type_info_v_1_0_0_0(struct device *dev,
struct acf_bin_info *acf_info)
{
@ -888,7 +957,6 @@ static int aw_get_dde_type_info_v_1_0_0_0(struct device *dev,
static int aw_parse_get_dev_type_prof_count_v_1_0_0_0(struct device *dev,
struct acf_bin_info *acf_info)
{
uint8_t soft_off_enable = acf_info->aw_dev->soft_off_enable;
struct aw_acf_hdr *acf_hdr = (struct aw_acf_hdr *)acf_info->fw_data;
struct aw_acf_dde_v_1_0_0_0 *acf_dde =
(struct aw_acf_dde_v_1_0_0_0 *)(acf_info->fw_data + acf_hdr->ddt_offset);
@ -899,7 +967,8 @@ static int aw_parse_get_dev_type_prof_count_v_1_0_0_0(struct device *dev,
for (i = 0; i < acf_hdr->dde_num; ++i) {
if (((acf_dde[i].data_type == AW_BIN_TYPE_REG) ||
(acf_dde[i].data_type == AW_BIN_TYPE_HDR_REG)) &&
(acf_dde[i].data_type == AW_BIN_TYPE_HDR_REG) ||
(acf_dde[i].data_type == AW_BIN_TYPE_MUTLBIN)) &&
((acf_info->aw_dev->i2c_bus == acf_dde[i].dev_bus) &&
(acf_info->aw_dev->i2c_addr == acf_dde[i].dev_addr)) &&
(acf_info->aw_dev->chipid == acf_dde[i].chip_id)) {
@ -909,17 +978,10 @@ static int aw_parse_get_dev_type_prof_count_v_1_0_0_0(struct device *dev,
continue;
ret = aw_check_prof_str_is_off(acf_dde[i].dev_profile_str);
if (ret == 0) {
if (ret == 0)
found_off_prof_flag = AW_PROFILE_OK;
if (soft_off_enable) {
count++;
} else {
AW_DEV_LOGE(dev, "profile_off is not allowed");
return -EINVAL;
}
} else {
count++;
}
}
}
@ -928,13 +990,7 @@ static int aw_parse_get_dev_type_prof_count_v_1_0_0_0(struct device *dev,
return -EINVAL;
}
if (!found_off_prof_flag && soft_off_enable) {
AW_DEV_LOGE(dev, "profile power off is necessary,but not found");
aw_print_prof_off_name_can_support_v_1_0_0_0(dev);
return -EINVAL;
}
if (!found_off_prof_flag && !soft_off_enable) {
if (!found_off_prof_flag) {
count++;
AW_DEV_LOGD(dev, "set no config power off profile in count");
}
@ -947,7 +1003,6 @@ static int aw_parse_get_dev_type_prof_count_v_1_0_0_0(struct device *dev,
static int aw_parse_get_default_type_prof_count_v_1_0_0_0(struct device *dev,
struct acf_bin_info *acf_info)
{
uint8_t soft_off_enable = acf_info->aw_dev->soft_off_enable;
struct aw_acf_hdr *acf_hdr = (struct aw_acf_hdr *)acf_info->fw_data;
struct aw_acf_dde_v_1_0_0_0 *acf_dde =
(struct aw_acf_dde_v_1_0_0_0 *)(acf_info->fw_data + acf_hdr->ddt_offset);
@ -958,7 +1013,8 @@ static int aw_parse_get_default_type_prof_count_v_1_0_0_0(struct device *dev,
for (i = 0; i < acf_hdr->dde_num; ++i) {
if (((acf_dde[i].data_type == AW_BIN_TYPE_REG) ||
(acf_dde[i].data_type == AW_BIN_TYPE_HDR_REG)) &&
(acf_dde[i].data_type == AW_BIN_TYPE_HDR_REG) ||
(acf_dde[i].data_type == AW_BIN_TYPE_MUTLBIN)) &&
(acf_info->dev_index == acf_dde[i].dev_index) &&
(acf_info->aw_dev->chipid == acf_dde[i].chip_id)) {
@ -967,17 +1023,10 @@ static int aw_parse_get_default_type_prof_count_v_1_0_0_0(struct device *dev,
continue;
ret = aw_check_prof_str_is_off(acf_dde[i].dev_profile_str);
if (ret == 0) {
if (ret == 0)
found_off_prof_flag = AW_PROFILE_OK;
if (soft_off_enable) {
count++;
} else {
AW_DEV_LOGE(dev, "profile_off is not allowed");
return -EINVAL;
}
} else {
count++;
}
}
}
@ -986,13 +1035,7 @@ static int aw_parse_get_default_type_prof_count_v_1_0_0_0(struct device *dev,
return -EINVAL;
}
if (!found_off_prof_flag && soft_off_enable) {
AW_DEV_LOGE(dev, "profile power off is necessary,but not found");
aw_print_prof_off_name_can_support_v_1_0_0_0(dev);
return -EINVAL;
}
if (!found_off_prof_flag && !soft_off_enable) {
if (!found_off_prof_flag) {
count++;
AW_DEV_LOGD(dev, "set no config power off profile in count");
}
@ -1044,7 +1087,8 @@ static int aw_parse_dev_type_prof_name_v_1_0_0_0(struct device *dev,
for (i = 0; i < acf_hdr->dde_num; ++i) {
if (((acf_dde[i].data_type == AW_BIN_TYPE_REG) ||
(acf_dde[i].data_type == AW_BIN_TYPE_HDR_REG)) &&
(acf_dde[i].data_type == AW_BIN_TYPE_HDR_REG) ||
(acf_dde[i].data_type == AW_BIN_TYPE_MUTLBIN)) &&
(acf_info->aw_dev->i2c_bus == acf_dde[i].dev_bus) &&
(acf_info->aw_dev->i2c_addr == acf_dde[i].dev_addr) &&
(acf_info->aw_dev->chipid == acf_dde[i].chip_id)) {
@ -1081,7 +1125,8 @@ static int aw_parse_default_type_prof_name_v_1_0_0_0(struct device *dev,
for (i = 0; i < acf_hdr->dde_num; ++i) {
if (((acf_dde[i].data_type == AW_BIN_TYPE_REG) ||
(acf_dde[i].data_type == AW_BIN_TYPE_HDR_REG)) &&
(acf_dde[i].data_type == AW_BIN_TYPE_HDR_REG) ||
(acf_dde[i].data_type == AW_BIN_TYPE_MUTLBIN)) &&
(acf_info->dev_index == acf_dde[i].dev_index) &&
(acf_info->aw_dev->chipid == acf_dde[i].chip_id)) {
if (list_index > prof_info->count) {
@ -1152,6 +1197,11 @@ static int aw_search_prof_index_from_list_v_1_0_0_0(struct device *dev,
int count = acf_info->prof_info.count;
char (*prof_name_list)[AW_PROFILE_STR_MAX] = acf_info->prof_info.prof_name_list;
if (prof_name_list == NULL) {
AW_DEV_LOGE(dev, "the declared prof_name_list pointer is empty");
return -ENOMEM;
}
for (i = 0; i < count; i++) {
if (!strncmp(prof_name_list[i], prof_hdr->dev_profile_str, AW_PROFILE_STR_MAX)) {
*prof_desc = &(acf_info->prof_info.prof_desc[i]);
@ -1198,6 +1248,16 @@ static int aw_parse_data_by_sec_type_v_1_0_0_0(struct device *dev,
ret = aw_parse_reg_with_hdr(dev, cfg_data,
prof_hdr->data_size, prof_desc);
break;
case AW_BIN_TYPE_MUTLBIN:
snprintf(prof_desc->dev_name, sizeof(prof_hdr->dev_name),
"%s", prof_hdr->dev_name);
AW_DEV_LOGI(dev, "parse multi type data enter,product=[%s],prof_id=[%d],prof_name=[%s]",
prof_hdr->dev_name, prof_hdr->dev_profile,
prof_hdr->dev_profile_str);
prof_desc->prof_name = prof_hdr->dev_profile_str;
ret = aw_dev_prof_parse_multi_bin(dev, cfg_data,
prof_hdr->data_size,
prof_desc);
}
return ret;
@ -1313,13 +1373,12 @@ static int aw_parse_by_hdr_v_1_0_0_0(struct device *dev,
static int aw_set_prof_off_info_v_1_0_0_0(struct device *dev,
struct acf_bin_info *acf_info)
{
uint8_t soft_off_enable = acf_info->aw_dev->soft_off_enable;
struct aw_prof_info *prof_info = &acf_info->prof_info;
int i = 0;
int ret = 0;
for (i = 0; i < prof_info->count; ++i) {
if (!(prof_info->prof_desc[i].prof_st) && !soft_off_enable) {
if (!(prof_info->prof_desc[i].prof_st)) {
snprintf(prof_info->prof_name_list[i], AW_PROFILE_STR_MAX, "%s",
g_power_off_name[0]);
prof_info->prof_desc[i].prof_name = prof_info->prof_name_list[i];
@ -1391,7 +1450,7 @@ static int aw_parse_acf_v_1_0_0_0(struct device *dev,
*acf parse API
*
*************************************************************************/
void aw_acf_profile_free(struct device *dev, struct acf_bin_info *acf_info)
void aw87xxx_acf_profile_free(struct device *dev, struct acf_bin_info *acf_info)
{
struct aw_prof_info *prof_info = &acf_info->prof_info;
@ -1415,7 +1474,7 @@ void aw_acf_profile_free(struct device *dev, struct acf_bin_info *acf_info)
}
}
int aw_acf_parse(struct device *dev, struct acf_bin_info *acf_info)
int aw87xxx_acf_parse(struct device *dev, struct acf_bin_info *acf_info)
{
int ret = 0;
@ -1445,7 +1504,7 @@ int aw_acf_parse(struct device *dev, struct acf_bin_info *acf_info)
return ret;
}
struct aw_prof_desc *aw_acf_get_prof_desc_form_name(struct device *dev,
struct aw_prof_desc *aw87xxx_acf_get_prof_desc_form_name(struct device *dev,
struct acf_bin_info *acf_info, char *profile_name)
{
int i = 0;
@ -1476,7 +1535,7 @@ struct aw_prof_desc *aw_acf_get_prof_desc_form_name(struct device *dev,
return prof_desc;
}
int aw_acf_get_prof_index_form_name(struct device *dev,
int aw87xxx_acf_get_prof_index_form_name(struct device *dev,
struct acf_bin_info *acf_info, char *profile_name)
{
int i = 0;
@ -1498,7 +1557,7 @@ int aw_acf_get_prof_index_form_name(struct device *dev,
return -EINVAL;
}
char *aw_acf_get_prof_name_form_index(struct device *dev,
char *aw87xxx_acf_get_prof_name_form_index(struct device *dev,
struct acf_bin_info *acf_info, int index)
{
struct aw_prof_info *prof_info = &acf_info->prof_info;
@ -1517,7 +1576,7 @@ char *aw_acf_get_prof_name_form_index(struct device *dev,
}
int aw_acf_get_profile_count(struct device *dev,
int aw87xxx_acf_get_profile_count(struct device *dev,
struct acf_bin_info *acf_info)
{
struct aw_prof_info *prof_info = &acf_info->prof_info;
@ -1527,14 +1586,14 @@ int aw_acf_get_profile_count(struct device *dev,
return -EINVAL;
}
if (prof_info->count > 0) {
if (prof_info->count > 0)
return prof_info->count;
}
return -EINVAL;
}
char *aw_acf_get_prof_off_name(struct device *dev,
char *aw87xxx_acf_get_prof_off_name(struct device *dev,
struct acf_bin_info *acf_info)
{
int i = 0;
@ -1555,7 +1614,7 @@ char *aw_acf_get_prof_off_name(struct device *dev,
return NULL;
}
void aw_acf_init(struct aw_device *aw_dev, struct acf_bin_info *acf_info, int index)
void aw87xxx_acf_init(struct aw_device *aw_dev, struct acf_bin_info *acf_info, int index)
{
acf_info->load_count = 0;

39
sound/soc/codecs/aw87xxx/aw_acf_bin.h
View File

@ -1,7 +1,20 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/* SPDX-License-Identifier: GPL-2.0
*
* aw87xxx_acf_bin.h aw87xxx pa module
*
* Copyright (c) 2021 AWINIC Technology CO., LTD
*
* Author: Barry <zhaozhongbo@awinic.com>
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*
*/
#ifndef __AW_ACF_BIN_H__
#define __AW_ACF_BIN_H__
#ifndef __AW87XXX_ACF_BIN_H__
#define __AW87XXX_ACF_BIN_H__
#include "aw_device.h"
@ -173,23 +186,21 @@ struct acf_bin_info {
struct aw_prof_info prof_info;
};
void aw_acf_profile_free(struct device *dev,
char *aw87xxx_ctos_get_prof_name(int profile_id);
void aw87xxx_acf_profile_free(struct device *dev,
struct acf_bin_info *acf_info);
int aw_acf_parse(struct device *dev, struct acf_bin_info *acf_info);
struct aw_prof_desc *aw_acf_get_prof_desc_form_name(struct device *dev,
int aw87xxx_acf_parse(struct device *dev, struct acf_bin_info *acf_info);
struct aw_prof_desc *aw87xxx_acf_get_prof_desc_form_name(struct device *dev,
struct acf_bin_info *acf_info, char *profile_name);
int aw_acf_get_prof_index_form_name(struct device *dev,
int aw87xxx_acf_get_prof_index_form_name(struct device *dev,
struct acf_bin_info *acf_info, char *profile_name);
char *aw_acf_get_prof_name_form_index(struct device *dev,
char *aw87xxx_acf_get_prof_name_form_index(struct device *dev,
struct acf_bin_info *acf_info, int index);
int aw_acf_get_profile_count(struct device *dev,
int aw87xxx_acf_get_profile_count(struct device *dev,
struct acf_bin_info *acf_info);
int aw_acf_check_profile_is_off(struct device *dev,
struct acf_bin_info *acf_info, char *profile_name);
char *aw_acf_get_prof_off_name(struct device *dev,
char *aw87xxx_acf_get_prof_off_name(struct device *dev,
struct acf_bin_info *acf_info);
void aw_acf_init(struct aw_device *aw_dev, struct acf_bin_info *acf_info, int index);
void aw87xxx_acf_init(struct aw_device *aw_dev, struct acf_bin_info *acf_info, int index);
#endif

140
sound/soc/codecs/aw87xxx/aw_bin_parse.c
View File

@ -1,8 +1,10 @@
/*
* aw_bin_parse.c
// SPDX-License-Identifier: GPL-2.0
/* aw87xxx_bin_parse.c
*
* Copyright (c) 2020 AWINIC Technology CO., LTD
*
* Author: Barry <zhaozhongbo@awinic.com>
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
@ -22,7 +24,7 @@
#include <linux/interrupt.h>
#include <linux/debugfs.h>
#include <linux/miscdevice.h>
#include <asm/uaccess.h>
#include <linux/uaccess.h>
#include <linux/regmap.h>
#include <linux/timer.h>
#include <linux/workqueue.h>
@ -37,58 +39,30 @@
#define DEBUG_LOG_LEVEL
#ifdef DEBUG_LOG_LEVEL
#define DBG(fmt, arg...) do {\
printk("AWINIC_BIN %s,line= %d,"fmt, __func__, __LINE__, ##arg);\
} while (0)
#define DBG_ERR(fmt, arg...) do {\
printk("AWINIC_BIN_ERR %s,line= %d,"fmt, __func__, __LINE__, ##arg);\
} while (0)
#define DBG(fmt, arg...) \
pr_debug("AWINIC_BIN %s,line= %d,"fmt, __func__, __LINE__, ##arg)
#define DBG_ERR(fmt, arg...) \
pr_err("AWINIC_BIN_ERR %s,line= %d,"fmt, __func__, __LINE__, ##arg)
#else
#define DBG(fmt, arg...) do {} while (0)
#define DBG_ERR(fmt, arg...) do {} while (0)
#endif
#define printing_data_code
typedef unsigned short int aw_uint16;
typedef unsigned long int aw_uint32;
#define BigLittleSwap16(A) ((((aw_uint16)(A) & 0xff00) >> 8) | \
(((aw_uint16)(A) & 0x00ff) << 8))
#define BigLittleSwap32(A) ((((aw_uint32)(A) & 0xff000000) >> 24) | \
(((aw_uint32)(A) & 0x00ff0000) >> 8) | \
(((aw_uint32)(A) & 0x0000ff00) << 8) | \
(((aw_uint32)(A) & 0x000000ff) << 24))
/**
*
* Interface function
*
* return value:
* value = 0 :success;
* value = -1 :check bin header version
* value = -2 :check bin data type
* value = -3 :check sum or check bin data len error
* value = -4 :check data version
* value = -5 :check register num
* value = -6 :check dsp reg num
* value = -7 :check soc app num
* value = -8 :bin is NULL point
*
**/
static int aw_parse_bin_header_1_0_0(struct aw_bin *bin);
/********************************************************
*
* check sum data
*
********************************************************/
int aw_check_sum(struct aw_bin *bin, int bin_num)
static int aw_check_sum(struct aw_bin *bin, int bin_num)
{
unsigned int i = 0;
unsigned int sum_data = 0;
unsigned int check_sum = 0;
char *p_check_sum = NULL;
unsigned char *p_check_sum = NULL;
DBG("enter\n");
@ -112,32 +86,33 @@ int aw_check_sum(struct aw_bin *bin, int bin_num)
p_check_sum = NULL;
DBG_ERR("aw_bin_parse check sum or check bin data len error\n");
DBG_ERR("aw_bin_parse bin_num=%d, check_sum = 0x%x, sum_data = 0x%x\n", bin_num, check_sum, sum_data);
return -3;
return -EINVAL;
}
p_check_sum = NULL;
return 0;
}
int aw_check_data_version(struct aw_bin *bin, int bin_num)
static int aw_check_data_version(struct aw_bin *bin, int bin_num)
{
int i = 0;
DBG("enter\n");
for (i = DATA_VERSION_V1; i < DATA_VERSION_MAX; i++) {
if (bin->header_info[bin_num].bin_data_ver == i) {
if (bin->header_info[bin_num].bin_data_ver == i)
return 0;
}
}
DBG_ERR("aw_bin_parse Unrecognized this bin data version\n");
return -4;
return -EINVAL;
}
int aw_check_register_num_v1(struct aw_bin *bin, int bin_num)
static int aw_check_register_num_v1(struct aw_bin *bin, int bin_num)
{
unsigned int check_register_num = 0;
unsigned int parse_register_num = 0;
char *p_check_sum = NULL;
unsigned char *p_check_sum = NULL;
DBG("enter\n");
@ -157,7 +132,7 @@ int aw_check_register_num_v1(struct aw_bin *bin, int bin_num)
p_check_sum = NULL;
DBG_ERR("aw_bin_parse register num is error\n");
DBG_ERR("aw_bin_parse bin_num=%d, parse_register_num = 0x%x, check_register_num = 0x%x\n", bin_num, parse_register_num, check_register_num);
return -5;
return -EINVAL;
}
bin->header_info[bin_num].reg_num = parse_register_num;
bin->header_info[bin_num].valid_data_len =
@ -168,11 +143,11 @@ int aw_check_register_num_v1(struct aw_bin *bin, int bin_num)
return 0;
}
int aw_check_dsp_reg_num_v1(struct aw_bin *bin, int bin_num)
static int aw_check_dsp_reg_num_v1(struct aw_bin *bin, int bin_num)
{
unsigned int check_dsp_reg_num = 0;
unsigned int parse_dsp_reg_num = 0;
char *p_check_sum = NULL;
unsigned char *p_check_sum = NULL;
DBG("enter\n");
@ -195,7 +170,7 @@ int aw_check_dsp_reg_num_v1(struct aw_bin *bin, int bin_num)
p_check_sum = NULL;
DBG_ERR("aw_bin_parse dsp reg num is error\n");
DBG_ERR("aw_bin_parse bin_num=%d, parse_dsp_reg_num = 0x%x, check_dsp_reg_num = 0x%x\n", bin_num, parse_dsp_reg_num, check_dsp_reg_num);
return -6;
return -EINVAL;
}
bin->header_info[bin_num].download_addr =
GET_32_DATA(*(p_check_sum + 3), *(p_check_sum + 2),
@ -209,11 +184,11 @@ int aw_check_dsp_reg_num_v1(struct aw_bin *bin, int bin_num)
return 0;
}
int aw_check_soc_app_num_v1(struct aw_bin *bin, int bin_num)
static int aw_check_soc_app_num_v1(struct aw_bin *bin, int bin_num)
{
unsigned int check_soc_app_num = 0;
unsigned int parse_soc_app_num = 0;
char *p_check_sum = NULL;
unsigned char *p_check_sum = NULL;
DBG("enter\n");
@ -235,7 +210,7 @@ int aw_check_soc_app_num_v1(struct aw_bin *bin, int bin_num)
p_check_sum = NULL;
DBG_ERR("aw_bin_parse soc app num is error\n");
DBG_ERR("aw_bin_parse bin_num=%d, parse_soc_app_num = 0x%x, check_soc_app_num = 0x%x\n", bin_num, parse_soc_app_num, check_soc_app_num);
return -7;
return -EINVAL;
}
bin->header_info[bin_num].reg_num = parse_soc_app_num;
bin->header_info[bin_num].download_addr =
@ -254,10 +229,11 @@ int aw_check_soc_app_num_v1(struct aw_bin *bin, int bin_num)
***bin header 1_0_0
***
************************/
void aw_get_single_bin_header_1_0_0(struct aw_bin *bin)
static void aw_get_single_bin_header_1_0_0(struct aw_bin *bin)
{
int i;
DBG("enter %s\n", __func__);
int i = 0;
DBG("enter\n");
bin->header_info[bin->all_bin_parse_num].header_len = 60;
bin->header_info[bin->all_bin_parse_num].check_sum =
GET_32_DATA(*(bin->p_addr + 3), *(bin->p_addr + 2),
@ -298,12 +274,13 @@ void aw_get_single_bin_header_1_0_0(struct aw_bin *bin)
bin->all_bin_parse_num += 1;
}
int aw_parse_each_of_multi_bins_1_0_0(unsigned int bin_num, int bin_serial_num,
static int aw_parse_each_of_multi_bins_1_0_0(unsigned int bin_num, int bin_serial_num,
struct aw_bin *bin)
{
int ret = 0;
unsigned int bin_start_addr = 0;
unsigned int valid_data_len = 0;
DBG("aw_bin_parse enter multi bin branch -- %s\n", __func__);
if (!bin_serial_num) {
bin_start_addr = GET_32_DATA(*(bin->p_addr + 67),
@ -330,26 +307,27 @@ int aw_parse_each_of_multi_bins_1_0_0(unsigned int bin_num, int bin_serial_num,
}
/* Get the number of bins in multi bins, and set a for loop, loop processing each bin data */
int aw_get_multi_bin_header_1_0_0(struct aw_bin *bin)
static int aw_get_multi_bin_header_1_0_0(struct aw_bin *bin)
{
int i = 0;
int ret = 0;
unsigned int bin_num = 0;
DBG("aw_bin_parse enter multi bin branch -- %s\n", __func__);
bin_num = GET_32_DATA(*(bin->p_addr + 63),
*(bin->p_addr + 62),
*(bin->p_addr + 61), *(bin->p_addr + 60));
if (bin->multi_bin_parse_num == 1) {
if (bin->multi_bin_parse_num == 1)
bin->header_info[bin->all_bin_parse_num].valid_data_addr = 60;
}
aw_get_single_bin_header_1_0_0(bin);
for (i = 0; i < bin_num; i++) {
DBG("aw_bin_parse enter multi bin for is %d\n", i);
ret = aw_parse_each_of_multi_bins_1_0_0(bin_num, i, bin);
if (ret < 0) {
if (ret < 0)
return ret;
}
}
return 0;
}
@ -365,11 +343,12 @@ int aw_get_multi_bin_header_1_0_0(struct aw_bin *bin)
according to the bin number to process the frame header information of each bin separately
*
********************************************************/
int aw_parse_bin_header_1_0_0(struct aw_bin *bin)
static int aw_parse_bin_header_1_0_0(struct aw_bin *bin)
{
int ret = 0;
unsigned int bin_data_type;
DBG("enter %s\n", __func__);
DBG("enter\n");
bin_data_type = GET_32_DATA(*(bin->p_addr + 11),
*(bin->p_addr + 10),
*(bin->p_addr + 9), *(bin->p_addr + 8));
@ -379,17 +358,16 @@ int aw_parse_bin_header_1_0_0(struct aw_bin *bin)
case DATA_TYPE_DSP_REG:
case DATA_TYPE_SOC_APP:
/* Divided into two processing methods,
one is single bin processing,
and the other is single bin processing in multi bin */
* one is single bin processing,
* and the other is single bin processing in multi bin
*/
DBG("aw_bin_parse enter single bin branch\n");
bin->single_bin_parse_num += 1;
DBG("%s bin->single_bin_parse_num is %d\n", __func__,
bin->single_bin_parse_num);
if (!bin->multi_bin_parse_num) {
bin->header_info[bin->
all_bin_parse_num].valid_data_addr =
60;
}
if (!bin->multi_bin_parse_num)
bin->header_info[bin->all_bin_parse_num].valid_data_addr = 60;
aw_get_single_bin_header_1_0_0(bin);
break;
case DATA_TYPE_MULTI_BINS:
@ -399,13 +377,14 @@ int aw_parse_bin_header_1_0_0(struct aw_bin *bin)
DBG("%s bin->multi_bin_parse_num is %d\n", __func__,
bin->multi_bin_parse_num);
ret = aw_get_multi_bin_header_1_0_0(bin);
if (ret < 0) {
if (ret < 0)
return ret;
}
break;
default:
DBG_ERR("aw_bin_parse Unrecognized this bin data type\n");
return -2;
DBG("aw_bin_parse Unrecognized this bin data type 0x%x\n",
bin_data_type);
break;
}
return 0;
}
@ -423,18 +402,19 @@ static int aw_check_bin_header_version(struct aw_bin *bin)
DBG("aw_bin_parse header_version 0x%x\n", header_version);
/* Write data to the corresponding structure array
according to different formats of the bin frame header version */
* according to different formats of the bin frame header version
*/
switch (header_version) {
case HEADER_VERSION_1_0_0:
ret = aw_parse_bin_header_1_0_0(bin);
return ret;
default:
DBG_ERR("aw_bin_parse Unrecognized this bin header version\n");
return -1;
return -EINVAL;
}
}
int aw_parsing_bin_file(struct aw_bin *bin)
int aw87xxx_parsing_bin_file(struct aw_bin *bin)
{
int i = 0;
int ret = 0;
@ -442,7 +422,7 @@ int aw_parsing_bin_file(struct aw_bin *bin)
DBG("aw_bin_parse code version:%s\n", AWINIC_CODE_VERSION);
if (!bin) {
DBG_ERR("aw_bin_parse bin is NULL\n");
return -8;
return -EINVAL;
}
bin->p_addr = bin->info.data;
bin->all_bin_parse_num = 0;

22
sound/soc/codecs/aw87xxx/aw_bin_parse.h
View File

@ -1,7 +1,18 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/* SPDX-License-Identifier: GPL-2.0
* aw87xxx_bin_parse.h
*
* Copyright (c) 2020 AWINIC Technology CO., LTD
*
* Author: Barry <zhaozhongbo@awinic.com>
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*/
#ifndef __AW_BIN_PARSE_H__
#define __AW_BIN_PARSE_H__
#ifndef __AW87XXX_BIN_PARSE_H__
#define __AW87XXX_BIN_PARSE_H__
#define NULL ((void *)0)
#define GET_32_DATA(w, x, y, z) ((unsigned int)(((w) << 24) | ((x) << 16) | ((y) << 8) | (z)))
@ -63,7 +74,7 @@ struct bin_container {
};
struct aw_bin {
char *p_addr; /* Offset pointer (backward offset pointer to obtain frame header information and important information) */
unsigned char *p_addr; /* Offset pointer (backward offset pointer to obtain frame header information and important information) */
unsigned int all_bin_parse_num; /* The number of all bin files */
unsigned int multi_bin_parse_num; /* The number of single bin files */
unsigned int single_bin_parse_num; /* The number of multiple bin files */
@ -71,6 +82,5 @@ struct aw_bin {
struct bin_container info; /* Obtained bin file data that needs to be parsed */
};
extern int aw_parsing_bin_file(struct aw_bin *bin);
int aw_parse_bin_header_1_0_0(struct aw_bin *bin);
extern int aw87xxx_parsing_bin_file(struct aw_bin *bin);
#endif

611
sound/soc/codecs/aw87xxx/aw_device.c
View File

@ -1,5 +1,5 @@
/*
* aw_device.c aw87xxx pa module
// SPDX-License-Identifier: GPL-2.0
/* aw87xxx_device.c aw87xxx pa module
*
* Copyright (c) 2021 AWINIC Technology CO., LTD
*
@ -25,6 +25,7 @@
#include <linux/timer.h>
#include "aw87xxx.h"
#include "aw_device.h"
#include "aw_dsp.h"
#include "aw_log.h"
#include "aw87xxx_pid_9b_reg.h"
#include "aw87xxx_pid_18_reg.h"
@ -33,54 +34,123 @@
#include "aw87xxx_pid_59_5x9_reg.h"
#include "aw87xxx_pid_5a_reg.h"
#include "aw87xxx_pid_76_reg.h"
#include "aw87xxx_pid_60_reg.h"
#include "aw87xxx_pid_c1_reg.h"
#include "aw87xxx_pid_c2_reg.h"
#ifdef AW_ALGO_AUTH_DSP
static DEFINE_MUTEX(g_algo_auth_dsp_lock);
int g_algo_auth_st;
#endif
/*************************************************************************
* aw87xxx variable
************************************************************************/
const char *g_aw_pid_9b_product[] = {
"aw87319",
"AW87319",
};
const char *g_aw_pid_18_product[] = {
"aw87358",
"AW87358",
};
const char *g_aw_pid_39_product[] = {
"aw87329",
"AW87329",
"aw87339",
"AW87339",
"aw87349",
"AW87349",
};
const char *g_aw_pid_59_3x9_product[] = {
"aw87359",
"AW87359",
"aw87389",
"AW87389",
};
const char *g_aw_pid_59_5x9_product[] = {
"aw87509",
"AW87509",
"aw87519",
"AW87519",
"aw87529",
"AW87529",
"aw87539",
"AW87539",
};
const char *g_aw_pid_5a_product[] = {
"aw87549",
"AW87549",
"aw87559",
"AW87559",
"aw87569",
"AW87569",
"aw87579",
"AW87579",
"aw81509",
"AW81509",
"aw87579G",
"AW87579G",
};
const char *g_aw_pid_76_product[] = {
"aw87390",
"AW87390",
"aw87320",
"AW87320",
"aw87401",
"AW87401",
"aw87360",
"AW87360",
"aw87390G",
"AW87390G",
};
static int aw_dev_get_chipid(struct aw_device *aw_dev);
const char *g_aw_pid_60_product[] = {
"aw87560",
"AW87560",
"aw87561",
"AW87561",
"aw87562",
"AW87562",
"aw87501",
"AW87501",
"aw87550",
"AW87550",
};
const char *g_aw_pid_c1_product[] = {
"aw87391",
"AW87391",
"aw87392",
"AW87392",
};
const char *g_aw_pid_c2_product[] = {
"aw87565",
"AW87565",
"aw87566",
"AW87566",
"aw81564",
"AW81564",
"aw87567",
"AW87567",
"aw87568",
"AW87568",
};
static int aw87xxx_dev_get_chipid(struct aw_device *aw_dev);
/***************************************************************************
*
* reading and writing of I2C bus
*
***************************************************************************/
int aw_dev_i2c_write_byte(struct aw_device *aw_dev,
int aw87xxx_dev_i2c_write_byte(struct aw_device *aw_dev,
uint8_t reg_addr, uint8_t reg_data)
{
int ret = -1;
@ -101,7 +171,7 @@ int aw_dev_i2c_write_byte(struct aw_device *aw_dev,
return ret;
}
int aw_dev_i2c_read_byte(struct aw_device *aw_dev,
int aw87xxx_dev_i2c_read_byte(struct aw_device *aw_dev,
uint8_t reg_addr, uint8_t *reg_data)
{
int ret = -1;
@ -123,7 +193,7 @@ int aw_dev_i2c_read_byte(struct aw_device *aw_dev,
return ret;
}
int aw_dev_i2c_read_msg(struct aw_device *aw_dev,
int aw87xxx_dev_i2c_read_msg(struct aw_device *aw_dev,
uint8_t reg_addr, uint8_t *data_buf, uint32_t data_len)
{
int ret = -1;
@ -155,20 +225,20 @@ int aw_dev_i2c_read_msg(struct aw_device *aw_dev,
return 0;
}
int aw_dev_i2c_write_bits(struct aw_device *aw_dev,
int aw87xxx_dev_i2c_write_bits(struct aw_device *aw_dev,
uint8_t reg_addr, uint8_t mask, uint8_t reg_data)
{
int ret = -1;
unsigned char reg_val = 0;
ret = aw_dev_i2c_read_byte(aw_dev, reg_addr, &reg_val);
ret = aw87xxx_dev_i2c_read_byte(aw_dev, reg_addr, &reg_val);
if (ret < 0) {
AW_DEV_LOGE(aw_dev->dev, "i2c read error, ret=%d", ret);
return ret;
}
reg_val &= mask;
reg_val |= reg_data;
ret = aw_dev_i2c_write_byte(aw_dev, reg_addr, reg_val);
reg_val |= (reg_data & (~mask));
ret = aw87xxx_dev_i2c_write_byte(aw_dev, reg_addr, reg_val);
if (ret < 0) {
AW_DEV_LOGE(aw_dev->dev, "i2c write error, ret=%d", ret);
return ret;
@ -182,7 +252,7 @@ int aw_dev_i2c_write_bits(struct aw_device *aw_dev,
* aw87xxx device update profile data to registers
*
************************************************************************/
static int aw_dev_reg_update(struct aw_device *aw_dev,
static int aw87xxx_dev_reg_update(struct aw_device *aw_dev,
struct aw_data_container *profile_data)
{
int i = 0;
@ -200,7 +270,15 @@ static int aw_dev_reg_update(struct aw_device *aw_dev,
//AW_DEV_LOGI(aw_dev->dev, "reg=0x%02x, val = 0x%02x",
// profile_data->data[i], profile_data->data[i + 1]);
ret = aw_dev_i2c_write_byte(aw_dev, profile_data->data[i],
/*delay ms*/
if (profile_data->data[i] == AW87XXX_DELAY_REG_ADDR) {
AW_DEV_LOGI(aw_dev->dev, "delay %d ms", profile_data->data[i + 1]);
usleep_range(profile_data->data[i + 1] * AW87XXX_REG_DELAY_TIME,
profile_data->data[i + 1] * AW87XXX_REG_DELAY_TIME + 10);
continue;
}
ret = aw87xxx_dev_i2c_write_byte(aw_dev, profile_data->data[i],
profile_data->data[i + 1]);
if (ret < 0)
return ret;
@ -209,7 +287,7 @@ static int aw_dev_reg_update(struct aw_device *aw_dev,
return 0;
}
static void aw_dev_reg_mute_bits_set(struct aw_device *aw_dev,
static void aw87xxx_dev_reg_mute_bits_set(struct aw_device *aw_dev,
uint8_t *reg_val, bool enable)
{
if (enable) {
@ -221,12 +299,58 @@ static void aw_dev_reg_mute_bits_set(struct aw_device *aw_dev,
}
}
static int aw87xxx_dev_reg_update_mute(struct aw_device *aw_dev,
struct aw_data_container *profile_data)
{
int i = 0;
int ret = -1;
uint8_t reg_val = 0;
if (profile_data == NULL)
return -EINVAL;
if (aw_dev->hwen_status == AW_DEV_HWEN_OFF) {
AW_DEV_LOGE(aw_dev->dev, "hwen is off,can not update reg");
return -EINVAL;
}
if (aw_dev->mute_desc.mask == AW_DEV_REG_INVALID_MASK) {
AW_DEV_LOGE(aw_dev->dev, "mute ctrl mask invalid");
return -EINVAL;
}
for (i = 0; i < profile_data->len; i = i + 2) {
AW_DEV_LOGI(aw_dev->dev, "reg=0x%02x, val = 0x%02x",
profile_data->data[i], profile_data->data[i + 1]);
/*delay ms*/
if (profile_data->data[i] == AW87XXX_DELAY_REG_ADDR) {
AW_DEV_LOGI(aw_dev->dev, "delay %d ms", profile_data->data[i + 1]);
usleep_range(profile_data->data[i + 1] * AW87XXX_REG_DELAY_TIME,
profile_data->data[i + 1] * AW87XXX_REG_DELAY_TIME + 10);
continue;
}
reg_val = profile_data->data[i + 1];
if (profile_data->data[i] == aw_dev->mute_desc.addr) {
aw87xxx_dev_reg_mute_bits_set(aw_dev, &reg_val, true);
AW_DEV_LOGD(aw_dev->dev, "change mute_mask, val = 0x%02x",
reg_val);
}
ret = aw87xxx_dev_i2c_write_byte(aw_dev, profile_data->data[i], reg_val);
if (ret < 0)
return ret;
}
return 0;
}
/************************************************************************
*
* aw87xxx device hadware and soft contols
*
************************************************************************/
static bool aw_dev_gpio_is_valid(struct aw_device *aw_dev)
static bool aw87xxx_dev_gpio_is_valid(struct aw_device *aw_dev)
{
if (gpio_is_valid(aw_dev->rst_gpio))
return true;
@ -234,14 +358,14 @@ static bool aw_dev_gpio_is_valid(struct aw_device *aw_dev)
return false;
}
void aw_dev_hw_pwr_ctrl(struct aw_device *aw_dev, bool enable)
void aw87xxx_dev_hw_pwr_ctrl(struct aw_device *aw_dev, bool enable)
{
if (aw_dev->hwen_status == AW_DEV_HWEN_INVALID) {
AW_DEV_LOGD(aw_dev->dev, "product not have reset-pin,hardware pwd control invalid");
return;
}
if (enable) {
if (aw_dev_gpio_is_valid(aw_dev)) {
if (aw87xxx_dev_gpio_is_valid(aw_dev)) {
gpio_set_value_cansleep(aw_dev->rst_gpio, AW_GPIO_LOW_LEVEL);
mdelay(2);
gpio_set_value_cansleep(aw_dev->rst_gpio, AW_GPIO_HIGHT_LEVEL);
@ -252,7 +376,7 @@ void aw_dev_hw_pwr_ctrl(struct aw_device *aw_dev, bool enable)
AW_DEV_LOGI(aw_dev->dev, "hw already power on");
}
} else {
if (aw_dev_gpio_is_valid(aw_dev)) {
if (aw87xxx_dev_gpio_is_valid(aw_dev)) {
gpio_set_value_cansleep(aw_dev->rst_gpio, AW_GPIO_LOW_LEVEL);
mdelay(2);
aw_dev->hwen_status = AW_DEV_HWEN_OFF;
@ -263,18 +387,18 @@ void aw_dev_hw_pwr_ctrl(struct aw_device *aw_dev, bool enable)
}
}
int aw_dev_mute_ctrl(struct aw_device *aw_dev, bool enable)
static int aw87xxx_dev_mute_ctrl(struct aw_device *aw_dev, bool enable)
{
int ret = 0;
if (enable) {
ret = aw_dev_i2c_write_bits(aw_dev, aw_dev->mute_desc.addr,
ret = aw87xxx_dev_i2c_write_bits(aw_dev, aw_dev->mute_desc.addr,
aw_dev->mute_desc.mask, aw_dev->mute_desc.enable);
if (ret < 0)
return ret;
AW_DEV_LOGI(aw_dev->dev, "set mute down");
} else {
ret = aw_dev_i2c_write_bits(aw_dev, aw_dev->mute_desc.addr,
ret = aw87xxx_dev_i2c_write_bits(aw_dev, aw_dev->mute_desc.addr,
aw_dev->mute_desc.mask, aw_dev->mute_desc.disable);
if (ret < 0)
return ret;
@ -284,7 +408,7 @@ int aw_dev_mute_ctrl(struct aw_device *aw_dev, bool enable)
return 0;
}
void aw_dev_soft_reset(struct aw_device *aw_dev)
void aw87xxx_dev_soft_reset(struct aw_device *aw_dev)
{
int i = 0;
int ret = -1;
@ -313,11 +437,11 @@ void aw_dev_soft_reset(struct aw_device *aw_dev)
return;
}
for (i = 0; i < soft_rst->len / sizeof(uint8_t); i += 2) {
for (i = 0; i < soft_rst->len; i += 2) {
AW_DEV_LOGD(aw_dev->dev, "softrst_reg=0x%02x, val = 0x%02x",
soft_rst->access[i], soft_rst->access[i + 1]);
ret = aw_dev_i2c_write_byte(aw_dev, soft_rst->access[i],
ret = aw87xxx_dev_i2c_write_byte(aw_dev, soft_rst->access[i],
soft_rst->access[i + 1]);
if (ret < 0) {
AW_DEV_LOGE(aw_dev->dev, "write failed,ret = %d,cnt=%d",
@ -329,7 +453,7 @@ void aw_dev_soft_reset(struct aw_device *aw_dev)
}
int aw_dev_default_pwr_off(struct aw_device *aw_dev,
int aw87xxx_dev_default_pwr_off(struct aw_device *aw_dev,
struct aw_data_container *profile_data)
{
int ret = 0;
@ -341,19 +465,22 @@ int aw_dev_default_pwr_off(struct aw_device *aw_dev,
}
if (aw_dev->soft_off_enable && profile_data) {
ret = aw_dev_reg_update(aw_dev, profile_data);
ret = aw87xxx_dev_reg_update(aw_dev, profile_data);
if (ret < 0) {
AW_DEV_LOGE(aw_dev->dev, "update profile[Off] fw config failed");
goto reg_off_update_failed;
}
}
aw_dev_hw_pwr_ctrl(aw_dev, false);
if (aw_dev->chipid == AW_DEV_CHIPID_C2)
mdelay(5);
aw87xxx_dev_hw_pwr_ctrl(aw_dev, false);
AW_DEV_LOGD(aw_dev->dev, "down");
return 0;
reg_off_update_failed:
aw_dev_hw_pwr_ctrl(aw_dev, false);
aw87xxx_dev_hw_pwr_ctrl(aw_dev, false);
return ret;
}
@ -364,15 +491,18 @@ reg_off_update_failed:
*
************************************************************************/
int aw_dev_default_pwr_on(struct aw_device *aw_dev,
int aw87xxx_dev_default_pwr_on(struct aw_device *aw_dev,
struct aw_data_container *profile_data)
{
int ret = 0;
/*hw power on*/
aw_dev_hw_pwr_ctrl(aw_dev, true);
aw87xxx_dev_hw_pwr_ctrl(aw_dev, true);
ret = aw_dev_reg_update(aw_dev, profile_data);
if (aw_dev->chipid == AW_DEV_CHIPID_C2)
mdelay(3);
ret = aw87xxx_dev_reg_update(aw_dev, profile_data);
if (ret < 0)
return ret;
@ -384,7 +514,7 @@ int aw_dev_default_pwr_on(struct aw_device *aw_dev,
* aw87xxx chip esd status check
*
****************************************************************************/
int aw_dev_esd_reg_status_check(struct aw_device *aw_dev)
int aw87xxx_dev_esd_reg_status_check(struct aw_device *aw_dev)
{
int ret;
unsigned char reg_val = 0;
@ -397,7 +527,7 @@ int aw_dev_esd_reg_status_check(struct aw_device *aw_dev)
return -EINVAL;
}
ret = aw_dev_i2c_read_byte(aw_dev, esd_desc->first_update_reg_addr,
ret = aw87xxx_dev_i2c_read_byte(aw_dev, esd_desc->first_update_reg_addr,
&reg_val);
if (ret < 0) {
AW_DEV_LOGE(aw_dev->dev, "read reg 0x%02x failed",
@ -416,7 +546,7 @@ int aw_dev_esd_reg_status_check(struct aw_device *aw_dev)
return 0;
}
int aw_dev_check_reg_is_rec_mode(struct aw_device *aw_dev)
int aw87xxx_dev_check_reg_is_rec_mode(struct aw_device *aw_dev)
{
int ret;
unsigned char reg_val = 0;
@ -427,7 +557,7 @@ int aw_dev_check_reg_is_rec_mode(struct aw_device *aw_dev)
return -EINVAL;
}
ret = aw_dev_i2c_read_byte(aw_dev, rec_desc->addr, &reg_val);
ret = aw87xxx_dev_i2c_read_byte(aw_dev, rec_desc->addr, &reg_val);
if (ret < 0) {
AW_DEV_LOGE(aw_dev->dev, "read reg 0x%02x failed",
rec_desc->addr);
@ -452,6 +582,140 @@ int aw_dev_check_reg_is_rec_mode(struct aw_device *aw_dev)
return 0;
}
/****************************************************************************
*
* aw87xxx algo_encryption
*
****************************************************************************/
int aw87xxx_dev_get_encrypted_value(struct aw_device *aw_dev,
unsigned int in, unsigned int *out)
{
int ret = 0;
struct aw_auth_desc *desc = &aw_dev->auth_desc;
uint8_t out_l = 0;
uint8_t out_h = 0;
if ((desc->reg_in_l == AW_REG_NONE) || (desc->reg_in_h == AW_REG_NONE) ||
(desc->reg_out_l == AW_REG_NONE) || (desc->reg_out_h == AW_REG_NONE)) {
AW_DEV_LOGD(aw_dev->dev, "Missing encryption register");
return -EINVAL;
}
ret = aw87xxx_dev_i2c_write_byte(aw_dev, desc->reg_in_l, (in & 0xFF));
if (ret < 0)
return ret;
ret = aw87xxx_dev_i2c_write_byte(aw_dev, desc->reg_in_h, ((in >> 8) & 0xFF));
if (ret < 0)
return ret;
ret = aw87xxx_dev_i2c_read_byte(aw_dev, desc->reg_out_l, &out_l);
if (ret < 0)
return ret;
ret = aw87xxx_dev_i2c_read_byte(aw_dev, desc->reg_out_h, &out_h);
*out = out_l | (out_h << 8);
return ret;
}
int aw87xxx_dev_algo_auth_mode(struct aw_device *aw_dev, struct algo_auth_data *algo_data)
{
int ret = 0;
unsigned int encrypted_out = 0;
AW_DEV_LOGD(aw_dev->dev, "algo auth mode: %d", algo_data->auth_mode);
aw_dev->auth_desc.auth_mode = algo_data->auth_mode;
aw_dev->auth_desc.random = algo_data->random;
aw_dev->auth_desc.chip_id = AW_ALGO_AUTH_MAGIC_ID;
aw_dev->auth_desc.check_result = algo_data->check_result;
switch (algo_data->auth_mode) {
case AW_ALGO_AUTH_MODE_MAGIC_ID:
aw_dev->auth_desc.reg_crc = algo_data->reg_crc;
break;
case AW_ALGO_AUTH_MODE_REG_CRC:
ret = aw87xxx_dev_get_encrypted_value(aw_dev, algo_data->random, &encrypted_out);
if (ret < 0)
AW_DEV_LOGE(aw_dev->dev, "get encrypted value failed");
aw_dev->auth_desc.reg_crc = encrypted_out;
break;
default:
AW_DEV_LOGE(aw_dev->dev, "unsupport auth mode[%d]", algo_data->auth_mode);
ret = -EINVAL;
}
return ret;
}
#ifdef AW_ALGO_AUTH_DSP
int aw87xxx_dev_algo_auth_dsp_mode(struct aw_device *aw_dev, struct algo_auth_data *algo_data)
{
int ret = 0;
unsigned int encrypted_out = 0;
AW_DEV_LOGD(aw_dev->dev, "algo auth mode: %d", algo_data->auth_mode);
algo_data->chip_id = AW_ALGO_AUTH_MAGIC_ID;
if (algo_data->auth_mode == AW_ALGO_AUTH_MODE_REG_CRC) {
ret = aw87xxx_dev_get_encrypted_value(aw_dev, algo_data->random, &encrypted_out);
if (ret < 0)
AW_DEV_LOGE(aw_dev->dev, "get encrypted value failed");
algo_data->reg_crc = encrypted_out;
}
return ret;
}
void aw87xxx_dev_algo_authentication(struct aw_device *aw_dev)
{
int ret = 0;
struct algo_auth_data algo_data;
mutex_lock(&g_algo_auth_dsp_lock);
AW_DEV_LOGD(aw_dev->dev, "g_algo_auth_st=%d", g_algo_auth_st);
if (g_algo_auth_st == AW_ALGO_AUTH_OK) {
AW_DEV_LOGD(aw_dev->dev, "algo auth complete");
goto exit;
}
ret = aw87xxx_dsp_get_algo_auth_data(aw_dev, (char *)&algo_data, sizeof(struct algo_auth_data));
if (ret < 0)
goto exit;
ret = aw87xxx_dev_algo_auth_dsp_mode(aw_dev, &algo_data);
if (ret < 0)
goto exit;
ret = aw87xxx_dsp_set_algo_auth_data(aw_dev, (char *)&algo_data, sizeof(struct algo_auth_data));
if (ret < 0)
goto exit;
g_algo_auth_st = AW_ALGO_AUTH_OK;
AW_DEV_LOGI(aw_dev->dev, "g_algo_auth_st=%d", g_algo_auth_st);
AW_DEV_LOGD(aw_dev->dev, "mode=%d,reg_crc=0x%x,random=0x%x,id=0x%x,res=%d",
algo_data.auth_mode, algo_data.reg_crc, algo_data.random,
algo_data.chip_id, algo_data.check_result);
exit:
mutex_unlock(&g_algo_auth_dsp_lock);
}
#endif
static void aw_dev_auth_reg_none(struct aw_device *aw_dev)
{
/*encryption info*/
aw_dev->auth_desc.reg_in_l = AW_REG_NONE;
aw_dev->auth_desc.reg_in_h = AW_REG_NONE;
aw_dev->auth_desc.reg_out_l = AW_REG_NONE;
aw_dev->auth_desc.reg_out_h = AW_REG_NONE;
}
/****************************************************************************
*
@ -480,7 +744,7 @@ static int aw_dev_pid_9b_reg_update(struct aw_device *aw_dev,
AW_DEV_LOGE(aw_dev->dev, "reg_config count of bin is error,can not update reg");
return -EINVAL;
}
ret = aw_dev_i2c_write_byte(aw_dev, AW87XXX_PID_9B_ENCRYPTION_REG,
ret = aw87xxx_dev_i2c_write_byte(aw_dev, AW87XXX_PID_9B_ENCRYPTION_REG,
AW87XXX_PID_9B_ENCRYPTION_BOOST_OUTPUT_SET);
if (ret < 0)
return ret;
@ -488,14 +752,22 @@ static int aw_dev_pid_9b_reg_update(struct aw_device *aw_dev,
for (i = 1; i < AW_PID_9B_BIN_REG_CFG_COUNT; i++) {
AW_DEV_LOGI(aw_dev->dev, "reg=0x%02x, val = 0x%02x",
i, profile_data->data[i]);
/*delay ms*/
if (profile_data->data[i] == AW87XXX_DELAY_REG_ADDR) {
AW_DEV_LOGI(aw_dev->dev, "delay %d ms", profile_data->data[i + 1]);
usleep_range(profile_data->data[i + 1] * AW87XXX_REG_DELAY_TIME,
profile_data->data[i + 1] * AW87XXX_REG_DELAY_TIME + 10);
continue;
}
reg_val = profile_data->data[i];
if (i == AW87XXX_PID_9B_SYSCTRL_REG) {
aw_dev_reg_mute_bits_set(aw_dev, &reg_val, true);
aw87xxx_dev_reg_mute_bits_set(aw_dev, &reg_val, true);
AW_DEV_LOGD(aw_dev->dev, "change mute_mask, val = 0x%02x",
reg_val);
}
ret = aw_dev_i2c_write_byte(aw_dev, i, reg_val);
ret = aw87xxx_dev_i2c_write_byte(aw_dev, i, reg_val);
if (ret < 0)
return ret;
}
@ -503,15 +775,15 @@ static int aw_dev_pid_9b_reg_update(struct aw_device *aw_dev,
return 0;
}
int aw_dev_pid_9b_pwr_on(struct aw_device *aw_dev, struct aw_data_container *data)
static int aw_dev_pid_9b_pwr_on(struct aw_device *aw_dev, struct aw_data_container *data)
{
int ret = 0;
/*hw power on*/
aw_dev_hw_pwr_ctrl(aw_dev, true);
aw87xxx_dev_hw_pwr_ctrl(aw_dev, true);
/* open the mute */
ret = aw_dev_mute_ctrl(aw_dev, true);
ret = aw87xxx_dev_mute_ctrl(aw_dev, true);
if (ret < 0)
return ret;
@ -521,7 +793,7 @@ int aw_dev_pid_9b_pwr_on(struct aw_device *aw_dev, struct aw_data_container *dat
return ret;
/* close the mute */
aw_dev_mute_ctrl(aw_dev, false);
ret = aw87xxx_dev_mute_ctrl(aw_dev, false);
if (ret < 0)
return ret;
@ -559,20 +831,24 @@ static void aw_dev_pid_9b_init(struct aw_device *aw_dev)
/* esd reg info */
aw_dev->esd_desc.first_update_reg_addr = AW87XXX_PID_9B_SYSCTRL_REG;
aw_dev->esd_desc.first_update_reg_val = AW87XXX_PID_9B_SYSCTRL_DEFAULT;
aw_dev->vol_desc.addr = AW_REG_NONE;
aw_dev_auth_reg_none(aw_dev);
}
static int aw_dev_pid_9a_init(struct aw_device *aw_dev)
{
int ret = 0;
ret = aw_dev_i2c_write_byte(aw_dev, AW87XXX_PID_9B_ENCRYPTION_REG,
ret = aw87xxx_dev_i2c_write_byte(aw_dev, AW87XXX_PID_9B_ENCRYPTION_REG,
AW87XXX_PID_9B_ENCRYPTION_BOOST_OUTPUT_SET);
if (ret < 0) {
AW_DEV_LOGE(aw_dev->dev, "write 0x64=0x2C error");
return -EINVAL;
}
ret = aw_dev_get_chipid(aw_dev);
ret = aw87xxx_dev_get_chipid(aw_dev);
if (ret < 0) {
AW_DEV_LOGE(aw_dev->dev, "read chipid is failed,ret=%d", ret);
return ret;
@ -582,7 +858,7 @@ static int aw_dev_pid_9a_init(struct aw_device *aw_dev)
AW_DEV_LOGI(aw_dev->dev, "product is pid_9B class");
aw_dev_pid_9b_init(aw_dev);
} else {
AW_DEV_LOGE(aw_dev->dev, "product is not pid_9B class, not support");
AW_DEV_LOGE(aw_dev->dev, "product is not pid_9B class，not support");
return -EINVAL;
}
@ -591,6 +867,71 @@ static int aw_dev_pid_9a_init(struct aw_device *aw_dev)
/********************** aw87xxx_pid_9b attributes end ***********************/
/********************** aw87xxx_pid_18 attributes ***************************/
static int aw_dev_pid_18_pwr_on(struct aw_device *aw_dev, struct aw_data_container *data)
{
int ret = 0;
/*hw power on*/
aw87xxx_dev_hw_pwr_ctrl(aw_dev, true);
/* open the mute */
ret = aw87xxx_dev_mute_ctrl(aw_dev, true);
if (ret < 0)
return ret;
/* Update scene parameters in mute mode */
ret = aw87xxx_dev_reg_update_mute(aw_dev, data);
if (ret < 0)
return ret;
/* close the mute */
ret = aw87xxx_dev_mute_ctrl(aw_dev, false);
if (ret < 0)
return ret;
return 0;
}
static void aw_dev_chipid_18_init(struct aw_device *aw_dev)
{
/* Product register permission info */
aw_dev->reg_max_addr = AW87XXX_PID_18_REG_MAX;
aw_dev->reg_access = aw87xxx_pid_18_reg_access;
aw_dev->mute_desc.addr = AW87XXX_PID_18_SYSCTRL_REG;
aw_dev->mute_desc.mask = AW87XXX_PID_18_REG_EN_SW_MASK;
aw_dev->mute_desc.enable = AW87XXX_PID_18_REG_EN_SW_DISABLE_VALUE;
aw_dev->mute_desc.disable = AW87XXX_PID_18_REG_EN_SW_ENABLE_VALUE;
aw_dev->ops.pwr_on_func = aw_dev_pid_18_pwr_on;
/* software reset control info */
aw_dev->soft_rst_desc.len = sizeof(aw87xxx_pid_18_softrst_access);
aw_dev->soft_rst_desc.access = aw87xxx_pid_18_softrst_access;
aw_dev->soft_rst_enable = AW_DEV_SOFT_RST_ENABLE;
/* Whether to allow register operation to power off */
aw_dev->soft_off_enable = AW_DEV_SOFT_OFF_ENABLE;
aw_dev->product_tab = g_aw_pid_18_product;
aw_dev->product_cnt = AW87XXX_PID_18_PRODUCT_MAX;
aw_dev->rec_desc.addr = AW87XXX_PID_18_SYSCTRL_REG;
aw_dev->rec_desc.disable = AW87XXX_PID_18_REG_REC_MODE_DISABLE;
aw_dev->rec_desc.enable = AW87XXX_PID_18_REG_REC_MODE_ENABLE;
aw_dev->rec_desc.mask = AW87XXX_PID_18_REG_REC_MODE_MASK;
/* esd reg info */
aw_dev->esd_desc.first_update_reg_addr = AW87XXX_PID_18_CLASSD_REG;
aw_dev->esd_desc.first_update_reg_val = AW87XXX_PID_18_CLASSD_DEFAULT;
aw_dev->ipeak_desc.reg = AW_REG_NONE;
aw_dev->vol_desc.addr = AW87XXX_PID_18_CPOC_REG;
aw_dev_auth_reg_none(aw_dev);
}
/********************** aw87xxx_pid_18 attributes end ***********************/
/********************** aw87xxx_pid_39 attributes ***************************/
static void aw_dev_chipid_39_init(struct aw_device *aw_dev)
{
@ -617,6 +958,11 @@ static void aw_dev_chipid_39_init(struct aw_device *aw_dev)
/* esd reg info */
aw_dev->esd_desc.first_update_reg_addr = AW87XXX_PID_39_REG_MODECTRL;
aw_dev->esd_desc.first_update_reg_val = AW87XXX_PID_39_MODECTRL_DEFAULT;
aw_dev->ipeak_desc.reg = AW_REG_NONE;
aw_dev->vol_desc.addr = AW87XXX_PID_39_REG_CPOVP;
aw_dev_auth_reg_none(aw_dev);
}
/********************* aw87xxx_pid_39 attributes end *************************/
@ -647,6 +993,11 @@ static void aw_dev_chipid_59_5x9_init(struct aw_device *aw_dev)
/* esd reg info */
aw_dev->esd_desc.first_update_reg_addr = AW87XXX_PID_59_5X9_REG_ENCR;
aw_dev->esd_desc.first_update_reg_val = AW87XXX_PID_59_5X9_ENCRY_DEFAULT;
aw_dev->ipeak_desc.reg = AW_REG_NONE;
aw_dev->vol_desc.addr = AW_REG_NONE;
aw_dev_auth_reg_none(aw_dev);
}
/******************* aw87xxx_pid_59_5x9 attributes end ***********************/
@ -676,6 +1027,11 @@ static void aw_dev_chipid_59_3x9_init(struct aw_device *aw_dev)
/* esd reg info */
aw_dev->esd_desc.first_update_reg_addr = AW87XXX_PID_59_3X9_REG_ENCR;
aw_dev->esd_desc.first_update_reg_val = AW87XXX_PID_59_3X9_ENCR_DEFAULT;
aw_dev->ipeak_desc.reg = AW_REG_NONE;
aw_dev->vol_desc.addr = AW87XXX_PID_59_3X9_REG_CPOVP;
aw_dev_auth_reg_none(aw_dev);
}
/******************* aw87xxx_pid_59_3x9 attributes end ***********************/
@ -705,8 +1061,16 @@ static void aw_dev_chipid_5a_init(struct aw_device *aw_dev)
/* esd reg info */
aw_dev->esd_desc.first_update_reg_addr = AW87XXX_PID_5A_REG_DFT3R_REG;
aw_dev->esd_desc.first_update_reg_val = AW87XXX_PID_5A_DFT3R_DEFAULT;
}
aw_dev->ipeak_desc.reg = AW87XXX_PID_5A_REG_BSTCPR2_REG;
aw_dev->ipeak_desc.mask = AW87XXX_PID_5A_REG_BST_IPEAK_MASK;
aw_dev->vol_desc.addr = AW_REG_NONE;
aw_dev_auth_reg_none(aw_dev);
}
/********************** aw87xxx_pid_5a attributes end ************************/
/********************** aw87xxx_pid_76 attributes ****************************/
static void aw_dev_chipid_76_init(struct aw_device *aw_dev)
{
/* Product register permission info */
@ -732,11 +1096,128 @@ static void aw_dev_chipid_76_init(struct aw_device *aw_dev)
/* esd reg info */
aw_dev->esd_desc.first_update_reg_addr = AW87XXX_PID_76_DFT_ADP1_REG;
aw_dev->esd_desc.first_update_reg_val = AW87XXX_PID_76_DFT_ADP1_CHECK;
aw_dev->ipeak_desc.reg = AW_REG_NONE;
aw_dev->vol_desc.addr = AW87XXX_PID_76_CPOVP_REG;
aw_dev_auth_reg_none(aw_dev);
}
/********************** aw87xxx_pid_76 attributes end ************************/
/********************** aw87xxx_pid_5a attributes end ************************/
/********************** aw87xxx_pid_60 attributes ****************************/
static void aw_dev_chipid_60_init(struct aw_device *aw_dev)
{
/* Product register permission info */
aw_dev->reg_max_addr = AW87XXX_PID_60_REG_MAX;
aw_dev->reg_access = aw87xxx_pid_60_reg_access;
static void aw_dev_chip_init(struct aw_device *aw_dev)
/* software reset control info */
aw_dev->soft_rst_desc.len = sizeof(aw87xxx_pid_60_softrst_access);
aw_dev->soft_rst_desc.access = aw87xxx_pid_60_softrst_access;
aw_dev->soft_rst_enable = AW_DEV_SOFT_RST_ENABLE;
/* software power off control info */
aw_dev->soft_off_enable = AW_DEV_SOFT_OFF_ENABLE;
aw_dev->product_tab = g_aw_pid_60_product;
aw_dev->product_cnt = AW87XXX_PID_60_PROFUCT_MAX;
aw_dev->rec_desc.addr = AW87XXX_PID_60_SYSCTRL_REG;
aw_dev->rec_desc.disable = AW87XXX_PID_60_RCV_MODE_DISABLE;
aw_dev->rec_desc.enable = AW87XXX_PID_60_RCV_MODE_ENABLE;
aw_dev->rec_desc.mask = AW87XXX_PID_60_RCV_MODE_MASK;
/* esd reg info */
aw_dev->esd_desc.first_update_reg_addr = AW87XXX_PID_60_NG3_REG;
aw_dev->esd_desc.first_update_reg_val = AW87XXX_PID_60_ESD_REG_VAL;
aw_dev->ipeak_desc.reg = AW_REG_NONE;
aw_dev->vol_desc.addr = AW_REG_NONE;
aw_dev_auth_reg_none(aw_dev);
}
/********************** aw87xxx_pid_60 attributes end ************************/
/********************** aw87xxx_pid_c1 attributes ****************************/
static void aw_dev_chipid_c1_init(struct aw_device *aw_dev)
{
/* Product register permission info */
aw_dev->reg_max_addr = AW87XXX_PID_C1_REG_MAX;
aw_dev->reg_access = aw87xxx_pid_c1_reg_access;
/* software reset control info */
aw_dev->soft_rst_desc.len = sizeof(aw87xxx_pid_c1_softrst_access);
aw_dev->soft_rst_desc.access = aw87xxx_pid_c1_softrst_access;
aw_dev->soft_rst_enable = AW_DEV_SOFT_RST_ENABLE;
/* software power off control info */
aw_dev->soft_off_enable = AW_DEV_SOFT_OFF_ENABLE;
aw_dev->product_tab = g_aw_pid_c1_product;
aw_dev->product_cnt = AW87XXX_PID_C1_PROFUCT_MAX;
aw_dev->rec_desc.addr = AW87XXX_PID_C1_SYSCTRL_REG;
aw_dev->rec_desc.disable = AW87XXX_PID_C1_EN_SPK_SPK_MODE_ENABLE;
aw_dev->rec_desc.enable = AW87XXX_PID_C1_EN_SPK_SPK_MODE_DISABLE;
aw_dev->rec_desc.mask = AW87XXX_PID_C1_EN_SPK_MASK;
/* esd reg info */
aw_dev->esd_desc.first_update_reg_addr = AW87XXX_PID_C1_DFT_THGEN1_REG;
aw_dev->esd_desc.first_update_reg_val = AW87XXX_PID_C1_DFT_THGEN1_CHECK;
aw_dev->vol_desc.addr = AW_REG_NONE;
aw_dev->ipeak_desc.reg = AW_REG_NONE;
/*encryption info*/
aw_dev->auth_desc.reg_in_l = AW87XXX_PID_C1_TESTIN1_REG;
aw_dev->auth_desc.reg_in_h = AW87XXX_PID_C1_TESTIN2_REG;
aw_dev->auth_desc.reg_out_l = AW87XXX_PID_C1_TESTOUT1_REG;
aw_dev->auth_desc.reg_out_h = AW87XXX_PID_C1_TESTOUT2_REG;
}
/********************** aw87xxx_pid_c1 attributes end ************************/
/********************** aw87xxx_pid_c2 attributes ****************************/
static void aw_dev_chipid_c2_init(struct aw_device *aw_dev)
{
/* Product register permission info */
aw_dev->reg_max_addr = AW87XXX_PID_C2_REG_MAX;
aw_dev->reg_access = aw87xxx_pid_c2_reg_access;
/* software reset control info */
aw_dev->soft_rst_desc.len = sizeof(aw87xxx_pid_c2_softrst_access);
aw_dev->soft_rst_desc.access = aw87xxx_pid_c2_softrst_access;
aw_dev->soft_rst_enable = AW_DEV_SOFT_RST_ENABLE;
/* software power off control info */
aw_dev->soft_off_enable = AW_DEV_SOFT_OFF_ENABLE;
aw_dev->product_tab = g_aw_pid_c2_product;
aw_dev->product_cnt = AW87XXX_PID_C2_PROFUCT_MAX;
aw_dev->rec_desc.addr = AW87XXX_PID_C2_SYSCTRL_REG;
aw_dev->rec_desc.disable = AW87XXX_PID_C2_RCV_MODE_DISABLE;
aw_dev->rec_desc.enable = AW87XXX_PID_C2_RCV_MODE_ENABLE;
aw_dev->rec_desc.mask = AW87XXX_PID_C2_RCV_MODE_MASK;
/* esd reg info */
aw_dev->esd_desc.first_update_reg_addr = AW87XXX_PID_C2_CP_REG;
aw_dev->esd_desc.first_update_reg_val = AW87XXX_PID_C2_CP_CHECK;
aw_dev->ipeak_desc.reg = AW87XXX_PID_C2_PEAKLIMIT_REG;
aw_dev->ipeak_desc.mask = AW87XXX_PID_C2_BST_IPEAK_MASK;
aw_dev->vol_desc.addr = AW_REG_NONE;
/*encryption info*/
aw_dev->auth_desc.reg_in_l = AW87XXX_PID_C2_TESTIN1_REG;
aw_dev->auth_desc.reg_in_h = AW87XXX_PID_C2_TESTIN2_REG;
aw_dev->auth_desc.reg_out_l = AW87XXX_PID_C2_CRCOUT0_REG;
aw_dev->auth_desc.reg_out_h = AW87XXX_PID_C2_CRCOUT1_REG;
}
/********************** aw87xxx_pid_c2 attributes end ************************/
static int aw_dev_chip_init(struct aw_device *aw_dev)
{
int ret = 0;
@ -751,12 +1232,16 @@ static void aw_dev_chip_init(struct aw_device *aw_dev)
aw_dev_pid_9b_init(aw_dev);
AW_DEV_LOGI(aw_dev->dev, "product is pid_9B class");
break;
case AW_DEV_CHIPID_18:
aw_dev_chipid_18_init(aw_dev);
AW_DEV_LOGI(aw_dev->dev, "product is pid_18 class");
break;
case AW_DEV_CHIPID_39:
aw_dev_chipid_39_init(aw_dev);
AW_DEV_LOGI(aw_dev->dev, "product is pid_39 class");
break;
case AW_DEV_CHIPID_59:
if (aw_dev_gpio_is_valid(aw_dev)) {
if (aw87xxx_dev_gpio_is_valid(aw_dev)) {
aw_dev_chipid_59_5x9_init(aw_dev);
AW_DEV_LOGI(aw_dev->dev, "product is pid_59_5x9 class");
} else {
@ -772,21 +1257,35 @@ static void aw_dev_chip_init(struct aw_device *aw_dev)
aw_dev_chipid_76_init(aw_dev);
AW_DEV_LOGI(aw_dev->dev, "product is pid_76 class");
break;
case AW_DEV_CHIPID_60:
aw_dev_chipid_60_init(aw_dev);
AW_DEV_LOGI(aw_dev->dev, "product is pid_60 class");
break;
case AW_DEV_CHIPID_C1:
aw_dev_chipid_c1_init(aw_dev);
AW_DEV_LOGI(aw_dev->dev, "product is pid_c1 class");
break;
case AW_DEV_CHIPID_C2:
aw_dev_chipid_c2_init(aw_dev);
AW_DEV_LOGI(aw_dev->dev, "product is pid_c2 class");
break;
default:
AW_DEV_LOGE(aw_dev->dev, "unsupported device revision [0x%x]",
aw_dev->chipid);
return;
}
return -EINVAL;
}
static int aw_dev_get_chipid(struct aw_device *aw_dev)
return 0;
}
static int aw87xxx_dev_get_chipid(struct aw_device *aw_dev)
{
int ret = -1;
unsigned int cnt = 0;
unsigned char reg_val = 0;
for (cnt = 0; cnt < AW_READ_CHIPID_RETRIES; cnt++) {
ret = aw_dev_i2c_read_byte(aw_dev, AW_DEV_REG_CHIPID, &reg_val);
ret = aw87xxx_dev_i2c_read_byte(aw_dev, AW_DEV_REG_CHIPID, &reg_val);
if (ret < 0) {
AW_DEV_LOGE(aw_dev->dev, "[%d] read chip is failed, ret=%d",
cnt, ret);
@ -807,19 +1306,19 @@ static int aw_dev_get_chipid(struct aw_device *aw_dev)
return 0;
}
int aw_dev_init(struct aw_device *aw_dev)
int aw87xxx_dev_init(struct aw_device *aw_dev)
{
int ret = -1;
ret = aw_dev_get_chipid(aw_dev);
ret = aw87xxx_dev_get_chipid(aw_dev);
if (ret < 0) {
AW_DEV_LOGE(aw_dev->dev, "read chipid is failed,ret=%d", ret);
return ret;
}
aw_dev_chip_init(aw_dev);
ret = aw_dev_chip_init(aw_dev);
return 0;
return ret;
}

135
sound/soc/codecs/aw87xxx/aw_device.h
View File

@ -1,19 +1,37 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/* SPDX-License-Identifier: GPL-2.0
*
* aw87xxx_device.h aw87xxx pa module
*
* Copyright (c) 2021 AWINIC Technology CO., LTD
*
* Author: Barry <zhaozhongbo@awinic.com>
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*
*/
#ifndef __AW_DEVICE_H__
#define __AW_DEVICE_H__
#ifndef __AW87XXX_DEVICE_H__
#define __AW87XXX_DEVICE_H__
#include <linux/version.h>
#include <linux/kernel.h>
#include <sound/control.h>
#include <sound/soc.h>
#include "aw_acf_bin.h"
#define AW87XXX_PID_9B_PRODUCT_MAX (1)
#define AW87XXX_PID_39_PRODUCT_MAX (3)
#define AW87XXX_PID_59_3X9_PRODUCT_MAX (2)
#define AW87XXX_PID_59_5X9_PRODUCT_MAX (4)
#define AW87XXX_PID_5A_PRODUCT_MAX (5)
#define AW87XXX_PID_76_PROFUCT_MAX (3)
#define AW87XXX_PID_9B_PRODUCT_MAX (2)
#define AW87XXX_PID_18_PRODUCT_MAX (2)
#define AW87XXX_PID_39_PRODUCT_MAX (6)
#define AW87XXX_PID_59_3X9_PRODUCT_MAX (4)
#define AW87XXX_PID_59_5X9_PRODUCT_MAX (8)
#define AW87XXX_PID_5A_PRODUCT_MAX (12)
#define AW87XXX_PID_76_PROFUCT_MAX (10)
#define AW87XXX_PID_60_PROFUCT_MAX (10)
#define AW87XXX_PID_C1_PROFUCT_MAX (4)
#define AW87XXX_PID_C2_PROFUCT_MAX (10)
#define AW_PRODUCT_NAME_LEN (8)
#define AW_GPIO_HIGHT_LEVEL (1)
@ -33,6 +51,12 @@
#define AW_PID_9B_BIN_REG_CFG_COUNT (10)
#define AW87XXX_DELAY_REG_ADDR (0xFE)
#define AW87XXX_REG_DELAY_TIME (1000)
#define AW_BOOST_VOLTAGE_MIN (0x00)
#define AW_REG_NONE (0xFF)
/********************************************
*
* aw87xxx devices attributes
@ -40,6 +64,36 @@
*******************************************/
struct aw_device;
/*#define AW_ALGO_AUTH_DSP*/
extern int g_algo_auth_st;
enum AW_ALGO_AUTH_MODE {
AW_ALGO_AUTH_DISABLE = 0,
AW_ALGO_AUTH_MODE_MAGIC_ID,
AW_ALGO_AUTH_MODE_REG_CRC,
};
enum AW_ALGO_AUTH_ID {
AW_ALGO_AUTH_MAGIC_ID = 0x4157,
};
enum AW_ALGO_AUTH_STATUS {
AW_ALGO_AUTH_WAIT = 0,
AW_ALGO_AUTH_OK = 1,
};
#define AW_IOCTL_MAGIC_S 'w'
#define AW_IOCTL_GET_ALGO_AUTH _IOWR(AW_IOCTL_MAGIC_S, 1, struct algo_auth_data)
#define AW_IOCTL_SET_ALGO_AUTH _IOWR(AW_IOCTL_MAGIC_S, 2, struct algo_auth_data)
struct algo_auth_data {
int32_t auth_mode; /* 0: disable 1 : chip ID 2 : reg crc */
int32_t reg_crc;
int32_t random;
int32_t chip_id;
int32_t check_result; /* 0 failed 1 success */
};
struct aw_device_ops {
int (*pwr_on_func)(struct aw_device *aw_dev, struct aw_data_container *data);
int (*pwr_off_func)(struct aw_device *aw_dev, struct aw_data_container *data);
@ -54,6 +108,9 @@ enum aw_dev_chipid {
AW_DEV_CHIPID_9A = 0x9A,
AW_DEV_CHIPID_9B = 0x9B,
AW_DEV_CHIPID_76 = 0x76,
AW_DEV_CHIPID_60 = 0x60,
AW_DEV_CHIPID_C1 = 0xC1,
AW_DEV_CHIPID_C2 = 0xC2,
};
enum aw_dev_hw_status {
@ -78,6 +135,11 @@ enum aw_reg_receiver_mode {
AW_IS_REC_MODE = 1,
};
enum aw_reg_voltage_status {
AW_VOLTAGE_LOW = 0,
AW_VOLTAGE_HIGH,
};
struct aw_mute_desc {
uint8_t addr;
uint8_t enable;
@ -102,6 +164,29 @@ struct aw_rec_mode_desc {
uint8_t mask;
};
struct aw_voltage_desc {
uint8_t addr;
uint8_t vol_max;
uint8_t vol_min;
};
struct aw_auth_desc {
uint8_t reg_in_l;
uint8_t reg_in_h;
uint8_t reg_out_l;
uint8_t reg_out_h;
int32_t auth_mode;
int32_t reg_crc;
int32_t random;
int32_t chip_id;
int32_t check_result;
};
struct aw_ipeak_desc {
unsigned int reg;
unsigned int mask;
};
struct aw_device {
uint8_t i2c_addr;
uint8_t chipid;
@ -111,7 +196,6 @@ struct aw_device {
int hwen_status;
int i2c_bus;
int rst_gpio;
int rst_shared_gpio;
int reg_max_addr;
int product_cnt;
const char **product_tab;
@ -123,29 +207,34 @@ struct aw_device {
struct aw_soft_rst_desc soft_rst_desc;
struct aw_esd_check_desc esd_desc;
struct aw_rec_mode_desc rec_desc;
struct aw_voltage_desc vol_desc;
struct aw_auth_desc auth_desc;
struct aw_ipeak_desc ipeak_desc;
struct aw_device_ops ops;
};
int aw_dev_i2c_write_byte(struct aw_device *aw_dev,
int aw87xxx_dev_i2c_write_byte(struct aw_device *aw_dev,
uint8_t reg_addr, uint8_t reg_data);
int aw_dev_i2c_read_byte(struct aw_device *aw_dev,
int aw87xxx_dev_i2c_read_byte(struct aw_device *aw_dev,
uint8_t reg_addr, uint8_t *reg_data);
int aw_dev_i2c_read_msg(struct aw_device *aw_dev,
int aw87xxx_dev_i2c_read_msg(struct aw_device *aw_dev,
uint8_t reg_addr, uint8_t *data_buf, uint32_t data_len);
int aw_dev_i2c_write_bits(struct aw_device *aw_dev,
int aw87xxx_dev_i2c_write_bits(struct aw_device *aw_dev,
uint8_t reg_addr, uint8_t mask, uint8_t reg_data);
void aw_dev_soft_reset(struct aw_device *aw_dev);
void aw_dev_hw_pwr_ctrl(struct aw_device *aw_dev, bool enable);
int aw_dev_default_profile_check(struct aw_device *aw_dev,
int profile, struct aw_data_container *profile_data);
int aw_dev_default_pwr_on(struct aw_device *aw_dev,
void aw87xxx_dev_soft_reset(struct aw_device *aw_dev);
void aw87xxx_dev_hw_pwr_ctrl(struct aw_device *aw_dev, bool enable);
int aw87xxx_dev_default_pwr_on(struct aw_device *aw_dev,
struct aw_data_container *profile_data);
int aw_dev_default_pwr_off(struct aw_device *aw_dev,
int aw87xxx_dev_default_pwr_off(struct aw_device *aw_dev,
struct aw_data_container *profile_data);
int aw_dev_esd_reg_status_check(struct aw_device *aw_dev);
int aw_dev_check_reg_is_rec_mode(struct aw_device *aw_dev);
int aw_dev_init(struct aw_device *aw_dev);
int aw87xxx_dev_esd_reg_status_check(struct aw_device *aw_dev);
int aw87xxx_dev_check_reg_is_rec_mode(struct aw_device *aw_dev);
int aw87xxx_dev_init(struct aw_device *aw_dev);
int aw87xxx_dev_algo_auth_mode(struct aw_device *aw_dev, struct algo_auth_data *algo_data);
#ifdef AW_ALGO_AUTH_DSP
void aw87xxx_dev_algo_authentication(struct aw_device *aw_dev);
#endif
#endif

245
sound/soc/codecs/aw87xxx/aw_dsp.c
View File

@ -1,5 +1,5 @@
/*
* aw87xxx_dsp.c
// SPDX-License-Identifier: GPL-2.0
/* aw87xxx_dsp.c
*
* Copyright (c) 2021 AWINIC Technology CO., LTD
*
@ -24,47 +24,34 @@
#include "aw_dsp.h"
static DEFINE_MUTEX(g_dsp_lock);
static unsigned int g_spin_value;
static int g_rx_topo_id = AW_RX_DEFAULT_TOPO_ID;
static int g_rx_port_id = AW_RX_DEFAULT_PORT_ID;
#ifdef AW_MTK_OPEN_DSP_PLATFORM
extern int mtk_spk_send_ipi_buf_to_dsp(void *data_buffer,
uint32_t data_size);
extern int mtk_spk_recv_ipi_buf_from_dsp(int8_t *buffer,
int16_t size, uint32_t *buf_len);
/*
static int mtk_spk_send_ipi_buf_to_dsp(void *data_buffer,
uint32_t data_size)
{
AW_LOGI("enter");
return 0;
}
static int mtk_spk_recv_ipi_buf_from_dsp(int8_t *buffer,
int16_t size, uint32_t *buf_len)
{
AW_LOGI("enter");
return 0;
}
*/
#elif defined AW_QCOM_OPEN_DSP_PLATFORM
extern int afe_get_topology(int port_id);
extern int aw_send_afe_cal_apr(uint32_t param_id,
void *buf, int cmd_size, bool write);
/*
static int afe_get_topology(int port_id)
{
return -EPERM;
}
static int aw_send_afe_cal_apr(uint32_t param_id,
void *buf, int cmd_size, bool write)
{
AW_LOGI("enter, no define AWINIC_ADSP_ENABLE", __func__);
return 0;
}
*/
#endif
uint8_t aw_dsp_isEnable(void)
#ifdef AW_QCOM_OPEN_DSP_PLATFORM
extern void aw_set_port_id(int rx_port_id);
#else
static void aw_set_port_id(int rx_port_id)
{
}
#endif
uint8_t aw87xxx_dsp_isEnable(void)
{
#if (defined AW_QCOM_OPEN_DSP_PLATFORM) || (defined AW_MTK_OPEN_DSP_PLATFORM)
return true;
@ -142,97 +129,87 @@ failed:
/******************qcom dsp communication function start**********************/
#ifdef AW_QCOM_OPEN_DSP_PLATFORM
static int aw_check_dsp_ready(void)
static void aw_check_dsp_ready(void)
{
int ret;
ret = afe_get_topology(AFE_PORT_ID_AWDSP_RX);
ret = afe_get_topology(g_rx_port_id);
AW_LOGD("topo_id 0x%x", ret);
if (ret <= 0)
return 0;
else
return 1;
if (ret != g_rx_topo_id)
AW_LOGE("topo id 0x%x", ret);
}
static int aw_qcom_write_data_to_dsp(int32_t param_id,
void *data, int data_size)
{
int ret = 0;
int try = 0;
AW_LOGI("enter");
mutex_lock(&g_dsp_lock);
while (try < AW_DSP_TRY_TIME) {
if (aw_check_dsp_ready()) {
aw_check_dsp_ready();
ret = aw_send_afe_cal_apr(param_id, data,
data_size, true);
mutex_unlock(&g_dsp_lock);
return ret;
} else {
try++;
msleep(AW_DSP_SLEEP_TIME);
AW_LOGD("afe not ready try again");
}
}
mutex_unlock(&g_dsp_lock);
return -EINVAL;
}
static int aw_qcom_read_data_from_dsp(int32_t param_id,
void *data, int data_size)
{
int ret = 0;
int try = 0;
AW_LOGI("enter");
mutex_lock(&g_dsp_lock);
while (try < AW_DSP_TRY_TIME) {
if (aw_check_dsp_ready()) {
aw_check_dsp_ready();
ret = aw_send_afe_cal_apr(param_id, data,
data_size, false);
mutex_unlock(&g_dsp_lock);
return ret;
} else {
try++;
msleep(AW_DSP_SLEEP_TIME);
AW_LOGD("afe not ready try again");
}
}
mutex_unlock(&g_dsp_lock);
return -EINVAL;
}
#endif
/*****************qcom dsp communication function end*********************/
int aw_dsp_get_rx_module_enable(int *enable)
/*****************read/write msg communication function*********************/
static int aw_write_data_to_dsp(int32_t param_id, void *data, int data_size)
{
int ret = 0;
#if defined AW_QCOM_OPEN_DSP_PLATFORM
return aw_qcom_write_data_to_dsp(param_id, data, data_size);
#elif defined AW_MTK_OPEN_DSP_PLATFORM
return aw_mtk_write_data_to_dsp(param_id, data, data_size);
#else
return -EINVAL;
#endif
}
static int aw_read_data_from_dsp(int32_t param_id, void *data, int data_size)
{
#if defined AW_QCOM_OPEN_DSP_PLATFORM
return aw_qcom_read_data_from_dsp(param_id, data, data_size);
#elif defined AW_MTK_OPEN_DSP_PLATFORM
return aw_mtk_read_data_from_dsp(param_id, data, data_size);
#else
return -EINVAL;
#endif
}
/***************read/write msg communication function end*******************/
int aw87xxx_dsp_get_rx_module_enable(int *enable)
{
if (!enable) {
AW_LOGE("enable is NULL");
return -EINVAL;
}
#ifdef AW_QCOM_OPEN_DSP_PLATFORM
ret = aw_qcom_read_data_from_dsp(AWDSP_RX_SET_ENABLE,
return aw_read_data_from_dsp(AWDSP_RX_SET_ENABLE,
(void *)enable, sizeof(uint32_t));
#elif defined AW_MTK_OPEN_DSP_PLATFORM
ret = aw_mtk_read_data_from_dsp(AWDSP_RX_SET_ENABLE,
(void *)enable, sizeof(uint32_t));
#endif
return ret;
}
int aw_dsp_set_rx_module_enable(int enable)
int aw87xxx_dsp_set_rx_module_enable(int enable)
{
int ret = 0;
switch (enable) {
case AW_RX_MODULE_DISENABLE:
AW_LOGD("set enable=%d", enable);
@ -245,21 +222,13 @@ int aw_dsp_set_rx_module_enable(int enable)
return -EINVAL;
}
#ifdef AW_QCOM_OPEN_DSP_PLATFORM
ret = aw_qcom_write_data_to_dsp(AWDSP_RX_SET_ENABLE,
return aw_write_data_to_dsp(AWDSP_RX_SET_ENABLE,
&enable, sizeof(uint32_t));
#elif defined AW_MTK_OPEN_DSP_PLATFORM
ret = aw_mtk_write_data_to_dsp(AWDSP_RX_SET_ENABLE,
&enable, sizeof(uint32_t));
#endif
return ret;
}
int aw_dsp_get_vmax(uint32_t *vmax, int dev_index)
int aw87xxx_dsp_get_vmax(uint32_t *vmax, int dev_index)
{
int ret = 0;
int32_t param_id = 0;
switch (dev_index % AW_DSP_CHANNEL_MAX) {
@ -274,20 +243,13 @@ int aw_dsp_get_vmax(uint32_t *vmax, int dev_index)
dev_index);
return -EINVAL;
}
#ifdef AW_QCOM_OPEN_DSP_PLATFORM
ret = aw_qcom_read_data_from_dsp(param_id,
(void *)vmax, sizeof(uint32_t));
#elif defined AW_MTK_OPEN_DSP_PLATFORM
ret = aw_mtk_read_data_from_dsp(param_id,
(void *)vmax, sizeof(uint32_t));
#endif
return ret;
return aw_read_data_from_dsp(param_id,
(void *)vmax, sizeof(uint32_t));
}
int aw_dsp_set_vmax(uint32_t vmax, int dev_index)
int aw87xxx_dsp_set_vmax(uint32_t vmax, int dev_index)
{
int ret = 0;
int32_t param_id = 0;
switch (dev_index % AW_DSP_CHANNEL_MAX) {
@ -302,12 +264,99 @@ int aw_dsp_set_vmax(uint32_t vmax, int dev_index)
dev_index);
return -EINVAL;
}
#ifdef AW_QCOM_OPEN_DSP_PLATFORM
ret = aw_qcom_write_data_to_dsp(param_id, &vmax, sizeof(uint32_t));
#elif defined AW_MTK_OPEN_DSP_PLATFORM
ret = aw_mtk_write_data_to_dsp(param_id, &vmax, sizeof(uint32_t));
#endif
return aw_write_data_to_dsp(param_id, &vmax, sizeof(uint32_t));
}
int aw87xxx_dsp_set_spin(uint32_t ctrl_value)
{
int ret = 0;
if (ctrl_value >= AW_SPIN_MAX) {
AW_LOGE("spin [%d] unsupported ", ctrl_value);
return -EINVAL;
}
ret = aw_write_data_to_dsp(AW_MSG_ID_SPIN, &ctrl_value,
sizeof(uint32_t));
if (ret) {
AW_LOGE("spin [%d] set failed ", ctrl_value);
return ret;
}
g_spin_value = ctrl_value;
return 0;
}
int aw87xxx_dsp_get_spin(void)
{
return g_spin_value;
}
int aw87xxx_spin_set_record_val(void)
{
AW_LOGD("record write spin enter");
return aw87xxx_dsp_set_spin(g_spin_value);
}
EXPORT_SYMBOL(aw87xxx_spin_set_record_val);
#ifdef AW_ALGO_AUTH_DSP
int aw87xxx_dsp_get_algo_auth_data(struct aw_device *aw_dev,
char *data, unsigned int data_len)
{
int ret = 0;
ret = aw_read_data_from_dsp(AW_MSG_ID_ALGO_AUTHENTICATION, data, data_len);
if (ret) {
AW_DEV_LOGE(aw_dev->dev, "read algo auth failed");
return ret;
}
AW_DEV_LOGD(aw_dev->dev, "get algo auth data done");
return ret;
}
int aw87xxx_dsp_set_algo_auth_data(struct aw_device *aw_dev,
char *data, unsigned int data_len)
{
int ret = 0;
ret = aw_write_data_to_dsp(AW_MSG_ID_ALGO_AUTHENTICATION, data, data_len);
if (ret) {
AW_DEV_LOGE(aw_dev->dev, "write algo auth failed ");
return ret;
}
AW_DEV_LOGD(aw_dev->dev, "set algo auth done");
return ret;
}
#endif
void aw87xxx_device_parse_topo_id_dt(struct aw_device *aw_dev)
{
int ret;
ret = of_property_read_u32(aw_dev->dev->of_node, "aw-rx-topo-id", &g_rx_topo_id);
if (ret < 0) {
g_rx_topo_id = AW_RX_DEFAULT_TOPO_ID;
AW_DEV_LOGI(aw_dev->dev, "read aw-rx-topo-id failed,use default");
}
AW_DEV_LOGI(aw_dev->dev, "rx-topo-id: 0x%x", g_rx_topo_id);
}
void aw87xxx_device_parse_port_id_dt(struct aw_device *aw_dev)
{
int ret;
ret = of_property_read_u32(aw_dev->dev->of_node, "aw-rx-port-id", &g_rx_port_id);
if (ret < 0) {
g_rx_port_id = AW_RX_DEFAULT_PORT_ID;
AW_DEV_LOGI(aw_dev->dev, "read aw-rx-port-id failed,use default");
}
aw_set_port_id(g_rx_port_id);
AW_DEV_LOGI(aw_dev->dev, "rx-port-id: 0x%x", g_rx_port_id);
}

54
sound/soc/codecs/aw87xxx/aw_dsp.h
View File

@ -1,22 +1,47 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/* SPDX-License-Identifier: GPL-2.0
* aw87xxx_dsp.h
*
* Copyright (c) 2021 AWINIC Technology CO., LTD
*
* Author: Barry <zhaozhongbo@awinic.com>
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*/
#ifndef __AW_DSP_H__
#define __AW_DSP_H__
#ifndef __AW87XXX_DSP_H__
#define __AW87XXX_DSP_H__
#include "aw_device.h"
/*#define AW_MTK_OPEN_DSP_PLATFORM*/
/*#define AW_QCOM_OPEN_DSP_PLATFORM*/
/*Note: The pord_ID is configured according to different platforms*/
#define AFE_PORT_ID_AWDSP_RX (0x4000)
#define AW_DSP_TRY_TIME (3)
#define AW_DSP_SLEEP_TIME (10)
#define AW_DSP_MSG_HDR_VER (1)
#define AW_RX_DEFAULT_TOPO_ID (0x1000FF01)
#define AW_RX_DEFAULT_PORT_ID (0x4000)
#define AWDSP_RX_SET_ENABLE (0x10013D11)
#define AWDSP_RX_PARAMS (0x10013D12)
#define AWDSP_RX_VMAX_0 (0X10013D17)
#define AWDSP_RX_VMAX_1 (0X10013D18)
#define AW_MSG_ID_SPIN (0x10013D2E)
#define AW_MSG_ID_ALGO_AUTHENTICATION (0x10013D46)
enum {
AW_SPIN_0 = 0,
AW_SPIN_90,
AW_SPIN_180,
AW_SPIN_270,
AW_SPIN_MAX,
};
typedef struct mtk_dsp_msg_header {
int32_t type;
@ -41,10 +66,19 @@ enum aw_dsp_channel {
AW_DSP_CHANNEL_MAX,
};
uint8_t aw_dsp_isEnable(void);
int aw_dsp_get_rx_module_enable(int *enable);
int aw_dsp_set_rx_module_enable(int enable);
int aw_dsp_get_vmax(uint32_t *vmax, int channel);
int aw_dsp_set_vmax(uint32_t vmax, int channel);
uint8_t aw87xxx_dsp_isEnable(void);
int aw87xxx_dsp_get_rx_module_enable(int *enable);
int aw87xxx_dsp_set_rx_module_enable(int enable);
int aw87xxx_dsp_get_vmax(uint32_t *vmax, int channel);
int aw87xxx_dsp_set_vmax(uint32_t vmax, int channel);
int aw87xxx_dsp_set_spin(uint32_t ctrl_value);
int aw87xxx_dsp_get_spin(void);
int aw87xxx_spin_set_record_val(void);
void aw87xxx_device_parse_port_id_dt(struct aw_device *aw_dev);
void aw87xxx_device_parse_topo_id_dt(struct aw_device *aw_dev);
#ifdef AW_ALGO_AUTH_DSP
int aw87xxx_dsp_get_algo_auth_data(struct aw_device *aw_dev, char *data, unsigned int data_len);
int aw87xxx_dsp_set_algo_auth_data(struct aw_device *aw_dev, char *data, unsigned int data_len);
#endif
#endif

17
sound/soc/codecs/aw87xxx/aw_log.h
View File

@ -1,7 +1,18 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/* SPDX-License-Identifier: GPL-2.0
* aw87xxx_log.h
*
* Copyright (c) 2021 AWINIC Technology CO., LTD
*
* Author: Barry <zhaozhongbo@awinic.com>
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*/
#ifndef __AW_LOG_H__
#define __AW_LOG_H__
#ifndef __AW87XXX_LOG_H__
#define __AW87XXX_LOG_H__
#include <linux/kernel.h>

1355
sound/soc/codecs/aw87xxx/aw_monitor.c
View File

File diff suppressed because it is too large Load Diff

189
sound/soc/codecs/aw87xxx/aw_monitor.h
View File

@ -1,7 +1,20 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/* SPDX-License-Identifier: GPL-2.0
* aw87xxx_monitor.h
*
* Copyright (c) 2021 AWINIC Technology CO., LTD
*
* Author: Barry <zhaozhongbo@awinic.com>
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*/
#ifndef __AW_MONITOR_H__
#define __AW_MONITOR_H__
#ifndef __AW87XXX_MONITOR_H__
#define __AW87XXX_MONITOR_H__
/*#define AW_DEBUG*/
#define AW_WAIT_DSP_OPEN_TIME (3000)
#define AW_VBAT_CAPACITY_MIN (0)
@ -11,11 +24,64 @@
#define AW_VMAX_MAX (0)
#define AW_DEFAULT_MONITOR_TIME (3000)
#define AW_WAIT_TIME (3000)
#define REG_STATUS_CHECK_MAX (10)
#define REG_STATUS_CHECK_MAX (5)
#define AW_ESD_CHECK_DELAY (1)
#define AW_MONOTOR_ESD_ERR_CNT_MAX (3)
#define AW_MONITOR_TIME_MIN (0)
#define AW_MONITOR_TIME_MAX (50000)
#define AW_ESD_ENABLE (true)
#define AW_ESD_DISABLE (false)
#define AW_ESD_ENABLE_STRLEN (16)
#define MONITOR_EN_MASK 0x01
#define AW_TABLE_SIZE sizeof(struct aw_table)
#define AW_GET_32_DATA(w, x, y, z) \
((uint32_t)((((uint8_t)w) << 24) | (((uint8_t)x) << 16) | (((uint8_t)y) << 8) | ((uint8_t)z)))
#define AW_GET_16_DATA(x, y) \
((uint16_t)((((uint8_t)x) << 8) | (uint8_t)y))
#define IPEAK_NONE (0xFF)
#define GAIN_NONE (0xFF)
#define VMAX_NONE (0xFFFFFFFF)
enum {
AW_MON_LOGIC_OR = 0,
AW_MON_LOGIC_AND = 1,
};
enum {
MONITOR_EN_BIT = 0,
MONITOR_LOGIC_BIT = 1,
MONITOR_IPEAK_EN_BIT = 2,
MONITOR_GAIN_EN_BIT = 3,
MONITOR_VMAX_EN_BIT = 4,
MONITOR_TEMP_EN_BIT = 5,
MONITOR_VOL_EN_BIT = 6,
MONITOR_TEMPERATURE_SOURCE_BIT = 7,
MONITOR_VOLTAGE_SOURCE_BIT = 8,
MONITOR_VOLTAGE_MODE_BIT = 9,
};
enum {
AW_SYS_VOLTAGE_NOW = 0,
AW_SYS_CAPACITY = 1,
};
enum {
AW_VOLTAGE_INFO = 0,
AW_CAPACITY_INFO = 1,
AW_TEMPERATURE_INFO = 2,
};
enum {
AW_CHIP_INFO = 0,
AW_PLATFORM_INFO = 1,
};
enum aw_monitor_init {
AW_MONITOR_CFG_WAIT = 0,
@ -32,11 +98,30 @@ enum aw_monitor_data_ver {
AW_MONITOR_DATA_VER_MAX,
};
enum aw_monitor_hdr_ver {
AW_MONITOR_HDR_VER_0_1_0 = 0x00010000,
AW_MONITOR_HDR_VER_0_1_1 = 0x00010100,
AW_MONITOR_HDR_VER_0_1_2 = 0x00010200,
};
enum aw_monitor_first_enter {
AW_FIRST_ENTRY = 0,
AW_NOT_FIRST_ENTRY = 1,
};
struct aw_container {
int len;
uint8_t data[];
};
struct aw_table {
int16_t min_val;
int16_t max_val;
uint16_t ipeak;
uint16_t gain;
uint32_t vmax;
};
struct aw_bin_header {
uint32_t check_sum;
uint32_t header_ver;
@ -59,12 +144,75 @@ struct aw_monitor_header {
uint32_t reserve[4];
};
/* v0.1.2 */
struct aw_monitor_hdr {
uint32_t check_sum;
uint32_t monitor_ver;
char chip_type[16];
uint32_t ui_ver;
uint32_t monitor_time;
uint32_t monitor_count;
uint32_t enable_flag;
/* [bit 31:7]*/
/* [bit 9: voltage mode]*/
/* [bit 8: voltage source]*/
/* [bit 7: temperature source]*/
/* [bit 6: vol en]*/
/* [bit 5: temp en]*/
/* [bit 4: vmax en]*/
/* [bit 3: gain en]*/
/* [bit 2: ipeak en]*/
/* [bit 1: & or | flag]*/
/* [bit 0: monitor en]*/
uint32_t temp_aplha;
uint32_t temp_num;
uint32_t single_temp_size;
uint32_t temp_offset;
uint32_t vol_aplha;
uint32_t vol_num;
uint32_t single_vol_size;
uint32_t vol_offset;
uint32_t reserver[3];
};
struct vmax_step_config {
uint32_t vbat_min;
uint32_t vbat_max;
int vmax_vol;
};
struct aw_table_info {
uint8_t table_num;
struct aw_table *aw_table;
};
struct aw_monitor_cfg {
uint8_t monitor_status;
uint32_t monitor_switch;
uint32_t monitor_time;
uint32_t monitor_count;
uint32_t logic_switch;
uint32_t temp_switch;
uint32_t temp_aplha;
uint32_t vol_switch;
uint32_t vol_aplha;
uint32_t ipeak_switch;
uint32_t gain_switch;
uint32_t vmax_switch;
uint32_t temp_source;
uint32_t vol_source;
uint32_t vol_mode;
struct aw_table_info temp_info;
struct aw_table_info vol_info;
};
struct aw_monitor_trace {
int32_t pre_val;
int32_t sum_val;
struct aw_table aw_table;
};
struct aw_monitor {
bool open_dsp_en;
bool esd_enable;
@ -72,24 +220,39 @@ struct aw_monitor {
uint8_t first_entry;
uint8_t timer_cnt;
uint32_t vbat_sum;
uint32_t custom_capacity;
int32_t custom_capacity;
uint32_t pre_vmax;
uint32_t esd_err_cnt;
uint8_t samp_count;
uint32_t version;
#ifdef AW_DEBUG
uint16_t test_vol;
int16_t test_temp;
#endif
int bin_status;
struct aw_monitor_header monitor_hdr;
struct vmax_step_config *vmax_cfg;
struct aw_monitor_cfg monitor_cfg;
struct aw_monitor_trace temp_trace;
struct aw_monitor_trace vol_trace;
struct aw_container *monitor_container;
struct delayed_work with_dsp_work;
};
void aw_monitor_cfg_free(struct aw_monitor *monitor);
int aw_monitor_bin_parse(struct device *dev,
char *monitor_data, uint32_t data_len);
void aw_monitor_stop(struct aw_monitor *monitor);
void aw_monitor_start(struct aw_monitor *monitor);
int aw_monitor_no_dsp_get_vmax(struct aw_monitor *monitor,
void aw87xxx_monitor_cfg_free(struct aw_monitor *monitor);
int aw87xxx_monitor_bin_parse(struct device *dev,
const char *monitor_data, uint32_t data_len);
void aw87xxx_monitor_stop(struct aw_monitor *monitor);
void aw87xxx_monitor_start(struct aw_monitor *monitor);
int aw87xxx_monitor_no_dsp_get_vmax(struct aw_monitor *monitor,
int32_t *vmax);
void aw_monitor_init(struct device *dev, struct aw_monitor *monitor,
void aw87xxx_monitor_init(struct device *dev, struct aw_monitor *monitor,
struct device_node *dev_node);
void aw_monitor_exit(struct aw_monitor *monitor);
void aw87xxx_monitor_exit(struct aw_monitor *monitor);
int aw87xxx_dev_monitor_switch_set(struct aw_monitor *monitor, uint32_t enable);
#endif

7
sound/soc/codecs/es8328.c
View File

@ -893,13 +893,6 @@ int es8328_probe(struct device *dev, struct regmap *regmap)
dev_set_drvdata(dev, es8328);
#ifdef CONFIG_SND_SOC_AW87XXX
ret = aw87xxx_add_codec_controls((void *)component);
if (ret < 0) {
pr_err("%s: add_codec_controls failed, ret %d\n", __func__, ret);
}
#endif
return devm_snd_soc_register_component(dev,
&es8328_component_driver, &es8328_dai, 1);
}