phy/rockchip: samsung-hdptx: Fix link train EQ failed
Signed-off-by: Wyon Bi <bivvy.bi@rock-chips.com> Change-Id: I72b78e063eb014e756ba9d39d9e79909a09dce5e
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@ -595,10 +595,22 @@ static int rockchip_hdptx_phy_set_voltages(struct rockchip_hdptx_phy *hdptx,
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struct phy_configure_opts_dp *dp)
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{
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u8 lane;
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u32 status;
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int ret;
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for (lane = 0; lane < dp->lanes; lane++)
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rockchip_hdptx_phy_set_voltage(hdptx, dp, lane);
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reset_control_deassert(hdptx->lane_reset);
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ret = regmap_read_poll_timeout(hdptx->grf, HDPTXPHY_GRF_STATUS0,
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status, FIELD_GET(PHY_RDY, status),
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50, 5000);
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if (ret) {
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dev_err(hdptx->dev, "timeout waiting for phy_rdy\n");
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return ret;
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}
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return 0;
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}
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@ -623,9 +635,6 @@ static void rockchip_hdptx_phy_lane_disable(struct rockchip_hdptx_phy *hdptx)
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static int rockchip_hdptx_phy_set_lanes(struct rockchip_hdptx_phy *hdptx,
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struct phy_configure_opts_dp *dp)
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{
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u32 status;
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int ret;
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if (!dp->lanes) {
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rockchip_hdptx_phy_lane_disable(hdptx);
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return 0;
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@ -634,16 +643,6 @@ static int rockchip_hdptx_phy_set_lanes(struct rockchip_hdptx_phy *hdptx,
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regmap_update_bits(hdptx->regmap, 0x081c, LANE_EN,
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FIELD_PREP(LANE_EN, GENMASK(dp->lanes - 1, 0)));
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reset_control_deassert(hdptx->lane_reset);
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ret = regmap_read_poll_timeout(hdptx->grf, HDPTXPHY_GRF_STATUS0,
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status, FIELD_GET(PHY_RDY, status),
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50, 5000);
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if (ret) {
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dev_err(hdptx->dev, "timeout waiting for phy_rdy\n");
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return ret;
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}
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return 0;
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}
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