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Support Orange Pi Zero2 W

This commit is contained in:
orangepi-xunlong 2023-06-15 18:07:52 +08:00
parent 5b98978bd1
commit a2713f5075
17 changed files with 1455 additions and 3294 deletions
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BIN
external/cache/debs/arm64/wiringpi_2.48.deb vendored
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external/cache/debs/arm64/wiringpi_2.49.deb vendored Normal file
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15
external/config/boards/orangepizero2w.conf vendored Executable file
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@ -0,0 +1,15 @@
# Allwinner H618 quad core 1GB/1.5GB/2GB/4GB RAM
BOARD_NAME="OPI Zero2W"
BOARDFAMILY="sun50iw9"
BOOTCONFIG="orangepi_zero2w_defconfig"
KERNEL_TARGET="current,next"
MODULES_LEGACY="uwe5622_bsp_sdio sprdwl_ng sprdbt_tty"
MODULES_CURRENT="uwe5622_bsp_sdio sprdwl_ng sprdbt_tty"
MODULES_NEXT="uwe5622_bsp_sdio sprdwl_ng sprdbt_tty"
MODULES_BLACKLIST_LEGACY="bcmdhd"
MODULES_BLACKLIST_CURRENT="bcmdhd"
DISTRIB_TYPE_LEGACY="buster"
DISTRIB_TYPE_CURRENT="bullseye focal jammy"
DISTRIB_TYPE_NEXT="bullseye bookworm jammy"
BOOT_LOGO="desktop"
REVISION="1.0.0"

6
external/config/bootscripts/boot-sun50iw9-next.cmd vendored
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@ -27,7 +27,11 @@ fi
if test "${console}" = "display" || test "${console}" = "both"; then setenv consoleargs "console=ttyS0,115200 console=tty1"; fi
if test "${console}" = "serial"; then setenv consoleargs "console=ttyS0,115200"; fi
if test "${bootlogo}" = "true"; then setenv consoleargs "bootsplash.bootfile=bootsplash.orangepi ${consoleargs}"; fi
if test "${bootlogo}" = "true"; then
setenv consoleargs "splash plymouth.ignore-serial-consoles ${consoleargs}"
else
setenv consoleargs "splash=verbose ${consoleargs}"
fi
# get PARTUUID of first partition on SD/eMMC it was loaded from
# mmc 0 is always mapped to device u-boot (2016.09+) was loaded from

4
external/config/bootscripts/boot-sun50iw9.cmd vendored
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@ -53,8 +53,8 @@ fdt set disp boot_disp1 <${boot_disp1}>
fdt set disp boot_disp2 <${boot_disp2}>
fdt set disp tv_vdid <${tv_vdid}>
fdt set disp fb0_width <${fb0_width}>
fdt set disp fb0_height <${fb0_height}>
fdt set /soc/disp fb0_width <${fb0_width}>
fdt set /soc/disp fb0_height <${fb0_height}>
fdt set mmc0 cap-sd-highspeed
#fdt set mmc0 sd-uhs-sdr50

295
external/config/kernel/linux-sun50iw9-current.config vendored
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@ -1070,8 +1070,8 @@ CONFIG_NF_CONNTRACK_SANE=y
CONFIG_NF_CONNTRACK_SIP=m
CONFIG_NF_CONNTRACK_TFTP=y
CONFIG_NF_CT_NETLINK=y
CONFIG_NF_CT_NETLINK_TIMEOUT=m
CONFIG_NF_CT_NETLINK_HELPER=m
CONFIG_NF_CT_NETLINK_TIMEOUT=y
CONFIG_NF_CT_NETLINK_HELPER=y
CONFIG_NETFILTER_NETLINK_GLUE_CT=y
CONFIG_NF_NAT=y
CONFIG_NF_NAT_AMANDA=y
@ -1082,28 +1082,28 @@ CONFIG_NF_NAT_TFTP=y
CONFIG_NF_NAT_REDIRECT=y
CONFIG_NF_NAT_MASQUERADE=y
CONFIG_NETFILTER_SYNPROXY=m
CONFIG_NF_TABLES=m
CONFIG_NF_TABLES_SET=m
CONFIG_NF_TABLES=y
CONFIG_NF_TABLES_SET=y
CONFIG_NF_TABLES_INET=y
CONFIG_NF_TABLES_NETDEV=y
CONFIG_NFT_NUMGEN=m
CONFIG_NFT_CT=m
# CONFIG_NFT_FLOW_OFFLOAD is not set
CONFIG_NFT_COUNTER=m
CONFIG_NFT_CONNLIMIT=m
CONFIG_NFT_LOG=m
CONFIG_NFT_LIMIT=m
CONFIG_NFT_MASQ=m
CONFIG_NFT_REDIR=m
CONFIG_NFT_NAT=m
CONFIG_NFT_TUNNEL=m
CONFIG_NFT_OBJREF=m
CONFIG_NFT_QUEUE=m
CONFIG_NFT_QUOTA=m
CONFIG_NFT_REJECT=m
CONFIG_NFT_REJECT_INET=m
CONFIG_NFT_COMPAT=m
CONFIG_NFT_HASH=m
CONFIG_NFT_NUMGEN=y
CONFIG_NFT_CT=y
CONFIG_NFT_FLOW_OFFLOAD=m
CONFIG_NFT_COUNTER=y
CONFIG_NFT_CONNLIMIT=y
CONFIG_NFT_LOG=y
CONFIG_NFT_LIMIT=y
CONFIG_NFT_MASQ=y
CONFIG_NFT_REDIR=y
CONFIG_NFT_NAT=y
CONFIG_NFT_TUNNEL=y
CONFIG_NFT_OBJREF=y
CONFIG_NFT_QUEUE=y
CONFIG_NFT_QUOTA=y
CONFIG_NFT_REJECT=y
CONFIG_NFT_REJECT_INET=y
CONFIG_NFT_COMPAT=y
CONFIG_NFT_HASH=y
CONFIG_NFT_FIB=m
# CONFIG_NFT_FIB_INET is not set
CONFIG_NFT_XFRM=m
@ -1284,7 +1284,7 @@ CONFIG_NF_DEFRAG_IPV4=y
CONFIG_NF_SOCKET_IPV4=y
CONFIG_NF_TPROXY_IPV4=y
CONFIG_NF_TABLES_IPV4=y
CONFIG_NFT_REJECT_IPV4=m
CONFIG_NFT_REJECT_IPV4=y
CONFIG_NFT_DUP_IPV4=m
CONFIG_NFT_FIB_IPV4=m
CONFIG_NF_TABLES_ARP=y
@ -1325,7 +1325,7 @@ CONFIG_IP_NF_ARP_MANGLE=y
CONFIG_NF_SOCKET_IPV6=y
CONFIG_NF_TPROXY_IPV6=y
CONFIG_NF_TABLES_IPV6=y
CONFIG_NFT_REJECT_IPV6=m
CONFIG_NFT_REJECT_IPV6=y
CONFIG_NFT_DUP_IPV6=m
CONFIG_NFT_FIB_IPV6=m
CONFIG_NF_FLOW_TABLE_IPV6=m
@ -1792,8 +1792,126 @@ CONFIG_SUNXI_MBUS=y
# end of Bus devices
# CONFIG_CONNECTOR is not set
# CONFIG_GNSS is not set
# CONFIG_MTD is not set
CONFIG_GNSS=m
CONFIG_MTD=y
CONFIG_MTD_TESTS=m
#
# Partition parsers
#
# CONFIG_MTD_AR7_PARTS is not set
CONFIG_MTD_CMDLINE_PARTS=m
CONFIG_MTD_OF_PARTS=y
# CONFIG_MTD_AFS_PARTS is not set
# CONFIG_MTD_REDBOOT_PARTS is not set
# end of Partition parsers
#
# User Modules And Translation Layers
#
CONFIG_MTD_BLKDEVS=m
CONFIG_MTD_BLOCK=m
CONFIG_MTD_BLOCK_RO=m
CONFIG_FTL=m
CONFIG_NFTL=m
CONFIG_NFTL_RW=y
CONFIG_INFTL=m
CONFIG_RFD_FTL=m
CONFIG_SSFDC=m
CONFIG_SM_FTL=m
CONFIG_MTD_OOPS=y
# CONFIG_MTD_PSTORE is not set
CONFIG_MTD_SWAP=m
CONFIG_MTD_PARTITIONED_MASTER=y
#
# RAM/ROM/Flash chip drivers
#
CONFIG_MTD_CFI=m
CONFIG_MTD_JEDECPROBE=m
CONFIG_MTD_GEN_PROBE=m
CONFIG_MTD_CFI_ADV_OPTIONS=y
CONFIG_MTD_CFI_NOSWAP=y
# CONFIG_MTD_CFI_BE_BYTE_SWAP is not set
# CONFIG_MTD_CFI_LE_BYTE_SWAP is not set
CONFIG_MTD_CFI_GEOMETRY=y
CONFIG_MTD_MAP_BANK_WIDTH_1=y
CONFIG_MTD_MAP_BANK_WIDTH_2=y
CONFIG_MTD_MAP_BANK_WIDTH_4=y
# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
CONFIG_MTD_CFI_I1=y
CONFIG_MTD_CFI_I2=y
# CONFIG_MTD_CFI_I4 is not set
# CONFIG_MTD_CFI_I8 is not set
# CONFIG_MTD_OTP is not set
# CONFIG_MTD_CFI_INTELEXT is not set
# CONFIG_MTD_CFI_AMDSTD is not set
# CONFIG_MTD_CFI_STAA is not set
CONFIG_MTD_CFI_UTIL=m
CONFIG_MTD_RAM=m
# CONFIG_MTD_ROM is not set
# CONFIG_MTD_ABSENT is not set
# end of RAM/ROM/Flash chip drivers
#
# Mapping drivers for chip access
#
CONFIG_MTD_COMPLEX_MAPPINGS=y
CONFIG_MTD_PHYSMAP=m
CONFIG_MTD_PHYSMAP_COMPAT=y
CONFIG_MTD_PHYSMAP_START=0x8000000
CONFIG_MTD_PHYSMAP_LEN=0
CONFIG_MTD_PHYSMAP_BANKWIDTH=2
CONFIG_MTD_PHYSMAP_OF=y
CONFIG_MTD_PHYSMAP_VERSATILE=y
CONFIG_MTD_PHYSMAP_GEMINI=y
CONFIG_MTD_PHYSMAP_GPIO_ADDR=y
CONFIG_MTD_PLATRAM=m
# end of Mapping drivers for chip access
#
# Self-contained MTD device drivers
#
CONFIG_MTD_DATAFLASH=m
CONFIG_MTD_DATAFLASH_WRITE_VERIFY=y
CONFIG_MTD_DATAFLASH_OTP=y
CONFIG_MTD_MCHP23K256=m
CONFIG_MTD_SST25L=m
CONFIG_MTD_SLRAM=m
CONFIG_MTD_PHRAM=m
CONFIG_MTD_MTDRAM=m
CONFIG_MTDRAM_TOTAL_SIZE=4096
CONFIG_MTDRAM_ERASE_SIZE=128
CONFIG_MTD_BLOCK2MTD=m
#
# Disk-On-Chip Device Drivers
#
CONFIG_MTD_DOCG3=m
CONFIG_BCH_CONST_M=14
CONFIG_BCH_CONST_T=4
# end of Self-contained MTD device drivers
# CONFIG_MTD_ONENAND is not set
CONFIG_MTD_NAND_ECC_SW_HAMMING=m
# CONFIG_MTD_NAND_ECC_SW_HAMMING_SMC is not set
# CONFIG_MTD_RAW_NAND is not set
# CONFIG_MTD_SPI_NAND is not set
#
# LPDDR & LPDDR2 PCM memory drivers
#
# CONFIG_MTD_LPDDR is not set
# end of LPDDR & LPDDR2 PCM memory drivers
CONFIG_MTD_SPI_NOR=y
CONFIG_MTD_SPI_NOR_USE_4K_SECTORS=y
CONFIG_SPI_CADENCE_QUADSPI=y
CONFIG_SPI_MTK_QUADSPI=y
# CONFIG_MTD_UBI is not set
# CONFIG_MTD_HYPERBUS is not set
CONFIG_DTC=y
CONFIG_OF=y
# CONFIG_OF_UNITTEST is not set
@ -2781,7 +2899,7 @@ CONFIG_HW_RANDOM_TPM=y
CONFIG_DUMP_REG=y
CONFIG_DUMP_REG_MISC=y
CONFIG_SUNXI_SYS_INFO=y
# CONFIG_SUNXI_QA_TEST is not set
CONFIG_SUNXI_QA_TEST=y
CONFIG_SUNXI_SMC=y
CONFIG_SUNXI_G2D=y
# CONFIG_SUNXI_G2D_MIXER is not set
@ -2877,7 +2995,7 @@ CONFIG_I2C_SLAVE_EEPROM=m
CONFIG_SPI=y
# CONFIG_SPI_DEBUG is not set
CONFIG_SPI_MASTER=y
# CONFIG_SPI_MEM is not set
CONFIG_SPI_MEM=y
#
# SPI Master Controller Drivers
@ -2907,9 +3025,11 @@ CONFIG_SPI_SUNXI=y
# SPI Protocol Masters
#
CONFIG_SPI_SPIDEV=y
# CONFIG_SPI_LOOPBACK_TEST is not set
CONFIG_SPI_LOOPBACK_TEST=m
# CONFIG_SPI_TLE62X0 is not set
# CONFIG_SPI_SLAVE is not set
CONFIG_SPI_SLAVE=y
# CONFIG_SPI_SLAVE_TIME is not set
# CONFIG_SPI_SLAVE_SYSTEM_CONTROL is not set
CONFIG_SPI_DYNAMIC=y
# CONFIG_SPMI is not set
# CONFIG_HSI is not set
@ -4786,6 +4906,7 @@ CONFIG_LEDS_LM3697=m
CONFIG_LEDS_TRIGGERS=y
CONFIG_LEDS_TRIGGER_TIMER=y
CONFIG_LEDS_TRIGGER_ONESHOT=y
# CONFIG_LEDS_TRIGGER_MTD is not set
CONFIG_LEDS_TRIGGER_HEARTBEAT=y
CONFIG_LEDS_TRIGGER_BACKLIGHT=y
CONFIG_LEDS_TRIGGER_CPU=y
@ -4968,7 +5089,7 @@ CONFIG_SYNC_FILE=y
# CONFIG_AUXDISPLAY is not set
# CONFIG_UIO is not set
# CONFIG_VFIO is not set
# CONFIG_VIRT_DRIVERS is not set
CONFIG_VIRT_DRIVERS=y
CONFIG_VIRTIO_MENU=y
# CONFIG_VIRTIO_MMIO is not set
@ -5520,41 +5641,85 @@ CONFIG_CONFIGFS_FS=y
# end of Pseudo filesystems
CONFIG_MISC_FILESYSTEMS=y
# CONFIG_ORANGEFS_FS is not set
# CONFIG_ADFS_FS is not set
# CONFIG_AFFS_FS is not set
# CONFIG_ECRYPT_FS is not set
# CONFIG_HFS_FS is not set
CONFIG_ORANGEFS_FS=m
CONFIG_ADFS_FS=m
CONFIG_ADFS_FS_RW=y
CONFIG_AFFS_FS=m
CONFIG_ECRYPT_FS=m
CONFIG_ECRYPT_FS_MESSAGING=y
CONFIG_HFS_FS=m
# CONFIG_HFSPLUS_FS is not set
# CONFIG_BEFS_FS is not set
# CONFIG_BFS_FS is not set
# CONFIG_EFS_FS is not set
# CONFIG_CRAMFS is not set
# CONFIG_SQUASHFS is not set
# CONFIG_VXFS_FS is not set
# CONFIG_MINIX_FS is not set
# CONFIG_OMFS_FS is not set
# CONFIG_HPFS_FS is not set
# CONFIG_QNX4FS_FS is not set
# CONFIG_QNX6FS_FS is not set
# CONFIG_ROMFS_FS is not set
CONFIG_BEFS_FS=m
CONFIG_BEFS_DEBUG=y
CONFIG_BFS_FS=m
CONFIG_EFS_FS=m
# CONFIG_JFFS2_FS is not set
CONFIG_CRAMFS=m
CONFIG_CRAMFS_BLOCKDEV=y
CONFIG_CRAMFS_MTD=y
CONFIG_SQUASHFS=y
CONFIG_SQUASHFS_FILE_CACHE=y
# CONFIG_SQUASHFS_FILE_DIRECT is not set
CONFIG_SQUASHFS_DECOMP_SINGLE=y
# CONFIG_SQUASHFS_DECOMP_MULTI is not set
# CONFIG_SQUASHFS_DECOMP_MULTI_PERCPU is not set
CONFIG_SQUASHFS_XATTR=y
CONFIG_SQUASHFS_ZLIB=y
CONFIG_SQUASHFS_LZ4=y
CONFIG_SQUASHFS_LZO=y
CONFIG_SQUASHFS_XZ=y
CONFIG_SQUASHFS_ZSTD=y
CONFIG_SQUASHFS_4K_DEVBLK_SIZE=y
CONFIG_SQUASHFS_EMBEDDED=y
CONFIG_SQUASHFS_FRAGMENT_CACHE_SIZE=3
CONFIG_VXFS_FS=m
CONFIG_MINIX_FS=m
CONFIG_OMFS_FS=m
CONFIG_HPFS_FS=y
CONFIG_QNX4FS_FS=m
CONFIG_QNX6FS_FS=m
CONFIG_QNX6FS_DEBUG=y
CONFIG_ROMFS_FS=m
CONFIG_ROMFS_BACKED_BY_BLOCK=y
# CONFIG_ROMFS_BACKED_BY_MTD is not set
# CONFIG_ROMFS_BACKED_BY_BOTH is not set
CONFIG_ROMFS_ON_BLOCK=y
CONFIG_PSTORE=y
CONFIG_PSTORE_DEFLATE_COMPRESS=y
# CONFIG_PSTORE_LZO_COMPRESS is not set
# CONFIG_PSTORE_LZ4_COMPRESS is not set
# CONFIG_PSTORE_LZ4HC_COMPRESS is not set
# CONFIG_PSTORE_842_COMPRESS is not set
# CONFIG_PSTORE_ZSTD_COMPRESS is not set
CONFIG_PSTORE_LZO_COMPRESS=m
CONFIG_PSTORE_LZ4_COMPRESS=m
CONFIG_PSTORE_LZ4HC_COMPRESS=m
CONFIG_PSTORE_842_COMPRESS=y
CONFIG_PSTORE_ZSTD_COMPRESS=y
CONFIG_PSTORE_COMPRESS=y
CONFIG_PSTORE_DEFLATE_COMPRESS_DEFAULT=y
# CONFIG_PSTORE_LZO_COMPRESS_DEFAULT is not set
# CONFIG_PSTORE_LZ4_COMPRESS_DEFAULT is not set
# CONFIG_PSTORE_LZ4HC_COMPRESS_DEFAULT is not set
# CONFIG_PSTORE_842_COMPRESS_DEFAULT is not set
# CONFIG_PSTORE_ZSTD_COMPRESS_DEFAULT is not set
CONFIG_PSTORE_COMPRESS_DEFAULT="deflate"
CONFIG_PSTORE_CONSOLE=y
# CONFIG_PSTORE_PMSG is not set
CONFIG_PSTORE_PMSG=y
CONFIG_PSTORE_RAM=y
# CONFIG_PSTORE_BLK is not set
# CONFIG_SYSV_FS is not set
# CONFIG_UFS_FS is not set
# CONFIG_EROFS_FS is not set
CONFIG_PSTORE_ZONE=m
CONFIG_PSTORE_BLK=m
CONFIG_PSTORE_BLK_BLKDEV=""
CONFIG_PSTORE_BLK_KMSG_SIZE=64
CONFIG_PSTORE_BLK_MAX_REASON=2
CONFIG_PSTORE_BLK_PMSG_SIZE=64
CONFIG_PSTORE_BLK_CONSOLE_SIZE=64
CONFIG_SYSV_FS=m
CONFIG_UFS_FS=m
CONFIG_UFS_FS_WRITE=y
# CONFIG_UFS_DEBUG is not set
CONFIG_EROFS_FS=m
# CONFIG_EROFS_FS_DEBUG is not set
CONFIG_EROFS_FS_XATTR=y
CONFIG_EROFS_FS_POSIX_ACL=y
CONFIG_EROFS_FS_SECURITY=y
CONFIG_EROFS_FS_ZIP=y
CONFIG_EROFS_FS_CLUSTER_PAGE_LIMIT=1
CONFIG_NETWORK_FILESYSTEMS=y
CONFIG_NFS_FS=y
CONFIG_NFS_V2=y
@ -5678,7 +5843,7 @@ CONFIG_BIG_KEYS=y
# CONFIG_TRUSTED_KEYS is not set
CONFIG_ENCRYPTED_KEYS=y
CONFIG_KEY_DH_OPERATIONS=y
CONFIG_SECURITY_DMESG_RESTRICT=y
# CONFIG_SECURITY_DMESG_RESTRICT is not set
CONFIG_SECURITY=y
CONFIG_SECURITYFS=y
CONFIG_SECURITY_NETWORK=y
@ -5880,10 +6045,10 @@ CONFIG_CRYPTO_SM4=m
#
CONFIG_CRYPTO_DEFLATE=y
CONFIG_CRYPTO_LZO=y
# CONFIG_CRYPTO_842 is not set
# CONFIG_CRYPTO_LZ4 is not set
# CONFIG_CRYPTO_LZ4HC is not set
# CONFIG_CRYPTO_ZSTD is not set
CONFIG_CRYPTO_842=y
CONFIG_CRYPTO_LZ4=m
CONFIG_CRYPTO_LZ4HC=m
CONFIG_CRYPTO_ZSTD=y
#
# Random Number Generation
@ -5978,6 +6143,8 @@ CONFIG_AUDIT_GENERIC=y
CONFIG_AUDIT_ARCH_COMPAT_GENERIC=y
CONFIG_AUDIT_COMPAT_GENERIC=y
# CONFIG_RANDOM32_SELFTEST is not set
CONFIG_842_COMPRESS=y
CONFIG_842_DECOMPRESS=y
CONFIG_ZLIB_INFLATE=y
CONFIG_ZLIB_DEFLATE=y
CONFIG_LZO_COMPRESS=y
@ -6006,6 +6173,8 @@ CONFIG_GENERIC_ALLOCATOR=y
CONFIG_REED_SOLOMON=y
CONFIG_REED_SOLOMON_ENC8=y
CONFIG_REED_SOLOMON_DEC8=y
CONFIG_BCH=m
CONFIG_BCH_CONST_PARAMS=y
CONFIG_TEXTSEARCH=y
CONFIG_TEXTSEARCH_KMP=y
CONFIG_TEXTSEARCH_BM=y

1
external/config/optional/families/sun50iw9/_config/desktop/focal/environments/xfce/config_base/packages vendored
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@ -13,6 +13,7 @@ fcitx-table-cangjie
fcitx-table-wubi
fcitx-ui-classic
fcitx-ui-qimpanel
firefox
fonts-noto-cjk
fonts-noto-cjk-extra
geany

9
external/config/sources/families/sun50iw9.conf vendored
View File

@ -34,8 +34,8 @@ case $BRANCH in
OVERLAY_PREFIX='sun50i-h616'
KERNELBRANCH="branch:orange-pi-5.4-sun50iw9"
#BOOTBRANCH='branch:u-boot-2018'
BOOTBRANCH='branch:u-boot-2018-h618'
#BOOTBRANCH='branch:v2018.05-sun50iw9'
[[ $BOARD =~ orangepizero2 ]] && BOOTBRANCH='branch:v2018.05-sun50iw9'
[[ $BOARD =~ orangepizero3|orangepir1b|orangepizero2w ]] && BOOTBRANCH='branch:v2018.05-h618'
KERNELPATCHDIR=${BOARDFAMILY}-${BRANCH}
UBOOT_TARGET_MAP=";;dts/${BOARD}-u-boot.dts boot0_sdcard.fex boot_package.fex"
@ -60,7 +60,7 @@ case $BRANCH in
ATF_TARGET_MAP='PLAT=sun50i_h616 DEBUG=1 bl31;;build/sun50i_h616/debug/bl31.bin'
UBOOT_TARGET_MAP=';;u-boot-sunxi-with-spl.bin'
[[ $BOARD =~ orangepizero2 ]] && BOOTBRANCH='branch:v2021.10-sunxi'
[[ $BOARD =~ orangepizero3|orangepir1b ]] && BOOTBRANCH='v2021.07-sunxi'
[[ $BOARD =~ orangepizero3|orangepir1b|orangepizero2w ]] && BOOTBRANCH='v2021.07-sunxi'
BOOTSCRIPT='boot-sun50iw9-next.cmd:boot.cmd'
## For Linux5.16.y
@ -78,7 +78,7 @@ family_tweaks_s()
{
rsync -a --chown=root:root "${EXTER}"/packages/bsp/overlays_arm64/* ${SDCARD}/
chroot $SDCARD /bin/bash -c "apt-get -y -qq install rfkill bluetooth bluez bluez-tools ir-keytable tree lirc v4l-utils" >/dev/null 2>&1
chroot $SDCARD /bin/bash -c "apt-get -y -qq install rfkill bluetooth bluez bluez-tools ir-keytable tree lirc v4l-utils dnsmasq" >/dev/null 2>&1
if [[ $BUILD_DESKTOP == yes ]]; then
@ -124,6 +124,7 @@ uboot_custom_postprocess()
mv boot_package.cfg-linux5.4 boot_package.cfg
mv boot0_sdcard.fex-linux5.4 boot0_sdcard.fex
fi
cp dts/${BOARD}-u-boot-${BRANCH}.dts dts/${BOARD}-u-boot.dts
# make u-boot dtb
$EXTER/packages/pack-uboot/${BOARDFAMILY}/tools/dtc -p 2048 -W no-unit_address_vs_reg -@ -O dtb -o ${BOARD}-u-boot.dtb -b 0 dts/${BOARD}-u-boot-${BRANCH}.dts >/dev/null 2>&1

2
external/packages/bsp/common/usr/lib/orangepi/orangepi-hardware-optimization vendored
View File

@ -162,7 +162,7 @@ prepare_board() {
/usr/bin/pwm-fan.sh &
;;
orangepizero2|orangepizero2-lts|orangepizero2-b|orangepizero3|orangepir1b)
orangepizero2|orangepizero2-lts|orangepizero2-b|orangepizero3|orangepir1b|orangepizero2w)
kv=$(uname -r)
#if [[ $BRANCH == current ]]; then

BIN
external/packages/bsp/overlays_arm64/usr/bin/blink vendored Executable file
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4
external/packages/bsp/overlays_arm64/usr/bin/enable_docker.sh vendored
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@ -1,4 +1,8 @@
#!/bin/bash
if [[ $(uname -r) == 5.4.* ]]; then
echo 1 | sudo update-alternatives --config iptables > /dev/null
fi
sudo systemctl enable docker.service
sudo systemctl start docker.service

312
external/packages/pack-uboot/sun50iw9/bin/dts/orangepizero3-u-boot-current-pwm.dts → external/packages/pack-uboot/sun50iw9/bin/dts/orangepizero2w-u-boot-current.dts vendored
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@ -4,7 +4,7 @@
interrupt-parent = <0x1>;
#address-cells = <0x2>;
#size-cells = <0x2>;
model = "Orange Pi Zero 3";
model = "Orange Pi Zero2w";
compatible = "allwinner,h616", "arm,sun50iw9p1";
aliases {
@ -247,11 +247,11 @@
opp@1512000000 {
opp-hz = <0x0 0x5a1f4a00>;
opp-microvolt-a0 = <0x10c8e0>;
opp-microvolt-a1 = <0x10c8e0>;
opp-microvolt-a2 = <0x10c8e0>;
opp-microvolt-a3 = <0x10c8e0>;
opp-microvolt-a4 = <0x10c8e0>;
opp-microvolt-a0 = <0x118c30>;
opp-microvolt-a1 = <0x118c30>;
opp-microvolt-a2 = <0x118c30>;
opp-microvolt-a3 = <0x118c30>;
opp-microvolt-a4 = <0x118c30>;
clock-latency-ns = <0x3b9b0>;
opp-supported-hw = <0x1f>;
};
@ -719,9 +719,9 @@
reg = <0x0 0x0300a011 0x0 0x4>;
reg_base = <0x0300a000>;
pinctrl-names = "active", "sleep";
pinctrl-0 = <&pwm1_pin_a>;
pinctrl-1 = <&pwm1_pin_b>;
status = "okay";
pinctrl-0 = <&pwm1_pi_pin_a>;
pinctrl-1 = <&pwm1_pi_pin_b>;
status = "disabled";
};
pwm2: pwm2@300a012 {
@ -729,9 +729,9 @@
reg = <0x0 0x0300a012 0x0 0x4>;
reg_base = <0x0300a000>;
pinctrl-names = "active", "sleep";
pinctrl-0 = <&pwm2_pin_a>;
pinctrl-1 = <&pwm2_pin_b>;
status = "okay";
pinctrl-0 = <&pwm2_pi_pin_a>;
pinctrl-1 = <&pwm2_pi_pin_b>;
status = "disabled";
};
pwm3: pwm3@300a013 {
@ -739,9 +739,9 @@
reg = <0x0 0x0300a013 0x0 0x4>;
reg_base = <0x0300a000>;
pinctrl-names = "active", "sleep";
pinctrl-0 = <&pwm3_pin_a>;
pinctrl-1 = <&pwm3_pin_b>;
status = "okay";
pinctrl-0 = <&pwm3_pi_pin_a>;
pinctrl-1 = <&pwm3_pi_pin_b>;
status = "disabled";
};
pwm4: pwm4@300a014 {
@ -749,9 +749,9 @@
reg = <0x0 0x0300a014 0x0 0x4>;
reg_base = <0x0300a000>;
pinctrl-names = "active", "sleep";
pinctrl-0 = <&pwm4_pin_a>;
pinctrl-1 = <&pwm4_pin_b>;
status = "okay";
pinctrl-0 = <&pwm4_pi_pin_a>;
pinctrl-1 = <&pwm4_pi_pin_b>;
status = "disabled";
};
pwm5: pwm5@300a015 {
@ -790,14 +790,14 @@
vcc-pg-supply = <0x17>;
phandle = <0x23>;
uart0-ph-pins {
uart0_ph_pins_a: uart0-ph-pins {
pins = "PH0", "PH1";
function = "uart0";
bias-pull-up;
phandle = <0x29>;
};
uart0-ph-sleep {
uart0_ph_pins_b: uart0-ph-sleep {
pins = "PH0", "PH1";
function = "gpio_in";
phandle = <0x2a>;
@ -915,61 +915,67 @@
phandle = <0x28>;
};
uart1-ph-pins {
uart1_ph_pins_a: uart1-ph-pins {
pins = "PG6", "PG7", "PG8", "PG9";
function = "uart1";
phandle = <0x2b>;
};
uart1-ph-sleep {
uart1_ph_pins_b: uart1-ph-sleep {
pins = "PG6", "PG7", "PG8", "PG9";
function = "gpio_in";
phandle = <0x2c>;
};
uart2-ph-pins {
uart2_ph_pins_a: uart2-ph-pins {
pins = "PH5", "PH6";
function = "uart2";
phandle = <0x2d>;
};
uart2-ph-sleep {
uart2_pi_pins_a: uart2-pi-pins {
pins = "PI5", "PI6";
function = "uart2";
};
uart2_pi_pins_b: uart2-pi-sleep {
pins = "PI5", "PI6";
function = "gpio_in";
};
uart2_ph_pins_b: uart2-ph-sleep {
pins = "PH5", "PH6";
function = "gpio_in";
phandle = <0x2e>;
};
uart3-ph-pins {
uart3_pi_pins_a: uart3-pi-pins {
pins = "PI9", "PI10";
function = "uart3";
phandle = <0x2f>;
};
uart3-ph-sleep {
uart3_pi_pins_b: uart3-pi-sleep {
pins = "PI9", "PI10";
function = "gpio_in";
phandle = <0x30>;
};
uart4-ph-pins {
uart4_pi_pins_a: uart4-pi-pins {
pins = "PI13", "PI14";
function = "uart4";
phandle = <0x31>;
};
uart4-ph-sleep {
uart4_pi_pins_b: uart4-pi-sleep {
pins = "PI13", "PI14";
function = "gpio_in";
phandle = <0x32>;
};
uart5-ph-pins {
uart5_ph_pins_a: uart5-ph-pins {
pins = "PH2", "PH3";
function = "uart5";
phandle = <0x33>;
};
uart5-ph-sleep {
uart5_ph_pins_b: uart5-ph-sleep {
pins = "PH2", "PH3";
function = "gpio_in";
phandle = <0x34>;
@ -989,35 +995,44 @@
phandle = <0x65>;
};
twi0@0 {
twi0_pi_pins_a: twi0-pi-pins-a@0 {
pins = "PI5", "PI6";
function = "twi0";
drive-strength = <0xa>;
bias-pull-up;
phandle = <0x36>;
};
twi0@1 {
twi0_pi_pins_b: twi0-pi-pins-b@1 {
pins = "PI5", "PI6";
function = "gpio_in";
phandle = <0x37>;
};
twi1@0 {
twi1_ph_pins_a: twi1-ph-pins-a@0 {
pins = "PH0", "PH1";
function = "twi1";
drive-strength = <0xa>;
bias-pull-up;
phandle = <0x38>;
};
twi1@1 {
twi1_ph_pins_b: twi1-ph-pins-b@0 {
pins = "PH0", "PH1";
function = "gpio_in";
phandle = <0x39>;
};
twi2@0 {
twi1_pi_pins_a: twi1-pi-pins-a@0 {
pins = "PI7", "PI8";
function = "twi1";
drive-strength = <0xa>;
bias-pull-up;
};
twi1_pi_pins_b: twi1-pi-pins-b@0 {
pins = "PI7", "PI8";
function = "gpio_in";
};
twi2_ph_pins_a: twi2-ph-pins-a@0 {
pins = "PH2", "PH3";
function = "twi2";
drive-strength = <0xa>;
@ -1025,13 +1040,25 @@
phandle = <0x3a>;
};
twi2@1 {
twi2_ph_pins_b: twi2-ph-pins-b@0 {
pins = "PH2", "PH3";
function = "gpio_in";
phandle = <0x3b>;
};
twi3@0 {
twi2_pi_pins_a: twi2-pi-pins-a@0 {
pins = "PI9", "PI10";
function = "twi2";
drive-strength = <0xa>;
bias-pull-up;
};
twi2_pi_pins_b: twi2-pi-pins-b@0 {
pins = "PI9", "PI10";
function = "gpio_in";
};
twi3_ph_pins_a: twi3-ph-pins-a@0 {
pins = "PH4", "PH5";
function = "twi3";
drive-strength = <0xa>;
@ -1039,13 +1066,13 @@
phandle = <0x3c>;
};
twi3@1 {
twi3_ph_pins_b: twi3-ph-pins-b@0 {
pins = "PH4", "PH5";
function = "gpio_in";
phandle = <0x3d>;
};
twi4@0 {
twi4_ph_pins_a: twi4-ph-pins-a@0 {
pins = "PH6", "PH7";
function = "twi4";
drive-strength = <0xa>;
@ -1053,7 +1080,7 @@
phandle = <0x3e>;
};
twi4@1 {
twi4_ph_pins_b: twi4-ph-pins-b@0 {
pins = "PH6", "PH7";
function = "gpio_in";
phandle = <0x3f>;
@ -1081,26 +1108,30 @@
phandle = <0x44>;
};
spi1@0 {
spi1_pins_a: spi1-pins-a {
pins = "PH6", "PH7", "PH8";
function = "spi1";
drive-strength = <0x14>;
phandle = <0x45>;
};
spi1@1 {
spi1_cs0_pin: spi1-cs0-pin {
pins = "PH5";
function = "spi1";
drive-strength = <0x14>;
bias-pull-up;
};
spi1_cs1_pin: spi1-cs1-pin {
pins = "PH9";
function = "spi1";
drive-strength = <0x14>;
bias-pull-up;
phandle = <0x46>;
};
spi1@2 {
pins = "PH6", "PH7", "PH8", "PH9";
spi1_pins_b: spi1-pins-b {
pins = "PH6", "PH7", "PH8";
function = "gpio_in";
drive-strength = <0x14>;
phandle = <0x47>;
};
gmac0@0 {
@ -1135,66 +1166,114 @@
phandle = <0x61>;
};
pwm0_pin_a: pwm0@0 {
pwm0_pin_a: pwm0-pin-a@0 {
pins = "PD28";
function = "pwm0";
drive-strength = <10>;
bias-pull-up;
};
pwm0_pin_b: pwm0@1 {
pwm0_pin_b: pwm0-pin-b@0 {
pins = "PD28";
function = "gpio_in";
};
pwm1_pin_a: pwm1@0 {
pwm1_ph_pin_a: pwm1-ph-pin-a@0 {
pins = "PH3";
function = "pwm1";
drive-strength = <10>;
bias-pull-up;
};
pwm1_pin_b: pwm1@1 {
pwm1_ph_pin_b: pwm1-ph-pin-b@0 {
pins = "PH3";
function = "gpio_in";
};
pwm2_pin_a: pwm2@0 {
pwm2_ph_pin_a: pwm2-ph-pin-a@0 {
pins = "PH2";
function = "pwm2";
drive-strength = <10>;
bias-pull-up;
};
pwm2_pin_b: pwm2@1 {
pwm2_ph_pin_b: pwm2-ph-pin-b@0 {
pins = "PH2";
function = "gpio_in";
};
pwm3_pin_a: pwm3@0 {
pwm3_ph_pin_a: pwm3-ph-pin-a@0 {
pins = "PH0";
function = "pwm3";
drive-strength = <10>;
bias-pull-up;
};
pwm3_pin_b: pwm3@1 {
pwm3_ph_pin_b: pwm3-ph-pin-b@0 {
pins = "PH0";
function = "gpio_in";
};
pwm4_pin_a: pwm4@0 {
pwm4_ph_pin_a: pwm4-ph-pin-a@0 {
pins = "PH1";
function = "pwm4";
drive-strength = <10>;
bias-pull-up;
};
pwm4_pin_b: pwm4@1 {
pwm4_ph_pin_b: pwm4-ph-pin-b@0 {
pins = "PH1";
function = "gpio_in";
};
pwm1_pi_pin_a: pwm1-pi-pin-a@0 {
pins = "PI11";
function = "pwm1";
drive-strength = <10>;
bias-pull-up;
};
pwm1_pi_pin_b: pwm1-pi-pin-b@0 {
pins = "PI11";
function = "gpio_in";
};
pwm2_pi_pin_a: pwm2-pi-pin-a@0 {
pins = "PI12";
function = "pwm2";
drive-strength = <10>;
bias-pull-up;
};
pwm2_pi_pin_b: pwm2-pi-pin-b@0 {
pins = "PI12";
function = "gpio_in";
};
pwm3_pi_pin_a: pwm3-pi-pin-a@0 {
pins = "PI13";
function = "pwm3";
drive-strength = <10>;
bias-pull-up;
};
pwm3_pi_pin_b: pwm3-pi-pin-b@0 {
pins = "PI13";
function = "gpio_in";
};
pwm4_pi_pin_a: pwm4-pi-pin-a@0 {
pins = "PI14";
function = "pwm4";
drive-strength = <10>;
bias-pull-up;
};
pwm4_pi_pin_b: pwm4-pi-pin-b@0 {
pins = "PI14";
function = "gpio_in";
};
pwm5_pin_a: pwm5@0 {
pins = "PA12";
function = "pwm5";
@ -1516,7 +1595,7 @@
phandle = <0x99>;
};
uart@5000000 {
uart0: uart@5000000 {
compatible = "allwinner,sun50i-uart";
reg = <0x0 0x5000000 0x0 0x400>;
interrupts = <0x0 0x0 0x4>;
@ -1524,14 +1603,14 @@
resets = <0x2 0x11>;
uart0_port = <0x0>;
uart0_type = <0x2>;
status = "disabled";
status = "okay";
pinctrl-names = "default", "sleep";
pinctrl-0 = <0x29>;
pinctrl-1 = <0x2a>;
phandle = <0x9a>;
};
uart@5000400 {
uart1: uart@5000400 {
compatible = "allwinner,sun50i-uart";
reg = <0x0 0x5000400 0x0 0x400>;
interrupts = <0x0 0x1 0x4>;
@ -1548,7 +1627,7 @@
phandle = <0x9b>;
};
uart@5000800 {
uart2: uart@5000800 {
compatible = "allwinner,sun50i-uart";
reg = <0x0 0x5000800 0x0 0x400>;
interrupts = <0x0 0x2 0x4>;
@ -1564,7 +1643,7 @@
phandle = <0x9c>;
};
uart@5000c00 {
uart3: uart@5000c00 {
compatible = "allwinner,sun50i-uart";
reg = <0x0 0x5000c00 0x0 0x400>;
interrupts = <0x0 0x3 0x4>;
@ -1580,7 +1659,7 @@
phandle = <0x9d>;
};
uart@5001000 {
uart4: uart@5001000 {
compatible = "allwinner,sun50i-uart";
reg = <0x0 0x5001000 0x0 0x400>;
interrupts = <0x0 0x4 0x4>;
@ -1596,7 +1675,7 @@
phandle = <0x9e>;
};
uart@5001400 {
uart5: uart@5001400 {
compatible = "allwinner,sun50i-uart";
reg = <0x0 0x5001400 0x0 0x400>;
interrupts = <0x0 0x5 0x4>;
@ -1612,7 +1691,7 @@
phandle = <0x9f>;
};
twi@5002000 {
twi0: twi@5002000 {
#address-cells = <0x1>;
#size-cells = <0x0>;
compatible = "allwinner,sun50i-twi";
@ -1639,7 +1718,7 @@
};
};
twi@5002400 {
twi1: twi@5002400 {
#address-cells = <0x1>;
#size-cells = <0x0>;
compatible = "allwinner,sun50i-twi";
@ -1660,7 +1739,7 @@
phandle = <0xa1>;
};
twi@5002800 {
twi2: twi@5002800 {
#address-cells = <0x1>;
#size-cells = <0x0>;
compatible = "allwinner,sun50i-twi";
@ -1681,7 +1760,7 @@
phandle = <0xa2>;
};
twi@5002c00 {
twi3: twi@5002c00 {
#address-cells = <0x1>;
#size-cells = <0x0>;
compatible = "allwinner,sun50i-twi";
@ -1693,7 +1772,7 @@
resets = <0x2 0x1a>;
dmas = <0x35 0x2e 0x35 0x2e>;
dma-names = "tx", "rx";
status = "okay";
status = "disabled";
clock-frequency = <0x61a80>;
pinctrl-0 = <0x3c>;
pinctrl-1 = <0x3d>;
@ -1702,7 +1781,7 @@
phandle = <0xa3>;
};
twi@5003000 {
twi4: twi@5003000 {
#address-cells = <0x1>;
#size-cells = <0x0>;
compatible = "allwinner,sun50i-twi";
@ -1723,7 +1802,7 @@
phandle = <0xa4>;
};
twi@7081400 {
twi5: twi@7081400 {
#address-cells = <0x1>;
#size-cells = <0x0>;
compatible = "allwinner,sun50i-twi";
@ -1815,7 +1894,7 @@
};
};
spi@5010000 {
spi0: spi@5010000 {
#address-cells = <0x1>;
#size-cells = <0x0>;
compatible = "allwinner,sun50i-spi";
@ -1845,11 +1924,20 @@
compatible = "rohm,dh2228fv";
spi-max-frequency = <0x10000000>;
reg = <0x0>;
status = "disabled";
};
flash@0 {
status = "okay";
#address-cells = <1>;
#size-cells = <1>;
compatible = "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <0x10000000>;
};
};
spi@5011000 {
spi1: spi@5011000 {
#address-cells = <0x1>;
#size-cells = <0x0>;
compatible = "allwinner,sun50i-spi";
@ -1864,7 +1952,7 @@
spi1_cs_bitmap = <0x2>;
dmas = <0x35 0x17 0x35 0x17>;
dma-names = "tx", "rx";
status = "okay";
status = "disabled";
spi_slave_mode = <0x0>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <0x45 0x46>;
@ -1872,13 +1960,13 @@
/*spi_dbi_enable = <0x0>;*/
phandle = <0xaa>;
spi_board1@1 {
device_type = "spi_board1";
compatible = "rohm,dh2228fv";
spi-max-frequency = <0x989680>;
reg = <0x1>;
status = "okay";
};
//spi_board1: spi_board1@1 {
// device_type = "spi_board1";
// compatible = "rohm,dh2228fv";
// spi-max-frequency = <0x989680>;
// reg = <0x1>;
// status = "disabled";
//};
};
thermal-sensor@5070400 {
@ -2016,7 +2104,7 @@
ahub_dam_mach {
compatible = "allwinner,sunxi-snd-mach";
soundcard-mach,name = "ahubdam";
status = "disabled";
status = "okay";
phandle = <0xaf>;
soundcard-mach,cpu {
@ -2265,19 +2353,14 @@
};
};
leds {
leds: leds {
compatible = "gpio-leds";
status = "okay";
power {
label = "red_led";
gpios = <0x23 0x2 0xc 0x1>; /* PC12 */
default-state = "on";
};
status {
led-green {
label = "green_led";
gpios = <0x23 0x2 0xd 0x1>; /* PC13 */
default-state = "off";
gpios = <0x23 0x2 0xd 0x0>; /* PC13 */
linux,default-trigger = "heartbeat";
};
};
@ -2305,7 +2388,7 @@
gmac-power0;
gmac-power1;
gmac-power2;
status = "okay";
status = "disabled";
use_ephy25m = <0x0>;
pinctrl-0 = <0x5e>;
pinctrl-1 = <0x5f>;
@ -2569,7 +2652,7 @@
clocks = <0xd 0x8 0xa 0xd 0x7>;
clock-names = "bus", "pclk", "mclk";
resets = <0xd 0x3>;
status = "okay";
status = "disabled";
s_cir0_used = <0x1>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <0x64>;
@ -2933,13 +3016,13 @@
cryptoengine = "/soc@3000000/ce@1904000";
soc_timer0 = "/soc@3000000/timer@3009000";
wdt = "/soc@3000000/watchdog@30090a0";
pwm = "/soc@3000000/pwm@300a000";
/*pwm = "/soc@3000000/pwm@300a000";
pwm0 = "/soc@3000000/pwm0@300a010";
pwm1 = "/soc@3000000/pwm1@300a011";
pwm2 = "/soc@3000000/pwm2@300a012";
pwm3 = "/soc@3000000/pwm3@300a013";
pwm4 = "/soc@3000000/pwm4@300a014";
pwm5 = "/soc@3000000/pwm5@300a015";
pwm5 = "/soc@3000000/pwm5@300a015";*/
ac200 = "/soc@3000000/ac200";
pio = "/soc@3000000/pinctrl@300b000";
uart0_ph_pins = "/soc@3000000/pinctrl@300b000/uart0-ph-pins";
@ -2961,10 +3044,6 @@
uart1_ph_sleep = "/soc@3000000/pinctrl@300b000/uart1-ph-sleep";
uart2_ph_pins = "/soc@3000000/pinctrl@300b000/uart2-ph-pins";
uart2_ph_sleep = "/soc@3000000/pinctrl@300b000/uart2-ph-sleep";
uart3_ph_pins = "/soc@3000000/pinctrl@300b000/uart3-ph-pins";
uart3_ph_sleep = "/soc@3000000/pinctrl@300b000/uart3-ph-sleep";
uart4_ph_pins = "/soc@3000000/pinctrl@300b000/uart4-ph-pins";
uart4_ph_sleep = "/soc@3000000/pinctrl@300b000/uart4-ph-sleep";
uart5_ph_pins = "/soc@3000000/pinctrl@300b000/uart5-ph-pins";
uart5_ph_sleep = "/soc@3000000/pinctrl@300b000/uart5-ph-sleep";
s_cir0_pins_a = "/soc@3000000/pinctrl@300b000/s_cir0@0";
@ -2982,15 +3061,16 @@
spi0_pins_a = "/soc@3000000/pinctrl@300b000/spi0@0";
spi0_pins_b = "/soc@3000000/pinctrl@300b000/spi0@1";
spi0_pins_c = "/soc@3000000/pinctrl@300b000/spi0@2";
spi1_pins_a = "/soc@3000000/pinctrl@300b000/spi1@0";
spi1_pins_b = "/soc@3000000/pinctrl@300b000/spi1@1";
spi1_pins_c = "/soc@3000000/pinctrl@300b000/spi1@2";
spi1_pins_a = "/soc@3000000/pinctrl@300b000/spi1-pins-a";
spi1_pins_b = "/soc@3000000/pinctrl@300b000/spi1-pins-b";
spi1_cs0_pin = "/soc@3000000/pinctrl@300b000/spi1-cs0-pin";
spi1_cs1_pin = "/soc@3000000/pinctrl@300b000/spi1-cs1-pin";
gmac0_pins_a = "/soc@3000000/pinctrl@300b000/gmac0@0";
gmac0_pins_b = "/soc@3000000/pinctrl@300b000/gmac0@1";
gmac1_pins_a = "/soc@3000000/pinctrl@300b000/gmac1@0";
gmac1_pins_b = "/soc@3000000/pinctrl@300b000/gmac1@1";
pwm5_pin_a = "/soc@3000000/pinctrl@300b000/pwm5@0";
pwm5_pin_b = "/soc@3000000/pinctrl@300b000/pwm5@1";
//pwm5_pin_a = "/soc@3000000/pinctrl@300b000/pwm5@0";
//pwm5_pin_b = "/soc@3000000/pinctrl@300b000/pwm5@1";
spdif_pins_a = "/soc@3000000/pinctrl@300b000/spdif@0";
spdif_pins_b = "/soc@3000000/pinctrl@300b000/spdif_sleep@0";
ahub_daudio0_pins_a = "/soc@3000000/pinctrl@300b000/ahub_daudio0@0";
@ -3015,7 +3095,7 @@
sdc1 = "/soc@3000000/sdmmc@4021000";
nand0 = "/soc@3000000/nand0@4011000";
mbus0 = "/soc@3000000/mbus-controller@47fa000";
uart0 = "/soc@3000000/uart@5000000";
/*uart0 = "/soc@3000000/uart@5000000";
uart1 = "/soc@3000000/uart@5000400";
uart2 = "/soc@3000000/uart@5000800";
uart3 = "/soc@3000000/uart@5000c00";
@ -3026,7 +3106,7 @@
twi2 = "/soc@3000000/twi@5002800";
twi3 = "/soc@3000000/twi@5002c00";
twi4 = "/soc@3000000/twi@5003000";
twi5 = "/soc@3000000/twi@7081400";
twi5 = "/soc@3000000/twi@7081400";*/
pmu0 = "/soc@3000000/twi@7081400/pmu";
standby_param = "/soc@3000000/twi@7081400/pmu/standby_param";
reg_dcdc1 = "/soc@3000000/twi@7081400/pmu/regulators/dcdc1";
@ -3034,8 +3114,8 @@
reg_dcdc3 = "/soc@3000000/twi@7081400/pmu/regulators/dcdc3";
reg_aldo1 = "/soc@3000000/twi@7081400/pmu/regulators/ldo1";
reg_dldo1 = "/soc@3000000/twi@7081400/pmu/regulators/ldo2";
spi0 = "/soc@3000000/spi@5010000";
spi1 = "/soc@3000000/spi@5011000";
/*spi0 = "/soc@3000000/spi@5010000";
spi1 = "/soc@3000000/spi@5011000";*/
ths = "/soc@3000000/thermal-sensor@5070400";
gpadc = "/soc@3000000/gpadc@5070000";
keyboard = "/soc@3000000/keyboard@5070800";

213
external/packages/pack-uboot/sun50iw9/bin/dts/orangepizero3-u-boot-current.dts vendored Normal file → Executable file
View File

@ -719,8 +719,8 @@
reg = <0x0 0x0300a011 0x0 0x4>;
reg_base = <0x0300a000>;
pinctrl-names = "active", "sleep";
pinctrl-0 = <&pwm1_pin_a>;
pinctrl-1 = <&pwm1_pin_b>;
pinctrl-0 = <&pwm1_ph_pin_a>;
pinctrl-1 = <&pwm1_ph_pin_b>;
status = "disabled";
};
@ -729,8 +729,8 @@
reg = <0x0 0x0300a012 0x0 0x4>;
reg_base = <0x0300a000>;
pinctrl-names = "active", "sleep";
pinctrl-0 = <&pwm2_pin_a>;
pinctrl-1 = <&pwm2_pin_b>;
pinctrl-0 = <&pwm2_ph_pin_a>;
pinctrl-1 = <&pwm2_ph_pin_b>;
status = "disabled";
};
@ -739,8 +739,8 @@
reg = <0x0 0x0300a013 0x0 0x4>;
reg_base = <0x0300a000>;
pinctrl-names = "active", "sleep";
pinctrl-0 = <&pwm3_pin_a>;
pinctrl-1 = <&pwm3_pin_b>;
pinctrl-0 = <&pwm3_ph_pin_a>;
pinctrl-1 = <&pwm3_ph_pin_b>;
status = "disabled";
};
@ -749,8 +749,8 @@
reg = <0x0 0x0300a014 0x0 0x4>;
reg_base = <0x0300a000>;
pinctrl-names = "active", "sleep";
pinctrl-0 = <&pwm4_pin_a>;
pinctrl-1 = <&pwm4_pin_b>;
pinctrl-0 = <&pwm4_ph_pin_a>;
pinctrl-1 = <&pwm4_ph_pin_b>;
status = "disabled";
};
@ -790,14 +790,14 @@
vcc-pg-supply = <0x17>;
phandle = <0x23>;
uart0-ph-pins {
uart0_ph_pins_a: uart0-ph-pins {
pins = "PH0", "PH1";
function = "uart0";
bias-pull-up;
phandle = <0x29>;
};
uart0-ph-sleep {
uart0_ph_pins_b: uart0-ph-sleep {
pins = "PH0", "PH1";
function = "gpio_in";
phandle = <0x2a>;
@ -915,61 +915,67 @@
phandle = <0x28>;
};
uart1-ph-pins {
uart1_ph_pins_a: uart1-ph-pins {
pins = "PG6", "PG7", "PG8", "PG9";
function = "uart1";
phandle = <0x2b>;
};
uart1-ph-sleep {
uart1_ph_pins_b: uart1-ph-sleep {
pins = "PG6", "PG7", "PG8", "PG9";
function = "gpio_in";
phandle = <0x2c>;
};
uart2-ph-pins {
uart2_ph_pins_a: uart2-ph-pins {
pins = "PH5", "PH6";
function = "uart2";
phandle = <0x2d>;
};
uart2-ph-sleep {
uart2_pi_pins_a: uart2-pi-pins {
pins = "PI5", "PI6";
function = "uart2";
};
uart2_pi_pins_b: uart2-pi-sleep {
pins = "PI5", "PI6";
function = "gpio_in";
};
uart2_ph_pins_b: uart2-ph-sleep {
pins = "PH5", "PH6";
function = "gpio_in";
phandle = <0x2e>;
};
uart3-ph-pins {
uart3_pi_pins_a: uart3-pi-pins {
pins = "PI9", "PI10";
function = "uart3";
phandle = <0x2f>;
};
uart3-ph-sleep {
uart3_pi_pins_b: uart3-pi-sleep {
pins = "PI9", "PI10";
function = "gpio_in";
phandle = <0x30>;
};
uart4-ph-pins {
uart4_pi_pins_a: uart4-pi-pins {
pins = "PI13", "PI14";
function = "uart4";
phandle = <0x31>;
};
uart4-ph-sleep {
uart4_pi_pins_b: uart4-pi-sleep {
pins = "PI13", "PI14";
function = "gpio_in";
phandle = <0x32>;
};
uart5-ph-pins {
uart5_ph_pins_a: uart5-ph-pins {
pins = "PH2", "PH3";
function = "uart5";
phandle = <0x33>;
};
uart5-ph-sleep {
uart5_ph_pins_b: uart5-ph-sleep {
pins = "PH2", "PH3";
function = "gpio_in";
phandle = <0x34>;
@ -989,35 +995,44 @@
phandle = <0x65>;
};
twi0@0 {
twi0_pi_pins_a: twi0-pi-pins-a@0 {
pins = "PI5", "PI6";
function = "twi0";
drive-strength = <0xa>;
bias-pull-up;
phandle = <0x36>;
};
twi0@1 {
twi0_pi_pins_b: twi0-pi-pins-b@1 {
pins = "PI5", "PI6";
function = "gpio_in";
phandle = <0x37>;
};
twi1@0 {
twi1_ph_pins_a: twi1-ph-pins-a@0 {
pins = "PH0", "PH1";
function = "twi1";
drive-strength = <0xa>;
bias-pull-up;
phandle = <0x38>;
};
twi1@1 {
twi1_ph_pins_b: twi1-ph-pins-b@0 {
pins = "PH0", "PH1";
function = "gpio_in";
phandle = <0x39>;
};
twi2@0 {
twi1_pi_pins_a: twi1-pi-pins-a@0 {
pins = "PI7", "PI8";
function = "twi1";
drive-strength = <0xa>;
bias-pull-up;
};
twi1_pi_pins_b: twi1-pi-pins-b@0 {
pins = "PI7", "PI8";
function = "gpio_in";
};
twi2_ph_pins_a: twi2-ph-pins-a@0 {
pins = "PH2", "PH3";
function = "twi2";
drive-strength = <0xa>;
@ -1025,13 +1040,25 @@
phandle = <0x3a>;
};
twi2@1 {
twi2_ph_pins_b: twi2-ph-pins-b@0 {
pins = "PH2", "PH3";
function = "gpio_in";
phandle = <0x3b>;
};
twi3@0 {
twi2_pi_pins_a: twi2-pi-pins-a@0 {
pins = "PI9", "PI10";
function = "twi2";
drive-strength = <0xa>;
bias-pull-up;
};
twi2_pi_pins_b: twi2-pi-pins-b@0 {
pins = "PI9", "PI10";
function = "gpio_in";
};
twi3_ph_pins_a: twi3-ph-pins-a@0 {
pins = "PH4", "PH5";
function = "twi3";
drive-strength = <0xa>;
@ -1039,13 +1066,13 @@
phandle = <0x3c>;
};
twi3@1 {
twi3_ph_pins_b: twi3-ph-pins-b@0 {
pins = "PH4", "PH5";
function = "gpio_in";
phandle = <0x3d>;
};
twi4@0 {
twi4_ph_pins_a: twi4-ph-pins-a@0 {
pins = "PH6", "PH7";
function = "twi4";
drive-strength = <0xa>;
@ -1053,7 +1080,7 @@
phandle = <0x3e>;
};
twi4@1 {
twi4_ph_pins_b: twi4-ph-pins-b@0 {
pins = "PH6", "PH7";
function = "gpio_in";
phandle = <0x3f>;
@ -1135,66 +1162,114 @@
phandle = <0x61>;
};
pwm0_pin_a: pwm0@0 {
pwm0_pin_a: pwm0-pin-a@0 {
pins = "PD28";
function = "pwm0";
drive-strength = <10>;
bias-pull-up;
};
pwm0_pin_b: pwm0@1 {
pwm0_pin_b: pwm0-pin-b@0 {
pins = "PD28";
function = "gpio_in";
};
pwm1_pin_a: pwm1@0 {
pwm1_ph_pin_a: pwm1-ph-pin-a@0 {
pins = "PH3";
function = "pwm1";
drive-strength = <10>;
bias-pull-up;
};
pwm1_pin_b: pwm1@1 {
pwm1_ph_pin_b: pwm1-ph-pin-b@0 {
pins = "PH3";
function = "gpio_in";
};
pwm2_pin_a: pwm2@0 {
pwm2_ph_pin_a: pwm2-ph-pin-a@0 {
pins = "PH2";
function = "pwm2";
drive-strength = <10>;
bias-pull-up;
};
pwm2_pin_b: pwm2@1 {
pwm2_ph_pin_b: pwm2-ph-pin-b@0 {
pins = "PH2";
function = "gpio_in";
};
pwm3_pin_a: pwm3@0 {
pwm3_ph_pin_a: pwm3-ph-pin-a@0 {
pins = "PH0";
function = "pwm3";
drive-strength = <10>;
bias-pull-up;
};
pwm3_pin_b: pwm3@1 {
pwm3_ph_pin_b: pwm3-ph-pin-b@0 {
pins = "PH0";
function = "gpio_in";
};
pwm4_pin_a: pwm4@0 {
pwm4_ph_pin_a: pwm4-ph-pin-a@0 {
pins = "PH1";
function = "pwm4";
drive-strength = <10>;
bias-pull-up;
};
pwm4_pin_b: pwm4@1 {
pwm4_ph_pin_b: pwm4-ph-pin-b@0 {
pins = "PH1";
function = "gpio_in";
};
pwm1_pi_pin_a: pwm1-pi-pin-a@0 {
pins = "PI11";
function = "pwm1";
drive-strength = <10>;
bias-pull-up;
};
pwm1_pi_pin_b: pwm1-pi-pin-b@0 {
pins = "PI11";
function = "gpio_in";
};
pwm2_pi_pin_a: pwm2-pi-pin-a@0 {
pins = "PI12";
function = "pwm2";
drive-strength = <10>;
bias-pull-up;
};
pwm2_pi_pin_b: pwm2-pi-pin-b@0 {
pins = "PI12";
function = "gpio_in";
};
pwm3_pi_pin_a: pwm3-pi-pin-a@0 {
pins = "PI13";
function = "pwm3";
drive-strength = <10>;
bias-pull-up;
};
pwm3_pi_pin_b: pwm3-pi-pin-b@0 {
pins = "PI13";
function = "gpio_in";
};
pwm4_pi_pin_a: pwm4-pi-pin-a@0 {
pins = "PI14";
function = "pwm4";
drive-strength = <10>;
bias-pull-up;
};
pwm4_pi_pin_b: pwm4-pi-pin-b@0 {
pins = "PI14";
function = "gpio_in";
};
pwm5_pin_a: pwm5@0 {
pins = "PA12";
function = "pwm5";
@ -1845,7 +1920,16 @@
compatible = "rohm,dh2228fv";
spi-max-frequency = <0x10000000>;
reg = <0x0>;
status = "disabled";
};
flash@0 {
status = "okay";
#address-cells = <1>;
#size-cells = <1>;
compatible = "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <0x10000000>;
};
};
@ -2265,19 +2349,20 @@
};
};
leds {
leds: leds {
compatible = "gpio-leds";
status = "okay";
power {
led-red {
label = "red_led";
gpios = <0x23 0x2 0xc 0x1>; /* PC12 */
default-state = "on";
gpios = <0x23 0x2 0xc 0x0>; /* PC12 */
linux,default-trigger = "none";
};
status {
led-green {
label = "green_led";
gpios = <0x23 0x2 0xd 0x1>; /* PC13 */
default-state = "off";
gpios = <0x23 0x2 0xd 0x0>; /* PC13 */
linux,default-trigger = "heartbeat";
};
};
@ -2933,13 +3018,13 @@
cryptoengine = "/soc@3000000/ce@1904000";
soc_timer0 = "/soc@3000000/timer@3009000";
wdt = "/soc@3000000/watchdog@30090a0";
pwm = "/soc@3000000/pwm@300a000";
/*pwm = "/soc@3000000/pwm@300a000";
pwm0 = "/soc@3000000/pwm0@300a010";
pwm1 = "/soc@3000000/pwm1@300a011";
pwm2 = "/soc@3000000/pwm2@300a012";
pwm3 = "/soc@3000000/pwm3@300a013";
pwm4 = "/soc@3000000/pwm4@300a014";
pwm5 = "/soc@3000000/pwm5@300a015";
pwm5 = "/soc@3000000/pwm5@300a015";*/
ac200 = "/soc@3000000/ac200";
pio = "/soc@3000000/pinctrl@300b000";
uart0_ph_pins = "/soc@3000000/pinctrl@300b000/uart0-ph-pins";
@ -2961,10 +3046,6 @@
uart1_ph_sleep = "/soc@3000000/pinctrl@300b000/uart1-ph-sleep";
uart2_ph_pins = "/soc@3000000/pinctrl@300b000/uart2-ph-pins";
uart2_ph_sleep = "/soc@3000000/pinctrl@300b000/uart2-ph-sleep";
uart3_ph_pins = "/soc@3000000/pinctrl@300b000/uart3-ph-pins";
uart3_ph_sleep = "/soc@3000000/pinctrl@300b000/uart3-ph-sleep";
uart4_ph_pins = "/soc@3000000/pinctrl@300b000/uart4-ph-pins";
uart4_ph_sleep = "/soc@3000000/pinctrl@300b000/uart4-ph-sleep";
uart5_ph_pins = "/soc@3000000/pinctrl@300b000/uart5-ph-pins";
uart5_ph_sleep = "/soc@3000000/pinctrl@300b000/uart5-ph-sleep";
s_cir0_pins_a = "/soc@3000000/pinctrl@300b000/s_cir0@0";
@ -2989,8 +3070,8 @@
gmac0_pins_b = "/soc@3000000/pinctrl@300b000/gmac0@1";
gmac1_pins_a = "/soc@3000000/pinctrl@300b000/gmac1@0";
gmac1_pins_b = "/soc@3000000/pinctrl@300b000/gmac1@1";
pwm5_pin_a = "/soc@3000000/pinctrl@300b000/pwm5@0";
pwm5_pin_b = "/soc@3000000/pinctrl@300b000/pwm5@1";
//pwm5_pin_a = "/soc@3000000/pinctrl@300b000/pwm5@0";
//pwm5_pin_b = "/soc@3000000/pinctrl@300b000/pwm5@1";
spdif_pins_a = "/soc@3000000/pinctrl@300b000/spdif@0";
spdif_pins_b = "/soc@3000000/pinctrl@300b000/spdif_sleep@0";
ahub_daudio0_pins_a = "/soc@3000000/pinctrl@300b000/ahub_daudio0@0";
@ -3015,7 +3096,7 @@
sdc1 = "/soc@3000000/sdmmc@4021000";
nand0 = "/soc@3000000/nand0@4011000";
mbus0 = "/soc@3000000/mbus-controller@47fa000";
uart0 = "/soc@3000000/uart@5000000";
/*uart0 = "/soc@3000000/uart@5000000";
uart1 = "/soc@3000000/uart@5000400";
uart2 = "/soc@3000000/uart@5000800";
uart3 = "/soc@3000000/uart@5000c00";
@ -3026,7 +3107,7 @@
twi2 = "/soc@3000000/twi@5002800";
twi3 = "/soc@3000000/twi@5002c00";
twi4 = "/soc@3000000/twi@5003000";
twi5 = "/soc@3000000/twi@7081400";
twi5 = "/soc@3000000/twi@7081400";*/
pmu0 = "/soc@3000000/twi@7081400/pmu";
standby_param = "/soc@3000000/twi@7081400/pmu/standby_param";
reg_dcdc1 = "/soc@3000000/twi@7081400/pmu/regulators/dcdc1";
@ -3034,8 +3115,8 @@
reg_dcdc3 = "/soc@3000000/twi@7081400/pmu/regulators/dcdc3";
reg_aldo1 = "/soc@3000000/twi@7081400/pmu/regulators/ldo1";
reg_dldo1 = "/soc@3000000/twi@7081400/pmu/regulators/ldo2";
spi0 = "/soc@3000000/spi@5010000";
spi1 = "/soc@3000000/spi@5011000";
/*spi0 = "/soc@3000000/spi@5010000";
spi1 = "/soc@3000000/spi@5011000";*/
ths = "/soc@3000000/thermal-sensor@5070400";
gpadc = "/soc@3000000/gpadc@5070000";
keyboard = "/soc@3000000/keyboard@5070800";

3040
external/packages/pack-uboot/sun50iw9/bin/dts/orangepizero3-u-boot.dts vendored
View File

File diff suppressed because it is too large Load Diff

845
external/packages/pack-uboot/sun50iw9/bin/sys_config/sys_config_orangepizero2w.fex vendored Executable file
View File

@ -0,0 +1,845 @@
;sunxi platform application
;---------------------------------------------------------------------------------------------------------
; 说明： 脚本中的字符串区分大小写，用户可以修改"="后面的数值，但是不要修改前面的字符串
; 描述gpio的形式：Port:端口+组内序号<功能分配><内部电阻状态><驱动能力><输出电平状态>
;---------------------------------------------------------------------------------------------------------
[product]
version = "100"
machine = "orangepizero3"
[platform]
eraseflag = 1
debug_mode = 3
;----------------------------------------------------------------------------------
;[target] system bootup configuration
;boot_clock = CPU boot frequency, Unit: MHz
;storage_type = boot medium, 0-nand, 1-card0, 2-card2, -1(defualt)auto scan
;advert_enable = 0-close advert logo 1-open advert logo (只有多核启动下有效)
;----------------------------------------------------------------------------------
[target]
boot_clock = 1008
storage_type = -1
advert_enable = 0
burn_key = 1
dragonboard_test= 0
;----------------------------------------------------------------------------------
; system configuration
; ?
;dcdc2_vol ---set dcdc2 voltage,mV,500-1200,10mV/step
; 1220-1540,20mV/step
;aldo1_vol ---set aldo1 voltage,mV,500-3500,100mV/step
;dldo1_vol ---set dldo1 voltage,mV,500-3500,100mV/step
;----------------------------------------------------------------------------------
[power_sply]
dcdc2_vol = 1001000
aldo1_vol = 1001800
dldo1_vol = 1003300
cldo1_vol = 1001800
[axp1530_power_sply]
dcdc2_vol = 1001000
aldo1_vol = 1001800
dldo1_vol = 1003300
cldo1_vol = 1001800
[axp806_power_sply]
dcdce_vol = 1003300
;dcdcd_vol = 1001110
aldo1_vol = 1003300
bldo1_vol = 1001800
bldo2_vol = 1001800
cldo1_vol = 1001800
[card_boot]
logical_start = 40960
sprite_gpio0 =
;----------------------------------------------------------------------------------
; ir_boot_recovery_used : 1: used this function 0: not used
; ir_work_mode : 模式选择
; 0: 刷机,
; 1: 一键恢复(uboot阶段),
; 2: 安卓recovery,
; 3: 安卓恢复出厂设置.
; 如果不设置，默认为安卓recovery .
; ir_press_times : ir遥控器连续按几次才生效,如果不设置默认为按1次生效
; ir_detect_time : ir遥控检测时间,单位:ms,如果不设置默认为3000ms
; ir_key_no_duplicate : ir遥控按键是否可重复，0：可重复(默认)，1：不可重复；
; 不可重复表示一个按键无论被按下几次，都只算ir_press_times的一次；
; 不可重复的应用场景为组合按键功能，如:交替按下'菜单键'和'音量-键'进入安卓recovery.
; ir_recovery_key_code0 : ir check key code
; ir_addr_code0 : ir key addr
; you can increase ir support num, like:
; ir_recovery_key_code1, or 2, 3, but limit to 16
;----------------------------------------------------------------------------------
[ir_boot_recovery]
ir_boot_recovery_used = 1
ir_work_mode = 1
ir_press_times = 2
ir_detect_time = 1
ir_key_no_duplicate = 0
ir_recovery_key_code0 = 0x11
ir_addr_code0 = 0xfe01
ir_recovery_key_code1 = 0x19
ir_addr_code1 = 0xfe01
ir_recovery_key_code2 = 0x4c
ir_addr_code2 = 0xfe01
ir_recovery_key_code3 = 0x00
ir_addr_code3 = 0xfe01
;----------------------------------------------------------------------------------
; recovery_key_used : 模块使能端， 1：开启，0：关闭
; press_mode_enable : 长短按模式使能，1：开启，0：关闭
; a)如果开启了该模式，则key_work_mode失效，short_press_mode和long_press_mode生>效,
; recovery按键可以通过长按和短按来触发两种不同的模式;
; b)如果关闭了该模式，则key_work_mode生效，recovery按键只能触发一种模式.
; key_work_mode : 模式选择
; 0: 刷机,
; 1: 一键恢复(uboot阶段),
; 2: 安卓recovery,
; 3: 安卓恢复出厂设置.
; 如果不设置，模式为安卓recovery.
; short_press_mode : 长按触发的模式，选项同上.
; long_press_mode : 短按触发的模式，选项同上.
; key_press_time : 定义长按的时间，单位:毫秒.
; recovery_key : 按键配置.
;----------------------------------------------------------------------------------
[key_boot_recovery]
recovery_key_used = 1
press_mode_enable = 0
key_work_mode = 0
short_press_mode = 0
long_press_mode = 1
key_press_time = 2000
recovery_key =
;---------------------------------------------------------------------------------------------------------
; if 1 == standby_mode, then support super standby;
; else, support normal standby.
;---------------------------------------------------------------------------------------------------------
[pm_para]
standby_mode = 1
[card0_boot_para]
card_ctrl = 0
card_high_speed = 1
card_line = 4
sdc_d1 = port:PF0<2><1><3><default>
sdc_d0 = port:PF1<2><1><3><default>
sdc_clk = port:PF2<2><1><3><default>
sdc_cmd = port:PF3<2><1><3><default>
sdc_d3 = port:PF4<2><1><3><default>
sdc_d2 = port:PF5<2><1><3><default>
;sdc_type = "tm1"
[card2_boot_para]
card_ctrl = 2
card_high_speed = 1
card_line = 8
sdc_clk = port:PC5<3><1><3><default>
sdc_cmd = port:PC6<3><1><3><default>
sdc_d0 = port:PC10<3><1><3><default>
sdc_d1 = port:PC13<3><1><3><default>
sdc_d2 = port:PC15<3><1><3><default>
sdc_d3 = port:PC8<3><1><3><default>
sdc_d4 = port:PC9<3><1><3><default>
sdc_d5 = port:PC11<3><1><3><default>
sdc_d6 = port:PC14<3><1><3><default>
sdc_d7 = port:PC16<3><1><3><default>
sdc_emmc_rst = port:PC1<3><1><3><default>
sdc_ds = port:PC0<3><2><3><default>
sdc_ex_dly_used = 2
sdc_io_1v8 = 1
;sdc_dis_host_caps = 0x100
;sdc_type = "tm4"
[gpio_bias]
pc_bias = 1800
[twi_para]
twi_port = 0
twi_scl = port:PH14<2><default><default><default>
twi_sda = port:PH15<2><default><default><default>
[auto_print]
auto_print_used = 1
[uart_para]
uart_debug_port = 0
uart_debug_tx = port:PH00<2><1><default><default>
uart_debug_rx = port:PH01<2><1><default><default>
[jtag_para]
jtag_enable = 0
jtag_ms = port:PH9<3><default><default><default>
jtag_ck = port:PH10<3><default><default><default>
jtag_do = port:PH11<3><default><default><default>
jtag_di = port:PH12<3><default><default><default>
[clock]
pll4 = 300
pll6 = 600
pll8 = 360
pll9 = 297
pll10 = 264
;*****************************************************************************
;
;dram select configuration
;
;select_mode : dram模式选择, 0:不进行自动识别
; 1:gpio识别模式(dram_para, dram_para1-15, 共16组有效)
; 2:gpadc识别模式(dram_para, dram_para1-7, 共8组有效)
; 3:1个IO+gpadc识别模式(dram_para, dram_para1-15, 共16组有效)。其中IO配置优先级按select_gpio0>select_gpio1>select_gpio2>select_gpio3
;gpadc_channel : 选择gpadc通道 有效值(0-3)
;select_gpio1-4 : 选择gpio pin
;*****************************************************************************
[dram_select_para]
select_mode = 0
gpadc_channel = 1
select_gpio0 =
select_gpio1 =
select_gpio2 =
select_gpio3 =
;*****************************************************************************
;sdram configuration
;
;*****************************************************************************
[dram_para]
dram_clk = 792
dram_type = 8
dram_dx_odt = 0x07070707
dram_dx_dri = 0x0e0e0e0e
dram_ca_dri = 0x0e0e
dram_odt_en = 0xaaaaeeee
dram_para1 = 0x30fa
dram_para2 = 0x0000
dram_mr0 = 0x0
dram_mr1 = 0x34
dram_mr2 = 0x1b
dram_mr3 = 0x33
dram_mr4 = 0x3
dram_mr5 = 0x0
dram_mr6 = 0x0
dram_mr11 = 0x4
dram_mr12 = 0x72
dram_mr13 = 0x0
dram_mr14 = 0x9
dram_mr16 = 0x0
dram_mr17 = 0x0
dram_mr22 = 0x24
dram_tpr0 = 0x0
dram_tpr1 = 0x0
dram_tpr2 = 0x0
dram_tpr3 = 0x0
dram_tpr6 = 0x35808080
dram_tpr10 = 0x402f6663
dram_tpr11 = 0x36363535
dram_tpr12 = 0x10101110
dram_tpr13 = 0x2080C60
[dram_para1]
dram_clk = 720
dram_type = 3
dram_dx_odt = 0x08080808
dram_dx_dri = 0x0e0e0e0e
dram_ca_dri = 0x0e0e
dram_odt_en = 1
dram_para1 = 0x30FA
dram_para2 = 0x1000
dram_mr0 = 0x840
dram_mr1 = 0x4
dram_mr2 = 0x8
dram_mr3 = 0x0
dram_mr4 = 0x0
dram_mr5 = 0x0
dram_mr6 = 0x0
dram_mr11 = 0x0
dram_mr12 = 0x0
dram_mr13 = 0x0
dram_mr14 = 0x0
dram_mr16 = 0x0
dram_mr17 = 0x0
dram_mr22 = 0x0
dram_tpr0 = 0x0
dram_tpr1 = 0x0
dram_tpr2 = 0x0
dram_tpr3 = 0x0
dram_tpr6 = 0x33808080
dram_tpr10 = 0x00f83438
dram_tpr11 = 0x0
dram_tpr12 = 0x0
dram_tpr13 = 0x40
[dram_para2]
dram_clk = 720
dram_type = 3
dram_dx_odt = 0x08080808
dram_dx_dri = 0x0e0e0e0e
dram_ca_dri = 0x0e0e
dram_odt_en = 1
dram_para1 = 0x30FA
dram_para2 = 0x1000
dram_mr0 = 0x840
dram_mr1 = 0x4
dram_mr2 = 0x8
dram_mr3 = 0x0
dram_mr4 = 0x0
dram_mr5 = 0x0
dram_mr6 = 0x0
dram_mr11 = 0x0
dram_mr12 = 0x0
dram_mr13 = 0x0
dram_mr14 = 0x0
dram_mr16 = 0x0
dram_mr17 = 0x0
dram_mr22 = 0x0
dram_tpr0 = 0x0
dram_tpr1 = 0x0
dram_tpr2 = 0x0
dram_tpr3 = 0x0
dram_tpr6 = 0x33808080
dram_tpr10 = 0x00f83438
dram_tpr11 = 0x0
dram_tpr12 = 0x0
dram_tpr13 = 0x40
[dram_para3]
dram_clk = 720
dram_type = 3
dram_dx_odt = 0x08080808
dram_dx_dri = 0x0e0e0e0e
dram_ca_dri = 0x0e0e
dram_odt_en = 1
dram_para1 = 0x30FA
dram_para2 = 0x1000
dram_mr0 = 0x840
dram_mr1 = 0x4
dram_mr2 = 0x8
dram_mr3 = 0x0
dram_mr4 = 0x0
dram_mr5 = 0x0
dram_mr6 = 0x0
dram_mr11 = 0x0
dram_mr12 = 0x0
dram_mr13 = 0x0
dram_mr14 = 0x0
dram_mr16 = 0x0
dram_mr17 = 0x0
dram_mr22 = 0x0
dram_tpr0 = 0x0
dram_tpr1 = 0x0
dram_tpr2 = 0x0
dram_tpr3 = 0x0
dram_tpr6 = 0x33808080
dram_tpr10 = 0x00f83438
dram_tpr11 = 0x0
dram_tpr12 = 0x0
dram_tpr13 = 0x40
[dram_para4]
dram_clk = 720
dram_type = 3
dram_dx_odt = 0x08080808
dram_dx_dri = 0x0e0e0e0e
dram_ca_dri = 0x0e0e
dram_odt_en = 1
dram_para1 = 0x30FA
dram_para2 = 0x1000
dram_mr0 = 0x840
dram_mr1 = 0x4
dram_mr2 = 0x8
dram_mr3 = 0x0
dram_mr4 = 0x0
dram_mr5 = 0x0
dram_mr6 = 0x0
dram_mr11 = 0x0
dram_mr12 = 0x0
dram_mr13 = 0x0
dram_mr14 = 0x0
dram_mr16 = 0x0
dram_mr17 = 0x0
dram_mr22 = 0x0
dram_tpr0 = 0x0
dram_tpr1 = 0x0
dram_tpr2 = 0x0
dram_tpr3 = 0x0
dram_tpr6 = 0x33808080
dram_tpr10 = 0x00f83438
dram_tpr11 = 0x0
dram_tpr12 = 0x0
dram_tpr13 = 0x40
[dram_para5]
dram_clk = 720
dram_type = 3
dram_dx_odt = 0x08080808
dram_dx_dri = 0x0e0e0e0e
dram_ca_dri = 0x0e0e
dram_odt_en = 1
dram_para1 = 0x30FA
dram_para2 = 0x1000
dram_mr0 = 0x840
dram_mr1 = 0x4
dram_mr2 = 0x8
dram_mr3 = 0x0
dram_mr4 = 0x0
dram_mr5 = 0x0
dram_mr6 = 0x0
dram_mr11 = 0x0
dram_mr12 = 0x0
dram_mr13 = 0x0
dram_mr14 = 0x0
dram_mr16 = 0x0
dram_mr17 = 0x0
dram_mr22 = 0x0
dram_tpr0 = 0x0
dram_tpr1 = 0x0
dram_tpr2 = 0x0
dram_tpr3 = 0x0
dram_tpr6 = 0x33808080
dram_tpr10 = 0x00f83438
dram_tpr11 = 0x0
dram_tpr12 = 0x0
dram_tpr13 = 0x40
[dram_para6]
dram_clk = 720
dram_type = 3
dram_dx_odt = 0x08080808
dram_dx_dri = 0x0e0e0e0e
dram_ca_dri = 0x0e0e
dram_odt_en = 1
dram_para1 = 0x30FA
dram_para2 = 0x1000
dram_mr0 = 0x840
dram_mr1 = 0x4
dram_mr2 = 0x8
dram_mr3 = 0x0
dram_mr4 = 0x0
dram_mr5 = 0x0
dram_mr6 = 0x0
dram_mr11 = 0x0
dram_mr12 = 0x0
dram_mr13 = 0x0
dram_mr14 = 0x0
dram_mr16 = 0x0
dram_mr17 = 0x0
dram_mr22 = 0x0
dram_tpr0 = 0x0
dram_tpr1 = 0x0
dram_tpr2 = 0x0
dram_tpr3 = 0x0
dram_tpr6 = 0x33808080
dram_tpr10 = 0x00f83438
dram_tpr11 = 0x0
dram_tpr12 = 0x0
dram_tpr13 = 0x40
[dram_para7]
dram_clk = 720
dram_type = 3
dram_dx_odt = 0x08080808
dram_dx_dri = 0x0e0e0e0e
dram_ca_dri = 0x0e0e
dram_odt_en = 1
dram_para1 = 0x30FA
dram_para2 = 0x1000
dram_mr0 = 0x840
dram_mr1 = 0x4
dram_mr2 = 0x8
dram_mr3 = 0x0
dram_mr4 = 0x0
dram_mr5 = 0x0
dram_mr6 = 0x0
dram_mr11 = 0x0
dram_mr12 = 0x0
dram_mr13 = 0x0
dram_mr14 = 0x0
dram_mr16 = 0x0
dram_mr17 = 0x0
dram_mr22 = 0x0
dram_tpr0 = 0x0
dram_tpr1 = 0x0
dram_tpr2 = 0x0
dram_tpr3 = 0x0
dram_tpr6 = 0x33808080
dram_tpr10 = 0x00f83438
dram_tpr11 = 0x0
dram_tpr12 = 0x0
dram_tpr13 = 0x40
[dram_para8]
dram_clk = 720
dram_type = 3
dram_dx_odt = 0x08080808
dram_dx_dri = 0x0e0e0e0e
dram_ca_dri = 0x0e0e
dram_odt_en = 1
dram_para1 = 0x30FA
dram_para2 = 0x1000
dram_mr0 = 0x840
dram_mr1 = 0x4
dram_mr2 = 0x8
dram_mr3 = 0x0
dram_mr4 = 0x0
dram_mr5 = 0x0
dram_mr6 = 0x0
dram_mr11 = 0x0
dram_mr12 = 0x0
dram_mr13 = 0x0
dram_mr14 = 0x0
dram_mr16 = 0x0
dram_mr17 = 0x0
dram_mr22 = 0x0
dram_tpr0 = 0x0
dram_tpr1 = 0x0
dram_tpr2 = 0x0
dram_tpr3 = 0x0
dram_tpr6 = 0x33808080
dram_tpr10 = 0x00f83438
dram_tpr11 = 0x0
dram_tpr12 = 0x0
dram_tpr13 = 0x40
[dram_para9]
dram_clk = 720
dram_type = 3
dram_dx_odt = 0x08080808
dram_dx_dri = 0x0e0e0e0e
dram_ca_dri = 0x0e0e
dram_odt_en = 1
dram_para1 = 0x30FA
dram_para2 = 0x1000
dram_mr0 = 0x840
dram_mr1 = 0x4
dram_mr2 = 0x8
dram_mr3 = 0x0
dram_mr4 = 0x0
dram_mr5 = 0x0
dram_mr6 = 0x0
dram_mr11 = 0x0
dram_mr12 = 0x0
dram_mr13 = 0x0
dram_mr14 = 0x0
dram_mr16 = 0x0
dram_mr17 = 0x0
dram_mr22 = 0x0
dram_tpr0 = 0x0
dram_tpr1 = 0x0
dram_tpr2 = 0x0
dram_tpr3 = 0x0
dram_tpr6 = 0x33808080
dram_tpr10 = 0x00f83438
dram_tpr11 = 0x0
dram_tpr12 = 0x0
dram_tpr13 = 0x40
[dram_para10]
dram_clk = 720
dram_type = 3
dram_dx_odt = 0x08080808
dram_dx_dri = 0x0e0e0e0e
dram_ca_dri = 0x0e0e
dram_odt_en = 1
dram_para1 = 0x30FA
dram_para2 = 0x1000
dram_mr0 = 0x840
dram_mr1 = 0x4
dram_mr2 = 0x8
dram_mr3 = 0x0
dram_mr4 = 0x0
dram_mr5 = 0x0
dram_mr6 = 0x0
dram_mr11 = 0x0
dram_mr12 = 0x0
dram_mr13 = 0x0
dram_mr14 = 0x0
dram_mr16 = 0x0
dram_mr17 = 0x0
dram_mr22 = 0x0
dram_tpr0 = 0x0
dram_tpr1 = 0x0
dram_tpr2 = 0x0
dram_tpr3 = 0x0
dram_tpr6 = 0x33808080
dram_tpr10 = 0x00f83438
dram_tpr11 = 0x0
dram_tpr12 = 0x0
dram_tpr13 = 0x40
[dram_para11]
dram_clk = 720
dram_type = 3
dram_dx_odt = 0x08080808
dram_dx_dri = 0x0e0e0e0e
dram_ca_dri = 0x0e0e
dram_odt_en = 1
dram_para1 = 0x30FA
dram_para2 = 0x1000
dram_mr0 = 0x840
dram_mr1 = 0x4
dram_mr2 = 0x8
dram_mr3 = 0x0
dram_mr4 = 0x0
dram_mr5 = 0x0
dram_mr6 = 0x0
dram_mr11 = 0x0
dram_mr12 = 0x0
dram_mr13 = 0x0
dram_mr14 = 0x0
dram_mr16 = 0x0
dram_mr17 = 0x0
dram_mr22 = 0x0
dram_tpr0 = 0x0
dram_tpr1 = 0x0
dram_tpr2 = 0x0
dram_tpr3 = 0x0
dram_tpr6 = 0x33808080
dram_tpr10 = 0x00f83438
dram_tpr11 = 0x0
dram_tpr12 = 0x0
dram_tpr13 = 0x40
[dram_para12]
dram_clk = 720
dram_type = 3
dram_dx_odt = 0x08080808
dram_dx_dri = 0x0e0e0e0e
dram_ca_dri = 0x0e0e
dram_odt_en = 1
dram_para1 = 0x30FA
dram_para2 = 0x1000
dram_mr0 = 0x840
dram_mr1 = 0x4
dram_mr2 = 0x8
dram_mr3 = 0x0
dram_mr4 = 0x0
dram_mr5 = 0x0
dram_mr6 = 0x0
dram_mr11 = 0x0
dram_mr12 = 0x0
dram_mr13 = 0x0
dram_mr14 = 0x0
dram_mr16 = 0x0
dram_mr17 = 0x0
dram_mr22 = 0x0
dram_tpr0 = 0x0
dram_tpr1 = 0x0
dram_tpr2 = 0x0
dram_tpr3 = 0x0
dram_tpr6 = 0x33808080
dram_tpr10 = 0x00f83438
dram_tpr11 = 0x0
dram_tpr12 = 0x0
dram_tpr13 = 0x40
[dram_para13]
dram_clk = 720
dram_type = 3
dram_dx_odt = 0x08080808
dram_dx_dri = 0x0e0e0e0e
dram_ca_dri = 0x0e0e
dram_odt_en = 1
dram_para1 = 0x30FA
dram_para2 = 0x1000
dram_mr0 = 0x840
dram_mr1 = 0x4
dram_mr2 = 0x8
dram_mr3 = 0x0
dram_mr4 = 0x0
dram_mr5 = 0x0
dram_mr6 = 0x0
dram_mr11 = 0x0
dram_mr12 = 0x0
dram_mr13 = 0x0
dram_mr14 = 0x0
dram_mr16 = 0x0
dram_mr17 = 0x0
dram_mr22 = 0x0
dram_tpr0 = 0x0
dram_tpr1 = 0x0
dram_tpr2 = 0x0
dram_tpr3 = 0x0
dram_tpr6 = 0x33808080
dram_tpr10 = 0x00f83438
dram_tpr11 = 0x0
dram_tpr12 = 0x0
dram_tpr13 = 0x40
[dram_para14]
dram_clk = 720
dram_type = 3
dram_dx_odt = 0x08080808
dram_dx_dri = 0x0e0e0e0e
dram_ca_dri = 0x0e0e
dram_odt_en = 1
dram_para1 = 0x30FA
dram_para2 = 0x1000
dram_mr0 = 0x840
dram_mr1 = 0x4
dram_mr2 = 0x8
dram_mr3 = 0x0
dram_mr4 = 0x0
dram_mr5 = 0x0
dram_mr6 = 0x0
dram_mr11 = 0x0
dram_mr12 = 0x0
dram_mr13 = 0x0
dram_mr14 = 0x0
dram_mr16 = 0x0
dram_mr17 = 0x0
dram_mr22 = 0x0
dram_tpr0 = 0x0
dram_tpr1 = 0x0
dram_tpr2 = 0x0
dram_tpr3 = 0x0
dram_tpr6 = 0x33808080
dram_tpr10 = 0x00f83438
dram_tpr11 = 0x0
dram_tpr12 = 0x0
dram_tpr13 = 0x40
[dram_para15]
dram_clk = 720
dram_type = 3
dram_dx_odt = 0x08080808
dram_dx_dri = 0x0e0e0e0e
dram_ca_dri = 0x0e0e
dram_odt_en = 1
dram_para1 = 0x30FA
dram_para2 = 0x1000
dram_mr0 = 0x840
dram_mr1 = 0x4
dram_mr2 = 0x8
dram_mr3 = 0x0
dram_mr4 = 0x0
dram_mr5 = 0x0
dram_mr6 = 0x0
dram_mr11 = 0x0
dram_mr12 = 0x0
dram_mr13 = 0x0
dram_mr14 = 0x0
dram_mr16 = 0x0
dram_mr17 = 0x0
dram_mr22 = 0x0
dram_tpr0 = 0x0
dram_tpr1 = 0x0
dram_tpr2 = 0x0
dram_tpr3 = 0x0
dram_tpr6 = 0x33808080
dram_tpr10 = 0x00f83438
dram_tpr11 = 0x0
dram_tpr12 = 0x0
dram_tpr13 = 0x40
[dram_para16]
dram_clk = 792
dram_type = 8
dram_dx_odt = 0x07070707
dram_dx_dri = 0x0e0e0e0e
dram_ca_dri = 0x0e0e
dram_odt_en = 0xaaaaeeee
dram_para1 = 0x30fa
dram_para2 = 0x0000
dram_mr0 = 0x0
dram_mr1 = 0x34
dram_mr2 = 0x1b
dram_mr3 = 0x33
dram_mr4 = 0x3
dram_mr5 = 0x0
dram_mr6 = 0x0
dram_mr11 = 0x4
dram_mr12 = 0x72
dram_mr13 = 0x0
dram_mr14 = 0x9
dram_mr16 = 0x0
dram_mr17 = 0x0
dram_mr22 = 0x24
dram_tpr0 = 0x0
dram_tpr1 = 0x0
dram_tpr2 = 0x0
dram_tpr3 = 0x0
dram_tpr6 = 0x35808080
dram_tpr10 = 0x402f6663
dram_tpr11 = 0x36363535
dram_tpr12 = 0x10101110
dram_tpr13 = 0x2080C60
;----------------------------------------------------------------------------------
;os life cycle para configuration
;----------------------------------------------------------------------------------
;----------------------------------------------------------------------------------
;uart configuration
;uart_type --- 2 (2 wire), 4 (4 wire), 8 (8 wire, full function)
;----------------------------------------------------------------------------------
[uart0]
uart0_used = 1
uart0_port = 0
uart0_type = 2
uart0_tx = port:PH00<2><1><default><default>
uart0_rx = port:PH01<2><1><default><default>
[nand0_para]
nand0_support_2ch = 0
nand0_used = 0
nand0_we = port:PC00<2><0><1><default>
nand0_ale = port:PC01<2><0><1><default>
nand0_cle = port:PC02<2><0><1><default>
nand0_ce0 = port:PC03<2><1><1><default>
nand0_nre = port:PC04<2><0><1><default>
nand0_rb0 = port:PC05<2><1><1><default>
nand0_d0 = port:PC06<2><0><1><default>
nand0_d1 = port:PC07<2><0><1><default>
nand0_d2 = port:PC08<2><0><1><default>
nand0_d3 = port:PC09<2><0><1><default>
nand0_d4 = port:PC10<2><0><1><default>
nand0_d5 = port:PC11<2><0><1><default>
nand0_d6 = port:PC12<2><0><1><default>
nand0_d7 = port:PC13<2><0><1><default>
nand0_ndqs = port:PC14<2><0><1><default>
nand0_ce1 = port:PC15<2><1><1><default>
nand0_rb1 = port:PC16<2><1><1><default>
nand0_regulator1 = "vcc-nand"
nand0_regulator2 = "none"
nand0_cache_level = 0x55aaaa55
nand0_flush_cache_num = 0x55aaaa55
nand0_capacity_level = 0x55aaaa55
nand0_id_number_ctl = 0x55aaaa55
nand0_print_level = 0x55aaaa55
nand0_p0 = 0x55aaaa55
nand0_p1 = 0x55aaaa55
nand0_p2 = 0x55aaaa55
nand0_p3 = 0x55aaaa55
[secure]
dram_region_mbytes = 80
drm_region_mbytes = 0
drm_region_start_mbytes = 0

2
scripts/general.sh
View File

@ -1837,7 +1837,7 @@ show_checklist_variables ()
install_wiringop()
{
install_deb_chroot "$EXTER/cache/debs/arm64/wiringpi_2.48.deb"
install_deb_chroot "$EXTER/cache/debs/arm64/wiringpi_2.49.deb"
chroot "${SDCARD}" /bin/bash -c "apt-mark hold wiringpi" >> "${DEST}"/${LOG_SUBPATH}/install.log 2>&1
if [[ ${IGNORE_UPDATES} != yes ]]; then

1
scripts/main.sh
View File

@ -227,6 +227,7 @@ if [[ -z $BOARD ]]; then
#options+=("orangepizero2-b" "Allwinner H616 quad core 512MB/1GB RAM WiFi/BT GBE SPI")
#options+=("orangepizero2-lts" "Allwinner H616 quad core 1.5GB RAM WiFi/BT GBE SPI")
options+=("orangepizero3" "Allwinner H618 quad core 1GB/1.5GB/2GB/4GB RAM WiFi/BT GBE SPI")
#options+=("orangepizero2w" "Allwinner H618 quad core 1GB/1.5GB/2GB/4GB RAM WiFi/BT SPI")
#options+=("orangepir1b" "Allwinner H618 quad core 1.5GB/2GB/4GB RAM WiFi/BT GBE SPI")
#options+=("orangepi400" "Allwinner H616 quad core 4GB RAM WiFi/BT GBE eMMC VGA")
options+=("orangepi4" "Rockchip RK3399 hexa core 4GB RAM GBE eMMC USB3 USB-C WiFi/BT")