mfd: Add support for Maxim MAX96755F
The MAX96755F convert MIPI DSI 4-lane input port data to GMSL2 high-speed serial link protocol. They also send and receive control channel and peripheral control data, enabling bidirectional transmission of video and data over cables in excess of 15 meters in length. Signed-off-by: Guochun Huang <hero.huang@rock-chips.com> Change-Id: I540bd4ca61ae6b6e77cb9635567690fe3367a281
This commit is contained in:
Guochun Huang
Tao Huang
parent
6a4a40a39d
commit
b564d3921a
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@ -939,6 +939,14 @@ config MFD_MAX96752F
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help
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Say yes here to add support for Maxim Semiconductor MAX96752F.
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config MFD_MAX96755F
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tristate "Maxim Semiconductor MAX96755 GMSL2 Serializer Support"
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depends on I2C
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select MFD_CORE
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select REGMAP_I2C
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help
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Say yes here to add support for Maxim Semiconductor MAX96755.
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config MFD_MT6360
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tristate "Mediatek MT6360 SubPMIC"
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select MFD_CORE
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@ -172,6 +172,7 @@ obj-$(CONFIG_MFD_MAX8997) += max8997.o max8997-irq.o
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obj-$(CONFIG_MFD_MAX8998) += max8998.o max8998-irq.o
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obj-$(CONFIG_MFD_MAX96745) += max96745.o
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obj-$(CONFIG_MFD_MAX96752F) += max96752f.o
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obj-$(CONFIG_MFD_MAX96755F) += max96755f.o
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obj-$(CONFIG_MFD_MP2629) += mp2629.o
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@ -0,0 +1,261 @@
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Maxim max96755f MFD driver
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*
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* Copyright (C) 2022 Rockchip Electronics Co. Ltd.
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*/
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#include <linux/module.h>
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#include <linux/init.h>
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#include <linux/i2c.h>
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#include <linux/i2c-mux.h>
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#include <linux/gpio/consumer.h>
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#include <linux/regmap.h>
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#include <linux/mfd/core.h>
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#include <linux/regulator/consumer.h>
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#include <linux/mfd/max96755f.h>
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struct max96755f {
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struct device *dev;
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struct regmap *regmap;
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struct i2c_mux_core *muxc;
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struct gpio_desc *enable_gpio;
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struct gpio_desc *reset_gpio;
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struct regulator *supply;
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struct gpio_desc *pwdnb_gpio;
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struct gpio_desc *lock_gpio;
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bool split_mode;
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};
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static const struct mfd_cell max96755f_devs[] = {
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{
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.name = "max96755f-pinctrl",
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.of_compatible = "maxim,max96755f-pinctrl",
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}, {
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.name = "max96755f-bridge",
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.of_compatible = "maxim,max96755f-bridge",
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},
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};
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static const struct regmap_config max96755f_regmap_config = {
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.name = "max96755f",
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.reg_bits = 16,
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.val_bits = 8,
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.max_register = 0x1b17,
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};
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static int max96755f_select(struct i2c_mux_core *muxc, u32 chan)
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{
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struct max96755f *max96755f = dev_get_drvdata(muxc->dev);
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u32 link_cfg, val;
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int ret;
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regmap_update_bits(max96755f->regmap, 0x0001, DIS_REM_CC,
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FIELD_PREP(DIS_REM_CC, 0));
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if (!max96755f->split_mode)
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return 0;
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regmap_read(max96755f->regmap, 0x0010, &link_cfg);
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if ((link_cfg & LINK_CFG) == SPLITTER_MODE)
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return 0;
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if (chan == 0 && (link_cfg & LINK_CFG) != LINKA) {
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regmap_update_bits(max96755f->regmap, 0x0010,
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RESET_ONESHOT | AUTO_LINK | LINK_CFG,
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FIELD_PREP(RESET_ONESHOT, 1) |
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FIELD_PREP(AUTO_LINK, 0) |
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FIELD_PREP(LINK_CFG, LINKA));
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} else if (chan == 1 && (link_cfg & LINK_CFG) != LINKB) {
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regmap_update_bits(max96755f->regmap, 0x0010,
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RESET_ONESHOT | AUTO_LINK | LINK_CFG,
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FIELD_PREP(RESET_ONESHOT, 1) |
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FIELD_PREP(AUTO_LINK, 0) |
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FIELD_PREP(LINK_CFG, LINKB));
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}
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ret = regmap_read_poll_timeout(max96755f->regmap, 0x0013, val,
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val & LOCKED, 100,
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50 * USEC_PER_MSEC);
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if (ret < 0) {
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dev_err(max96755f->dev, "GMSL2 link lock timeout\n");
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return ret;
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}
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return 0;
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}
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static int max96755f_deselect(struct i2c_mux_core *muxc, u32 chan)
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{
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struct max96755f *max96755f = dev_get_drvdata(muxc->dev);
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regmap_update_bits(max96755f->regmap, 0x0001, DIS_REM_CC,
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FIELD_PREP(DIS_REM_CC, 1));
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return 0;
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}
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static void max96755f_power_off(void *data)
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{
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struct max96755f *max96755f = data;
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if (max96755f->reset_gpio)
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gpiod_direction_output(max96755f->reset_gpio, 1);
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if (max96755f->enable_gpio)
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gpiod_direction_output(max96755f->enable_gpio, 0);
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if (max96755f->supply)
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regulator_disable(max96755f->supply);
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}
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static int max96755f_power_on(struct max96755f *max96755f)
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{
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int ret;
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if (max96755f->supply) {
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ret = regulator_enable(max96755f->supply);
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if (ret < 0)
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return ret;
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}
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if (max96755f->enable_gpio) {
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gpiod_direction_output(max96755f->enable_gpio, 1);
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msleep(100);
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}
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if (max96755f->reset_gpio) {
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gpiod_direction_output(max96755f->reset_gpio, 0);
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msleep(100);
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gpiod_direction_output(max96755f->reset_gpio, 1);
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msleep(100);
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gpiod_direction_output(max96755f->reset_gpio, 0);
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msleep(100);
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}
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regmap_update_bits(max96755f->regmap, 0x0001, DIS_REM_CC,
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FIELD_PREP(DIS_REM_CC, 1));
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return 0;
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}
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static int max96755f_i2c_probe(struct i2c_client *client)
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{
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struct device *dev = &client->dev;
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struct device_node *child;
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struct max96755f *max96755f;
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unsigned int nr = 0;
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int ret;
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for_each_available_child_of_node(dev->of_node, child) {
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if (!of_find_property(child, "reg", NULL))
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continue;
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nr++;
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}
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max96755f = devm_kzalloc(dev, sizeof(*max96755f), GFP_KERNEL);
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if (!max96755f)
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return -ENOMEM;
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max96755f->muxc = i2c_mux_alloc(client->adapter, dev, nr, 0,
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I2C_MUX_LOCKED, max96755f_select,
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max96755f_deselect);
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if (!max96755f->muxc)
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return -ENOMEM;
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if (nr == 2)
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max96755f->split_mode = true;
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max96755f->dev = dev;
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i2c_set_clientdata(client, max96755f);
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max96755f->supply = devm_regulator_get(dev, "power");
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if (IS_ERR(max96755f->supply))
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return dev_err_probe(dev, PTR_ERR(max96755f->supply),
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"failed to get power supply\n");
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max96755f->lock_gpio = devm_gpiod_get_optional(dev, "lock", GPIOD_IN);
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if (IS_ERR(max96755f->lock_gpio))
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return dev_err_probe(dev, PTR_ERR(max96755f->lock_gpio),
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"failed to get lock GPIO\n");
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max96755f->enable_gpio = devm_gpiod_get_optional(dev, "enable", GPIOD_ASIS);
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if (IS_ERR(max96755f->enable_gpio)) {
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return dev_err_probe(dev, PTR_ERR(max96755f->enable_gpio),
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"failed to get enable GPIO\n");
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}
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max96755f->reset_gpio = devm_gpiod_get_optional(dev, "reset", GPIOD_ASIS);
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if (IS_ERR(max96755f->reset_gpio))
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return dev_err_probe(dev, PTR_ERR(max96755f->reset_gpio),
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"failed to get reset GPIO\n");
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max96755f->regmap = devm_regmap_init_i2c(client, &max96755f_regmap_config);
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if (IS_ERR(max96755f->regmap))
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return dev_err_probe(dev, PTR_ERR(max96755f->regmap),
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"failed to initialize regmap");
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ret = max96755f_power_on(max96755f);
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if (ret)
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return ret;
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ret = devm_add_action_or_reset(dev, max96755f_power_off, max96755f);
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if (ret)
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return ret;
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ret = devm_mfd_add_devices(dev, PLATFORM_DEVID_AUTO, max96755f_devs,
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ARRAY_SIZE(max96755f_devs), NULL, 0, NULL);
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if (ret)
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return ret;
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for_each_available_child_of_node(dev->of_node, child) {
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if (of_property_read_u32(child, "reg", &nr))
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continue;
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ret = i2c_mux_add_adapter(max96755f->muxc, 0, nr, 0);
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if (ret) {
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i2c_mux_del_adapters(max96755f->muxc);
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return ret;
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}
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}
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return 0;
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}
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static int max96755f_i2c_remove(struct i2c_client *client)
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{
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struct max96755f *max96755f = i2c_get_clientdata(client);
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i2c_mux_del_adapters(max96755f->muxc);
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return 0;
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}
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static void max96755f_i2c_shutdown(struct i2c_client *client)
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{
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struct max96755f *max96755f = i2c_get_clientdata(client);
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max96755f_power_off(max96755f);
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}
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static const struct of_device_id max96755f_of_match[] = {
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{ .compatible = "maxim,max96755f", },
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{}
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};
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MODULE_DEVICE_TABLE(of, max96755f_of_match);
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static struct i2c_driver max96755f_i2c_driver = {
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.driver = {
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.name = "max96755f",
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.of_match_table = max96755f_of_match,
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},
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.probe_new = max96755f_i2c_probe,
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.remove = max96755f_i2c_remove,
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.shutdown = max96755f_i2c_shutdown,
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};
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module_i2c_driver(max96755f_i2c_driver);
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MODULE_AUTHOR("Guochun Huang<hero.huang@rock-chips.com>");
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MODULE_DESCRIPTION("Maxim max96755f MFD driver");
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MODULE_LICENSE("GPL");
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@ -0,0 +1,175 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Defining registers address and its bit definitions of MAX96752F
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*
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* Copyright (c) 2022 Rockchip Electronics Co. Ltd.
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*/
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#ifndef _MFD_MAX96755F_H_
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#define _MFD_MAX96755F_H_
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#include <linux/bitfield.h>
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#define GPIO_A_REG(gpio) (0x02be + ((gpio) * 3))
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#define GPIO_B_REG(gpio) (0x02bf + ((gpio) * 3))
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#define GPIO_C_REG(gpio) (0x02c0 + ((gpio) * 3))
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/* 0000h */
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#define DEV_ADDR GENMASK(7, 1)
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#define CFG_BLOCK BIT(0)
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/* 0001h */
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#define IIC_2_EN BIT(7)
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#define IIC_1_EN BIT(6)
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#define DIS_REM_CC BIT(4)
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#define TX_RATE GENMASK(3, 2)
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/* 0002h */
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#define VID_TX_EN_U BIT(7)
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#define VID_TX_EN_Z BIT(6)
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#define VID_TX_EN_Y BIT(5)
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#define VID_TX_EN_X BIT(4)
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#define AUD_TX_EN_Y BIT(3)
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#define AUD_TX_EN_X BIT(2)
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/* 0003h */
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#define UART_2_EN BIT(5)
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#define UART_1_EN BIT(4)
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/* 0005h */
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#define LOCK_EN BIT(7)
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#define ERRB_EN BIT(6)
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#define PU_LF3 BIT(3)
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#define PU_LF2 BIT(2)
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#define PU_LF1 BIT(1)
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#define PU_LF0 BIT(0)
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/* 0006h */
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#define RCLKEN BIT(5)
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/* 0010h */
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#define RESET_ALL BIT(7)
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#define RESET_LINK BIT(6)
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#define RESET_ONESHOT BIT(5)
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#define AUTO_LINK BIT(4)
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#define SLEEP BIT(3)
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#define REG_ENABLE BIT(2)
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#define LINK_CFG GENMASK(1, 0)
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/* 0013h */
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#define LINK_MODE GENMASK(5, 4)
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#define LOCKED BIT(3)
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/* 0048h */
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#define REM_MS_EN BIT(5)
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#define LOC_MS_EN BIT(4)
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/* 0053h */
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#define TX_SPLIT_MASK_B BIT(5)
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#define TX_SPLIT_MASK_A BIT(4)
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#define TX_STR_SEL GENMASK(1, 0)
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/* 0140h */
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#define AUD_RX_EN BIT(0)
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/* 0170h */
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#define SPI_EN BIT(0)
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/* 02beh */
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#define RES_CFG BIT(7)
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#define TX_PRIO BIT(6)
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#define TX_COMP_EN BIT(5)
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#define GPIO_OUT BIT(4)
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#define GPIO_IN BIT(3)
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#define GPIO_RX_EN BIT(2)
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#define GPIO_TX_EN BIT(1)
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#define GPIO_OUT_DIS BIT(0)
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/* 02bfh */
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#define PULL_UPDN_SEL GENMASK(7, 6)
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#define OUT_TYPE BIT(5)
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#define GPIO_TX_ID GENMASK(4, 0)
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/* 02c0h */
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#define OVR_RES_CFG BIT(7)
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#define GPIO_RX_ID GENMASK(4, 0)
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/* 0311h */
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#define START_PORTBU BIT(7)
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#define START_PORTBZ BIT(6)
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#define START_PORTBY BIT(5)
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#define START_PORTBX BIT(4)
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#define START_PORTAU BIT(3)
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#define START_PORTAZ BIT(2)
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#define START_PORTAY BIT(1)
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#define START_PORTAX BIT(0)
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/* 032ah */
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#define DV_LOCK BIT(7)
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#define DV_SWP_AB BIT(6)
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#define LINE_ALT BIT(5)
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#define DV_CONV BIT(2)
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#define DV_SPL BIT(1)
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#define DV_EN BIT(0)
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/* 0330h */
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#define PHY_CONFIG GENMASK(2, 0)
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#define MIPI_RX_RESET BIT(3)
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/* 0331h */
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#define NUM_LANES GENMASK(1, 0)
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/* 0385h */
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#define DPI_HSYNC_WIDTH_L GENMASK(7, 0)
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/* 0386h */
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#define DPI_VYSNC_WIDTH_L GENMASK(7, 0)
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/* 0387h */
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#define DPI_HSYNC_WIDTH_H GENMASK(3, 0)
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#define DPI_VSYNC_WIDTH_H GENMASK(7, 4)
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/* 03a4h */
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#define DPI_DE_SKEW_SEL BIT(1)
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#define DPI_DESKEW_EN BIT(0)
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/* 03a5h */
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#define DPI_VFP_L GENMASK(7, 0)
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/* 03a6h */
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#define DPI_VFP_H GENMASK(3, 0)
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#define DPI_VBP_L GENMASK(7, 4)
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/* 03a7h */
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#define DPI_VBP_H GENMASK(7, 0)
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/* 03a8h */
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#define DPI_VACT_L GENMASK(7, 0)
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/* 03a9h */
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#define DPI_VACT_H GENMASK(3, 0)
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/* 03aah */
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#define DPI_HFP_L GENMASK(7, 0)
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/* 03abh */
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#define DPI_HFP_H GENMASK(3, 0)
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#define DPI_HBP_L GENMASK(7, 4)
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/* 03ach */
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#define DPI_HBP_H GENMASK(7, 0)
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/* 03adh */
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#define DPI_HACT_L GENMASK(7, 0)
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/* 03aeh */
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#define DPI_HACT_H GENMASK(4, 0)
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enum link_mode {
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DUAL_LINK,
|
||||
LINKA,
|
||||
LINKB,
|
||||
SPLITTER_MODE,
|
||||
};
|
||||
|
||||
#endif /* _MFD_MAX96755F_H_ */
|
||||
Loading…
Reference in New Issue