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ARM: dts: rockchip: rk3288: move psci node to core dtsi 

Currently the psci node is in rk3288-linx/android.dtsi file, move them
into the core dt file.

Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
Change-Id: I0265719ab4eb6b05cb3c9414fd54f916fcce9d77
This commit is contained in:
Jianqun Xu 2022-11-24 11:23:08 +08:00 committed by Tao Huang
parent d9cadd60be
commit b63c12102a
4 changed files with 9 additions and 63 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

21
arch/arm/boot/dts/rk3288-android.dtsi
View File

@ -152,11 +152,6 @@
};
};
psci {
compatible = "arm,psci-1.0";
method = "smc";
};
/delete-node/ timer@ff810000;
display-subsystem {
@ -243,22 +238,6 @@
};
};
&cpu0 {
enable-method = "psci";
};
&cpu1 {
enable-method = "psci";
};
&cpu2 {
enable-method = "psci";
};
&cpu3 {
enable-method = "psci";
};
&dmac_bus_s {
/* change to non-secure dmac */
reg = <0x0 0xff600000 0x0 0x4000>;

21
arch/arm/boot/dts/rk3288-firefly-rk808.dts
View File

@ -217,11 +217,6 @@
clock-names = "ext_clock";
};
psci {
compatible = "arm,psci-1.0";
method = "smc";
};
rk_key: rockchip-key {
compatible = "rockchip,key";
status = "okay";
@ -632,22 +627,6 @@
status = "okay";
};
&cpu0 {
enable-method = "psci";
};
&cpu1 {
enable-method = "psci";
};
&cpu2 {
enable-method = "psci";
};
&cpu3 {
enable-method = "psci";
};
&dfi {
status = "okay";
};

21
arch/arm/boot/dts/rk3288-linux.dtsi
View File

@ -95,11 +95,6 @@
pinctrl-0 = <&uart2_xfer>;
};
psci {
compatible = "arm,psci-1.0";
method = "smc";
};
/delete-node/ timer@ff810000;
display-subsystem {
@ -157,22 +152,6 @@
};
};
&cpu0 {
enable-method = "psci";
};
&cpu1 {
enable-method = "psci";
};
&cpu2 {
enable-method = "psci";
};
&cpu3 {
enable-method = "psci";
};
&dmac_bus_s {
/* change to non-secure dmac */
reg = <0x0 0xff600000 0x0 0x4000>;

9
arch/arm/boot/dts/rk3288.dtsi
View File

@ -60,6 +60,11 @@
interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
};
psci {
compatible = "arm,psci-1.0";
method = "smc";
};
cpus {
#address-cells = <1>;
#size-cells = <0>;
@ -70,6 +75,7 @@
device_type = "cpu";
compatible = "arm,cortex-a12";
reg = <0x500>;
enable-method = "psci";
resets = <&cru SRST_CORE0>;
operating-points-v2 = <&cpu_opp_table>;
#cooling-cells = <2>; /* min followed by max */
@ -81,6 +87,7 @@
device_type = "cpu";
compatible = "arm,cortex-a12";
reg = <0x501>;
enable-method = "psci";
resets = <&cru SRST_CORE1>;
operating-points-v2 = <&cpu_opp_table>;
#cooling-cells = <2>; /* min followed by max */
@ -92,6 +99,7 @@
device_type = "cpu";
compatible = "arm,cortex-a12";
reg = <0x502>;
enable-method = "psci";
resets = <&cru SRST_CORE2>;
operating-points-v2 = <&cpu_opp_table>;
#cooling-cells = <2>; /* min followed by max */
@ -103,6 +111,7 @@
device_type = "cpu";
compatible = "arm,cortex-a12";
reg = <0x503>;
enable-method = "psci";
resets = <&cru SRST_CORE3>;
operating-points-v2 = <&cpu_opp_table>;
#cooling-cells = <2>; /* min followed by max */