diff --git a/arch/arm/boot/dts/rk3288-android.dtsi b/arch/arm/boot/dts/rk3288-android.dtsi
index b1d9d742c835..4922f3c00bae 100644
--- a/arch/arm/boot/dts/rk3288-android.dtsi
+++ b/arch/arm/boot/dts/rk3288-android.dtsi
@@ -152,11 +152,6 @@
 		};
 	};
 
-	psci {
-		compatible = "arm,psci-1.0";
-		method = "smc";
-	};
-
 	/delete-node/ timer@ff810000;
 
 	display-subsystem {
@@ -243,22 +238,6 @@
 	};
 };
 
-&cpu0 {
-	enable-method = "psci";
-};
-
-&cpu1 {
-	enable-method = "psci";
-};
-
-&cpu2 {
-	enable-method = "psci";
-};
-
-&cpu3 {
-	enable-method = "psci";
-};
-
 &dmac_bus_s {
 	/* change to non-secure dmac */
 	reg = <0x0 0xff600000 0x0 0x4000>;
diff --git a/arch/arm/boot/dts/rk3288-firefly-rk808.dts b/arch/arm/boot/dts/rk3288-firefly-rk808.dts
index 0990c326f465..dc418937de2d 100644
--- a/arch/arm/boot/dts/rk3288-firefly-rk808.dts
+++ b/arch/arm/boot/dts/rk3288-firefly-rk808.dts
@@ -217,11 +217,6 @@
 		clock-names = "ext_clock";
 	};
 
-	psci {
-		compatible = "arm,psci-1.0";
-		method = "smc";
-	};
-
 	rk_key: rockchip-key {
 		compatible = "rockchip,key";
 		status = "okay";
@@ -632,22 +627,6 @@
 	status = "okay";
 };
 
-&cpu0 {
-	enable-method = "psci";
-};
-
-&cpu1 {
-	enable-method = "psci";
-};
-
-&cpu2 {
-	enable-method = "psci";
-};
-
-&cpu3 {
-	enable-method = "psci";
-};
-
 &dfi {
 	status = "okay";
 };
diff --git a/arch/arm/boot/dts/rk3288-linux.dtsi b/arch/arm/boot/dts/rk3288-linux.dtsi
index c5d9dc214bab..8262a19d8b52 100644
--- a/arch/arm/boot/dts/rk3288-linux.dtsi
+++ b/arch/arm/boot/dts/rk3288-linux.dtsi
@@ -95,11 +95,6 @@
 		pinctrl-0 = <&uart2_xfer>;
 	};
 
-	psci {
-		compatible = "arm,psci-1.0";
-		method = "smc";
-	};
-
 	/delete-node/ timer@ff810000;
 
 	display-subsystem {
@@ -157,22 +152,6 @@
 	};
 };
 
-&cpu0 {
-	enable-method = "psci";
-};
-
-&cpu1 {
-	enable-method = "psci";
-};
-
-&cpu2 {
-	enable-method = "psci";
-};
-
-&cpu3 {
-	enable-method = "psci";
-};
-
 &dmac_bus_s {
 	/* change to non-secure dmac */
 	reg = <0x0 0xff600000 0x0 0x4000>;
diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi
index b37075bc74f7..2b05d31b4df3 100644
--- a/arch/arm/boot/dts/rk3288.dtsi
+++ b/arch/arm/boot/dts/rk3288.dtsi
@@ -60,6 +60,11 @@
 		interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
 	};
 
+	psci {
+		compatible = "arm,psci-1.0";
+		method = "smc";
+	};
+
 	cpus {
 		#address-cells = <1>;
 		#size-cells = <0>;
@@ -70,6 +75,7 @@
 			device_type = "cpu";
 			compatible = "arm,cortex-a12";
 			reg = <0x500>;
+			enable-method = "psci";
 			resets = <&cru SRST_CORE0>;
 			operating-points-v2 = <&cpu_opp_table>;
 			#cooling-cells = <2>; /* min followed by max */
@@ -81,6 +87,7 @@
 			device_type = "cpu";
 			compatible = "arm,cortex-a12";
 			reg = <0x501>;
+			enable-method = "psci";
 			resets = <&cru SRST_CORE1>;
 			operating-points-v2 = <&cpu_opp_table>;
 			#cooling-cells = <2>; /* min followed by max */
@@ -92,6 +99,7 @@
 			device_type = "cpu";
 			compatible = "arm,cortex-a12";
 			reg = <0x502>;
+			enable-method = "psci";
 			resets = <&cru SRST_CORE2>;
 			operating-points-v2 = <&cpu_opp_table>;
 			#cooling-cells = <2>; /* min followed by max */
@@ -103,6 +111,7 @@
 			device_type = "cpu";
 			compatible = "arm,cortex-a12";
 			reg = <0x503>;
+			enable-method = "psci";
 			resets = <&cru SRST_CORE3>;
 			operating-points-v2 = <&cpu_opp_table>;
 			#cooling-cells = <2>; /* min followed by max */