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rk3588s orangepi cm5: fix YT8522C RMII clocking

This commit is contained in:
OrangePi CM5 Builder 2026-05-13 17:54:04 +08:00
parent 88fae346ea
commit c5ab82e420
1 changed files with 23 additions and 12 deletions
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35
external/patch/kernel/rockchip-rk3588-legacy/board_orangepicm5/0001-rk3588s-orangepi-cm5-gmac1-RMII-for-YT8522C.patch vendored
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@ -1,29 +1,41 @@
From ede9ed9d5582f744ed108c544316b90f7db678b3 Mon Sep 17 00:00:00 2001 From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
From: yuquanjun <yuquanjun@lookzn.cn> From: yuquanjun <yuquanjun@lookzn.cn>
Date: Tue, 12 May 2026 18:44:11 +0800 Date: Tue, 13 May 2026 00:00:00 +0800
Subject: [PATCH] rk3588s: orangepi-cm5: gmac1 RMII for YT8522C Subject: [PATCH] rk3588s: orangepi-cm5: gmac1 RMII for YT8522C on custom board
Configure GMAC1 for RMII mode with Motorcomm YT8522C PHY:
- Switch from RGMII to RMII mode
- SOC outputs 25MHz refclk (REFCLKO25M_ETH1_OUT) to PHY via GMAC_MCLK pin
- PHY address: 0x1 (PHYAD[1:0] = 2'b01 per schematic)
- PHY reset: GPIO1_C1 (active-low, per MR3588S_MB_BASE_V1.0 schematic)
- Remove RGMII-specific pinmux, tx/rx delay settings
- Add RMII clock pinmux (gmac1_clkinout)
--- ---
.../boot/dts/rockchip/rk3588s-orangepi-cm5.dts | 14 ++++---------- arch/arm64/boot/dts/rockchip/rk3588s-orangepi-cm5.dts | 17 +++++-----------
1 file changed, 4 insertions(+), 10 deletions(-) 1 file changed, 6 insertions(+), 11 deletions(-)
diff --git a/arch/arm64/boot/dts/rockchip/rk3588s-orangepi-cm5.dts b/arch/arm64/boot/dts/rockchip/rk3588s-orangepi-cm5.dts diff --git a/arch/arm64/boot/dts/rockchip/rk3588s-orangepi-cm5.dts b/arch/arm64/boot/dts/rockchip/rk3588s-orangepi-cm5.dts
index b9e4af46e..79c14ad02 100755 index b9e4af46e..49b96e821 100755
--- a/arch/arm64/boot/dts/rockchip/rk3588s-orangepi-cm5.dts --- a/arch/arm64/boot/dts/rockchip/rk3588s-orangepi-cm5.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3588s-orangepi-cm5.dts +++ b/arch/arm64/boot/dts/rockchip/rk3588s-orangepi-cm5.dts
@@ -123,31 +123,25 @@ ext_cam_ov5647_clk: external-camera-ov5647-clock { @@ -123,33 +123,30 @@ ext_cam_ov5647_clk: external-camera-ov5647-clock {
}; };
&gmac1 { &gmac1 {
- /* Use rgmii-rxid mode to disable rx delay inside Soc */ - /* Use rgmii-rxid mode to disable rx delay inside Soc */
- phy-mode = "rgmii-rxid"; - phy-mode = "rgmii-rxid";
+ phy-supply = <&vcc3v3_sys>;
+ phy-mode = "rmii"; + phy-mode = "rmii";
+ max-speed = <100>;
clock_in_out = "output"; clock_in_out = "output";
snps,reset-gpio = <&gpio3 RK_PB2 GPIO_ACTIVE_LOW>; - snps,reset-gpio = <&gpio3 RK_PB2 GPIO_ACTIVE_LOW>;
+ snps,reset-gpios = <&gpio1 RK_PC1 GPIO_ACTIVE_LOW>; /* YT8522C PHY reset */
snps,reset-active-low; snps,reset-active-low;
- /* Reset time is 20ms, 100ms for rtl8211f */ - /* Reset time is 20ms, 100ms for rtl8211f */
snps,reset-delays-us = <0 20000 100000>; - snps,reset-delays-us = <0 20000 100000>;
+ snps,reset-delays-us = <0 20000 50000>;
pinctrl-names = "default"; pinctrl-names = "default";
pinctrl-0 = <&gmac1_miim pinctrl-0 = <&gmac1_miim
@ -46,7 +58,6 @@ index b9e4af46e..79c14ad02 100755
+ rmii_phy1: phy@1 { + rmii_phy1: phy@1 {
compatible = "ethernet-phy-ieee802.3-c22"; compatible = "ethernet-phy-ieee802.3-c22";
reg = <0x1>; reg = <0x1>;
+ clocks = <&cru REFCLKO25M_ETH1_OUT>;
};
}; };
--
2.34.1