orangepi5: support ov13855

This commit is contained in:
orangepi-xunlong 2022-12-14 15:34:31 +08:00 committed by baiywt
parent 7ff5b3c7a6
commit d2ec819375
7 changed files with 444 additions and 30 deletions

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@ -25,6 +25,9 @@ dtbo-$(CONFIG_ARCH_ROCKCHIP) += \
rk3588-ov13850-c1.dtbo \
rk3588-ov13850-c2.dtbo \
rk3588-ov13850-c3.dtbo \
rk3588-ov13855-c1.dtbo \
rk3588-ov13855-c2.dtbo \
rk3588-ov13855-c3.dtbo \
rk3588-ssd-sata.dtbo
scr-$(CONFIG_ARCH_ROCKCHIP) += \

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@ -0,0 +1,100 @@
/dts-v1/;
/plugin/;
/ {
fragment@0 {
target = <&csi2_dphy0_hw>;
__overlay__ {
status = "okay";
};
};
fragment@1 {
target = <&csi2_dphy0>;
__overlay__ {
status = "okay";
};
};
fragment@2 {
target = <&mipi2_csi2>;
__overlay__ {
status = "okay";
};
};
fragment@3 {
target = <&rkcif_mipi_lvds2>;
__overlay__ {
status = "okay";
};
};
fragment@4 {
target = <&rkcif_mipi_lvds2_sditf>;
__overlay__ {
status = "okay";
};
};
fragment@5 {
target = <&rkisp0_vir1>;
__overlay__ {
status = "okay";
};
};
fragment@6 {
target = <&i2c7>;
__overlay__ {
status = "okay";
dw9714-p1@c {
status = "okay";
};
ov13855-1@36 {
status = "okay";
};
};
};
fragment@7 {
target = <&rkcif>;
__overlay__ {
status = "okay";
};
};
fragment@8 {
target = <&rkcif_mmu>;
__overlay__ {
status = "okay";
};
};
fragment@9 {
target = <&rkisp0>;
__overlay__ {
status = "okay";
};
};
fragment@10 {
target = <&isp0_mmu>;
__overlay__ {
status = "okay";
};
};
};

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@ -0,0 +1,94 @@
/dts-v1/;
/plugin/;
/ {
compatible = "rockchip,rk3588s-orangepi-5", "rockchip,rk3588";
fragment@0 {
target = <&csi2_dcphy0>;
__overlay__ {
status = "okay";
};
};
fragment@1 {
target = <&mipi0_csi2>;
__overlay__ {
status = "okay";
};
};
fragment@2 {
target = <&rkcif_mipi_lvds>;
__overlay__ {
status = "okay";
};
};
fragment@3 {
target = <&rkcif_mipi_lvds_sditf>;
__overlay__ {
status = "okay";
};
};
fragment@4 {
target = <&rkisp0_vir0>;
__overlay__ {
status = "okay";
};
};
fragment@6 {
target = <&i2c7>;
__overlay__ {
status = "okay";
dw9714-p2@c {
status = "okay";
};
ov13855-2@36 {
status = "okay";
};
};
};
fragment@7 {
target = <&rkcif>;
__overlay__ {
status = "okay";
};
};
fragment@8 {
target = <&rkcif_mmu>;
__overlay__ {
status = "okay";
};
};
fragment@9 {
target = <&rkisp0>;
__overlay__ {
status = "okay";
};
};
fragment@10 {
target = <&isp0_mmu>;
__overlay__ {
status = "okay";
};
};
};

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@ -0,0 +1,94 @@
/dts-v1/;
/plugin/;
/ {
compatible = "rockchip,rk3588s-orangepi-5", "rockchip,rk3588";
fragment@0 {
target = <&csi2_dcphy1>;
__overlay__ {
status = "okay";
};
};
fragment@1 {
target = <&mipi1_csi2>;
__overlay__ {
status = "okay";
};
};
fragment@2 {
target = <&rkcif_mipi_lvds1>;
__overlay__ {
status = "okay";
};
};
fragment@3 {
target = <&rkcif_mipi_lvds1_sditf>;
__overlay__ {
status = "okay";
};
};
fragment@4 {
target = <&rkisp1_vir0>;
__overlay__ {
status = "okay";
};
};
fragment@5 {
target = <&i2c2>;
__overlay__ {
status = "okay";
dw9714@c {
status = "okay";
};
ov13855@36 {
status = "okay";
};
};
};
fragment@6 {
target = <&rkcif>;
__overlay__ {
status = "okay";
};
};
fragment@7 {
target = <&rkcif_mmu>;
__overlay__ {
status = "okay";
};
};
fragment@8 {
target = <&rkisp1>;
__overlay__ {
status = "okay";
};
};
fragment@9 {
target = <&isp1_mmu>;
__overlay__ {
status = "okay";
};
};
};

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@ -9,30 +9,37 @@
};
&csi2_dphy0 {
status = "disabled";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
#address-cells = <1>;
#size-cells = <0>;
mipi_in_ucam0: endpoint@1 {
reg = <1>;
remote-endpoint = <&ov13850_out2>;
data-lanes = <1 2 3 4>;
};
};
port@1 {
reg = <1>;
#address-cells = <1>;
#size-cells = <0>;
csidphy0_out: endpoint@0 {
reg = <0>;
remote-endpoint = <&mipi2_csi2_input>;
};
};
};
status = "disabled";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
#address-cells = <1>;
#size-cells = <0>;
mipi_in_ucam0: endpoint@0 {
reg = <0>;
remote-endpoint = <&ov13850_out2>;
data-lanes = <1 2>;
};
mipi_in_ucam1: endpoint@1 {
reg = <1>;
remote-endpoint = <&ov13855_out2>;
data-lanes = <1 2>;
};
};
port@1 {
reg = <1>;
#address-cells = <1>;
#size-cells = <0>;
csidphy0_out: endpoint@0 {
reg = <0>;
remote-endpoint = <&mipi2_csi2_input>;
};
};
};
};
&i2c7 {
@ -66,7 +73,41 @@
port {
ov13850_out2: endpoint {
remote-endpoint = <&mipi_in_ucam0>;
data-lanes = <1 2 3 4>;
data-lanes = <1 2>;
};
};
};
dw9714_p1: dw9714-p1@c {
compatible = "dongwoon,dw9714";
status = "disabled";
reg = <0x0c>;
rockchip,camera-module-index = <0>;
rockchip,vcm-start-current = <10>;
rockchip,vcm-rated-current = <85>;
rockchip,vcm-step-mode = <5>;
rockchip,camera-module-facing = "back";
};
ov13855_1: ov13855-1@36 {
compatible = "ovti,ov13855";
status = "disabled";
reg = <0x36>;
clocks = <&cru CLK_MIPI_CAMARAOUT_M3>;
clock-names = "xvclk";
pinctrl-names = "default";
pinctrl-0 = <&mipim0_camera3_clk>;
reset-gpios = <&gpio3 RK_PC4 GPIO_ACTIVE_HIGH>;
pwdn-gpios = <&gpio3 RK_PC6 GPIO_ACTIVE_HIGH>;
rockchip,camera-module-index = <0>;
rockchip,camera-module-facing = "back";
rockchip,camera-module-name = "CMK-OT2016-FV1";
rockchip,camera-module-lens-name = "default";
lens-focus = <&dw9714_p1>;
port {
ov13855_out2: endpoint {
remote-endpoint = <&mipi_in_ucam1>;
data-lanes = <1 2>;
};
};
};

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@ -15,11 +15,17 @@
#address-cells = <1>;
#size-cells = <0>;
mipi_in_ucam1: endpoint@1 {
reg = <1>;
mipi_in_cam0: endpoint@0 {
reg = <0>;
remote-endpoint = <&ov13850_out>;
data-lanes = <1 2>;
};
mipi_in_cam1: endpoint@1 {
reg = <1>;
remote-endpoint = <&ov13855_out>;
data-lanes = <1 2>;
};
};
port@1 {
@ -67,7 +73,43 @@
lens-focus = <&vm149c_p2>;
port {
ov13850_out: endpoint {
remote-endpoint = <&mipi_in_ucam1>;
remote-endpoint = <&mipi_in_cam0>;
data-lanes = <1 2>;
};
};
};
dw9714_p2: dw9714-p2@c {
compatible = "dongwoon,dw9714";
status = "disabled";
reg = <0x0c>;
rockchip,camera-module-index = <0>;
rockchip,vcm-start-current = <10>;
rockchip,vcm-rated-current = <85>;
rockchip,vcm-step-mode = <5>;
rockchip,camera-module-facing = "back";
};
ov13855_2: ov13855-2@36 {
compatible = "ovti,ov13855";
status = "disabled";
reg = <0x36>;
clocks = <&cru CLK_MIPI_CAMARAOUT_M4>;
clock-names = "xvclk";
power-domains = <&power RK3588_PD_VI>;
pinctrl-names = "default";
pinctrl-0 = <&mipim0_camera4_clk>;
rockchip,grf = <&sys_grf>;
reset-gpios = <&gpio1 RK_PB2 GPIO_ACTIVE_HIGH>;
pwdn-gpios = <&gpio3 RK_PC1 GPIO_ACTIVE_HIGH>;
rockchip,camera-module-index = <0>;
rockchip,camera-module-facing = "back";
rockchip,camera-module-name = "CMK-OT2016-FV1";
rockchip,camera-module-lens-name = "default";
lens-focus = <&dw9714_p2>;
port {
ov13855_out: endpoint {
remote-endpoint = <&mipi_in_cam1>;
data-lanes = <1 2>;
};
};

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@ -16,9 +16,15 @@
#address-cells = <1>;
#size-cells = <0>;
mipi_in_dcphy0: endpoint@0 {
reg = <0>;
remote-endpoint = <&ov13850_out1>;
data-lanes = <1 2>;
};
mipi_in_dcphy1: endpoint@1 {
reg = <1>;
remote-endpoint = <&ov13850_out1>;
remote-endpoint = <&ov13855_out1>;
data-lanes = <1 2>;
};
};
@ -53,7 +59,6 @@
reg = <0x10>;
clocks = <&cru CLK_MIPI_CAMARAOUT_M4>;
clock-names = "xvclk";
//power-domains = <&power RK3588_PD_VI>;
pinctrl-names = "default";
pinctrl-0 = <&mipim0_camera4_clk>;
rockchip,grf = <&sys_grf>;
@ -66,6 +71,41 @@
lens-focus = <&vm149cp1>;
port {
ov13850_out1: endpoint {
remote-endpoint = <&mipi_in_dcphy0>;
data-lanes = <1 2>;
};
};
};
dw9714: dw9714@c {
compatible = "dongwoon,dw9714";
status = "disabled";
reg = <0x0c>;
rockchip,camera-module-index = <0>;
rockchip,vcm-start-current = <10>;
rockchip,vcm-rated-current = <85>;
rockchip,vcm-step-mode = <5>;
rockchip,camera-module-facing = "front";
};
ov13855_3: ov13855@36 {
compatible = "ovti,ov13855";
status = "disabled";
reg = <0x36>;
clocks = <&cru CLK_MIPI_CAMARAOUT_M4>;
clock-names = "xvclk";
pinctrl-names = "default";
pinctrl-0 = <&mipim0_camera4_clk>;
rockchip,grf = <&sys_grf>;
reset-gpios = <&gpio1 RK_PA6 GPIO_ACTIVE_HIGH>;
pwdn-gpios = <&gpio3 RK_PC5 GPIO_ACTIVE_HIGH>;
rockchip,camera-module-index = <1>;
rockchip,camera-module-facing = "front";
rockchip,camera-module-name = "CMK-OT2016-FV1";
rockchip,camera-module-lens-name = "default";
lens-focus = <&dw9714>;
port {
ov13855_out1: endpoint {
remote-endpoint = <&mipi_in_dcphy1>;
data-lanes = <1 2>;
};