Commit Graph

1617 Commits

Author SHA1 Message Date
Lin Jinhan 5e16d409fe arm64: dts: rockchip: rk3528: trng use scmi clk
Change-Id: I7a8bb9e824e9e7732a8fc497a2c828980086bd65
Signed-off-by: Lin Jinhan <troy.lin@rock-chips.com>
2023-02-15 09:37:43 +00:00
Joseph Chen e18f50d371 arm64: dts: rockchip: rk3528: crypto use scmi clock and dummy softrst
Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
Change-Id: I3340c8a2acb2ee4913e42a558f321e62f63899a2
2023-02-15 09:37:43 +00:00
Finley Xiao c44d1ff0ab clk: rockchip: rk3562: Add clock ids for secure crypto
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
Change-Id: Ic2614c5ff312e6a2b69b481eb5d794c97e6f711e
2023-02-09 20:48:24 +08:00
Finley Xiao 14d8aa4a04 clk: rockchip: add dt-binding header for rk3562
Add the dt-bindings header for the rk3562, that gets shared between
the clock controller and the clock references in the dts.
Add softreset ID for rk3562.

Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
Signed-off-by: Liang Chen <cl@rock-chips.com>
Change-Id: I25c4b2b8276f7d371ae861fdd24bd98fcf7c1629
2023-02-02 18:54:49 +08:00
Joseph Chen 7a7e67d633 clk: rockchip: add dt-binding header for rk3528
Add the dt-bindings header for the rk3528, that gets shared between
the clock controller and the clock references in the dts.
Add softreset ID for rk3528.

Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
Change-Id: I465f0a3c7fc36eee4c2ab0de38a810b8e691d41e
2022-12-21 19:05:45 +08:00
Finley Xiao 6b9329bb95 clk: rockchip: rk3128: Add sclk_hsadc_tsp
Change-Id: I842869a7ea79730daa6616f1cf2a8f5db7165ceb
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
2022-12-08 11:57:54 +08:00
Elaine Zhang 87c43bed76 clk: rockchip: rk3288: fix up the clk register for hclk_vio
Change-Id: If07e27b1f88974fa0dcb2c8f719df6ba3c35dbcd
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
2022-11-07 15:26:24 +08:00
Wyon Bi 88873a50fa clk/rockchip: rk3288: Add support for sclk_testout
Change-Id: Ibd521712a6517300984db4199ac0164a499dc0f7
Signed-off-by: Wyon Bi <bivvy.bi@rock-chips.com>
Signed-off-by: Guochun Huang <hero.huang@rock-chips.com>
2022-11-07 15:26:02 +08:00
Finley Xiao 485bbe0375 clk: rockchip: rk3288: Add TSP clock
Change-Id: I02185c5ab7a1072d271cd51161f6d4b05d327673
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
2022-11-07 15:25:57 +08:00
Finley Xiao 4d1b83cce8 clk: rockchip: rk3288: Add id for i2s_src
Change-Id: I0d15dd656e96a3905012d42fef6640e152838888
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
2022-11-07 15:25:53 +08:00
Jacob Chen 4d78dbf449 clk: rockchip: associate SCLK_MAC_PLL on rk3288
see:
http://elixir.free-electrons.com/linux/v4.8/source/Documentation/devicetree/bindings/net/rockchip-dwmac.txt#L32

Change-Id: Ibf94d88219b13f5dd16cfdeb02d1b255e695399f
Signed-off-by: Jacob Chen <jacob-chen@iotwrt.com>
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
2022-11-07 15:25:42 +08:00
Finley Xiao e9b2f6ce99 clk: rockchip: rk3288: add ddrc clock support
Add a ddrc clock into clk branches, so we can do ddr frequency
scaling on rk3288 platform in future.

Change-Id: Ia6c93e5ce82fa30475eddf051bc9ea2512b0cc07
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
2022-11-07 15:25:36 +08:00
Frank Wang 2550716315 clk: rockchip: rk3288: add gate id of hclk_usb_peri for usb otg
Change-Id: Ib45f6d97ec81329ec9a4a19e9e836efa0ea61fe2
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
2022-11-07 15:25:26 +08:00
Elaine Zhang 676b9d98e7 clk: rockchip: rk3588: Fixed clock properties for aclk_vop
aclk_vop->aclk_vop_root (1:1) by default.
aclk_vop->aclk_vop_div2_src->aclk_vop_root (1:2) for special case.

Fixes: af14a79ae3 ("rk3588: support aclk_vop_sub_src set parent to aclk_vop_div2_src")
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Change-Id: Ica7ae4d614a4b0bb49d047fe0e20d9b7104df759
2022-10-18 19:22:43 +08:00
Sandy Huang 97d06e74fb clk: rockchip: rk3128: add clk gate for PCLK_MIPIPHY
Change-Id: Icf55c315edc9514a23d00433ffe56c864ad7f3d8
Signed-off-by: Sandy Huang <hjc@rock-chips.com>
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
2022-10-17 11:40:55 +08:00
Finley Xiao 00ae13ff18 dt-bindings: update SPDX-License-Identifier for rockchip clock header
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
Change-Id: I626838b5d18f1a0007f03dfd6132821ff01a026c
2022-09-07 14:36:08 +08:00
Elaine Zhang 3724dcef5f clk: rockchip: px30: support px30s
Change-Id: Id86199e066e254279d59a76aaed02f657b40e0c7
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
2022-07-22 17:02:55 +08:00
Xing Zheng 54a7a1cc01 clk: rockchip: rv1106: remove the mclk_acodec_rx
Dues to the broken doc, there is no path of
mclk_i2s0_rx to mclk_acodec_rx, we need to
remove it directly and let mclk_acodec_tx
below to the mclk_i2s0_8ch_tx.

- Before:
          clk_i2s0_8ch_rx_src         1        1        0   594000000          0     0  50000
             clk_i2s0_8ch_rx_frac       1        1        0    12288000          0     0  50000
                clk_i2s0_8ch_rx       1        1        0    12288000          0     0  50000
                   mclk_i2s0_8ch_rx       2        2        0    12288000          0     0  50000
                      mclk_acodec_rx       1        1        0    12288000          0     0  50000
          clk_i2s0_8ch_tx_src         1        1        0   594000000          0     0  50000
             clk_i2s0_8ch_tx_frac       1        1        0    12288000          0     0  50000
                clk_i2s0_8ch_tx       1        1        0    12288000          0     0  50000
                   mclk_i2s0_8ch_tx       2        2        0    12288000          0     0  50000
                      mclk_acodec_tx       1        1        0    12288000          0     0  50000

- After:
          clk_i2s0_8ch_rx_src         1        1        0   594000000          0     0  50000
             clk_i2s0_8ch_rx_frac       1        1        0    12288000          0     0  50000
                clk_i2s0_8ch_rx       1        1        0    12288000          0     0  50000
                   mclk_i2s0_8ch_rx       1        1        0    12288000          0     0  50000
          clk_i2s0_8ch_tx_src         1        1        0   594000000          0     0  50000
             clk_i2s0_8ch_tx_frac       1        1        0    12288000          0     0  50000
                clk_i2s0_8ch_tx       1        1        0    12288000          0     0  50000
                   mclk_i2s0_8ch_tx       2        2        0    12288000          0     0  50000
                      mclk_sai        0        0        0    12288000          0     0  50000
                      mclk_dsm        0        0        0    12288000          0     0  50000
                      mclk_acodec_tx       1        1        0    12288000          0     0  50000

Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
Change-Id: I223189b6852f2e796eeb01ad4ce957fde7f9a52c
2022-03-28 18:56:33 +08:00
Elaine Zhang 092e33390d clk : rockchip: rv1106: add grf clk
add grf clk for emmc\sdio\sdmmc sample and dev.

Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Change-Id: I6b048dd456c1be280b5e5f7711e672efb4572e03
2022-03-25 14:44:59 +08:00
Elaine Zhang 1ce367190e clk: rockchip: rv1106: export pclk_mailbox clk id
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Change-Id: I84c8d8e3987af45b72db8eccbf97b7fc842f6205
2022-03-01 11:14:02 +08:00
Elaine Zhang 33b5055b63 clk: rockchip: add dt-binding header for rv1106
Add the dt-bindings header for the rv1106, that gets shared between
the clock controller and the clock references in the dts.
Add softreset ID for rv1106.

Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Change-Id: Ia5bd903c6dc9caf925277fd42f873d8e8d6f643a
2022-01-25 17:55:08 +08:00
Elaine Zhang 6926e98d70 clk: rockchip: rk3588: export hdmirx_biu soft reset id
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Change-Id: I37c1f67bd62eabe3b0cfa2e1b304a3ae1950b66e
2022-01-25 16:41:58 +08:00
Tao Huang f6909c028f Merge tag 'ASB-2021-12-05_12-5.10' of https://android.googlesource.com/kernel/common
https://source.android.com/security/bulletin/2021-12-01
CVE-2021-33909
CVE-2021-38204
CVE-2021-0961

* tag 'ASB-2021-12-05_12-5.10': (3010 commits)
  ANDROID: workqueue: export symbol of the function wq_worker_comm()
  ANDROID: GKI: Update symbols to symbol list
  ANDROID: vendor_hooks: Add hooks for binder proc transaction
  ANDROID: GKI: Add symbols abi for USB IP kernel modules.
  ANDROID: GKI: Fix file mode on mtk abi file
  UPSTREAM: erofs: fix deadlock when shrink erofs slab
  ANDROID: init_task: Init android vendor and oem data
  UPSTREAM: sched/core: Mitigate race cpus_share_cache()/update_top_cache_domain()
  ANDROID: Update symbol list for mtk
  UPSTREAM: erofs: fix unsafe pagevec reuse of hooked pclusters
  UPSTREAM: erofs: remove the occupied parameter from z_erofs_pagevec_enqueue()
  UPSTREAM: usb: dwc3: gadget: Fix null pointer exception
  ANDROID: fips140: support "evaluation testing" builds via build.sh
  FROMGIT: sched/scs: Reset task stack state in bringup_cpu()
  ANDROID: dma-buf: heaps: fix dma-buf heap pool pages stat
  ANDROID: ABI: Add several spi_mem related symbols
  UPSTREAM: spi: spi-mem: add spi_mem_dtr_supports_op()
  ANDROID: gki_defconfig: enable CONFIG_SPI_MEM
  ANDROID: ABI: Add several iio related symbols
  ANDROID: ABI: Update symbol list for IMX
  ...

Change-Id: I09cddc92fa34553b944e62cc5cbbba94a84e5437

Conflicts:
	arch/arm/boot/dts/rk322x.dtsi
	arch/arm64/boot/dts/rockchip/rk3399.dtsi
	drivers/dma-buf/heaps/system_heap.c
	drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c
	drivers/gpu/drm/rockchip/rockchip_drm_vop.c
	drivers/gpu/drm/rockchip/rockchip_lvds.c
	drivers/gpu/drm/rockchip/rockchip_vop_reg.c
	drivers/mtd/nand/spi/core.c
	drivers/pci/controller/pcie-rockchip-host.c
	drivers/soc/rockchip/Kconfig
	drivers/usb/dwc3/core.c
	drivers/usb/dwc3/core.h
2021-12-14 17:09:02 +08:00
Elaine Zhang 1f57d9eb1b clk: rockchip: rk3588: export clk_phy0/1_ref_alt_p/m clk id
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Change-Id: I149c43cd77f777c9d45c095be8c0c77c126b56d2
2021-12-02 18:10:18 +08:00
Wyon Bi 6f62dc64fe Revert "clk: rockchip: rk3588: export pclk_vopgrf id for vop"
This reverts commit 9c9db5fd41.

Signed-off-by: Wyon Bi <bivvy.bi@rock-chips.com>
Change-Id: I11ef7f3e52cb7512acbc638a67e75c9295ddbbdd
2021-11-25 15:10:00 +08:00
Wyon Bi 9c9db5fd41 clk: rockchip: rk3588: export pclk_vopgrf id for vop
Signed-off-by: Wyon Bi <bivvy.bi@rock-chips.com>
Change-Id: I1d1d2b8d0a87763f1671ce0bc6f9933caaac3800
2021-11-23 20:59:23 +08:00
Elaine Zhang d3a274cb5e Revert "clk: rockchip: rk3588: export clk_gmac id"
This reverts commit de8a7dc11e.

Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Change-Id: I10be8115666498baf872a40fc9c72964744f3243
2021-11-05 11:32:52 +08:00
Elaine Zhang 9528bfc14a clk: rockchip: rk3588: export clk_aux16m_x id for dp
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Change-Id: Iec7deb4005d4ce3b842eccd89018a7d9f335434c
2021-10-28 16:31:46 +08:00
Wyon Bi 3082499844 clk/rockchip/regmap: rk628: Add support for clk_testout
Change-Id: I71f5ca1d4002d45438ff9d038ccc7eef5a28a857
Signed-off-by: Wyon Bi <bivvy.bi@rock-chips.com>
2021-10-18 16:56:42 +08:00
Elaine Zhang de8a7dc11e clk: rockchip: rk3588: export clk_gmac id
The mux of Clk_gmac is special and is in the php_grf register.

Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Change-Id: I678f87a48b04a9701029f455d2e67378ca9072b6
2021-09-06 19:18:27 +08:00
Elaine Zhang 5df480db6f clk: rockchip: rk3588: rename some clks
1) rename pvtm clks name;
2) usbdp and mipidphy share one ref clk;
3) hdmitx, hdmirx, and usb2phy share one ref clk;

Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Change-Id: I2c85609359424ed388a051f4bb04b0d401c05d12
2021-08-27 17:42:18 +08:00
Elaine Zhang 4834c511d2 clk: rockchip: rk3399: fix up the spi softrst ID
fix up the spi3 and spi5 softrst ID.

Change-Id: Ib8870ef765284e04674ce80acf0b4702ed77cebc
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
2021-08-25 17:58:42 +08:00
Mark Yao 21dc499588 rockchip: clk: rk3399: default enable dual pll for vop
Change-Id: I88a2a549eaafa91e4159f262a5f5838c834a89e9
Signed-off-by: Mark Yao <mark.yao@rock-chips.com>
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
2021-08-25 17:07:22 +08:00
Elaine Zhang 958d13f841 arm64: dts: rockchip: rk3588: fix up the clocks
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Change-Id: I4136922bea4e4e47e580a644593f7b98310623e7
2021-08-23 19:16:56 +08:00
Elaine Zhang 9a7bdd5455 clk: rockchip: add dt-binding header for rk3588
Add the dt-bindings header for the rk3588, that gets shared between
the clock controller and the clock references in the dts.
Add softreset ID for rk3588.

Change-Id: I9fa9d27a187a6951c5c1cf210b0eff988a41457e
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
2021-08-20 15:11:16 +08:00
Tao Huang 4bb7503ad3 dt-bindings: clock: Remove unused rockchip files
Signed-off-by: Tao Huang <huangtao@rock-chips.com>
Change-Id: I9a528f75413a7376407afff4e0737747d6f66a87
2021-08-11 16:32:38 +08:00
Randy Li 3eddd5dd86 clk: rockchip: rk3036: export the sfc clocks
The serial Flash controller on the rk3036 would request
two clock nodes.

Change-Id: Iaa50c4a25602a68241b0b9b2f186e4c7e55bc3da
Signed-off-by: Randy Li <randy.li@rock-chips.com>
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
2021-08-04 21:26:51 +08:00
Caesar Wang 54a9bb2c72 clk: rockchip: export SCLK_I2S_PRE and SCLK_I2S_FRAC of i2s on rk3036
Change-Id: I627c8c2582be2b27414e7b82e9d56dd560f68e64
Signed-off-by: Caesar Wang <wxt@rock-chips.com>
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
2021-08-04 21:26:51 +08:00
Randy Li e35fd036b3 clk: rockchip: rk3036: export the hevc core clock
The clock hevc core will be used to drive the hevc decoder.

Change-Id: Ic1298ce1edd07f86e5c243e3a2c9876481f4cba9
Signed-off-by: Randy Li <randy.li@rock-chips.com>
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
2021-08-04 21:26:51 +08:00
Finley Xiao f467c0ecb0 clk: rockchip: rk3066a: Rename i2s hclk id
Change-Id: I0a5ccf1846950353ea6fc6980c1c4a4fb3457fd1
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
2021-08-04 20:40:34 +08:00
Elaine Zhang 3151edc8a4 clk: rockchip: Avoid __clk_lookup() calls
clk pointer gets cached in the driver's private data and
can be used later instead of a __clk_lookup() call.

clk provider clk_data.clks[] and we can reference
the clk pointers directly rather than using __clk_lookup()
with global names.

Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Change-Id: I058413a912e0eaf5bf551d2515ad55ae28709985
2021-07-22 16:08:56 +08:00
Lucas Stach 581098969c clk: imx8mq: remove SYS PLL 1/2 clock gates
[ Upstream commit c586f53ae159c6c1390f093a1ec94baef2df9f3a ]

Remove the PLL clock gates as the allowing to gate the sys1_pll_266m breaks
the uSDHC module which is sporadically unable to enumerate devices after
this change. Also it makes AMP clock management harder with no obvious
benefit to Linux, so just revert the change.

Link: https://lore.kernel.org/r/20210528180135.1640876-1-l.stach@pengutronix.de
Fixes: b04383b6a5 ("clk: imx8mq: Define gates for pll1/2 fixed dividers")
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Reviewed-by: Abel Vesa <abel.vesa@nxp.com>
Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
Signed-off-by: Sasha Levin <sashal@kernel.org>
2021-07-14 16:56:20 +02:00
Sugar Zhang 2b1b3a5b70 clk: rockchip: px30: Export clk id for sclk_i2s0_tx/rx mux
Change-Id: I697d20fb0c69f9dcd76aaf2d18d666db2241360d
Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
2021-07-02 17:17:40 +08:00
Elaine Zhang 35e637b1a5 clk: rockchip: rk3128: add hclk_sfc
Change-Id: I20d0975156dc73bcdd02c09b7ecb815d5aca6bc6
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
2021-05-18 20:33:37 +08:00
Elaine Zhang 9322b4700a clk: rockchip: rk3288: export PCLK_PD_PMU and PCLK_PD_ALIVE clock id
Change-Id: Ie0550d9528367fa070328562fad2e597a5d6d7f7
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
2021-05-18 20:33:36 +08:00
Elaine Zhang b1d64bdb31 clk: rockchip: rk3368: add aclk_cci_pre ID
Change-Id: I855e79023a9e244c2db37af88a075a4ef4c36aec
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
2021-05-18 20:33:36 +08:00
Elaine Zhang 64f77336b9 clk: rockchip: rk3399: fix up the clk tree description for clk_uart4
slove clk_uart4 set rate error.

Change-Id: Icf8f36a5c68658ed92a1b794dc68f37c729d2646
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
2021-04-02 11:51:49 +08:00
Elaine Zhang 7b581139c3 clk: rockchip: rk3399: fix up some regs description error
Change-Id: Ia992b20f13ba7037b93fcd2fbd67a4d6b3fd1266
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
2021-04-02 11:51:07 +08:00
Elaine Zhang 9de42c75ff clk: rockchip: rk3399: export SCLK_I2SOUT_SRC clk ID for i2s
Change-Id: Ifbcea830e5f49946c1feea3f51d125e6ed566d5f
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
2021-04-02 11:50:54 +08:00
Elaine Zhang d658ee9626 clk: rockchip: rk3399: export CIF_OUT_SRC clock id for cif
Change-Id: I77423891821dae0412dda4414222ba64bd0a4a4a
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
2021-04-02 11:50:37 +08:00