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Author SHA1 Message Date
Sugar Zhang 645df41e1c arm64: dts: rockchip: rk3562: Use mclk{out,in}_saix for devices 
e.g.

1. mclkout_sai0:

  &ext_codec {
      clocks = <&mclkout_sai0>;
      clock-names = "mclk";
      assigned-clocks = <&mclkout_sai0>;
      assigned-clock-rates = <12288000>;
      pinctrl-names = "default";
      pinctrl-0 = <&i2s0m0_mclk>;
  };

  clk_summary on sai0 work:

  cat /sys/kernel/debug/clk/clk_summary | egrep "pll|sai0"

  clk_sai0_src                1        1        0  1188000000          0     0  50000
    clk_sai0_frac             1        1        0    12288000          0     0  50000
      clk_sai0                1        1        0    12288000          0     0  50000
        mclk_sai0             1        1        0    12288000          0     0  50000
          mclk_sai0_out2io    1        1        0    12288000          0     0  50000
            mclk_sai0_to_io   1        1        0    12288000          0     0  50000

2. mclkin_sai0:

  &ext_codec {
      clocks = <&mclkin_sai0>;
      clock-names = "mclk";
      assigned-clocks = <&cru CLK_SAI0>;
      assigned-clock-parents = <&mclkin_sai0>;
      pinctrl-names = "default";
      pinctrl-0 = <&i2s0m0_mclk>;
  };

  clk_summary on sai0 work:

  cat /sys/kernel/debug/clk/clk_summary | egrep "pll|sai0"

  mclk_sai0_from_io          1        1        0    12288000          0     0  50000
    clk_sai0                 1        1        0    12288000          0     0  50000
      mclk_sai0              1        1        0    12288000          0     0  50000
        mclk_sai0_out2io     0        0        0    12288000          0     0  50000
          mclk_sai0_to_io    0        0        0    12288000          0     0  50000

Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>
Change-Id: Ib8441bfd0dbb69353a6492f2d406b29a26d1dba0
 2023-02-21 09:50:13 +08:00
Finley Xiao 2df94e8259 arm64: dts: rockchip: Add RK3562 evaluation board devicetree 
evb1: LPDDR4/LPDDR4X + RK817 + ECM MIC
evb2: DDR4 + RK809 + RTC IC with external BAT + SPI Flash + MEMS MIC

The rk3562-evb1 and rk3562-evb2 force the maximum-speed of
usb dwc3 controller to high-speed, it needs the following
two properties to fix usb compatibility issues.

1. Set "snps,dis_u2_susphy_quirk" to disable dwc3 controller
   suspend phy automatically. And the usb phy driver can
   manage phy suspend/normal mode by itself.

2. Set "snps,usb2-lpm-disable" to disable usb2 lpm for dwc3
   xhci controller. It can fix some usb disks with lpm broken
   issue.

Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
Signed-off-by: Li Huang <putin.li@rock-chips.com>
Signed-off-by: shengfei Xu <xsf@rock-chips.com>
Signed-off-by: Guochun Huang <hero.huang@rock-chips.com>
Signed-off-by: Chandler Chen <chandler.chen@rock-chips.com>
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
Signed-off-by: William Wu <william.wu@rock-chips.com>
Signed-off-by: Yifeng Zhao <yifeng.zhao@rock-chips.com>
Signed-off-by: Lin Jinhan <troy.lin@rock-chips.com>
Signed-off-by: Jake Wu <jake.wu@rock-chips.com>
Signed-off-by: Yu Qiaowei <cerf.yu@rock-chips.com>
Signed-off-by: Damon Ding <damon.ding@rock-chips.com>
Signed-off-by: Sandy Huang <hjc@rock-chips.com>
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Signed-off-by: Binyuan Lan <lby@rock-chips.com>
Signed-off-by: Jason Zhu <jason.zhu@rock-chips.com>
Signed-off-by: Alex Zhao <zzc@rock-chips.com>
Signed-off-by: Huibin Hong <huibin.hong@rock-chips.com>
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
Signed-off-by: David Wu <david.wu@rock-chips.com>
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>
Signed-off-by: Felix Zeng <felix.zeng@rock-chips.com>
Signed-off-by: Wangqiang Guo <kay.guo@rock-chips.com>
Change-Id: I066b6daa6d0f36ff0b28564f07f4d371c2796fd6
 2023-02-02 19:02:07 +08:00