Commit Graph

25 Commits

Author SHA1 Message Date
baiywt 38b0a66a10 Merge linux-5.10-gen-rkr6 2024-01-19 18:35:00 +08:00
orangepi-xunlong fba77f9a27 Support Orange Pi 5 Plus 2023-07-07 15:03:01 +08:00
baiywt 054e7f7707 Fix some boards cannot enter deep sleep mode 2023-07-07 15:03:01 +08:00
orangepi-xunlong e73a0ae2fc Prepare for Orange Pi 5 2023-07-07 15:02:44 +08:00
Jianqun Xu 76af1962e1 arm64: dts: rockchip: use rk3588s-pinconf.dtsi for rk3588s/rk3588
The rk3588s/rk3588 SoCs have 4 level for io drive-strength
2'b00: 2.5mA 100ohm
2'b01:   5mA  50ohm
2'b10: 7.5mA  33ohm
2'b11:  10mA  25ohm

Use rk3588s-pinconf.dtsi to only define specified drive strength levels.

Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
Change-Id: Ibed41ab49cc0c0f955448dd1d0b75e57ce4cac63
2023-01-11 15:15:24 +08:00
Jon Lin a366f684c2 arm64: dts: rockchip: rk3588s: Fix spi driver strength
Except spi2m2 which is used for pmic. all spi change from 33ohm to 40ohm
to avoid overcharge.

Change-Id: Ib1f613b19c1ca9f978c11a7d26422ff66b4b910c
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
2022-10-10 10:56:32 +08:00
Algea Cao 3690970c81 arm64: dts: rockchip: rk3588: Adjust the HDMI DDC IO driver strength
There is a bug in the HDMI controller DDC. The falling edge of
SDA and SCL almost coincide and cannot be adjusted, resulting
in poor compatibility of DDC. The compatibility of DDC can be
improved by increasing the driver strength of SCL and decreasing
the driver strength of SDA to increase the slope of the falling edge.

Signed-off-by: Algea Cao <algea.cao@rock-chips.com>
Change-Id: Ia7e70c3a8f7f3ee5e36f401919e36d045448250c
2022-08-31 10:09:36 +08:00
Wangqiang Guo 27366d4294 arm64: dts: rockchip: rk3588: fix hdmirx ddc communicate err.
Signed-off-by: Wangqiang Guo <kay.guo@rock-chips.com>
Change-Id: I8307283bf833fabdeef6f8911bf1d3b525db7a37
2022-08-10 15:29:29 +08:00
Algea Cao d2f8138d0c arm64: dts: rockchip: rk3588: Optimize hdmi ddc compatibility
Set hdmi ddc pin smt enable.

Signed-off-by: Algea Cao <algea.cao@rock-chips.com>
Change-Id: I12bc18f960bdd5890bb6281607a5edf88e5ddfb7
2022-07-11 15:50:02 +08:00
Dingxian Wen 1ee5d90938 arm64: dts: rockchip: rk3588: modify hdmirx pinctrl
add hdmim1_rx pinctrl group, set hdmirx detect pin to pull up.

Signed-off-by: Dingxian Wen <shawn.wen@rock-chips.com>
Change-Id: I637d5d432d5879ed69077f00907667102e83153d
2022-06-21 16:36:07 +08:00
Alex Zhao b96485b7af arm64: dts: rockchip: rk3588s fix sdio pins to pull up
The sdio requires the cmd and data pins to pull up by soc.

Signed-off-by: Alex Zhao <zzc@rock-chips.com>
Change-Id: I7390dad3e1af19c5cae778064e49e47eb8514baf
2022-04-19 09:11:53 +08:00
shengfei Xu 277361df6a arm64: dts: rockchip: rk3588: fix pmic_int pull-up on rk3588
RK806 INT pin is connected to pmic_int(gpio0a7).
the pmic_int sets low-level interrupt, which requires pull-up
voltage(VCC_1V8_S0). but the pull-up voltage is powered off
in system suspend, causing the system to wake up immediately.

Signed-off-by: shengfei Xu <xsf@rock-chips.com>
Change-Id: Id85b441c9ce7f9837e3c61647b39f03dd4c63e53
2022-01-13 14:13:39 +08:00
Jon Lin c7c9c50b55 arm64: dts: rockchip: rk3588: Set the default value of spi data strength to level1
1.The EVB signal test of this configuration is good.
2.This confitguration is compatible with 16MHz and 50MHz SI test case.

Change-Id: Ie259e2e8229d68013efa13278b0479c5dc73739c
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
2021-12-21 18:23:31 +08:00
Jon Lin 6a0b6f63ed arm64: dts: rockchip: rk3588s: remove spi high-speed pinctrl configuration
Change-Id: Ibde8d4498f0bd056803aafdad71a09d925a7927a
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
2021-12-21 18:23:31 +08:00
Damon Ding 9e02641588 arm64: dts: rockchip: rk3588: modify driver strength for bt656 pins
According to the SI report, reduce the driver strength
from 40ohm to 50ohm.

Signed-off-by: Damon Ding <damon.ding@rock-chips.com>
Change-Id: Iffd65851dfe6ac8032764a3fb44334d5c3dcd154
2021-12-16 11:24:05 +08:00
Jon Lin 4e7395fe28 arm64: dts: rockchip: rk3588: Fix FSPI io to ds level 2
55ohm is the recommended value after hardware signal test.

Change-Id: Iddb2d9eabfc5abb79662e25f40f5b332864aed15
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
2021-12-14 16:20:51 +08:00
Damon Ding 1ed78e4f4e arm64: dts: rockchip: rk3588: add pinctrl of bt656 mode
Signed-off-by: Damon Ding <damon.ding@rock-chips.com>
Change-Id: Ia659d2b486aa31fd36fc04c971620894e9db1d7e
2021-11-22 21:16:22 +08:00
Jianqun Xu 9f19c0d417 arm64: dts: rockchip: rk3588s-pinctrl fix mipi camera clks
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
Change-Id: Id33754b3c8dea5c36f0f84e49df4606f547077d8
2021-11-18 10:07:02 +08:00
Jianqun Xu cc6a4c9133 arm64: dts: rockchip: rk3588s-pinctrl define hdmi pins one by one
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
Change-Id: I747f3c5fb7316514458c24384a14997287bc106e
2021-11-16 16:58:45 +08:00
Steven Liu 57276b0cae arm64: dts: rockchip: rk3588/rk3588s: fix uart8m0 pinctrl
Signed-off-by: Steven Liu <steven.liu@rock-chips.com>
Change-Id: I7b475b4c81f31e5f8139c32e9bb530d01896db42
2021-11-12 20:39:34 +08:00
Jianqun Xu 675ff1b10a arm64: dts: rockchip: rk3588/rk3588s: fix pinctrl
Change-Id: I8291c7c89c1aa2a530536ddcbb349ea540ee7296
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
2021-11-09 17:21:05 +08:00
Jianqun Xu a75da01111 arm64: dts: rockchip: rk3588/rk3588s: fix pinctrl
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
Change-Id: I15b93a9ab1bbd40fe35e1b4ed94e84ad41c2cc28
2021-11-08 15:53:47 +08:00
Jon Lin 0e542bf348 arm64: dts: rockchip: rk3588s: add spi node
Change-Id: I4e72251952f5aae5b9588c4c5cb00de4f70b7ae1
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
2021-09-02 14:39:24 +08:00
Finley Xiao 3fbcef574f arm64: dts: rockchip: rk3588: Add gpio func for tsadc
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
Change-Id: I625871a5b6238ae664698a5fe81d911183a72a18
2021-08-27 17:35:22 +08:00
Jianqun Xu 53997ece58 arm64: dts: rockchip: rk3588s add pinctrl support
RK3588S SoC has 5 gpios, from gpio0 to gpio4.

Change-Id: Ic9b6e620aa4ba06223724edd8da3ec35d47d91da
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
2021-08-24 08:21:43 +08:00