qjyu
/
OrangePi_CM5
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity
85,434 Commits 5 Branches 0 Tags 3.3 GiB
Commit Graph

2 Commits

Author SHA1 Message Date
Ralf Baechle 17099b1142 [MIPS] Make support for weakly ordered LL/SC a config option. 
None of weakly ordered processor supported in tree need this but it seems
like this could change ...

Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
 2007-07-20 18:57:39 +01:00
Ralf Baechle 0004a9dfea [MIPS] Cleanup memory barriers for weakly ordered systems. 
Also the R4000 / R4600 LL/SC instructions imply a sync so no explicit sync
needed.

Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
 2006-12-04 22:43:14 +00:00