This patch adjust the RK3528 U3 Rx squelch input filler
bandwidth to 3'b110 which is used for rx_lfps, reduce the
bandwidth to avoid filtering valid superspeed data.
With this patch, it can fix the issue that Kingston U3 Disk
(idVendor=0951, idProduct=1666, bcdDevice= 1.10) read error
on RK3528 platforms.
Change-Id: Ifa4eac24bbdebe020db356ba45dae146f4df22f1
Signed-off-by: William Wu <william.wu@rock-chips.com>
This patch adjust the RK3562 U3 Rx squelch input filler
bandwidth to 3'b110 which is used for rx_lfps, reduce the
bandwidth to avoid filtering valid superspeed data.
With this patch, it can fix the issue that Kingston U3 Disk
(idVendor=0951, idProduct=1666, bcdDevice= 1.10) read error
on RK3562 platforms.
Change-Id: Idb667d159f9dba6b1de0a9ec04af9dae2d065927
Signed-off-by: William Wu <william.wu@rock-chips.com>
This patch adjust the RK3568 U3 Rx squelch input filler
bandwidth to 3'b110 which is used for rx_lfps, reduce the
bandwidth to avoid filtering valid superspeed data.
With this patch, it can fix the issue that Kingston U3 Disk
(idVendor=0951, idProduct=1666, bcdDevice= 1.10) read error
on RK3568 platforms.
Change-Id: I27410c5702862df2d8829a2ca3c2c1d9f57885be
Signed-off-by: William Wu <william.wu@rock-chips.com>
Fix set pll rate err when play hdr video first time after
system boot.
Signed-off-by: Algea Cao <algea.cao@rock-chips.com>
Change-Id: Ic85b8f8b20a2a588627f650ff402076decd23b63
Some special devices connected to host port, the linestate
maybe SE1 (DP/DM both in High level).
The below devices are the known special devices
Wireless HID: VID = 0xa604, PID = 0x0715
RK3308BS ADB: VID = 0x2207, PID = 0x0006
In order to support these special devices, this patch
handle the linestate SE1 as device connected state,
and power on the phy if it has already suspended.
Change-Id: I55fe83150c18d6c2629fbc857790ef04cdb68da5
Signed-off-by: William Wu <william.wu@rock-chips.com>
In hdmi2.0 resolution, the phase of D2 lane is probabilistically
ahead of other lanes. Set phy deskew FIFO works on shared pointer
to fix this problem.
According to vendor, this patch is also available for frl mode.
Signed-off-by: Algea Cao <algea.cao@rock-chips.com>
Change-Id: Ic6f5111ede5a553fb6d6511bd340d4f2010f3fe7
Test on RK3588S Tablet, set the power supply of logic on
and set the power supply of usb2 phy off during deep sleep,
then the id falling edge interrupt will be triggered after
system resume, and kernel panic with the following log:
SError Interrupt on CPU0, code 0xbe000011 -- SError
CPU: 0 PID: 1946 Comm: kworker/0:0 Not tainted 5.10.110 #600
Hardware name: Rockchip RK3588S TABLET RK806 SINGLE Board (DT)
Workqueue: events rockchip_usb2phy_otg_sm_work
pstate: 20c00009 (nzCv daif +PAN +UAO -TCO BTYPE=--)
pc : _raw_spin_unlock_irqrestore+0x28/0x60
lr : regmap_unlock_spinlock+0x18/0x28
......
Kernel panic - not syncing: Asynchronous SError Interrupt
CPU: 0 PID: 1946 Comm: kworker/0:0 Not tainted 5.10.110 #600
Hardware name: Rockchip RK3588S TABLET RK806 SINGLE Board (DT)
Workqueue: events rockchip_usb2phy_otg_sm_work
Call trace:
dump_backtrace+0x0/0x1c8
show_stack+0x1c/0x2c
dump_stack_lvl+0xdc/0x12c
dump_stack+0x1c/0x64
panic+0x150/0x3a4
test_taint+0x0/0x30
arm64_serror_panic+0x78/0x84
do_serror+0xe0/0x100
el1_error+0x94/0x118
_raw_spin_unlock_irqrestore+0x28/0x60
regmap_unlock_spinlock+0x18/0x28
regmap_write+0x68/0x84
rockchip_usb2phy_power_on+0x128/0x1f0
rockchip_usb2phy_otg_sm_work+0x1d0/0x454
process_one_work+0x1f4/0x490
worker_thread+0x278/0x4dc
kthread+0x13c/0x344
ret_from_fork+0x10/0x30
In fact, there are two issues here.
1. The power of phy id belongs to the usb2 phy power supply.
And the id is pulled up to high level by default. So if we
power off usb2 phy supply during deep sleep, the id status
will fall to low level and trigger the falling edge interrupt.
In the id irq handler rockchip_usb2phy_id_irq(), it send Host
notification only depends the id falling edge irq status, it's
not enough in this case, it needs to check the iddig status
to make sure that the id status is indeed in low level.
2. For RK3588S, the pipe phystatus select register from the
usb grf, and the power domain of usb grf belongs to PD_USB.
So we must make sure the PD_USB is on when operate the pipe
phystatus select register. Originally, we operated the pipe
phystatus register in the phy ops of power_on, because we
expected that the phy ops of power_on called from the dwc3
controller pm runtime resume process which can power on the
PD_USB. However, in this test case, if the id falling edge
interrupt after system resume, the phy ops of power_on can
be called when PD_USB is off.
The call stack:
rockchip_usb2phy_id_irq()
-> send Host notification ->
rockchip_otg_event()
-> receive notification and schedule otg_sm_work ->
rockchip_usb2phy_otg_sm_work()
-> detect EXTCON_USB_HOST is set and call phy power_on ops
rockchip_usb2phy_power_on()
-> set the pipe phystatus select register
Change-Id: Ib7e5bc095ab1df2ca4c983d58a9f15720f0cccb9
Signed-off-by: William Wu <william.wu@rock-chips.com>
When switching modes, the synchronization reset time
of the four lanes cannot be too long, ldo cannot be
turned off either.
Signed-off-by: Algea Cao <algea.cao@rock-chips.com>
Change-Id: I3b8308bf03e9f5796f93189a009d22100c642894
This patch set HS disconnect detect mode to single ended detect mode
for RV1106, fix RV1106 can not recognize device plug out sometimes.
Signed-off-by: Jianwei Zheng <jianwei.zheng@rock-chips.com>
Change-Id: I6ee6ded4cc12032cf2825eadd207c1e5003957cd
1.Assert phy-reset via PIPEPHY GRF instead of asserting via CRU that
would be useless when PD_PHP is off.
2.RK3562 change to use phy grf reset
Change-Id: Id30e8bf28c0bb8d30bab27ad069201978ec74785
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
24M clock noise is carried into the PHY ROPLL loop filter.
Due to the low noise frequency, it can pass through the low-pass loop
filter of ROPLL, resulting in hdmi flash. Reduce ROPLL loop bandwidth
can solve this problem.
Signed-off-by: Algea Cao <algea.cao@rock-chips.com>
Change-Id: Ibea774bc26ea8c2b06cf79c84b6cd6456df66ea5
add support to tcpm framework and remove extcon.
Change-Id: I6ea7aa21b65a50eca2d85f8959d8d317184204e2
Signed-off-by: Zhang Yubing <yubing.zhang@rock-chips.com>
The U2PHY sent "peripheral connected" extcon message to DWC3 even if
there is no USB cable pluuged when the otg_sm_work is scheduled first
time, this would be resumed DWC3 unexpectedly and cause the DWC3 gadget
to incorrect state. So initialize the perip_connected to false before
send the extcon message to fix it.
This can fix the ADB can not be enumerated when plug the USB cable
in the first time after the system boot up and the below messages
may find in the Kernel log on RK3562-EVB2 board.
[ 7.218101] read descriptors
[ 7.218191] read strings
[ 7.306784] dwc3 fe500000.usb: failed to enable ep0out
Fixes: 00168bb5b5 ("phy: rockchip: inno-usb2: fix otg port with vbus always on")
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
Change-Id: I90209f15605d16ca746dd6c44fbaf6d9c1684eaa
RK3652 has one USB2.0 PHY with two ports, the OTG port support OTG
and BC1.2, the SoC provide USB GRF and APB to access the registers.
This adds vbus detection function control and make the below tuning
to enhance the usb2-phy SQ for RK3562 SoC.
- enable pre-emphasis during non-chirp phase
- set HS eye height to 425mv
- turn off differential receiver by default to save power
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
Signed-off-by: William Wu <william.wu@rock-chips.com>
Change-Id: If93c3a072be4c532aa823cf3cd9f05fe9414f727
The otg wakelock should be destroyed when the device probe failed
or removed, else may cause the following kernel errors.
list_add corruption. next->prev should be prev (ffffffc01209d3c8), but
was 0000000000000000. (next=ffffff800350faf8).
------------[ cut here ]------------
kernel BUG at lib/list_debug.c:25!
Internal error: Oops - BUG: 0 [#1] PREEMPT SMP
Modules linked in:
CPU: 1 PID: 1 Comm: swapper/0 Not tainted 5.10.110 #83
Hardware name: Rockchip RK3562 EVB1 LP4X V10 Board (DT)
pstate: 60400085 (nZCv daIf +PAN -UAO -TCO BTYPE=--)
pc : __list_add_valid+0x6c/0x88
lr : __list_add_valid+0x6c/0x88
[...]
Call trace:
__list_add_valid+0x7c/0x98
wakeup_source_register+0x120/0x160
wakeup_source_register+0x120/0x160
device_init_wakeup+0x60/0xf4
[...]
So add devm action to fix it.
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
Change-Id: If54a299a694414ad759002e4f6c4187448ccdb15
1. The layout of controller registers has changed, remove legacy config;
2. Using the default value for grf register;
3. sync to use rk3568 parameter for phy PLL, signal test pass
4. Add 24MHz refclk for rk3528 PCIe, Enable the counting clock of the
rterm detect by setting tx_trim[14] bit for rx detecting.
5. set SSC modulation frequency to 31.5KHz
Change-Id: I45742c416d452037e61b7a7b8765269931d56402
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
Signed-off-by: Jianwei Zheng <jianwei.zheng@rock-chips.com>
This patch set the linestate filter time to support wakeup for
rk3528. Different from other platforms, Both the otg port and
host port have linestate_filter_con register, so we need to set
them separately.
Signed-off-by: Jianwei Zheng <jianwei.zheng@rock-chips.com>
Change-Id: I4a78dccbdb73c48436876b72e106a2eb608ea99d
This patch add usb2 phy support for rk3528 and modified the
rk3568_vbus_detect_control as a universal interface due to
more and more platforms may use this interface in the future.
Usb2 phy also has one different design for rk3528. It doesn't
has commonon control bit, we found that there is a phy inner
debug register which can control the pll out. So we can use
this register to support phy pll control for rk3528.
Add usb2 phy tuning for rk3528:
1. Turn off differential receiver in suspend mode for
the otg and host port to save power consumption.
2. Choose the Tx fs/ls data as linestate from TX driver
for otg port which uses dwc3 controller to improve
fs/ls devices compatibility with long cable.
3. Enable both the otg and host ports phy irq to pmu
wakeup source.
4. Set HS eye-height to 400mV for rk3528
Signed-off-by: Jianwei Zheng <jianwei.zheng@rock-chips.com>
Change-Id: Ia4a861bccd6a37db4e1ba42cede66a6b07947b5d
This fw fix some RX issue:
1. connect detect error;
2. transfer error in ssd huge data write(more than 10GB).
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Change-Id: If9b8d7fbe4414ae4d28ff6bbd4415d88b582113d
Rockchip platforms support to force usb3 to usb2 only
via the property "rockchip,dis-u3otg*-port". With this
property, we can disable the usb3 port and select the
clk utmi for the source clk of usb3 controller.
However, during system PM suspend, the related registers
may lost power, so the usb3 port configurations will
lost. This patch initializes the usb3 port in the usb3
phy init, and it doesn't need to configure the usb3 mode
if the property "rockchip,dis-u3otg*-port" is set.
Change-Id: If82cfb9e3e34dc799db32b2b84f843fce2028df5
Signed-off-by: William Wu <william.wu@rock-chips.com>
It should be initialized the USB flip for fixed lane mapping case
if the USB lanes are assigned. The ln0/ln1 is normal (!flip) and ln2/ln3
is reverse (flip).
This also amend "rx cdr lock timeout" log level to notice since it
may not cause the functional defect in most cases.
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
Change-Id: I693f772b87df97581a60f89219ec4dc6cafb79a3
Usb controller require the clk from phy to work normally. In the
current code, if the dr_mode is set to peripheral and limit to
high speed, there are two cases that usb controller will work
abnormally due to phy power off.
1. The USB cable is not plug in when system start up, at this
time, the otg_sm_work will call rockchip_usb2phy_power_off to
suspend phy. However, if the upper layer uses configfs to operate
the controller after phy power off, controller will work abnormally.
2. Plug in the usb cable and start up the system, the controller
works in peripheral mode and PC recongnize it. IF we unplug the
usb cable, the vbus will not detected, otg_sm_work will also call
rockchip_usb2phy_power_off to suspend phy, when the upper layer
use configfs to operate the controller, phy has been suspended,
controller will work abnormally.
To fix these cases, this patch add a new property "rockchip,dis-u2-
susphy" to avoid phy power off.
Signed-off-by: Jianwei Zheng <jianwei.zheng@rock-chips.com>
Change-Id: I6c9921c8060747667d7bedb2cf76a38a896c05f5
[ Upstream commit ca1c73628f5bd0c1ef6e46073cc3be2450605b06 ]
If "index > usbphyc->nphys" is true then this returns success but it
should return -EINVAL.
Fixes: 94c358da3a ("phy: stm32: add support for STM32 USB PHY Controller (USBPHYC)")
Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com>
Reviewed-by: Amelie Delaunay <amelie.delaunay@foss.st.com>
Link: https://lore.kernel.org/r/Y0kq8j6S+5nDdMpr@kili
Signed-off-by: Vinod Koul <vkoul@kernel.org>
Signed-off-by: Sasha Levin <sashal@kernel.org>
In RK3588C, 24M clock noise is carried into the PHY ROPLL loop filter.
Due to the low noise frequency, it can pass through the low-pass loop
filter of ROPLL, resulting in hdmi clk jitter test fail.
The loop bandwidth of LCPLL is low, so LCPLL can be used to circumvent
this problem. RK3588 is also suitable for this scheme.
Signed-off-by: Algea Cao <algea.cao@rock-chips.com>
Change-Id: I1eafbc3db3daca6b86c97a6682d120f88b71dfa0
[ Upstream commit c3966ced8eb8dc53b6c8d7f97d32cc8a2107d83e ]
Smatch reports the following error:
drivers/phy/qualcomm/phy-qcom-usb-hsic.c:82 qcom_usb_hsic_phy_power_on()
warn: 'uphy->cal_clk' from clk_prepare_enable() not released on lines:
58.
drivers/phy/qualcomm/phy-qcom-usb-hsic.c:82 qcom_usb_hsic_phy_power_on()
warn: 'uphy->cal_sleep_clk' from clk_prepare_enable() not released on
lines: 58.
drivers/phy/qualcomm/phy-qcom-usb-hsic.c:82 qcom_usb_hsic_phy_power_on()
warn: 'uphy->phy_clk' from clk_prepare_enable() not released on lines:
58.
Fix this by calling proper clk_disable_unprepare calls.
Fixes: 0b56e9a7e8 ("phy: Group vendor specific phy drivers")
Signed-off-by: Dongliang Mu <mudongliangabcd@gmail.com>
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Link: https://lore.kernel.org/r/20220914051334.69282-1-dzm91@hust.edu.cn
Signed-off-by: Vinod Koul <vkoul@kernel.org>
Signed-off-by: Sasha Levin <sashal@kernel.org>
The RK3588 USB2 PHY provides CLK12MOHCI and CLK48MOHCI to
OHCI controllers, and the two clocks are turned off upon
PHY reset, therefore it shouldn't access OHCI Controller
if USB2 PHY in reset. However, during the system PM resume,
the current USB2 PHY power on sequence with PHY reset
operation has potential risk that reset PHY accidentally
when OHCI platform resume access OHCI Controller, and
cause system hung.
The reason is EHCI/OHCI controllers resume ordering on
RK3588. In outline form, the hcd_bus_resume() of EHCI
and the ohci_resume() of OHCI operating concurrently on
different CPUs perform the following actions:
CPU 0 CPU 1
---------------------------- ---------------------------------
async_resume()
usb_resume()
hcd_bus_resume() -- EHCI
usb_phy_roothub_resume()
phy_power_on()
rockchip_usb2phy_power_on() ohci_platform_resume()
rockchip_usb2phy_reset() ohci_resume()
assert phy reset ...
udelay(10); ohci_readl or ohci_writel
This patch fixes USB2 PHY reset during power on for RK3588,
only do USB2 PHY reset for RK3588 USB OTG0 and OTG1, because
their 'common_on_n' bit can be set to 1'b1 (aka REFCLK_LOGIC,
Bias, and PLL blocks are powered down) in PM runtime process.
And keep the 'common_on_n' to 1'b0 for RK3588 USB2 HOST0 and
HOST1, thus we don't need to do PHY reset during power on for
them.
This patch doesn't increase the USB2 PHY power consumption,
because the USB2 HOST0 and HOST1 don't support PM runtime
management, so actually the PHY PLL blocks of USB2 HOST0 and
HOST1 are always powered on.
Signed-off-by: William Wu <william.wu@rock-chips.com>
Change-Id: Ia0121a7c49bef4f0f3a1fb11a810e4ef95b29982
Best parameter: 24M T0_1 650mV.
Should co-work with change like below:
&combphy0_ps {
+ rockchip,enable-ssc;
+ assigned-clock-rates = <24000000>;
status = "okay";
};
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Change-Id: I863b8d1758431c0037332e7da1b2c64cd7113573
RK3588 platform may miss line irq if the line state is not in
SE0(D+ low, D- low) before usb controller call phy init function
and enable line irq.
To resolve this, when usb controller call phy init function, we
can clear host_disconnect state if the line state is not in SE0
which means there is an usb device connected to the port.
Signed-off-by: Jianwei Zheng <jianwei.zheng@rock-chips.com>
Change-Id: Icb3f1abd790f16ddd66bbc098e0c06cc5d922d86
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