If it is not controlled, when the path is configured after
resume, the clock will be continuously turn on to increase
the clock count.
Therefore, we can count and control the switch of clock
separately according to the current status of playback and
capture, so as to avoid that mclk is accidentally turned off
when playback and capture exist at the same time, causing
the other stream to fail to work.
For example:
- before:
mclk_sai0 2 2 0 11289600 0 0 50000
mclk_sai0_out2io 1 1 0 11289600 0 0 50000
mclk_sai0_to_io 16 16 0 11289600 0 0 50000
- after:
mclk_sai0 2 2 0 11289600 0 0 50000
mclk_sai0_out2io 1 1 0 11289600 0 0 50000
mclk_sai0_to_io 2 2 0 11289600 0 0 50000
Change-Id: I78ec18c7ffc42f548e82357bcf20701aa057f15d
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
We can configure automatically playback/capture path via
the controlling of 'Resume Path'.
Signed-off-by: Caesar Wang <wxt@rock-chips.com>
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
Change-Id: Ie00e7a673bff068aa922e322d833106f4cbacfde
As mind by sugar, sometimes the master device will exit unexpectly, stop
the sclk before the slave device to do stop trigger, for example the bt
module, which not act as a codec driver, is replaced by a dummy codec.
This patch adds a normal clear for i2s tdm before force switch to
master.
Fixes: c003b7fd8a ("ASoC: rockchip: i2s-tdm: Fix FIFO Clear failed on SLAVE mode sometimes")
Change-Id: Ia3ae2d9b008b07addcfcec38d4e970c376dae1e7
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
TRCM require TX/RX enabled at the same time, or need the one
which provide clk enabled at first for master mode.
It is quite a different for slave mode which does not have
these restrictions, because the BCLK / LRCK are provided by
external master devices.
So, we just set the right clk path value on TRCM register on
stage probe and then drop the trcm value to make TX / RX work
independently.
Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>
Change-Id: I104f168d75787d79625ca7765a1bda1e77cdde12
ALSA core blocks userspace for 10 seconds for PCM R/W default.
Consider the situation BT-slave which acts as SLAVE mode, when
BT-master offline sometime, the CLK lost, user have to wait the
core timeout(10s), it's quite bad experience.
This patch allows userspace to override the WAIT_TIME to recover
more quickly from terminal audio stream. especially for stream
which have no mechanism to detect the LINK offline.
Usage:
/# amixer -c 0 contents | grep Wait
numid=43,iface=PCM,name='PCM Read Wait Time MS'
numid=44,iface=PCM,name='PCM Write Wait Time MS'
/# amixer -c 0 cset numid=43 500
numid=43,iface=PCM,name='PCM Read Wait Time MS'
; type=INTEGER,access=rw------,values=1,min=0,max=10000,step=1
: values=500
Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>
Change-Id: I73e98d54388a50672c5ed710db448cd13c0e1098
After FS idle, should wait at least 2 BCLK cycle to make sure
the CLK gate operation done, and then disable mclk.
Otherwise, the BCLK is still ungated. once the mclk is enabled,
there maybe a risk that a few BCLK cycle leak. especially for
low speed situation, such as 8k samplerate.
The best way is to use delay per samplerate, but, the max time
is quite a tiny value, so, let's make it simple to use the max
time. the max BCLK cycle time is: 31us @ 8K-8Bit (64K BCLK)
udelay(40);
Should wait for one BCLK ready after DIV and then ungate clk to
achieve the clean clk. the max BCLK cycle time is:
15.6us @ 8K-8Bit (64K BCLK)
udelay(20);
Increase the max timeout to 1ms to fix FS idle failed. because
it's not enough for 8k samplerate.
rockchip-sai ff810000.sai: Failed to idle FS
Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>
Change-Id: Ia9da291dd8586236bb32cc0376a6de389f2f0a40
This patch add property 'rockchip,no-dmaengine' to
support register DAI without PCM, and it's usually
used for Multi-DAIs which combine DAIs into a union one.
Change-Id: I4e0da8fae2c692601e05118442218de0f7b4efee
Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>
This patch add support for keeping BCLK / FSYNC always on.
it's required by some devices, such as HDMI, PA, etc.
For example: on HDMI situation
There are some TVs require maintaining N/CTS packets or AUDS
packets to keep audio logic active, otherwise, the first tone
may be lost.
In order to optimize the user experience, we need to ensure
continuous transmission of N/CTS and AUDS packets from the
HDMI-TX, so that the SINK TV devices can maintain audio logic
activation, promptly process audio data, and achieve the
completeness of the first tone.
We init a 48k I2S-STANDARD clock timing as default.
Change-Id: I298b0ad2d53bdc41927f567c2af481f2a0bd5422
Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>
This patch add support for Clk-Auto Switch.
Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>
Change-Id: I2d3b10fcf4cc55ba005d1c9da1049190882f7494
* Support 8-bits width
* Support Mono channel
* Support up to 384k samplerate
Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>
Change-Id: I9f1c10bad2bfb9a3beee1dd91508158e79da2492
CA info should be ignored in the ELD Bypass Situation.
Fixes: c6c61f8679 ("ASoC: hdmi-codec: Add option for ELD bypass")
Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>
Change-Id: I02265570ebcf4d17558b604644dcf5e9425f06cb
This patch allow users to enable "ELD Bypass" who don't
care anything from EDID Link Data.
Currently, this driver gets ELD(from EDID) to constraint
channels and rates.
Unfortunately, EDID is not always valid, maybe caused by
the fragile HDMI port or cable, in this situation, the max
features are limited to 48kHz stereo.
So, add this option to allow user to select the manual way
to output audio as expected. such as multi-channels LPCM(7.1),
or HBR bitstream for these sink devices.
Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>
Change-Id: Ic5ad66002d6f97b4585aaeb01620a53e08b7ed84
We haven't used the rk3036 codec driver on upstream for
a long time, it seems like it needs some changes to work
well with our EVB.
- Clean up the process of DAC working/closing
- Since there is no mixer on the path, remove the mixer
widgets to make simple the driver path
- Only keep one control node "Headphone Switch" to simplify
user operation
- Add the control gpio of power amplifier
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
Change-Id: Ia4b41b0148fe9680f58abe4113d1276f260ef1b5
This patch do reparent CLK_TX/RX to the same parent on TRCM mode
in driver instead of assign parent from DT.
Now, the assigned-parent from DT can be removed.
-assigned-clocks = <&cru SCLK_I2S0_8CH_RX>;
-assigned-clock-parents = <&cru SCLK_I2S0_8CH_TX_MUX>;
Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>
Change-Id: I0abda09a1348d05306e4026f61f7daa2850ae323
Workaround for HDMIIN and HDMIOUT plug-{in,out} when streaming.
Actually, we should do stop stream both for HDMI_{OUT,IN} on
plug-{out,in} event. but for better experience and depop stream,
we optimize as follows:
a) Do stop stream for HDMIIN on plug-out when streaming.
because HDMIIN work as SLAVE mode, CLK lost after HDMI cable
plugged out which will make stream stuck until ALSA timeout(10s).
so, for better experience, we should stop stream at the moment.
b) Do stop stream for HDMIOUT on plug-in when streaming.
because HDMIOUT work as MASTER mode, there is no clk-issue like
HDMIIN, but, on HDR situation, HDMI will be reconfigured which
make HDMI audio configure lost, especially for NLPCM/HBR bitstream
which require IEC937 packet alignment, so, for this situation,
we stop stream to notify user to re-open and configure sound card
and then go on streaming.
Userspace should notice Error-Code(such as -EBADFD) from snd_pcm_write
to do reopen.
Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>
Change-Id: I85455e56f843afcdc9a5f1d5c9e85733b6732cdf
Delete unused definition and modify the error register definition.
Signed-off-by: Jason Zhu <jason.zhu@rock-chips.com>
Change-Id: I255c17049bc28faf108dbca8ec0337d3ccb11555
The dsm sound may be channel disorder when play sometimes,
we can reset the rk_dsm to reconfigure the IP and make it
work well.
Signed-off-by: Jason Zhu <jason.zhu@rock-chips.com>
Change-Id: Iece70267c478c0ec60f685ab85e39ff365b16f4c
Fixes: 5d33c809c3 ("ASoC: codecs: Add support for rockchip codec digital interface")
Signed-off-by: Jason Zhu <jason.zhu@rock-chips.com>
Change-Id: I867538d4aef82120b9cefa2cf833ccfe43f11596
Workaround for FIFO clear on SLAVE mode:
A Suggest to do reset hclk domain and then do mclk
domain, especially for SLAVE mode without CLK in.
at last, recovery regmap config.
B Suggest to switch to MASTER, and then do FIFO clr,
at last, bring back to SLAVE.
Now we choose plan B here.
Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>
Change-Id: I1884659df7fa9052477652b7b0315da21e3165c2
The previous idea about FIFO clear on SLAVE mode is:
1, Switch to MASTER mode
2, Do FIFO clear
3, Switch to SLAVE mode
But, there is a risk that drivers don't set mclk on SLAVE mode,
the mclk from PLL maybe a very high freq (higher than controllers'
signoff freq) that make controller work unexpected.
This patch allow set mclk freq for MASTER / SLAVE mode to fix it.
and, of course, there is no side effect.
This patch also simplify the clear routine by merging clear step 1/2
into a single one.
Fixes: 0a0a0b7606 ("ASoC: rockchip: i2s-tdm: Fix FIFO clear error on SLAVE mode")
Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>
Change-Id: I8488b039e1e21a632bfd2a1c48c86b343fded17a
There is no need to start DAIs which have no channel mapping.
Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>
Change-Id: Ia6be32d474845b9ecb443c38b6801e9836e8a77a
Fix channel disorder caused by "ASoC: rockchip: pdm: Fix pop noise
in the beginning".
The PDM device need to delete some unused data since the pdm of
various manufacturers can not be stable quickly. This is done by
commit "ASoC: rockchip: pdm: Fix pop noise in the beginning".
But we do not know how many data we delete, this cause channel
disorder. For example, we record two channel 24-bit sound, then
delete some starting data. Because the deleted starting data is
uncertain, the next data may be left or right channel and cause
channel disorder.
Luckily, we can use the PDM_RX_CLR to fix this. Use the PDM_RX_CLR
to clear fifo written data and address, but can not clear the read
data and address. In initial state, the read data and address are
zero.
Signed-off-by: Jason Zhu <jason.zhu@rock-chips.com>
Change-Id: I248744c7982365adeb23aa516cf5bed346f4beaf
It's helpful for user to observe the DAI path by kmsg.
Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>
Change-Id: I4e4e0c784a70d19b2b3c05d7fa424022e79a94ba
It's helpful for user to observe the DAI path by kmsg.
Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>
Change-Id: Iebf69a9ecbca5fe6a98ca1512ea549c67f18cdff
It's helpful for user to observe the DAI path by kmsg.
Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>
Change-Id: I60baaf787551362994c2bcb58a1c2d7c21bd23d4
Set jack for the first successful one to fix the disorder
codec assignment.
And of course, we suggest user to place the one which use
the jack in the first place in Device Tree.
Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>
Change-Id: I8dc5d95ba73c053a599d95c0448042fd04765c05
Should use dai->component instead of the fixed rtd->codec[0],
because codec may be addressed in multi-codecs situation,
Obviously, it's wrong. the dais' one is always RIGHT.
Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>
Change-Id: I97cd09aa0886e2b89f2c2f257defb228168e93b0
Should use dai->component instead of the fixed rtd->codec[0],
because codec may be addressed in multi-codecs situation,
Obviously, it's wrong. the dais' one is always RIGHT.
Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>
Change-Id: I4d95b82e36a929e46f4992cbb198b6a060c5c939
leeboby