OrangePi_CM5/drivers/clk/renesas
Ralph Siemsen 6471c83894 clk: renesas: r9a06g032: Fix UART clkgrp bitsel
[ Upstream commit 2dee50ab9e72a3cae75b65e5934c8dd3e9bf01bc ]

There are two UART clock groups, each having a mux to select its
upstream clock source. The register/bit definitions for accessing these
two muxes appear to have been reversed since introduction. Correct them
so as to match the hardware manual.

Fixes: 4c3d88526e ("clk: renesas: Renesas R9A06G032 clock driver")

Signed-off-by: Ralph Siemsen <ralph.siemsen@linaro.org>
Reviewed-by: Phil Edworthy <phil.edworthy@renesas.com>
Link: https://lore.kernel.org/r/20220518182527.1693156-1-ralph.siemsen@linaro.org
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Sasha Levin <sashal@kernel.org>
2022-08-21 15:15:52 +02:00
..
Kconfig clk: renesas: rcar-gen3: Update description for RZ/G2 2020-09-17 15:32:25 +02:00
Makefile clk: renesas: cpg-mssr: Add support for R-Car V3U 2020-09-17 15:32:25 +02:00
clk-div6.c
clk-div6.h
clk-emev2.c
clk-mstp.c
clk-r8a73a4.c
clk-r8a7740.c
clk-r8a7778.c
clk-r8a7779.c
clk-rz.c
clk-sh73a0.c
r7s9210-cpg-mssr.c clk: renesas: cpg-mssr: Use enum clk_reg_layout instead of a boolean flag 2020-09-17 15:30:08 +02:00
r8a774a1-cpg-mssr.c
r8a774b1-cpg-mssr.c
r8a774c0-cpg-mssr.c
r8a774e1-cpg-mssr.c
r8a779a0-cpg-mssr.c clk: renesas: r8a779a0: Fix parent of CBFUSA clock 2021-03-04 11:37:54 +01:00
r8a7742-cpg-mssr.c
r8a7743-cpg-mssr.c clk: renesas: rcar-gen2: Rename vsp1-(sy|rt) clocks to vsp(s|r) 2020-09-04 09:42:01 +02:00
r8a7745-cpg-mssr.c clk: renesas: rcar-gen2: Rename vsp1-(sy|rt) clocks to vsp(s|r) 2020-09-04 09:42:01 +02:00
r8a7790-cpg-mssr.c clk: renesas: rcar-gen2: Rename vsp1-(sy|rt) clocks to vsp(s|r) 2020-09-04 09:42:01 +02:00
r8a7791-cpg-mssr.c clk: renesas: rcar-gen2: Rename vsp1-(sy|rt) clocks to vsp(s|r) 2020-09-04 09:42:01 +02:00
r8a7792-cpg-mssr.c clk: renesas: rcar-gen2: Rename vsp1-(sy|rt) clocks to vsp(s|r) 2020-09-04 09:42:01 +02:00
r8a7794-cpg-mssr.c clk: renesas: rcar-gen2: Rename vsp1-(sy|rt) clocks to vsp(s|r) 2020-09-04 09:42:01 +02:00
r8a7795-cpg-mssr.c
r8a7796-cpg-mssr.c
r8a77470-cpg-mssr.c clk: renesas: rcar-gen2: Rename vsp1-(sy|rt) clocks to vsp(s|r) 2020-09-04 09:42:01 +02:00
r8a77965-cpg-mssr.c
r8a77970-cpg-mssr.c
r8a77980-cpg-mssr.c
r8a77990-cpg-mssr.c
r8a77995-cpg-mssr.c clk: renesas: r8a77995: Add ZA2 clock 2021-07-19 09:44:42 +02:00
r9a06g032-clocks.c clk: renesas: r9a06g032: Fix UART clkgrp bitsel 2022-08-21 15:15:52 +02:00
rcar-gen2-cpg.c
rcar-gen2-cpg.h
rcar-gen3-cpg.c
rcar-gen3-cpg.h
rcar-usb2-clock-sel.c clk: renesas: rcar-usb2-clock-sel: Fix kernel NULL pointer dereference 2021-09-03 10:09:26 +02:00
renesas-cpg-mssr.c clk: renesas: cpg-mssr: Add support for R-Car V3U 2020-09-17 15:32:25 +02:00
renesas-cpg-mssr.h clk: renesas: cpg-mssr: Add support for R-Car V3U 2020-09-17 15:32:25 +02:00