120 lines
3.2 KiB
C
Executable File
120 lines
3.2 KiB
C
Executable File
/*
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* include/linux/motorcomm_phy.h
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*
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* Motorcomm PHY IDs
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*
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*/
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#ifndef _MOTORCOMM_PHY_H
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#define _MOTORCOMM_PHY_H
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#define MOTORCOMM_PHY_ID_MASK 0x00000fff
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#define MOTORCOMM_PHY_ID_8531_MASK 0xffffffff
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#define MOTORCOMM_MPHY_ID_MASK 0x0000ffff
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#define PHY_ID_YT8010 0x00000309
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#define PHY_ID_YT8510 0x00000109
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#define PHY_ID_YT8511 0x0000010a
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#define PHY_ID_YT8512 0x00000118
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#define PHY_ID_YT8512B 0x00000128
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#define PHY_ID_YT8521 0x0000011a
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#define PHY_ID_YT8531S 0x4f51e91a
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#define PHY_ID_YT8531 0x4f51e91b
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//#define PHY_ID_YT8614 0x0000e899
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#define PHY_ID_YT8618 0x0000e889
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#define REG_PHY_SPEC_STATUS 0x11
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#define REG_DEBUG_ADDR_OFFSET 0x1e
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#define REG_DEBUG_DATA 0x1f
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#define YT8512_EXTREG_AFE_PLL 0x50
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#define YT8512_EXTREG_EXTEND_COMBO 0x4000
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#define YT8512_EXTREG_LED0 0x40c0
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#define YT8512_EXTREG_LED1 0x40c3
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#define YT8512_EXTREG_SLEEP_CONTROL1 0x2027
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#define YT_SOFTWARE_RESET 0x8000
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#define YT8512_CONFIG_PLL_REFCLK_SEL_EN 0x0040
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#define YT8512_CONTROL1_RMII_EN 0x0001
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#define YT8512_LED0_ACT_BLK_IND 0x1000
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#define YT8512_LED0_DIS_LED_AN_TRY 0x0001
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#define YT8512_LED0_BT_BLK_EN 0x0002
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#define YT8512_LED0_HT_BLK_EN 0x0004
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#define YT8512_LED0_COL_BLK_EN 0x0008
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#define YT8512_LED0_BT_ON_EN 0x0010
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#define YT8512_LED1_BT_ON_EN 0x0010
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#define YT8512_LED1_TXACT_BLK_EN 0x0100
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#define YT8512_LED1_RXACT_BLK_EN 0x0200
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#define YT8512_SPEED_MODE 0xc000
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#define YT8512_DUPLEX 0x2000
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#define YT8512_SPEED_MODE_BIT 14
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#define YT8512_DUPLEX_BIT 13
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#define YT8512_EN_SLEEP_SW_BIT 15
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#define YT8521_EXTREG_SLEEP_CONTROL1 0x27
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#define YT8521_EN_SLEEP_SW_BIT 15
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#define YT8521_SPEED_MODE 0xc000
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#define YT8521_DUPLEX 0x2000
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#define YT8521_SPEED_MODE_BIT 14
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#define YT8521_DUPLEX_BIT 13
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#define YT8521_LINK_STATUS_BIT 10
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/* based on yt8521 wol config register */
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#define YTPHY_UTP_INTR_REG 0x12
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/* WOL Event Interrupt Enable */
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#define YTPHY_WOL_INTR BIT(6)
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/* Magic Packet MAC address registers */
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#define YTPHY_MAGIC_PACKET_MAC_ADDR2 0xa007
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#define YTPHY_MAGIC_PACKET_MAC_ADDR1 0xa008
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#define YTPHY_MAGIC_PACKET_MAC_ADDR0 0xa009
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#define YTPHY_WOL_CFG_REG 0xa00a
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#define YTPHY_WOL_CFG_TYPE BIT(0) /* WOL TYPE */
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#define YTPHY_WOL_CFG_EN BIT(3) /* WOL Enable */
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#define YTPHY_WOL_CFG_INTR_SEL BIT(6) /* WOL Event Interrupt Enable */
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#define YTPHY_WOL_CFG_WIDTH1 BIT(1) /* WOL Pulse Width */
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#define YTPHY_WOL_CFG_WIDTH2 BIT(2)
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#define YTPHY_REG_SPACE_UTP 0
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#define YTPHY_REG_SPACE_FIBER 2
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enum ytphy_wol_type_e
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{
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YTPHY_WOL_TYPE_LEVEL,
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YTPHY_WOL_TYPE_PULSE,
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YTPHY_WOL_TYPE_MAX
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};
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typedef enum ytphy_wol_type_e ytphy_wol_type_t;
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enum ytphy_wol_width_e
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{
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YTPHY_WOL_WIDTH_84MS,
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YTPHY_WOL_WIDTH_168MS,
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YTPHY_WOL_WIDTH_336MS,
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YTPHY_WOL_WIDTH_672MS,
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YTPHY_WOL_WIDTH_MAX
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};
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typedef enum ytphy_wol_width_e ytphy_wol_width_t;
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struct ytphy_wol_cfg_s
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{
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int enable;
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int type;
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int width;
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};
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typedef struct ytphy_wol_cfg_s ytphy_wol_cfg_t;
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#endif /* _MOTORCOMM_PHY_H */
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