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[ Upstream commit 268a491aebc25e6dc7c618903b09ac3a2e8af530 ] The DWC2 USB controller on the Agilex platform does not support clock gating, so use the chip specific "intel,socfpga-agilex-hsotg" compatible. Signed-off-by: Dinh Nguyen <dinguyen@kernel.org> Signed-off-by: Sasha Levin <sashal@kernel.org> |
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| .. | ||
| Makefile | ||
| keembay-evm.dts | ||
| keembay-soc.dtsi | ||
| socfpga_agilex.dtsi | ||
| socfpga_agilex_socdk.dts | ||
| socfpga_agilex_socdk_nand.dts | ||