ef3a87e0c4
commit 1a307cc299430dd7139d351a3b8941f493dfa885 upstream.
Though GIC ARE option is disabled for no GIC-v2 compatibility,
Cortex-A72 is free to implement the CPU interface as long as it
communicates with the GIC using the stream protocol. This requires
that the SoC integration mark out the PERIPHBASE[1] as reserved area
within the SoC. See longer discussion in [2] for further information.
Update the GIC register map to indicate offsets from PERIPHBASE based
on [3]. Without doing this, systems like kvm will not function with
gic-v2 emulation.
[1] https://developer.arm.com/documentation/100095/0002/system-control/aarch64-register-descriptions/configuration-base-address-register--el1
[2] https://lore.kernel.org/all/87k0e0tirw.wl-maz@kernel.org/
[3] https://developer.arm.com/documentation/100095/0002/way1382452674438
Cc: stable@vger.kernel.org
Fixes:
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|---|---|---|
| .. | ||
| Makefile | ||
| k3-am65-main.dtsi | ||
| k3-am65-mcu.dtsi | ||
| k3-am65-wakeup.dtsi | ||
| k3-am65.dtsi | ||
| k3-am654-base-board.dts | ||
| k3-am654-industrial-thermal.dtsi | ||
| k3-am654.dtsi | ||
| k3-j721e-common-proc-board.dts | ||
| k3-j721e-main.dtsi | ||
| k3-j721e-mcu-wakeup.dtsi | ||
| k3-j721e-som-p0.dtsi | ||
| k3-j721e.dtsi | ||
| k3-j7200-common-proc-board.dts | ||
| k3-j7200-main.dtsi | ||
| k3-j7200-mcu-wakeup.dtsi | ||
| k3-j7200-som-p0.dtsi | ||
| k3-j7200.dtsi | ||