19f6dcb1f0
commit 839769c35477d4acc2369e45000ca7b0b6af39a7 upstream.
Fast coprocessor exception handler saves a3..a6, but coprocessor context
load/store code uses a4..a7 as temporaries, potentially clobbering a7.
'Potentially' because coprocessor state load/store macros may not use
all four temporary registers (and neither FPU nor HiFi macros do).
Use a3..a6 as intended.
Cc: stable@vger.kernel.org
Fixes:
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||
|---|---|---|
| .. | ||
| syscalls | ||
| .gitignore | ||
| Makefile | ||
| align.S | ||
| asm-offsets.c | ||
| coprocessor.S | ||
| entry.S | ||
| head.S | ||
| hw_breakpoint.c | ||
| irq.c | ||
| jump_label.c | ||
| mcount.S | ||
| module.c | ||
| mxhead.S | ||
| pci-dma.c | ||
| pci.c | ||
| perf_event.c | ||
| platform.c | ||
| process.c | ||
| ptrace.c | ||
| s32c1i_selftest.c | ||
| setup.c | ||
| signal.c | ||
| smp.c | ||
| stacktrace.c | ||
| syscall.c | ||
| time.c | ||
| traps.c | ||
| vectors.S | ||
| vmlinux.lds.S | ||
| xtensa_ksyms.c | ||