OrangePi_CM5/drivers/clk/at91
Codrin Ciubotariu 639744b242 clk: at91: sama7g5: fix parents of PDMCs' GCLK
[ Upstream commit 1a944729d8635fa59638f24e8727d5ccaa0c8c19 ]

Audio PLL can be used as parent by the GCLKs of PDMCs.

Fixes: cb783bbbcf ("clk: at91: sama7g5: add clock support for sama7g5")
Signed-off-by: Codrin Ciubotariu <codrin.ciubotariu@microchip.com>
Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com>
Link: https://lore.kernel.org/r/20220304182616.1920392-1-codrin.ciubotariu@microchip.com
Signed-off-by: Sasha Levin <sashal@kernel.org>
2022-04-08 14:40:25 +02:00
..
Makefile
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at91rm9200.c
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at91sam9g45.c
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at91sam9n12.c
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at91sam9rl.c
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at91sam9x5.c
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at91sam9260.c
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clk-audio-pll.c
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clk-generated.c
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clk-h32mx.c
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clk-i2s-mux.c
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clk-main.c
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clk-master.c
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clk-peripheral.c
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clk-pll.c
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clk-plldiv.c
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clk-programmable.c
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clk-sam9x60-pll.c clk: at91: sam9x60-pll: use DIV_ROUND_CLOSEST_ULL 2021-11-18 14:04:21 +01:00
clk-slow.c
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clk-smd.c
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clk-system.c
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clk-usb.c
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clk-utmi.c
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dt-compat.c
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pmc.c
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pmc.h
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sam9x60.c
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sama5d2.c
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sama5d3.c
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sama5d4.c
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sama7g5.c clk: at91: sama7g5: fix parents of PDMCs' GCLK 2022-04-08 14:40:25 +02:00
sckc.c
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