OrangePi_CM5/external/patch/kernel/rockchip-rk3588-current/0001-opi5ultra-cam1-imx586....

80 lines
2.1 KiB
Diff

diff --git a/arch/arm64/boot/dts/rockchip/overlay/rk3588-opi5ultra-cam1.dts b/arch/arm64/boot/dts/rockchip/overlay/rk3588-opi5ultra-cam1.dts
index 866eeb3a8..1dc5e2af3 100644
--- a/arch/arm64/boot/dts/rockchip/overlay/rk3588-opi5ultra-cam1.dts
+++ b/arch/arm64/boot/dts/rockchip/overlay/rk3588-opi5ultra-cam1.dts
@@ -57,18 +57,22 @@ __overlay__ {
status = "okay";
vm149c-p1@c {
- status = "okay";
+ status = "disabled";
};
ov13850-1@10 {
- status = "okay";
+ status = "disabled";
};
dw9714-p1@c {
- status = "okay";
+ status = "disabled";
};
ov13855-1@36 {
+ status = "disabled";
+ };
+
+ imx586@1a {
status = "okay";
};
};
diff --git a/arch/arm64/boot/dts/rockchip/rk3588-orangepi-5-max-camera1.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-orangepi-5-max-camera1.dtsi
index 61cafdf53..e02b19059 100755
--- a/arch/arm64/boot/dts/rockchip/rk3588-orangepi-5-max-camera1.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3588-orangepi-5-max-camera1.dtsi
@@ -25,6 +25,12 @@ mipidphy1_in_ucam1: endpoint@1 {
remote-endpoint = <&ov13855_out1>;
data-lanes = <1 2>;
};
+
+ mipidphy1_in_ucam2: endpoint@2 {
+ reg = <2>;
+ remote-endpoint = <&imx586_out1>;
+ data-lanes = <1 2 3 4>;
+ };
};
port@1 {
reg = <1>;
@@ -107,6 +113,31 @@ ov13855_out1: endpoint {
};
};
};
+
+ imx586_1: imx586@1a {
+ compatible = "sony,imx586";
+ status = "disabled";
+ reg = <0x1a>;
+ clocks = <&cru CLK_MIPI_CAMARAOUT_M2>;
+ clock-names = "xvclk";
+ pinctrl-names = "default";
+ pinctrl-0 = <&mipim1_camera2_clk>;
+ reset-gpios = <&gpio3 RK_PB1 GPIO_ACTIVE_HIGH>;
+ pwdn-gpios = <&gpio3 RK_PB3 GPIO_ACTIVE_HIGH>;
+ avdd-supply = <&vcc_3v3_s0>;
+ dovdd-supply = <&vcc_1v8_s0>;
+ dvdd-supply = <&avdd_1v2_s0>;
+ rockchip,camera-module-index = <1>;
+ rockchip,camera-module-facing = "back";
+ rockchip,camera-module-name = "CIS-IMX586";
+ rockchip,camera-module-lens-name = "default";
+ port {
+ imx586_out1: endpoint {
+ remote-endpoint = <&mipidphy1_in_ucam2>;
+ data-lanes = <1 2 3 4>;
+ };
+ };
+ };
};
&mipi4_csi2 {