699 lines
29 KiB
C
699 lines
29 KiB
C
/* SPDX-License-Identifier: GPL-2.0
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* aw87xxx_pid_c1_reg.h
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*
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* Copyright (c) 2021 AWINIC Technology CO., LTD
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*
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* Author: Barry <zhaozhongbo@awinic.com>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*/
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#ifndef __AW87XXX_PID_C1_REG_H__
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#define __AW87XXX_PID_C1_REG_H__
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/* registers list */
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#define AW87XXX_PID_C1_ID_REG (0x00)
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#define AW87XXX_PID_C1_SYSCTRL_REG (0x01)
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#define AW87XXX_PID_C1_CP_REG (0x02)
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#define AW87XXX_PID_C1_PAG_REG (0x03)
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#define AW87XXX_PID_C1_AGCPO_REG (0x04)
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#define AW87XXX_PID_C1_AGC2PA_REG (0x05)
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#define AW87XXX_PID_C1_SYSST_REG (0x06)
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#define AW87XXX_PID_C1_SYSINT_REG (0x07)
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#define AW87XXX_PID_C1_DFT_SYSCTRL0_REG (0x5D)
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#define AW87XXX_PID_C1_DFT_SYSCTRL1_REG (0x5E)
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#define AW87XXX_PID_C1_DFT_CP_REG (0x5F)
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#define AW87XXX_PID_C1_DFT_TRIM0_REG (0x60)
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#define AW87XXX_PID_C1_DFT_TRIM1_REG (0x61)
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#define AW87XXX_PID_C1_DFT_OC_REG (0x62)
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#define AW87XXX_PID_C1_DFT_THGEN0_REG (0x63)
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#define AW87XXX_PID_C1_DFT_THGEN1_REG (0x64)
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#define AW87XXX_PID_C1_DFT_AGC_REG (0x65)
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#define AW87XXX_PID_C1_DFT_LPMODE_REG (0x66)
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#define AW87XXX_PID_C1_DFT_RAMPGEN_REG (0x67)
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#define AW87XXX_PID_C1_DFT_BIAS_REG (0x68)
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#define AW87XXX_PID_C1_OPTION_STATUS0_REG (0x69)
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#define AW87XXX_PID_C1_OPTION_STATUS1_REG (0x6A)
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#define AW87XXX_PID_C1_OPTION_STATUS2_REG (0x6B)
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#define AW87XXX_PID_C1_OPTION_STATUS3_REG (0x6C)
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#define AW87XXX_PID_C1_TESTCTRL0_REG (0x6E)
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#define AW87XXX_PID_C1_TESTCTRL1_REG (0x6F)
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#define AW87XXX_PID_C1_EFWH_REG (0x70)
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#define AW87XXX_PID_C1_EFWL_REG (0x71)
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#define AW87XXX_PID_C1_EFCTRL1_REG (0x72)
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#define AW87XXX_PID_C1_EFCTRL2_REG (0x73)
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#define AW87XXX_PID_C1_EFCTRL3_REG (0x74)
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#define AW87XXX_PID_C1_EFCTRL4_REG (0x75)
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#define AW87XXX_PID_C1_EFRH2_REG (0x76)
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#define AW87XXX_PID_C1_EFRH1_REG (0x77)
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#define AW87XXX_PID_C1_EFRL2_REG (0x78)
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#define AW87XXX_PID_C1_EFRL1_REG (0x79)
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#define AW87XXX_PID_C1_TM_REG (0x7A)
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#define AW87XXX_PID_C1_TESTIN_REG (0x7B)
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#define AW87XXX_PID_C1_TESTIN1_REG (0x7C)
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#define AW87XXX_PID_C1_TESTIN2_REG (0x7D)
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#define AW87XXX_PID_C1_TESTOUT1_REG (0x7E)
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#define AW87XXX_PID_C1_TESTOUT2_REG (0x7F)
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#define AW87XXX_PID_C1_DFT_THGEN1_CHECK (0x0a)
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/********************************************
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* soft control info
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* If you need to update this file, add this information manually
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*******************************************/
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unsigned char aw87xxx_pid_c1_softrst_access[2] = {0x00, 0xaa};
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/********************************************
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* Register Access
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*******************************************/
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#define AW87XXX_PID_C1_REG_MAX (0x80)
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#define REG_NONE_ACCESS (0)
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#define REG_RD_ACCESS (1 << 0)
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#define REG_WR_ACCESS (1 << 1)
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const unsigned char aw87xxx_pid_c1_reg_access[AW87XXX_PID_C1_REG_MAX] = {
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[AW87XXX_PID_C1_ID_REG] = (REG_RD_ACCESS),
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[AW87XXX_PID_C1_SYSCTRL_REG] = (REG_RD_ACCESS | REG_WR_ACCESS),
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[AW87XXX_PID_C1_CP_REG] = (REG_RD_ACCESS | REG_WR_ACCESS),
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[AW87XXX_PID_C1_PAG_REG] = (REG_RD_ACCESS | REG_WR_ACCESS),
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[AW87XXX_PID_C1_AGCPO_REG] = (REG_RD_ACCESS | REG_WR_ACCESS),
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[AW87XXX_PID_C1_AGC2PA_REG] = (REG_RD_ACCESS | REG_WR_ACCESS),
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[AW87XXX_PID_C1_SYSST_REG] = (REG_RD_ACCESS),
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[AW87XXX_PID_C1_SYSINT_REG] = (REG_RD_ACCESS),
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[AW87XXX_PID_C1_DFT_SYSCTRL0_REG] = (REG_RD_ACCESS | REG_WR_ACCESS),
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[AW87XXX_PID_C1_DFT_SYSCTRL1_REG] = (REG_RD_ACCESS | REG_WR_ACCESS),
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[AW87XXX_PID_C1_DFT_CP_REG] = (REG_RD_ACCESS | REG_WR_ACCESS),
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[AW87XXX_PID_C1_DFT_TRIM0_REG] = (REG_RD_ACCESS | REG_WR_ACCESS),
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[AW87XXX_PID_C1_DFT_TRIM1_REG] = (REG_RD_ACCESS | REG_WR_ACCESS),
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[AW87XXX_PID_C1_DFT_OC_REG] = (REG_RD_ACCESS | REG_WR_ACCESS),
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[AW87XXX_PID_C1_DFT_THGEN0_REG] = (REG_RD_ACCESS | REG_WR_ACCESS),
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[AW87XXX_PID_C1_DFT_THGEN1_REG] = (REG_RD_ACCESS | REG_WR_ACCESS),
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[AW87XXX_PID_C1_DFT_AGC_REG] = (REG_RD_ACCESS | REG_WR_ACCESS),
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[AW87XXX_PID_C1_DFT_LPMODE_REG] = (REG_RD_ACCESS | REG_WR_ACCESS),
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[AW87XXX_PID_C1_DFT_RAMPGEN_REG] = (REG_RD_ACCESS | REG_WR_ACCESS),
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[AW87XXX_PID_C1_DFT_BIAS_REG] = (REG_RD_ACCESS | REG_WR_ACCESS),
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[AW87XXX_PID_C1_OPTION_STATUS0_REG] = (REG_RD_ACCESS),
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[AW87XXX_PID_C1_OPTION_STATUS1_REG] = (REG_RD_ACCESS),
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[AW87XXX_PID_C1_OPTION_STATUS2_REG] = (REG_RD_ACCESS),
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[AW87XXX_PID_C1_OPTION_STATUS3_REG] = (REG_RD_ACCESS),
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[AW87XXX_PID_C1_TESTCTRL0_REG] = (REG_RD_ACCESS | REG_WR_ACCESS),
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[AW87XXX_PID_C1_TESTCTRL1_REG] = (REG_RD_ACCESS | REG_WR_ACCESS),
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[AW87XXX_PID_C1_EFWH_REG] = (REG_RD_ACCESS | REG_WR_ACCESS),
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[AW87XXX_PID_C1_EFWL_REG] = (REG_RD_ACCESS | REG_WR_ACCESS),
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[AW87XXX_PID_C1_EFCTRL1_REG] = (REG_RD_ACCESS | REG_WR_ACCESS),
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[AW87XXX_PID_C1_EFCTRL2_REG] = (REG_RD_ACCESS | REG_WR_ACCESS),
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[AW87XXX_PID_C1_EFCTRL3_REG] = (REG_RD_ACCESS | REG_WR_ACCESS),
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[AW87XXX_PID_C1_EFCTRL4_REG] = (REG_RD_ACCESS | REG_WR_ACCESS),
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[AW87XXX_PID_C1_EFRH2_REG] = (REG_RD_ACCESS),
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[AW87XXX_PID_C1_EFRH1_REG] = (REG_RD_ACCESS),
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[AW87XXX_PID_C1_EFRL2_REG] = (REG_RD_ACCESS),
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[AW87XXX_PID_C1_EFRL1_REG] = (REG_RD_ACCESS),
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[AW87XXX_PID_C1_TM_REG] = (REG_NONE_ACCESS),
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[AW87XXX_PID_C1_TESTIN_REG] = (REG_RD_ACCESS | REG_WR_ACCESS),
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[AW87XXX_PID_C1_TESTIN1_REG] = (REG_RD_ACCESS | REG_WR_ACCESS),
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[AW87XXX_PID_C1_TESTIN2_REG] = (REG_RD_ACCESS | REG_WR_ACCESS),
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[AW87XXX_PID_C1_TESTOUT1_REG] = (REG_RD_ACCESS),
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[AW87XXX_PID_C1_TESTOUT2_REG] = (REG_RD_ACCESS),
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};
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/* detail information of registers begin */
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/* ID (0x00) detail */
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/* IDCODE bit 7:0 (ID 0x00) */
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#define AW87XXX_PID_C1_IDCODE_START_BIT (0)
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#define AW87XXX_PID_C1_IDCODE_BITS_LEN (8)
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#define AW87XXX_PID_C1_IDCODE_MASK \
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(~(((1<<AW87XXX_PID_C1_IDCODE_BITS_LEN)-1) << AW87XXX_PID_C1_IDCODE_START_BIT))
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#define AW87XXX_PID_C1_IDCODE_DEFAULT (0xC1)
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#define AW87XXX_PID_C1_IDCODE_DEFAULT_VALUE \
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(AW87XXX_PID_C1_IDCODE_DEFAULT << AW87XXX_PID_C1_IDCODE_START_BIT)
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/* default value of ID (0x00) */
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/* #define AW87XXX_PID_C1_ID_DEFAULT (0xC1) */
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/* SYSCTRL (0x01) detail */
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/* REG_VER_SEL bit 7:6 (SYSCTRL 0x01) */
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#define AW87XXX_PID_C1_REG_VER_SEL_START_BIT (6)
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#define AW87XXX_PID_C1_REG_VER_SEL_BITS_LEN (2)
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#define AW87XXX_PID_C1_REG_VER_SEL_MASK \
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(~(((1<<AW87XXX_PID_C1_REG_VER_SEL_BITS_LEN)-1) << AW87XXX_PID_C1_REG_VER_SEL_START_BIT))
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#define AW87XXX_PID_C1_REG_VER_SEL_LOW_NOISE_VERSION (0)
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#define AW87XXX_PID_C1_REG_VER_SEL_LOW_NOISE_VERSION_VALUE \
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(AW87XXX_PID_C1_REG_VER_SEL_LOW_NOISE_VERSION << AW87XXX_PID_C1_REG_VER_SEL_START_BIT)
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#define AW87XXX_PID_C1_REG_VER_SEL_NORMAL_VERSIONBOM_COMPACT (1)
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#define AW87XXX_PID_C1_REG_VER_SEL_NORMAL_VERSIONBOM_COMPACT_VALUE \
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(AW87XXX_PID_C1_REG_VER_SEL_NORMAL_VERSIONBOM_COMPACT << AW87XXX_PID_C1_REG_VER_SEL_START_BIT)
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#define AW87XXX_PID_C1_REG_VER_SEL_SUPER_RCV_MODE_NOTE_ONLY_ENSPK0_VALID (2)
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#define AW87XXX_PID_C1_REG_VER_SEL_SUPER_RCV_MODE_NOTE_ONLY_ENSPK0_VALID_VALUE \
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(AW87XXX_PID_C1_REG_VER_SEL_SUPER_RCV_MODE_NOTE_ONLY_ENSPK0_VALID << AW87XXX_PID_C1_REG_VER_SEL_START_BIT)
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#define AW87XXX_PID_C1_REG_VER_SEL_TURN_TO_01 (3)
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#define AW87XXX_PID_C1_REG_VER_SEL_TURN_TO_01_VALUE \
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(AW87XXX_PID_C1_REG_VER_SEL_TURN_TO_01 << AW87XXX_PID_C1_REG_VER_SEL_START_BIT)
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#define AW87XXX_PID_C1_REG_VER_SEL_DEFAULT (0x0)
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#define AW87XXX_PID_C1_REG_VER_SEL_DEFAULT_VALUE \
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(AW87XXX_PID_C1_REG_VER_SEL_DEFAULT << AW87XXX_PID_C1_REG_VER_SEL_START_BIT)
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/* REG_EN_ADAP bit 5 (SYSCTRL 0x01) */
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#define AW87XXX_PID_C1_REG_EN_ADAP_START_BIT (5)
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#define AW87XXX_PID_C1_REG_EN_ADAP_BITS_LEN (1)
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#define AW87XXX_PID_C1_REG_EN_ADAP_MASK \
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(~(((1<<AW87XXX_PID_C1_REG_EN_ADAP_BITS_LEN)-1) << AW87XXX_PID_C1_REG_EN_ADAP_START_BIT))
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#define AW87XXX_PID_C1_REG_EN_ADAP_ADP_DISABLE (0)
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#define AW87XXX_PID_C1_REG_EN_ADAP_ADP_DISABLE_VALUE \
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(AW87XXX_PID_C1_REG_EN_ADAP_ADP_DISABLE << AW87XXX_PID_C1_REG_EN_ADAP_START_BIT)
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#define AW87XXX_PID_C1_REG_EN_ADAP_ADP_ENABLE (1)
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#define AW87XXX_PID_C1_REG_EN_ADAP_ADP_ENABLE_VALUE \
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(AW87XXX_PID_C1_REG_EN_ADAP_ADP_ENABLE << AW87XXX_PID_C1_REG_EN_ADAP_START_BIT)
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#define AW87XXX_PID_C1_REG_EN_ADAP_DEFAULT (0x1)
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#define AW87XXX_PID_C1_REG_EN_ADAP_DEFAULT_VALUE \
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(AW87XXX_PID_C1_REG_EN_ADAP_DEFAULT << AW87XXX_PID_C1_REG_EN_ADAP_START_BIT)
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/* REG_EN_2X bit 4 (SYSCTRL 0x01) */
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#define AW87XXX_PID_C1_REG_EN_2X_START_BIT (4)
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#define AW87XXX_PID_C1_REG_EN_2X_BITS_LEN (1)
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#define AW87XXX_PID_C1_REG_EN_2X_MASK \
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(~(((1<<AW87XXX_PID_C1_REG_EN_2X_BITS_LEN)-1) << AW87XXX_PID_C1_REG_EN_2X_START_BIT))
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#define AW87XXX_PID_C1_REG_EN_2X_2X_CHARGE_PUMP_MODE_DISABLE_1X_DIRECT_THROUGH_MODE_ENABLE (0)
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#define AW87XXX_PID_C1_REG_EN_2X_2X_CHARGE_PUMP_MODE_DISABLE_1X_DIRECT_THROUGH_MODE_ENABLE_VALUE \
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(AW87XXX_PID_C1_REG_EN_2X_2X_CHARGE_PUMP_MODE_DISABLE_1X_DIRECT_THROUGH_MODE_ENABLE << AW87XXX_PID_C1_REG_EN_2X_START_BIT)
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#define AW87XXX_PID_C1_REG_EN_2X_2X_CHARGE_PUMP_MODE_ENABLE_1X_DIRECT_THROUGH_MODE_DISABLE (1)
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#define AW87XXX_PID_C1_REG_EN_2X_2X_CHARGE_PUMP_MODE_ENABLE_1X_DIRECT_THROUGH_MODE_DISABLE_VALUE \
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(AW87XXX_PID_C1_REG_EN_2X_2X_CHARGE_PUMP_MODE_ENABLE_1X_DIRECT_THROUGH_MODE_DISABLE << AW87XXX_PID_C1_REG_EN_2X_START_BIT)
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#define AW87XXX_PID_C1_REG_EN_2X_DEFAULT (0x1)
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#define AW87XXX_PID_C1_REG_EN_2X_DEFAULT_VALUE \
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(AW87XXX_PID_C1_REG_EN_2X_DEFAULT << AW87XXX_PID_C1_REG_EN_2X_START_BIT)
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/* EN_SPK bit 3 (SYSCTRL 0x01) */
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#define AW87XXX_PID_C1_EN_SPK_START_BIT (3)
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#define AW87XXX_PID_C1_EN_SPK_BITS_LEN (1)
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#define AW87XXX_PID_C1_EN_SPK_MASK \
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(~(((1<<AW87XXX_PID_C1_EN_SPK_BITS_LEN)-1) << AW87XXX_PID_C1_EN_SPK_START_BIT))
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#define AW87XXX_PID_C1_EN_SPK_SPK_MODE_DISABLE (0)
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#define AW87XXX_PID_C1_EN_SPK_SPK_MODE_DISABLE_VALUE \
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(AW87XXX_PID_C1_EN_SPK_SPK_MODE_DISABLE << AW87XXX_PID_C1_EN_SPK_START_BIT)
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#define AW87XXX_PID_C1_EN_SPK_SPK_MODE_ENABLE (1)
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#define AW87XXX_PID_C1_EN_SPK_SPK_MODE_ENABLE_VALUE \
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(AW87XXX_PID_C1_EN_SPK_SPK_MODE_ENABLE << AW87XXX_PID_C1_EN_SPK_START_BIT)
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#define AW87XXX_PID_C1_EN_SPK_DEFAULT (0x1)
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#define AW87XXX_PID_C1_EN_SPK_DEFAULT_VALUE \
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(AW87XXX_PID_C1_EN_SPK_DEFAULT << AW87XXX_PID_C1_EN_SPK_START_BIT)
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/* EN_PA bit 2 (SYSCTRL 0x01) */
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#define AW87XXX_PID_C1_EN_PA_START_BIT (2)
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#define AW87XXX_PID_C1_EN_PA_BITS_LEN (1)
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#define AW87XXX_PID_C1_EN_PA_MASK \
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(~(((1<<AW87XXX_PID_C1_EN_PA_BITS_LEN)-1) << AW87XXX_PID_C1_EN_PA_START_BIT))
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#define AW87XXX_PID_C1_EN_PA_POWER_AMPLIFIER_DISABLE (0)
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#define AW87XXX_PID_C1_EN_PA_POWER_AMPLIFIER_DISABLE_VALUE \
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(AW87XXX_PID_C1_EN_PA_POWER_AMPLIFIER_DISABLE << AW87XXX_PID_C1_EN_PA_START_BIT)
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#define AW87XXX_PID_C1_EN_PA_POWER_AMPLIFIER_ENABLE (1)
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#define AW87XXX_PID_C1_EN_PA_POWER_AMPLIFIER_ENABLE_VALUE \
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(AW87XXX_PID_C1_EN_PA_POWER_AMPLIFIER_ENABLE << AW87XXX_PID_C1_EN_PA_START_BIT)
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#define AW87XXX_PID_C1_EN_PA_DEFAULT (0x1)
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#define AW87XXX_PID_C1_EN_PA_DEFAULT_VALUE \
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(AW87XXX_PID_C1_EN_PA_DEFAULT << AW87XXX_PID_C1_EN_PA_START_BIT)
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/* REG_EN_CP bit 1 (SYSCTRL 0x01) */
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#define AW87XXX_PID_C1_REG_EN_CP_START_BIT (1)
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#define AW87XXX_PID_C1_REG_EN_CP_BITS_LEN (1)
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#define AW87XXX_PID_C1_REG_EN_CP_MASK \
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(~(((1<<AW87XXX_PID_C1_REG_EN_CP_BITS_LEN)-1) << AW87XXX_PID_C1_REG_EN_CP_START_BIT))
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#define AW87XXX_PID_C1_REG_EN_CP_CHARGE_PUMP_DISABLE_PVDD0 (0)
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#define AW87XXX_PID_C1_REG_EN_CP_CHARGE_PUMP_DISABLE_PVDD0_VALUE \
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(AW87XXX_PID_C1_REG_EN_CP_CHARGE_PUMP_DISABLE_PVDD0 << AW87XXX_PID_C1_REG_EN_CP_START_BIT)
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#define AW87XXX_PID_C1_REG_EN_CP_CHARGE_PUMP_ENABLE_THE_CP_WORKING_MODE_DEPENDS_ON_EN2X (1)
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#define AW87XXX_PID_C1_REG_EN_CP_CHARGE_PUMP_ENABLE_THE_CP_WORKING_MODE_DEPENDS_ON_EN2X_VALUE \
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(AW87XXX_PID_C1_REG_EN_CP_CHARGE_PUMP_ENABLE_THE_CP_WORKING_MODE_DEPENDS_ON_EN2X << AW87XXX_PID_C1_REG_EN_CP_START_BIT)
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#define AW87XXX_PID_C1_REG_EN_CP_DEFAULT (0x1)
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#define AW87XXX_PID_C1_REG_EN_CP_DEFAULT_VALUE \
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(AW87XXX_PID_C1_REG_EN_CP_DEFAULT << AW87XXX_PID_C1_REG_EN_CP_START_BIT)
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/* EN_SW bit 0 (SYSCTRL 0x01) */
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#define AW87XXX_PID_C1_EN_SW_START_BIT (0)
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#define AW87XXX_PID_C1_EN_SW_BITS_LEN (1)
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#define AW87XXX_PID_C1_EN_SW_MASK \
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(~(((1<<AW87XXX_PID_C1_EN_SW_BITS_LEN)-1) << AW87XXX_PID_C1_EN_SW_START_BIT))
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#define AW87XXX_PID_C1_EN_SW_SOFTWARE_DISABLE (0)
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#define AW87XXX_PID_C1_EN_SW_SOFTWARE_DISABLE_VALUE \
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(AW87XXX_PID_C1_EN_SW_SOFTWARE_DISABLE << AW87XXX_PID_C1_EN_SW_START_BIT)
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#define AW87XXX_PID_C1_EN_SW_SOFTWARE_ENABLE (1)
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#define AW87XXX_PID_C1_EN_SW_SOFTWARE_ENABLE_VALUE \
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(AW87XXX_PID_C1_EN_SW_SOFTWARE_ENABLE << AW87XXX_PID_C1_EN_SW_START_BIT)
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#define AW87XXX_PID_C1_EN_SW_DEFAULT (0x0)
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#define AW87XXX_PID_C1_EN_SW_DEFAULT_VALUE \
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(AW87XXX_PID_C1_EN_SW_DEFAULT << AW87XXX_PID_C1_EN_SW_START_BIT)
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/* default value of SYSCTRL (0x01) */
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/* #define AW87XXX_PID_C1_SYSCTRL_DEFAULT (0x3E) */
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/* CP (0x02) detail */
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/* REG_CP_PEAK_CUR bit 7:6 (CP 0x02) */
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#define AW87XXX_PID_C1_REG_CP_PEAK_CUR_START_BIT (6)
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#define AW87XXX_PID_C1_REG_CP_PEAK_CUR_BITS_LEN (2)
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#define AW87XXX_PID_C1_REG_CP_PEAK_CUR_MASK \
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(~(((1<<AW87XXX_PID_C1_REG_CP_PEAK_CUR_BITS_LEN)-1) << AW87XXX_PID_C1_REG_CP_PEAK_CUR_START_BIT))
|
|
|
|
#define AW87XXX_PID_C1_REG_CP_PEAK_CUR_DEFAULT (0x1)
|
|
#define AW87XXX_PID_C1_REG_CP_PEAK_CUR_DEFAULT_VALUE \
|
|
(AW87XXX_PID_C1_REG_CP_PEAK_CUR_DEFAULT << AW87XXX_PID_C1_REG_CP_PEAK_CUR_START_BIT)
|
|
|
|
/* REG_CP_SOFT_CUR bit 5:4 (CP 0x02) */
|
|
#define AW87XXX_PID_C1_REG_CP_SOFT_CUR_START_BIT (4)
|
|
#define AW87XXX_PID_C1_REG_CP_SOFT_CUR_BITS_LEN (2)
|
|
#define AW87XXX_PID_C1_REG_CP_SOFT_CUR_MASK \
|
|
(~(((1<<AW87XXX_PID_C1_REG_CP_SOFT_CUR_BITS_LEN)-1) << AW87XXX_PID_C1_REG_CP_SOFT_CUR_START_BIT))
|
|
|
|
#define AW87XXX_PID_C1_REG_CP_SOFT_CUR_DEFAULT (0x1)
|
|
#define AW87XXX_PID_C1_REG_CP_SOFT_CUR_DEFAULT_VALUE \
|
|
(AW87XXX_PID_C1_REG_CP_SOFT_CUR_DEFAULT << AW87XXX_PID_C1_REG_CP_SOFT_CUR_START_BIT)
|
|
|
|
/* REG_CP_OVP bit 3:0 (CP 0x02) */
|
|
#define AW87XXX_PID_C1_REG_CP_OVP_START_BIT (0)
|
|
#define AW87XXX_PID_C1_REG_CP_OVP_BITS_LEN (4)
|
|
#define AW87XXX_PID_C1_REG_CP_OVP_MASK \
|
|
(~(((1<<AW87XXX_PID_C1_REG_CP_OVP_BITS_LEN)-1) << AW87XXX_PID_C1_REG_CP_OVP_START_BIT))
|
|
|
|
#define AW87XXX_PID_C1_REG_CP_OVP_DEFAULT (0x8)
|
|
#define AW87XXX_PID_C1_REG_CP_OVP_DEFAULT_VALUE \
|
|
(AW87XXX_PID_C1_REG_CP_OVP_DEFAULT << AW87XXX_PID_C1_REG_CP_OVP_START_BIT)
|
|
|
|
/* default value of CP (0x02) */
|
|
/* #define AW87XXX_PID_C1_CP_DEFAULT (0x58) */
|
|
|
|
/* PAG (0x03) detail */
|
|
/* GAIN bit 2:0 (PAG 0x03) */
|
|
#define AW87XXX_PID_C1_GAIN_START_BIT (0)
|
|
#define AW87XXX_PID_C1_GAIN_BITS_LEN (3)
|
|
#define AW87XXX_PID_C1_GAIN_MASK \
|
|
(~(((1<<AW87XXX_PID_C1_GAIN_BITS_LEN)-1) << AW87XXX_PID_C1_GAIN_START_BIT))
|
|
|
|
#define AW87XXX_PID_C1_GAIN_DEFAULT (0x2)
|
|
#define AW87XXX_PID_C1_GAIN_DEFAULT_VALUE \
|
|
(AW87XXX_PID_C1_GAIN_DEFAULT << AW87XXX_PID_C1_GAIN_START_BIT)
|
|
|
|
/* default value of PAG (0x03) */
|
|
/* #define AW87XXX_PID_C1_PAG_DEFAULT (0x02) */
|
|
|
|
/* AGCPO (0x04) detail */
|
|
/* AK1_S bit 6:5 (AGCPO 0x04) */
|
|
#define AW87XXX_PID_C1_AK1_S_START_BIT (5)
|
|
#define AW87XXX_PID_C1_AK1_S_BITS_LEN (2)
|
|
#define AW87XXX_PID_C1_AK1_S_MASK \
|
|
(~(((1<<AW87XXX_PID_C1_AK1_S_BITS_LEN)-1) << AW87XXX_PID_C1_AK1_S_START_BIT))
|
|
|
|
#define AW87XXX_PID_C1_AK1_S_0P04MSDB (0)
|
|
#define AW87XXX_PID_C1_AK1_S_0P04MSDB_VALUE \
|
|
(AW87XXX_PID_C1_AK1_S_0P04MSDB << AW87XXX_PID_C1_AK1_S_START_BIT)
|
|
|
|
#define AW87XXX_PID_C1_AK1_S_0P08MSDB (1)
|
|
#define AW87XXX_PID_C1_AK1_S_0P08MSDB_VALUE \
|
|
(AW87XXX_PID_C1_AK1_S_0P08MSDB << AW87XXX_PID_C1_AK1_S_START_BIT)
|
|
|
|
#define AW87XXX_PID_C1_AK1_S_0P16MSDB (2)
|
|
#define AW87XXX_PID_C1_AK1_S_0P16MSDB_VALUE \
|
|
(AW87XXX_PID_C1_AK1_S_0P16MSDB << AW87XXX_PID_C1_AK1_S_START_BIT)
|
|
|
|
#define AW87XXX_PID_C1_AK1_S_0P32MSDB (3)
|
|
#define AW87XXX_PID_C1_AK1_S_0P32MSDB_VALUE \
|
|
(AW87XXX_PID_C1_AK1_S_0P32MSDB << AW87XXX_PID_C1_AK1_S_START_BIT)
|
|
|
|
#define AW87XXX_PID_C1_AK1_S_DEFAULT (0x1)
|
|
#define AW87XXX_PID_C1_AK1_S_DEFAULT_VALUE \
|
|
(AW87XXX_PID_C1_AK1_S_DEFAULT << AW87XXX_PID_C1_AK1_S_START_BIT)
|
|
|
|
/* PD_AGC1 bit 4 (AGCPO 0x04) */
|
|
#define AW87XXX_PID_C1_PD_AGC1_START_BIT (4)
|
|
#define AW87XXX_PID_C1_PD_AGC1_BITS_LEN (1)
|
|
#define AW87XXX_PID_C1_PD_AGC1_MASK \
|
|
(~(((1<<AW87XXX_PID_C1_PD_AGC1_BITS_LEN)-1) << AW87XXX_PID_C1_PD_AGC1_START_BIT))
|
|
|
|
#define AW87XXX_PID_C1_PD_AGC1_AGC1_FUNCTION_POWERMINUSUP (0)
|
|
#define AW87XXX_PID_C1_PD_AGC1_AGC1_FUNCTION_POWERMINUSUP_VALUE \
|
|
(AW87XXX_PID_C1_PD_AGC1_AGC1_FUNCTION_POWERMINUSUP << AW87XXX_PID_C1_PD_AGC1_START_BIT)
|
|
|
|
#define AW87XXX_PID_C1_PD_AGC1_AGC1_FUNCTION_POWERMINUSDOWN (1)
|
|
#define AW87XXX_PID_C1_PD_AGC1_AGC1_FUNCTION_POWERMINUSDOWN_VALUE \
|
|
(AW87XXX_PID_C1_PD_AGC1_AGC1_FUNCTION_POWERMINUSDOWN << AW87XXX_PID_C1_PD_AGC1_START_BIT)
|
|
|
|
#define AW87XXX_PID_C1_PD_AGC1_DEFAULT (0x0)
|
|
#define AW87XXX_PID_C1_PD_AGC1_DEFAULT_VALUE \
|
|
(AW87XXX_PID_C1_PD_AGC1_DEFAULT << AW87XXX_PID_C1_PD_AGC1_START_BIT)
|
|
|
|
/* AGC2PO bit 3:0 (AGCPO 0x04) */
|
|
#define AW87XXX_PID_C1_AGC2PO_START_BIT (0)
|
|
#define AW87XXX_PID_C1_AGC2PO_BITS_LEN (4)
|
|
#define AW87XXX_PID_C1_AGC2PO_MASK \
|
|
(~(((1<<AW87XXX_PID_C1_AGC2PO_BITS_LEN)-1) << AW87XXX_PID_C1_AGC2PO_START_BIT))
|
|
|
|
#define AW87XXX_PID_C1_AGC2PO_0P5W8 (0)
|
|
#define AW87XXX_PID_C1_AGC2PO_0P5W8_VALUE \
|
|
(AW87XXX_PID_C1_AGC2PO_0P5W8 << AW87XXX_PID_C1_AGC2PO_START_BIT)
|
|
|
|
#define AW87XXX_PID_C1_AGC2PO_0P6W8 (1)
|
|
#define AW87XXX_PID_C1_AGC2PO_0P6W8_VALUE \
|
|
(AW87XXX_PID_C1_AGC2PO_0P6W8 << AW87XXX_PID_C1_AGC2PO_START_BIT)
|
|
|
|
#define AW87XXX_PID_C1_AGC2PO_0P7W8 (2)
|
|
#define AW87XXX_PID_C1_AGC2PO_0P7W8_VALUE \
|
|
(AW87XXX_PID_C1_AGC2PO_0P7W8 << AW87XXX_PID_C1_AGC2PO_START_BIT)
|
|
|
|
#define AW87XXX_PID_C1_AGC2PO_0P8W8 (3)
|
|
#define AW87XXX_PID_C1_AGC2PO_0P8W8_VALUE \
|
|
(AW87XXX_PID_C1_AGC2PO_0P8W8 << AW87XXX_PID_C1_AGC2PO_START_BIT)
|
|
|
|
#define AW87XXX_PID_C1_AGC2PO_0P9W8 (4)
|
|
#define AW87XXX_PID_C1_AGC2PO_0P9W8_VALUE \
|
|
(AW87XXX_PID_C1_AGC2PO_0P9W8 << AW87XXX_PID_C1_AGC2PO_START_BIT)
|
|
|
|
#define AW87XXX_PID_C1_AGC2PO_1P0W8 (5)
|
|
#define AW87XXX_PID_C1_AGC2PO_1P0W8_VALUE \
|
|
(AW87XXX_PID_C1_AGC2PO_1P0W8 << AW87XXX_PID_C1_AGC2PO_START_BIT)
|
|
|
|
#define AW87XXX_PID_C1_AGC2PO_1P1W8 (6)
|
|
#define AW87XXX_PID_C1_AGC2PO_1P1W8_VALUE \
|
|
(AW87XXX_PID_C1_AGC2PO_1P1W8 << AW87XXX_PID_C1_AGC2PO_START_BIT)
|
|
|
|
#define AW87XXX_PID_C1_AGC2PO_1P2W8 (7)
|
|
#define AW87XXX_PID_C1_AGC2PO_1P2W8_VALUE \
|
|
(AW87XXX_PID_C1_AGC2PO_1P2W8 << AW87XXX_PID_C1_AGC2PO_START_BIT)
|
|
|
|
#define AW87XXX_PID_C1_AGC2PO_1P3W8 (8)
|
|
#define AW87XXX_PID_C1_AGC2PO_1P3W8_VALUE \
|
|
(AW87XXX_PID_C1_AGC2PO_1P3W8 << AW87XXX_PID_C1_AGC2PO_START_BIT)
|
|
|
|
#define AW87XXX_PID_C1_AGC2PO_1P4W8 (9)
|
|
#define AW87XXX_PID_C1_AGC2PO_1P4W8_VALUE \
|
|
(AW87XXX_PID_C1_AGC2PO_1P4W8 << AW87XXX_PID_C1_AGC2PO_START_BIT)
|
|
|
|
#define AW87XXX_PID_C1_AGC2PO_1P5W8 (10)
|
|
#define AW87XXX_PID_C1_AGC2PO_1P5W8_VALUE \
|
|
(AW87XXX_PID_C1_AGC2PO_1P5W8 << AW87XXX_PID_C1_AGC2PO_START_BIT)
|
|
|
|
#define AW87XXX_PID_C1_AGC2PO_1P6W8 (11)
|
|
#define AW87XXX_PID_C1_AGC2PO_1P6W8_VALUE \
|
|
(AW87XXX_PID_C1_AGC2PO_1P6W8 << AW87XXX_PID_C1_AGC2PO_START_BIT)
|
|
|
|
#define AW87XXX_PID_C1_AGC2PO_AGC2_OFF (15)
|
|
#define AW87XXX_PID_C1_AGC2PO_AGC2_OFF_VALUE \
|
|
(AW87XXX_PID_C1_AGC2PO_AGC2_OFF << AW87XXX_PID_C1_AGC2PO_START_BIT)
|
|
|
|
#define AW87XXX_PID_C1_AGC2PO_DEFAULT (0x7)
|
|
#define AW87XXX_PID_C1_AGC2PO_DEFAULT_VALUE \
|
|
(AW87XXX_PID_C1_AGC2PO_DEFAULT << AW87XXX_PID_C1_AGC2PO_START_BIT)
|
|
|
|
/* default value of AGCPO (0x04) */
|
|
/* #define AW87XXX_PID_C1_AGCPO_DEFAULT (0x27) */
|
|
|
|
/* AGC2PA (0x05) detail */
|
|
/* RK_S bit 7:5 (AGC2PA 0x05) */
|
|
#define AW87XXX_PID_C1_RK_S_START_BIT (5)
|
|
#define AW87XXX_PID_C1_RK_S_BITS_LEN (3)
|
|
#define AW87XXX_PID_C1_RK_S_MASK \
|
|
(~(((1<<AW87XXX_PID_C1_RK_S_BITS_LEN)-1) << AW87XXX_PID_C1_RK_S_START_BIT))
|
|
|
|
#define AW87XXX_PID_C1_RK_S_5P12MSDB (0)
|
|
#define AW87XXX_PID_C1_RK_S_5P12MSDB_VALUE \
|
|
(AW87XXX_PID_C1_RK_S_5P12MSDB << AW87XXX_PID_C1_RK_S_START_BIT)
|
|
|
|
#define AW87XXX_PID_C1_RK_S_10P24MSDB (1)
|
|
#define AW87XXX_PID_C1_RK_S_10P24MSDB_VALUE \
|
|
(AW87XXX_PID_C1_RK_S_10P24MSDB << AW87XXX_PID_C1_RK_S_START_BIT)
|
|
|
|
#define AW87XXX_PID_C1_RK_S_20P48MSDB (2)
|
|
#define AW87XXX_PID_C1_RK_S_20P48MSDB_VALUE \
|
|
(AW87XXX_PID_C1_RK_S_20P48MSDB << AW87XXX_PID_C1_RK_S_START_BIT)
|
|
|
|
#define AW87XXX_PID_C1_RK_S_41MSDB (3)
|
|
#define AW87XXX_PID_C1_RK_S_41MSDB_VALUE \
|
|
(AW87XXX_PID_C1_RK_S_41MSDB << AW87XXX_PID_C1_RK_S_START_BIT)
|
|
|
|
#define AW87XXX_PID_C1_RK_S_82MSDB (4)
|
|
#define AW87XXX_PID_C1_RK_S_82MSDB_VALUE \
|
|
(AW87XXX_PID_C1_RK_S_82MSDB << AW87XXX_PID_C1_RK_S_START_BIT)
|
|
|
|
#define AW87XXX_PID_C1_RK_S_164MSDB (5)
|
|
#define AW87XXX_PID_C1_RK_S_164MSDB_VALUE \
|
|
(AW87XXX_PID_C1_RK_S_164MSDB << AW87XXX_PID_C1_RK_S_START_BIT)
|
|
|
|
#define AW87XXX_PID_C1_RK_S_328MSDB (6)
|
|
#define AW87XXX_PID_C1_RK_S_328MSDB_VALUE \
|
|
(AW87XXX_PID_C1_RK_S_328MSDB << AW87XXX_PID_C1_RK_S_START_BIT)
|
|
|
|
#define AW87XXX_PID_C1_RK_S_656MSDB (7)
|
|
#define AW87XXX_PID_C1_RK_S_656MSDB_VALUE \
|
|
(AW87XXX_PID_C1_RK_S_656MSDB << AW87XXX_PID_C1_RK_S_START_BIT)
|
|
|
|
#define AW87XXX_PID_C1_RK_S_DEFAULT (0x2)
|
|
#define AW87XXX_PID_C1_RK_S_DEFAULT_VALUE \
|
|
(AW87XXX_PID_C1_RK_S_DEFAULT << AW87XXX_PID_C1_RK_S_START_BIT)
|
|
|
|
/* AK2_S bit 4:2 (AGC2PA 0x05) */
|
|
#define AW87XXX_PID_C1_AK2_S_START_BIT (2)
|
|
#define AW87XXX_PID_C1_AK2_S_BITS_LEN (3)
|
|
#define AW87XXX_PID_C1_AK2_S_MASK \
|
|
(~(((1<<AW87XXX_PID_C1_AK2_S_BITS_LEN)-1) << AW87XXX_PID_C1_AK2_S_START_BIT))
|
|
|
|
#define AW87XXX_PID_C1_AK2_S_1P28MSDB (0)
|
|
#define AW87XXX_PID_C1_AK2_S_1P28MSDB_VALUE \
|
|
(AW87XXX_PID_C1_AK2_S_1P28MSDB << AW87XXX_PID_C1_AK2_S_START_BIT)
|
|
|
|
#define AW87XXX_PID_C1_AK2_S_2P56MSDB (1)
|
|
#define AW87XXX_PID_C1_AK2_S_2P56MSDB_VALUE \
|
|
(AW87XXX_PID_C1_AK2_S_2P56MSDB << AW87XXX_PID_C1_AK2_S_START_BIT)
|
|
|
|
#define AW87XXX_PID_C1_AK2_S_10P24MSDB (2)
|
|
#define AW87XXX_PID_C1_AK2_S_10P24MSDB_VALUE \
|
|
(AW87XXX_PID_C1_AK2_S_10P24MSDB << AW87XXX_PID_C1_AK2_S_START_BIT)
|
|
|
|
#define AW87XXX_PID_C1_AK2_S_41MSDB (3)
|
|
#define AW87XXX_PID_C1_AK2_S_41MSDB_VALUE \
|
|
(AW87XXX_PID_C1_AK2_S_41MSDB << AW87XXX_PID_C1_AK2_S_START_BIT)
|
|
|
|
#define AW87XXX_PID_C1_AK2_S_82MSDB (4)
|
|
#define AW87XXX_PID_C1_AK2_S_82MSDB_VALUE \
|
|
(AW87XXX_PID_C1_AK2_S_82MSDB << AW87XXX_PID_C1_AK2_S_START_BIT)
|
|
|
|
#define AW87XXX_PID_C1_AK2_S_164MSDB (5)
|
|
#define AW87XXX_PID_C1_AK2_S_164MSDB_VALUE \
|
|
(AW87XXX_PID_C1_AK2_S_164MSDB << AW87XXX_PID_C1_AK2_S_START_BIT)
|
|
|
|
#define AW87XXX_PID_C1_AK2_S_328MSDB (6)
|
|
#define AW87XXX_PID_C1_AK2_S_328MSDB_VALUE \
|
|
(AW87XXX_PID_C1_AK2_S_328MSDB << AW87XXX_PID_C1_AK2_S_START_BIT)
|
|
|
|
#define AW87XXX_PID_C1_AK2_S_656MSDB (7)
|
|
#define AW87XXX_PID_C1_AK2_S_656MSDB_VALUE \
|
|
(AW87XXX_PID_C1_AK2_S_656MSDB << AW87XXX_PID_C1_AK2_S_START_BIT)
|
|
|
|
#define AW87XXX_PID_C1_AK2_S_DEFAULT (0x3)
|
|
#define AW87XXX_PID_C1_AK2_S_DEFAULT_VALUE \
|
|
(AW87XXX_PID_C1_AK2_S_DEFAULT << AW87XXX_PID_C1_AK2_S_START_BIT)
|
|
|
|
/* AK2F_S bit 1:0 (AGC2PA 0x05) */
|
|
#define AW87XXX_PID_C1_AK2F_S_START_BIT (0)
|
|
#define AW87XXX_PID_C1_AK2F_S_BITS_LEN (2)
|
|
#define AW87XXX_PID_C1_AK2F_S_MASK \
|
|
(~(((1<<AW87XXX_PID_C1_AK2F_S_BITS_LEN)-1) << AW87XXX_PID_C1_AK2F_S_START_BIT))
|
|
|
|
#define AW87XXX_PID_C1_AK2F_S_10P24MSDB (0)
|
|
#define AW87XXX_PID_C1_AK2F_S_10P24MSDB_VALUE \
|
|
(AW87XXX_PID_C1_AK2F_S_10P24MSDB << AW87XXX_PID_C1_AK2F_S_START_BIT)
|
|
|
|
#define AW87XXX_PID_C1_AK2F_S_20P48MSDB (1)
|
|
#define AW87XXX_PID_C1_AK2F_S_20P48MSDB_VALUE \
|
|
(AW87XXX_PID_C1_AK2F_S_20P48MSDB << AW87XXX_PID_C1_AK2F_S_START_BIT)
|
|
|
|
#define AW87XXX_PID_C1_AK2F_S_41MSDB (2)
|
|
#define AW87XXX_PID_C1_AK2F_S_41MSDB_VALUE \
|
|
(AW87XXX_PID_C1_AK2F_S_41MSDB << AW87XXX_PID_C1_AK2F_S_START_BIT)
|
|
|
|
#define AW87XXX_PID_C1_AK2F_S_82MSDB (3)
|
|
#define AW87XXX_PID_C1_AK2F_S_82MSDB_VALUE \
|
|
(AW87XXX_PID_C1_AK2F_S_82MSDB << AW87XXX_PID_C1_AK2F_S_START_BIT)
|
|
|
|
#define AW87XXX_PID_C1_AK2F_S_DEFAULT (0x2)
|
|
#define AW87XXX_PID_C1_AK2F_S_DEFAULT_VALUE \
|
|
(AW87XXX_PID_C1_AK2F_S_DEFAULT << AW87XXX_PID_C1_AK2F_S_START_BIT)
|
|
|
|
/* default value of AGC2PA (0x05) */
|
|
/* #define AW87XXX_PID_C1_AGC2PA_DEFAULT (0x4E) */
|
|
|
|
/* SYSST (0x06) detail */
|
|
/* UVLO bit 7 (SYSST 0x06) */
|
|
#define AW87XXX_PID_C1_UVLO_START_BIT (7)
|
|
#define AW87XXX_PID_C1_UVLO_BITS_LEN (1)
|
|
#define AW87XXX_PID_C1_UVLO_MASK \
|
|
(~(((1<<AW87XXX_PID_C1_UVLO_BITS_LEN)-1) << AW87XXX_PID_C1_UVLO_START_BIT))
|
|
|
|
#define AW87XXX_PID_C1_UVLO_DEFAULT (0x0)
|
|
#define AW87XXX_PID_C1_UVLO_DEFAULT_VALUE \
|
|
(AW87XXX_PID_C1_UVLO_DEFAULT << AW87XXX_PID_C1_UVLO_START_BIT)
|
|
|
|
/* OTN bit 6 (SYSST 0x06) */
|
|
#define AW87XXX_PID_C1_OTN_START_BIT (6)
|
|
#define AW87XXX_PID_C1_OTN_BITS_LEN (1)
|
|
#define AW87XXX_PID_C1_OTN_MASK \
|
|
(~(((1<<AW87XXX_PID_C1_OTN_BITS_LEN)-1) << AW87XXX_PID_C1_OTN_START_BIT))
|
|
|
|
#define AW87XXX_PID_C1_OTN_DEFAULT (0x1)
|
|
#define AW87XXX_PID_C1_OTN_DEFAULT_VALUE \
|
|
(AW87XXX_PID_C1_OTN_DEFAULT << AW87XXX_PID_C1_OTN_START_BIT)
|
|
|
|
/* OC_FLAG bit 5 (SYSST 0x06) */
|
|
#define AW87XXX_PID_C1_OC_FLAG_START_BIT (5)
|
|
#define AW87XXX_PID_C1_OC_FLAG_BITS_LEN (1)
|
|
#define AW87XXX_PID_C1_OC_FLAG_MASK \
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(~(((1<<AW87XXX_PID_C1_OC_FLAG_BITS_LEN)-1) << AW87XXX_PID_C1_OC_FLAG_START_BIT))
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#define AW87XXX_PID_C1_OC_FLAG_DEFAULT (0x0)
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#define AW87XXX_PID_C1_OC_FLAG_DEFAULT_VALUE \
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(AW87XXX_PID_C1_OC_FLAG_DEFAULT << AW87XXX_PID_C1_OC_FLAG_START_BIT)
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/* ADAP_CP bit 4 (SYSST 0x06) */
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#define AW87XXX_PID_C1_ADAP_CP_START_BIT (4)
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#define AW87XXX_PID_C1_ADAP_CP_BITS_LEN (1)
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#define AW87XXX_PID_C1_ADAP_CP_MASK \
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(~(((1<<AW87XXX_PID_C1_ADAP_CP_BITS_LEN)-1) << AW87XXX_PID_C1_ADAP_CP_START_BIT))
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#define AW87XXX_PID_C1_ADAP_CP_DEFAULT (0x1)
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#define AW87XXX_PID_C1_ADAP_CP_DEFAULT_VALUE \
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(AW87XXX_PID_C1_ADAP_CP_DEFAULT << AW87XXX_PID_C1_ADAP_CP_START_BIT)
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/* STARTOK bit 3 (SYSST 0x06) */
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#define AW87XXX_PID_C1_STARTOK_START_BIT (3)
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#define AW87XXX_PID_C1_STARTOK_BITS_LEN (1)
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#define AW87XXX_PID_C1_STARTOK_MASK \
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(~(((1<<AW87XXX_PID_C1_STARTOK_BITS_LEN)-1) << AW87XXX_PID_C1_STARTOK_START_BIT))
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#define AW87XXX_PID_C1_STARTOK_DEFAULT (0x0)
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#define AW87XXX_PID_C1_STARTOK_DEFAULT_VALUE \
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(AW87XXX_PID_C1_STARTOK_DEFAULT << AW87XXX_PID_C1_STARTOK_START_BIT)
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/* CP_OVP bit 2 (SYSST 0x06) */
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#define AW87XXX_PID_C1_CP_OVP_START_BIT (2)
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#define AW87XXX_PID_C1_CP_OVP_BITS_LEN (1)
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#define AW87XXX_PID_C1_CP_OVP_MASK \
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(~(((1<<AW87XXX_PID_C1_CP_OVP_BITS_LEN)-1) << AW87XXX_PID_C1_CP_OVP_START_BIT))
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#define AW87XXX_PID_C1_CP_OVP_DEFAULT (0x0)
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#define AW87XXX_PID_C1_CP_OVP_DEFAULT_VALUE \
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(AW87XXX_PID_C1_CP_OVP_DEFAULT << AW87XXX_PID_C1_CP_OVP_START_BIT)
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/* PORN bit 1 (SYSST 0x06) */
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#define AW87XXX_PID_C1_PORN_START_BIT (1)
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#define AW87XXX_PID_C1_PORN_BITS_LEN (1)
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#define AW87XXX_PID_C1_PORN_MASK \
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(~(((1<<AW87XXX_PID_C1_PORN_BITS_LEN)-1) << AW87XXX_PID_C1_PORN_START_BIT))
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#define AW87XXX_PID_C1_PORN_DEFAULT (0x0)
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#define AW87XXX_PID_C1_PORN_DEFAULT_VALUE \
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(AW87XXX_PID_C1_PORN_DEFAULT << AW87XXX_PID_C1_PORN_START_BIT)
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/* default value of SYSST (0x06) */
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/* #define AW87XXX_PID_C1_SYSST_DEFAULT (0x50) */
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/* SYSINT (0x07) detail */
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/* UVLOI bit 7 (SYSINT 0x07) */
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#define AW87XXX_PID_C1_UVLOI_START_BIT (7)
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#define AW87XXX_PID_C1_UVLOI_BITS_LEN (1)
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#define AW87XXX_PID_C1_UVLOI_MASK \
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(~(((1<<AW87XXX_PID_C1_UVLOI_BITS_LEN)-1) << AW87XXX_PID_C1_UVLOI_START_BIT))
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#define AW87XXX_PID_C1_UVLOI_DEFAULT (0x0)
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#define AW87XXX_PID_C1_UVLOI_DEFAULT_VALUE \
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(AW87XXX_PID_C1_UVLOI_DEFAULT << AW87XXX_PID_C1_UVLOI_START_BIT)
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/* OTNI bit 6 (SYSINT 0x07) */
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#define AW87XXX_PID_C1_OTNI_START_BIT (6)
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#define AW87XXX_PID_C1_OTNI_BITS_LEN (1)
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#define AW87XXX_PID_C1_OTNI_MASK \
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(~(((1<<AW87XXX_PID_C1_OTNI_BITS_LEN)-1) << AW87XXX_PID_C1_OTNI_START_BIT))
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#define AW87XXX_PID_C1_OTNI_DEFAULT (0x1)
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#define AW87XXX_PID_C1_OTNI_DEFAULT_VALUE \
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(AW87XXX_PID_C1_OTNI_DEFAULT << AW87XXX_PID_C1_OTNI_START_BIT)
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/* OC_FLAGI bit 5 (SYSINT 0x07) */
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#define AW87XXX_PID_C1_OC_FLAGI_START_BIT (5)
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#define AW87XXX_PID_C1_OC_FLAGI_BITS_LEN (1)
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#define AW87XXX_PID_C1_OC_FLAGI_MASK \
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(~(((1<<AW87XXX_PID_C1_OC_FLAGI_BITS_LEN)-1) << AW87XXX_PID_C1_OC_FLAGI_START_BIT))
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#define AW87XXX_PID_C1_OC_FLAGI_DEFAULT (0x0)
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#define AW87XXX_PID_C1_OC_FLAGI_DEFAULT_VALUE \
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(AW87XXX_PID_C1_OC_FLAGI_DEFAULT << AW87XXX_PID_C1_OC_FLAGI_START_BIT)
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/* ADAP_CPI bit 4 (SYSINT 0x07) */
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#define AW87XXX_PID_C1_ADAP_CPI_START_BIT (4)
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#define AW87XXX_PID_C1_ADAP_CPI_BITS_LEN (1)
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#define AW87XXX_PID_C1_ADAP_CPI_MASK \
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(~(((1<<AW87XXX_PID_C1_ADAP_CPI_BITS_LEN)-1) << AW87XXX_PID_C1_ADAP_CPI_START_BIT))
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#define AW87XXX_PID_C1_ADAP_CPI_DEFAULT (0x1)
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#define AW87XXX_PID_C1_ADAP_CPI_DEFAULT_VALUE \
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(AW87XXX_PID_C1_ADAP_CPI_DEFAULT << AW87XXX_PID_C1_ADAP_CPI_START_BIT)
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/* STARTOKI bit 3 (SYSINT 0x07) */
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#define AW87XXX_PID_C1_STARTOKI_START_BIT (3)
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#define AW87XXX_PID_C1_STARTOKI_BITS_LEN (1)
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#define AW87XXX_PID_C1_STARTOKI_MASK \
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(~(((1<<AW87XXX_PID_C1_STARTOKI_BITS_LEN)-1) << AW87XXX_PID_C1_STARTOKI_START_BIT))
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#define AW87XXX_PID_C1_STARTOKI_DEFAULT (0x0)
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#define AW87XXX_PID_C1_STARTOKI_DEFAULT_VALUE \
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(AW87XXX_PID_C1_STARTOKI_DEFAULT << AW87XXX_PID_C1_STARTOKI_START_BIT)
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/* CP_OVPI bit 2 (SYSINT 0x07) */
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#define AW87XXX_PID_C1_CP_OVPI_START_BIT (2)
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#define AW87XXX_PID_C1_CP_OVPI_BITS_LEN (1)
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#define AW87XXX_PID_C1_CP_OVPI_MASK \
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(~(((1<<AW87XXX_PID_C1_CP_OVPI_BITS_LEN)-1) << AW87XXX_PID_C1_CP_OVPI_START_BIT))
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#define AW87XXX_PID_C1_CP_OVPI_DEFAULT (0x0)
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#define AW87XXX_PID_C1_CP_OVPI_DEFAULT_VALUE \
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(AW87XXX_PID_C1_CP_OVPI_DEFAULT << AW87XXX_PID_C1_CP_OVPI_START_BIT)
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/* PORNI bit 1 (SYSINT 0x07) */
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#define AW87XXX_PID_C1_PORNI_START_BIT (1)
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#define AW87XXX_PID_C1_PORNI_BITS_LEN (1)
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#define AW87XXX_PID_C1_PORNI_MASK \
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(~(((1<<AW87XXX_PID_C1_PORNI_BITS_LEN)-1) << AW87XXX_PID_C1_PORNI_START_BIT))
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#define AW87XXX_PID_C1_PORNI_DEFAULT (0x0)
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#define AW87XXX_PID_C1_PORNI_DEFAULT_VALUE \
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(AW87XXX_PID_C1_PORNI_DEFAULT << AW87XXX_PID_C1_PORNI_START_BIT)
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/* default value of SYSINT (0x07) */
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/* #define AW87XXX_PID_C1_SYSINT_DEFAULT (0x50) */
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/* detail information of registers end */
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#endif /* #ifndef __AW87XXX_PID_C1_REG_H__ */
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