1759 lines
78 KiB
C
1759 lines
78 KiB
C
/* SPDX-License-Identifier: GPL-2.0
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* aw87xxx_pid_5a_reg.h
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*
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* Copyright (c) 2021 AWINIC Technology CO., LTD
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*
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* Author: Barry <zhaozhongbo@awinic.com>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*/
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#ifndef __AW87XXX_PID_C2_REG_H__
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#define __AW87XXX_PID_C2_REG_H__
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/* registers list */
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#define AW87XXX_PID_C2_ID_REG (0x00)
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#define AW87XXX_PID_C2_SYSCTRL_REG (0x01)
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#define AW87XXX_PID_C2_BSTOVR_REG (0x02)
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#define AW87XXX_PID_C2_PEAKLIMIT_REG (0x03)
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#define AW87XXX_PID_C2_ADPSET_REG (0x04)
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#define AW87XXX_PID_C2_PAG_REG (0x05)
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#define AW87XXX_PID_C2_AGC1PA_REG (0x06)
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#define AW87XXX_PID_C2_AGC2PA_REG (0x07)
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#define AW87XXX_PID_C2_AGC3PA_REG (0x08)
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#define AW87XXX_PID_C2_AGC3P_REG (0x09)
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#define AW87XXX_PID_C2_BATT_DECT_REG (0x0A)
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#define AW87XXX_PID_C2_BSTOUT_REG (0x0B)
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#define AW87XXX_PID_C2_SYSST_REG (0x59)
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#define AW87XXX_PID_C2_SYSINT_REG (0x60)
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#define AW87XXX_PID_C2_BURST_CON_REG (0x0C)
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#define AW87XXX_PID_C2_BST_BIAS_REG (0x0D)
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#define AW87XXX_PID_C2_BST_EA_REG (0x0E)
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#define AW87XXX_PID_C2_BST_DE_SOFT_REG (0x0F)
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#define AW87XXX_PID_C2_BST_BURST_KICK_REG (0x10)
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#define AW87XXX_PID_C2_BST_CON1_REG (0x11)
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#define AW87XXX_PID_C2_BST_OVP_REG (0x12)
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#define AW87XXX_PID_C2_LINE_MODE_REG (0x13)
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#define AW87XXX_PID_C2_BST_ISEN_REG (0x14)
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#define AW87XXX_PID_C2_BST_PEAK_REG (0x15)
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#define AW87XXX_PID_C2_OFFTIME_MODE_REG (0x16)
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#define AW87XXX_PID_C2_OFFTIME_REG (0x17)
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#define AW87XXX_PID_C2_ADPBST_IRUSH_REG (0x18)
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#define AW87XXX_PID_C2_RAMPGEN_REG (0x19)
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#define AW87XXX_PID_C2_CLASSD_SYSCTRL_REG (0x1A)
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#define AW87XXX_PID_C2_GTDR_REG (0x1B)
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#define AW87XXX_PID_C2_OC_REG (0x1C)
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#define AW87XXX_PID_C2_AGC_CON_REG (0x1D)
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#define AW87XXX_PID_C2_LP_MODE_REG (0x1E)
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#define AW87XXX_PID_C2_THGEN_UVLO_REG (0x1F)
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#define AW87XXX_PID_C2_VOS_TRIM_REG (0x20)
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#define AW87XXX_PID_C2_CP_REG (0x21)
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#define AW87XXX_PID_C2_BOP_TIME_REG (0x22)
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#define AW87XXX_PID_C2_BOP_TIME2_REG (0x23)
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#define AW87XXX_PID_C2_OPTION_STATUS0_REG (0x24)
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#define AW87XXX_PID_C2_OPTION_STATUS1_REG (0x25)
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#define AW87XXX_PID_C2_OPTION_STATUS2_REG (0x26)
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#define AW87XXX_PID_C2_OPTION_STATUS3_REG (0x27)
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#define AW87XXX_PID_C2_TESTCTRL0_REG (0x28)
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#define AW87XXX_PID_C2_TESTCTRL1_REG (0x29)
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#define AW87XXX_PID_C2_EFWH_REG (0x2A)
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#define AW87XXX_PID_C2_EFWM_REG (0x2B)
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#define AW87XXX_PID_C2_EFWL_REG (0x2C)
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#define AW87XXX_PID_C2_EFCTRL1_REG (0x2D)
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#define AW87XXX_PID_C2_EFCTRL2_REG (0x2E)
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#define AW87XXX_PID_C2_EFCTRL3_REG (0x2F)
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#define AW87XXX_PID_C2_EFCTRL4_REG (0x30)
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#define AW87XXX_PID_C2_EFRHH_REG (0x31)
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#define AW87XXX_PID_C2_EFRHL_REG (0x32)
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#define AW87XXX_PID_C2_EFRMH_REG (0x33)
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#define AW87XXX_PID_C2_EFRML_REG (0x34)
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#define AW87XXX_PID_C2_EFRLH_REG (0x35)
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#define AW87XXX_PID_C2_EFRLL_REG (0x36)
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#define AW87XXX_PID_C2_CRCOUT0_REG (0x37)
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#define AW87XXX_PID_C2_CRCOUT1_REG (0x38)
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#define AW87XXX_PID_C2_TESTOUT2_REG (0x39)
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#define AW87XXX_PID_C2_TESTOUT3_REG (0x3A)
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#define AW87XXX_PID_C2_TESTOUT4_REG (0x3B)
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#define AW87XXX_PID_C2_TESTOUT5_REG (0x3C)
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#define AW87XXX_PID_C2_TESTOUT6_REG (0x3D)
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#define AW87XXX_PID_C2_TESTIN1_REG (0x3E)
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#define AW87XXX_PID_C2_TESTIN2_REG (0x3F)
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#define AW87XXX_PID_C2_RESERVED_REG1_REG (0x50)
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#define AW87XXX_PID_C2_RESERVED_REG2_REG (0x51)
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#define AW87XXX_PID_C2_TM_REG (0x7E)
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#define AW87XXX_PID_C2_TESTIN_REG (0x7F)
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#define AW87XXX_PID_C2_CP_CHECK (0x77)
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/********************************************
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* soft control info
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* If you need to update this file, add this information manually
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*******************************************/
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unsigned char aw87xxx_pid_c2_softrst_access[2] = {0x00, 0xaa};
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/********************************************
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* Register Access
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*******************************************/
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#define AW87XXX_PID_C2_REG_MAX (0x80)
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#define REG_NONE_ACCESS (0)
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#define REG_RD_ACCESS (1 << 0)
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#define REG_WR_ACCESS (1 << 1)
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const unsigned char aw87xxx_pid_c2_reg_access[AW87XXX_PID_C2_REG_MAX] = {
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[AW87XXX_PID_C2_ID_REG] = (REG_RD_ACCESS),
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[AW87XXX_PID_C2_SYSCTRL_REG] = (REG_RD_ACCESS | REG_WR_ACCESS),
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[AW87XXX_PID_C2_BSTOVR_REG] = (REG_RD_ACCESS | REG_WR_ACCESS),
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[AW87XXX_PID_C2_PEAKLIMIT_REG] = (REG_RD_ACCESS | REG_WR_ACCESS),
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[AW87XXX_PID_C2_ADPSET_REG] = (REG_RD_ACCESS | REG_WR_ACCESS),
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[AW87XXX_PID_C2_PAG_REG] = (REG_RD_ACCESS | REG_WR_ACCESS),
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[AW87XXX_PID_C2_AGC1PA_REG] = (REG_RD_ACCESS | REG_WR_ACCESS),
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[AW87XXX_PID_C2_AGC2PA_REG] = (REG_RD_ACCESS | REG_WR_ACCESS),
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[AW87XXX_PID_C2_AGC3PA_REG] = (REG_RD_ACCESS | REG_WR_ACCESS),
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[AW87XXX_PID_C2_AGC3P_REG] = (REG_RD_ACCESS | REG_WR_ACCESS),
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[AW87XXX_PID_C2_BATT_DECT_REG] = (REG_RD_ACCESS | REG_WR_ACCESS),
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[AW87XXX_PID_C2_BSTOUT_REG] = (REG_RD_ACCESS | REG_WR_ACCESS),
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[AW87XXX_PID_C2_SYSST_REG] = (REG_RD_ACCESS),
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[AW87XXX_PID_C2_SYSINT_REG] = (REG_RD_ACCESS),
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[AW87XXX_PID_C2_BURST_CON_REG] = (REG_RD_ACCESS | REG_WR_ACCESS),
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[AW87XXX_PID_C2_BST_BIAS_REG] = (REG_RD_ACCESS | REG_WR_ACCESS),
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[AW87XXX_PID_C2_BST_EA_REG] = (REG_RD_ACCESS | REG_WR_ACCESS),
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[AW87XXX_PID_C2_BST_DE_SOFT_REG] = (REG_RD_ACCESS | REG_WR_ACCESS),
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[AW87XXX_PID_C2_BST_BURST_KICK_REG] = (REG_RD_ACCESS | REG_WR_ACCESS),
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[AW87XXX_PID_C2_BST_CON1_REG] = (REG_RD_ACCESS | REG_WR_ACCESS),
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[AW87XXX_PID_C2_BST_OVP_REG] = (REG_RD_ACCESS | REG_WR_ACCESS),
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[AW87XXX_PID_C2_LINE_MODE_REG] = (REG_RD_ACCESS | REG_WR_ACCESS),
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[AW87XXX_PID_C2_BST_ISEN_REG] = (REG_RD_ACCESS | REG_WR_ACCESS),
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[AW87XXX_PID_C2_BST_PEAK_REG] = (REG_RD_ACCESS | REG_WR_ACCESS),
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[AW87XXX_PID_C2_OFFTIME_MODE_REG] = (REG_RD_ACCESS | REG_WR_ACCESS),
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[AW87XXX_PID_C2_OFFTIME_REG] = (REG_RD_ACCESS | REG_WR_ACCESS),
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[AW87XXX_PID_C2_ADPBST_IRUSH_REG] = (REG_RD_ACCESS | REG_WR_ACCESS),
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[AW87XXX_PID_C2_RAMPGEN_REG] = (REG_RD_ACCESS | REG_WR_ACCESS),
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[AW87XXX_PID_C2_CLASSD_SYSCTRL_REG] = (REG_RD_ACCESS | REG_WR_ACCESS),
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[AW87XXX_PID_C2_GTDR_REG] = (REG_RD_ACCESS | REG_WR_ACCESS),
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[AW87XXX_PID_C2_OC_REG] = (REG_RD_ACCESS | REG_WR_ACCESS),
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[AW87XXX_PID_C2_AGC_CON_REG] = (REG_RD_ACCESS | REG_WR_ACCESS),
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[AW87XXX_PID_C2_LP_MODE_REG] = (REG_RD_ACCESS | REG_WR_ACCESS),
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[AW87XXX_PID_C2_THGEN_UVLO_REG] = (REG_RD_ACCESS | REG_WR_ACCESS),
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[AW87XXX_PID_C2_VOS_TRIM_REG] = (REG_RD_ACCESS | REG_WR_ACCESS),
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[AW87XXX_PID_C2_CP_REG] = (REG_RD_ACCESS | REG_WR_ACCESS),
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[AW87XXX_PID_C2_BOP_TIME_REG] = (REG_RD_ACCESS | REG_WR_ACCESS),
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[AW87XXX_PID_C2_BOP_TIME2_REG] = (REG_RD_ACCESS | REG_WR_ACCESS),
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[AW87XXX_PID_C2_OPTION_STATUS0_REG] = (REG_RD_ACCESS),
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[AW87XXX_PID_C2_OPTION_STATUS1_REG] = (REG_RD_ACCESS),
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[AW87XXX_PID_C2_OPTION_STATUS2_REG] = (REG_RD_ACCESS),
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[AW87XXX_PID_C2_OPTION_STATUS3_REG] = (REG_RD_ACCESS),
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[AW87XXX_PID_C2_TESTCTRL0_REG] = (REG_RD_ACCESS | REG_WR_ACCESS),
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[AW87XXX_PID_C2_TESTCTRL1_REG] = (REG_RD_ACCESS | REG_WR_ACCESS),
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[AW87XXX_PID_C2_EFWH_REG] = (REG_RD_ACCESS | REG_WR_ACCESS),
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[AW87XXX_PID_C2_EFWM_REG] = (REG_RD_ACCESS | REG_WR_ACCESS),
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[AW87XXX_PID_C2_EFWL_REG] = (REG_RD_ACCESS | REG_WR_ACCESS),
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[AW87XXX_PID_C2_EFCTRL1_REG] = (REG_RD_ACCESS | REG_WR_ACCESS),
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[AW87XXX_PID_C2_EFCTRL2_REG] = (REG_RD_ACCESS | REG_WR_ACCESS),
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[AW87XXX_PID_C2_EFCTRL3_REG] = (REG_RD_ACCESS | REG_WR_ACCESS),
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[AW87XXX_PID_C2_EFCTRL4_REG] = (REG_RD_ACCESS | REG_WR_ACCESS),
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[AW87XXX_PID_C2_EFRHH_REG] = (REG_RD_ACCESS),
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[AW87XXX_PID_C2_EFRHL_REG] = (REG_RD_ACCESS),
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[AW87XXX_PID_C2_EFRMH_REG] = (REG_RD_ACCESS),
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[AW87XXX_PID_C2_EFRML_REG] = (REG_RD_ACCESS),
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[AW87XXX_PID_C2_EFRLH_REG] = (REG_RD_ACCESS),
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[AW87XXX_PID_C2_EFRLL_REG] = (REG_RD_ACCESS),
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[AW87XXX_PID_C2_CRCOUT0_REG] = (REG_RD_ACCESS),
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[AW87XXX_PID_C2_CRCOUT1_REG] = (REG_RD_ACCESS),
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[AW87XXX_PID_C2_TESTOUT2_REG] = (REG_RD_ACCESS),
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[AW87XXX_PID_C2_TESTOUT3_REG] = (REG_RD_ACCESS),
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[AW87XXX_PID_C2_TESTOUT4_REG] = (REG_RD_ACCESS),
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[AW87XXX_PID_C2_TESTOUT5_REG] = (REG_RD_ACCESS),
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[AW87XXX_PID_C2_TESTOUT6_REG] = (REG_RD_ACCESS),
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[AW87XXX_PID_C2_TESTIN1_REG] = (REG_RD_ACCESS | REG_WR_ACCESS),
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[AW87XXX_PID_C2_TESTIN2_REG] = (REG_RD_ACCESS | REG_WR_ACCESS),
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[AW87XXX_PID_C2_RESERVED_REG1_REG] = (REG_RD_ACCESS | REG_WR_ACCESS),
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[AW87XXX_PID_C2_RESERVED_REG2_REG] = (REG_RD_ACCESS | REG_WR_ACCESS),
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[AW87XXX_PID_C2_TM_REG] = (REG_NONE_ACCESS),
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[AW87XXX_PID_C2_TESTIN_REG] = (REG_RD_ACCESS | REG_WR_ACCESS),
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};
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/* detail information of registers begin */
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/* ID (0x00) detail */
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/* IDCODE bit 7:0 (ID 0x00) */
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#define AW87XXX_PID_C2_IDCODE_START_BIT (0)
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#define AW87XXX_PID_C2_IDCODE_BITS_LEN (8)
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#define AW87XXX_PID_C2_IDCODE_MASK \
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(~(((1<<AW87XXX_PID_C2_IDCODE_BITS_LEN)-1) << AW87XXX_PID_C2_IDCODE_START_BIT))
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#define AW87XXX_PID_C2_IDCODE_DEFAULT (0xC2)
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#define AW87XXX_PID_C2_IDCODE_DEFAULT_VALUE \
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(AW87XXX_PID_C2_IDCODE_DEFAULT << AW87XXX_PID_C2_IDCODE_START_BIT)
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/* default value of ID (0x00) */
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/* #define AW87XXX_PID_C2_ID_DEFAULT (0xC2) */
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/* SYSCTRL (0x01) detail */
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/* IIC_WEN bit 7:6 (SYSCTRL 0x01) */
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#define AW87XXX_PID_C2_IIC_WEN_START_BIT (6)
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#define AW87XXX_PID_C2_IIC_WEN_BITS_LEN (2)
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#define AW87XXX_PID_C2_IIC_WEN_MASK \
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(~(((1<<AW87XXX_PID_C2_IIC_WEN_BITS_LEN)-1) << AW87XXX_PID_C2_IIC_WEN_START_BIT))
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#define AW87XXX_PID_C2_IIC_WEN_ENABLE_IIC (2)
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#define AW87XXX_PID_C2_IIC_WEN_ENABLE_IIC_VALUE \
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(AW87XXX_PID_C2_IIC_WEN_ENABLE_IIC << AW87XXX_PID_C2_IIC_WEN_START_BIT)
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#define AW87XXX_PID_C2_IIC_WEN_OTHERS_DISABLE (others)
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#define AW87XXX_PID_C2_IIC_WEN_OTHERS_DISABLE_VALUE \
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(AW87XXX_PID_C2_IIC_WEN_OTHERS_DISABLE << AW87XXX_PID_C2_IIC_WEN_START_BIT)
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#define AW87XXX_PID_C2_IIC_WEN_DEFAULT (0x0)
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#define AW87XXX_PID_C2_IIC_WEN_DEFAULT_VALUE \
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(AW87XXX_PID_C2_IIC_WEN_DEFAULT << AW87XXX_PID_C2_IIC_WEN_START_BIT)
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/* EN_SW bit 5 (SYSCTRL 0x01) */
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#define AW87XXX_PID_C2_EN_SW_START_BIT (5)
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#define AW87XXX_PID_C2_EN_SW_BITS_LEN (1)
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#define AW87XXX_PID_C2_EN_SW_MASK \
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(~(((1<<AW87XXX_PID_C2_EN_SW_BITS_LEN)-1) << AW87XXX_PID_C2_EN_SW_START_BIT))
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#define AW87XXX_PID_C2_EN_SW_DISABLE (0)
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#define AW87XXX_PID_C2_EN_SW_DISABLE_VALUE \
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(AW87XXX_PID_C2_EN_SW_DISABLE << AW87XXX_PID_C2_EN_SW_START_BIT)
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#define AW87XXX_PID_C2_EN_SW_ENABLE (1)
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#define AW87XXX_PID_C2_EN_SW_ENABLE_VALUE \
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(AW87XXX_PID_C2_EN_SW_ENABLE << AW87XXX_PID_C2_EN_SW_START_BIT)
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#define AW87XXX_PID_C2_EN_SW_DEFAULT (0x0)
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#define AW87XXX_PID_C2_EN_SW_DEFAULT_VALUE \
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(AW87XXX_PID_C2_EN_SW_DEFAULT << AW87XXX_PID_C2_EN_SW_START_BIT)
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/* EN_CP bit 4 (SYSCTRL 0x01) */
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#define AW87XXX_PID_C2_EN_CP_START_BIT (4)
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#define AW87XXX_PID_C2_EN_CP_BITS_LEN (1)
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#define AW87XXX_PID_C2_EN_CP_MASK \
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(~(((1<<AW87XXX_PID_C2_EN_CP_BITS_LEN)-1) << AW87XXX_PID_C2_EN_CP_START_BIT))
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#define AW87XXX_PID_C2_EN_CP_DISABLE (0)
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#define AW87XXX_PID_C2_EN_CP_DISABLE_VALUE \
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(AW87XXX_PID_C2_EN_CP_DISABLE << AW87XXX_PID_C2_EN_CP_START_BIT)
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#define AW87XXX_PID_C2_EN_CP_ENABLE (1)
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#define AW87XXX_PID_C2_EN_CP_ENABLE_VALUE \
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(AW87XXX_PID_C2_EN_CP_ENABLE << AW87XXX_PID_C2_EN_CP_START_BIT)
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#define AW87XXX_PID_C2_EN_CP_DEFAULT (0x1)
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#define AW87XXX_PID_C2_EN_CP_DEFAULT_VALUE \
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(AW87XXX_PID_C2_EN_CP_DEFAULT << AW87XXX_PID_C2_EN_CP_START_BIT)
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/* EN_BOOST bit 3 (SYSCTRL 0x01) */
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#define AW87XXX_PID_C2_EN_BOOST_START_BIT (3)
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#define AW87XXX_PID_C2_EN_BOOST_BITS_LEN (1)
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#define AW87XXX_PID_C2_EN_BOOST_MASK \
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(~(((1<<AW87XXX_PID_C2_EN_BOOST_BITS_LEN)-1) << AW87XXX_PID_C2_EN_BOOST_START_BIT))
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#define AW87XXX_PID_C2_EN_BOOST_DISABLE (0)
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#define AW87XXX_PID_C2_EN_BOOST_DISABLE_VALUE \
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(AW87XXX_PID_C2_EN_BOOST_DISABLE << AW87XXX_PID_C2_EN_BOOST_START_BIT)
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#define AW87XXX_PID_C2_EN_BOOST_ENABLE (1)
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#define AW87XXX_PID_C2_EN_BOOST_ENABLE_VALUE \
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(AW87XXX_PID_C2_EN_BOOST_ENABLE << AW87XXX_PID_C2_EN_BOOST_START_BIT)
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#define AW87XXX_PID_C2_EN_BOOST_DEFAULT (0x1)
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#define AW87XXX_PID_C2_EN_BOOST_DEFAULT_VALUE \
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(AW87XXX_PID_C2_EN_BOOST_DEFAULT << AW87XXX_PID_C2_EN_BOOST_START_BIT)
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/* EN_PA bit 2 (SYSCTRL 0x01) */
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#define AW87XXX_PID_C2_EN_PA_START_BIT (2)
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#define AW87XXX_PID_C2_EN_PA_BITS_LEN (1)
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#define AW87XXX_PID_C2_EN_PA_MASK \
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(~(((1<<AW87XXX_PID_C2_EN_PA_BITS_LEN)-1) << AW87XXX_PID_C2_EN_PA_START_BIT))
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#define AW87XXX_PID_C2_EN_PA_DISABLE (0)
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#define AW87XXX_PID_C2_EN_PA_DISABLE_VALUE \
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(AW87XXX_PID_C2_EN_PA_DISABLE << AW87XXX_PID_C2_EN_PA_START_BIT)
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#define AW87XXX_PID_C2_EN_PA_ENABLE (1)
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#define AW87XXX_PID_C2_EN_PA_ENABLE_VALUE \
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(AW87XXX_PID_C2_EN_PA_ENABLE << AW87XXX_PID_C2_EN_PA_START_BIT)
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#define AW87XXX_PID_C2_EN_PA_DEFAULT (0x1)
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#define AW87XXX_PID_C2_EN_PA_DEFAULT_VALUE \
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(AW87XXX_PID_C2_EN_PA_DEFAULT << AW87XXX_PID_C2_EN_PA_START_BIT)
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/* RCV_MODE bit 1 (SYSCTRL 0x01) */
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#define AW87XXX_PID_C2_RCV_MODE_START_BIT (1)
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#define AW87XXX_PID_C2_RCV_MODE_BITS_LEN (1)
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#define AW87XXX_PID_C2_RCV_MODE_MASK \
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(~(((1<<AW87XXX_PID_C2_RCV_MODE_BITS_LEN)-1) << AW87XXX_PID_C2_RCV_MODE_START_BIT))
|
|
|
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#define AW87XXX_PID_C2_RCV_MODE_DISABLE (0)
|
|
#define AW87XXX_PID_C2_RCV_MODE_DISABLE_VALUE \
|
|
(AW87XXX_PID_C2_RCV_MODE_DISABLE << AW87XXX_PID_C2_RCV_MODE_START_BIT)
|
|
|
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#define AW87XXX_PID_C2_RCV_MODE_ENABLE (1)
|
|
#define AW87XXX_PID_C2_RCV_MODE_ENABLE_VALUE \
|
|
(AW87XXX_PID_C2_RCV_MODE_ENABLE << AW87XXX_PID_C2_RCV_MODE_START_BIT)
|
|
|
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#define AW87XXX_PID_C2_RCV_MODE_DEFAULT (0x0)
|
|
#define AW87XXX_PID_C2_RCV_MODE_DEFAULT_VALUE \
|
|
(AW87XXX_PID_C2_RCV_MODE_DEFAULT << AW87XXX_PID_C2_RCV_MODE_START_BIT)
|
|
|
|
/* EN_HVBAT bit 0 (SYSCTRL 0x01) */
|
|
#define AW87XXX_PID_C2_EN_HVBAT_START_BIT (0)
|
|
#define AW87XXX_PID_C2_EN_HVBAT_BITS_LEN (1)
|
|
#define AW87XXX_PID_C2_EN_HVBAT_MASK \
|
|
(~(((1<<AW87XXX_PID_C2_EN_HVBAT_BITS_LEN)-1) << AW87XXX_PID_C2_EN_HVBAT_START_BIT))
|
|
|
|
#define AW87XXX_PID_C2_EN_HVBAT_DISABLE (0)
|
|
#define AW87XXX_PID_C2_EN_HVBAT_DISABLE_VALUE \
|
|
(AW87XXX_PID_C2_EN_HVBAT_DISABLE << AW87XXX_PID_C2_EN_HVBAT_START_BIT)
|
|
|
|
#define AW87XXX_PID_C2_EN_HVBAT_ENABLE (1)
|
|
#define AW87XXX_PID_C2_EN_HVBAT_ENABLE_VALUE \
|
|
(AW87XXX_PID_C2_EN_HVBAT_ENABLE << AW87XXX_PID_C2_EN_HVBAT_START_BIT)
|
|
|
|
#define AW87XXX_PID_C2_EN_HVBAT_DEFAULT (0x0)
|
|
#define AW87XXX_PID_C2_EN_HVBAT_DEFAULT_VALUE \
|
|
(AW87XXX_PID_C2_EN_HVBAT_DEFAULT << AW87XXX_PID_C2_EN_HVBAT_START_BIT)
|
|
|
|
/* default value of SYSCTRL (0x01) */
|
|
/* #define AW87XXX_PID_C2_SYSCTRL_DEFAULT (0x1C) */
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|
|
|
/* BSTOVR (0x02) detail */
|
|
/* CP_FREQ_PRE bit 6:5 (BSTOVR 0x02) */
|
|
#define AW87XXX_PID_C2_CP_FREQ_PRE_START_BIT (5)
|
|
#define AW87XXX_PID_C2_CP_FREQ_PRE_BITS_LEN (2)
|
|
#define AW87XXX_PID_C2_CP_FREQ_PRE_MASK \
|
|
(~(((1<<AW87XXX_PID_C2_CP_FREQ_PRE_BITS_LEN)-1) << AW87XXX_PID_C2_CP_FREQ_PRE_START_BIT))
|
|
|
|
#define AW87XXX_PID_C2_CP_FREQ_PRE_9P99MHZ (0)
|
|
#define AW87XXX_PID_C2_CP_FREQ_PRE_9P99MHZ_VALUE \
|
|
(AW87XXX_PID_C2_CP_FREQ_PRE_9P99MHZ << AW87XXX_PID_C2_CP_FREQ_PRE_START_BIT)
|
|
|
|
#define AW87XXX_PID_C2_CP_FREQ_PRE_13P48MHZ (1)
|
|
#define AW87XXX_PID_C2_CP_FREQ_PRE_13P48MHZ_VALUE \
|
|
(AW87XXX_PID_C2_CP_FREQ_PRE_13P48MHZ << AW87XXX_PID_C2_CP_FREQ_PRE_START_BIT)
|
|
|
|
#define AW87XXX_PID_C2_CP_FREQ_PRE_16P76MHZ (2)
|
|
#define AW87XXX_PID_C2_CP_FREQ_PRE_16P76MHZ_VALUE \
|
|
(AW87XXX_PID_C2_CP_FREQ_PRE_16P76MHZ << AW87XXX_PID_C2_CP_FREQ_PRE_START_BIT)
|
|
|
|
#define AW87XXX_PID_C2_CP_FREQ_PRE_3P2MHZ (3)
|
|
#define AW87XXX_PID_C2_CP_FREQ_PRE_3P2MHZ_VALUE \
|
|
(AW87XXX_PID_C2_CP_FREQ_PRE_3P2MHZ << AW87XXX_PID_C2_CP_FREQ_PRE_START_BIT)
|
|
|
|
#define AW87XXX_PID_C2_CP_FREQ_PRE_DEFAULT (0x1)
|
|
#define AW87XXX_PID_C2_CP_FREQ_PRE_DEFAULT_VALUE \
|
|
(AW87XXX_PID_C2_CP_FREQ_PRE_DEFAULT << AW87XXX_PID_C2_CP_FREQ_PRE_START_BIT)
|
|
|
|
/* BST_VOUT bit 4:0 (BSTOVR 0x02) */
|
|
#define AW87XXX_PID_C2_BST_VOUT_START_BIT (0)
|
|
#define AW87XXX_PID_C2_BST_VOUT_BITS_LEN (5)
|
|
#define AW87XXX_PID_C2_BST_VOUT_MASK \
|
|
(~(((1<<AW87XXX_PID_C2_BST_VOUT_BITS_LEN)-1) << AW87XXX_PID_C2_BST_VOUT_START_BIT))
|
|
|
|
#define AW87XXX_PID_C2_BST_VOUT_4P75V (0)
|
|
#define AW87XXX_PID_C2_BST_VOUT_4P75V_VALUE \
|
|
(AW87XXX_PID_C2_BST_VOUT_4P75V << AW87XXX_PID_C2_BST_VOUT_START_BIT)
|
|
|
|
#define AW87XXX_PID_C2_BST_VOUT_5P0V (1)
|
|
#define AW87XXX_PID_C2_BST_VOUT_5P0V_VALUE \
|
|
(AW87XXX_PID_C2_BST_VOUT_5P0V << AW87XXX_PID_C2_BST_VOUT_START_BIT)
|
|
|
|
#define AW87XXX_PID_C2_BST_VOUT_5P25V (2)
|
|
#define AW87XXX_PID_C2_BST_VOUT_5P25V_VALUE \
|
|
(AW87XXX_PID_C2_BST_VOUT_5P25V << AW87XXX_PID_C2_BST_VOUT_START_BIT)
|
|
|
|
#define AW87XXX_PID_C2_BST_VOUT_5P5V (3)
|
|
#define AW87XXX_PID_C2_BST_VOUT_5P5V_VALUE \
|
|
(AW87XXX_PID_C2_BST_VOUT_5P5V << AW87XXX_PID_C2_BST_VOUT_START_BIT)
|
|
|
|
#define AW87XXX_PID_C2_BST_VOUT_5P75V (4)
|
|
#define AW87XXX_PID_C2_BST_VOUT_5P75V_VALUE \
|
|
(AW87XXX_PID_C2_BST_VOUT_5P75V << AW87XXX_PID_C2_BST_VOUT_START_BIT)
|
|
|
|
#define AW87XXX_PID_C2_BST_VOUT_6P0V (5)
|
|
#define AW87XXX_PID_C2_BST_VOUT_6P0V_VALUE \
|
|
(AW87XXX_PID_C2_BST_VOUT_6P0V << AW87XXX_PID_C2_BST_VOUT_START_BIT)
|
|
|
|
#define AW87XXX_PID_C2_BST_VOUT_6P25V (6)
|
|
#define AW87XXX_PID_C2_BST_VOUT_6P25V_VALUE \
|
|
(AW87XXX_PID_C2_BST_VOUT_6P25V << AW87XXX_PID_C2_BST_VOUT_START_BIT)
|
|
|
|
#define AW87XXX_PID_C2_BST_VOUT_6P5V (7)
|
|
#define AW87XXX_PID_C2_BST_VOUT_6P5V_VALUE \
|
|
(AW87XXX_PID_C2_BST_VOUT_6P5V << AW87XXX_PID_C2_BST_VOUT_START_BIT)
|
|
|
|
#define AW87XXX_PID_C2_BST_VOUT_6P75V (8)
|
|
#define AW87XXX_PID_C2_BST_VOUT_6P75V_VALUE \
|
|
(AW87XXX_PID_C2_BST_VOUT_6P75V << AW87XXX_PID_C2_BST_VOUT_START_BIT)
|
|
|
|
#define AW87XXX_PID_C2_BST_VOUT_7P0V (9)
|
|
#define AW87XXX_PID_C2_BST_VOUT_7P0V_VALUE \
|
|
(AW87XXX_PID_C2_BST_VOUT_7P0V << AW87XXX_PID_C2_BST_VOUT_START_BIT)
|
|
|
|
#define AW87XXX_PID_C2_BST_VOUT_7P25V (10)
|
|
#define AW87XXX_PID_C2_BST_VOUT_7P25V_VALUE \
|
|
(AW87XXX_PID_C2_BST_VOUT_7P25V << AW87XXX_PID_C2_BST_VOUT_START_BIT)
|
|
|
|
#define AW87XXX_PID_C2_BST_VOUT_7P5V (11)
|
|
#define AW87XXX_PID_C2_BST_VOUT_7P5V_VALUE \
|
|
(AW87XXX_PID_C2_BST_VOUT_7P5V << AW87XXX_PID_C2_BST_VOUT_START_BIT)
|
|
|
|
#define AW87XXX_PID_C2_BST_VOUT_7P75V (12)
|
|
#define AW87XXX_PID_C2_BST_VOUT_7P75V_VALUE \
|
|
(AW87XXX_PID_C2_BST_VOUT_7P75V << AW87XXX_PID_C2_BST_VOUT_START_BIT)
|
|
|
|
#define AW87XXX_PID_C2_BST_VOUT_8P0V (13)
|
|
#define AW87XXX_PID_C2_BST_VOUT_8P0V_VALUE \
|
|
(AW87XXX_PID_C2_BST_VOUT_8P0V << AW87XXX_PID_C2_BST_VOUT_START_BIT)
|
|
|
|
#define AW87XXX_PID_C2_BST_VOUT_8P25V (14)
|
|
#define AW87XXX_PID_C2_BST_VOUT_8P25V_VALUE \
|
|
(AW87XXX_PID_C2_BST_VOUT_8P25V << AW87XXX_PID_C2_BST_VOUT_START_BIT)
|
|
|
|
#define AW87XXX_PID_C2_BST_VOUT_8P5V (15)
|
|
#define AW87XXX_PID_C2_BST_VOUT_8P5V_VALUE \
|
|
(AW87XXX_PID_C2_BST_VOUT_8P5V << AW87XXX_PID_C2_BST_VOUT_START_BIT)
|
|
|
|
#define AW87XXX_PID_C2_BST_VOUT_8P75V (16)
|
|
#define AW87XXX_PID_C2_BST_VOUT_8P75V_VALUE \
|
|
(AW87XXX_PID_C2_BST_VOUT_8P75V << AW87XXX_PID_C2_BST_VOUT_START_BIT)
|
|
|
|
#define AW87XXX_PID_C2_BST_VOUT_9P0V (17)
|
|
#define AW87XXX_PID_C2_BST_VOUT_9P0V_VALUE \
|
|
(AW87XXX_PID_C2_BST_VOUT_9P0V << AW87XXX_PID_C2_BST_VOUT_START_BIT)
|
|
|
|
#define AW87XXX_PID_C2_BST_VOUT_9P25V (18)
|
|
#define AW87XXX_PID_C2_BST_VOUT_9P25V_VALUE \
|
|
(AW87XXX_PID_C2_BST_VOUT_9P25V << AW87XXX_PID_C2_BST_VOUT_START_BIT)
|
|
|
|
#define AW87XXX_PID_C2_BST_VOUT_9P5V (19)
|
|
#define AW87XXX_PID_C2_BST_VOUT_9P5V_VALUE \
|
|
(AW87XXX_PID_C2_BST_VOUT_9P5V << AW87XXX_PID_C2_BST_VOUT_START_BIT)
|
|
|
|
#define AW87XXX_PID_C2_BST_VOUT_9P75V (20)
|
|
#define AW87XXX_PID_C2_BST_VOUT_9P75V_VALUE \
|
|
(AW87XXX_PID_C2_BST_VOUT_9P75V << AW87XXX_PID_C2_BST_VOUT_START_BIT)
|
|
|
|
#define AW87XXX_PID_C2_BST_VOUT_10P0V (21)
|
|
#define AW87XXX_PID_C2_BST_VOUT_10P0V_VALUE \
|
|
(AW87XXX_PID_C2_BST_VOUT_10P0V << AW87XXX_PID_C2_BST_VOUT_START_BIT)
|
|
|
|
#define AW87XXX_PID_C2_BST_VOUT_10P25V (22)
|
|
#define AW87XXX_PID_C2_BST_VOUT_10P25V_VALUE \
|
|
(AW87XXX_PID_C2_BST_VOUT_10P25V << AW87XXX_PID_C2_BST_VOUT_START_BIT)
|
|
|
|
#define AW87XXX_PID_C2_BST_VOUT_10P5V (23)
|
|
#define AW87XXX_PID_C2_BST_VOUT_10P5V_VALUE \
|
|
(AW87XXX_PID_C2_BST_VOUT_10P5V << AW87XXX_PID_C2_BST_VOUT_START_BIT)
|
|
|
|
#define AW87XXX_PID_C2_BST_VOUT_DEFAULT (0x11)
|
|
#define AW87XXX_PID_C2_BST_VOUT_DEFAULT_VALUE \
|
|
(AW87XXX_PID_C2_BST_VOUT_DEFAULT << AW87XXX_PID_C2_BST_VOUT_START_BIT)
|
|
|
|
/* default value of BSTOVR (0x02) */
|
|
/* #define AW87XXX_PID_C2_BSTOVR_DEFAULT (0x31) */
|
|
|
|
/* PEAKLIMIT (0x03) detail */
|
|
/* EN_LP_FT bit 6 (PEAKLIMIT 0x03) */
|
|
#define AW87XXX_PID_C2_EN_LP_FT_START_BIT (6)
|
|
#define AW87XXX_PID_C2_EN_LP_FT_BITS_LEN (1)
|
|
#define AW87XXX_PID_C2_EN_LP_FT_MASK \
|
|
(~(((1<<AW87XXX_PID_C2_EN_LP_FT_BITS_LEN)-1) << AW87XXX_PID_C2_EN_LP_FT_START_BIT))
|
|
|
|
#define AW87XXX_PID_C2_EN_LP_FT_LP_MODE_FT_DISABLE (0)
|
|
#define AW87XXX_PID_C2_EN_LP_FT_LP_MODE_FT_DISABLE_VALUE \
|
|
(AW87XXX_PID_C2_EN_LP_FT_LP_MODE_FT_DISABLE << AW87XXX_PID_C2_EN_LP_FT_START_BIT)
|
|
|
|
#define AW87XXX_PID_C2_EN_LP_FT_LP_MODE_FT_ENABLEFAST_ENTER_LP_MODE (1)
|
|
#define AW87XXX_PID_C2_EN_LP_FT_LP_MODE_FT_ENABLEFAST_ENTER_LP_MODE_VALUE \
|
|
(AW87XXX_PID_C2_EN_LP_FT_LP_MODE_FT_ENABLEFAST_ENTER_LP_MODE << AW87XXX_PID_C2_EN_LP_FT_START_BIT)
|
|
|
|
#define AW87XXX_PID_C2_EN_LP_FT_DEFAULT (0x0)
|
|
#define AW87XXX_PID_C2_EN_LP_FT_DEFAULT_VALUE \
|
|
(AW87XXX_PID_C2_EN_LP_FT_DEFAULT << AW87XXX_PID_C2_EN_LP_FT_START_BIT)
|
|
|
|
/* BST_OVP2_VTH bit 5:4 (PEAKLIMIT 0x03) */
|
|
#define AW87XXX_PID_C2_BST_OVP2_VTH_START_BIT (4)
|
|
#define AW87XXX_PID_C2_BST_OVP2_VTH_BITS_LEN (2)
|
|
#define AW87XXX_PID_C2_BST_OVP2_VTH_MASK \
|
|
(~(((1<<AW87XXX_PID_C2_BST_OVP2_VTH_BITS_LEN)-1) << AW87XXX_PID_C2_BST_OVP2_VTH_START_BIT))
|
|
|
|
#define AW87XXX_PID_C2_BST_OVP2_VTH_9V (0)
|
|
#define AW87XXX_PID_C2_BST_OVP2_VTH_9V_VALUE \
|
|
(AW87XXX_PID_C2_BST_OVP2_VTH_9V << AW87XXX_PID_C2_BST_OVP2_VTH_START_BIT)
|
|
|
|
#define AW87XXX_PID_C2_BST_OVP2_VTH_10V_DEFAULT_FOR_PVDD9V_VERSION (1)
|
|
#define AW87XXX_PID_C2_BST_OVP2_VTH_10V_DEFAULT_FOR_PVDD9V_VERSION_VALUE \
|
|
(AW87XXX_PID_C2_BST_OVP2_VTH_10V_DEFAULT_FOR_PVDD9V_VERSION << AW87XXX_PID_C2_BST_OVP2_VTH_START_BIT)
|
|
|
|
#define AW87XXX_PID_C2_BST_OVP2_VTH_11V (2)
|
|
#define AW87XXX_PID_C2_BST_OVP2_VTH_11V_VALUE \
|
|
(AW87XXX_PID_C2_BST_OVP2_VTH_11V << AW87XXX_PID_C2_BST_OVP2_VTH_START_BIT)
|
|
|
|
#define AW87XXX_PID_C2_BST_OVP2_VTH_11P5V_DEFAULT_FOR_PVDD9V_VERSION (3)
|
|
#define AW87XXX_PID_C2_BST_OVP2_VTH_11P5V_DEFAULT_FOR_PVDD9V_VERSION_VALUE \
|
|
(AW87XXX_PID_C2_BST_OVP2_VTH_11P5V_DEFAULT_FOR_PVDD9V_VERSION << AW87XXX_PID_C2_BST_OVP2_VTH_START_BIT)
|
|
|
|
#define AW87XXX_PID_C2_BST_OVP2_VTH_DEFAULT (0x1)
|
|
#define AW87XXX_PID_C2_BST_OVP2_VTH_DEFAULT_VALUE \
|
|
(AW87XXX_PID_C2_BST_OVP2_VTH_DEFAULT << AW87XXX_PID_C2_BST_OVP2_VTH_START_BIT)
|
|
|
|
/* BST_IPEAK bit 3:0 (PEAKLIMIT 0x03) */
|
|
#define AW87XXX_PID_C2_BST_IPEAK_START_BIT (0)
|
|
#define AW87XXX_PID_C2_BST_IPEAK_BITS_LEN (4)
|
|
#define AW87XXX_PID_C2_BST_IPEAK_MASK \
|
|
(~(((1<<AW87XXX_PID_C2_BST_IPEAK_BITS_LEN)-1) << AW87XXX_PID_C2_BST_IPEAK_START_BIT))
|
|
|
|
#define AW87XXX_PID_C2_BST_IPEAK_1P5A (0)
|
|
#define AW87XXX_PID_C2_BST_IPEAK_1P5A_VALUE \
|
|
(AW87XXX_PID_C2_BST_IPEAK_1P5A << AW87XXX_PID_C2_BST_IPEAK_START_BIT)
|
|
|
|
#define AW87XXX_PID_C2_BST_IPEAK_1P75A (1)
|
|
#define AW87XXX_PID_C2_BST_IPEAK_1P75A_VALUE \
|
|
(AW87XXX_PID_C2_BST_IPEAK_1P75A << AW87XXX_PID_C2_BST_IPEAK_START_BIT)
|
|
|
|
#define AW87XXX_PID_C2_BST_IPEAK_2P0A (2)
|
|
#define AW87XXX_PID_C2_BST_IPEAK_2P0A_VALUE \
|
|
(AW87XXX_PID_C2_BST_IPEAK_2P0A << AW87XXX_PID_C2_BST_IPEAK_START_BIT)
|
|
|
|
#define AW87XXX_PID_C2_BST_IPEAK_2P25A (3)
|
|
#define AW87XXX_PID_C2_BST_IPEAK_2P25A_VALUE \
|
|
(AW87XXX_PID_C2_BST_IPEAK_2P25A << AW87XXX_PID_C2_BST_IPEAK_START_BIT)
|
|
|
|
#define AW87XXX_PID_C2_BST_IPEAK_2P5A (4)
|
|
#define AW87XXX_PID_C2_BST_IPEAK_2P5A_VALUE \
|
|
(AW87XXX_PID_C2_BST_IPEAK_2P5A << AW87XXX_PID_C2_BST_IPEAK_START_BIT)
|
|
|
|
#define AW87XXX_PID_C2_BST_IPEAK_2P75A (5)
|
|
#define AW87XXX_PID_C2_BST_IPEAK_2P75A_VALUE \
|
|
(AW87XXX_PID_C2_BST_IPEAK_2P75A << AW87XXX_PID_C2_BST_IPEAK_START_BIT)
|
|
|
|
#define AW87XXX_PID_C2_BST_IPEAK_3P0A (6)
|
|
#define AW87XXX_PID_C2_BST_IPEAK_3P0A_VALUE \
|
|
(AW87XXX_PID_C2_BST_IPEAK_3P0A << AW87XXX_PID_C2_BST_IPEAK_START_BIT)
|
|
|
|
#define AW87XXX_PID_C2_BST_IPEAK_3P25A (7)
|
|
#define AW87XXX_PID_C2_BST_IPEAK_3P25A_VALUE \
|
|
(AW87XXX_PID_C2_BST_IPEAK_3P25A << AW87XXX_PID_C2_BST_IPEAK_START_BIT)
|
|
|
|
#define AW87XXX_PID_C2_BST_IPEAK_3P5A (8)
|
|
#define AW87XXX_PID_C2_BST_IPEAK_3P5A_VALUE \
|
|
(AW87XXX_PID_C2_BST_IPEAK_3P5A << AW87XXX_PID_C2_BST_IPEAK_START_BIT)
|
|
|
|
#define AW87XXX_PID_C2_BST_IPEAK_3P75A (9)
|
|
#define AW87XXX_PID_C2_BST_IPEAK_3P75A_VALUE \
|
|
(AW87XXX_PID_C2_BST_IPEAK_3P75A << AW87XXX_PID_C2_BST_IPEAK_START_BIT)
|
|
|
|
#define AW87XXX_PID_C2_BST_IPEAK_4A (10)
|
|
#define AW87XXX_PID_C2_BST_IPEAK_4A_VALUE \
|
|
(AW87XXX_PID_C2_BST_IPEAK_4A << AW87XXX_PID_C2_BST_IPEAK_START_BIT)
|
|
|
|
#define AW87XXX_PID_C2_BST_IPEAK_4P25A (11)
|
|
#define AW87XXX_PID_C2_BST_IPEAK_4P25A_VALUE \
|
|
(AW87XXX_PID_C2_BST_IPEAK_4P25A << AW87XXX_PID_C2_BST_IPEAK_START_BIT)
|
|
|
|
#define AW87XXX_PID_C2_BST_IPEAK_4P50A (12)
|
|
#define AW87XXX_PID_C2_BST_IPEAK_4P50A_VALUE \
|
|
(AW87XXX_PID_C2_BST_IPEAK_4P50A << AW87XXX_PID_C2_BST_IPEAK_START_BIT)
|
|
|
|
#define AW87XXX_PID_C2_BST_IPEAK_DEFAULT (0x9)
|
|
#define AW87XXX_PID_C2_BST_IPEAK_DEFAULT_VALUE \
|
|
(AW87XXX_PID_C2_BST_IPEAK_DEFAULT << AW87XXX_PID_C2_BST_IPEAK_START_BIT)
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|
|
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/* default value of PEAKLIMIT (0x03) */
|
|
/* #define AW87XXX_PID_C2_PEAKLIMIT_DEFAULT (0x19) */
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|
|
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/* ADPSET (0x04) detail */
|
|
/* EN_LP bit 7 (ADPSET 0x04) */
|
|
#define AW87XXX_PID_C2_EN_LP_START_BIT (7)
|
|
#define AW87XXX_PID_C2_EN_LP_BITS_LEN (1)
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|
#define AW87XXX_PID_C2_EN_LP_MASK \
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|
(~(((1<<AW87XXX_PID_C2_EN_LP_BITS_LEN)-1) << AW87XXX_PID_C2_EN_LP_START_BIT))
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|
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#define AW87XXX_PID_C2_EN_LP_LP_MODE_DISABLE (0)
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|
#define AW87XXX_PID_C2_EN_LP_LP_MODE_DISABLE_VALUE \
|
|
(AW87XXX_PID_C2_EN_LP_LP_MODE_DISABLE << AW87XXX_PID_C2_EN_LP_START_BIT)
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|
|
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#define AW87XXX_PID_C2_EN_LP_LP_MODE_ENABLE (1)
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#define AW87XXX_PID_C2_EN_LP_LP_MODE_ENABLE_VALUE \
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|
(AW87XXX_PID_C2_EN_LP_LP_MODE_ENABLE << AW87XXX_PID_C2_EN_LP_START_BIT)
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|
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#define AW87XXX_PID_C2_EN_LP_DEFAULT (0x1)
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#define AW87XXX_PID_C2_EN_LP_DEFAULT_VALUE \
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|
(AW87XXX_PID_C2_EN_LP_DEFAULT << AW87XXX_PID_C2_EN_LP_START_BIT)
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|
|
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/* EN_ADP_BST bit 6 (ADPSET 0x04) */
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|
#define AW87XXX_PID_C2_EN_ADP_BST_START_BIT (6)
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|
#define AW87XXX_PID_C2_EN_ADP_BST_BITS_LEN (1)
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#define AW87XXX_PID_C2_EN_ADP_BST_MASK \
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(~(((1<<AW87XXX_PID_C2_EN_ADP_BST_BITS_LEN)-1) << AW87XXX_PID_C2_EN_ADP_BST_START_BIT))
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#define AW87XXX_PID_C2_EN_ADP_BST_DISABLE (0)
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#define AW87XXX_PID_C2_EN_ADP_BST_DISABLE_VALUE \
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(AW87XXX_PID_C2_EN_ADP_BST_DISABLE << AW87XXX_PID_C2_EN_ADP_BST_START_BIT)
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#define AW87XXX_PID_C2_EN_ADP_BST_ENABLE (1)
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#define AW87XXX_PID_C2_EN_ADP_BST_ENABLE_VALUE \
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|
(AW87XXX_PID_C2_EN_ADP_BST_ENABLE << AW87XXX_PID_C2_EN_ADP_BST_START_BIT)
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#define AW87XXX_PID_C2_EN_ADP_BST_DEFAULT (0x1)
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#define AW87XXX_PID_C2_EN_ADP_BST_DEFAULT_VALUE \
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|
(AW87XXX_PID_C2_EN_ADP_BST_DEFAULT << AW87XXX_PID_C2_EN_ADP_BST_START_BIT)
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/* ADP_BOOST_MODE bit 5:3 (ADPSET 0x04) */
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|
#define AW87XXX_PID_C2_ADP_BOOST_MODE_START_BIT (3)
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|
#define AW87XXX_PID_C2_ADP_BOOST_MODE_BITS_LEN (3)
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|
#define AW87XXX_PID_C2_ADP_BOOST_MODE_MASK \
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|
(~(((1<<AW87XXX_PID_C2_ADP_BOOST_MODE_BITS_LEN)-1) << AW87XXX_PID_C2_ADP_BOOST_MODE_START_BIT))
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|
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#define AW87XXX_PID_C2_ADP_BOOST_MODE_RCV (0)
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|
#define AW87XXX_PID_C2_ADP_BOOST_MODE_RCV_VALUE \
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|
(AW87XXX_PID_C2_ADP_BOOST_MODE_RCV << AW87XXX_PID_C2_ADP_BOOST_MODE_START_BIT)
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|
|
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#define AW87XXX_PID_C2_ADP_BOOST_MODE_FORCE_BOOST (1)
|
|
#define AW87XXX_PID_C2_ADP_BOOST_MODE_FORCE_BOOST_VALUE \
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|
(AW87XXX_PID_C2_ADP_BOOST_MODE_FORCE_BOOST << AW87XXX_PID_C2_ADP_BOOST_MODE_START_BIT)
|
|
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#define AW87XXX_PID_C2_ADP_BOOST_MODE_OSBOSD (2)
|
|
#define AW87XXX_PID_C2_ADP_BOOST_MODE_OSBOSD_VALUE \
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|
(AW87XXX_PID_C2_ADP_BOOST_MODE_OSBOSD << AW87XXX_PID_C2_ADP_BOOST_MODE_START_BIT)
|
|
|
|
#define AW87XXX_PID_C2_ADP_BOOST_MODE_TSBTSD (3)
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|
#define AW87XXX_PID_C2_ADP_BOOST_MODE_TSBTSD_VALUE \
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|
(AW87XXX_PID_C2_ADP_BOOST_MODE_TSBTSD << AW87XXX_PID_C2_ADP_BOOST_MODE_START_BIT)
|
|
|
|
#define AW87XXX_PID_C2_ADP_BOOST_MODE_TSBOSD (4)
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|
#define AW87XXX_PID_C2_ADP_BOOST_MODE_TSBOSD_VALUE \
|
|
(AW87XXX_PID_C2_ADP_BOOST_MODE_TSBOSD << AW87XXX_PID_C2_ADP_BOOST_MODE_START_BIT)
|
|
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#define AW87XXX_PID_C2_ADP_BOOST_MODE_MSBOSD (5)
|
|
#define AW87XXX_PID_C2_ADP_BOOST_MODE_MSBOSD_VALUE \
|
|
(AW87XXX_PID_C2_ADP_BOOST_MODE_MSBOSD << AW87XXX_PID_C2_ADP_BOOST_MODE_START_BIT)
|
|
|
|
#define AW87XXX_PID_C2_ADP_BOOST_MODE_MSBTSD (6)
|
|
#define AW87XXX_PID_C2_ADP_BOOST_MODE_MSBTSD_VALUE \
|
|
(AW87XXX_PID_C2_ADP_BOOST_MODE_MSBTSD << AW87XXX_PID_C2_ADP_BOOST_MODE_START_BIT)
|
|
|
|
#define AW87XXX_PID_C2_ADP_BOOST_MODE_MSBMSD (7)
|
|
#define AW87XXX_PID_C2_ADP_BOOST_MODE_MSBMSD_VALUE \
|
|
(AW87XXX_PID_C2_ADP_BOOST_MODE_MSBMSD << AW87XXX_PID_C2_ADP_BOOST_MODE_START_BIT)
|
|
|
|
#define AW87XXX_PID_C2_ADP_BOOST_MODE_DEFAULT (0x2)
|
|
#define AW87XXX_PID_C2_ADP_BOOST_MODE_DEFAULT_VALUE \
|
|
(AW87XXX_PID_C2_ADP_BOOST_MODE_DEFAULT << AW87XXX_PID_C2_ADP_BOOST_MODE_START_BIT)
|
|
|
|
/* SET_BOOST_VTH2 bit 2:0 (ADPSET 0x04) */
|
|
#define AW87XXX_PID_C2_SET_BOOST_VTH2_START_BIT (0)
|
|
#define AW87XXX_PID_C2_SET_BOOST_VTH2_BITS_LEN (3)
|
|
#define AW87XXX_PID_C2_SET_BOOST_VTH2_MASK \
|
|
(~(((1<<AW87XXX_PID_C2_SET_BOOST_VTH2_BITS_LEN)-1) << AW87XXX_PID_C2_SET_BOOST_VTH2_START_BIT))
|
|
|
|
#define AW87XXX_PID_C2_SET_BOOST_VTH2_1P2W (0)
|
|
#define AW87XXX_PID_C2_SET_BOOST_VTH2_1P2W_VALUE \
|
|
(AW87XXX_PID_C2_SET_BOOST_VTH2_1P2W << AW87XXX_PID_C2_SET_BOOST_VTH2_START_BIT)
|
|
|
|
#define AW87XXX_PID_C2_SET_BOOST_VTH2_1P4W (1)
|
|
#define AW87XXX_PID_C2_SET_BOOST_VTH2_1P4W_VALUE \
|
|
(AW87XXX_PID_C2_SET_BOOST_VTH2_1P4W << AW87XXX_PID_C2_SET_BOOST_VTH2_START_BIT)
|
|
|
|
#define AW87XXX_PID_C2_SET_BOOST_VTH2_1P6W (2)
|
|
#define AW87XXX_PID_C2_SET_BOOST_VTH2_1P6W_VALUE \
|
|
(AW87XXX_PID_C2_SET_BOOST_VTH2_1P6W << AW87XXX_PID_C2_SET_BOOST_VTH2_START_BIT)
|
|
|
|
#define AW87XXX_PID_C2_SET_BOOST_VTH2_1P8W (3)
|
|
#define AW87XXX_PID_C2_SET_BOOST_VTH2_1P8W_VALUE \
|
|
(AW87XXX_PID_C2_SET_BOOST_VTH2_1P8W << AW87XXX_PID_C2_SET_BOOST_VTH2_START_BIT)
|
|
|
|
#define AW87XXX_PID_C2_SET_BOOST_VTH2_2P0W (4)
|
|
#define AW87XXX_PID_C2_SET_BOOST_VTH2_2P0W_VALUE \
|
|
(AW87XXX_PID_C2_SET_BOOST_VTH2_2P0W << AW87XXX_PID_C2_SET_BOOST_VTH2_START_BIT)
|
|
|
|
#define AW87XXX_PID_C2_SET_BOOST_VTH2_2P2W (5)
|
|
#define AW87XXX_PID_C2_SET_BOOST_VTH2_2P2W_VALUE \
|
|
(AW87XXX_PID_C2_SET_BOOST_VTH2_2P2W << AW87XXX_PID_C2_SET_BOOST_VTH2_START_BIT)
|
|
|
|
#define AW87XXX_PID_C2_SET_BOOST_VTH2_2P4W (6)
|
|
#define AW87XXX_PID_C2_SET_BOOST_VTH2_2P4W_VALUE \
|
|
(AW87XXX_PID_C2_SET_BOOST_VTH2_2P4W << AW87XXX_PID_C2_SET_BOOST_VTH2_START_BIT)
|
|
|
|
#define AW87XXX_PID_C2_SET_BOOST_VTH2_2P6W (7)
|
|
#define AW87XXX_PID_C2_SET_BOOST_VTH2_2P6W_VALUE \
|
|
(AW87XXX_PID_C2_SET_BOOST_VTH2_2P6W << AW87XXX_PID_C2_SET_BOOST_VTH2_START_BIT)
|
|
|
|
#define AW87XXX_PID_C2_SET_BOOST_VTH2_DEFAULT (0x4)
|
|
#define AW87XXX_PID_C2_SET_BOOST_VTH2_DEFAULT_VALUE \
|
|
(AW87XXX_PID_C2_SET_BOOST_VTH2_DEFAULT << AW87XXX_PID_C2_SET_BOOST_VTH2_START_BIT)
|
|
|
|
/* default value of ADPSET (0x04) */
|
|
/* #define AW87XXX_PID_C2_ADPSET_DEFAULT (0xD4) */
|
|
|
|
/* PAG (0x05) detail */
|
|
/* REG_BOPADJ_AGC bit 7 (PAG 0x05) */
|
|
#define AW87XXX_PID_C2_REG_BOPADJ_AGC_START_BIT (7)
|
|
#define AW87XXX_PID_C2_REG_BOPADJ_AGC_BITS_LEN (1)
|
|
#define AW87XXX_PID_C2_REG_BOPADJ_AGC_MASK \
|
|
(~(((1<<AW87XXX_PID_C2_REG_BOPADJ_AGC_BITS_LEN)-1) << AW87XXX_PID_C2_REG_BOPADJ_AGC_START_BIT))
|
|
|
|
#define AW87XXX_PID_C2_REG_BOPADJ_AGC_BOP_CONTROL_AGC1_DISABLE (0)
|
|
#define AW87XXX_PID_C2_REG_BOPADJ_AGC_BOP_CONTROL_AGC1_DISABLE_VALUE \
|
|
(AW87XXX_PID_C2_REG_BOPADJ_AGC_BOP_CONTROL_AGC1_DISABLE << AW87XXX_PID_C2_REG_BOPADJ_AGC_START_BIT)
|
|
|
|
#define AW87XXX_PID_C2_REG_BOPADJ_AGC_DEFAULT (0x1)
|
|
#define AW87XXX_PID_C2_REG_BOPADJ_AGC_DEFAULT_VALUE \
|
|
(AW87XXX_PID_C2_REG_BOPADJ_AGC_DEFAULT << AW87XXX_PID_C2_REG_BOPADJ_AGC_START_BIT)
|
|
|
|
/* SET_BOOST_VTH1 bit 6:5 (PAG 0x05) */
|
|
#define AW87XXX_PID_C2_SET_BOOST_VTH1_START_BIT (5)
|
|
#define AW87XXX_PID_C2_SET_BOOST_VTH1_BITS_LEN (2)
|
|
#define AW87XXX_PID_C2_SET_BOOST_VTH1_MASK \
|
|
(~(((1<<AW87XXX_PID_C2_SET_BOOST_VTH1_BITS_LEN)-1) << AW87XXX_PID_C2_SET_BOOST_VTH1_START_BIT))
|
|
|
|
#define AW87XXX_PID_C2_SET_BOOST_VTH1_0P1W (0)
|
|
#define AW87XXX_PID_C2_SET_BOOST_VTH1_0P1W_VALUE \
|
|
(AW87XXX_PID_C2_SET_BOOST_VTH1_0P1W << AW87XXX_PID_C2_SET_BOOST_VTH1_START_BIT)
|
|
|
|
#define AW87XXX_PID_C2_SET_BOOST_VTH1_0P2W (1)
|
|
#define AW87XXX_PID_C2_SET_BOOST_VTH1_0P2W_VALUE \
|
|
(AW87XXX_PID_C2_SET_BOOST_VTH1_0P2W << AW87XXX_PID_C2_SET_BOOST_VTH1_START_BIT)
|
|
|
|
#define AW87XXX_PID_C2_SET_BOOST_VTH1_0P3W (2)
|
|
#define AW87XXX_PID_C2_SET_BOOST_VTH1_0P3W_VALUE \
|
|
(AW87XXX_PID_C2_SET_BOOST_VTH1_0P3W << AW87XXX_PID_C2_SET_BOOST_VTH1_START_BIT)
|
|
|
|
#define AW87XXX_PID_C2_SET_BOOST_VTH1_0P4W (3)
|
|
#define AW87XXX_PID_C2_SET_BOOST_VTH1_0P4W_VALUE \
|
|
(AW87XXX_PID_C2_SET_BOOST_VTH1_0P4W << AW87XXX_PID_C2_SET_BOOST_VTH1_START_BIT)
|
|
|
|
#define AW87XXX_PID_C2_SET_BOOST_VTH1_DEFAULT (0x2)
|
|
#define AW87XXX_PID_C2_SET_BOOST_VTH1_DEFAULT_VALUE \
|
|
(AW87XXX_PID_C2_SET_BOOST_VTH1_DEFAULT << AW87XXX_PID_C2_SET_BOOST_VTH1_START_BIT)
|
|
|
|
/* EN_BOM bit 4 (PAG 0x05) */
|
|
#define AW87XXX_PID_C2_EN_BOM_START_BIT (4)
|
|
#define AW87XXX_PID_C2_EN_BOM_BITS_LEN (1)
|
|
#define AW87XXX_PID_C2_EN_BOM_MASK \
|
|
(~(((1<<AW87XXX_PID_C2_EN_BOM_BITS_LEN)-1) << AW87XXX_PID_C2_EN_BOM_START_BIT))
|
|
|
|
#define AW87XXX_PID_C2_EN_BOM_DISABLE (0)
|
|
#define AW87XXX_PID_C2_EN_BOM_DISABLE_VALUE \
|
|
(AW87XXX_PID_C2_EN_BOM_DISABLE << AW87XXX_PID_C2_EN_BOM_START_BIT)
|
|
|
|
#define AW87XXX_PID_C2_EN_BOM_ENABLE (1)
|
|
#define AW87XXX_PID_C2_EN_BOM_ENABLE_VALUE \
|
|
(AW87XXX_PID_C2_EN_BOM_ENABLE << AW87XXX_PID_C2_EN_BOM_START_BIT)
|
|
|
|
#define AW87XXX_PID_C2_EN_BOM_DEFAULT (0x0)
|
|
#define AW87XXX_PID_C2_EN_BOM_DEFAULT_VALUE \
|
|
(AW87XXX_PID_C2_EN_BOM_DEFAULT << AW87XXX_PID_C2_EN_BOM_START_BIT)
|
|
|
|
/* EN_LN bit 3 (PAG 0x05) */
|
|
#define AW87XXX_PID_C2_EN_LN_START_BIT (3)
|
|
#define AW87XXX_PID_C2_EN_LN_BITS_LEN (1)
|
|
#define AW87XXX_PID_C2_EN_LN_MASK \
|
|
(~(((1<<AW87XXX_PID_C2_EN_LN_BITS_LEN)-1) << AW87XXX_PID_C2_EN_LN_START_BIT))
|
|
|
|
#define AW87XXX_PID_C2_EN_LN_DISABLE (0)
|
|
#define AW87XXX_PID_C2_EN_LN_DISABLE_VALUE \
|
|
(AW87XXX_PID_C2_EN_LN_DISABLE << AW87XXX_PID_C2_EN_LN_START_BIT)
|
|
|
|
#define AW87XXX_PID_C2_EN_LN_ENABLE (1)
|
|
#define AW87XXX_PID_C2_EN_LN_ENABLE_VALUE \
|
|
(AW87XXX_PID_C2_EN_LN_ENABLE << AW87XXX_PID_C2_EN_LN_START_BIT)
|
|
|
|
#define AW87XXX_PID_C2_EN_LN_DEFAULT (0x0)
|
|
#define AW87XXX_PID_C2_EN_LN_DEFAULT_VALUE \
|
|
(AW87XXX_PID_C2_EN_LN_DEFAULT << AW87XXX_PID_C2_EN_LN_START_BIT)
|
|
|
|
/* PA_GAIN bit 2:0 (PAG 0x05) */
|
|
#define AW87XXX_PID_C2_PA_GAIN_START_BIT (0)
|
|
#define AW87XXX_PID_C2_PA_GAIN_BITS_LEN (3)
|
|
#define AW87XXX_PID_C2_PA_GAIN_MASK \
|
|
(~(((1<<AW87XXX_PID_C2_PA_GAIN_BITS_LEN)-1) << AW87XXX_PID_C2_PA_GAIN_START_BIT))
|
|
|
|
#define AW87XXX_PID_C2_PA_GAIN_0DB (0)
|
|
#define AW87XXX_PID_C2_PA_GAIN_0DB_VALUE \
|
|
(AW87XXX_PID_C2_PA_GAIN_0DB << AW87XXX_PID_C2_PA_GAIN_START_BIT)
|
|
|
|
#define AW87XXX_PID_C2_PA_GAIN_3DB (1)
|
|
#define AW87XXX_PID_C2_PA_GAIN_3DB_VALUE \
|
|
(AW87XXX_PID_C2_PA_GAIN_3DB << AW87XXX_PID_C2_PA_GAIN_START_BIT)
|
|
|
|
#define AW87XXX_PID_C2_PA_GAIN_6DB (2)
|
|
#define AW87XXX_PID_C2_PA_GAIN_6DB_VALUE \
|
|
(AW87XXX_PID_C2_PA_GAIN_6DB << AW87XXX_PID_C2_PA_GAIN_START_BIT)
|
|
|
|
#define AW87XXX_PID_C2_PA_GAIN_12DB (3)
|
|
#define AW87XXX_PID_C2_PA_GAIN_12DB_VALUE \
|
|
(AW87XXX_PID_C2_PA_GAIN_12DB << AW87XXX_PID_C2_PA_GAIN_START_BIT)
|
|
|
|
#define AW87XXX_PID_C2_PA_GAIN_15DB (4)
|
|
#define AW87XXX_PID_C2_PA_GAIN_15DB_VALUE \
|
|
(AW87XXX_PID_C2_PA_GAIN_15DB << AW87XXX_PID_C2_PA_GAIN_START_BIT)
|
|
|
|
#define AW87XXX_PID_C2_PA_GAIN_18DB (5)
|
|
#define AW87XXX_PID_C2_PA_GAIN_18DB_VALUE \
|
|
(AW87XXX_PID_C2_PA_GAIN_18DB << AW87XXX_PID_C2_PA_GAIN_START_BIT)
|
|
|
|
#define AW87XXX_PID_C2_PA_GAIN_21DB (6)
|
|
#define AW87XXX_PID_C2_PA_GAIN_21DB_VALUE \
|
|
(AW87XXX_PID_C2_PA_GAIN_21DB << AW87XXX_PID_C2_PA_GAIN_START_BIT)
|
|
|
|
#define AW87XXX_PID_C2_PA_GAIN_24DB (7)
|
|
#define AW87XXX_PID_C2_PA_GAIN_24DB_VALUE \
|
|
(AW87XXX_PID_C2_PA_GAIN_24DB << AW87XXX_PID_C2_PA_GAIN_START_BIT)
|
|
|
|
#define AW87XXX_PID_C2_PA_GAIN_DEFAULT (0x5)
|
|
#define AW87XXX_PID_C2_PA_GAIN_DEFAULT_VALUE \
|
|
(AW87XXX_PID_C2_PA_GAIN_DEFAULT << AW87XXX_PID_C2_PA_GAIN_START_BIT)
|
|
|
|
/* default value of PAG (0x05) */
|
|
/* #define AW87XXX_PID_C2_PAG_DEFAULT (0xC5) */
|
|
|
|
/* AGC1PA (0x06) detail */
|
|
/* PD_AGC1 bit 7 (AGC1PA 0x06) */
|
|
#define AW87XXX_PID_C2_PD_AGC1_START_BIT (7)
|
|
#define AW87XXX_PID_C2_PD_AGC1_BITS_LEN (1)
|
|
#define AW87XXX_PID_C2_PD_AGC1_MASK \
|
|
(~(((1<<AW87XXX_PID_C2_PD_AGC1_BITS_LEN)-1) << AW87XXX_PID_C2_PD_AGC1_START_BIT))
|
|
|
|
#define AW87XXX_PID_C2_PD_AGC1_ENABLE (0)
|
|
#define AW87XXX_PID_C2_PD_AGC1_ENABLE_VALUE \
|
|
(AW87XXX_PID_C2_PD_AGC1_ENABLE << AW87XXX_PID_C2_PD_AGC1_START_BIT)
|
|
|
|
#define AW87XXX_PID_C2_PD_AGC1_DISABLE (1)
|
|
#define AW87XXX_PID_C2_PD_AGC1_DISABLE_VALUE \
|
|
(AW87XXX_PID_C2_PD_AGC1_DISABLE << AW87XXX_PID_C2_PD_AGC1_START_BIT)
|
|
|
|
#define AW87XXX_PID_C2_PD_AGC1_DEFAULT (0x0)
|
|
#define AW87XXX_PID_C2_PD_AGC1_DEFAULT_VALUE \
|
|
(AW87XXX_PID_C2_PD_AGC1_DEFAULT << AW87XXX_PID_C2_PD_AGC1_START_BIT)
|
|
|
|
/* AGC1_OUTPUT_LEVEL bit 6:3 (AGC1PA 0x06) */
|
|
#define AW87XXX_PID_C2_AGC1_OUTPUT_LEVEL_START_BIT (3)
|
|
#define AW87XXX_PID_C2_AGC1_OUTPUT_LEVEL_BITS_LEN (4)
|
|
#define AW87XXX_PID_C2_AGC1_OUTPUT_LEVEL_MASK \
|
|
(~(((1<<AW87XXX_PID_C2_AGC1_OUTPUT_LEVEL_BITS_LEN)-1) << AW87XXX_PID_C2_AGC1_OUTPUT_LEVEL_START_BIT))
|
|
|
|
#define AW87XXX_PID_C2_AGC1_OUTPUT_LEVEL_5V (0)
|
|
#define AW87XXX_PID_C2_AGC1_OUTPUT_LEVEL_5V_VALUE \
|
|
(AW87XXX_PID_C2_AGC1_OUTPUT_LEVEL_5V << AW87XXX_PID_C2_AGC1_OUTPUT_LEVEL_START_BIT)
|
|
|
|
#define AW87XXX_PID_C2_AGC1_OUTPUT_LEVEL_5P2V (1)
|
|
#define AW87XXX_PID_C2_AGC1_OUTPUT_LEVEL_5P2V_VALUE \
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(AW87XXX_PID_C2_AGC1_OUTPUT_LEVEL_5P2V << AW87XXX_PID_C2_AGC1_OUTPUT_LEVEL_START_BIT)
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#define AW87XXX_PID_C2_AGC1_OUTPUT_LEVEL_5P4V (2)
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#define AW87XXX_PID_C2_AGC1_OUTPUT_LEVEL_5P4V_VALUE \
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(AW87XXX_PID_C2_AGC1_OUTPUT_LEVEL_5P4V << AW87XXX_PID_C2_AGC1_OUTPUT_LEVEL_START_BIT)
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#define AW87XXX_PID_C2_AGC1_OUTPUT_LEVEL_5P6V (3)
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#define AW87XXX_PID_C2_AGC1_OUTPUT_LEVEL_5P6V_VALUE \
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(AW87XXX_PID_C2_AGC1_OUTPUT_LEVEL_5P6V << AW87XXX_PID_C2_AGC1_OUTPUT_LEVEL_START_BIT)
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#define AW87XXX_PID_C2_AGC1_OUTPUT_LEVEL_5P8V (4)
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#define AW87XXX_PID_C2_AGC1_OUTPUT_LEVEL_5P8V_VALUE \
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(AW87XXX_PID_C2_AGC1_OUTPUT_LEVEL_5P8V << AW87XXX_PID_C2_AGC1_OUTPUT_LEVEL_START_BIT)
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#define AW87XXX_PID_C2_AGC1_OUTPUT_LEVEL_6P0V (5)
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#define AW87XXX_PID_C2_AGC1_OUTPUT_LEVEL_6P0V_VALUE \
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(AW87XXX_PID_C2_AGC1_OUTPUT_LEVEL_6P0V << AW87XXX_PID_C2_AGC1_OUTPUT_LEVEL_START_BIT)
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#define AW87XXX_PID_C2_AGC1_OUTPUT_LEVEL_6P2V (6)
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#define AW87XXX_PID_C2_AGC1_OUTPUT_LEVEL_6P2V_VALUE \
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(AW87XXX_PID_C2_AGC1_OUTPUT_LEVEL_6P2V << AW87XXX_PID_C2_AGC1_OUTPUT_LEVEL_START_BIT)
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#define AW87XXX_PID_C2_AGC1_OUTPUT_LEVEL_6P4V (7)
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#define AW87XXX_PID_C2_AGC1_OUTPUT_LEVEL_6P4V_VALUE \
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(AW87XXX_PID_C2_AGC1_OUTPUT_LEVEL_6P4V << AW87XXX_PID_C2_AGC1_OUTPUT_LEVEL_START_BIT)
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#define AW87XXX_PID_C2_AGC1_OUTPUT_LEVEL_6P6V (8)
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#define AW87XXX_PID_C2_AGC1_OUTPUT_LEVEL_6P6V_VALUE \
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(AW87XXX_PID_C2_AGC1_OUTPUT_LEVEL_6P6V << AW87XXX_PID_C2_AGC1_OUTPUT_LEVEL_START_BIT)
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#define AW87XXX_PID_C2_AGC1_OUTPUT_LEVEL_6P8V (9)
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#define AW87XXX_PID_C2_AGC1_OUTPUT_LEVEL_6P8V_VALUE \
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(AW87XXX_PID_C2_AGC1_OUTPUT_LEVEL_6P8V << AW87XXX_PID_C2_AGC1_OUTPUT_LEVEL_START_BIT)
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#define AW87XXX_PID_C2_AGC1_OUTPUT_LEVEL_7V (10)
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#define AW87XXX_PID_C2_AGC1_OUTPUT_LEVEL_7V_VALUE \
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(AW87XXX_PID_C2_AGC1_OUTPUT_LEVEL_7V << AW87XXX_PID_C2_AGC1_OUTPUT_LEVEL_START_BIT)
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#define AW87XXX_PID_C2_AGC1_OUTPUT_LEVEL_7P2V (11)
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#define AW87XXX_PID_C2_AGC1_OUTPUT_LEVEL_7P2V_VALUE \
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(AW87XXX_PID_C2_AGC1_OUTPUT_LEVEL_7P2V << AW87XXX_PID_C2_AGC1_OUTPUT_LEVEL_START_BIT)
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#define AW87XXX_PID_C2_AGC1_OUTPUT_LEVEL_7P4V (12)
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#define AW87XXX_PID_C2_AGC1_OUTPUT_LEVEL_7P4V_VALUE \
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(AW87XXX_PID_C2_AGC1_OUTPUT_LEVEL_7P4V << AW87XXX_PID_C2_AGC1_OUTPUT_LEVEL_START_BIT)
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#define AW87XXX_PID_C2_AGC1_OUTPUT_LEVEL_7P6V (13)
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#define AW87XXX_PID_C2_AGC1_OUTPUT_LEVEL_7P6V_VALUE \
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(AW87XXX_PID_C2_AGC1_OUTPUT_LEVEL_7P6V << AW87XXX_PID_C2_AGC1_OUTPUT_LEVEL_START_BIT)
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#define AW87XXX_PID_C2_AGC1_OUTPUT_LEVEL_7P8V (14)
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#define AW87XXX_PID_C2_AGC1_OUTPUT_LEVEL_7P8V_VALUE \
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(AW87XXX_PID_C2_AGC1_OUTPUT_LEVEL_7P8V << AW87XXX_PID_C2_AGC1_OUTPUT_LEVEL_START_BIT)
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#define AW87XXX_PID_C2_AGC1_OUTPUT_LEVEL_8V (15)
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#define AW87XXX_PID_C2_AGC1_OUTPUT_LEVEL_8V_VALUE \
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(AW87XXX_PID_C2_AGC1_OUTPUT_LEVEL_8V << AW87XXX_PID_C2_AGC1_OUTPUT_LEVEL_START_BIT)
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#define AW87XXX_PID_C2_AGC1_OUTPUT_LEVEL_DEFAULT (0x9)
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#define AW87XXX_PID_C2_AGC1_OUTPUT_LEVEL_DEFAULT_VALUE \
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(AW87XXX_PID_C2_AGC1_OUTPUT_LEVEL_DEFAULT << AW87XXX_PID_C2_AGC1_OUTPUT_LEVEL_START_BIT)
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/* AGC1_ATT_TIME bit 2:0 (AGC1PA 0x06) */
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#define AW87XXX_PID_C2_AGC1_ATT_TIME_START_BIT (0)
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#define AW87XXX_PID_C2_AGC1_ATT_TIME_BITS_LEN (3)
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#define AW87XXX_PID_C2_AGC1_ATT_TIME_MASK \
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(~(((1<<AW87XXX_PID_C2_AGC1_ATT_TIME_BITS_LEN)-1) << AW87XXX_PID_C2_AGC1_ATT_TIME_START_BIT))
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#define AW87XXX_PID_C2_AGC1_ATT_TIME_0P04MSDB (0)
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#define AW87XXX_PID_C2_AGC1_ATT_TIME_0P04MSDB_VALUE \
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(AW87XXX_PID_C2_AGC1_ATT_TIME_0P04MSDB << AW87XXX_PID_C2_AGC1_ATT_TIME_START_BIT)
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#define AW87XXX_PID_C2_AGC1_ATT_TIME_0P08MSDB (1)
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#define AW87XXX_PID_C2_AGC1_ATT_TIME_0P08MSDB_VALUE \
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(AW87XXX_PID_C2_AGC1_ATT_TIME_0P08MSDB << AW87XXX_PID_C2_AGC1_ATT_TIME_START_BIT)
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#define AW87XXX_PID_C2_AGC1_ATT_TIME_0P16MSDB (2)
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#define AW87XXX_PID_C2_AGC1_ATT_TIME_0P16MSDB_VALUE \
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(AW87XXX_PID_C2_AGC1_ATT_TIME_0P16MSDB << AW87XXX_PID_C2_AGC1_ATT_TIME_START_BIT)
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#define AW87XXX_PID_C2_AGC1_ATT_TIME_0P32MSDB (3)
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#define AW87XXX_PID_C2_AGC1_ATT_TIME_0P32MSDB_VALUE \
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(AW87XXX_PID_C2_AGC1_ATT_TIME_0P32MSDB << AW87XXX_PID_C2_AGC1_ATT_TIME_START_BIT)
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#define AW87XXX_PID_C2_AGC1_ATT_TIME_0P02MSDB (4)
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#define AW87XXX_PID_C2_AGC1_ATT_TIME_0P02MSDB_VALUE \
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(AW87XXX_PID_C2_AGC1_ATT_TIME_0P02MSDB << AW87XXX_PID_C2_AGC1_ATT_TIME_START_BIT)
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#define AW87XXX_PID_C2_AGC1_ATT_TIME_0P01MSDB (5)
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#define AW87XXX_PID_C2_AGC1_ATT_TIME_0P01MSDB_VALUE \
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(AW87XXX_PID_C2_AGC1_ATT_TIME_0P01MSDB << AW87XXX_PID_C2_AGC1_ATT_TIME_START_BIT)
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#define AW87XXX_PID_C2_AGC1_ATT_TIME_0P005MSDB (6)
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#define AW87XXX_PID_C2_AGC1_ATT_TIME_0P005MSDB_VALUE \
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(AW87XXX_PID_C2_AGC1_ATT_TIME_0P005MSDB << AW87XXX_PID_C2_AGC1_ATT_TIME_START_BIT)
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#define AW87XXX_PID_C2_AGC1_ATT_TIME_DEFAULT (0x1)
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#define AW87XXX_PID_C2_AGC1_ATT_TIME_DEFAULT_VALUE \
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(AW87XXX_PID_C2_AGC1_ATT_TIME_DEFAULT << AW87XXX_PID_C2_AGC1_ATT_TIME_START_BIT)
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/* default value of AGC1PA (0x06) */
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/* #define AW87XXX_PID_C2_AGC1PA_DEFAULT (0x49) */
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|
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/* AGC2PA (0x07) detail */
|
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/* AGC2_OUTPUT_POWER bit 6:3 (AGC2PA 0x07) */
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|
#define AW87XXX_PID_C2_AGC2_OUTPUT_POWER_START_BIT (3)
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#define AW87XXX_PID_C2_AGC2_OUTPUT_POWER_BITS_LEN (4)
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#define AW87XXX_PID_C2_AGC2_OUTPUT_POWER_MASK \
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(~(((1<<AW87XXX_PID_C2_AGC2_OUTPUT_POWER_BITS_LEN)-1) << AW87XXX_PID_C2_AGC2_OUTPUT_POWER_START_BIT))
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#define AW87XXX_PID_C2_AGC2_OUTPUT_POWER_2P0W4_OHM (0)
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#define AW87XXX_PID_C2_AGC2_OUTPUT_POWER_2P0W4_OHM_VALUE \
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|
(AW87XXX_PID_C2_AGC2_OUTPUT_POWER_2P0W4_OHM << AW87XXX_PID_C2_AGC2_OUTPUT_POWER_START_BIT)
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#define AW87XXX_PID_C2_AGC2_OUTPUT_POWER_2P4W4_OHM (1)
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#define AW87XXX_PID_C2_AGC2_OUTPUT_POWER_2P4W4_OHM_VALUE \
|
|
(AW87XXX_PID_C2_AGC2_OUTPUT_POWER_2P4W4_OHM << AW87XXX_PID_C2_AGC2_OUTPUT_POWER_START_BIT)
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|
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#define AW87XXX_PID_C2_AGC2_OUTPUT_POWER_2P8W4_OHM (2)
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#define AW87XXX_PID_C2_AGC2_OUTPUT_POWER_2P8W4_OHM_VALUE \
|
|
(AW87XXX_PID_C2_AGC2_OUTPUT_POWER_2P8W4_OHM << AW87XXX_PID_C2_AGC2_OUTPUT_POWER_START_BIT)
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|
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|
#define AW87XXX_PID_C2_AGC2_OUTPUT_POWER_3P2W4_OHM (3)
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|
#define AW87XXX_PID_C2_AGC2_OUTPUT_POWER_3P2W4_OHM_VALUE \
|
|
(AW87XXX_PID_C2_AGC2_OUTPUT_POWER_3P2W4_OHM << AW87XXX_PID_C2_AGC2_OUTPUT_POWER_START_BIT)
|
|
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#define AW87XXX_PID_C2_AGC2_OUTPUT_POWER_3P6W4_OHM (4)
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|
#define AW87XXX_PID_C2_AGC2_OUTPUT_POWER_3P6W4_OHM_VALUE \
|
|
(AW87XXX_PID_C2_AGC2_OUTPUT_POWER_3P6W4_OHM << AW87XXX_PID_C2_AGC2_OUTPUT_POWER_START_BIT)
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|
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|
#define AW87XXX_PID_C2_AGC2_OUTPUT_POWER_4P0W4_OHM (5)
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|
#define AW87XXX_PID_C2_AGC2_OUTPUT_POWER_4P0W4_OHM_VALUE \
|
|
(AW87XXX_PID_C2_AGC2_OUTPUT_POWER_4P0W4_OHM << AW87XXX_PID_C2_AGC2_OUTPUT_POWER_START_BIT)
|
|
|
|
#define AW87XXX_PID_C2_AGC2_OUTPUT_POWER_4P4W4_OHM (6)
|
|
#define AW87XXX_PID_C2_AGC2_OUTPUT_POWER_4P4W4_OHM_VALUE \
|
|
(AW87XXX_PID_C2_AGC2_OUTPUT_POWER_4P4W4_OHM << AW87XXX_PID_C2_AGC2_OUTPUT_POWER_START_BIT)
|
|
|
|
#define AW87XXX_PID_C2_AGC2_OUTPUT_POWER_4P8W4_OHM (7)
|
|
#define AW87XXX_PID_C2_AGC2_OUTPUT_POWER_4P8W4_OHM_VALUE \
|
|
(AW87XXX_PID_C2_AGC2_OUTPUT_POWER_4P8W4_OHM << AW87XXX_PID_C2_AGC2_OUTPUT_POWER_START_BIT)
|
|
|
|
#define AW87XXX_PID_C2_AGC2_OUTPUT_POWER_5P2W4_OHM (8)
|
|
#define AW87XXX_PID_C2_AGC2_OUTPUT_POWER_5P2W4_OHM_VALUE \
|
|
(AW87XXX_PID_C2_AGC2_OUTPUT_POWER_5P2W4_OHM << AW87XXX_PID_C2_AGC2_OUTPUT_POWER_START_BIT)
|
|
|
|
#define AW87XXX_PID_C2_AGC2_OUTPUT_POWER_5P6W4_OHM (9)
|
|
#define AW87XXX_PID_C2_AGC2_OUTPUT_POWER_5P6W4_OHM_VALUE \
|
|
(AW87XXX_PID_C2_AGC2_OUTPUT_POWER_5P6W4_OHM << AW87XXX_PID_C2_AGC2_OUTPUT_POWER_START_BIT)
|
|
|
|
#define AW87XXX_PID_C2_AGC2_OUTPUT_POWER_6W4_OHM (10)
|
|
#define AW87XXX_PID_C2_AGC2_OUTPUT_POWER_6W4_OHM_VALUE \
|
|
(AW87XXX_PID_C2_AGC2_OUTPUT_POWER_6W4_OHM << AW87XXX_PID_C2_AGC2_OUTPUT_POWER_START_BIT)
|
|
|
|
#define AW87XXX_PID_C2_AGC2_OUTPUT_POWER_AGC2_OFF (11)
|
|
#define AW87XXX_PID_C2_AGC2_OUTPUT_POWER_AGC2_OFF_VALUE \
|
|
(AW87XXX_PID_C2_AGC2_OUTPUT_POWER_AGC2_OFF << AW87XXX_PID_C2_AGC2_OUTPUT_POWER_START_BIT)
|
|
|
|
#define AW87XXX_PID_C2_AGC2_OUTPUT_POWER_DEFAULT (0x3)
|
|
#define AW87XXX_PID_C2_AGC2_OUTPUT_POWER_DEFAULT_VALUE \
|
|
(AW87XXX_PID_C2_AGC2_OUTPUT_POWER_DEFAULT << AW87XXX_PID_C2_AGC2_OUTPUT_POWER_START_BIT)
|
|
|
|
/* AGC2_ATT_TIME bit 2:0 (AGC2PA 0x07) */
|
|
#define AW87XXX_PID_C2_AGC2_ATT_TIME_START_BIT (0)
|
|
#define AW87XXX_PID_C2_AGC2_ATT_TIME_BITS_LEN (3)
|
|
#define AW87XXX_PID_C2_AGC2_ATT_TIME_MASK \
|
|
(~(((1<<AW87XXX_PID_C2_AGC2_ATT_TIME_BITS_LEN)-1) << AW87XXX_PID_C2_AGC2_ATT_TIME_START_BIT))
|
|
|
|
#define AW87XXX_PID_C2_AGC2_ATT_TIME_0P16MSDB (0)
|
|
#define AW87XXX_PID_C2_AGC2_ATT_TIME_0P16MSDB_VALUE \
|
|
(AW87XXX_PID_C2_AGC2_ATT_TIME_0P16MSDB << AW87XXX_PID_C2_AGC2_ATT_TIME_START_BIT)
|
|
|
|
#define AW87XXX_PID_C2_AGC2_ATT_TIME_0P32MSDB (1)
|
|
#define AW87XXX_PID_C2_AGC2_ATT_TIME_0P32MSDB_VALUE \
|
|
(AW87XXX_PID_C2_AGC2_ATT_TIME_0P32MSDB << AW87XXX_PID_C2_AGC2_ATT_TIME_START_BIT)
|
|
|
|
#define AW87XXX_PID_C2_AGC2_ATT_TIME_0P64MSDB (2)
|
|
#define AW87XXX_PID_C2_AGC2_ATT_TIME_0P64MSDB_VALUE \
|
|
(AW87XXX_PID_C2_AGC2_ATT_TIME_0P64MSDB << AW87XXX_PID_C2_AGC2_ATT_TIME_START_BIT)
|
|
|
|
#define AW87XXX_PID_C2_AGC2_ATT_TIME_2P56MSDB (3)
|
|
#define AW87XXX_PID_C2_AGC2_ATT_TIME_2P56MSDB_VALUE \
|
|
(AW87XXX_PID_C2_AGC2_ATT_TIME_2P56MSDB << AW87XXX_PID_C2_AGC2_ATT_TIME_START_BIT)
|
|
|
|
#define AW87XXX_PID_C2_AGC2_ATT_TIME_10P24MSDB (4)
|
|
#define AW87XXX_PID_C2_AGC2_ATT_TIME_10P24MSDB_VALUE \
|
|
(AW87XXX_PID_C2_AGC2_ATT_TIME_10P24MSDB << AW87XXX_PID_C2_AGC2_ATT_TIME_START_BIT)
|
|
|
|
#define AW87XXX_PID_C2_AGC2_ATT_TIME_40P96MSDB (5)
|
|
#define AW87XXX_PID_C2_AGC2_ATT_TIME_40P96MSDB_VALUE \
|
|
(AW87XXX_PID_C2_AGC2_ATT_TIME_40P96MSDB << AW87XXX_PID_C2_AGC2_ATT_TIME_START_BIT)
|
|
|
|
#define AW87XXX_PID_C2_AGC2_ATT_TIME_82MSDB (6)
|
|
#define AW87XXX_PID_C2_AGC2_ATT_TIME_82MSDB_VALUE \
|
|
(AW87XXX_PID_C2_AGC2_ATT_TIME_82MSDB << AW87XXX_PID_C2_AGC2_ATT_TIME_START_BIT)
|
|
|
|
#define AW87XXX_PID_C2_AGC2_ATT_TIME_164MSDB (7)
|
|
#define AW87XXX_PID_C2_AGC2_ATT_TIME_164MSDB_VALUE \
|
|
(AW87XXX_PID_C2_AGC2_ATT_TIME_164MSDB << AW87XXX_PID_C2_AGC2_ATT_TIME_START_BIT)
|
|
|
|
#define AW87XXX_PID_C2_AGC2_ATT_TIME_DEFAULT (0x2)
|
|
#define AW87XXX_PID_C2_AGC2_ATT_TIME_DEFAULT_VALUE \
|
|
(AW87XXX_PID_C2_AGC2_ATT_TIME_DEFAULT << AW87XXX_PID_C2_AGC2_ATT_TIME_START_BIT)
|
|
|
|
/* default value of AGC2PA (0x07) */
|
|
/* #define AW87XXX_PID_C2_AGC2PA_DEFAULT (0x1A) */
|
|
|
|
/* AGC3PA (0x08) detail */
|
|
/* LPVTH bit 7:5 (AGC3PA 0x08) */
|
|
#define AW87XXX_PID_C2_LPVTH_START_BIT (5)
|
|
#define AW87XXX_PID_C2_LPVTH_BITS_LEN (3)
|
|
#define AW87XXX_PID_C2_LPVTH_MASK \
|
|
(~(((1<<AW87XXX_PID_C2_LPVTH_BITS_LEN)-1) << AW87XXX_PID_C2_LPVTH_START_BIT))
|
|
|
|
#define AW87XXX_PID_C2_LPVTH_VTH7MV_VTHHYS2MV (0)
|
|
#define AW87XXX_PID_C2_LPVTH_VTH7MV_VTHHYS2MV_VALUE \
|
|
(AW87XXX_PID_C2_LPVTH_VTH7MV_VTHHYS2MV << AW87XXX_PID_C2_LPVTH_START_BIT)
|
|
|
|
#define AW87XXX_PID_C2_LPVTH_VTH10MV_VTHHYS7MV (1)
|
|
#define AW87XXX_PID_C2_LPVTH_VTH10MV_VTHHYS7MV_VALUE \
|
|
(AW87XXX_PID_C2_LPVTH_VTH10MV_VTHHYS7MV << AW87XXX_PID_C2_LPVTH_START_BIT)
|
|
|
|
#define AW87XXX_PID_C2_LPVTH_VTH12MV_VTHHYS10MV (2)
|
|
#define AW87XXX_PID_C2_LPVTH_VTH12MV_VTHHYS10MV_VALUE \
|
|
(AW87XXX_PID_C2_LPVTH_VTH12MV_VTHHYS10MV << AW87XXX_PID_C2_LPVTH_START_BIT)
|
|
|
|
#define AW87XXX_PID_C2_LPVTH_VTH14MV_VTHHYS12MV (3)
|
|
#define AW87XXX_PID_C2_LPVTH_VTH14MV_VTHHYS12MV_VALUE \
|
|
(AW87XXX_PID_C2_LPVTH_VTH14MV_VTHHYS12MV << AW87XXX_PID_C2_LPVTH_START_BIT)
|
|
|
|
#define AW87XXX_PID_C2_LPVTH_VTH16MV_VTHHYS14MV (4)
|
|
#define AW87XXX_PID_C2_LPVTH_VTH16MV_VTHHYS14MV_VALUE \
|
|
(AW87XXX_PID_C2_LPVTH_VTH16MV_VTHHYS14MV << AW87XXX_PID_C2_LPVTH_START_BIT)
|
|
|
|
#define AW87XXX_PID_C2_LPVTH_VTH18MV_VTHHYS16MV (5)
|
|
#define AW87XXX_PID_C2_LPVTH_VTH18MV_VTHHYS16MV_VALUE \
|
|
(AW87XXX_PID_C2_LPVTH_VTH18MV_VTHHYS16MV << AW87XXX_PID_C2_LPVTH_START_BIT)
|
|
|
|
#define AW87XXX_PID_C2_LPVTH_VTHVLCZ_VTHHYS16MV (6)
|
|
#define AW87XXX_PID_C2_LPVTH_VTHVLCZ_VTHHYS16MV_VALUE \
|
|
(AW87XXX_PID_C2_LPVTH_VTHVLCZ_VTHHYS16MV << AW87XXX_PID_C2_LPVTH_START_BIT)
|
|
|
|
#define AW87XXX_PID_C2_LPVTH_VTH35MV_VTHHYS30MV (7)
|
|
#define AW87XXX_PID_C2_LPVTH_VTH35MV_VTHHYS30MV_VALUE \
|
|
(AW87XXX_PID_C2_LPVTH_VTH35MV_VTHHYS30MV << AW87XXX_PID_C2_LPVTH_START_BIT)
|
|
|
|
#define AW87XXX_PID_C2_LPVTH_DEFAULT (0x1)
|
|
#define AW87XXX_PID_C2_LPVTH_DEFAULT_VALUE \
|
|
(AW87XXX_PID_C2_LPVTH_DEFAULT << AW87XXX_PID_C2_LPVTH_START_BIT)
|
|
|
|
/* PD_AGC3 bit 4 (AGC3PA 0x08) */
|
|
#define AW87XXX_PID_C2_PD_AGC3_START_BIT (4)
|
|
#define AW87XXX_PID_C2_PD_AGC3_BITS_LEN (1)
|
|
#define AW87XXX_PID_C2_PD_AGC3_MASK \
|
|
(~(((1<<AW87XXX_PID_C2_PD_AGC3_BITS_LEN)-1) << AW87XXX_PID_C2_PD_AGC3_START_BIT))
|
|
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#define AW87XXX_PID_C2_PD_AGC3_ENABLE (0)
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#define AW87XXX_PID_C2_PD_AGC3_ENABLE_VALUE \
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(AW87XXX_PID_C2_PD_AGC3_ENABLE << AW87XXX_PID_C2_PD_AGC3_START_BIT)
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#define AW87XXX_PID_C2_PD_AGC3_DISABLE (1)
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#define AW87XXX_PID_C2_PD_AGC3_DISABLE_VALUE \
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(AW87XXX_PID_C2_PD_AGC3_DISABLE << AW87XXX_PID_C2_PD_AGC3_START_BIT)
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#define AW87XXX_PID_C2_PD_AGC3_DEFAULT (0x0)
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#define AW87XXX_PID_C2_PD_AGC3_DEFAULT_VALUE \
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(AW87XXX_PID_C2_PD_AGC3_DEFAULT << AW87XXX_PID_C2_PD_AGC3_START_BIT)
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/* AGC3_OUTPUT_POWER bit 3:0 (AGC3PA 0x08) */
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#define AW87XXX_PID_C2_AGC3_OUTPUT_POWER_START_BIT (0)
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#define AW87XXX_PID_C2_AGC3_OUTPUT_POWER_BITS_LEN (4)
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#define AW87XXX_PID_C2_AGC3_OUTPUT_POWER_MASK \
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(~(((1<<AW87XXX_PID_C2_AGC3_OUTPUT_POWER_BITS_LEN)-1) << AW87XXX_PID_C2_AGC3_OUTPUT_POWER_START_BIT))
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#define AW87XXX_PID_C2_AGC3_OUTPUT_POWER_1P0W4_OHM (0)
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#define AW87XXX_PID_C2_AGC3_OUTPUT_POWER_1P0W4_OHM_VALUE \
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(AW87XXX_PID_C2_AGC3_OUTPUT_POWER_1P0W4_OHM << AW87XXX_PID_C2_AGC3_OUTPUT_POWER_START_BIT)
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#define AW87XXX_PID_C2_AGC3_OUTPUT_POWER_1P2W4_OHM (1)
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#define AW87XXX_PID_C2_AGC3_OUTPUT_POWER_1P2W4_OHM_VALUE \
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(AW87XXX_PID_C2_AGC3_OUTPUT_POWER_1P2W4_OHM << AW87XXX_PID_C2_AGC3_OUTPUT_POWER_START_BIT)
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#define AW87XXX_PID_C2_AGC3_OUTPUT_POWER_1P4W4_OHM (2)
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#define AW87XXX_PID_C2_AGC3_OUTPUT_POWER_1P4W4_OHM_VALUE \
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(AW87XXX_PID_C2_AGC3_OUTPUT_POWER_1P4W4_OHM << AW87XXX_PID_C2_AGC3_OUTPUT_POWER_START_BIT)
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#define AW87XXX_PID_C2_AGC3_OUTPUT_POWER_1P6W4_OHM (3)
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#define AW87XXX_PID_C2_AGC3_OUTPUT_POWER_1P6W4_OHM_VALUE \
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(AW87XXX_PID_C2_AGC3_OUTPUT_POWER_1P6W4_OHM << AW87XXX_PID_C2_AGC3_OUTPUT_POWER_START_BIT)
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#define AW87XXX_PID_C2_AGC3_OUTPUT_POWER_1P8W4_OHM (4)
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#define AW87XXX_PID_C2_AGC3_OUTPUT_POWER_1P8W4_OHM_VALUE \
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(AW87XXX_PID_C2_AGC3_OUTPUT_POWER_1P8W4_OHM << AW87XXX_PID_C2_AGC3_OUTPUT_POWER_START_BIT)
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#define AW87XXX_PID_C2_AGC3_OUTPUT_POWER_2P0W4_OHM (5)
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#define AW87XXX_PID_C2_AGC3_OUTPUT_POWER_2P0W4_OHM_VALUE \
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(AW87XXX_PID_C2_AGC3_OUTPUT_POWER_2P0W4_OHM << AW87XXX_PID_C2_AGC3_OUTPUT_POWER_START_BIT)
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#define AW87XXX_PID_C2_AGC3_OUTPUT_POWER_2P2W4_OHM (6)
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#define AW87XXX_PID_C2_AGC3_OUTPUT_POWER_2P2W4_OHM_VALUE \
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(AW87XXX_PID_C2_AGC3_OUTPUT_POWER_2P2W4_OHM << AW87XXX_PID_C2_AGC3_OUTPUT_POWER_START_BIT)
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#define AW87XXX_PID_C2_AGC3_OUTPUT_POWER_2P4W4_OHM (7)
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#define AW87XXX_PID_C2_AGC3_OUTPUT_POWER_2P4W4_OHM_VALUE \
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(AW87XXX_PID_C2_AGC3_OUTPUT_POWER_2P4W4_OHM << AW87XXX_PID_C2_AGC3_OUTPUT_POWER_START_BIT)
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#define AW87XXX_PID_C2_AGC3_OUTPUT_POWER_2P6W4_OHM (8)
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#define AW87XXX_PID_C2_AGC3_OUTPUT_POWER_2P6W4_OHM_VALUE \
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(AW87XXX_PID_C2_AGC3_OUTPUT_POWER_2P6W4_OHM << AW87XXX_PID_C2_AGC3_OUTPUT_POWER_START_BIT)
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#define AW87XXX_PID_C2_AGC3_OUTPUT_POWER_2P8W4_OHM (9)
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#define AW87XXX_PID_C2_AGC3_OUTPUT_POWER_2P8W4_OHM_VALUE \
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(AW87XXX_PID_C2_AGC3_OUTPUT_POWER_2P8W4_OHM << AW87XXX_PID_C2_AGC3_OUTPUT_POWER_START_BIT)
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#define AW87XXX_PID_C2_AGC3_OUTPUT_POWER_3P0W4_OHM (10)
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#define AW87XXX_PID_C2_AGC3_OUTPUT_POWER_3P0W4_OHM_VALUE \
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(AW87XXX_PID_C2_AGC3_OUTPUT_POWER_3P0W4_OHM << AW87XXX_PID_C2_AGC3_OUTPUT_POWER_START_BIT)
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#define AW87XXX_PID_C2_AGC3_OUTPUT_POWER_3P2W4_OHM (11)
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#define AW87XXX_PID_C2_AGC3_OUTPUT_POWER_3P2W4_OHM_VALUE \
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(AW87XXX_PID_C2_AGC3_OUTPUT_POWER_3P2W4_OHM << AW87XXX_PID_C2_AGC3_OUTPUT_POWER_START_BIT)
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#define AW87XXX_PID_C2_AGC3_OUTPUT_POWER_3P4W4_OHM (12)
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#define AW87XXX_PID_C2_AGC3_OUTPUT_POWER_3P4W4_OHM_VALUE \
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(AW87XXX_PID_C2_AGC3_OUTPUT_POWER_3P4W4_OHM << AW87XXX_PID_C2_AGC3_OUTPUT_POWER_START_BIT)
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#define AW87XXX_PID_C2_AGC3_OUTPUT_POWER_3P6W4_OHM (13)
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#define AW87XXX_PID_C2_AGC3_OUTPUT_POWER_3P6W4_OHM_VALUE \
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(AW87XXX_PID_C2_AGC3_OUTPUT_POWER_3P6W4_OHM << AW87XXX_PID_C2_AGC3_OUTPUT_POWER_START_BIT)
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#define AW87XXX_PID_C2_AGC3_OUTPUT_POWER_3P8W4_OHM (14)
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#define AW87XXX_PID_C2_AGC3_OUTPUT_POWER_3P8W4_OHM_VALUE \
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|
(AW87XXX_PID_C2_AGC3_OUTPUT_POWER_3P8W4_OHM << AW87XXX_PID_C2_AGC3_OUTPUT_POWER_START_BIT)
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#define AW87XXX_PID_C2_AGC3_OUTPUT_POWER_4P0W4_OHM (15)
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#define AW87XXX_PID_C2_AGC3_OUTPUT_POWER_4P0W4_OHM_VALUE \
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(AW87XXX_PID_C2_AGC3_OUTPUT_POWER_4P0W4_OHM << AW87XXX_PID_C2_AGC3_OUTPUT_POWER_START_BIT)
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#define AW87XXX_PID_C2_AGC3_OUTPUT_POWER_DEFAULT (0x3)
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#define AW87XXX_PID_C2_AGC3_OUTPUT_POWER_DEFAULT_VALUE \
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(AW87XXX_PID_C2_AGC3_OUTPUT_POWER_DEFAULT << AW87XXX_PID_C2_AGC3_OUTPUT_POWER_START_BIT)
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/* default value of AGC3PA (0x08) */
|
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/* #define AW87XXX_PID_C2_AGC3PA_DEFAULT (0x23) */
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|
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/* AGC3P (0x09) detail */
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/* AGC3_REL_TIME bit 7:5 (AGC3P 0x09) */
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#define AW87XXX_PID_C2_AGC3_REL_TIME_START_BIT (5)
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#define AW87XXX_PID_C2_AGC3_REL_TIME_BITS_LEN (3)
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#define AW87XXX_PID_C2_AGC3_REL_TIME_MASK \
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(~(((1<<AW87XXX_PID_C2_AGC3_REL_TIME_BITS_LEN)-1) << AW87XXX_PID_C2_AGC3_REL_TIME_START_BIT))
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#define AW87XXX_PID_C2_AGC3_REL_TIME_5P12MSDB (0)
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#define AW87XXX_PID_C2_AGC3_REL_TIME_5P12MSDB_VALUE \
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(AW87XXX_PID_C2_AGC3_REL_TIME_5P12MSDB << AW87XXX_PID_C2_AGC3_REL_TIME_START_BIT)
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#define AW87XXX_PID_C2_AGC3_REL_TIME_10P24MSDB (1)
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#define AW87XXX_PID_C2_AGC3_REL_TIME_10P24MSDB_VALUE \
|
|
(AW87XXX_PID_C2_AGC3_REL_TIME_10P24MSDB << AW87XXX_PID_C2_AGC3_REL_TIME_START_BIT)
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|
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#define AW87XXX_PID_C2_AGC3_REL_TIME_20P48MSDB (2)
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#define AW87XXX_PID_C2_AGC3_REL_TIME_20P48MSDB_VALUE \
|
|
(AW87XXX_PID_C2_AGC3_REL_TIME_20P48MSDB << AW87XXX_PID_C2_AGC3_REL_TIME_START_BIT)
|
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#define AW87XXX_PID_C2_AGC3_REL_TIME_40P96MSDB (3)
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#define AW87XXX_PID_C2_AGC3_REL_TIME_40P96MSDB_VALUE \
|
|
(AW87XXX_PID_C2_AGC3_REL_TIME_40P96MSDB << AW87XXX_PID_C2_AGC3_REL_TIME_START_BIT)
|
|
|
|
#define AW87XXX_PID_C2_AGC3_REL_TIME_81P92MSDB (4)
|
|
#define AW87XXX_PID_C2_AGC3_REL_TIME_81P92MSDB_VALUE \
|
|
(AW87XXX_PID_C2_AGC3_REL_TIME_81P92MSDB << AW87XXX_PID_C2_AGC3_REL_TIME_START_BIT)
|
|
|
|
#define AW87XXX_PID_C2_AGC3_REL_TIME_163P84MSDB (5)
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|
#define AW87XXX_PID_C2_AGC3_REL_TIME_163P84MSDB_VALUE \
|
|
(AW87XXX_PID_C2_AGC3_REL_TIME_163P84MSDB << AW87XXX_PID_C2_AGC3_REL_TIME_START_BIT)
|
|
|
|
#define AW87XXX_PID_C2_AGC3_REL_TIME_327P68MSDB (6)
|
|
#define AW87XXX_PID_C2_AGC3_REL_TIME_327P68MSDB_VALUE \
|
|
(AW87XXX_PID_C2_AGC3_REL_TIME_327P68MSDB << AW87XXX_PID_C2_AGC3_REL_TIME_START_BIT)
|
|
|
|
#define AW87XXX_PID_C2_AGC3_REL_TIME_655P36MSDB (7)
|
|
#define AW87XXX_PID_C2_AGC3_REL_TIME_655P36MSDB_VALUE \
|
|
(AW87XXX_PID_C2_AGC3_REL_TIME_655P36MSDB << AW87XXX_PID_C2_AGC3_REL_TIME_START_BIT)
|
|
|
|
#define AW87XXX_PID_C2_AGC3_REL_TIME_DEFAULT (0x2)
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|
#define AW87XXX_PID_C2_AGC3_REL_TIME_DEFAULT_VALUE \
|
|
(AW87XXX_PID_C2_AGC3_REL_TIME_DEFAULT << AW87XXX_PID_C2_AGC3_REL_TIME_START_BIT)
|
|
|
|
/* AGC3_ATT_TIME bit 4:2 (AGC3P 0x09) */
|
|
#define AW87XXX_PID_C2_AGC3_ATT_TIME_START_BIT (2)
|
|
#define AW87XXX_PID_C2_AGC3_ATT_TIME_BITS_LEN (3)
|
|
#define AW87XXX_PID_C2_AGC3_ATT_TIME_MASK \
|
|
(~(((1<<AW87XXX_PID_C2_AGC3_ATT_TIME_BITS_LEN)-1) << AW87XXX_PID_C2_AGC3_ATT_TIME_START_BIT))
|
|
|
|
#define AW87XXX_PID_C2_AGC3_ATT_TIME_1P28MSDB (0)
|
|
#define AW87XXX_PID_C2_AGC3_ATT_TIME_1P28MSDB_VALUE \
|
|
(AW87XXX_PID_C2_AGC3_ATT_TIME_1P28MSDB << AW87XXX_PID_C2_AGC3_ATT_TIME_START_BIT)
|
|
|
|
#define AW87XXX_PID_C2_AGC3_ATT_TIME_2P56MSDB (1)
|
|
#define AW87XXX_PID_C2_AGC3_ATT_TIME_2P56MSDB_VALUE \
|
|
(AW87XXX_PID_C2_AGC3_ATT_TIME_2P56MSDB << AW87XXX_PID_C2_AGC3_ATT_TIME_START_BIT)
|
|
|
|
#define AW87XXX_PID_C2_AGC3_ATT_TIME_10P24MSDB (2)
|
|
#define AW87XXX_PID_C2_AGC3_ATT_TIME_10P24MSDB_VALUE \
|
|
(AW87XXX_PID_C2_AGC3_ATT_TIME_10P24MSDB << AW87XXX_PID_C2_AGC3_ATT_TIME_START_BIT)
|
|
|
|
#define AW87XXX_PID_C2_AGC3_ATT_TIME_40P96MSDB (3)
|
|
#define AW87XXX_PID_C2_AGC3_ATT_TIME_40P96MSDB_VALUE \
|
|
(AW87XXX_PID_C2_AGC3_ATT_TIME_40P96MSDB << AW87XXX_PID_C2_AGC3_ATT_TIME_START_BIT)
|
|
|
|
#define AW87XXX_PID_C2_AGC3_ATT_TIME_82MSDB (4)
|
|
#define AW87XXX_PID_C2_AGC3_ATT_TIME_82MSDB_VALUE \
|
|
(AW87XXX_PID_C2_AGC3_ATT_TIME_82MSDB << AW87XXX_PID_C2_AGC3_ATT_TIME_START_BIT)
|
|
|
|
#define AW87XXX_PID_C2_AGC3_ATT_TIME_164MSDB (5)
|
|
#define AW87XXX_PID_C2_AGC3_ATT_TIME_164MSDB_VALUE \
|
|
(AW87XXX_PID_C2_AGC3_ATT_TIME_164MSDB << AW87XXX_PID_C2_AGC3_ATT_TIME_START_BIT)
|
|
|
|
#define AW87XXX_PID_C2_AGC3_ATT_TIME_328MSDB (6)
|
|
#define AW87XXX_PID_C2_AGC3_ATT_TIME_328MSDB_VALUE \
|
|
(AW87XXX_PID_C2_AGC3_ATT_TIME_328MSDB << AW87XXX_PID_C2_AGC3_ATT_TIME_START_BIT)
|
|
|
|
#define AW87XXX_PID_C2_AGC3_ATT_TIME_656MSDB (7)
|
|
#define AW87XXX_PID_C2_AGC3_ATT_TIME_656MSDB_VALUE \
|
|
(AW87XXX_PID_C2_AGC3_ATT_TIME_656MSDB << AW87XXX_PID_C2_AGC3_ATT_TIME_START_BIT)
|
|
|
|
#define AW87XXX_PID_C2_AGC3_ATT_TIME_DEFAULT (0x3)
|
|
#define AW87XXX_PID_C2_AGC3_ATT_TIME_DEFAULT_VALUE \
|
|
(AW87XXX_PID_C2_AGC3_ATT_TIME_DEFAULT << AW87XXX_PID_C2_AGC3_ATT_TIME_START_BIT)
|
|
|
|
/* AGC3_FIRST_ATT_TIME bit 1:0 (AGC3P 0x09) */
|
|
#define AW87XXX_PID_C2_AGC3_FIRST_ATT_TIME_START_BIT (0)
|
|
#define AW87XXX_PID_C2_AGC3_FIRST_ATT_TIME_BITS_LEN (2)
|
|
#define AW87XXX_PID_C2_AGC3_FIRST_ATT_TIME_MASK \
|
|
(~(((1<<AW87XXX_PID_C2_AGC3_FIRST_ATT_TIME_BITS_LEN)-1) << AW87XXX_PID_C2_AGC3_FIRST_ATT_TIME_START_BIT))
|
|
|
|
#define AW87XXX_PID_C2_AGC3_FIRST_ATT_TIME_5P12MS (0)
|
|
#define AW87XXX_PID_C2_AGC3_FIRST_ATT_TIME_5P12MS_VALUE \
|
|
(AW87XXX_PID_C2_AGC3_FIRST_ATT_TIME_5P12MS << AW87XXX_PID_C2_AGC3_FIRST_ATT_TIME_START_BIT)
|
|
|
|
#define AW87XXX_PID_C2_AGC3_FIRST_ATT_TIME_10P24MS (1)
|
|
#define AW87XXX_PID_C2_AGC3_FIRST_ATT_TIME_10P24MS_VALUE \
|
|
(AW87XXX_PID_C2_AGC3_FIRST_ATT_TIME_10P24MS << AW87XXX_PID_C2_AGC3_FIRST_ATT_TIME_START_BIT)
|
|
|
|
#define AW87XXX_PID_C2_AGC3_FIRST_ATT_TIME_20P48MS (2)
|
|
#define AW87XXX_PID_C2_AGC3_FIRST_ATT_TIME_20P48MS_VALUE \
|
|
(AW87XXX_PID_C2_AGC3_FIRST_ATT_TIME_20P48MS << AW87XXX_PID_C2_AGC3_FIRST_ATT_TIME_START_BIT)
|
|
|
|
#define AW87XXX_PID_C2_AGC3_FIRST_ATT_TIME_41MS (3)
|
|
#define AW87XXX_PID_C2_AGC3_FIRST_ATT_TIME_41MS_VALUE \
|
|
(AW87XXX_PID_C2_AGC3_FIRST_ATT_TIME_41MS << AW87XXX_PID_C2_AGC3_FIRST_ATT_TIME_START_BIT)
|
|
|
|
#define AW87XXX_PID_C2_AGC3_FIRST_ATT_TIME_DEFAULT (0x2)
|
|
#define AW87XXX_PID_C2_AGC3_FIRST_ATT_TIME_DEFAULT_VALUE \
|
|
(AW87XXX_PID_C2_AGC3_FIRST_ATT_TIME_DEFAULT << AW87XXX_PID_C2_AGC3_FIRST_ATT_TIME_START_BIT)
|
|
|
|
/* default value of AGC3P (0x09) */
|
|
/* #define AW87XXX_PID_C2_AGC3P_DEFAULT (0x4E) */
|
|
|
|
/* BATT_DECT (0x0A) detail */
|
|
/* VOS_GAIN bit 6:2 (BATT_DECT 0x0A) */
|
|
#define AW87XXX_PID_C2_VOS_GAIN_START_BIT (2)
|
|
#define AW87XXX_PID_C2_VOS_GAIN_BITS_LEN (5)
|
|
#define AW87XXX_PID_C2_VOS_GAIN_MASK \
|
|
(~(((1<<AW87XXX_PID_C2_VOS_GAIN_BITS_LEN)-1) << AW87XXX_PID_C2_VOS_GAIN_START_BIT))
|
|
|
|
#define AW87XXX_PID_C2_VOS_GAIN_RCVMODE1ENLN1PAGAIN000 (4)
|
|
#define AW87XXX_PID_C2_VOS_GAIN_RCVMODE1ENLN1PAGAIN000_VALUE \
|
|
(AW87XXX_PID_C2_VOS_GAIN_RCVMODE1ENLN1PAGAIN000 << AW87XXX_PID_C2_VOS_GAIN_START_BIT)
|
|
|
|
#define AW87XXX_PID_C2_VOS_GAIN_RCVMODE1ENLN0PAGAIN000 (8)
|
|
#define AW87XXX_PID_C2_VOS_GAIN_RCVMODE1ENLN0PAGAIN000_VALUE \
|
|
(AW87XXX_PID_C2_VOS_GAIN_RCVMODE1ENLN0PAGAIN000 << AW87XXX_PID_C2_VOS_GAIN_START_BIT)
|
|
|
|
#define AW87XXX_PID_C2_VOS_GAIN_RCVMODE1ENLN0PAGAIN001 (11)
|
|
#define AW87XXX_PID_C2_VOS_GAIN_RCVMODE1ENLN0PAGAIN001_VALUE \
|
|
(AW87XXX_PID_C2_VOS_GAIN_RCVMODE1ENLN0PAGAIN001 << AW87XXX_PID_C2_VOS_GAIN_START_BIT)
|
|
|
|
#define AW87XXX_PID_C2_VOS_GAIN_RCVMODE1ENLN0PAGAIN010 (16)
|
|
#define AW87XXX_PID_C2_VOS_GAIN_RCVMODE1ENLN0PAGAIN010_VALUE \
|
|
(AW87XXX_PID_C2_VOS_GAIN_RCVMODE1ENLN0PAGAIN010 << AW87XXX_PID_C2_VOS_GAIN_START_BIT)
|
|
|
|
#define AW87XXX_PID_C2_VOS_GAIN_RCVMODE1ENLN0PAGAIN011 (23)
|
|
#define AW87XXX_PID_C2_VOS_GAIN_RCVMODE1ENLN0PAGAIN011_VALUE \
|
|
(AW87XXX_PID_C2_VOS_GAIN_RCVMODE1ENLN0PAGAIN011 << AW87XXX_PID_C2_VOS_GAIN_START_BIT)
|
|
|
|
#define AW87XXX_PID_C2_VOS_GAIN_RCVMODE0PAGAIN011111 (31)
|
|
#define AW87XXX_PID_C2_VOS_GAIN_RCVMODE0PAGAIN011111_VALUE \
|
|
(AW87XXX_PID_C2_VOS_GAIN_RCVMODE0PAGAIN011111 << AW87XXX_PID_C2_VOS_GAIN_START_BIT)
|
|
|
|
#define AW87XXX_PID_C2_VOS_GAIN_DEFAULT (0x10)
|
|
#define AW87XXX_PID_C2_VOS_GAIN_DEFAULT_VALUE \
|
|
(AW87XXX_PID_C2_VOS_GAIN_DEFAULT << AW87XXX_PID_C2_VOS_GAIN_START_BIT)
|
|
|
|
/* REG_BOP_MD bit 1 (BATT_DECT 0x0A) */
|
|
#define AW87XXX_PID_C2_REG_BOP_MD_START_BIT (1)
|
|
#define AW87XXX_PID_C2_REG_BOP_MD_BITS_LEN (1)
|
|
#define AW87XXX_PID_C2_REG_BOP_MD_MASK \
|
|
(~(((1<<AW87XXX_PID_C2_REG_BOP_MD_BITS_LEN)-1) << AW87XXX_PID_C2_REG_BOP_MD_START_BIT))
|
|
|
|
#define AW87XXX_PID_C2_REG_BOP_MD_DISABLE_THE_DETECTION_OF_VDDABOVE3P4 (0)
|
|
#define AW87XXX_PID_C2_REG_BOP_MD_DISABLE_THE_DETECTION_OF_VDDABOVE3P4_VALUE \
|
|
(AW87XXX_PID_C2_REG_BOP_MD_DISABLE_THE_DETECTION_OF_VDDABOVE3P4 << AW87XXX_PID_C2_REG_BOP_MD_START_BIT)
|
|
|
|
#define AW87XXX_PID_C2_REG_BOP_MD_NORMAL (1)
|
|
#define AW87XXX_PID_C2_REG_BOP_MD_NORMAL_VALUE \
|
|
(AW87XXX_PID_C2_REG_BOP_MD_NORMAL << AW87XXX_PID_C2_REG_BOP_MD_START_BIT)
|
|
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|
#define AW87XXX_PID_C2_REG_BOP_MD_DEFAULT (0x1)
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#define AW87XXX_PID_C2_REG_BOP_MD_DEFAULT_VALUE \
|
|
(AW87XXX_PID_C2_REG_BOP_MD_DEFAULT << AW87XXX_PID_C2_REG_BOP_MD_START_BIT)
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/* REG_BOP_EN bit 0 (BATT_DECT 0x0A) */
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#define AW87XXX_PID_C2_REG_BOP_EN_START_BIT (0)
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#define AW87XXX_PID_C2_REG_BOP_EN_BITS_LEN (1)
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#define AW87XXX_PID_C2_REG_BOP_EN_MASK \
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(~(((1<<AW87XXX_PID_C2_REG_BOP_EN_BITS_LEN)-1) << AW87XXX_PID_C2_REG_BOP_EN_START_BIT))
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#define AW87XXX_PID_C2_REG_BOP_EN_DEFAULT (0x0)
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#define AW87XXX_PID_C2_REG_BOP_EN_DEFAULT_VALUE \
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(AW87XXX_PID_C2_REG_BOP_EN_DEFAULT << AW87XXX_PID_C2_REG_BOP_EN_START_BIT)
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/* default value of BATT_DECT (0x0A) */
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/* #define AW87XXX_PID_C2_BATT_DECT_DEFAULT (0x42) */
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/* BSTOUT (0x0B) detail */
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/* REG_VCM_SEL bit 7 (BSTOUT 0x0B) */
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#define AW87XXX_PID_C2_REG_VCM_SEL_START_BIT (7)
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#define AW87XXX_PID_C2_REG_VCM_SEL_BITS_LEN (1)
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#define AW87XXX_PID_C2_REG_VCM_SEL_MASK \
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(~(((1<<AW87XXX_PID_C2_REG_VCM_SEL_BITS_LEN)-1) << AW87XXX_PID_C2_REG_VCM_SEL_START_BIT))
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#define AW87XXX_PID_C2_REG_VCM_SEL_VCM_FROM_BIAS (0)
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#define AW87XXX_PID_C2_REG_VCM_SEL_VCM_FROM_BIAS_VALUE \
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(AW87XXX_PID_C2_REG_VCM_SEL_VCM_FROM_BIAS << AW87XXX_PID_C2_REG_VCM_SEL_START_BIT)
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#define AW87XXX_PID_C2_REG_VCM_SEL_VCM_FROM_PREAMP (1)
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#define AW87XXX_PID_C2_REG_VCM_SEL_VCM_FROM_PREAMP_VALUE \
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(AW87XXX_PID_C2_REG_VCM_SEL_VCM_FROM_PREAMP << AW87XXX_PID_C2_REG_VCM_SEL_START_BIT)
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#define AW87XXX_PID_C2_REG_VCM_SEL_DEFAULT (0x0)
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#define AW87XXX_PID_C2_REG_VCM_SEL_DEFAULT_VALUE \
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(AW87XXX_PID_C2_REG_VCM_SEL_DEFAULT << AW87XXX_PID_C2_REG_VCM_SEL_START_BIT)
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/* BOP_VP_SEL bit 6:5 (BSTOUT 0x0B) */
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#define AW87XXX_PID_C2_BOP_VP_SEL_START_BIT (5)
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#define AW87XXX_PID_C2_BOP_VP_SEL_BITS_LEN (2)
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#define AW87XXX_PID_C2_BOP_VP_SEL_MASK \
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(~(((1<<AW87XXX_PID_C2_BOP_VP_SEL_BITS_LEN)-1) << AW87XXX_PID_C2_BOP_VP_SEL_START_BIT))
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#define AW87XXX_PID_C2_BOP_VP_SEL_SMALLEST_VTH (0)
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#define AW87XXX_PID_C2_BOP_VP_SEL_SMALLEST_VTH_VALUE \
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(AW87XXX_PID_C2_BOP_VP_SEL_SMALLEST_VTH << AW87XXX_PID_C2_BOP_VP_SEL_START_BIT)
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#define AW87XXX_PID_C2_BOP_VP_SEL_LARGER_VTH (1)
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#define AW87XXX_PID_C2_BOP_VP_SEL_LARGER_VTH_VALUE \
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(AW87XXX_PID_C2_BOP_VP_SEL_LARGER_VTH << AW87XXX_PID_C2_BOP_VP_SEL_START_BIT)
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#define AW87XXX_PID_C2_BOP_VP_SEL_LARGEST_VTH (2)
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#define AW87XXX_PID_C2_BOP_VP_SEL_LARGEST_VTH_VALUE \
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(AW87XXX_PID_C2_BOP_VP_SEL_LARGEST_VTH << AW87XXX_PID_C2_BOP_VP_SEL_START_BIT)
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#define AW87XXX_PID_C2_BOP_VP_SEL_DEFAULT (0x1)
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#define AW87XXX_PID_C2_BOP_VP_SEL_DEFAULT_VALUE \
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(AW87XXX_PID_C2_BOP_VP_SEL_DEFAULT << AW87XXX_PID_C2_BOP_VP_SEL_START_BIT)
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/* HEAD_ROOM_VTH0 bit 4 (BSTOUT 0x0B) */
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|
#define AW87XXX_PID_C2_HEAD_ROOM_VTH0_START_BIT (4)
|
|
#define AW87XXX_PID_C2_HEAD_ROOM_VTH0_BITS_LEN (1)
|
|
#define AW87XXX_PID_C2_HEAD_ROOM_VTH0_MASK \
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|
(~(((1<<AW87XXX_PID_C2_HEAD_ROOM_VTH0_BITS_LEN)-1) << AW87XXX_PID_C2_HEAD_ROOM_VTH0_START_BIT))
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#define AW87XXX_PID_C2_HEAD_ROOM_VTH0_LARGER_LEVEL (0)
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#define AW87XXX_PID_C2_HEAD_ROOM_VTH0_LARGER_LEVEL_VALUE \
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(AW87XXX_PID_C2_HEAD_ROOM_VTH0_LARGER_LEVEL << AW87XXX_PID_C2_HEAD_ROOM_VTH0_START_BIT)
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#define AW87XXX_PID_C2_HEAD_ROOM_VTH0_SMALLER_LEVEL (1)
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|
#define AW87XXX_PID_C2_HEAD_ROOM_VTH0_SMALLER_LEVEL_VALUE \
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|
(AW87XXX_PID_C2_HEAD_ROOM_VTH0_SMALLER_LEVEL << AW87XXX_PID_C2_HEAD_ROOM_VTH0_START_BIT)
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|
|
|
#define AW87XXX_PID_C2_HEAD_ROOM_VTH0_DEFAULT (0x0)
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|
#define AW87XXX_PID_C2_HEAD_ROOM_VTH0_DEFAULT_VALUE \
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|
(AW87XXX_PID_C2_HEAD_ROOM_VTH0_DEFAULT << AW87XXX_PID_C2_HEAD_ROOM_VTH0_START_BIT)
|
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|
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/* MPDVTH bit 3:2 (BSTOUT 0x0B) */
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|
#define AW87XXX_PID_C2_MPDVTH_START_BIT (2)
|
|
#define AW87XXX_PID_C2_MPDVTH_BITS_LEN (2)
|
|
#define AW87XXX_PID_C2_MPDVTH_MASK \
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(~(((1<<AW87XXX_PID_C2_MPDVTH_BITS_LEN)-1) << AW87XXX_PID_C2_MPDVTH_START_BIT))
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|
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|
#define AW87XXX_PID_C2_MPDVTH_VTH60MV_VTHHYS40MV (0)
|
|
#define AW87XXX_PID_C2_MPDVTH_VTH60MV_VTHHYS40MV_VALUE \
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|
(AW87XXX_PID_C2_MPDVTH_VTH60MV_VTHHYS40MV << AW87XXX_PID_C2_MPDVTH_START_BIT)
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|
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|
#define AW87XXX_PID_C2_MPDVTH_VTH70MV_VTHHYS50MV (1)
|
|
#define AW87XXX_PID_C2_MPDVTH_VTH70MV_VTHHYS50MV_VALUE \
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|
(AW87XXX_PID_C2_MPDVTH_VTH70MV_VTHHYS50MV << AW87XXX_PID_C2_MPDVTH_START_BIT)
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|
|
|
#define AW87XXX_PID_C2_MPDVTH_VTH80MV_VTHHYS60MVDEFAULT (2)
|
|
#define AW87XXX_PID_C2_MPDVTH_VTH80MV_VTHHYS60MVDEFAULT_VALUE \
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|
(AW87XXX_PID_C2_MPDVTH_VTH80MV_VTHHYS60MVDEFAULT << AW87XXX_PID_C2_MPDVTH_START_BIT)
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|
|
|
#define AW87XXX_PID_C2_MPDVTH_VTH90MV_VTHHYS115MV (3)
|
|
#define AW87XXX_PID_C2_MPDVTH_VTH90MV_VTHHYS115MV_VALUE \
|
|
(AW87XXX_PID_C2_MPDVTH_VTH90MV_VTHHYS115MV << AW87XXX_PID_C2_MPDVTH_START_BIT)
|
|
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|
#define AW87XXX_PID_C2_MPDVTH_DEFAULT (0x2)
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|
#define AW87XXX_PID_C2_MPDVTH_DEFAULT_VALUE \
|
|
(AW87XXX_PID_C2_MPDVTH_DEFAULT << AW87XXX_PID_C2_MPDVTH_START_BIT)
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|
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|
/* EN_MPD bit 1 (BSTOUT 0x0B) */
|
|
#define AW87XXX_PID_C2_EN_MPD_START_BIT (1)
|
|
#define AW87XXX_PID_C2_EN_MPD_BITS_LEN (1)
|
|
#define AW87XXX_PID_C2_EN_MPD_MASK \
|
|
(~(((1<<AW87XXX_PID_C2_EN_MPD_BITS_LEN)-1) << AW87XXX_PID_C2_EN_MPD_START_BIT))
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|
|
|
#define AW87XXX_PID_C2_EN_MPD_MPD_MOS_OF_POWERSTAGE_DIVISION_MODULE_DISABLE (0)
|
|
#define AW87XXX_PID_C2_EN_MPD_MPD_MOS_OF_POWERSTAGE_DIVISION_MODULE_DISABLE_VALUE \
|
|
(AW87XXX_PID_C2_EN_MPD_MPD_MOS_OF_POWERSTAGE_DIVISION_MODULE_DISABLE << AW87XXX_PID_C2_EN_MPD_START_BIT)
|
|
|
|
#define AW87XXX_PID_C2_EN_MPD_MPD_MOS_OF_POWERSTAGE_DIVISION_MODULE_ENABLE (1)
|
|
#define AW87XXX_PID_C2_EN_MPD_MPD_MOS_OF_POWERSTAGE_DIVISION_MODULE_ENABLE_VALUE \
|
|
(AW87XXX_PID_C2_EN_MPD_MPD_MOS_OF_POWERSTAGE_DIVISION_MODULE_ENABLE << AW87XXX_PID_C2_EN_MPD_START_BIT)
|
|
|
|
#define AW87XXX_PID_C2_EN_MPD_DEFAULT (0x1)
|
|
#define AW87XXX_PID_C2_EN_MPD_DEFAULT_VALUE \
|
|
(AW87XXX_PID_C2_EN_MPD_DEFAULT << AW87XXX_PID_C2_EN_MPD_START_BIT)
|
|
|
|
/* EN_ADAP_VTH0 bit 0 (BSTOUT 0x0B) */
|
|
#define AW87XXX_PID_C2_EN_ADAP_VTH0_START_BIT (0)
|
|
#define AW87XXX_PID_C2_EN_ADAP_VTH0_BITS_LEN (1)
|
|
#define AW87XXX_PID_C2_EN_ADAP_VTH0_MASK \
|
|
(~(((1<<AW87XXX_PID_C2_EN_ADAP_VTH0_BITS_LEN)-1) << AW87XXX_PID_C2_EN_ADAP_VTH0_START_BIT))
|
|
|
|
#define AW87XXX_PID_C2_EN_ADAP_VTH0_ADJ_ADAPVTH0_DISABLE (0)
|
|
#define AW87XXX_PID_C2_EN_ADAP_VTH0_ADJ_ADAPVTH0_DISABLE_VALUE \
|
|
(AW87XXX_PID_C2_EN_ADAP_VTH0_ADJ_ADAPVTH0_DISABLE << AW87XXX_PID_C2_EN_ADAP_VTH0_START_BIT)
|
|
|
|
#define AW87XXX_PID_C2_EN_ADAP_VTH0_ADJ_ADAPVTH0_ENABLE (1)
|
|
#define AW87XXX_PID_C2_EN_ADAP_VTH0_ADJ_ADAPVTH0_ENABLE_VALUE \
|
|
(AW87XXX_PID_C2_EN_ADAP_VTH0_ADJ_ADAPVTH0_ENABLE << AW87XXX_PID_C2_EN_ADAP_VTH0_START_BIT)
|
|
|
|
#define AW87XXX_PID_C2_EN_ADAP_VTH0_DEFAULT (0x1)
|
|
#define AW87XXX_PID_C2_EN_ADAP_VTH0_DEFAULT_VALUE \
|
|
(AW87XXX_PID_C2_EN_ADAP_VTH0_DEFAULT << AW87XXX_PID_C2_EN_ADAP_VTH0_START_BIT)
|
|
|
|
/* default value of BSTOUT (0x0B) */
|
|
/* #define AW87XXX_PID_C2_BSTOUT_DEFAULT (0x2B) */
|
|
|
|
/* SYSST (0x59) detail */
|
|
/* UVLO_S bit 7 (SYSST 0x59) */
|
|
#define AW87XXX_PID_C2_UVLO_S_START_BIT (7)
|
|
#define AW87XXX_PID_C2_UVLO_S_BITS_LEN (1)
|
|
#define AW87XXX_PID_C2_UVLO_S_MASK \
|
|
(~(((1<<AW87XXX_PID_C2_UVLO_S_BITS_LEN)-1) << AW87XXX_PID_C2_UVLO_S_START_BIT))
|
|
|
|
#define AW87XXX_PID_C2_UVLO_S_NORMAL_OPERATION (0)
|
|
#define AW87XXX_PID_C2_UVLO_S_NORMAL_OPERATION_VALUE \
|
|
(AW87XXX_PID_C2_UVLO_S_NORMAL_OPERATION << AW87XXX_PID_C2_UVLO_S_START_BIT)
|
|
|
|
#define AW87XXX_PID_C2_UVLO_S_VBAT_UNDER_VOLTAGE (1)
|
|
#define AW87XXX_PID_C2_UVLO_S_VBAT_UNDER_VOLTAGE_VALUE \
|
|
(AW87XXX_PID_C2_UVLO_S_VBAT_UNDER_VOLTAGE << AW87XXX_PID_C2_UVLO_S_START_BIT)
|
|
|
|
#define AW87XXX_PID_C2_UVLO_S_DEFAULT (0x1)
|
|
#define AW87XXX_PID_C2_UVLO_S_DEFAULT_VALUE \
|
|
(AW87XXX_PID_C2_UVLO_S_DEFAULT << AW87XXX_PID_C2_UVLO_S_START_BIT)
|
|
|
|
/* BST_OVP_S bit 5 (SYSST 0x59) */
|
|
#define AW87XXX_PID_C2_BST_OVP_S_START_BIT (5)
|
|
#define AW87XXX_PID_C2_BST_OVP_S_BITS_LEN (1)
|
|
#define AW87XXX_PID_C2_BST_OVP_S_MASK \
|
|
(~(((1<<AW87XXX_PID_C2_BST_OVP_S_BITS_LEN)-1) << AW87XXX_PID_C2_BST_OVP_S_START_BIT))
|
|
|
|
#define AW87XXX_PID_C2_BST_OVP_S_NORMAL_OPERATION (0)
|
|
#define AW87XXX_PID_C2_BST_OVP_S_NORMAL_OPERATION_VALUE \
|
|
(AW87XXX_PID_C2_BST_OVP_S_NORMAL_OPERATION << AW87XXX_PID_C2_BST_OVP_S_START_BIT)
|
|
|
|
#define AW87XXX_PID_C2_BST_OVP_S_BOOST_OVER_VOLTAGE_PROTECTION (1)
|
|
#define AW87XXX_PID_C2_BST_OVP_S_BOOST_OVER_VOLTAGE_PROTECTION_VALUE \
|
|
(AW87XXX_PID_C2_BST_OVP_S_BOOST_OVER_VOLTAGE_PROTECTION << AW87XXX_PID_C2_BST_OVP_S_START_BIT)
|
|
|
|
#define AW87XXX_PID_C2_BST_OVP_S_DEFAULT (0x1)
|
|
#define AW87XXX_PID_C2_BST_OVP_S_DEFAULT_VALUE \
|
|
(AW87XXX_PID_C2_BST_OVP_S_DEFAULT << AW87XXX_PID_C2_BST_OVP_S_START_BIT)
|
|
|
|
/* BST_OVP2_S bit 4 (SYSST 0x59) */
|
|
#define AW87XXX_PID_C2_BST_OVP2_S_START_BIT (4)
|
|
#define AW87XXX_PID_C2_BST_OVP2_S_BITS_LEN (1)
|
|
#define AW87XXX_PID_C2_BST_OVP2_S_MASK \
|
|
(~(((1<<AW87XXX_PID_C2_BST_OVP2_S_BITS_LEN)-1) << AW87XXX_PID_C2_BST_OVP2_S_START_BIT))
|
|
|
|
#define AW87XXX_PID_C2_BST_OVP2_S_NORMAL_OPERATION (0)
|
|
#define AW87XXX_PID_C2_BST_OVP2_S_NORMAL_OPERATION_VALUE \
|
|
(AW87XXX_PID_C2_BST_OVP2_S_NORMAL_OPERATION << AW87XXX_PID_C2_BST_OVP2_S_START_BIT)
|
|
|
|
#define AW87XXX_PID_C2_BST_OVP2_S_BOOST_HEAVY_LOAD_PROTECTION_DETECTED (1)
|
|
#define AW87XXX_PID_C2_BST_OVP2_S_BOOST_HEAVY_LOAD_PROTECTION_DETECTED_VALUE \
|
|
(AW87XXX_PID_C2_BST_OVP2_S_BOOST_HEAVY_LOAD_PROTECTION_DETECTED << AW87XXX_PID_C2_BST_OVP2_S_START_BIT)
|
|
|
|
#define AW87XXX_PID_C2_BST_OVP2_S_DEFAULT (0x1)
|
|
#define AW87XXX_PID_C2_BST_OVP2_S_DEFAULT_VALUE \
|
|
(AW87XXX_PID_C2_BST_OVP2_S_DEFAULT << AW87XXX_PID_C2_BST_OVP2_S_START_BIT)
|
|
|
|
/* BST_SCP_S bit 3 (SYSST 0x59) */
|
|
#define AW87XXX_PID_C2_BST_SCP_S_START_BIT (3)
|
|
#define AW87XXX_PID_C2_BST_SCP_S_BITS_LEN (1)
|
|
#define AW87XXX_PID_C2_BST_SCP_S_MASK \
|
|
(~(((1<<AW87XXX_PID_C2_BST_SCP_S_BITS_LEN)-1) << AW87XXX_PID_C2_BST_SCP_S_START_BIT))
|
|
|
|
#define AW87XXX_PID_C2_BST_SCP_S_NORMAL_OPERATION (0)
|
|
#define AW87XXX_PID_C2_BST_SCP_S_NORMAL_OPERATION_VALUE \
|
|
(AW87XXX_PID_C2_BST_SCP_S_NORMAL_OPERATION << AW87XXX_PID_C2_BST_SCP_S_START_BIT)
|
|
|
|
#define AW87XXX_PID_C2_BST_SCP_S_BOOST_SHORT_CIRCUIT_PROTECTION_DETECTED (1)
|
|
#define AW87XXX_PID_C2_BST_SCP_S_BOOST_SHORT_CIRCUIT_PROTECTION_DETECTED_VALUE \
|
|
(AW87XXX_PID_C2_BST_SCP_S_BOOST_SHORT_CIRCUIT_PROTECTION_DETECTED << AW87XXX_PID_C2_BST_SCP_S_START_BIT)
|
|
|
|
#define AW87XXX_PID_C2_BST_SCP_S_DEFAULT (0x1)
|
|
#define AW87XXX_PID_C2_BST_SCP_S_DEFAULT_VALUE \
|
|
(AW87XXX_PID_C2_BST_SCP_S_DEFAULT << AW87XXX_PID_C2_BST_SCP_S_START_BIT)
|
|
|
|
/* PA_OC_S bit 2 (SYSST 0x59) */
|
|
#define AW87XXX_PID_C2_PA_OC_S_START_BIT (2)
|
|
#define AW87XXX_PID_C2_PA_OC_S_BITS_LEN (1)
|
|
#define AW87XXX_PID_C2_PA_OC_S_MASK \
|
|
(~(((1<<AW87XXX_PID_C2_PA_OC_S_BITS_LEN)-1) << AW87XXX_PID_C2_PA_OC_S_START_BIT))
|
|
|
|
#define AW87XXX_PID_C2_PA_OC_S_NORMAL_OPERATION (0)
|
|
#define AW87XXX_PID_C2_PA_OC_S_NORMAL_OPERATION_VALUE \
|
|
(AW87XXX_PID_C2_PA_OC_S_NORMAL_OPERATION << AW87XXX_PID_C2_PA_OC_S_START_BIT)
|
|
|
|
#define AW87XXX_PID_C2_PA_OC_S_PA_OVER_CURRENT_PROTECTION_DETECTED (1)
|
|
#define AW87XXX_PID_C2_PA_OC_S_PA_OVER_CURRENT_PROTECTION_DETECTED_VALUE \
|
|
(AW87XXX_PID_C2_PA_OC_S_PA_OVER_CURRENT_PROTECTION_DETECTED << AW87XXX_PID_C2_PA_OC_S_START_BIT)
|
|
|
|
#define AW87XXX_PID_C2_PA_OC_S_DEFAULT (0x1)
|
|
#define AW87XXX_PID_C2_PA_OC_S_DEFAULT_VALUE \
|
|
(AW87XXX_PID_C2_PA_OC_S_DEFAULT << AW87XXX_PID_C2_PA_OC_S_START_BIT)
|
|
|
|
/* OT160_S bit 1 (SYSST 0x59) */
|
|
#define AW87XXX_PID_C2_OT160_S_START_BIT (1)
|
|
#define AW87XXX_PID_C2_OT160_S_BITS_LEN (1)
|
|
#define AW87XXX_PID_C2_OT160_S_MASK \
|
|
(~(((1<<AW87XXX_PID_C2_OT160_S_BITS_LEN)-1) << AW87XXX_PID_C2_OT160_S_START_BIT))
|
|
|
|
#define AW87XXX_PID_C2_OT160_S_NORMAL_OPERATION (0)
|
|
#define AW87XXX_PID_C2_OT160_S_NORMAL_OPERATION_VALUE \
|
|
(AW87XXX_PID_C2_OT160_S_NORMAL_OPERATION << AW87XXX_PID_C2_OT160_S_START_BIT)
|
|
|
|
#define AW87XXX_PID_C2_OT160_S_PA_OVER_TEMPRETURE_PROTECTION_DETECTED (1)
|
|
#define AW87XXX_PID_C2_OT160_S_PA_OVER_TEMPRETURE_PROTECTION_DETECTED_VALUE \
|
|
(AW87XXX_PID_C2_OT160_S_PA_OVER_TEMPRETURE_PROTECTION_DETECTED << AW87XXX_PID_C2_OT160_S_START_BIT)
|
|
|
|
#define AW87XXX_PID_C2_OT160_S_DEFAULT (0x1)
|
|
#define AW87XXX_PID_C2_OT160_S_DEFAULT_VALUE \
|
|
(AW87XXX_PID_C2_OT160_S_DEFAULT << AW87XXX_PID_C2_OT160_S_START_BIT)
|
|
|
|
/* ADP_BOOST_S bit 0 (SYSST 0x59) */
|
|
#define AW87XXX_PID_C2_ADP_BOOST_S_START_BIT (0)
|
|
#define AW87XXX_PID_C2_ADP_BOOST_S_BITS_LEN (1)
|
|
#define AW87XXX_PID_C2_ADP_BOOST_S_MASK \
|
|
(~(((1<<AW87XXX_PID_C2_ADP_BOOST_S_BITS_LEN)-1) << AW87XXX_PID_C2_ADP_BOOST_S_START_BIT))
|
|
|
|
#define AW87XXX_PID_C2_ADP_BOOST_S_DIRECT_MODE (0)
|
|
#define AW87XXX_PID_C2_ADP_BOOST_S_DIRECT_MODE_VALUE \
|
|
(AW87XXX_PID_C2_ADP_BOOST_S_DIRECT_MODE << AW87XXX_PID_C2_ADP_BOOST_S_START_BIT)
|
|
|
|
#define AW87XXX_PID_C2_ADP_BOOST_S_BOOST_MODE (1)
|
|
#define AW87XXX_PID_C2_ADP_BOOST_S_BOOST_MODE_VALUE \
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(AW87XXX_PID_C2_ADP_BOOST_S_BOOST_MODE << AW87XXX_PID_C2_ADP_BOOST_S_START_BIT)
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#define AW87XXX_PID_C2_ADP_BOOST_S_DEFAULT (0x0)
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#define AW87XXX_PID_C2_ADP_BOOST_S_DEFAULT_VALUE \
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(AW87XXX_PID_C2_ADP_BOOST_S_DEFAULT << AW87XXX_PID_C2_ADP_BOOST_S_START_BIT)
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/* default value of SYSST (0x59) */
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/* #define AW87XXX_PID_C2_SYSST_DEFAULT (0xBE) */
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/* SYSINT (0x60) detail */
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/* UVLO_I bit 7 (SYSINT 0x60) */
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#define AW87XXX_PID_C2_UVLO_I_START_BIT (7)
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#define AW87XXX_PID_C2_UVLO_I_BITS_LEN (1)
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#define AW87XXX_PID_C2_UVLO_I_MASK \
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(~(((1<<AW87XXX_PID_C2_UVLO_I_BITS_LEN)-1) << AW87XXX_PID_C2_UVLO_I_START_BIT))
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#define AW87XXX_PID_C2_UVLO_I_NORMAL_OPERATION (0)
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#define AW87XXX_PID_C2_UVLO_I_NORMAL_OPERATION_VALUE \
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(AW87XXX_PID_C2_UVLO_I_NORMAL_OPERATION << AW87XXX_PID_C2_UVLO_I_START_BIT)
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#define AW87XXX_PID_C2_UVLO_I_VBAT_UNDER_VOLTAGE (1)
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#define AW87XXX_PID_C2_UVLO_I_VBAT_UNDER_VOLTAGE_VALUE \
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(AW87XXX_PID_C2_UVLO_I_VBAT_UNDER_VOLTAGE << AW87XXX_PID_C2_UVLO_I_START_BIT)
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#define AW87XXX_PID_C2_UVLO_I_DEFAULT (0x1)
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#define AW87XXX_PID_C2_UVLO_I_DEFAULT_VALUE \
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(AW87XXX_PID_C2_UVLO_I_DEFAULT << AW87XXX_PID_C2_UVLO_I_START_BIT)
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/* BST_OVP_I bit 5 (SYSINT 0x60) */
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#define AW87XXX_PID_C2_BST_OVP_I_START_BIT (5)
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#define AW87XXX_PID_C2_BST_OVP_I_BITS_LEN (1)
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#define AW87XXX_PID_C2_BST_OVP_I_MASK \
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(~(((1<<AW87XXX_PID_C2_BST_OVP_I_BITS_LEN)-1) << AW87XXX_PID_C2_BST_OVP_I_START_BIT))
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#define AW87XXX_PID_C2_BST_OVP_I_NORMAL_OPERATION (0)
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#define AW87XXX_PID_C2_BST_OVP_I_NORMAL_OPERATION_VALUE \
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(AW87XXX_PID_C2_BST_OVP_I_NORMAL_OPERATION << AW87XXX_PID_C2_BST_OVP_I_START_BIT)
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#define AW87XXX_PID_C2_BST_OVP_I_BOOST_OVER_VOLTAGE_PROTECTION (1)
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#define AW87XXX_PID_C2_BST_OVP_I_BOOST_OVER_VOLTAGE_PROTECTION_VALUE \
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(AW87XXX_PID_C2_BST_OVP_I_BOOST_OVER_VOLTAGE_PROTECTION << AW87XXX_PID_C2_BST_OVP_I_START_BIT)
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#define AW87XXX_PID_C2_BST_OVP_I_DEFAULT (0x1)
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#define AW87XXX_PID_C2_BST_OVP_I_DEFAULT_VALUE \
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(AW87XXX_PID_C2_BST_OVP_I_DEFAULT << AW87XXX_PID_C2_BST_OVP_I_START_BIT)
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/* BST_OVP2_I bit 4 (SYSINT 0x60) */
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#define AW87XXX_PID_C2_BST_OVP2_I_START_BIT (4)
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#define AW87XXX_PID_C2_BST_OVP2_I_BITS_LEN (1)
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#define AW87XXX_PID_C2_BST_OVP2_I_MASK \
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(~(((1<<AW87XXX_PID_C2_BST_OVP2_I_BITS_LEN)-1) << AW87XXX_PID_C2_BST_OVP2_I_START_BIT))
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#define AW87XXX_PID_C2_BST_OVP2_I_NORMAL_OPERATION (0)
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#define AW87XXX_PID_C2_BST_OVP2_I_NORMAL_OPERATION_VALUE \
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(AW87XXX_PID_C2_BST_OVP2_I_NORMAL_OPERATION << AW87XXX_PID_C2_BST_OVP2_I_START_BIT)
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#define AW87XXX_PID_C2_BST_OVP2_I_BOOST_HEAVY_LOAD_PROTECTION_DETECTED (1)
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#define AW87XXX_PID_C2_BST_OVP2_I_BOOST_HEAVY_LOAD_PROTECTION_DETECTED_VALUE \
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(AW87XXX_PID_C2_BST_OVP2_I_BOOST_HEAVY_LOAD_PROTECTION_DETECTED << AW87XXX_PID_C2_BST_OVP2_I_START_BIT)
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#define AW87XXX_PID_C2_BST_OVP2_I_DEFAULT (0x1)
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#define AW87XXX_PID_C2_BST_OVP2_I_DEFAULT_VALUE \
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(AW87XXX_PID_C2_BST_OVP2_I_DEFAULT << AW87XXX_PID_C2_BST_OVP2_I_START_BIT)
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/* BST_SCP_I bit 3 (SYSINT 0x60) */
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#define AW87XXX_PID_C2_BST_SCP_I_START_BIT (3)
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#define AW87XXX_PID_C2_BST_SCP_I_BITS_LEN (1)
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#define AW87XXX_PID_C2_BST_SCP_I_MASK \
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(~(((1<<AW87XXX_PID_C2_BST_SCP_I_BITS_LEN)-1) << AW87XXX_PID_C2_BST_SCP_I_START_BIT))
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#define AW87XXX_PID_C2_BST_SCP_I_NORMAL_OPERATION (0)
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#define AW87XXX_PID_C2_BST_SCP_I_NORMAL_OPERATION_VALUE \
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(AW87XXX_PID_C2_BST_SCP_I_NORMAL_OPERATION << AW87XXX_PID_C2_BST_SCP_I_START_BIT)
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#define AW87XXX_PID_C2_BST_SCP_I_BOOST_SHORT_CIRCUIT_PROTECTION_DETECTED (1)
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#define AW87XXX_PID_C2_BST_SCP_I_BOOST_SHORT_CIRCUIT_PROTECTION_DETECTED_VALUE \
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(AW87XXX_PID_C2_BST_SCP_I_BOOST_SHORT_CIRCUIT_PROTECTION_DETECTED << AW87XXX_PID_C2_BST_SCP_I_START_BIT)
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#define AW87XXX_PID_C2_BST_SCP_I_DEFAULT (0x1)
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#define AW87XXX_PID_C2_BST_SCP_I_DEFAULT_VALUE \
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(AW87XXX_PID_C2_BST_SCP_I_DEFAULT << AW87XXX_PID_C2_BST_SCP_I_START_BIT)
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/* PA_OC_I bit 2 (SYSINT 0x60) */
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#define AW87XXX_PID_C2_PA_OC_I_START_BIT (2)
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#define AW87XXX_PID_C2_PA_OC_I_BITS_LEN (1)
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#define AW87XXX_PID_C2_PA_OC_I_MASK \
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(~(((1<<AW87XXX_PID_C2_PA_OC_I_BITS_LEN)-1) << AW87XXX_PID_C2_PA_OC_I_START_BIT))
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#define AW87XXX_PID_C2_PA_OC_I_NORMAL_OPERATION (0)
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#define AW87XXX_PID_C2_PA_OC_I_NORMAL_OPERATION_VALUE \
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(AW87XXX_PID_C2_PA_OC_I_NORMAL_OPERATION << AW87XXX_PID_C2_PA_OC_I_START_BIT)
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#define AW87XXX_PID_C2_PA_OC_I_PA_OVER_CURRENT_PROTECTION_DETECTED (1)
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#define AW87XXX_PID_C2_PA_OC_I_PA_OVER_CURRENT_PROTECTION_DETECTED_VALUE \
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(AW87XXX_PID_C2_PA_OC_I_PA_OVER_CURRENT_PROTECTION_DETECTED << AW87XXX_PID_C2_PA_OC_I_START_BIT)
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#define AW87XXX_PID_C2_PA_OC_I_DEFAULT (0x1)
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#define AW87XXX_PID_C2_PA_OC_I_DEFAULT_VALUE \
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(AW87XXX_PID_C2_PA_OC_I_DEFAULT << AW87XXX_PID_C2_PA_OC_I_START_BIT)
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/* OT160_I bit 1 (SYSINT 0x60) */
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#define AW87XXX_PID_C2_OT160_I_START_BIT (1)
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#define AW87XXX_PID_C2_OT160_I_BITS_LEN (1)
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#define AW87XXX_PID_C2_OT160_I_MASK \
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(~(((1<<AW87XXX_PID_C2_OT160_I_BITS_LEN)-1) << AW87XXX_PID_C2_OT160_I_START_BIT))
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#define AW87XXX_PID_C2_OT160_I_NORMAL_OPERATION (0)
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#define AW87XXX_PID_C2_OT160_I_NORMAL_OPERATION_VALUE \
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(AW87XXX_PID_C2_OT160_I_NORMAL_OPERATION << AW87XXX_PID_C2_OT160_I_START_BIT)
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#define AW87XXX_PID_C2_OT160_I_PA_OVER_TEMPRETURE_PROTECTION_DETECTED (1)
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#define AW87XXX_PID_C2_OT160_I_PA_OVER_TEMPRETURE_PROTECTION_DETECTED_VALUE \
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(AW87XXX_PID_C2_OT160_I_PA_OVER_TEMPRETURE_PROTECTION_DETECTED << AW87XXX_PID_C2_OT160_I_START_BIT)
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#define AW87XXX_PID_C2_OT160_I_DEFAULT (0x1)
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#define AW87XXX_PID_C2_OT160_I_DEFAULT_VALUE \
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(AW87XXX_PID_C2_OT160_I_DEFAULT << AW87XXX_PID_C2_OT160_I_START_BIT)
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/* ADP_BOOST_I bit 0 (SYSINT 0x60) */
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#define AW87XXX_PID_C2_ADP_BOOST_I_START_BIT (0)
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#define AW87XXX_PID_C2_ADP_BOOST_I_BITS_LEN (1)
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#define AW87XXX_PID_C2_ADP_BOOST_I_MASK \
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(~(((1<<AW87XXX_PID_C2_ADP_BOOST_I_BITS_LEN)-1) << AW87XXX_PID_C2_ADP_BOOST_I_START_BIT))
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#define AW87XXX_PID_C2_ADP_BOOST_I_DIRECT_MODE (0)
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#define AW87XXX_PID_C2_ADP_BOOST_I_DIRECT_MODE_VALUE \
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(AW87XXX_PID_C2_ADP_BOOST_I_DIRECT_MODE << AW87XXX_PID_C2_ADP_BOOST_I_START_BIT)
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#define AW87XXX_PID_C2_ADP_BOOST_I_BOOST_MODE (1)
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#define AW87XXX_PID_C2_ADP_BOOST_I_BOOST_MODE_VALUE \
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(AW87XXX_PID_C2_ADP_BOOST_I_BOOST_MODE << AW87XXX_PID_C2_ADP_BOOST_I_START_BIT)
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#define AW87XXX_PID_C2_ADP_BOOST_I_DEFAULT (0x0)
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#define AW87XXX_PID_C2_ADP_BOOST_I_DEFAULT_VALUE \
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(AW87XXX_PID_C2_ADP_BOOST_I_DEFAULT << AW87XXX_PID_C2_ADP_BOOST_I_START_BIT)
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/* default value of SYSINT (0x60) */
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/* #define AW87XXX_PID_C2_SYSINT_DEFAULT (0xBE) */
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/* detail information of registers end */
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#endif /* #ifndef __AW87XXX_PID_C2_REG_H__ */
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