/*
 * Copyright (c) 2009-2018 ARM Limited. All rights reserved.
 * 
 * SPDX-License-Identifier: Apache-2.0
 * 
 * Licensed under the Apache License, Version 2.0 (the License); you may
 * not use this file except in compliance with the License.
 * You may obtain a copy of the License at
 * 
 * http://www.apache.org/licenses/LICENSE-2.0
 * 
 * Unless required by applicable law or agreed to in writing, software
 * distributed under the License is distributed on an AS IS BASIS, WITHOUT
 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
 * See the License for the specific language governing permissions and
 * limitations under the License.
 *
 * @file     CW32L012.h
 * @brief    CMSIS HeaderFile
 * @version  1.2
 * @date     Wed Jul 30 11:20:43 2025
 * @note     Generated by SVDConv V3.3.46
 *           from File 'cw32l012.svd',
 *           last modified on Wed Jul 30 11:20:28 2025
 */


/** @addtogroup Wuhan Xinyuan Semiconductor Co.Ltd
  * @{
  */


/** @addtogroup CW32L012
  * @{
  */


#ifndef __CW32L012_H
#define __CW32L012_H

#ifdef __cplusplus
extern "C" {
#endif


/** @addtogroup Configuration_of_CMSIS
  * @{
  */



/* =========================================================================================================================== */
/* ================                                Interrupt Number Definition                                ================ */
/* =========================================================================================================================== */

typedef enum {
/* =======================================  ARM Cortex-M0+ Specific Interrupt Numbers  ======================================= */
  Reset_IRQn                = -15,              /*!< -15  Reset Vector, invoked on Power up and warm reset                     */
  NonMaskableInt_IRQn       = -14,              /*!< -14  Non maskable Interrupt, cannot be stopped or preempted               */
  HardFault_IRQn            = -13,              /*!< -13  Hard Fault, all classes of Fault                                     */
  SVCall_IRQn               =  -5,              /*!< -5 System Service Call via SVC instruction                                */
  PendSV_IRQn               =  -2,              /*!< -2 Pendable request for system service                                    */
  SysTick_IRQn              =  -1,              /*!< -1 System Tick Timer                                                      */
/* ==========================================  cw32l012 Specific Interrupt Numbers  ========================================== */
  WDT_IRQn                  =   0,              /*!< 0  Watch Dog Timer Interrupt                                              */
  LVD_IRQn                  =   1,              /*!< 1  Low Voltage Detect Interrupt                                           */
  RTC_IRQn                  =   2,              /*!< 2  Real Time Clock Interrupt                                              */
  FLASHRAM_IRQn             =   3,              /*!< 3  Flash/RAM Interrupt                                                    */
  SYSCTRL_IRQn              =   4,              /*!< 4  SYSCTRL Interupt                                                       */
  GPIOA_IRQn                =   5,              /*!< 5  GPIOA Interrupt                                                        */
  GPIOB_IRQn                =   6,              /*!< 6  GPIOB Interrupt                                                        */
  GPIOC_IRQn                =   7,              /*!< 7  GPIOC Interrupt                                                        */
  GPIOF_IRQn                =   8,              /*!< 8  GPIOF Interrupt                                                        */
  DMACH12_IRQn              =   9,              /*!< 9  DMA Channel 1/2 Interrupt                                              */
  DMACH34_IRQn              =  10,              /*!< 10 DMA Channel 3/4 Interrupt                                              */
  CORDIC_IRQn               =  11,              /*!< 11 desc CORDIC                                                            */
  ADC1_IRQn                 =  12,              /*!< 12 ADC Interrupt                                                          */
  ATIM_IRQn                 =  13,              /*!< 13 Advanced Timer Interrupt                                               */
  VC13_IRQn                 =  14,              /*!< 14 Voltage Comparator 1/3 Interrupt                                       */
  VC24_IRQn                 =  15,              /*!< 15 Voltage Comparator 2/4 Interrupt                                       */
  GTIM1_IRQn                =  16,              /*!< 16 General Timer1 Interrupt                                               */
  GTIM2_IRQn                =  17,              /*!< 17 General Timer1 Interrupt                                               */
  GTIM34_IRQn               =  18,              /*!< 18 General Timer3_4 Interrupt                                             */
  LPTIM_IRQn                =  19,              /*!< 19 LPTIM Interrupt                                                        */
  BTIM1_IRQn                =  20,              /*!< 20 Base Timer1 Interrupt                                                  */
  BTIM2_IRQn                =  21,              /*!< 21 Base Timer2 Interrupt                                                  */
  BTIM3_HALLTIM_IRQn        =  22,              /*!< 22 Base Timer3 and Hall timer Interrupt                                   */
  I2C1_IRQn                 =  23,              /*!< 23 I2C1 Interrupt                                                         */
  I2C2_IRQn                 =  24,              /*!< 24 I2C2 Interrupt                                                         */
  SPI1_IRQn                 =  25,              /*!< 25 SPI1 Interrupt                                                         */
  SPI23_IRQn                =  26,              /*!< 26 SPI23 Interrupt                                                        */
  UART1_IRQn                =  27,              /*!< 27 UART1 Interrupt                                                        */
  UART2_IRQn                =  28,              /*!< 28 UART2 Interrupt                                                        */
  UART3_IRQn                =  29,              /*!< 29 UART3 Interrupt                                                        */
  ADC2_DAC_IRQn             =  30,              /*!< 30 ADC2 and DAC Interrupt                                                 */
  CLKFAULT_IRQn             =  31               /*!< 31 Clock Fault Interrupt                                                  */
} IRQn_Type;



/* =========================================================================================================================== */
/* ================                           Processor and Core Peripheral Section                           ================ */
/* =========================================================================================================================== */

/* ==========================  Configuration of the ARM Cortex-M0+ Processor and Core Peripherals  =========================== */
#define __CM0PLUS_REV                 0x0001U   /*!< CM0PLUS Core Revision                                                     */
#define __NVIC_PRIO_BITS               2        /*!< Number of Bits used for Priority Levels                                   */
#define __Vendor_SysTickConfig         0        /*!< Set to 1 if different SysTick Config is used                              */
#define __VTOR_PRESENT                 0        /*!< Set to 1 if CPU supports Vector Table Offset Register                     */
#define __MPU_PRESENT                  0        /*!< MPU present                                                               */
#define __FPU_PRESENT                  0        /*!< FPU present                                                               */


/** @} */ /* End of group Configuration_of_CMSIS */

#include "core_cm0plus.h"                       /*!< ARM Cortex-M0+ processor and core peripherals                             */
#include "system_cw32l012.h"                    /*!< cw32l012 System                                                           */

#ifndef __IM                                    /*!< Fallback for older CMSIS versions                                         */
  #define __IM   __I
#endif
#ifndef __OM                                    /*!< Fallback for older CMSIS versions                                         */
  #define __OM   __O
#endif
#ifndef __IOM                                   /*!< Fallback for older CMSIS versions                                         */
  #define __IOM  __IO
#endif


/* ========================================  Start of section using anonymous unions  ======================================== */
#if defined (__CC_ARM)
  #pragma push
  #pragma anon_unions
#elif defined (__ICCARM__)
  #pragma language=extended
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
  #pragma clang diagnostic push
  #pragma clang diagnostic ignored "-Wc11-extensions"
  #pragma clang diagnostic ignored "-Wreserved-id-macro"
  #pragma clang diagnostic ignored "-Wgnu-anonymous-struct"
  #pragma clang diagnostic ignored "-Wnested-anon-types"
#elif defined (__GNUC__)
  /* anonymous unions are enabled by default */
#elif defined (__TMS470__)
  /* anonymous unions are enabled by default */
#elif defined (__TASKING__)
  #pragma warning 586
#elif defined (__CSMC__)
  /* anonymous unions are enabled by default */
#else
  #warning Not supported compiler type
#endif


/* =========================================================================================================================== */
/* ================                            Device Specific Peripheral Section                             ================ */
/* =========================================================================================================================== */


/** @addtogroup Device_Peripheral_peripherals
  * @{
  */



/* =========================================================================================================================== */
/* ================                                           ADC1                                            ================ */
/* =========================================================================================================================== */


/**
  * @brief desc ADC1 (ADC1)
  */

typedef struct {                                /*!< (@ 0x40000000) ADC1 Structure                                             */
  
  union {
    __IOM uint32_t CR;                          /*!< (@ 0x00000000) desc CR                                                    */
    
    struct {
      __IOM uint32_t EN         : 1;            /*!< [0..0] desc EN                                                            */
      __IOM uint32_t CONT       : 1;            /*!< [1..1] desc CONT                                                          */
      __IOM uint32_t CLK        : 2;            /*!< [3..2] desc CLK                                                           */
      __IOM uint32_t ENS        : 3;            /*!< [6..4] desc ENS                                                           */
      __IOM uint32_t SLAVE      : 1;            /*!< [7..7] desc SLAVE                                                         */
      __IOM uint32_t SAM        : 2;            /*!< [9..8] desc SAM                                                           */
    } CR_f;
  } ;
  
  union {
    __IOM uint32_t START;                       /*!< (@ 0x00000004) desc START                                                 */
    
    struct {
      __IOM uint32_t START      : 1;            /*!< [0..0] desc START                                                         */
    } START_f;
  } ;
  
  union {
    __IOM uint32_t AWDTR;                       /*!< (@ 0x00000008) desc AWDTR                                                 */
    
    struct {
      __IOM uint32_t VTL        : 12;           /*!< [11..0] desc VTL                                                          */
      __IM  uint32_t            : 4;
      __IOM uint32_t VTH        : 12;           /*!< [27..16] desc VTH                                                         */
    } AWDTR_f;
  } ;
  
  union {
    __IOM uint32_t AWDCR;                       /*!< (@ 0x0000000C) desc AWDCR                                                 */
    
    struct {
      __IOM uint32_t IN0        : 1;            /*!< [0..0] desc IN0                                                           */
      __IOM uint32_t IN1        : 1;            /*!< [1..1] desc IN1                                                           */
      __IOM uint32_t IN2        : 1;            /*!< [2..2] desc IN2                                                           */
      __IOM uint32_t IN3        : 1;            /*!< [3..3] desc IN3                                                           */
      __IOM uint32_t IN4        : 1;            /*!< [4..4] desc IN4                                                           */
      __IOM uint32_t IN5        : 1;            /*!< [5..5] desc IN5                                                           */
      __IOM uint32_t IN6        : 1;            /*!< [6..6] desc IN6                                                           */
      __IOM uint32_t IN7        : 1;            /*!< [7..7] desc IN7                                                           */
      __IOM uint32_t IN8        : 1;            /*!< [8..8] desc IN8                                                           */
      __IOM uint32_t IN9        : 1;            /*!< [9..9] desc IN9                                                           */
      __IOM uint32_t IN10       : 1;            /*!< [10..10] desc IN10                                                        */
      __IOM uint32_t IN11       : 1;            /*!< [11..11] desc IN11                                                        */
      __IOM uint32_t IN12       : 1;            /*!< [12..12] desc IN12                                                        */
      __IOM uint32_t IN13       : 1;            /*!< [13..13] desc IN13                                                        */
      __IOM uint32_t IN14       : 1;            /*!< [14..14] desc IN14                                                        */
      __IOM uint32_t IN15       : 1;            /*!< [15..15] desc IN15                                                        */
    } AWDCR_f;
  } ;
  
  union {
    __IOM uint32_t TRIGGER;                     /*!< (@ 0x00000010) desc TRIGGER                                               */
    
    struct {
      __IOM uint32_t ATIMTRGO   : 1;            /*!< [0..0] desc ATIMTRGO                                                      */
      __IOM uint32_t ATIMTRGO2  : 1;            /*!< [1..1] desc ATIMTRGO2                                                     */
      __IOM uint32_t ATIMOC1REFC : 1;           /*!< [2..2] desc ATIMOC1REFC                                                   */
      __IOM uint32_t ATIMOC2REFC : 1;           /*!< [3..3] desc ATIMOC2REFC                                                   */
      __IOM uint32_t ATIMOC3REFC : 1;           /*!< [4..4] desc ATIMOC3REFC                                                   */
      __IOM uint32_t ATIMOC4REFC : 1;           /*!< [5..5] desc ATIMOC4REFC                                                   */
      __IOM uint32_t ATIMOC5REFC : 1;           /*!< [6..6] desc ATIMOC5REFC                                                   */
      __IOM uint32_t ATIMOC6REFC : 1;           /*!< [7..7] desc ATIMOC6REFC                                                   */
      __IOM uint32_t GTIM1TRGO  : 1;            /*!< [8..8] desc GTIM1TRGO                                                     */
      __IOM uint32_t GTIM1OC1REFC : 1;          /*!< [9..9] desc GTIM1OC1REFC                                                  */
      __IOM uint32_t GTIM1OC2REFC : 1;          /*!< [10..10] desc GTIM1OC2REFC                                                */
      __IOM uint32_t GTIM1OC3REFC : 1;          /*!< [11..11] desc GTIM1OC3REFC                                                */
      __IOM uint32_t GTIM1OC4REFC : 1;          /*!< [12..12] desc GTIM1OC4REFC                                                */
      __IOM uint32_t GTIM2TRGO  : 1;            /*!< [13..13] desc GTIM2TRGO                                                   */
      __IOM uint32_t GTIM2OC1REFC : 1;          /*!< [14..14] desc GTIM2OC1REFC                                                */
      __IOM uint32_t GTIM2OC2REFC : 1;          /*!< [15..15] desc GTIM2OC2REFC                                                */
      __IOM uint32_t GTIM2OC3REFC : 1;          /*!< [16..16] desc GTIM2OC3REFC                                                */
      __IOM uint32_t GTIM2OC4REFC : 1;          /*!< [17..17] desc GTIM2OC4REFC                                                */
      __IOM uint32_t GTIM3TRGO  : 1;            /*!< [18..18] desc GTIM3TRGO                                                   */
      __IOM uint32_t GTIM3OC1REFC : 1;          /*!< [19..19] desc GTIM3OC1REFC                                                */
      __IOM uint32_t GTIM3OC2REFC : 1;          /*!< [20..20] desc GTIM3OC2REFC                                                */
      __IOM uint32_t GTIM3OC3REFC : 1;          /*!< [21..21] desc GTIM3OC3REFC                                                */
      __IOM uint32_t GTIM3OC4REFC : 1;          /*!< [22..22] desc GTIM3OC4REFC                                                */
      __IOM uint32_t GTIM4TRGO  : 1;            /*!< [23..23] desc GTIM4TRGO                                                   */
      __IOM uint32_t GTIM4OC1REFC : 1;          /*!< [24..24] desc GTIM4OC1REFC                                                */
      __IOM uint32_t GTIM4OC2REFC : 1;          /*!< [25..25] desc GTIM4OC2REFC                                                */
      __IOM uint32_t GTIM4OC3REFC : 1;          /*!< [26..26] desc GTIM4OC3REFC                                                */
      __IOM uint32_t GTIM4OC4REFC : 1;          /*!< [27..27] desc GTIM4OC4REFC                                                */
      __IOM uint32_t BTIM1TRGO  : 1;            /*!< [28..28] desc BTIM1TRGO                                                   */
      __IOM uint32_t BTIM2TRGO  : 1;            /*!< [29..29] desc BTIM2TRGO                                                   */
      __IOM uint32_t BTIM3TRGO  : 1;            /*!< [30..30] desc BTIM3TRGO                                                   */
      __IOM uint32_t HALLTIMTRGO : 1;           /*!< [31..31] desc HALLTIMTRGO                                                 */
    } TRIGGER_f;
  } ;
  __IM  uint32_t  RESERVED;
  
  union {
    __IOM uint32_t SAMPLE;                      /*!< (@ 0x00000018) desc SAMPLE                                                */
    
    struct {
      __IOM uint32_t SQRCH0     : 4;            /*!< [3..0] desc SQRCH0                                                        */
      __IOM uint32_t SQRCH1     : 4;            /*!< [7..4] desc SQRCH1                                                        */
      __IOM uint32_t SQRCH2     : 4;            /*!< [11..8] desc SQRCH2                                                       */
      __IOM uint32_t SQRCH3     : 4;            /*!< [15..12] desc SQRCH3                                                      */
      __IOM uint32_t SQRCH4     : 4;            /*!< [19..16] desc SQRCH4                                                      */
      __IOM uint32_t SQRCH5     : 4;            /*!< [23..20] desc SQRCH5                                                      */
      __IOM uint32_t SQRCH6     : 4;            /*!< [27..24] desc SQRCH6                                                      */
      __IOM uint32_t SQRCH7     : 4;            /*!< [31..28] desc SQRCH7                                                      */
    } SAMPLE_f;
  } ;
  __IM  uint32_t  RESERVED1;
  
  union {
    __IOM uint32_t SQRCFR;                      /*!< (@ 0x00000020) desc SQRCFR                                                */
    
    struct {
      __IOM uint32_t SQRCH0     : 4;            /*!< [3..0] desc SQRCH0                                                        */
      __IOM uint32_t SQRCH1     : 4;            /*!< [7..4] desc SQRCH1                                                        */
      __IOM uint32_t SQRCH2     : 4;            /*!< [11..8] desc SQRCH2                                                       */
      __IOM uint32_t SQRCH3     : 4;            /*!< [15..12] desc SQRCH3                                                      */
      __IOM uint32_t SQRCH4     : 4;            /*!< [19..16] desc SQRCH4                                                      */
      __IOM uint32_t SQRCH5     : 4;            /*!< [23..20] desc SQRCH5                                                      */
      __IOM uint32_t SQRCH6     : 4;            /*!< [27..24] desc SQRCH6                                                      */
      __IOM uint32_t SQRCH7     : 4;            /*!< [31..28] desc SQRCH7                                                      */
    } SQRCFR_f;
  } ;
  __IM  uint32_t  RESERVED2[3];
  
  union {
    __IM  uint32_t RESULT0;                     /*!< (@ 0x00000030) desc RESULT0                                               */
    
    struct {
      __IM  uint32_t RESULT     : 12;           /*!< [15..0] desc RESULT                                                       */
    } RESULT0_f;
  } ;
  
  union {
    __IM  uint32_t RESULT1;                     /*!< (@ 0x00000034) desc RESULT1                                               */
    
    struct {
      __IM  uint32_t RESULT     : 12;           /*!< [15..0] desc RESULT                                                       */
    } RESULT1_f;
  } ;
  
  union {
    __IM  uint32_t RESULT2;                     /*!< (@ 0x00000038) desc RESULT2                                               */
    
    struct {
      __IM  uint32_t RESULT     : 12;           /*!< [15..0] desc RESULT                                                       */
    } RESULT2_f;
  } ;
  
  union {
    __IM  uint32_t RESULT3;                     /*!< (@ 0x0000003C) desc RESULT3                                               */
    
    struct {
      __IM  uint32_t RESULT     : 12;           /*!< [15..0] desc RESULT                                                       */
    } RESULT3_f;
  } ;
  
  union {
    __IM  uint32_t RESULT4;                     /*!< (@ 0x00000040) desc RESULT4                                               */
    
    struct {
      __IM  uint32_t RESULT     : 12;           /*!< [15..0] desc RESULT                                                       */
    } RESULT4_f;
  } ;
  
  union {
    __IM  uint32_t RESULT5;                     /*!< (@ 0x00000044) desc RESULT5                                               */
    
    struct {
      __IM  uint32_t RESULT     : 12;           /*!< [15..0] desc RESULT                                                       */
    } RESULT5_f;
  } ;
  
  union {
    __IM  uint32_t RESULT6;                     /*!< (@ 0x00000048) desc RESULT6                                               */
    
    struct {
      __IM  uint32_t RESULT     : 12;           /*!< [15..0] desc RESULT                                                       */
    } RESULT6_f;
  } ;
  
  union {
    __IM  uint32_t RESULT7;                     /*!< (@ 0x0000004C) desc RESULT7                                               */
    
    struct {
      __IM  uint32_t RESULT     : 12;           /*!< [15..0] desc RESULT                                                       */
    } RESULT7_f;
  } ;
  __IM  uint32_t  RESERVED3[8];
  
  union {
    __IOM uint32_t IER;                         /*!< (@ 0x00000070) desc IER                                                   */
    
    struct {
      __IOM uint32_t EOC        : 1;            /*!< [0..0] desc EOC                                                           */
      __IOM uint32_t EOS        : 1;            /*!< [1..1] desc EOS                                                           */
      __IM  uint32_t            : 1;
      __IOM uint32_t AWDL       : 1;            /*!< [3..3] desc AWDL                                                          */
      __IOM uint32_t AWDH       : 1;            /*!< [4..4] desc AWDH                                                          */
      __IOM uint32_t DMAEOC     : 1;            /*!< [5..5] desc DMAEOC                                                        */
      __IOM uint32_t DMAEOS     : 1;            /*!< [6..6] desc DMAEOS                                                        */
    } IER_f;
  } ;
  
  union {
    __IOM uint32_t ICR;                         /*!< (@ 0x00000074) desc ICR                                                   */
    
    struct {
      __IOM uint32_t EOC        : 1;            /*!< [0..0] desc EOC                                                           */
      __IOM uint32_t EOS        : 1;            /*!< [1..1] desc EOS                                                           */
      __IM  uint32_t            : 1;
      __IOM uint32_t AWDL       : 1;            /*!< [3..3] desc AWDL                                                          */
      __IOM uint32_t AWDH       : 1;            /*!< [4..4] desc AWDH                                                          */
    } ICR_f;
  } ;
  
  union {
    __IOM uint32_t ISR;                         /*!< (@ 0x00000078) desc ISR                                                   */
    
    struct {
      __IM  uint32_t EOC        : 1;            /*!< [0..0] desc EOC                                                           */
      __IM  uint32_t EOS        : 1;            /*!< [1..1] desc EOS                                                           */
      __IM  uint32_t            : 1;
      __IM  uint32_t AWDL       : 1;            /*!< [3..3] desc AWDL                                                          */
      __IOM uint32_t AWDH       : 1;            /*!< [4..4] desc AWDH                                                          */
    } ISR_f;
  } ;
} ADC_TypeDef;                                     /*!< Size = 124 (0x7c)                                                         */



/* =========================================================================================================================== */
/* ================                                           ATIM                                            ================ */
/* =========================================================================================================================== */


/**
  * @brief desc ATIM (ATIM)
  */

typedef struct {                                /*!< (@ 0x40001400) ATIM Structure                                             */
  
  union {
    __IOM uint32_t CR1;                         /*!< (@ 0x00000000) Control Register1                                          */
    
    struct {
      __IOM uint32_t CEN        : 1;            /*!< [0..0] desc CEN                                                           */
      __IOM uint32_t UDIS       : 1;            /*!< [1..1] desc UDIS                                                          */
      __IOM uint32_t URS        : 1;            /*!< [2..2] desc URS                                                           */
      __IOM uint32_t OPM        : 1;            /*!< [3..3] desc OPM                                                           */
      __IOM uint32_t DIR        : 1;            /*!< [4..4] desc DIR                                                           */
      __IOM uint32_t CMS        : 2;            /*!< [6..5] desc CMS                                                           */
      __IOM uint32_t ARPE       : 1;            /*!< [7..7] desc ARPE                                                          */
      __IOM uint32_t CKD        : 2;            /*!< [9..8] desc CKD                                                           */
      __IM  uint32_t            : 1;
      __IOM uint32_t UIFREMAP   : 1;            /*!< [11..11] desc UIFREMAP                                                    */
    } CR1_f;
  } ;
  
  union {
    __IOM uint32_t CR2;                         /*!< (@ 0x00000004) Control Register2                                          */
    
    struct {
      __IOM uint32_t CCPC       : 1;            /*!< [0..0] desc CCPC                                                          */
      __IM  uint32_t            : 1;
      __IOM uint32_t CCUS       : 1;            /*!< [2..2] desc CCUS                                                          */
      __IOM uint32_t CCDS       : 1;            /*!< [3..3] desc CCDS                                                          */
      __IOM uint32_t MMS        : 3;            /*!< [6..4] desc MMS                                                           */
      __IOM uint32_t TI1S       : 1;            /*!< [7..7] desc TI1S                                                          */
      __IOM uint32_t OIS1       : 1;            /*!< [8..8] desc OIS1                                                          */
      __IOM uint32_t OIS1N      : 1;            /*!< [9..9] desc OIS1N                                                         */
      __IOM uint32_t OIS2       : 1;            /*!< [10..10] desc OIS2                                                        */
      __IOM uint32_t OIS2N      : 1;            /*!< [11..11] desc OIS2N                                                       */
      __IOM uint32_t OIS3       : 1;            /*!< [12..12] desc OIS3                                                        */
      __IOM uint32_t OIS3N      : 1;            /*!< [13..13] desc OIS3N                                                       */
      __IOM uint32_t OIS4       : 1;            /*!< [14..14] desc OIS4                                                        */
      __IOM uint32_t OIS4N      : 1;            /*!< [15..15] desc OIS4N                                                       */
      __IOM uint32_t OIS5       : 1;            /*!< [16..16] desc OIS5                                                        */
      __IOM uint32_t OIS5N      : 1;            /*!< [17..17] desc OIS5N                                                       */
      __IOM uint32_t OIS6       : 1;            /*!< [18..18] desc OIS6                                                        */
      __IOM uint32_t OIS6N      : 1;            /*!< [19..19] desc OIS6N                                                       */
      __IOM uint32_t MMS2       : 5;            /*!< [24..20] desc MMS2                                                        */
      __IOM uint32_t MMSH       : 2;            /*!< [26..25] desc MMSH                                                        */
    } CR2_f;
  } ;
  
  union {
    __IOM uint32_t SMCR;                        /*!< (@ 0x00000008) Slave Mode Control Register                                */
    
    struct {
      __IOM uint32_t SMS        : 3;            /*!< [2..0] desc SMS                                                           */
      __IOM uint32_t OCCS       : 1;            /*!< [3..3] desc OCCS                                                          */
      __IOM uint32_t TS         : 3;            /*!< [6..4] desc TS                                                            */
      __IOM uint32_t MSM        : 1;            /*!< [7..7] desc MSM                                                           */
      __IOM uint32_t ETF        : 4;            /*!< [11..8] desc ETF                                                          */
      __IOM uint32_t ETPS       : 2;            /*!< [13..12] desc ETPS                                                        */
      __IOM uint32_t ECE        : 1;            /*!< [14..14] desc ECE                                                         */
      __IOM uint32_t ETP        : 1;            /*!< [15..15] desc ETP                                                         */
      __IOM uint32_t SMSH       : 1;            /*!< [16..16] desc SMSH                                                        */
      __IM  uint32_t            : 3;
      __IOM uint32_t TSH        : 2;            /*!< [21..20] desc TSH                                                         */
      __IM  uint32_t            : 2;
      __IOM uint32_t SMSPE      : 1;            /*!< [24..24] desc SMSPE                                                       */
      __IOM uint32_t SMSPS      : 1;            /*!< [25..25] desc SMSPS                                                       */
    } SMCR_f;
  } ;
  
  union {
    __IOM uint32_t IER;                         /*!< (@ 0x0000000C) Interrupt Enable Register                                  */
    
    struct {
      __IOM uint32_t UIE        : 1;            /*!< [0..0] desc UIE                                                           */
      __IOM uint32_t CC1IE      : 1;            /*!< [1..1] desc CC1IE                                                         */
      __IOM uint32_t CC2IE      : 1;            /*!< [2..2] desc CC2IE                                                         */
      __IOM uint32_t CC3IE      : 1;            /*!< [3..3] desc CC3IE                                                         */
      __IOM uint32_t CC4IE      : 1;            /*!< [4..4] desc CC4IE                                                         */
      __IOM uint32_t COMIE      : 1;            /*!< [5..5] desc COMIE                                                         */
      __IOM uint32_t TIE        : 1;            /*!< [6..6] desc TIE                                                           */
      __IOM uint32_t BIE        : 1;            /*!< [7..7] desc BIE                                                           */
      __IOM uint32_t UDE        : 1;            /*!< [8..8] desc UDE                                                           */
      __IOM uint32_t CC1DE      : 1;            /*!< [9..9] desc CC1DE                                                         */
      __IOM uint32_t CC2DE      : 1;            /*!< [10..10] desc CC2DE                                                       */
      __IOM uint32_t CC3DE      : 1;            /*!< [11..11] desc CC3DE                                                       */
      __IOM uint32_t CC4DE      : 1;            /*!< [12..12] desc CC4DE                                                       */
      __IOM uint32_t COMDE      : 1;            /*!< [13..13] desc COMDE                                                       */
      __IOM uint32_t TDE        : 1;            /*!< [14..14] desc TDE                                                         */
            uint32_t            : 1;
      __IOM uint32_t CC5IE      : 1;            /*!< [16..16] desc CC5IE                                                       */
      __IOM uint32_t CC6IE      : 1;            /*!< [17..17] desc CC6IE                                                       */
      __IOM uint32_t CC5DE      : 1;            /*!< [18..18] desc CC5DE                                                       */
      __IOM uint32_t CC6DE      : 1;            /*!< [19..19] desc CC6DE                                                       */
      __IOM uint32_t IDXIE      : 1;            /*!< [20..20] desc IDXIE                                                       */
      __IOM uint32_t DIRIE      : 1;            /*!< [21..21] desc DIRIE                                                       */
      __IOM uint32_t IERRIE     : 1;            /*!< [22..22] desc IERRIE                                                      */
      __IOM uint32_t TERRIE     : 1;            /*!< [23..23] desc TERRIE                                                      */
    } IER_f;
  } ;
  
  union {
    __IM  uint32_t ISR;                         /*!< (@ 0x00000010) Interrupt status register                                  */
    
    struct {
      __IM  uint32_t UIF        : 1;            /*!< [0..0] desc UIF                                                           */
      __IM  uint32_t CC1IF      : 1;            /*!< [1..1] desc CC1IF                                                         */
      __IM  uint32_t CC2IF      : 1;            /*!< [2..2] desc CC2IF                                                         */
      __IM  uint32_t CC3IF      : 1;            /*!< [3..3] desc CC3IF                                                         */
      __IM  uint32_t CC4IF      : 1;            /*!< [4..4] desc CC4IF                                                         */
      __IM  uint32_t COMIF      : 1;            /*!< [5..5] desc COMIF                                                         */
      __IM  uint32_t TIF        : 1;            /*!< [6..6] desc TIF                                                           */
      __IM  uint32_t BIF        : 1;            /*!< [7..7] desc BIF                                                           */
      __IM  uint32_t B2IF       : 1;            /*!< [8..8] desc B2IF                                                          */
      __IM  uint32_t CC1OF      : 1;            /*!< [9..9] desc CC1OF                                                         */
      __IM  uint32_t CC2OF      : 1;            /*!< [10..10] desc CC2OF                                                       */
      __IM  uint32_t CC3OF      : 1;            /*!< [11..11] desc CC3OF                                                       */
      __IM  uint32_t CC4OF      : 1;            /*!< [12..12] desc CC4OF                                                       */
      __IM  uint32_t SBIF       : 1;            /*!< [13..13] desc SBIF                                                        */
      __IM  uint32_t            : 2;
      __IM  uint32_t CC5IF      : 1;            /*!< [16..16] desc CC5IF                                                       */
      __IM  uint32_t CC6IF      : 1;            /*!< [17..17] desc CC6IF                                                       */
      __IM  uint32_t CC5OF      : 1;            /*!< [18..18] desc CC5OF                                                       */
      __IM  uint32_t CC6OF      : 1;            /*!< [19..19] desc CC6OF                                                       */
      __IM  uint32_t IDXF       : 1;            /*!< [20..20] desc IDXF                                                        */
      __IM  uint32_t DIRF       : 1;            /*!< [21..21] desc DIRF                                                        */
      __IM  uint32_t IERRF      : 1;            /*!< [22..22] desc IERRF                                                       */
      __IM  uint32_t TERRF      : 1;            /*!< [23..23] desc TERRF                                                       */
    } ISR_f;
  } ;
  
  union {
    __IOM uint32_t EGR;                         /*!< (@ 0x00000014) Event generation register                                  */
    
    struct {
      __IOM uint32_t UG         : 1;            /*!< [0..0] desc UG                                                            */
      __IOM uint32_t CC1G       : 1;            /*!< [1..1] desc CC1G                                                          */
      __IOM uint32_t CC2G       : 1;            /*!< [2..2] desc CC2G                                                          */
      __IOM uint32_t CC3G       : 1;            /*!< [3..3] desc CC3G                                                          */
      __IOM uint32_t CC4G       : 1;            /*!< [4..4] desc CC4G                                                          */
      __IOM uint32_t COMG       : 1;            /*!< [5..5] desc COMG                                                          */
      __IOM uint32_t TG         : 1;            /*!< [6..6] desc TG                                                            */
      __IOM uint32_t BG         : 1;            /*!< [7..7] desc BG                                                            */
      __IOM uint32_t B2G        : 1;            /*!< [8..8] desc B2G                                                           */
      __IM  uint32_t            : 7;
      __IOM uint32_t CC5G       : 1;            /*!< [16..16] desc CC5G                                                        */
      __IOM uint32_t CC6G       : 1;            /*!< [17..17] desc CC6G                                                        */
    } EGR_f;
  } ;
  
  union {
    union {
      __IOM uint32_t CCMR1CAP;                  /*!< (@ 0x00000018) capture compare mode register 1                            */
      
      struct {
        __IOM uint32_t CC1S     : 2;            /*!< [1..0] desc CC1S                                                          */
        __IOM uint32_t IC1PSC   : 2;            /*!< [3..2] desc IC1PSC                                                        */
        __IOM uint32_t IC1F     : 4;            /*!< [7..4] desc IC1F                                                          */
        __IOM uint32_t CC2S     : 2;            /*!< [9..8] desc CC2S                                                          */
        __IOM uint32_t IC2PSC   : 2;            /*!< [11..10] desc IC2PSC                                                      */
        __IOM uint32_t IC2F     : 4;            /*!< [15..12] desc IC2F                                                        */
      } CCMR1CAP_f;
    } ;
    
    union {
      __IOM uint32_t CCMR1CMP;                  /*!< (@ 0x00000018) capture compare mode register 1                            */
      
      struct {
        __IOM uint32_t CC1S     : 2;            /*!< [1..0] desc CC1S                                                          */
        __IOM uint32_t OC1FE    : 1;            /*!< [2..2] desc OC1FE                                                         */
        __IOM uint32_t OC1PE    : 1;            /*!< [3..3] desc OC1PE                                                         */
        __IOM uint32_t OC1M     : 3;            /*!< [6..4] desc OC1M                                                          */
        __IOM uint32_t OC1CE    : 1;            /*!< [7..7] desc OC1CE                                                         */
        __IOM uint32_t CC2S     : 2;            /*!< [9..8] desc CC2S                                                          */
        __IOM uint32_t OC2FE    : 1;            /*!< [10..10] desc OC2FE                                                       */
        __IOM uint32_t OC2PE    : 1;            /*!< [11..11] desc OC2PE                                                       */
        __IOM uint32_t OC2M     : 3;            /*!< [14..12] desc OC2M                                                        */
        __IOM uint32_t OC2CE    : 1;            /*!< [15..15] desc OC2CE                                                       */
        __IOM uint32_t OC1MH    : 1;            /*!< [16..16] desc OC1MH                                                       */
        __IM  uint32_t          : 7;
        __IOM uint32_t OC2MH    : 1;            /*!< [24..24] desc OC2MH                                                       */
      } CCMR1CMP_f;
    } ;
  };
  
  union {
    union {
      __IOM uint32_t CCMR2CAP;                  /*!< (@ 0x0000001C) capture compare mode register 2                            */
      
      struct {
        __IOM uint32_t CC3S     : 2;            /*!< [1..0] desc CC3S                                                          */
        __IOM uint32_t IC3PSC   : 2;            /*!< [3..2] desc IC3PSC                                                        */
        __IOM uint32_t IC3F     : 4;            /*!< [7..4] desc IC3F                                                          */
        __IOM uint32_t CC4S     : 2;            /*!< [9..8] desc CC4S                                                          */
        __IOM uint32_t IC4PSC   : 2;            /*!< [11..10] desc IC4PSC                                                      */
        __IOM uint32_t IC4F     : 4;            /*!< [15..12] desc IC4F                                                        */
      } CCMR2CAP_f;
    } ;
    
    union {
      __IOM uint32_t CCMR2CMP;                  /*!< (@ 0x0000001C) capture compare mode register 2                            */
      
      struct {
        __IOM uint32_t CC3S     : 2;            /*!< [1..0] desc CC3S                                                          */
        __IOM uint32_t OC3FE    : 1;            /*!< [2..2] desc OC3FE                                                         */
        __IOM uint32_t OC3PE    : 1;            /*!< [3..3] desc OC3PE                                                         */
        __IOM uint32_t OC3M     : 3;            /*!< [6..4] desc OC3M                                                          */
        __IOM uint32_t OC3CE    : 1;            /*!< [7..7] desc OC3CE                                                         */
        __IOM uint32_t CC4S     : 2;            /*!< [9..8] desc CC4S                                                          */
        __IOM uint32_t OC4FE    : 1;            /*!< [10..10] desc OC4FE                                                       */
        __IOM uint32_t OC4PE    : 1;            /*!< [11..11] desc OC4PE                                                       */
        __IOM uint32_t OC4M     : 3;            /*!< [14..12] desc OC4M                                                        */
        __IOM uint32_t OC4CE    : 1;            /*!< [15..15] desc OC4CE                                                       */
        __IOM uint32_t OC3MH    : 1;            /*!< [16..16] desc OC3MH                                                       */
        __IM  uint32_t          : 7;
        __IOM uint32_t OC4MH    : 1;            /*!< [24..24] desc OC4MH                                                       */
      } CCMR2CMP_f;
    } ;
  };
  
  union {
    __IOM uint32_t CCER;                        /*!< (@ 0x00000020) capture compare enable register                            */
    
    struct {
      __IOM uint32_t CC1E       : 1;            /*!< [0..0] desc CC1E                                                          */
      __IOM uint32_t CC1P       : 1;            /*!< [1..1] desc CC1P                                                          */
      __IOM uint32_t CC1NE      : 1;            /*!< [2..2] desc CC1NE                                                         */
      __IOM uint32_t CC1NP      : 1;            /*!< [3..3] desc CC1NP                                                         */
      __IOM uint32_t CC2E       : 1;            /*!< [4..4] desc CC2E                                                          */
      __IOM uint32_t CC2P       : 1;            /*!< [5..5] desc CC2P                                                          */
      __IOM uint32_t CC2NE      : 1;            /*!< [6..6] desc CC2NE                                                         */
      __IOM uint32_t CC2NP      : 1;            /*!< [7..7] desc CC2NP                                                         */
      __IOM uint32_t CC3E       : 1;            /*!< [8..8] desc CC3E                                                          */
      __IOM uint32_t CC3P       : 1;            /*!< [9..9] desc CC3P                                                          */
      __IOM uint32_t CC3NE      : 1;            /*!< [10..10] desc CC3NE                                                       */
      __IOM uint32_t CC3NP      : 1;            /*!< [11..11] desc CC3NP                                                       */
      __IOM uint32_t CC4E       : 1;            /*!< [12..12] desc CC4E                                                        */
      __IOM uint32_t CC4P       : 1;            /*!< [13..13] desc CC4P                                                        */
      __IOM uint32_t CC4NE      : 1;            /*!< [14..14] desc CC4NE                                                       */
      __IOM uint32_t CC4NP      : 1;            /*!< [15..15] desc CC4NP                                                       */
      __IOM uint32_t CC5E       : 1;            /*!< [16..16] desc CC5E                                                        */
      __IOM uint32_t CC5P       : 1;            /*!< [17..17] desc CC5P                                                        */
      __IOM uint32_t CC5NE      : 1;            /*!< [18..18] desc CC5NE                                                       */
      __IOM uint32_t CC5NP      : 1;            /*!< [19..19] desc CC5NP                                                       */
      __IOM uint32_t CC6E       : 1;            /*!< [20..20] desc CC6E                                                        */
      __IOM uint32_t CC6P       : 1;            /*!< [21..21] desc CC6P                                                        */
      __IOM uint32_t CC6NE      : 1;            /*!< [22..22] desc CC6NE                                                       */
      __IOM uint32_t CC6NP      : 1;            /*!< [23..23] desc CC6NP                                                       */
    } CCER_f;
  } ;
  
  union {
    __IOM uint32_t CNT;                         /*!< (@ 0x00000024) Counter Register                                           */
    
    struct {
      __IOM uint32_t CNT        : 16;           /*!< [15..0] desc CNT                                                          */
      __IM  uint32_t            : 15;
      __IM  uint32_t UIFCPY     : 1;            /*!< [31..31] desc UIFCPY                                                      */
    } CNT_f;
  } ;
  
  union {
    __IOM uint32_t PSC;                         /*!< (@ 0x00000028) prescaler Register                                         */
    
    struct {
      __IOM uint32_t PSC        : 16;           /*!< [15..0] desc PSC                                                          */
    } PSC_f;
  } ;
  
  union {
    __IOM uint32_t ARR;                         /*!< (@ 0x0000002C) Auto reload Register                                       */
    
    struct {
      __IOM uint32_t ARR        : 16;           /*!< [15..0] desc ARR                                                          */
    } ARR_f;
  } ;
  
  union {
    __IOM uint32_t RCR;                         /*!< (@ 0x00000030) Repetition Counter Register                                */
    
    struct {
      __IOM uint32_t REP        : 16;           /*!< [15..0] desc REP                                                          */
    } RCR_f;
  } ;
  
  union {
    __IOM uint32_t CCR1;                        /*!< (@ 0x00000034) capture compare register1                                  */
    
    struct {
      __IOM uint32_t CCR1       : 16;           /*!< [15..0] desc CCR1                                                         */
    } CCR1_f;
  } ;
  
  union {
    __IOM uint32_t CCR2;                        /*!< (@ 0x00000038) capture compare register2                                  */
    
    struct {
      __IOM uint32_t CCR2       : 16;           /*!< [15..0] desc CCR2                                                         */
    } CCR2_f;
  } ;
  
  union {
    __IOM uint32_t CCR3;                        /*!< (@ 0x0000003C) capture compare register3                                  */
    
    struct {
      __IOM uint32_t CCR3       : 16;           /*!< [15..0] desc CCR3                                                         */
    } CCR3_f;
  } ;
  
  union {
    __IOM uint32_t CCR4;                        /*!< (@ 0x00000040) capture compare register4                                  */
    
    struct {
      __IOM uint32_t CCR4       : 16;           /*!< [15..0] desc CCR4                                                         */
    } CCR4_f;
  } ;
  
  union {
    __IOM uint32_t BDTR;                        /*!< (@ 0x00000044) break and dead-time register                               */
    
    struct {
      __IOM uint32_t DTG        : 8;            /*!< [7..0] desc DTG                                                           */
      __IOM uint32_t LOCK       : 2;            /*!< [9..8] desc LOCK                                                          */
      __IOM uint32_t OSSI       : 1;            /*!< [10..10] desc OSSI                                                        */
      __IOM uint32_t OSSR       : 1;            /*!< [11..11] desc OSSR                                                        */
      __IOM uint32_t BKE        : 1;            /*!< [12..12] desc BKE                                                         */
      __IOM uint32_t BKP        : 1;            /*!< [13..13] desc BKP                                                         */
      __IOM uint32_t AOE        : 1;            /*!< [14..14] desc AOE                                                         */
      __IOM uint32_t MOE        : 1;            /*!< [15..15] desc MOE                                                         */
      __IOM uint32_t BKF        : 4;            /*!< [19..16] desc BKF                                                         */
      __IOM uint32_t BK2F       : 4;            /*!< [23..20] desc BK2F                                                        */
      __IOM uint32_t BK2E       : 1;            /*!< [24..24] desc BK2E                                                        */
      __IOM uint32_t BK2P       : 1;            /*!< [25..25] desc BK2P                                                        */
    } BDTR_f;
  } ;
  
  union {
    __IOM uint32_t CCR5;                        /*!< (@ 0x00000048) capture compare register5                                  */
    
    struct {
      __IOM uint32_t CCR5       : 16;           /*!< [15..0] desc CCR5                                                         */
      __IM  uint32_t            : 10;
      __IOM uint32_t GC5C1      : 1;            /*!< [26..26] desc GC5C1                                                       */
      __IOM uint32_t GC5C2      : 1;            /*!< [27..27] desc GC5C2                                                       */
      __IOM uint32_t GC5C3      : 1;            /*!< [28..28] desc GC5C3                                                       */
      __IOM uint32_t GC5C4      : 1;            /*!< [29..29] desc GC5C4                                                       */
      __IOM uint32_t GC5C5      : 1;            /*!< [30..30] desc GC5C5                                                       */
      __IOM uint32_t GC5C6      : 1;            /*!< [31..31] desc GC5C6                                                       */
    } CCR5_f;
  } ;
  
  union {
    __IOM uint32_t CCR6;                        /*!< (@ 0x0000004C) capture compare register6                                  */
    
    struct {
      __IOM uint32_t CCR6       : 16;           /*!< [15..0] desc CCR6                                                         */
      __IM  uint32_t            : 10;
      __IOM uint32_t GC6C1      : 1;            /*!< [26..26] desc GC6C1                                                       */
      __IOM uint32_t GC6C2      : 1;            /*!< [27..27] desc GC6C2                                                       */
      __IOM uint32_t GC6C3      : 1;            /*!< [28..28] desc GC6C3                                                       */
      __IOM uint32_t GC6C4      : 1;            /*!< [29..29] desc GC6C4                                                       */
      __IOM uint32_t GC6C5      : 1;            /*!< [30..30] desc GC6C5                                                       */
      __IOM uint32_t GC6C6      : 1;            /*!< [31..31] desc GC6C6                                                       */
    } CCR6_f;
  } ;
  
  union {
    union {
      __IOM uint32_t CCMR3CAP;                  /*!< (@ 0x00000050) capture compare mode register 3                            */
      
      struct {
        __IOM uint32_t CC5S     : 2;            /*!< [1..0] desc CC5S                                                          */
        __IOM uint32_t IC5PSC   : 2;            /*!< [3..2] desc IC5PSC                                                        */
        __IOM uint32_t IC5F     : 4;            /*!< [7..4] desc IC5F                                                          */
        __IOM uint32_t CC6S     : 2;            /*!< [9..8] desc CC6S                                                          */
        __IOM uint32_t IC6PSC   : 2;            /*!< [11..10] desc IC6PSC                                                      */
        __IOM uint32_t IC6F     : 4;            /*!< [15..12] desc IC6F                                                        */
      } CCMR3CAP_f;
    } ;
    
    union {
      __IOM uint32_t CCMR3CMP;                  /*!< (@ 0x00000050) capture compare mode register 3                            */
      
      struct {
        __IOM uint32_t CC5S     : 2;            /*!< [1..0] desc CC5S                                                          */
        __IOM uint32_t OC5FE    : 1;            /*!< [2..2] desc OC5FE                                                         */
        __IOM uint32_t OC5PE    : 1;            /*!< [3..3] desc OC5PE                                                         */
        __IOM uint32_t OC5M     : 3;            /*!< [6..4] desc OC5M                                                          */
        __IOM uint32_t OC5CE    : 1;            /*!< [7..7] desc OC5CE                                                         */
        __IOM uint32_t CC6S     : 2;            /*!< [9..8] desc CC6S                                                          */
        __IOM uint32_t OC6FE    : 1;            /*!< [10..10] desc OC6FE                                                       */
        __IOM uint32_t OC6PE    : 1;            /*!< [11..11] desc OC6PE                                                       */
        __IOM uint32_t OC6M     : 3;            /*!< [14..12] desc OC6M                                                        */
        __IOM uint32_t OC6CE    : 1;            /*!< [15..15] desc OC6CE                                                       */
        __IOM uint32_t OC5MH    : 1;            /*!< [16..16] desc OC5MH                                                       */
        __IM  uint32_t          : 7;
        __IOM uint32_t OC6MH    : 1;            /*!< [24..24] desc OC6MH                                                       */
      } CCMR3CMP_f;
    } ;
  };
  
  union {
    __IOM uint32_t DTR2;                        /*!< (@ 0x00000054) dead-time register2                                        */
    
    struct {
      __IOM uint32_t DTGF       : 8;            /*!< [7..0] desc DTGF                                                          */
      __IM  uint32_t            : 8;
      __IOM uint32_t DTAE       : 1;            /*!< [16..16] desc DTAE                                                        */
      __IOM uint32_t DTPE       : 1;            /*!< [17..17] desc DTPE                                                        */
    } DTR2_f;
  } ;
  
  union {
    __IOM uint32_t ECR;                         /*!< (@ 0x00000058) Encoder control Register                                   */
    
    struct {
      __IOM uint32_t IE         : 1;            /*!< [0..0] desc IE                                                            */
      __IOM uint32_t IDIR       : 2;            /*!< [2..1] desc IDIR                                                          */
      __IM  uint32_t            : 2;
      __IOM uint32_t FIDX       : 1;            /*!< [5..5] desc FIDX                                                          */
      __IOM uint32_t IPOS       : 2;            /*!< [7..6] desc IPOS                                                          */
    } ECR_f;
  } ;
  
  union {
    __IOM uint32_t TISEL1;                      /*!< (@ 0x0000005C) Timer Input Select Register1                               */
    
    struct {
      __IOM uint32_t TI1SEL     : 4;            /*!< [3..0] desc TI1SEL                                                        */
      __IM  uint32_t            : 4;
      __IOM uint32_t TI2SEL     : 4;            /*!< [11..8] desc TI2SEL                                                       */
      __IM  uint32_t            : 4;
      __IOM uint32_t TI3SEL     : 4;            /*!< [19..16] desc TI3SEL                                                      */
      __IM  uint32_t            : 4;
      __IOM uint32_t TI4SEL     : 4;            /*!< [27..24] desc TI4SEL                                                      */
    } TISEL1_f;
  } ;
  
  union {
    __IOM uint32_t AF1;                         /*!< (@ 0x00000060) Alternate function Register1                               */
    
    struct {
      __IOM uint32_t BKINE      : 1;            /*!< [0..0] desc BKINE                                                         */
      __IOM uint32_t BKVC1E     : 1;            /*!< [1..1] desc BKVC1E                                                        */
      __IOM uint32_t BKVC2E     : 1;            /*!< [2..2] desc BKVC2E                                                        */
      __IOM uint32_t BKVC3E     : 1;            /*!< [3..3] desc BKVC3E                                                        */
      __IOM uint32_t BKVC4E     : 1;            /*!< [4..4] desc BKVC4E                                                        */
      __IM  uint32_t            : 4;
      __IOM uint32_t BKINP      : 1;            /*!< [9..9] desc BKINP                                                         */
      __IOM uint32_t BKVC1P     : 1;            /*!< [10..10] desc BKVC1P                                                      */
      __IOM uint32_t BKVC2P     : 1;            /*!< [11..11] desc BKVC2P                                                      */
      __IOM uint32_t BKVC3P     : 1;            /*!< [12..12] desc BKVC3P                                                      */
      __IOM uint32_t BKVC4P     : 1;            /*!< [13..13] desc BKVC4P                                                      */
      __IM  uint32_t            : 2;
      __IOM uint32_t ETRSEL     : 4;            /*!< [19..16] desc ETRSEL                                                      */
    } AF1_f;
  } ;
  
  union {
    __IOM uint32_t AF2;                         /*!< (@ 0x00000064) Alternate function Register2                               */
    
    struct {
      __IOM uint32_t BK2INE     : 1;            /*!< [0..0] desc BK2INE                                                        */
      __IOM uint32_t BK2VC1E    : 1;            /*!< [1..1] desc BK2VC1E                                                       */
      __IOM uint32_t BK2VC2E    : 1;            /*!< [2..2] desc BK2VC2E                                                       */
      __IOM uint32_t BK2VC3E    : 1;            /*!< [3..3] desc BK2VC3E                                                       */
      __IOM uint32_t BK2VC4E    : 1;            /*!< [4..4] desc BK2VC4E                                                       */
      __IM  uint32_t            : 4;
      __IOM uint32_t BK2INP     : 1;            /*!< [9..9] desc BK2INP                                                        */
      __IOM uint32_t BK2VC1P    : 1;            /*!< [10..10] desc BK2VC1P                                                     */
      __IOM uint32_t BK2VC2P    : 1;            /*!< [11..11] desc BK2VC2P                                                     */
      __IOM uint32_t BK2VC3P    : 1;            /*!< [12..12] desc BK2VC3P                                                     */
      __IOM uint32_t BK2VC4P    : 1;            /*!< [13..13] desc BK2VC4P                                                     */
      __IM  uint32_t            : 2;
      __IOM uint32_t OCRSEL     : 4;            /*!< [19..16] desc OCRSEL                                                      */
    } AF2_f;
  } ;
  __IM  uint32_t  RESERVED;
  
  union {
    __IOM uint32_t TISEL2;                      /*!< (@ 0x0000006C) Timer Input Select Register2                               */
    
    struct {
      __IOM uint32_t TI5SEL     : 4;            /*!< [3..0] desc TI5SEL                                                        */
      __IM  uint32_t            : 4;
      __IOM uint32_t TI6SEL     : 4;            /*!< [11..8] desc TI6SEL                                                       */
    } TISEL2_f;
  } ;
  
  union {
    __IOM uint32_t ICR;                         /*!< (@ 0x00000070) Interrupt clean register                                   */
    
    struct {
      __IOM uint32_t UIF        : 1;            /*!< [0..0] desc UIF                                                           */
      __IOM uint32_t CC1IF      : 1;            /*!< [1..1] desc CC1IF                                                         */
      __IOM uint32_t CC2IF      : 1;            /*!< [2..2] desc CC2IF                                                         */
      __IOM uint32_t CC3IF      : 1;            /*!< [3..3] desc CC3IF                                                         */
      __IOM uint32_t CC4IF      : 1;            /*!< [4..4] desc CC4IF                                                         */
      __IOM uint32_t COMIF      : 1;            /*!< [5..5] desc COMIF                                                         */
      __IOM uint32_t TIF        : 1;            /*!< [6..6] desc TIF                                                           */
      __IOM uint32_t BIF        : 1;            /*!< [7..7] desc BIF                                                           */
      __IOM uint32_t B2IF       : 1;            /*!< [8..8] desc B2IF                                                          */
      __IOM uint32_t CC1OF      : 1;            /*!< [9..9] desc CC1OF                                                         */
      __IOM uint32_t CC2OF      : 1;            /*!< [10..10] desc CC2OF                                                       */
      __IOM uint32_t CC3OF      : 1;            /*!< [11..11] desc CC3OF                                                       */
      __IOM uint32_t CC4OF      : 1;            /*!< [12..12] desc CC4OF                                                       */
      __IOM uint32_t SBIF       : 1;            /*!< [13..13] desc SBIF                                                        */
      __IM  uint32_t            : 2;
      __IOM uint32_t CC5IF      : 1;            /*!< [16..16] desc CC5IF                                                       */
      __IOM uint32_t CC6IF      : 1;            /*!< [17..17] desc CC6IF                                                       */
      __IOM uint32_t CC5OF      : 1;            /*!< [18..18] desc CC5OF                                                       */
      __IOM uint32_t CC6OF      : 1;            /*!< [19..19] desc CC6OF                                                       */
      __IOM uint32_t IDXF       : 1;            /*!< [20..20] desc IDXF                                                        */
      __IOM uint32_t DIRF       : 1;            /*!< [21..21] desc DIRF                                                        */
      __IOM uint32_t IERRF      : 1;            /*!< [22..22] desc IERRF                                                       */
      __IOM uint32_t TERRF      : 1;            /*!< [23..23] desc TERRF                                                       */
    } ICR_f;
  } ;
} ATIM_TypeDef;                                    /*!< Size = 116 (0x74)                                                         */



/* =========================================================================================================================== */
/* ================                                            BGR                                            ================ */
/* =========================================================================================================================== */


/**
  * @brief BGR (BGR)
  */

typedef struct {                                /*!< (@ 0x400000FC) BGR Structure                                              */
  
  union {
    __IOM uint32_t CR;                          /*!< (@ 0x00000000) Control register1                                          */
    
    struct {
      __IOM uint32_t BGREN      : 1;            /*!< [0..0] desc BGREN                                                         */
      __IOM uint32_t TSEN       : 1;            /*!< [1..1] desc TSEN                                                          */
    } CR_f;
  } ;
} BGR_TypeDef;                                     /*!< Size = 4 (0x4)                                                            */



/* =========================================================================================================================== */
/* ================                                           BTIM1                                           ================ */
/* =========================================================================================================================== */


/**
  * @brief Base Timer 1 (BTIM1)
  */

typedef struct {                                /*!< (@ 0x40004800) BTIM1 Structure                                            */
  
  union {
    __IOM uint32_t CR1;                         /*!< (@ 0x00000000) Control register1                                          */
    
    struct {
      __IOM uint32_t EN         : 1;            /*!< [0..0] desc EN                                                            */
      __IOM uint32_t UDIS       : 1;            /*!< [1..1] desc UDIS                                                          */
      __IOM uint32_t URS        : 1;            /*!< [2..2] desc URS                                                           */
      __IOM uint32_t ONESHOT    : 1;            /*!< [3..3] desc ONESHOT                                                       */
      __IM  uint32_t            : 7;
      __IOM uint32_t UIFREMAP   : 1;            /*!< [11..11] desc UIFREMAP                                                    */
      __IM  uint32_t            : 3;
      __IOM uint32_t TOGEN      : 1;            /*!< [15..15] desc TOGEN                                                       */
    } CR1_f;
  } ;
  
  union {
    __IOM uint32_t CR2;                         /*!< (@ 0x00000004) Control register2                                          */
    
    struct {
      __IM  uint32_t            : 4;
      __IOM uint32_t MMS        : 3;            /*!< [6..4] desc MMS                                                           */
    } CR2_f;
  } ;
  
  union {
    __IOM uint32_t SMCR;                        /*!< (@ 0x00000008) Slave Mode Control register                                */
    
    struct {
      __IOM uint32_t SMS        : 3;            /*!< [2..0] desc SMS                                                           */
      __IOM uint32_t RSTISRC    : 4;            /*!< [6..3] desc RSTISRC                                                       */
      __IOM uint32_t TRGISRC    : 4;            /*!< [10..7] desc TRGISRC                                                      */
      __IOM uint32_t MSM        : 1;            /*!< [11..11] desc MSM                                                         */
      __IOM uint32_t TRGIFLT    : 3;            /*!< [14..12] desc TRGIFLT                                                     */
      __IM  uint32_t            : 1;
      __IOM uint32_t RSTIPOL    : 1;            /*!< [16..16] desc RSTIPOL                                                     */
      __IOM uint32_t TRGIPOL    : 1;            /*!< [17..17] desc TRGIPOL                                                     */
    } SMCR_f;
  } ;
  
  union {
    __IOM uint32_t DIER;                         /*!< (@ 0x0000000C) Interrupt enable register                                  */
    
    struct {
      __IOM uint32_t UIE        : 1;            /*!< [0..0] desc UIE                                                           */
      __IM  uint32_t            : 5;
      __IOM uint32_t TIE        : 1;            /*!< [6..6] desc TIE                                                           */
            uint32_t            : 1;
      __IOM uint32_t UDE        : 1;            /*!< [8..8] desc UDE                                                                  */
            uint32_t            : 5;
      __IOM uint32_t TDE        : 1;            /*!< [14..14] desc TDE                                                                  */
    } DIER_f;
  } ;
  
  union {
    __IM  uint32_t ISR;                         /*!< (@ 0x00000010) Interrupt status register                                  */
    
    struct {
      __IM  uint32_t UIF        : 1;            /*!< [0..0] desc UIF                                                           */
      __IM  uint32_t            : 5;
      __IM  uint32_t TIF        : 1;            /*!< [6..6] desc TIF                                                           */
    } ISR_f;
  } ;
  
  union {
    __OM  uint32_t EGR;                         /*!< (@ 0x00000014) Event Generate register                                    */
    
    struct {
      __OM  uint32_t UG         : 1;            /*!< [0..0] desc UG                                                            */
      __IM  uint32_t            : 5;
      __OM  uint32_t TG         : 1;            /*!< [6..6] desc TG                                                            */
    } EGR_f;
  } ;
  
  union {
    __IOM uint32_t ICR;                         /*!< (@ 0x00000018) Interrupt flag clear register                              */
    
    struct {
      __IOM uint32_t UIF        : 1;            /*!< [0..0] desc UIF                                                           */
      __IM  uint32_t            : 5;
      __IOM uint32_t TIF        : 1;            /*!< [6..6] desc TIF                                                           */
    } ICR_f;
  } ;
  __IM  uint32_t  RESERVED[2];
  
  union {
    __IOM uint32_t CNT;                         /*!< (@ 0x00000024) Counter Register                                           */
    
    struct {
      __IOM uint32_t CNT        : 16;           /*!< [15..0] desc CNT                                                          */
      __IM  uint32_t            : 15;
      __IM  uint32_t UIFCPY     : 1;            /*!< [31..31] desc UIFCPY                                                      */
    } CNT_f;
  } ;
  
  union {
    __IOM uint32_t PSC;                         /*!< (@ 0x00000028) Prescaler Control Register                                 */
    
    struct {
      __IOM uint32_t PSC        : 16;           /*!< [15..0] desc PSC                                                          */
    } PSC_f;
  } ;
  
  union {
    __IOM uint32_t ARR;                         /*!< (@ 0x0000002C) Auto Reload Register                                       */
    
    struct {
      __IOM uint32_t ARR        : 16;           /*!< [15..0] desc ARR                                                          */
    } ARR_f;
  } ;
} BTIM_TypeDef;                                    /*!< Size = 48 (0x30)                                                          */



/* =========================================================================================================================== */
/* ================                                          CORDIC                                           ================ */
/* =========================================================================================================================== */


/**
  * @brief desc CORDIC (CORDIC)
  */

typedef struct {                                /*!< (@ 0x40023400) CORDIC Structure                                           */
  
  union {
    __IOM uint32_t CSR;                         /*!< (@ 0x00000000) Control and State register                                 */
    
    struct {
      __IOM uint32_t FUNC       : 4;            /*!< [3..0] desc FUNC                                                          */
      __IOM uint32_t SCALE      : 3;            /*!< [6..4] desc SCALE                                                         */
      __IOM uint32_t FORMAT     : 1;            /*!< [7..7] desc FORMAT                                                        */
      __IOM uint32_t ITER       : 4;            /*!< [11..8] desc ITER                                                         */
      __IOM uint32_t COMP       : 1;            /*!< [12..12] desc COMP                                                        */
      __IOM uint32_t IE         : 1;            /*!< [13..13] desc IE                                                          */
      __IOM uint32_t DMAEOC     : 1;            /*!< [14..14] desc DMAEOC                                                      */
      __IOM uint32_t DMAIDLE    : 1;            /*!< [15..15] desc DMAIDLE                                                     */
      __IM  uint32_t EOC        : 1;            /*!< [16..16] desc EOC                                                         */
      __IM  uint32_t BUSY       : 1;            /*!< [17..17] desc BUSY                                                        */
    } CSR_f;
  } ;
  
  union {
    __IOM uint32_t X;                           /*!< (@ 0x00000004) Data register X                                            */
    
    struct {
      __IOM uint32_t X          : 32;           /*!< [31..0] desc DATA                                                         */
    } X_f;
  } ;
  
  union {
    __IOM uint32_t Y;                           /*!< (@ 0x00000008) Data register Y                                            */
    
    struct {
      __IOM uint32_t Y          : 32;           /*!< [31..0] desc DATA                                                         */
    } Y_f;
  } ;
  
  union {
    __IOM uint32_t Z;                           /*!< (@ 0x0000000C) Data register Y                                            */
    
    struct {
      __IOM uint32_t Z          : 32;           /*!< [31..0] desc DATA                                                         */
    } Z_f;
  } ;
} CORDIC_TypeDef;                                  /*!< Size = 16 (0x10)                                                          */



/* =========================================================================================================================== */
/* ================                                            CRC                                            ================ */
/* =========================================================================================================================== */


/**
  * @brief desc CRC (CRC)
  */

typedef struct {                                /*!< (@ 0x40023000) CRC Structure                                              */
  
  union {
    __IOM uint32_t CR;                          /*!< (@ 0x00000000) Control register                                           */
    
    struct {
      __IOM uint32_t MODE       : 4;            /*!< [3..0] desc MODE                                                          */
    } CR_f;
  } ;
  __IM  uint32_t  RESERVED;
  
  union {
    __IOM uint32_t DR;                          /*!< (@ 0x00000008) Data register                                              */
    
    struct {
      __IOM uint32_t DR         : 8;            /*!< [7..0] desc DR                                                            */
    } DR_f;
  } ;
  
  union {
    __IM  uint32_t RESULT;                      /*!< (@ 0x0000000C) Result register                                            */
    
    struct {
      __IM  uint32_t RESULT     : 16;           /*!< [15..0] desc RESULT                                                       */
    } RESULT_f;
  } ;
} CRC_TypeDef;                                     /*!< Size = 16 (0x10)                                                          */



/* =========================================================================================================================== */
/* ================                                            DAC                                            ================ */
/* =========================================================================================================================== */


/**
  * @brief desc DAC (DAC)
  */

typedef struct {                                /*!< (@ 0x400000C0) DAC Structure                                              */
  
  union {
    __IOM uint32_t CR0;                         /*!< (@ 0x00000000) Control register                                           */
    
    struct {
      __IOM uint32_t EN1        : 1;            /*!< [0..0] desc EN1                                                           */
      __IOM uint32_t TEN1       : 1;            /*!< [1..1] desc TEN1                                                          */
      __IOM uint32_t TSEL1      : 4;            /*!< [5..2] desc TSEL1                                                         */
      __IOM uint32_t WAVE1      : 2;            /*!< [7..6] desc WAVE1                                                         */
      __IOM uint32_t MAMP1      : 4;            /*!< [11..8] desc MAMP1                                                        */
      __IOM uint32_t DMAEN1     : 1;            /*!< [12..12] desc DMAEN1                                                      */
      __IOM uint32_t DMAUDRIE1  : 1;            /*!< [13..13] desc DMAUDRIE1                                                   */
      __IM  uint32_t            : 2;
      __IOM uint32_t EN2        : 1;            /*!< [16..16] desc EN2                                                         */
      __IOM uint32_t TEN2       : 1;            /*!< [17..17] desc TEN2                                                        */
      __IOM uint32_t TSEL2      : 4;            /*!< [21..18] desc TSEL2                                                       */
      __IOM uint32_t WAVE2      : 2;            /*!< [23..22] desc WAVE2                                                       */
      __IOM uint32_t MAMP2      : 4;            /*!< [27..24] desc MAMP2                                                       */
      __IOM uint32_t DMAEN2     : 1;            /*!< [28..28] desc DMAEN2                                                      */
      __IOM uint32_t DMAUDRIE2  : 1;            /*!< [29..29] desc DMAUDRIE2                                                   */
    } CR0_f;
  } ;
  
  union {
    __IOM uint32_t SWTRGR;                      /*!< (@ 0x00000004) Data register                                              */
    
    struct {
      __IOM uint32_t SWTRIG1    : 1;            /*!< [0..0] desc SWTRIG1                                                       */
      __IOM uint32_t SWTRIG2    : 1;            /*!< [1..1] desc SWTRIG2                                                       */
    } SWTRGR_f;
  } ;
  
  union {
    __IOM uint32_t DHR12R1;                     /*!< (@ 0x00000008) Result register                                            */
    
    struct {
      __IOM uint32_t DATA       : 12;           /*!< [11..0] desc DATA                                                         */
    } DHR12R1_f;
  } ;
  
  union {
    __IOM uint32_t DHR12L1;                     /*!< (@ 0x0000000C) Result register                                            */
    
    struct {
      __IM  uint32_t            : 4;
      __IOM uint32_t DATA       : 12;           /*!< [15..4] desc DATA                                                         */
    }DHR12L1_f;
  } ;
  
  union {
    __IOM uint32_t DHR8R1;                      /*!< (@ 0x00000010) Result register                                            */
    
    struct {
      __IM  uint32_t            : 4;
      __IOM uint32_t DATA       : 4;            /*!< [7..4] desc DATA                                                          */
    } DHR8R1_f;
  } ;
  
  union {
    __IOM uint32_t DHR12R2;                     /*!< (@ 0x00000014) Result register                                            */
    
    struct {
      __IOM uint32_t DATA       : 12;           /*!< [11..0] desc DATA                                                         */
    } DHR12R2_f;
  } ;
  
  union {
    __IOM uint32_t DHR12L2;                    /*!< (@ 0x00000018) Result register                                            */
    
    struct {
      __IM  uint32_t            : 4;
      __IOM uint32_t DATA       : 12;           /*!< [15..4] desc DATA                                                         */
    } DHR12L2_f;
  } ;
  
  union {
    __IOM uint32_t DHR8R2;                      /*!< (@ 0x0000001C) Result register                                            */
    
    struct {
      __IM  uint32_t            : 4;
      __IOM uint32_t DATA       : 4;            /*!< [7..4] desc DATA                                                          */
    } DHR8R2_f;
  } ;
  
  union {
    __IOM uint32_t DHR12RD;                     /*!< (@ 0x00000020) Result register                                            */
    
    struct {
      __IOM uint32_t C1DATA     : 12;           /*!< [11..0] desc C1DATA                                                       */
      __IM  uint32_t            : 4;
      __IOM uint32_t C2DATA     : 12;           /*!< [27..16] desc C2DATA                                                      */
    } DHR12RD_f;
  } ;
  
  union {
    __IOM uint32_t DHR12LD;                     /*!< (@ 0x00000024) Result register                                            */
    
    struct {
      __IM  uint32_t            : 4;
      __IOM uint32_t C1DATA     : 12;           /*!< [15..4] desc C1DATA                                                       */
      __IM  uint32_t            : 4;
      __IOM uint32_t C2DATA     : 12;           /*!< [31..20] desc C2DATA                                                      */
    } DHR12LD_f;
  } ;
  
  union {
    __IOM uint32_t DHR8RD;                      /*!< (@ 0x00000028) Result register                                            */
    
    struct {
      __IOM uint32_t C1DATA     : 8;            /*!< [7..0] desc C1DATA                                                        */
      __IOM uint32_t C2DATA     : 8;            /*!< [15..8] desc C2DATA                                                       */
    } DHR8RD_f;
  } ;
  
  union {
    __IOM uint32_t DOR1;                        /*!< (@ 0x0000002C) Result register                                            */
    
    struct {
      __IOM uint32_t DATA       : 12;           /*!< [12..0] desc DATA                                                          */
      __IM  uint32_t            : 3;
      __IOM uint32_t DMAUDR     : 1;            /*!< [15..15] desc DMAUDR                                                      */
    } DOR1_f;
  } ;
  
  union {
    __IOM uint32_t DOR2;                       /*!< (@ 0x00000030) Result register                                            */
    
    struct {
      __IOM uint32_t DATA       : 12;           /*!< [11..0] desc DATA                                                          */
      __IM  uint32_t            : 3;
      __IOM uint32_t DMAUDR     : 1;            /*!< [15..15] desc DMAUDR                                                      */
    } DOR2_f;
  } ;
  
  union {
    __IOM uint32_t CR1;                         /*!< (@ 0x00000034) Result register                                            */
    
    struct {
      __IOM uint32_t C1OUT      : 1;            /*!< [0..0] desc C1OUT                                                         */
      __IOM uint32_t C2OUT      : 1;            /*!< [1..1] desc C2OUT                                                         */
    } CR1_f;
  } ;
} DAC_TypeDef;                                     /*!< Size = 56 (0x38)                                                          */



/* =========================================================================================================================== */
/* ================                                            DMA                                            ================ */
/* =========================================================================================================================== */


/**
  * @brief desc DMA (DMA)
  */

typedef struct {                                /*!< (@ 0x40020000) DMA Structure                                              */
  
  union {
    __IM  uint32_t ISR;                         /*!< (@ 0x00000000) Interrupt status register                                  */
    
    struct {
      __IM  uint32_t TC1        : 1;            /*!< [0..0] desc TC1                                                           */
      __IM  uint32_t TE1        : 1;            /*!< [1..1] desc TE1                                                           */
      __IM  uint32_t            : 2;
      __IM  uint32_t TC2        : 1;            /*!< [4..4] desc TC2                                                           */
      __IM  uint32_t TE2        : 1;            /*!< [5..5] desc TE2                                                           */
      __IM  uint32_t            : 2;
      __IM  uint32_t TC3        : 1;            /*!< [8..8] desc TC3                                                           */
      __IM  uint32_t TE3        : 1;            /*!< [9..9] desc TE3                                                           */
      __IM  uint32_t            : 2;
      __IM  uint32_t TC4        : 1;            /*!< [12..12] desc TC4                                                         */
      __IM  uint32_t TE4        : 1;            /*!< [13..13] desc TE4                                                         */
    } ISR_f;
  } ;
  
  union {
    __IOM uint32_t ICR;                         /*!< (@ 0x00000004) Interrupt flag clear register                              */
    
    struct {
      __IOM uint32_t TC1        : 1;            /*!< [0..0] desc TC1                                                           */
      __IOM uint32_t TE1        : 1;            /*!< [1..1] desc TE1                                                           */
      __IM  uint32_t            : 2;
      __IOM uint32_t TC2        : 1;            /*!< [4..4] desc TC2                                                           */
      __IOM uint32_t TE2        : 1;            /*!< [5..5] desc TE2                                                           */
      __IM  uint32_t            : 2;
      __IOM uint32_t TC3        : 1;            /*!< [8..8] desc TC3                                                           */
      __IOM uint32_t TE3        : 1;            /*!< [9..9] desc TE3                                                           */
      __IM  uint32_t            : 2;
      __IOM uint32_t TC4        : 1;            /*!< [12..12] desc TC4                                                         */
      __IOM uint32_t TE4        : 1;            /*!< [13..13] desc TE4                                                         */
    } ICR_f;
  } ;
  __IM  uint32_t  RESERVED[6];
  
  union {
    __IOM uint32_t CSR1;                        /*!< (@ 0x00000020) Channel1 control and status register                       */
    
    struct {
      __IOM uint32_t EN         : 1;            /*!< [0..0] desc EN                                                            */
      __IOM uint32_t TCIE       : 1;            /*!< [1..1] desc TCIE                                                          */
      __IOM uint32_t TEIE       : 1;            /*!< [2..2] desc TEIE                                                          */
      __IOM uint32_t TRANS      : 1;            /*!< [3..3] desc TRANS                                                         */
      __IOM uint32_t SRCINC     : 1;            /*!< [4..4] desc SRCINC                                                        */
      __IOM uint32_t DSTINC     : 1;            /*!< [5..5] desc DSTINC                                                        */
      __IOM uint32_t SIZE       : 2;            /*!< [7..6] desc SIZE                                                          */
      __IOM uint32_t STATUS     : 3;            /*!< [10..8] desc STATUS                                                       */
      __IOM uint32_t RESTART    : 1;            /*!< [11..11] desc RESTART                                                     */
      __IM  uint32_t TC         : 1;            /*!< [12..12] desc TC                                                          */
      __IM  uint32_t TE         : 1;            /*!< [13..13] desc TE                                                          */
      __IOM uint32_t SRCLOAD    : 1;            /*!< [14..14] desc SRCLOAD                                                     */
      __IOM uint32_t DSTLOAD    : 1;            /*!< [15..15] desc DSTLOAD                                                     */
    } CSR1_f;
  } ;
  
  union {
    __IOM uint32_t CNT1;                        /*!< (@ 0x00000024) Channel1 counter register                                  */
    
    struct {
      __IOM uint32_t CNT        : 16;           /*!< [15..0] desc CNT                                                          */
      __IOM uint32_t REPEAT     : 4;            /*!< [19..16] desc REPEAT                                                      */
    } CNT1_f;
  } ;
  
  union {
    __IOM uint32_t SRCADDR1;                    /*!< (@ 0x00000028) Channel1 source address register                           */
    
    struct {
      __IOM uint32_t SRCADDR    : 32;           /*!< [31..0] desc SRCADDR                                                      */
    } SRCADDR1_f;
  } ;
  
  union {
    __IOM uint32_t DSTADDR1;                    /*!< (@ 0x0000002C) Channel1 destination address register                      */
    
    struct {
      __IOM uint32_t DSTADDR    : 32;           /*!< [31..0] desc DSTADDR                                                      */
    } DSTADDR1_f;
  } ;
  
  union {
    __IOM uint32_t TRIG1;                       /*!< (@ 0x00000030) Channel1 trigger register                                  */
    
    struct {
      __IOM uint32_t TYPE       : 1;            /*!< [0..0] desc TYPE                                                          */
      __IOM uint32_t SOFTSRC    : 1;            /*!< [1..1] desc SOFTSRC                                                       */
      __IOM uint32_t HARDSRC    : 6;            /*!< [7..2] desc HARDSRC                                                       */
    } TRIG1_f;
  } ;
  
  union {
    __IOM uint32_t CCNT1;                       /*!< (@ 0x00000034) Channel1 trigger register                                  */
    
    struct {
      __IOM uint32_t CCNT       : 16;           /*!< [15..0] desc CCNT                                                         */
      __IOM uint32_t CREPEAT    : 4;            /*!< [19..16] desc CREPEAT                                                     */
    } CCNT1_f;
  } ;
  
  union {
    __IM  uint32_t CSRCADDR1;                   /*!< (@ 0x00000038) Channel1 source address register                           */
    
    struct {
      __IM  uint32_t CSRCADDR   : 32;           /*!< [31..0] desc CSRCADDR                                                     */
    } CSRCADDR1_f;
  } ;
  
  union {
    __IM  uint32_t CDSTADDR1;                   /*!< (@ 0x0000003C) Channel1 destination address register                      */
    
    struct {
      __IM  uint32_t CDSTADDR   : 32;           /*!< [31..0] desc CDSTADDR                                                     */
    } CDSTADDR1_f;
  } ;
  
  union {
    __IOM uint32_t CSR2;                        /*!< (@ 0x00000040) Channel1 control and status register                       */
    
    struct {
      __IOM uint32_t EN         : 1;            /*!< [0..0] desc EN                                                            */
      __IOM uint32_t TCIE       : 1;            /*!< [1..1] desc TCIE                                                          */
      __IOM uint32_t TEIE       : 1;            /*!< [2..2] desc TEIE                                                          */
      __IOM uint32_t TRANS      : 1;            /*!< [3..3] desc TRANS                                                         */
      __IOM uint32_t SRCINC     : 1;            /*!< [4..4] desc SRCINC                                                        */
      __IOM uint32_t DSTINC     : 1;            /*!< [5..5] desc DSTINC                                                        */
      __IOM uint32_t SIZE       : 2;            /*!< [7..6] desc SIZE                                                          */
      __IOM uint32_t STATUS     : 3;            /*!< [10..8] desc STATUS                                                       */
      __IOM uint32_t RESTART    : 1;            /*!< [11..11] desc RESTART                                                     */
      __IM  uint32_t TC         : 1;            /*!< [12..12] desc TC                                                          */
      __IM  uint32_t TE         : 1;            /*!< [13..13] desc TE                                                          */
      __IOM uint32_t SRCLOAD    : 1;            /*!< [14..14] desc SRCLOAD                                                     */
      __IOM uint32_t DSTLOAD    : 1;            /*!< [15..15] desc DSTLOAD                                                     */
    } CSR2_f;
  } ;
  
  union {
    __IOM uint32_t CNT2;                        /*!< (@ 0x00000044) Channel1 counter register                                  */
    
    struct {
      __IOM uint32_t CNT        : 16;           /*!< [15..0] desc CNT                                                          */
      __IOM uint32_t REPEAT     : 4;            /*!< [19..16] desc REPEAT                                                      */
    } CNT2_f;
  } ;
  
  union {
    __IOM uint32_t SRCADDR2;                    /*!< (@ 0x00000048) Channel1 source address register                           */
    
    struct {
      __IOM uint32_t SRCADDR    : 32;           /*!< [31..0] desc SRCADDR                                                      */
    } SRCADDR2_f;
  } ;
  
  union {
    __IOM uint32_t DSTADDR2;                    /*!< (@ 0x0000004C) Channel1 destination address register                      */
    
    struct {
      __IOM uint32_t DSTADDR    : 32;           /*!< [31..0] desc DSTADDR                                                      */
    } DSTADDR2_f;
  } ;
  
  union {
    __IOM uint32_t TRIG2;                       /*!< (@ 0x00000050) Channel1 trigger register                                  */
    
    struct {
      __IOM uint32_t TYPE       : 1;            /*!< [0..0] desc TYPE                                                          */
      __IOM uint32_t SOFTSRC    : 1;            /*!< [1..1] desc SOFTSRC                                                       */
      __IOM uint32_t HARDSRC    : 6;            /*!< [7..2] desc HARDSRC                                                       */
    } TRIG2_f;
  } ;
  
  union {
    __IOM uint32_t CCNT2;                       /*!< (@ 0x00000054) Channel1 trigger register                                  */
    
    struct {
      __IOM uint32_t CCNT       : 16;           /*!< [15..0] desc CCNT                                                         */
      __IOM uint32_t CREPEAT    : 4;            /*!< [19..16] desc CREPEAT                                                     */
    } CCNT2_f;
  } ;
  
  union {
    __IM  uint32_t CSRCADDR2;                   /*!< (@ 0x00000058) Channel1 source address register                           */
    
    struct {
      __IM  uint32_t CSRCADDR   : 32;           /*!< [31..0] desc CSRCADDR                                                     */
    } CSRCADDR2_f;
  } ;
  
  union {
    __IM  uint32_t CDSTADDR2;                   /*!< (@ 0x0000005C) Channel1 destination address register                      */
    
    struct {
      __IM  uint32_t CDSTADDR   : 32;           /*!< [31..0] desc CDSTADDR                                                     */
    } CDSTADDR2_f;
  } ;
  
  union {
    __IOM uint32_t CSR3;                        /*!< (@ 0x00000060) Channel1 control and status register                       */
    
    struct {
      __IOM uint32_t EN         : 1;            /*!< [0..0] desc EN                                                            */
      __IOM uint32_t TCIE       : 1;            /*!< [1..1] desc TCIE                                                          */
      __IOM uint32_t TEIE       : 1;            /*!< [2..2] desc TEIE                                                          */
      __IOM uint32_t TRANS      : 1;            /*!< [3..3] desc TRANS                                                         */
      __IOM uint32_t SRCINC     : 1;            /*!< [4..4] desc SRCINC                                                        */
      __IOM uint32_t DSTINC     : 1;            /*!< [5..5] desc DSTINC                                                        */
      __IOM uint32_t SIZE       : 2;            /*!< [7..6] desc SIZE                                                          */
      __IOM uint32_t STATUS     : 3;            /*!< [10..8] desc STATUS                                                       */
      __IOM uint32_t RESTART    : 1;            /*!< [11..11] desc RESTART                                                     */
      __IM  uint32_t TC         : 1;            /*!< [12..12] desc TC                                                          */
      __IM  uint32_t TE         : 1;            /*!< [13..13] desc TE                                                          */
      __IOM uint32_t SRCLOAD    : 1;            /*!< [14..14] desc SRCLOAD                                                     */
      __IOM uint32_t DSTLOAD    : 1;            /*!< [15..15] desc DSTLOAD                                                     */
    } CSR3_f;
  } ;
  
  union {
    __IOM uint32_t CNT3;                        /*!< (@ 0x00000064) Channel1 counter register                                  */
    
    struct {
      __IOM uint32_t CNT        : 16;           /*!< [15..0] desc CNT                                                          */
      __IOM uint32_t REPEAT     : 4;            /*!< [19..16] desc REPEAT                                                      */
    } CNT3_f;
  } ;
  
  union {
    __IOM uint32_t SRCADDR3;                    /*!< (@ 0x00000068) Channel1 source address register                           */
    
    struct {
      __IOM uint32_t SRCADDR    : 32;           /*!< [31..0] desc SRCADDR                                                      */
    } SRCADDR3_f;
  } ;
  
  union {
    __IOM uint32_t DSTADDR3;                    /*!< (@ 0x0000006C) Channel1 destination address register                      */
    
    struct {
      __IOM uint32_t DSTADDR    : 32;           /*!< [31..0] desc DSTADDR                                                      */
    } DSTADDR3_f;
  } ;
  
  union {
    __IOM uint32_t TRIG3;                       /*!< (@ 0x00000070) Channel1 trigger register                                  */
    
    struct {
      __IOM uint32_t TYPE       : 1;            /*!< [0..0] desc TYPE                                                          */
      __IOM uint32_t SOFTSRC    : 1;            /*!< [1..1] desc SOFTSRC                                                       */
      __IOM uint32_t HARDSRC    : 6;            /*!< [7..2] desc HARDSRC                                                       */
    } TRIG3_f;
  } ;
  
  union {
    __IOM uint32_t CCNT3;                       /*!< (@ 0x00000074) Channel1 trigger register                                  */
    
    struct {
      __IOM uint32_t CCNT       : 16;           /*!< [15..0] desc CCNT                                                         */
      __IOM uint32_t CREPEAT    : 4;            /*!< [19..16] desc CREPEAT                                                     */
    } CCNT3_f;
  } ;
  
  union {
    __IM  uint32_t CSRCADDR3;                   /*!< (@ 0x00000078) Channel1 source address register                           */
    
    struct {
      __IM  uint32_t CSRCADDR   : 32;           /*!< [31..0] desc CSRCADDR                                                     */
    } CSRCADDR3_f;
  } ;
  
  union {
    __IM  uint32_t CDSTADDR3;                   /*!< (@ 0x0000007C) Channel1 destination address register                      */
    
    struct {
      __IM  uint32_t CDSTADDR   : 32;           /*!< [31..0] desc CDSTADDR                                                     */
    } CDSTADDR3_f;
  } ;
  
  union {
    __IOM uint32_t CSR4;                        /*!< (@ 0x00000080) Channel1 control and status register                       */
    
    struct {
      __IOM uint32_t EN         : 1;            /*!< [0..0] desc EN                                                            */
      __IOM uint32_t TCIE       : 1;            /*!< [1..1] desc TCIE                                                          */
      __IOM uint32_t TEIE       : 1;            /*!< [2..2] desc TEIE                                                          */
      __IOM uint32_t TRANS      : 1;            /*!< [3..3] desc TRANS                                                         */
      __IOM uint32_t SRCINC     : 1;            /*!< [4..4] desc SRCINC                                                        */
      __IOM uint32_t DSTINC     : 1;            /*!< [5..5] desc DSTINC                                                        */
      __IOM uint32_t SIZE       : 2;            /*!< [7..6] desc SIZE                                                          */
      __IOM uint32_t STATUS     : 3;            /*!< [10..8] desc STATUS                                                       */
      __IOM uint32_t RESTART    : 1;            /*!< [11..11] desc RESTART                                                     */
      __IM  uint32_t TC         : 1;            /*!< [12..12] desc TC                                                          */
      __IM  uint32_t TE         : 1;            /*!< [13..13] desc TE                                                          */
      __IOM uint32_t SRCLOAD    : 1;            /*!< [14..14] desc SRCLOAD                                                     */
      __IOM uint32_t DSTLOAD    : 1;            /*!< [15..15] desc DSTLOAD                                                     */
    } CSR4_f;
  } ;
  
  union {
    __IOM uint32_t CNT4;                        /*!< (@ 0x00000084) Channel1 counter register                                  */
    
    struct {
      __IOM uint32_t CNT        : 16;           /*!< [15..0] desc CNT                                                          */
      __IOM uint32_t REPEAT     : 4;            /*!< [19..16] desc REPEAT                                                      */
    } CNT4_f;
  } ;
  
  union {
    __IOM uint32_t SRCADDR4;                    /*!< (@ 0x00000088) Channel1 source address register                           */
    
    struct {
      __IOM uint32_t SRCADDR    : 32;           /*!< [31..0] desc SRCADDR                                                      */
    } SRCADDR4_f;
  } ;
  
  union {
    __IOM uint32_t DSTADDR4;                    /*!< (@ 0x0000008C) Channel1 destination address register                      */
    
    struct {
      __IOM uint32_t DSTADDR    : 32;           /*!< [31..0] desc DSTADDR                                                      */
    } DSTADDR4_f;
  } ;
  
  union {
    __IOM uint32_t TRIG4;                       /*!< (@ 0x00000090) Channel1 trigger register                                  */
    
    struct {
      __IOM uint32_t TYPE       : 1;            /*!< [0..0] desc TYPE                                                          */
      __IOM uint32_t SOFTSRC    : 1;            /*!< [1..1] desc SOFTSRC                                                       */
      __IOM uint32_t HARDSRC    : 6;            /*!< [7..2] desc HARDSRC                                                       */
    } TRIG4_f;
  } ;
  
  union {
    __IOM uint32_t CCNT4;                       /*!< (@ 0x00000094) Channel1 trigger register                                  */
    
    struct {
      __IOM uint32_t CCNT       : 16;           /*!< [15..0] desc CCNT                                                         */
      __IOM uint32_t CREPEAT    : 4;            /*!< [19..16] desc CREPEAT                                                     */
    } CCNT4_f;
  } ;
  
  union {
    __IM  uint32_t CSRCADDR4;                   /*!< (@ 0x00000098) Channel1 source address register                           */
    
    struct {
      __IM  uint32_t CSRCADDR   : 32;           /*!< [31..0] desc CSRCADDR                                                     */
    } CSRCADDR4_f;
  } ;
  
  union {
    __IM  uint32_t CDSTADDR4;                   /*!< (@ 0x0000009C) Channel1 destination address register                      */
    
    struct {
      __IM  uint32_t CDSTADDR   : 32;           /*!< [31..0] desc CDSTADDR                                                     */
    } CDSTADDR4_f;
  } ;
} DMA_TypeDef;                                     /*!< Size = 160 (0xa0)                                                         */



/* =========================================================================================================================== */
/* ================                                        DMACHANNEL1                                        ================ */
/* =========================================================================================================================== */


/**
  * @brief DMA Channel 1 (DMACHANNEL1)
  */

typedef struct {                                /*!< (@ 0x40020020) DMACHANNEL1 Structure                                      */
  
  union {
    __IOM uint32_t CSR;                         /*!< (@ 0x00000000) Channel1 control and status register                       */
    
    struct {
      __IOM uint32_t EN         : 1;            /*!< [0..0] desc EN                                                            */
      __IOM uint32_t TCIE       : 1;            /*!< [1..1] desc TCIE                                                          */
      __IOM uint32_t TEIE       : 1;            /*!< [2..2] desc TEIE                                                          */
      __IOM uint32_t TRANS      : 1;            /*!< [3..3] desc TRANS                                                         */
      __IOM uint32_t SRCINC     : 1;            /*!< [4..4] desc SRCINC                                                        */
      __IOM uint32_t DSTINC     : 1;            /*!< [5..5] desc DSTINC                                                        */
      __IOM uint32_t SIZE       : 2;            /*!< [7..6] desc SIZE                                                          */
      __IOM uint32_t STATUS     : 3;            /*!< [10..8] desc STATUS                                                       */
      __IOM uint32_t RESTART    : 1;            /*!< [11..11] desc RESTART                                                     */
      __IM  uint32_t TC         : 1;            /*!< [12..12] desc TC                                                          */
      __IM  uint32_t TE         : 1;            /*!< [13..13] desc TE                                                          */
      __IOM uint32_t SRCLOAD    : 1;            /*!< [14..14] desc SRCLOAD                                                     */
      __IOM uint32_t DSTLOAD    : 1;            /*!< [15..15] desc DSTLOAD                                                     */
    } CSR_f;
  } ;
  
  union {
    __IOM uint32_t CNT;                         /*!< (@ 0x00000004) Channel1 counter register                                  */
    
    struct {
      __IOM uint32_t CNT        : 16;           /*!< [15..0] desc CNT                                                          */
      __IOM uint32_t REPEAT     : 4;            /*!< [19..16] desc REPEAT                                                      */
    } CNT_f;
  } ;
  
  union {
    __IOM uint32_t SRCADDR;                     /*!< (@ 0x00000008) Channel1 source address register                           */
    
    struct {
      __IOM uint32_t SRCADDR    : 32;           /*!< [31..0] desc SRCADDR                                                      */
    } SRCADDR_f;
  } ;
  
  union {
    __IOM uint32_t DSTADDR;                     /*!< (@ 0x0000000C) Channel1 destination address register                      */
    
    struct {
      __IOM uint32_t DSTADDR    : 32;           /*!< [31..0] desc DSTADDR                                                      */
    } DSTADDR_f;
  } ;
  
  union {
    __IOM uint32_t TRIG;                        /*!< (@ 0x00000010) Channel1 trigger register                                  */
    
    struct {
      __IOM uint32_t TYPE       : 1;            /*!< [0..0] desc TYPE                                                          */
      __IOM uint32_t SOFTSRC    : 1;            /*!< [1..1] desc SOFTSRC                                                       */
      __IOM uint32_t HARDSRC    : 6;            /*!< [7..2] desc HARDSRC                                                       */
    } TRIG_f;
  } ;
  
  union {
    __IOM uint32_t CCNT;                        /*!< (@ 0x00000014) Channel1 trigger register                                  */
    
    struct {
      __IOM uint32_t CCNT       : 16;           /*!< [15..0] desc CCNT                                                         */
      __IOM uint32_t CREPEAT    : 4;            /*!< [19..16] desc CREPEAT                                                     */
    } CCNT_f;
  } ;
  
  union {
    __IM  uint32_t CSRCADDR;                    /*!< (@ 0x00000018) Channel1 source address register                           */
    
    struct {
      __IM  uint32_t CSRCADDR   : 32;           /*!< [31..0] desc CSRCADDR                                                     */
    } CSRCADDR_f;
  } ;
  
  union {
    __IM  uint32_t CDSTADDR;                    /*!< (@ 0x0000001C) Channel1 destination address register                      */
    
    struct {
      __IM  uint32_t CDSTADDR   : 32;           /*!< [31..0] desc CDSTADDR                                                     */
    } CDSTADDR_f;
  } ;
} DMACHANNEL_TypeDef;                              /*!< Size = 32 (0x20)                                                          */



/* =========================================================================================================================== */
/* ================                                            EAU                                            ================ */
/* =========================================================================================================================== */


/**
  * @brief desc EAU (EAU)
  */

typedef struct {                                /*!< (@ 0x40023200) EAU Structure                                              */
  
  union {
    __IOM uint32_t CSR;                         /*!< (@ 0x00000000) desc CSR                                                   */
    
    struct {
      __IOM uint32_t MODE       : 2;            /*!< [1..0] desc MODE                                                          */
      __IM  uint32_t OVR        : 1;            /*!< [2..2] desc OVR                                                           */
      __IM  uint32_t ZERO       : 1;            /*!< [3..3] desc ZERO                                                          */
      __IM  uint32_t BUSY       : 1;            /*!< [4..4] desc BUSY                                                          */
    } CSR_f;
  } ;
  
  union {
    __IOM uint32_t DIVIDEND;                    /*!< (@ 0x00000004) desc DIVIDEND                                              */
    
    struct {
      __IOM uint32_t DIVIDEND   : 32;           /*!< [31..0] desc DIVIDEND                                                     */
    } DIVIDEND_f;
  } ;
  
  union {
    __IOM uint32_t DIVISOR;                     /*!< (@ 0x00000008) desc DIVISOR                                               */
    
    struct {
      __IOM uint32_t DIVISOR    : 32;           /*!< [31..0] desc DIVISOR                                                      */
    } DIVISOR_f;
  } ;
  
  union {
    __IM  uint32_t QUOTIENT;                    /*!< (@ 0x0000000C) desc QUOTIENT                                              */
    
    struct {
      __IM  uint32_t QUOTIENT   : 32;           /*!< [31..0] desc QUOTIENT                                                     */
    } QUOTIENT_f;
  } ;
  
  union {
    __IM  uint32_t REMAINDER;                   /*!< (@ 0x00000010) desc REMAINDER                                             */
    
    struct {
      __IM  uint32_t REMAINDER  : 32;           /*!< [31..0] desc REMAINDER                                                    */
    } REMAINDER_f;
  } ;
} EAU_TypeDef;                                     /*!< Size = 20 (0x14)                                                          */



/* =========================================================================================================================== */
/* ================                                           FLASH                                           ================ */
/* =========================================================================================================================== */


/**
  * @brief desc FLASH (FLASH)
  */

typedef struct {                                /*!< (@ 0x40022000) FLASH Structure                                            */
  
  union {
    __IOM uint32_t CR1;                         /*!< (@ 0x00000000) Control register1                                          */
    
    struct {
      __IOM uint32_t MODE       : 2;            /*!< [1..0] desc MODE                                                          */
      __IM  uint32_t            : 3;
      __IM  uint32_t SECURITY   : 2;            /*!< [6..5] desc SECURITY                                                      */
      __IM  uint32_t            : 9;
      __OM  uint32_t KEY        : 16;           /*!< [31..16] desc KEY                                                         */
    } CR1_f;
  } ;
  
  union {
    __IOM uint32_t CR2;                         /*!< (@ 0x00000004) Control register2                                          */
    
    struct {
      __IOM uint32_t WAIT       : 3;            /*!< [2..0] desc WAIT                                                          */
      __IOM uint32_t FETCH      : 1;            /*!< [3..3] desc FETCH                                                         */
      __IOM uint32_t CACHE      : 1;            /*!< [4..4] desc CACHE                                                         */
      __IOM uint32_t CACHEINVALID : 1;          /*!< [5..5] desc CACHEINVALID                                                  */
      __IM  uint32_t            : 10;
      __OM  uint32_t KEY        : 16;           /*!< [31..16] desc KEY                                                         */
    } CR2_f;
  } ;
  
  union {
    __IOM uint32_t PAGELOCK;                    /*!< (@ 0x00000008) Page Write Erase Lock                                      */
    
    struct {
      __IOM uint32_t LOCK0      : 1;            /*!< [0..0] Page0 - 7                                                          */
      __IOM uint32_t LOCK1      : 1;            /*!< [1..1] Page8 - 15                                                         */
      __IOM uint32_t LOCK2      : 1;            /*!< [2..2] Page16 - 23                                                        */
      __IOM uint32_t LOCK3      : 1;            /*!< [3..3] Page24 - 31                                                        */
      __IOM uint32_t LOCK4      : 1;            /*!< [4..4] Page32 - 39                                                        */
      __IOM uint32_t LOCK5      : 1;            /*!< [5..5] Page40 - 47                                                        */
      __IOM uint32_t LOCK6      : 1;            /*!< [6..6] Page48 - 55                                                        */
      __IOM uint32_t LOCK7      : 1;            /*!< [7..7] Page56 - 63                                                        */
      __IOM uint32_t LOCK8      : 1;            /*!< [8..8] Page64 - 71                                                        */
      __IOM uint32_t LOCK9      : 1;            /*!< [9..9] Page72 - 79                                                        */
      __IOM uint32_t LOCK10     : 1;            /*!< [10..10] Page80 - 87                                                      */
      __IOM uint32_t LOCK11     : 1;            /*!< [11..11] Page88 - 95                                                      */
      __IOM uint32_t LOCK12     : 1;            /*!< [12..12] Page96 - 103                                                     */
      __IOM uint32_t LOCK13     : 1;            /*!< [13..13] Page104 - 111                                                    */
      __IOM uint32_t LOCK14     : 1;            /*!< [14..14] Page112 - 119                                                    */
      __IOM uint32_t LOCK15     : 1;            /*!< [15..15] Page120 - 127                                                    */
      __OM  uint32_t KEY        : 16;           /*!< [31..16] desc KEY                                                         */
    } PAGELOCK_f;
  } ;
  __IM  uint32_t  RESERVED[5];
  
  union {
    __IOM uint32_t IER;                         /*!< (@ 0x00000020) Interrupt enable register                                  */
    
    struct {
      __IOM uint32_t PC         : 1;            /*!< [0..0] desc PC                                                            */
      __IOM uint32_t PAGELOCK   : 1;            /*!< [1..1] desc PAGELOCK                                                      */
      __IOM uint32_t SDKERR     : 1;            /*!< [2..2] desc SDKERR                                                        */
      __IOM uint32_t CACHEON    : 1;            /*!< [3..3] desc CACHEON                                                       */
      __IOM uint32_t PROG       : 1;            /*!< [4..4] desc PROG                                                          */
    } IER_f;
  } ;
  
  union {
    __IM  uint32_t ISR;                         /*!< (@ 0x00000024) Interrupt status register                                  */
    
    struct {
      __IM  uint32_t PC         : 1;            /*!< [0..0] desc PC                                                            */
      __IM  uint32_t PAGELOCK   : 1;            /*!< [1..1] desc PAGELOCK                                                      */
      __IM  uint32_t SDKERR     : 1;            /*!< [2..2] desc SDKERR                                                        */
      __IM  uint32_t CACHEON    : 1;            /*!< [3..3] desc CACHEON                                                       */
      __IM  uint32_t PROG       : 1;            /*!< [4..4] desc PROG                                                          */
      __IM  uint32_t BUSY       : 1;            /*!< [5..5] desc BUSY                                                          */
    } ISR_f;
  } ;
  
  union {
    __IOM uint32_t ICR;                         /*!< (@ 0x00000028) Interrupt flag clear register                              */
    
    struct {
      __IOM uint32_t PC         : 1;            /*!< [0..0] desc PC                                                            */
      __IOM uint32_t PAGELOCK   : 1;            /*!< [1..1] desc PAGELOCK                                                      */
      __IOM uint32_t SDKERR     : 1;            /*!< [2..2] desc SDKERR                                                        */
      __IOM uint32_t CACHEON    : 1;            /*!< [3..3] desc CACHEON                                                       */
      __IOM uint32_t PROG       : 1;            /*!< [4..4] desc PROG                                                          */
    } ICR_f;
  } ;
  __IM  uint32_t  RESERVED1[17];
  
  union {
    __IM  uint32_t SDKCFR;                      /*!< (@ 0x00000070) SDK config register                                        */
    
    struct {
      __IM  uint32_t START      : 7;            /*!< [6..0] desc START                                                         */
            uint32_t            : 1;
      __IM  uint32_t END        : 7;            /*!< [14..8] desc END                                                          */
    } SDKCFR_f;
  } ;
} FLASH_TypeDef;                                   /*!< Size = 116 (0x74)                                                         */



/* =========================================================================================================================== */
/* ================                                           GPIOA                                           ================ */
/* =========================================================================================================================== */


/**
  * @brief desc GPIOA (GPIOA)
  */

typedef struct {                                /*!< (@ 0x48000000) GPIOA Structure                                            */
  
  union {
    __IOM uint32_t DIR;                         /*!< (@ 0x00000000) desc DIR                                                   */
    
    struct {
      __IOM uint32_t PIN0       : 1;            /*!< [0..0] desc PIN0                                                          */
      __IOM uint32_t PIN1       : 1;            /*!< [1..1] desc PIN1                                                          */
      __IOM uint32_t PIN2       : 1;            /*!< [2..2] desc PIN2                                                          */
      __IOM uint32_t PIN3       : 1;            /*!< [3..3] desc PIN3                                                          */
      __IOM uint32_t PIN4       : 1;            /*!< [4..4] desc PIN4                                                          */
      __IOM uint32_t PIN5       : 1;            /*!< [5..5] desc PIN5                                                          */
      __IOM uint32_t PIN6       : 1;            /*!< [6..6] desc PIN6                                                          */
      __IOM uint32_t PIN7       : 1;            /*!< [7..7] desc PIN7                                                          */
      __IOM uint32_t PIN8       : 1;            /*!< [8..8] desc PIN8                                                          */
      __IOM uint32_t PIN9       : 1;            /*!< [9..9] desc PIN9                                                          */
      __IOM uint32_t PIN10      : 1;            /*!< [10..10] desc PIN10                                                       */
      __IOM uint32_t PIN11      : 1;            /*!< [11..11] desc PIN11                                                       */
      __IOM uint32_t PIN12      : 1;            /*!< [12..12] desc PIN12                                                       */
      __IOM uint32_t PIN13      : 1;            /*!< [13..13] desc PIN13                                                       */
      __IOM uint32_t PIN14      : 1;            /*!< [14..14] desc PIN14                                                       */
      __IOM uint32_t PIN15      : 1;            /*!< [15..15] desc PIN15                                                       */
    } DIR_f;
  } ;
  
  union {
    __IOM uint32_t OPENDRAIN;                   /*!< (@ 0x00000004) desc OPENDRAIN                                             */
    
    struct {
      __IOM uint32_t PIN0       : 1;            /*!< [0..0] desc PIN0                                                          */
      __IOM uint32_t PIN1       : 1;            /*!< [1..1] desc PIN1                                                          */
      __IOM uint32_t PIN2       : 1;            /*!< [2..2] desc PIN2                                                          */
      __IOM uint32_t PIN3       : 1;            /*!< [3..3] desc PIN3                                                          */
      __IOM uint32_t PIN4       : 1;            /*!< [4..4] desc PIN4                                                          */
      __IOM uint32_t PIN5       : 1;            /*!< [5..5] desc PIN5                                                          */
      __IOM uint32_t PIN6       : 1;            /*!< [6..6] desc PIN6                                                          */
      __IOM uint32_t PIN7       : 1;            /*!< [7..7] desc PIN7                                                          */
      __IOM uint32_t PIN8       : 1;            /*!< [8..8] desc PIN8                                                          */
      __IOM uint32_t PIN9       : 1;            /*!< [9..9] desc PIN9                                                          */
      __IOM uint32_t PIN10      : 1;            /*!< [10..10] desc PIN10                                                       */
      __IOM uint32_t PIN11      : 1;            /*!< [11..11] desc PIN11                                                       */
      __IOM uint32_t PIN12      : 1;            /*!< [12..12] desc PIN12                                                       */
      __IOM uint32_t PIN13      : 1;            /*!< [13..13] desc PIN13                                                       */
      __IOM uint32_t PIN14      : 1;            /*!< [14..14] desc PIN14                                                       */
      __IOM uint32_t PIN15      : 1;            /*!< [15..15] desc PIN15                                                       */
    } OPENDRAIN_f;
  } ;
  __IM  uint32_t  RESERVED[2];
  
  union {
    __IOM uint32_t PUR;                         /*!< (@ 0x00000010) desc PUR                                                   */
    
    struct {
      __IOM uint32_t PIN0       : 1;            /*!< [0..0] desc PIN0                                                          */
      __IOM uint32_t PIN1       : 1;            /*!< [1..1] desc PIN1                                                          */
      __IOM uint32_t PIN2       : 1;            /*!< [2..2] desc PIN2                                                          */
      __IOM uint32_t PIN3       : 1;            /*!< [3..3] desc PIN3                                                          */
      __IOM uint32_t PIN4       : 1;            /*!< [4..4] desc PIN4                                                          */
      __IOM uint32_t PIN5       : 1;            /*!< [5..5] desc PIN5                                                          */
      __IOM uint32_t PIN6       : 1;            /*!< [6..6] desc PIN6                                                          */
      __IOM uint32_t PIN7       : 1;            /*!< [7..7] desc PIN7                                                          */
      __IOM uint32_t PIN8       : 1;            /*!< [8..8] desc PIN8                                                          */
      __IOM uint32_t PIN9       : 1;            /*!< [9..9] desc PIN9                                                          */
      __IOM uint32_t PIN10      : 1;            /*!< [10..10] desc PIN10                                                       */
      __IOM uint32_t PIN11      : 1;            /*!< [11..11] desc PIN11                                                       */
      __IOM uint32_t PIN12      : 1;            /*!< [12..12] desc PIN12                                                       */
      __IOM uint32_t PIN13      : 1;            /*!< [13..13] desc PIN13                                                       */
      __IOM uint32_t PIN14      : 1;            /*!< [14..14] desc PIN14                                                       */
      __IOM uint32_t PIN15      : 1;            /*!< [15..15] desc PIN15                                                       */
    } PUR_f;
  } ;
  
  union {
    __IOM uint32_t AFRH;                        /*!< (@ 0x00000014) desc AFRH                                                  */
    
    struct {
      __IOM uint32_t PIN8       : 4;            /*!< [2..0] desc AFR8                                                          */
      __IOM uint32_t PIN9       : 4;            /*!< [6..4] desc AFR9                                                          */
      __IOM uint32_t PIN10      : 4;            /*!< [10..8] desc AFR10                                                        */
      __IOM uint32_t PIN11      : 4;            /*!< [14..12] desc AFR11                                                       */
      __IOM uint32_t PIN12      : 4;            /*!< [18..16] desc AFR12                                                       */
      __IOM uint32_t PIN13      : 4;            /*!< [22..20] desc AFR13                                                       */
      __IOM uint32_t PIN14      : 4;            /*!< [26..24] desc AFR14                                                       */
      __IOM uint32_t PIN15      : 4;            /*!< [30..28] desc AFR15                                                       */
    } AFRH_f;
  } ;
  
  union {
    __IOM uint32_t AFRL;                        /*!< (@ 0x00000018) desc AFRL                                                  */
    
    struct {
      __IOM uint32_t PIN0       : 4;            /*!< [2..0] desc AFR0                                                          */
      __IOM uint32_t PIN1       : 4;            /*!< [6..4] desc AFR1                                                          */
      __IOM uint32_t PIN2       : 4;            /*!< [10..8] desc AFR2                                                         */
      __IOM uint32_t PIN3       : 4;            /*!< [14..12] desc AFR3                                                        */
      __IOM uint32_t PIN4       : 4;            /*!< [18..16] desc AFR4                                                        */
      __IOM uint32_t PIN5       : 4;            /*!< [22..20] desc AFR5                                                        */
      __IOM uint32_t PIN6       : 4;            /*!< [26..24] desc AFR6                                                        */
      __IOM uint32_t PIN7       : 4;            /*!< [30..28] desc AFR7                                                        */
    } AFRL_f;
  } ;
  
  union {
    __IOM uint32_t ANALOG;                      /*!< (@ 0x0000001C) desc ANALOG                                                */
    
    struct {
      __IOM uint32_t PIN0       : 1;            /*!< [0..0] desc PIN0                                                          */
      __IOM uint32_t PIN1       : 1;            /*!< [1..1] desc PIN1                                                          */
      __IOM uint32_t PIN2       : 1;            /*!< [2..2] desc PIN2                                                          */
      __IOM uint32_t PIN3       : 1;            /*!< [3..3] desc PIN3                                                          */
      __IOM uint32_t PIN4       : 1;            /*!< [4..4] desc PIN4                                                          */
      __IOM uint32_t PIN5       : 1;            /*!< [5..5] desc PIN5                                                          */
      __IOM uint32_t PIN6       : 1;            /*!< [6..6] desc PIN6                                                          */
      __IOM uint32_t PIN7       : 1;            /*!< [7..7] desc PIN7                                                          */
      __IOM uint32_t PIN8       : 1;            /*!< [8..8] desc PIN8                                                          */
      __IOM uint32_t PIN9       : 1;            /*!< [9..9] desc PIN9                                                          */
      __IOM uint32_t PIN10      : 1;            /*!< [10..10] desc PIN10                                                       */
      __IOM uint32_t PIN11      : 1;            /*!< [11..11] desc PIN11                                                       */
      __IOM uint32_t PIN12      : 1;            /*!< [12..12] desc PIN12                                                       */
      __IOM uint32_t PIN13      : 1;            /*!< [13..13] desc PIN13                                                       */
      __IOM uint32_t PIN14      : 1;            /*!< [14..14] desc PIN14                                                       */
      __IOM uint32_t PIN15      : 1;            /*!< [15..15] desc PIN15                                                       */
    } ANALOG_f;
  } ;
  __IM  uint32_t  RESERVED1;
  
  union {
    __IOM uint32_t RISEIE;                      /*!< (@ 0x00000024) Interrupt enable register                                  */
    
    struct {
      __IOM uint32_t PIN0       : 1;            /*!< [0..0] desc PIN0                                                          */
      __IOM uint32_t PIN1       : 1;            /*!< [1..1] desc PIN1                                                          */
      __IOM uint32_t PIN2       : 1;            /*!< [2..2] desc PIN2                                                          */
      __IOM uint32_t PIN3       : 1;            /*!< [3..3] desc PIN3                                                          */
      __IOM uint32_t PIN4       : 1;            /*!< [4..4] desc PIN4                                                          */
      __IOM uint32_t PIN5       : 1;            /*!< [5..5] desc PIN5                                                          */
      __IOM uint32_t PIN6       : 1;            /*!< [6..6] desc PIN6                                                          */
      __IOM uint32_t PIN7       : 1;            /*!< [7..7] desc PIN7                                                          */
      __IOM uint32_t PIN8       : 1;            /*!< [8..8] desc PIN8                                                          */
      __IOM uint32_t PIN9       : 1;            /*!< [9..9] desc PIN9                                                          */
      __IOM uint32_t PIN10      : 1;            /*!< [10..10] desc PIN10                                                       */
      __IOM uint32_t PIN11      : 1;            /*!< [11..11] desc PIN11                                                       */
      __IOM uint32_t PIN12      : 1;            /*!< [12..12] desc PIN12                                                       */
      __IOM uint32_t PIN13      : 1;            /*!< [13..13] desc PIN13                                                       */
      __IOM uint32_t PIN14      : 1;            /*!< [14..14] desc PIN14                                                       */
      __IOM uint32_t PIN15      : 1;            /*!< [15..15] desc PIN15                                                       */
    } RISEIE_f;
  } ;
  
  union {
    __IOM uint32_t FALLIE;                      /*!< (@ 0x00000028) Interrupt enable register                                  */
    
    struct {
      __IOM uint32_t PIN0       : 1;            /*!< [0..0] desc PIN0                                                          */
      __IOM uint32_t PIN1       : 1;            /*!< [1..1] desc PIN1                                                          */
      __IOM uint32_t PIN2       : 1;            /*!< [2..2] desc PIN2                                                          */
      __IOM uint32_t PIN3       : 1;            /*!< [3..3] desc PIN3                                                          */
      __IOM uint32_t PIN4       : 1;            /*!< [4..4] desc PIN4                                                          */
      __IOM uint32_t PIN5       : 1;            /*!< [5..5] desc PIN5                                                          */
      __IOM uint32_t PIN6       : 1;            /*!< [6..6] desc PIN6                                                          */
      __IOM uint32_t PIN7       : 1;            /*!< [7..7] desc PIN7                                                          */
      __IOM uint32_t PIN8       : 1;            /*!< [8..8] desc PIN8                                                          */
      __IOM uint32_t PIN9       : 1;            /*!< [9..9] desc PIN9                                                          */
      __IOM uint32_t PIN10      : 1;            /*!< [10..10] desc PIN10                                                       */
      __IOM uint32_t PIN11      : 1;            /*!< [11..11] desc PIN11                                                       */
      __IOM uint32_t PIN12      : 1;            /*!< [12..12] desc PIN12                                                       */
      __IOM uint32_t PIN13      : 1;            /*!< [13..13] desc PIN13                                                       */
      __IOM uint32_t PIN14      : 1;            /*!< [14..14] desc PIN14                                                       */
      __IOM uint32_t PIN15      : 1;            /*!< [15..15] desc PIN15                                                       */
    } FALLIE_f;
  } ;
  __IM  uint32_t  RESERVED2[2];
  
  union {
    __IM  uint32_t ISR;                         /*!< (@ 0x00000034) Interrupt status register                                  */
    
    struct {
      __IM  uint32_t PIN0       : 1;            /*!< [0..0] desc PIN0                                                          */
      __IM  uint32_t PIN1       : 1;            /*!< [1..1] desc PIN1                                                          */
      __IM  uint32_t PIN2       : 1;            /*!< [2..2] desc PIN2                                                          */
      __IM  uint32_t PIN3       : 1;            /*!< [3..3] desc PIN3                                                          */
      __IM  uint32_t PIN4       : 1;            /*!< [4..4] desc PIN4                                                          */
      __IM  uint32_t PIN5       : 1;            /*!< [5..5] desc PIN5                                                          */
      __IM  uint32_t PIN6       : 1;            /*!< [6..6] desc PIN6                                                          */
      __IM  uint32_t PIN7       : 1;            /*!< [7..7] desc PIN7                                                          */
      __IM  uint32_t PIN8       : 1;            /*!< [8..8] desc PIN8                                                          */
      __IM  uint32_t PIN9       : 1;            /*!< [9..9] desc PIN9                                                          */
      __IM  uint32_t PIN10      : 1;            /*!< [10..10] desc PIN10                                                       */
      __IM  uint32_t PIN11      : 1;            /*!< [11..11] desc PIN11                                                       */
      __IM  uint32_t PIN12      : 1;            /*!< [12..12] desc PIN12                                                       */
      __IM  uint32_t PIN13      : 1;            /*!< [13..13] desc PIN13                                                       */
      __IM  uint32_t PIN14      : 1;            /*!< [14..14] desc PIN14                                                       */
      __IM  uint32_t PIN15      : 1;            /*!< [15..15] desc PIN15                                                       */
    } ISR_f;
  } ;
  
  union {
    __IOM uint32_t ICR;                         /*!< (@ 0x00000038) Interrupt flag clear register                              */
    
    struct {
      __IOM uint32_t PIN0       : 1;            /*!< [0..0] desc PIN0                                                          */
      __IOM uint32_t PIN1       : 1;            /*!< [1..1] desc PIN1                                                          */
      __IOM uint32_t PIN2       : 1;            /*!< [2..2] desc PIN2                                                          */
      __IOM uint32_t PIN3       : 1;            /*!< [3..3] desc PIN3                                                          */
      __IOM uint32_t PIN4       : 1;            /*!< [4..4] desc PIN4                                                          */
      __IOM uint32_t PIN5       : 1;            /*!< [5..5] desc PIN5                                                          */
      __IOM uint32_t PIN6       : 1;            /*!< [6..6] desc PIN6                                                          */
      __IOM uint32_t PIN7       : 1;            /*!< [7..7] desc PIN7                                                          */
      __IOM uint32_t PIN8       : 1;            /*!< [8..8] desc PIN8                                                          */
      __IOM uint32_t PIN9       : 1;            /*!< [9..9] desc PIN9                                                          */
      __IOM uint32_t PIN10      : 1;            /*!< [10..10] desc PIN10                                                       */
      __IOM uint32_t PIN11      : 1;            /*!< [11..11] desc PIN11                                                       */
      __IOM uint32_t PIN12      : 1;            /*!< [12..12] desc PIN12                                                       */
      __IOM uint32_t PIN13      : 1;            /*!< [13..13] desc PIN13                                                       */
      __IOM uint32_t PIN14      : 1;            /*!< [14..14] desc PIN14                                                       */
      __IOM uint32_t PIN15      : 1;            /*!< [15..15] desc PIN15                                                       */
    } ICR_f;
  } ;
  __IM  uint32_t  RESERVED3;
  
  union {
    __IOM uint32_t FILTER;                      /*!< (@ 0x00000040) desc FILTER                                                */
    
    struct {
      __IOM uint32_t PIN0       : 1;            /*!< [0..0] desc PIN0                                                          */
      __IOM uint32_t PIN1       : 1;            /*!< [1..1] desc PIN1                                                          */
      __IOM uint32_t PIN2       : 1;            /*!< [2..2] desc PIN2                                                          */
      __IOM uint32_t PIN3       : 1;            /*!< [3..3] desc PIN3                                                          */
      __IOM uint32_t PIN4       : 1;            /*!< [4..4] desc PIN4                                                          */
      __IOM uint32_t PIN5       : 1;            /*!< [5..5] desc PIN5                                                          */
      __IOM uint32_t PIN6       : 1;            /*!< [6..6] desc PIN6                                                          */
      __IOM uint32_t PIN7       : 1;            /*!< [7..7] desc PIN7                                                          */
      __IOM uint32_t PIN8       : 1;            /*!< [8..8] desc PIN8                                                          */
      __IOM uint32_t PIN9       : 1;            /*!< [9..9] desc PIN9                                                          */
      __IOM uint32_t PIN10      : 1;            /*!< [10..10] desc PIN10                                                       */
      __IOM uint32_t PIN11      : 1;            /*!< [11..11] desc PIN11                                                       */
      __IOM uint32_t PIN12      : 1;            /*!< [12..12] desc PIN12                                                       */
      __IOM uint32_t PIN13      : 1;            /*!< [13..13] desc PIN13                                                       */
      __IOM uint32_t PIN14      : 1;            /*!< [14..14] desc PIN14                                                       */
      __IOM uint32_t PIN15      : 1;            /*!< [15..15] desc PIN15                                                       */
      __IOM uint32_t FLTCLK     : 3;            /*!< [18..16] desc FLTCLK                                                      */
    } FILTER_f;
  } ;
  __IM  uint32_t  RESERVED4[3];
  
  union {
    __IM  uint32_t IDR;                         /*!< (@ 0x00000050) desc IDR                                                   */
    
    struct {
      __IM  uint32_t PIN0       : 1;            /*!< [0..0] desc PIN0                                                          */
      __IM  uint32_t PIN1       : 1;            /*!< [1..1] desc PIN1                                                          */
      __IM  uint32_t PIN2       : 1;            /*!< [2..2] desc PIN2                                                          */
      __IM  uint32_t PIN3       : 1;            /*!< [3..3] desc PIN3                                                          */
      __IM  uint32_t PIN4       : 1;            /*!< [4..4] desc PIN4                                                          */
      __IM  uint32_t PIN5       : 1;            /*!< [5..5] desc PIN5                                                          */
      __IM  uint32_t PIN6       : 1;            /*!< [6..6] desc PIN6                                                          */
      __IM  uint32_t PIN7       : 1;            /*!< [7..7] desc PIN7                                                          */
      __IM  uint32_t PIN8       : 1;            /*!< [8..8] desc PIN8                                                          */
      __IM  uint32_t PIN9       : 1;            /*!< [9..9] desc PIN9                                                          */
      __IM  uint32_t PIN10      : 1;            /*!< [10..10] desc PIN10                                                       */
      __IM  uint32_t PIN11      : 1;            /*!< [11..11] desc PIN11                                                       */
      __IM  uint32_t PIN12      : 1;            /*!< [12..12] desc PIN12                                                       */
      __IM  uint32_t PIN13      : 1;            /*!< [13..13] desc PIN13                                                       */
      __IM  uint32_t PIN14      : 1;            /*!< [14..14] desc PIN14                                                       */
      __IM  uint32_t PIN15      : 1;            /*!< [15..15] desc PIN15                                                       */
    } IDR_f;
  } ;
  
  union {
    __IOM uint32_t ODR;                         /*!< (@ 0x00000054) desc ODR                                                   */
    
    struct {
      __IOM uint32_t PIN0       : 1;            /*!< [0..0] desc PIN0                                                          */
      __IOM uint32_t PIN1       : 1;            /*!< [1..1] desc PIN1                                                          */
      __IOM uint32_t PIN2       : 1;            /*!< [2..2] desc PIN2                                                          */
      __IOM uint32_t PIN3       : 1;            /*!< [3..3] desc PIN3                                                          */
      __IOM uint32_t PIN4       : 1;            /*!< [4..4] desc PIN4                                                          */
      __IOM uint32_t PIN5       : 1;            /*!< [5..5] desc PIN5                                                          */
      __IOM uint32_t PIN6       : 1;            /*!< [6..6] desc PIN6                                                          */
      __IOM uint32_t PIN7       : 1;            /*!< [7..7] desc PIN7                                                          */
      __IOM uint32_t PIN8       : 1;            /*!< [8..8] desc PIN8                                                          */
      __IOM uint32_t PIN9       : 1;            /*!< [9..9] desc PIN9                                                          */
      __IOM uint32_t PIN10      : 1;            /*!< [10..10] desc PIN10                                                       */
      __IOM uint32_t PIN11      : 1;            /*!< [11..11] desc PIN11                                                       */
      __IOM uint32_t PIN12      : 1;            /*!< [12..12] desc PIN12                                                       */
      __IOM uint32_t PIN13      : 1;            /*!< [13..13] desc PIN13                                                       */
      __IOM uint32_t PIN14      : 1;            /*!< [14..14] desc PIN14                                                       */
      __IOM uint32_t PIN15      : 1;            /*!< [15..15] desc PIN15                                                       */
    } ODR_f;
  } ;
  
  union {
    __IOM uint32_t BRR;                         /*!< (@ 0x00000058) desc BRR                                                   */
    
    struct {
      __IOM uint32_t BRR0       : 1;            /*!< [0..0] desc BRR0                                                          */
      __IOM uint32_t BRR1       : 1;            /*!< [1..1] desc BRR1                                                          */
      __IOM uint32_t BRR2       : 1;            /*!< [2..2] desc BRR2                                                          */
      __IOM uint32_t BRR3       : 1;            /*!< [3..3] desc BRR3                                                          */
      __IOM uint32_t BRR4       : 1;            /*!< [4..4] desc BRR4                                                          */
      __IOM uint32_t BRR5       : 1;            /*!< [5..5] desc BRR5                                                          */
      __IOM uint32_t BRR6       : 1;            /*!< [6..6] desc BRR6                                                          */
      __IOM uint32_t BRR7       : 1;            /*!< [7..7] desc BRR7                                                          */
      __IOM uint32_t BRR8       : 1;            /*!< [8..8] desc BRR8                                                          */
      __IOM uint32_t BRR9       : 1;            /*!< [9..9] desc BRR9                                                          */
      __IOM uint32_t BRR10      : 1;            /*!< [10..10] desc BRR10                                                       */
      __IOM uint32_t BRR11      : 1;            /*!< [11..11] desc BRR11                                                       */
      __IOM uint32_t BRR12      : 1;            /*!< [12..12] desc BRR12                                                       */
      __IOM uint32_t BRR13      : 1;            /*!< [13..13] desc BRR13                                                       */
      __IOM uint32_t BRR14      : 1;            /*!< [14..14] desc BRR14                                                       */
      __IOM uint32_t BRR15      : 1;            /*!< [15..15] desc BRR15                                                       */
    } BRR_f;
  } ;
  
  union {
    __IOM uint32_t BSRR;                        /*!< (@ 0x0000005C) desc BSRR                                                  */
    
    struct {
      __IOM uint32_t BSS0       : 1;            /*!< [0..0] desc BSS0                                                          */
      __IOM uint32_t BSS1       : 1;            /*!< [1..1] desc BSS1                                                          */
      __IOM uint32_t BSS2       : 1;            /*!< [2..2] desc BSS2                                                          */
      __IOM uint32_t BSS3       : 1;            /*!< [3..3] desc BSS3                                                          */
      __IOM uint32_t BSS4       : 1;            /*!< [4..4] desc BSS4                                                          */
      __IOM uint32_t BSS5       : 1;            /*!< [5..5] desc BSS5                                                          */
      __IOM uint32_t BSS6       : 1;            /*!< [6..6] desc BSS6                                                          */
      __IOM uint32_t BSS7       : 1;            /*!< [7..7] desc BSS7                                                          */
      __IOM uint32_t BSS8       : 1;            /*!< [8..8] desc BSS8                                                          */
      __IOM uint32_t BSS9       : 1;            /*!< [9..9] desc BSS9                                                          */
      __IOM uint32_t BSS10      : 1;            /*!< [10..10] desc BSS10                                                       */
      __IOM uint32_t BSS11      : 1;            /*!< [11..11] desc BSS11                                                       */
      __IOM uint32_t BSS12      : 1;            /*!< [12..12] desc BSS12                                                       */
      __IOM uint32_t BSS13      : 1;            /*!< [13..13] desc BSS13                                                       */
      __IOM uint32_t BSS14      : 1;            /*!< [14..14] desc BSS14                                                       */
      __IOM uint32_t BSS15      : 1;            /*!< [15..15] desc BSS15                                                       */
      __IOM uint32_t BRR0       : 1;            /*!< [16..16] desc BRR0                                                        */
      __IOM uint32_t BRR1       : 1;            /*!< [17..17] desc BRR1                                                        */
      __IOM uint32_t BRR2       : 1;            /*!< [18..18] desc BRR2                                                        */
      __IOM uint32_t BRR3       : 1;            /*!< [19..19] desc BRR3                                                        */
      __IOM uint32_t BRR4       : 1;            /*!< [20..20] desc BRR4                                                        */
      __IOM uint32_t BRR5       : 1;            /*!< [21..21] desc BRR5                                                        */
      __IOM uint32_t BRR6       : 1;            /*!< [22..22] desc BRR6                                                        */
      __IOM uint32_t BRR7       : 1;            /*!< [23..23] desc BRR7                                                        */
      __IOM uint32_t BRR8       : 1;            /*!< [24..24] desc BRR8                                                        */
      __IOM uint32_t BRR9       : 1;            /*!< [25..25] desc BRR9                                                        */
      __IOM uint32_t BRR10      : 1;            /*!< [26..26] desc BRR10                                                       */
      __IOM uint32_t BRR11      : 1;            /*!< [27..27] desc BRR11                                                       */
      __IOM uint32_t BRR12      : 1;            /*!< [28..28] desc BRR12                                                       */
      __IOM uint32_t BRR13      : 1;            /*!< [29..29] desc BRR13                                                       */
      __IOM uint32_t BRR14      : 1;            /*!< [30..30] desc BRR14                                                       */
      __IOM uint32_t BRR15      : 1;            /*!< [31..31] desc BRR15                                                       */
    } BSRR_f;
  } ;
  
  union {
    __IOM uint32_t TOG;                         /*!< (@ 0x00000060) desc TOG                                                   */
    
    struct {
      __IOM uint32_t PIN0       : 1;            /*!< [0..0] desc PIN0                                                          */
      __IOM uint32_t PIN1       : 1;            /*!< [1..1] desc PIN1                                                          */
      __IOM uint32_t PIN2       : 1;            /*!< [2..2] desc PIN2                                                          */
      __IOM uint32_t PIN3       : 1;            /*!< [3..3] desc PIN3                                                          */
      __IOM uint32_t PIN4       : 1;            /*!< [4..4] desc PIN4                                                          */
      __IOM uint32_t PIN5       : 1;            /*!< [5..5] desc PIN5                                                          */
      __IOM uint32_t PIN6       : 1;            /*!< [6..6] desc PIN6                                                          */
      __IOM uint32_t PIN7       : 1;            /*!< [7..7] desc PIN7                                                          */
      __IOM uint32_t PIN8       : 1;            /*!< [8..8] desc PIN8                                                          */
      __IOM uint32_t PIN9       : 1;            /*!< [9..9] desc PIN9                                                          */
      __IOM uint32_t PIN10      : 1;            /*!< [10..10] desc PIN10                                                       */
      __IOM uint32_t PIN11      : 1;            /*!< [11..11] desc PIN11                                                       */
      __IOM uint32_t PIN12      : 1;            /*!< [12..12] desc PIN12                                                       */
      __IOM uint32_t PIN13      : 1;            /*!< [13..13] desc PIN13                                                       */
      __IOM uint32_t PIN14      : 1;            /*!< [14..14] desc PIN14                                                       */
      __IOM uint32_t PIN15      : 1;            /*!< [15..15] desc PIN15                                                       */
    } TOG_f;
  } ;
} GPIO_TypeDef;                                    /*!< Size = 100 (0x64)                                                         */



/* =========================================================================================================================== */
/* ================                                           GTIM1                                           ================ */
/* =========================================================================================================================== */


/**
  * @brief General Timer 1 (GTIM1)
  */

typedef struct {                                /*!< (@ 0x40001800) GTIM1 Structure                                            */
  
  union {
    __IOM uint32_t CR1;                         /*!< (@ 0x00000000) Control register1                                          */
    
    struct {
      __IOM uint32_t CEN        : 1;            /*!< [0..0] desc CEN                                                           */
      __IOM uint32_t UDIS       : 1;            /*!< [1..1] desc UDIS                                                          */
      __IOM uint32_t URS        : 1;            /*!< [2..2] desc URS                                                           */
      __IOM uint32_t OPM        : 1;            /*!< [3..3] desc OPM                                                           */
      __IOM uint32_t DIR        : 1;            /*!< [4..4] desc DIR                                                           */
      __IOM uint32_t CMS        : 2;            /*!< [6..5] desc CMS                                                           */
      __IOM uint32_t ARPE       : 1;            /*!< [7..7] desc ARPE                                                          */
      __IOM uint32_t CKD        : 2;            /*!< [9..8] desc CKD                                                           */
      __IM  uint32_t            : 1;
      __IOM uint32_t UIFREMAP   : 1;            /*!< [11..11] desc UIFREMAP                                                    */
    } CR1_f;
  } ;
  
  union {
    __IOM uint32_t CR2;                         /*!< (@ 0x00000004) Control register2                                          */
    
    struct {
      __IM  uint32_t            : 3;
      __IOM uint32_t CCDS       : 1;            /*!< [3..3] desc CCDS                                                          */
      __IOM uint32_t MMS        : 3;            /*!< [6..4] desc MMS                                                           */
      __IOM uint32_t TI1S       : 1;            /*!< [7..7] desc TI1S                                                          */
      __IM  uint32_t            : 17;
      __IOM uint32_t MMSH       : 2;            /*!< [26..25] desc MMSH                                                        */
    } CR2_f;
  } ;
  
  union {
    __IOM uint32_t SMCR;                        /*!< (@ 0x00000008) Slave Mode control register                                */
    
    struct {
      __IOM uint32_t SMS        : 3;            /*!< [2..0] desc SMS                                                           */
      __IOM uint32_t OCCS       : 1;            /*!< [3..3] desc OCCS                                                          */
      __IOM uint32_t TS         : 3;            /*!< [6..4] desc TS                                                            */
      __IOM uint32_t MSM        : 1;            /*!< [7..7] desc MSM                                                           */
      __IOM uint32_t ETF        : 4;            /*!< [11..8] desc ETF                                                          */
      __IOM uint32_t ETPS       : 2;            /*!< [13..12] desc ETPS                                                        */
      __IOM uint32_t ECE        : 1;            /*!< [14..14] desc ECE                                                         */
      __IOM uint32_t ETP        : 1;            /*!< [15..15] desc ETP                                                         */
      __IOM uint32_t SMSH       : 1;            /*!< [16..16] desc SMSH                                                        */
      __IM  uint32_t            : 3;
      __IOM uint32_t TSH        : 2;            /*!< [21..20] desc TSH                                                         */
      __IM  uint32_t            : 2;
      __IOM uint32_t SMSPE      : 1;            /*!< [24..24] desc SMSPE                                                       */
      __IOM uint32_t SMSPS      : 1;            /*!< [25..25] desc SMSPS                                                       */
    } SMCR_f;
  } ;
  
  union {
    __IOM uint32_t IER;                         /*!< (@ 0x0000000C) Interrupt control register                                 */
    
    struct {
      __IOM uint32_t UIE        : 1;            /*!< [0..0] desc UIE                                                           */
      __IOM uint32_t CC1IE      : 1;            /*!< [1..1] desc CC1IE                                                         */
      __IOM uint32_t CC2IE      : 1;            /*!< [2..2] desc CC2IE                                                         */
      __IOM uint32_t CC3IE      : 1;            /*!< [3..3] desc CC3IE                                                         */
      __IOM uint32_t CC4IE      : 1;            /*!< [4..4] desc CC4IE                                                         */
      __IM  uint32_t            : 1;
      __IOM uint32_t TIE        : 1;            /*!< [6..6] desc TIE                                                           */
      __IM  uint32_t            : 1;
      __IOM uint32_t UDE        : 1;            /*!< [8.8] desc UDE                                                                  */
      __IOM uint32_t CC1DE      : 1;            /*!< [9.9] desc CC1DE                                                                */
      __IOM uint32_t CC2DE      : 1;            /*!< [10..10] desc CC2DE                                                                */
      __IOM uint32_t CC3DE      : 1;            /*!< [11..11] desc CC3DE                                                                */
      __IOM uint32_t CC4DE      : 1;            /*!< [12..12] desc CC4DE                                                                */
      __IM  uint32_t            : 1;
      __IOM uint32_t TDE        : 1;            /*!< [14..14] desc TDE                                                                  */
      __IM  uint32_t            : 5;
      __IOM uint32_t IDXIE      : 1;            /*!< [20..20] desc IDXIE                                                       */
      __IOM uint32_t DIRIE      : 1;            /*!< [21..21] desc DIRIE                                                       */
      __IOM uint32_t IERRIE     : 1;            /*!< [22..22] desc IERRIE                                                      */
      __IOM uint32_t TERRIE     : 1;            /*!< [23..23] desc TERRIE                                                      */
    } IER_f;
  } ;
  
  union {
    __IM  uint32_t ISR;                         /*!< (@ 0x00000010) Interrupt status register                                  */
    
    struct {
      __IM  uint32_t UIF        : 1;            /*!< [0..0] desc UIF                                                           */
      __IM  uint32_t CC1IF      : 1;            /*!< [1..1] desc CC1IF                                                         */
      __IM  uint32_t CC2IF      : 1;            /*!< [2..2] desc CC2IF                                                         */
      __IM  uint32_t CC3IF      : 1;            /*!< [3..3] desc CC3IF                                                         */
      __IM  uint32_t CC4IF      : 1;            /*!< [4..4] desc CC4IF                                                         */
      __IM  uint32_t            : 1;
      __IM  uint32_t TIF        : 1;            /*!< [6..6] desc TIF                                                           */
      __IM  uint32_t            : 2;
      __IM  uint32_t CC1OF      : 1;            /*!< [9..9] desc CC1OF                                                         */
      __IM  uint32_t CC2OF      : 1;            /*!< [10..10] desc CC2OF                                                       */
      __IM  uint32_t CC3OF      : 1;            /*!< [11..11] desc CC3OF                                                       */
      __IM  uint32_t CC4OF      : 1;            /*!< [12..12] desc CC4OF                                                       */
      __IM  uint32_t            : 7;
      __IM  uint32_t IDXF       : 1;            /*!< [20..20] desc IDXF                                                        */
      __IM  uint32_t DIRF       : 1;            /*!< [21..21] desc DIRF                                                        */
      __IM  uint32_t IERRF      : 1;            /*!< [22..22] desc IERRF                                                       */
      __IM  uint32_t TERRF      : 1;            /*!< [23..23] desc TERRF                                                       */
    } ISR_f;
  } ;
  
  union {
    __IOM uint32_t EGR;                         /*!< (@ 0x00000014) Event Generate register                                    */
    
    struct {
      __IOM uint32_t UG         : 1;            /*!< [0..0] desc UG                                                            */
      __IOM uint32_t CC1G       : 1;            /*!< [1..1] desc CC1G                                                          */
      __IOM uint32_t CC2G       : 1;            /*!< [2..2] desc CC2G                                                          */
      __IOM uint32_t CC3G       : 1;            /*!< [3..3] desc CC3G                                                          */
      __IOM uint32_t CC4G       : 1;            /*!< [4..4] desc CC4G                                                          */
      __IM  uint32_t            : 1;
      __IOM uint32_t TG         : 1;            /*!< [6..6] desc TG                                                            */
    } EGR_f;
  } ;
  
  union {
    union {
      __IOM uint32_t CCMR1CAP;                  /*!< (@ 0x00000018) Capture control Register1                                  */
      
      struct {
        __IOM uint32_t CC1S     : 2;            /*!< [1..0] desc CC1S                                                          */
        __IOM uint32_t IC1PSC   : 2;            /*!< [3..2] desc IC1PSC                                                        */
        __IOM uint32_t IC1F     : 4;            /*!< [7..4] desc IC1F                                                          */
        __IOM uint32_t CC2S     : 2;            /*!< [9..8] desc CC2S                                                          */
        __IOM uint32_t IC2PSC   : 2;            /*!< [11..10] desc IC2PSC                                                      */
        __IOM uint32_t IC2F     : 4;            /*!< [15..12] desc IC2F                                                        */
      } CCMR1CAP_f;
    } ;
    
    union {
      __IOM uint32_t CCMR1CMP;                  /*!< (@ 0x00000018) Compare control Register1                                  */
      
      struct {
        __IOM uint32_t CC1S     : 2;            /*!< [1..0] desc CC1S                                                          */
        __IOM uint32_t OC1FE    : 1;            /*!< [2..2] desc OC1FE                                                         */
        __IOM uint32_t OC1PE    : 1;            /*!< [3..3] desc OC1PE                                                         */
        __IOM uint32_t OC1M     : 3;            /*!< [6..4] desc OC1M                                                          */
        __IOM uint32_t OC1CE    : 1;            /*!< [7..7] desc OC1CE                                                         */
        __IOM uint32_t CC2S     : 2;            /*!< [9..8] desc CC2S                                                          */
        __IOM uint32_t OC2FE    : 1;            /*!< [10..10] desc OC2FE                                                       */
        __IOM uint32_t OC2PE    : 1;            /*!< [11..11] desc OC2PE                                                       */
        __IOM uint32_t OC2M     : 3;            /*!< [14..12] desc OC2M                                                        */
        __IOM uint32_t OC2CE    : 1;            /*!< [15..15] desc OC2CE                                                       */
        __IOM uint32_t OC1MH    : 1;            /*!< [16..16] desc OC1MH                                                       */
        __IM  uint32_t          : 7;
        __IOM uint32_t OC2MH    : 1;            /*!< [24..24] desc OC2MH                                                       */
      } CCMR1CMP_f;
    } ;
  };
  
  union {
    union {
      __IOM uint32_t CCMR2CAP;                  /*!< (@ 0x0000001C) Capture control Register2                                  */
      
      struct {
        __IOM uint32_t CC3S     : 2;            /*!< [1..0] desc CC3S                                                          */
        __IOM uint32_t IC3PSC   : 2;            /*!< [3..2] desc IC3PSC                                                        */
        __IOM uint32_t IC3F     : 4;            /*!< [7..4] desc IC3F                                                          */
        __IOM uint32_t CC4S     : 2;            /*!< [9..8] desc CC4S                                                          */
        __IOM uint32_t IC4PSC   : 2;            /*!< [11..10] desc IC4PSC                                                      */
        __IOM uint32_t IC4F     : 4;            /*!< [15..12] desc IC4F                                                        */
      } CCMR2CAP_f;
    } ;
    
    union {
      __IOM uint32_t CCMR2CMP;                  /*!< (@ 0x0000001C) Compare control Register2                                  */
      
      struct {
        __IOM uint32_t CC3S     : 2;            /*!< [1..0] desc CC3S                                                          */
        __IOM uint32_t OC3FE    : 1;            /*!< [2..2] desc OC3FE                                                         */
        __IOM uint32_t OC3PE    : 1;            /*!< [3..3] desc OC3PE                                                         */
        __IOM uint32_t OC3M     : 3;            /*!< [6..4] desc OC3M                                                          */
        __IOM uint32_t OC3CE    : 1;            /*!< [7..7] desc OC3CE                                                         */
        __IOM uint32_t CC4S     : 2;            /*!< [9..8] desc CC4S                                                          */
        __IOM uint32_t OC4FE    : 1;            /*!< [10..10] desc OC4FE                                                       */
        __IOM uint32_t OC4PE    : 1;            /*!< [11..11] desc OC4PE                                                       */
        __IOM uint32_t OC4M     : 3;            /*!< [14..12] desc OC4M                                                        */
        __IOM uint32_t OC4CE    : 1;            /*!< [15..15] desc OC4CE                                                       */
        __IOM uint32_t OC3MH    : 1;            /*!< [16..16] desc OC3MH                                                       */
        __IM  uint32_t          : 7;
        __IOM uint32_t OC4MH    : 1;            /*!< [24..24] desc OC4MH                                                       */
      } CCMR2CMP_f;
    } ;
  };
  
  union {
    __IOM uint32_t CCER;                        /*!< (@ 0x00000020) Capture compare Enable Register                            */
    
    struct {
      __IOM uint32_t CC1E       : 1;            /*!< [0..0] desc CC1E                                                          */
      __IOM uint32_t CC1P       : 1;            /*!< [1..1] desc CC1P                                                          */
      __IM  uint32_t            : 1;
      __IOM uint32_t CC1NP      : 1;            /*!< [3..3] desc CC1NP                                                         */
      __IOM uint32_t CC2E       : 1;            /*!< [4..4] desc CC2E                                                          */
      __IOM uint32_t CC2P       : 1;            /*!< [5..5] desc CC2P                                                          */
      __IM  uint32_t            : 1;
      __IOM uint32_t CC2NP      : 1;            /*!< [7..7] desc CC2NP                                                         */
      __IOM uint32_t CC3E       : 1;            /*!< [8..8] desc CC3E                                                          */
      __IOM uint32_t CC3P       : 1;            /*!< [9..9] desc CC3P                                                          */
      __IM  uint32_t            : 1;
      __IOM uint32_t CC3NP      : 1;            /*!< [11..11] desc CC3NP                                                       */
      __IOM uint32_t CC4E       : 1;            /*!< [12..12] desc CC4E                                                        */
      __IOM uint32_t CC4P       : 1;            /*!< [13..13] desc CC4P                                                        */
      __IM  uint32_t            : 1;
      __IOM uint32_t CC4NP      : 1;            /*!< [15..15] desc CC4NP                                                       */
    } CCER_f;
  } ;
  
  union {
    __IOM uint32_t CNT;                         /*!< (@ 0x00000024) Counter Register                                           */
    
    struct {
      __IOM uint32_t CNT        : 16;           /*!< [15..0] desc CNT                                                          */
      __IM  uint32_t            : 15;
      __IM  uint32_t UIFCPY     : 1;            /*!< [31..31] desc UIFCPY                                                      */
    } CNT_f;
  } ;
  
  union {
    __IOM uint32_t PSC;                         /*!< (@ 0x00000028) Prescaler Control Register                                 */
    
    struct {
      __IOM uint32_t PSC        : 16;           /*!< [15..0] desc PSC                                                          */
    } PSC_f;
  } ;
  
  union {
    __IOM uint32_t ARR;                         /*!< (@ 0x0000002C) Auto Reload Register                                       */
    
    struct {
      __IOM uint32_t ARR        : 16;           /*!< [15..0] desc ARR                                                          */
    } ARR_f;
  } ;
  __IM  uint32_t  RESERVED;
  
  union {
    __IOM uint32_t CCR1;                        /*!< (@ 0x00000034) Capture control Register1                                  */
    
    struct {
      __IOM uint32_t CCR1       : 16;           /*!< [15..0] desc CCR1                                                         */
    } CCR1_f;
  } ;
  
  union {
    __IOM uint32_t CCR2;                        /*!< (@ 0x00000038) Capture control Register2                                  */
    
    struct {
      __IOM uint32_t CCR2       : 16;           /*!< [15..0] desc CCR2                                                         */
    } CCR2_f;
  } ;
  
  union {
    __IOM uint32_t CCR3;                        /*!< (@ 0x0000003C) Capture control Register3                                  */
    
    struct {
      __IOM uint32_t CCR3       : 16;           /*!< [15..0] desc CCR3                                                         */
    } CCR3_f;
  } ;
  
  union {
    __IOM uint32_t CCR4;                        /*!< (@ 0x00000040) Capture control Register4                                  */
    
    struct {
      __IOM uint32_t CCR4       : 16;           /*!< [15..0] desc CCR4                                                         */
    } CCR4_f;
  } ;
  __IM  uint32_t  RESERVED1[5];
  
  union {
    __IOM uint32_t ECR;                         /*!< (@ 0x00000058) Encoder control Register                                   */
    
    struct {
      __IOM uint32_t IE         : 1;            /*!< [0..0] desc IE                                                            */
      __IOM uint32_t IDIR       : 2;            /*!< [2..1] desc IDIR                                                          */
      __IM  uint32_t            : 2;
      __IOM uint32_t FIDX       : 1;            /*!< [5..5] desc FIDX                                                          */
      __IOM uint32_t IPOS       : 2;            /*!< [7..6] desc IPOS                                                          */
    } ECR_f;
  } ;
  
  union {
    __IOM uint32_t TISEL;                       /*!< (@ 0x0000005C) Timer Input Select Register                                */
    
    struct {
      __IOM uint32_t TI1SEL     : 4;            /*!< [3..0] desc TI1SEL                                                        */
      __IM  uint32_t            : 4;
      __IOM uint32_t TI2SEL     : 4;            /*!< [11..8] desc TI2SEL                                                       */
      __IM  uint32_t            : 4;
      __IOM uint32_t TI3SEL     : 4;            /*!< [19..16] desc TI3SEL                                                      */
      __IM  uint32_t            : 4;
      __IOM uint32_t TI4SEL     : 4;            /*!< [27..24] desc TI4SEL                                                      */
    } TISEL_f;
  } ;
  
  union {
    __IOM uint32_t AF1;                         /*!< (@ 0x00000060) Alternate function Register1                               */
    
    struct {
      __IM  uint32_t            : 14;
      __IOM uint32_t ETRSEL     : 4;            /*!< [17..14] desc ETRSEL                                                      */
    } AF1_f;
  } ;
  
  union {
    __IOM uint32_t AF2;                         /*!< (@ 0x00000064) Alternate function Register2                               */
    
    struct {
      __IM  uint32_t            : 16;
      __IOM uint32_t OCRSEL     : 3;            /*!< [18..16] desc OCRSEL                                                      */
    } AF2_f;
  } ;
  __IM  uint32_t  RESERVED2[2];
  
  union {
    __IOM uint32_t ICR;                         /*!< (@ 0x00000070) Interrupt flag clear register                              */
    
    struct {
      __IOM uint32_t UIF        : 1;            /*!< [0..0] desc UIF                                                           */
      __IOM uint32_t CC1IF      : 1;            /*!< [1..1] desc CC1IF                                                         */
      __IOM uint32_t CC2IF      : 1;            /*!< [2..2] desc CC2IF                                                         */
      __IOM uint32_t CC3IF      : 1;            /*!< [3..3] desc CC3IF                                                         */
      __IOM uint32_t CC4IF      : 1;            /*!< [4..4] desc CC4IF                                                         */
      __IM  uint32_t            : 1;
      __IOM uint32_t TIF        : 1;            /*!< [6..6] desc TIF                                                           */
      __IM  uint32_t            : 2;
      __IOM uint32_t CC1OF      : 1;            /*!< [9..9] desc CC1OF                                                         */
      __IOM uint32_t CC2OF      : 1;            /*!< [10..10] desc CC2OF                                                       */
      __IOM uint32_t CC3OF      : 1;            /*!< [11..11] desc CC3OF                                                       */
      __IOM uint32_t CC4OF      : 1;            /*!< [12..12] desc CC4OF                                                       */
      __IM  uint32_t            : 7;
      __IOM uint32_t IDXF       : 1;            /*!< [20..20] desc IDXF                                                        */
      __IOM uint32_t DIRF       : 1;            /*!< [21..21] desc DIRF                                                        */
      __IOM uint32_t IERRF      : 1;            /*!< [22..22] desc IERRF                                                       */
      __IOM uint32_t TERRF      : 1;            /*!< [23..23] desc TERRF                                                       */
    } ICR_f;
  } ;
} GTIM_TypeDef;                                    /*!< Size = 116 (0x74)                                                         */



/* =========================================================================================================================== */
/* ================                                          HALLTIM                                          ================ */
/* =========================================================================================================================== */


/**
  * @brief HALL Timer (HALLTIM)
  */

typedef struct {                                /*!< (@ 0x40006400) HALLTIM Structure                                          */
  
  union {
    __IOM uint32_t CR;                          /*!< (@ 0x00000000) Control register1                                          */
    
    struct {
      __IOM uint32_t EN         : 1;            /*!< [0..0] desc EN                                                            */
      __IOM uint32_t FLT1EN     : 1;            /*!< [1..1] desc FLT1EN                                                         */
      __IOM uint32_t DIV        : 2;            /*!< [3..2] desc DIV                                                           */
      __IOM uint32_t MMS        : 3;            /*!< [6..4] desc MMS                                                           */
      __IM  uint32_t            : 1;
      __IOM uint32_t FLT2LEN    : 15;           /*!< [22..8] desc FLT2LEN                                                       */
      __IOM uint32_t SOFTCAP    : 1;            /*!< [23..23] desc SOFTCAP                                                    */
    } CR_f;
  } ;
  
  union {
    __IOM uint32_t DIER;                        /*!< (@ 0x00000004) DMA and Interrupt register2                                */
    
    struct {
      __IOM uint32_t CAPIE      : 1;            /*!< [0..0] desc CAPIE                                                         */
      __IOM uint32_t OVIE       : 1;            /*!< [1..1] desc OVIE                                                          */
      __IOM uint32_t MATCHIE    : 1;            /*!< [2..2] desc MATCHIE                                                       */
      __IM  uint32_t            : 1;
      __IOM uint32_t CAPDMA     : 1;            /*!< [4..4] desc CAPDMA                                                        */
      __IOM uint32_t OVDMA      : 1;            /*!< [5..5] desc OVDMA                                                         */
      __IOM uint32_t MATCHDMA   : 1;            /*!< [6..6] desc MATCHDMA                                                      */
      __IOM uint32_t SOFTDMA    : 1;            /*!< [7..7] desc SOFTDMA                                                       */
    } DIER_f;
  } ;
  
  union {
    __IOM uint32_t CNT;                         /*!< (@ 0x00000008) counter register                                           */
    
    struct {
      __IOM uint32_t DATA       : 24;           /*!< [23..0] desc CNT                                                          */
    } CNT_f;
  } ;
  
  union {
    __IOM uint32_t ARR;                         /*!< (@ 0x0000000C) Auto Reload Register                                       */
    
    struct {
      __IOM uint32_t DATA       : 24;           /*!< [23..0] desc ARR                                                          */
    } ARR_f;
  } ;
  
  union {
    __IM  uint32_t WIDTH;                       /*!< (@ 0x00000010) Width Register                                             */
    
    struct {
      __IM  uint32_t DATA       : 24;           /*!< [23..0] desc WIDTH                                                        */
    } WIDTH_f;
  } ;
  
  union {
    __IOM uint32_t CCR;                         /*!< (@ 0x00000014) Compare control Register                                   */
    
    struct {
      __IOM uint32_t DATA       : 24;           /*!< [23..0] desc CCR                                                          */
    } CCR_f;
  } ;
  
  union {
    __IM  uint32_t ISR;                         /*!< (@ 0x00000018) Interrupt states register                                  */
    
    struct {
      __IM  uint32_t CAPF       : 1;            /*!< [0..0] desc CAPF                                                         */
      __IM  uint32_t OV         : 1;            /*!< [1..1] desc OV                                                            */
      __IM  uint32_t MATCH      : 1;            /*!< [2..2] desc MATCH                                                         */
    } ISR_f;
  } ;
  
  union {
    __IOM uint32_t ICR;                         /*!< (@ 0x0000001C) Interrupt clean register                                   */
    
    struct {
      __IOM uint32_t CAPF       : 1;            /*!< [0..0] desc CHG                                                           */
      __IOM uint32_t OVF        : 1;            /*!< [1..1] desc OV                                                            */
      __IOM uint32_t MATCHF     : 1;            /*!< [2..2] desc MATCH                                                         */
    } ICR_f;
  } ;
  
  union {
    __IM  uint32_t STATE;                       /*!< (@ 0x00000020) State register                                             */
    
    struct {
      __IM  uint32_t CH1F       : 1;            /*!< desc CH1F                                                                 */
      __IM  uint32_t CH2F       : 1;            /*!< desc CH2F                                                                 */
      __IM  uint32_t CH3F       : 1;            /*!< desc CH3F                                                                 */
            uint32_t            : 1;
      __IM  uint32_t CH1S       : 1;            /*!< desc CH1S                                                                 */
      __IM  uint32_t CH2S       : 1;            /*!< desc CH2S                                                                 */
      __IM  uint32_t CH3S       : 1;            /*!< desc CH3S                                                                 */
    } STATE_f;
  } ;
} HALLTIM_TypeDef;                                 /*!< Size = 36 (0x24)                                                          */



/* =========================================================================================================================== */
/* ================                                           I2C1                                            ================ */
/* =========================================================================================================================== */


/**
  * @brief desc I2C1 (I2C1)
  */
typedef struct {                                /*!< (@ 0x40005800) I2C1 Structure                                             */
  __IM  uint32_t  RESERVED[2];

  union {
    __IOM uint32_t INSEL;                       /*!< (@ 0x00000008) Input selection register                                   */

    struct {
      __IOM uint32_t SCLINSEL   : 3;            /*!< [2..0] desc SCLINSEL                                                      */
      __IOM uint32_t SDAINSEL   : 3;            /*!< [5..3] desc SDAINSEL                                                      */
    } INSEL_f;
  } ;

  union {
    __IOM uint32_t MICR;                        /*!< (@ 0x0000000C) Master Interrupt Flag Clear Register                       */

    struct {
            uint32_t            : 8;
      __IOM uint32_t PACKET     : 1;            /*!< [8..8] desc PACKET                                                        */
      __IOM uint32_t STOP       : 1;            /*!< [9..9] desc STOP                                                          */
      __IOM uint32_t NACK       : 1;            /*!< [10..10] desc NACK                                                        */
      __IOM uint32_t ARBI       : 1;            /*!< [11..11] desc ARBI                                                        */
      __IOM uint32_t FIFO       : 1;            /*!< [12..12] desc FIFO                                                        */
      __IOM uint32_t PINLOW     : 1;            /*!< [13..13] desc PINLOW                                                      */
      __IOM uint32_t MATCH      : 1;            /*!< [14..14] desc MATCH                                                       */
    } MICR_f;
  } ;

  union {
    __IOM uint32_t MCR0;                        /*!< (@ 0x00000010) Master Control Register0                                   */

    struct {
      __IOM uint32_t MEN        : 1;            /*!< [0..0] desc MEN                                                           */
      __IOM uint32_t RESET      : 1;            /*!< [1..1] desc RESET                                                         */
      __IOM uint32_t SLEEPEN    : 1;            /*!< [2..2] desc SLEEPEN                                                       */
      __IOM uint32_t DBGEN      : 1;            /*!< [3..3] desc DBGEN                                                         */
      __IM  uint32_t            : 2;
      __IOM uint32_t CLKSRC     : 2;            /*!< [7..6] desc CLKSRC                                                        */
      __IOM uint32_t TXFIFORST  : 1;            /*!< [8..8] desc TXFIFORST                                                     */
      __IOM uint32_t RXFIFORST  : 1;            /*!< [9..9] desc RXFIFORST                                                     */
    } MCR0_f;
  } ;

  union {
    __IM  uint32_t MISR;                        /*!< (@ 0x00000014) Master Interrupt Status Register                           */

    struct {
      __IM  uint32_t TXE        : 1;            /*!< [0..0] desc TXE                                                           */
      __IM  uint32_t RXNE       : 1;            /*!< [1..1] desc RXNE                                                          */
            uint32_t            : 6;
      __IM  uint32_t PACKET     : 1;            /*!< [8..8] desc PACKET                                                        */
      __IM  uint32_t STOP       : 1;            /*!< [9..9] desc STOP                                                          */
      __IM  uint32_t NACK       : 1;            /*!< [10..10] desc NACK                                                        */
      __IM  uint32_t ARBI       : 1;            /*!< [11..11] desc ARBI                                                        */
      __IM  uint32_t FIFO       : 1;            /*!< [12..12] desc FIFO                                                        */
      __IM  uint32_t PINLOW     : 1;            /*!< [13..13] desc PINLOW                                                      */
      __IM  uint32_t MATCH      : 1;            /*!< [14..14] desc MATCH                                                       */
      __IM  uint32_t            : 9;
      __IM  uint32_t MSTBUSY    : 1;            /*!< [24..24] desc MSTBUSY                                                     */
      __IM  uint32_t BUSBUSY    : 1;            /*!< [25..25] desc BUSBUSY                                                     */
    } MISR_f;
  } ;

  union {
    __IOM uint32_t MIER;                        /*!< (@ 0x00000018) Master Interrupt Enable Register                           */

    struct {
      __IOM uint32_t TXE        : 1;            /*!< [0..0] desc TXE                                                           */
      __IOM uint32_t RXNE       : 1;            /*!< [1..1] desc RXNE                                                          */
            uint32_t            : 6;
      __IOM uint32_t PACKET     : 1;            /*!< [8..8] desc PACKET                                                        */
      __IOM uint32_t STOP       : 1;            /*!< [9..9] desc STOP                                                          */
      __IOM uint32_t NACK       : 1;            /*!< [10..10] desc NACK                                                        */
      __IOM uint32_t ARBI       : 1;            /*!< [11..11] desc ARBI                                                        */
      __IOM uint32_t FIFO       : 1;            /*!< [12..12] desc FIFO                                                        */
      __IOM uint32_t PINLOW     : 1;            /*!< [13..13] desc PINLOW                                                      */
      __IOM uint32_t MATCH      : 1;            /*!< [14..14] desc MATCH                                                       */
    } MIER_f;
  } ;

  union {
    __IOM uint32_t MDER;                        /*!< (@ 0x0000001C) Master DMA Enable Register                                 */

    struct {
      __IOM uint32_t TXE        : 1;            /*!< [0..0] desc TXE                                                           */
      __IOM uint32_t RXNE       : 1;            /*!< [1..1] desc RXNE                                                          */
    } MDER_f;
  } ;

  union {
    __IOM uint32_t MCR1;                        /*!< (@ 0x00000020) Master Control Register1                                   */

    struct {
      __IM  uint32_t            : 8;
      __IOM uint32_t CIRFIFO    : 1;            /*!< [8..8] desc CIRFIFO                                                       */
      __IOM uint32_t RDMO       : 1;            /*!< [9..9] desc RDMO                                                          */
    } MCR1_f;
  } ;

  union {
    union {
      __IOM uint32_t MCR2;                      /*!< (@ 0x00000024) Master Control Register2                                   */

      struct {
          __IOM uint32_t PRESCALE   : 3;        /*!< [2..0] desc PRESCALE                                                      */
          __IM  uint32_t            : 5;
          __IOM uint32_t AUTOSTOP   : 1;        /*!< [8..8] desc AUTOSTOP                                                      */
          __IOM uint32_t IGNACK     : 1;        /*!< [9..9] desc IGNACK                                                        */
          __IOM uint32_t TIMECFG    : 1;        /*!< [10..10] desc TIMECFG                                                     */
          __IM  uint32_t            : 4;
          __IOM uint32_t TRGSEL     : 1;        /*!< [15..15] desc TRGSEL                                                      */
          __IOM uint32_t MATCFG     : 3;        /*!< [18..16] desc MATCFG                                                      */
                uint32_t            : 5;
          __IOM uint32_t PINCFG     : 3;        /*!< [26..24] desc PINCFG                                                      */
      } MCR2_f;
    } ;

    union {
      __IOM uint32_t SCR2;                      /*!< (@ 0x00000024) desc SCR2                                                  */

      struct {
          __IM  uint32_t            : 24;
          __IOM uint32_t PINCFG     : 3;        /*!< [26..24] desc PINCFG                                                      */
      } SCR2_f;
    } ;
  } ;

  union {
    __IOM uint32_t MCR3;                        /*!< (@ 0x00000028) Master Control Register3                                   */

    struct {
      __IOM uint32_t BUSIDLE    : 12;           /*!< [11..0] desc BUSIDLE                                                      */
      __IM  uint32_t            : 4;
      __IOM uint32_t FLTSCL     : 4;            /*!< [19..16] desc FLTSCL                                                      */
      __IM  uint32_t            : 4;
      __IOM uint32_t FLTSDA     : 4;            /*!< [27..24] desc FLTSDA                                                      */
    } MCR3_f;
  } ;

  union {
    __IOM uint32_t MCR4;                        /*!< (@ 0x0000002C) Master Control Register4                                   */

    struct {
      __IM  uint32_t            : 8;
      __IOM uint32_t PINLOW     : 12;           /*!< [19..8] desc PINLOW                                                       */
    } MCR4_f;
  } ;
  __IM  uint32_t  RESERVED1[4];

  union {
    __IOM uint32_t MMATCH;                      /*!< (@ 0x00000040) Master Match Register                                      */

    struct {
      __IOM uint32_t MATCH0     : 8;            /*!< [7..0] desc MATCH0                                                        */
      __IM  uint32_t            : 8;
      __IOM uint32_t MATCH1     : 8;            /*!< [23..16] desc MATCH1                                                      */
    } MMATCH_f;
  } ;
  __IM  uint32_t  RESERVED2;

  union {
    __IOM uint32_t MCCR;                        /*!< (@ 0x00000048) Master Clock Control Register0                             */

    struct {
      __IOM uint32_t CLKLO      : 6;            /*!< [5..0] desc CLKLO                                                         */
      __IM  uint32_t            : 2;
      __IOM uint32_t CLKHI      : 6;            /*!< [13..8] desc CLKHI                                                        */
      __IM  uint32_t            : 2;
      __IOM uint32_t SETHOLD    : 6;            /*!< [21..16] desc SETHOLD                                                     */
      __IM  uint32_t            : 2;
      __IOM uint32_t DATAVD     : 6;            /*!< [29..24] desc DATAVD                                                      */
    } MCCR_f;
  } ;
  __IM  uint32_t  RESERVED3[3];

  union {
    __IOM uint32_t MFIFOCR;                     /*!< (@ 0x00000058) Master FIFO Control Register                               */

    struct {
      __IOM uint32_t TXWATER    : 1;            /*!< [0..0] desc TXWATER                                                       */
      __IM  uint32_t            : 15;
      __IOM uint32_t RXWATER    : 1;            /*!< [16..16] desc RXWATER                                                     */
    } MFIFOCR_f;
  } ;

  union {
    __IM  uint32_t MFIFOSR;                     /*!< (@ 0x0000005C) Master FIFO Status Register                                */

    struct {
      __IM  uint32_t TXCNT      : 2;            /*!< [1..0] desc TXCNT                                                         */
      __IM  uint32_t            : 14;
      __IM  uint32_t RXCNT      : 2;            /*!< [17..16] desc RXCNT                                                       */
    } MFIFOSR_f;
  } ;

  union {
    __OM  uint32_t MTDR;                        /*!< (@ 0x00000060) Master Tx Data Register                                    */

    struct {
      __OM  uint32_t DATA       : 8;            /*!< [7..0] desc DATA                                                          */
      __OM  uint32_t CMD        : 3;            /*!< [10..8] desc CMD                                                          */
    } MTDR_f;
  } ;
  __IM  uint32_t  RESERVED4[3];
  
  union {
    __IM  uint32_t MRDR;                        /*!< (@ 0x00000070) Master Rx Data Register                                    */

    struct {
      __IM  uint32_t DATA       : 8;            /*!< [7..0] desc DATA                                                          */
      __IM  uint32_t            : 6;
      __IM  uint32_t EMPTY      : 1;            /*!< [14..14] desc EMPTY                                                       */
    } MRDR_f;
  } ;
  __IM  uint32_t  RESERVED5[38];
  
  union {
    __IOM uint32_t SICR;                        /*!< (@ 0x0000010C) desc SICR                                                  */

    struct {
      __IM  uint32_t            : 8;
      __IOM uint32_t RESTART    : 1;            /*!< [8..8] desc RESTART                                                       */
      __IOM uint32_t STOP       : 1;            /*!< [9..9] desc STOP                                                          */
      __IOM uint32_t BIT        : 1;            /*!< [10..10] desc BIT                                                         */
      __IOM uint32_t FIFO       : 1;            /*!< [11..11] desc FIFO                                                        */
    } SICR_f;
  } ;

  union {
    __IOM uint32_t SCR0;                        /*!< (@ 0x00000110) Slave Control Register0                                    */

    struct {
      __IOM uint32_t SEN        : 1;            /*!< [0..0] desc SEN                                                           */
      __IOM uint32_t RESET      : 1;            /*!< [1..1] desc RESET                                                         */
      __IM  uint32_t            : 2;
      __IOM uint32_t FLTEN      : 1;            /*!< [4..4] desc FLTEN                                                         */
      __IM  uint32_t            : 1;
      __IOM uint32_t CLKSRC     : 2;            /*!< [7..6] desc CLKSRC                                                        */
      __IOM uint32_t TXFIFORST  : 1;            /*!< [8..8] desc TXFIFORST                                                     */
      __IOM uint32_t RXFIFORST  : 1;            /*!< [9..9] desc RXFIFORST                                                     */
    } SCR0_f;
  } ;

  union {
    __IM  uint32_t SISR;                        /*!< (@ 0x00000114) desc SISR                                                  */

    struct {
      __IM  uint32_t TXE        : 1;            /*!< [0..0] desc TXE                                                           */
      __IM  uint32_t RXNE       : 1;            /*!< [1..1] desc RXNE                                                          */
      __IM  uint32_t ADDR       : 1;            /*!< [2..2] desc ADDR                                                          */
      __IM  uint32_t TACK       : 1;            /*!< [3..3] desc TACK                                                          */
      __IM  uint32_t            : 4;
      __IM  uint32_t RESTART    : 1;            /*!< [8..8] desc RESTART                                                       */
      __IM  uint32_t STOP       : 1;            /*!< [9..9] desc STOP                                                          */
      __IM  uint32_t BIT        : 1;            /*!< [10..10] desc BIT                                                         */
      __IM  uint32_t FIFO       : 1;            /*!< [11..11] desc FIFO                                                        */
      __IM  uint32_t AM0        : 1;            /*!< [12..12] desc AM0                                                         */
      __IM  uint32_t AM1        : 1;            /*!< [13..13] desc AM1                                                         */
      __IM  uint32_t GC         : 1;            /*!< [14..14] desc GC                                                          */
      __IM  uint32_t ALERT      : 1;            /*!< [15..15] desc ALERT                                                       */
      __IM  uint32_t            : 8;
      __IM  uint32_t SLVBUSY    : 1;            /*!< [24..24] desc SLVBUSY                                                     */
      __IM  uint32_t BUSBUSY    : 1;            /*!< [25..25] desc BUSBUSY                                                     */
    } SISR_f;
  } ;

  union {
    __IOM uint32_t SIER;                        /*!< (@ 0x00000118) desc SIER                                                  */

    struct {
      __IOM uint32_t TXE        : 1;            /*!< [0..0] desc TXE                                                           */
      __IOM uint32_t RXNE       : 1;            /*!< [1..1] desc RXNE                                                          */
      __IOM uint32_t ADDR       : 1;            /*!< [2..2] desc ADDR                                                          */
      __IOM uint32_t TACK       : 1;            /*!< [3..3] desc TACK                                                          */
      __IM  uint32_t            : 4;
      __IOM uint32_t RESTART    : 1;            /*!< [8..8] desc RESTART                                                       */
      __IOM uint32_t STOP       : 1;            /*!< [9..9] desc STOP                                                          */
      __IOM uint32_t BIT        : 1;            /*!< [10..10] desc BIT                                                         */
      __IOM uint32_t FIFO       : 1;            /*!< [11..11] desc FIFO                                                        */
      __IOM uint32_t AM0        : 1;            /*!< [12..12] desc AM0                                                         */
      __IOM uint32_t AM1        : 1;            /*!< [13..13] desc AM1                                                         */
      __IOM uint32_t GC         : 1;            /*!< [14..14] desc GC                                                          */
      __IOM uint32_t ALERT      : 1;            /*!< [15..15] desc ALERT                                                       */
    } SIER_f;
  } ;

  union {
    __IOM uint32_t SDER;                        /*!< (@ 0x0000011C) desc SDER                                                  */

    struct {
      __IOM uint32_t TXE        : 1;            /*!< [0..0] desc TXE                                                           */
      __IOM uint32_t RXNE       : 1;            /*!< [1..1] desc RXNE                                                          */
      __IOM uint32_t ADDR       : 1;            /*!< [2..2] desc ADDR                                                          */
    } SDER_f;
  } ;
  __IM  uint32_t  RESERVED6;
  
  union {
    __IOM uint32_t SCR1;                        /*!< (@ 0x00000124) desc SCR1                                                  */

    struct {
      __IOM uint32_t ADRSTALL   : 1;            /*!< [0..0] desc ADRSTALL                                                      */
      __IOM uint32_t RXSTALL    : 1;            /*!< [1..1] desc RXSTALL                                                       */
      __IOM uint32_t TXSTALL    : 1;            /*!< [2..2] desc TXSTALL                                                       */
      __IOM uint32_t ACKSTALL   : 1;            /*!< [3..3] desc ACKSTALL                                                      */
      __IM  uint32_t            : 4;
      __IOM uint32_t GCEN       : 1;            /*!< [8..8] desc GCEN                                                          */
      __IOM uint32_t ALERTEN    : 1;            /*!< [9..9] desc ALERTEN                                                       */
      __IOM uint32_t TXCFG      : 1;            /*!< [10..10] desc TXCFG                                                       */
      __IOM uint32_t RXCFG      : 1;            /*!< [11..11] desc RXCFG                                                       */
      __IOM uint32_t IGNACK     : 1;            /*!< [12..12] desc IGNACK                                                      */
            uint32_t            : 2;
      __IOM uint32_t TRGSEL     : 1;            /*!< [15..15] desc TRGSEL                                                      */
      __IOM uint32_t ADDRCFG    : 3;            /*!< [18..16] desc ADDRCFG                                                     */
    } SCR1_f;
  } ;

  union {
    __IOM uint32_t SCR3;                        /*!< (@ 0x00000128) desc SCR3                                                  */

    struct {
      __IOM uint32_t CLKHOLD    : 4;            /*!< [3..0] desc CLKHOLD                                                       */
      __IM  uint32_t            : 4;
      __IOM uint32_t DATAVD     : 6;            /*!< [13..8] desc DATAVD                                                       */
      __IM  uint32_t            : 2;
      __IOM uint32_t FLTSCL     : 4;            /*!< [19..16] desc FLTSCL                                                      */
      __IM  uint32_t            : 4;
      __IOM uint32_t FLTSDA     : 4;            /*!< [27..24] desc FLTSDA                                                      */
    } SCR3_f;
  } ;
  __IM  uint32_t  RESERVED7[5];

  union {
    __IOM uint32_t SAMR;                        /*!< (@ 0x00000140) desc SAMR                                                  */

    struct {
      __IM  uint32_t            : 1;
      __IOM uint32_t ADDR0      : 10;           /*!< [10..1] desc ADDR0                                                        */
      __IM  uint32_t            : 6;
      __IOM uint32_t ADDR1      : 10;           /*!< [26..17] desc ADDR1                                                       */
    } SAMR_f;
  } ;
  __IM  uint32_t  RESERVED8[3];

  union {
    __IM  uint32_t SASR;                        /*!< (@ 0x00000150) desc SASR                                                  */

    struct {
      __IM  uint32_t RADDR      : 11;           /*!< [10..0] desc RADDR                                                        */
      __IM  uint32_t            : 3;
      __IM  uint32_t ANV        : 1;            /*!< [14..14] desc ANV                                                         */
    } SASR_f;
  } ;

  union {
    __IOM uint32_t STAR;                        /*!< (@ 0x00000154) desc STAR                                                  */

    struct {
      __IOM uint32_t TXNACK     : 1;            /*!< [0..0] desc TXNACK                                                        */
    } STAR_f;
  } ;
  __IM  uint32_t  RESERVED9[2];

  union {
    __OM  uint32_t STDR;                        /*!< (@ 0x00000160) desc STDR                                                  */

    struct {
      __OM  uint32_t DATA       : 8;            /*!< [7..0] desc DATA                                                          */
    } STDR_f;
  } ;
  __IM  uint32_t  RESERVED10[3];

  union {
    __IM  uint32_t SRDR;                        /*!< (@ 0x00000170) desc SRDR                                                  */

    struct {
      __IM  uint32_t DATA       : 8;            /*!< [7..0] desc DATA                                                          */
      __IM  uint32_t            : 6;
      __IM  uint32_t RXEMPTY    : 1;            /*!< [14..14] desc RXEMPTY                                                     */
      __IM  uint32_t SOF        : 1;            /*!< [15..15] desc SOF                                                         */
    } SRDR_f;
  } ;
} I2C_TypeDef;                                     /*!< Size = 372 (0x174)                                                        */



/* =========================================================================================================================== */
/* ================                                           IRMOD                                           ================ */
/* =========================================================================================================================== */


/**
  * @brief desc IRMOD (IRMOD)
  */

typedef struct {                                /*!< (@ 0x40004080) IRMOD Structure                                            */
  union {
    __IOM uint32_t CR;                          /*!< (@ 0x00000000) Input selection register                                   */
    
    struct {
      __IOM uint32_t MOD        : 4;            /*!< [3..0] desc MOD                                                           */
      __IOM uint32_t IRSW       : 1;            /*!< [4..4] desc IRSW                                                          */
      __IOM uint32_t INV        : 1;            /*!< [5..5] desc INV                                                           */
    } CR_f;
  } ;
} IRMOD_TypeDef;                                   /*!< Size = 12 (0xc)                                                           */



/* =========================================================================================================================== */
/* ================                                           IWDT                                            ================ */
/* =========================================================================================================================== */


/**
  * @brief desc IWDT (IWDT)
  */

typedef struct {                                /*!< (@ 0x40005000) IWDT Structure                                             */
  
  union {
    __OM  uint32_t KR;                          /*!< (@ 0x00000000) Key register                                               */
    
    struct {
      __OM  uint32_t KR         : 16;           /*!< [15..0] desc KR                                                           */
    } KR_f;
  } ;
  
  union {
    __IOM uint32_t CR;                          /*!< (@ 0x00000004) Control register                                           */
    
    struct {
      __IOM uint32_t PRS        : 3;            /*!< [2..0] desc PRS                                                           */
      __IOM uint32_t ACTION     : 1;            /*!< [3..3] desc ACTION                                                        */
      __IOM uint32_t IE         : 1;            /*!< [4..4] desc IE                                                            */
      __IOM uint32_t PAUSE      : 1;            /*!< [5..5] desc PAUSE                                                         */
    } CR_f;
  } ;
  
  union {
    __IOM uint32_t ARR;                         /*!< (@ 0x00000008) Auto reload register                                       */
    
    struct {
      __IOM uint32_t ARR        : 12;           /*!< [11..0] desc ARR                                                          */
    } ARR_f;
  } ;
  
  union {
    __IOM uint32_t SR;                          /*!< (@ 0x0000000C) Status register                                            */
    
    struct {
      __IM  uint32_t CRF        : 1;            /*!< [0..0] desc CRF                                                           */
      __IM  uint32_t ARRF       : 1;            /*!< [1..1] desc ARRF                                                          */
      __IM  uint32_t WINRF      : 1;            /*!< [2..2] desc WINRF                                                         */
      __IOM uint32_t OV         : 1;            /*!< [3..3] desc OV                                                            */
      __IM  uint32_t RUN        : 1;            /*!< [4..4] desc RUN                                                           */
      __IM  uint32_t RELOAD     : 1;            /*!< [5..5] desc RELOAD                                                        */
    } SR_f;
  } ;
  
  union {
    __IOM uint32_t WINR;                        /*!< (@ 0x00000010) Window register                                            */
    
    struct {
      __IOM uint32_t WINR       : 12;           /*!< [11..0] desc WINR                                                         */
    } WINR_f;
  } ;
  __IM  uint32_t  RESERVED[4];
  
  union {
    __IM  uint32_t CNT;                         /*!< (@ 0x00000024) counter                                                    */
    
    struct {
      __IM  uint32_t CNT        : 12;           /*!< [11..0] desc CNT                                                          */
    } CNT_f;
  } ;
} IWDT_TypeDef;                                    /*!< Size = 40 (0x28)                                                          */



/* =========================================================================================================================== */
/* ================                                           LPTIM                                           ================ */
/* =========================================================================================================================== */


/**
  * @brief desc LPTIM (LPTIM)
  */

typedef struct {                                /*!< (@ 0x40006000) LPTIM Structure                                            */
  
  union {
    __IM  uint32_t ISR;                         /*!< (@ 0x00000000) desc ISR                                                   */
    
    struct {
      __IM  uint32_t CMPM       : 1;            /*!< [0..0] desc CMPM                                                          */
      __IM  uint32_t ARRM       : 1;            /*!< [1..1] desc ARRM                                                          */
      __IM  uint32_t EXTTRIG    : 1;            /*!< [2..2] desc EXTTRIG                                                       */
      __IM  uint32_t CMPOK      : 1;            /*!< [3..3] desc CMPOK                                                         */
      __IM  uint32_t ARROK      : 1;            /*!< [4..4] desc ARROK                                                         */
      __IM  uint32_t UP         : 1;            /*!< [5..5] desc UP                                                            */
      __IM  uint32_t DOWN       : 1;            /*!< [6..6] desc DOWN                                                          */
      __IM  uint32_t DIR        : 2;            /*!< [8..7] desc DIR                                                           */
    } ISR_f;
  } ;
  
  union {
    __IOM uint32_t ICR;                         /*!< (@ 0x00000004) desc ICR                                                   */
    
    struct {
      __IOM uint32_t CMPM       : 1;            /*!< [0..0] desc CMPM                                                          */
      __IOM uint32_t ARRM       : 1;            /*!< [1..1] desc ARRM                                                          */
      __IOM uint32_t EXTTRIG    : 1;            /*!< [2..2] desc EXTTRIG                                                       */
      __IOM uint32_t CMPOK      : 1;            /*!< [3..3] desc CMPOK                                                         */
      __IOM uint32_t ARROK      : 1;            /*!< [4..4] desc ARROK                                                         */
      __IOM uint32_t UP         : 1;            /*!< [5..5] desc UP                                                            */
      __IOM uint32_t DOWN       : 1;            /*!< [6..6] desc DOWN                                                          */
    } ICR_f;
  } ;
  
  union {
    __IOM uint32_t IER;                         /*!< (@ 0x00000008) desc IER                                                   */
    
    struct {
      __IOM uint32_t CMPM       : 1;            /*!< [0..0] desc CMPM                                                          */
      __IOM uint32_t ARRM       : 1;            /*!< [1..1] desc ARRM                                                          */
      __IOM uint32_t EXTTRIG    : 1;            /*!< [2..2] desc EXTTRIG                                                       */
      __IOM uint32_t CMPOK      : 1;            /*!< [3..3] desc CMPOK                                                         */
      __IOM uint32_t ARROK      : 1;            /*!< [4..4] desc ARROK                                                         */
      __IOM uint32_t UP         : 1;            /*!< [5..5] desc UP                                                            */
      __IOM uint32_t DOWN       : 1;            /*!< [6..6] desc DOWN                                                          */
    } IER_f;
  } ;
  
  union {
    __IOM uint32_t CFGR;                        /*!< (@ 0x0000000C) desc CFGR1                                                 */
    
    struct {
      __IOM uint32_t CKSEL      : 1;            /*!< [0..0] desc CKSEL                                                         */
      __IOM uint32_t ENCMD_CKPOL : 2;           /*!< [2..1] desc ENCMD_CKPOL                                                   */
      __IOM uint32_t CHFLT      : 2;            /*!< [4..3] desc CHFLT                                                         */
      __IM  uint32_t            : 1;
      __IOM uint32_t TRIGFLT    : 2;            /*!< [7..6] desc TRIGFLT                                                       */
      __IM  uint32_t            : 1;
      __IOM uint32_t PRS        : 3;            /*!< [11..9] desc PRS                                                          */
      __IOM uint32_t TRIGSEL    : 4;            /*!< [15..12] desc TRIGSEL                                                     */
      __IM  uint32_t            : 1;
      __IOM uint32_t TRIGEN     : 2;            /*!< [18..17] desc TRIGEN                                                      */
      __IOM uint32_t TIMOUT     : 1;            /*!< [19..19] desc TIMOUT                                                      */
      __IOM uint32_t WAVE       : 1;            /*!< [20..20] desc WAVE                                                        */
      __IOM uint32_t WAVPOL     : 1;            /*!< [21..21] desc WAVPOL                                                      */
      __IOM uint32_t PRELOAD    : 1;            /*!< [22..22] desc PRELOAD                                                     */
      __IOM uint32_t COUNTMD    : 1;            /*!< [23..23] desc COUNTMD                                                     */
      __IOM uint32_t ENC        : 1;            /*!< [24..24] desc ENC                                                         */
      __IOM uint32_t ICLKSRC    : 2;            /*!< [26..25] desc ICLKSRC                                                     */
    } CFGR_f;
  } ;
  
  union {
    __IOM uint32_t CR0;                         /*!< (@ 0x00000010) desc CR                                                    */
    
    struct {
      __IOM uint32_t EN         : 1;            /*!< [0..0] desc EN                                                            */
      __IOM uint32_t SNGSTART   : 1;            /*!< [1..1] desc SNGSTART                                                      */
      __IOM uint32_t CNTSTART   : 1;            /*!< [2..2] desc CNTSTART                                                      */
      __IOM uint32_t SRST       : 1;            /*!< [3..3] desc SRST                                                          */
      __IOM uint32_t ARST       : 1;            /*!< [4..4] desc ARST                                                          */
    } CR0_f;
  } ;
  
  union {
    __IOM uint32_t CMP;                         /*!< (@ 0x00000014) desc CMP                                                   */
    
    struct {
      __IOM uint32_t CMP        : 16;           /*!< [15..0] desc CMP                                                          */
    } CMP_f;
  } ;
  
  union {
    __IOM uint32_t ARR;                         /*!< (@ 0x00000018) desc ARR                                                   */
    
    struct {
      __IOM uint32_t ARR        : 16;           /*!< [15..0] desc ARR                                                          */
    } ARR_f;
  } ;
  
  union {
    __IM  uint32_t CNT;                         /*!< (@ 0x0000001C) desc CNT                                                   */
    
    struct {
      __IM  uint32_t CNT        : 16;           /*!< [15..0] desc CNT                                                          */
    } CNT_f;
  } ;
  
  union {
    __IOM uint32_t CR1;                       /*!< (@ 0x00000020) desc CFGR2                                                 */
    
    struct {
      __IOM uint32_t CH1SRC     : 3;            /*!< [2..0] desc CH1SRC                                                        */
      __IOM uint32_t CH2SRC     : 3;            /*!< [5..3] desc CH2SRC                                                        */
    } CR1_f;
  } ;
} LPTIM_TypeDef;                                   /*!< Size = 36 (0x24)                                                          */



/* =========================================================================================================================== */
/* ================                                           UART1                                           ================ */
/* =========================================================================================================================== */


/**
  * @brief desc UART1 (UART1)
  */

typedef struct {                                /*!< (@ 0x40000C00) UART1 Structure                                            */
  
  union {
    __IOM uint32_t CR1;                         /*!< (@ 0x00000000) Control register1                                          */
    
    struct {
      __IOM uint32_t TXEN       : 1;            /*!< [0..0] desc TXEN                                                          */
      __IOM uint32_t RXEN       : 1;            /*!< [1..1] desc RXEN                                                          */
      __IOM uint32_t PARITY     : 1;            /*!< [2..2] desc PARITY                                                        */
      __IOM uint32_t PARITYEN   : 1;            /*!< [3..3] desc PARITYEN                                                      */
      __IOM uint32_t STOP       : 2;            /*!< [5..4] desc STOP                                                          */
      __IOM uint32_t CHLEN      : 1;            /*!< [6..6] desc CHLEN                                                         */
      __IOM uint32_t MSBF       : 1;            /*!< [7..7] desc MSBF                                                          */
      __IOM uint32_t START      : 1;            /*!< [8..8] desc START                                                         */
      __IOM uint32_t OVER       : 2;            /*!< [10..9] desc OVER                                                         */
      __IOM uint32_t SIGNAL     : 1;            /*!< [11..11] desc SIGNAL                                                      */
      __IOM uint32_t SOURCE     : 2;            /*!< [13..12] desc SOURCE                                                      */
      __IOM uint32_t SYNC       : 1;            /*!< [14..14] desc SYNC                                                        */
    } CR1_f;
  } ;
  
  union {
    __IOM uint32_t CR2;                         /*!< (@ 0x00000004) Control register2                                          */
    
    struct {
      __IOM uint32_t ADDREN     : 1;            /*!< [0..0] desc ADDREN                                                        */
      __IOM uint32_t RXMATCHEN  : 1;            /*!< [1..1] desc RXMATCHEN                                                     */
      __IOM uint32_t CTSEN      : 1;            /*!< [2..2] desc CTSEN                                                         */
      __IOM uint32_t RTSEN      : 1;            /*!< [3..3] desc RTSEN                                                         */
      __IOM uint32_t RXINV      : 1;            /*!< [4..4] desc RXINV                                                         */
      __IOM uint32_t TXINV      : 1;            /*!< [5..5] desc TXINV                                                         */
      __IOM uint32_t DMARX      : 1;            /*!< [6..6] desc DMARX                                                         */
      __IOM uint32_t DMATX      : 1;            /*!< [7..7] desc DMATX                                                         */
      __IOM uint32_t TIMCR      : 3;            /*!< [10..8] desc TIMCR                                                        */
      __IOM uint32_t SWAP       : 1;            /*!< [11..11] desc SWAP                                                        */
      __IOM uint32_t ADCRX      : 1;            /*!< desc ADCRX                                                                */
      __IOM uint32_t ADCTX      : 1;            /*!< desc ADCTX                                                                */
      __IOM uint32_t LOOP       : 1;            /*!< [14..14] desc LOOP                                                        */
      __IOM uint32_t RXSRC      : 3;            /*!< [17..15] desc RXSRC                                                       */
    } CR2_f;
  } ;
  
  union {
    __IOM uint32_t IER;                         /*!< (@ 0x00000008) Interrupt enable register                                  */
    
    struct {
      __IOM uint32_t TXE        : 1;            /*!< [0..0] desc TXE                                                           */
      __IOM uint32_t TC         : 1;            /*!< [1..1] desc TC                                                            */
      __IOM uint32_t RC         : 1;            /*!< [2..2] desc RC                                                            */
      __IOM uint32_t RXIDLE     : 1;            /*!< [3..3] desc RXIDLE                                                        */
      __IOM uint32_t RXBRK      : 1;            /*!< [4..4] desc RXBRK                                                         */
      __IOM uint32_t BAUD       : 1;            /*!< [5..5] desc BAUD                                                          */
      __IOM uint32_t TIMOV      : 1;            /*!< [6..6] desc TIMOV                                                         */
      __IOM uint32_t CTS        : 1;            /*!< [7..7] desc CTS                                                           */
      __IOM uint32_t FE         : 1;            /*!< [8..8] desc FE                                                            */
      __IOM uint32_t PE         : 1;            /*!< [9..9] desc PE                                                            */
      __IOM uint32_t NE         : 1;            /*!< [10..10] desc NE                                                          */
      __IOM uint32_t ORE        : 1;            /*!< [11..11] desc ORE                                                         */
      __IOM uint32_t RXMATCH    : 1;            /*!< [12..12] desc RXMATCH                                                     */
    } IER_f;
  } ;
  
  union {
    __IOM uint32_t BRRI;                        /*!< (@ 0x0000000C) desc BRRI                                                  */
    
    struct {
      __IOM uint32_t BRRI       : 16;           /*!< [15..0] desc BRRI                                                         */
    } BRRI_f;
  } ;
  
  union {
    __IOM uint32_t BRRF;                        /*!< (@ 0x00000010) desc BRRF                                                  */
    
    struct {
      __IOM uint32_t BRRF       : 4;            /*!< [3..0] desc BRRF                                                          */
    } BRRF_f;
  } ;
  
  union {
    __IOM uint32_t TIMARR;                      /*!< (@ 0x00000014) desc TIMARR                                                */
    
    struct {
      __IOM uint32_t TIMARR     : 24;           /*!< [23..0] desc TIMARR                                                       */
    } TIMARR_f;
  } ;
  
  union {
    __IM  uint32_t TIMCNT;                      /*!< (@ 0x00000018) desc TIMCNT                                                */
    
    struct {
      __IM  uint32_t TIMCNT     : 24;           /*!< [23..0] desc TIMCNT                                                       */
    } TIMCNT_f;
  } ;
  
  union {
    __IM  uint32_t ISR;                         /*!< (@ 0x0000001C) Interrupt status register                                  */
    
    struct {
      __IM  uint32_t TXE        : 1;            /*!< [0..0] desc TXE                                                           */
      __IM  uint32_t TC         : 1;            /*!< [1..1] desc TC                                                            */
      __IM  uint32_t RC         : 1;            /*!< [2..2] desc RC                                                            */
      __IM  uint32_t RXIDLE     : 1;            /*!< [3..3] desc RXIDLE                                                        */
      __IM  uint32_t RXBRK      : 1;            /*!< [4..4] desc RXBRK                                                         */
      __IM  uint32_t BAUD       : 1;            /*!< [5..5] desc BAUD                                                          */
      __IM  uint32_t TIMOV      : 1;            /*!< [6..6] desc TIMOV                                                         */
      __IM  uint32_t CTS        : 1;            /*!< [7..7] desc CTS                                                           */
      __IM  uint32_t FE         : 1;            /*!< [8..8] desc FE                                                            */
      __IM  uint32_t PE         : 1;            /*!< [9..9] desc PE                                                            */
      __IM  uint32_t NE         : 1;            /*!< [10..10] desc NE                                                          */
      __IM  uint32_t ORE        : 1;            /*!< [11..11] desc ORE                                                         */
      __IM  uint32_t RXMATCH    : 1;            /*!< [12..12] desc RXMATCH                                                     */
      __IM  uint32_t SLVMATCH   : 1;            /*!< [13..13] desc SLVMATCH                                                    */
      __IM  uint32_t TXBUSY     : 1;            /*!< [14..14] desc TXBUSY                                                      */
      __IM  uint32_t CTSLV      : 1;            /*!< [15..15] desc CTSLV                                                       */
    } ISR_f;
  } ;
  
  union {
    __IOM uint32_t ICR;                         /*!< (@ 0x00000020) Interrupt flag clear register                              */
    
    struct {
      __IM  uint32_t            : 1;
      __IOM uint32_t TC         : 1;            /*!< [1..1] desc TC                                                            */
      __IOM uint32_t RC         : 1;            /*!< [2..2] desc RC                                                            */
      __IOM uint32_t RXIDLE     : 1;            /*!< [3..3] desc RXIDLE                                                        */
      __IOM uint32_t RXBRK      : 1;            /*!< [4..4] desc RXBRK                                                         */
      __IOM uint32_t BAUD       : 1;            /*!< [5..5] desc BAUD                                                          */
      __IOM uint32_t TIMOV      : 1;            /*!< [6..6] desc TIMOV                                                         */
      __IOM uint32_t CTS        : 1;            /*!< [7..7] desc CTS                                                           */
      __IOM uint32_t FE         : 1;            /*!< [8..8] desc FE                                                            */
      __IOM uint32_t PE         : 1;            /*!< [9..9] desc PE                                                            */
      __IOM uint32_t NE         : 1;            /*!< [10..10] desc NE                                                          */
      __IOM uint32_t ORE        : 1;            /*!< [11..11] desc ORE                                                         */
      __IOM uint32_t RXMATCH    : 1;            /*!< [12..12] desc RXMATCH                                                     */
    } ICR_f;
  } ;
  
  union {
    __IM  uint32_t RDR;                         /*!< (@ 0x00000024) Data reg for read                                          */
    
    struct {
      __IM  uint32_t RDR        : 9;            /*!< [8..0] desc RDR                                                           */
    } RDR_f;
  } ;
  
  union {
    __OM  uint32_t TDR;                         /*!< (@ 0x00000028) Data reg for write                                         */
    
    struct {
      __OM  uint32_t TDR        : 9;            /*!< [8..0] desc TDR                                                           */
      __OM  uint32_t IDLE       : 1;            /*!< [9..9] desc IDLE                                                          */
      __OM  uint32_t BREAK      : 1;            /*!< [10..10] desc BREAK                                                       */
    } TDR_f;
  } ;
  __IM  uint32_t  RESERVED;
  
  union {
    __IOM uint32_t ADDR;                        /*!< (@ 0x00000030) Slave addr                                                 */
    
    struct {
      __IOM uint32_t ADDR       : 8;            /*!< [7..0] desc ADDR                                                          */
    } ADDR_f;
  } ;
  
  union {
    __IOM uint32_t MASK;                        /*!< (@ 0x00000034) Slave addr mask                                            */
    
    struct {
      __IOM uint32_t MASK       : 8;            /*!< [7..0] desc MASK                                                          */
    } MASK_f;
  } ;
  
  union {
    __IOM uint32_t CR3;                         /*!< (@ 0x00000038) Control register3                                          */
    
    struct {
      __IOM uint32_t DEM        : 1;            /*!< [0..0] desc DEM                                                           */
      __IOM uint32_t DEP        : 1;            /*!< desc DEP                                                                  */
      __IOM uint32_t DETIME     : 5;            /*!< [6..2] desc DETIME                                                        */
      __IOM uint32_t LIN        : 1;            /*!< [7..7] desc LIN                                                           */
      __IOM uint32_t BRKL       : 1;            /*!< [8..8] desc BRKL                                                          */
    } CR3_f;
  } ;
  
  union {
    __IOM uint32_t RXMATCH;                     /*!< (@ 0x0000003C) desc RXMATCH                                               */
    
    struct {
      __IOM uint32_t RXMATCH    : 9;            /*!< [8..0] desc RXMATCH                                                       */
    } RXMATCH_f;
  } ;
} UART_TypeDef;                                    /*!< Size = 64 (0x40)                                                          */



/* =========================================================================================================================== */
/* ================                                            LVD                                            ================ */
/* =========================================================================================================================== */


/**
  * @brief desc LVD (LVD)
  */

typedef struct {                                /*!< (@ 0x400000A4) LVD Structure                                              */
  
  union {
    __IOM uint32_t CR0;                         /*!< (@ 0x00000000) Control register0                                          */
    
    struct {
      __IOM uint32_t EN         : 1;            /*!< [0..0] desc EN                                                            */
      __IOM uint32_t ACTION     : 1;            /*!< [1..1] desc ACTION                                                        */
      __IOM uint32_t SOURCE     : 1;            /*!< [2..2] desc SOURCE                                                        */
      __IM  uint32_t            : 1;
      __IOM uint32_t VTH        : 3;            /*!< [6..4] desc VTH                                                           */
      __IM  uint32_t            : 1;
      __IOM uint32_t FLTCLK     : 1;            /*!< [8..8] desc FLTCLK                                                        */
    } CR0_f;
  } ;
  
  union {
    __IOM uint32_t CR1;                         /*!< (@ 0x00000004) Control register1                                          */
    
    struct {
      __IOM uint32_t IE         : 1;            /*!< [0..0] desc IE                                                            */
      __IOM uint32_t LEVEL      : 1;            /*!< [1..1] desc LEVEL                                                         */
      __IOM uint32_t RISE       : 1;            /*!< [2..2] desc RISE                                                          */
      __IOM uint32_t FALL       : 1;            /*!< [3..3] desc FALL                                                          */
      __IOM uint32_t FLTTIME    : 4;            /*!< [7..4] desc FLTTIME                                                       */
    } CR1_f;
  } ;
  
  union {
    __IOM uint32_t SR;                          /*!< (@ 0x00000008) status register                                            */
    
    struct {
      __IOM uint32_t INTF       : 1;            /*!< [0..0] desc INTF                                                          */
      __IM  uint32_t FLTV       : 1;            /*!< [1..1] desc FLTV                                                          */
    } SR_f;
  } ;
} LVD_TypeDef;                                     /*!< Size = 12 (0xc)                                                           */



/* =========================================================================================================================== */
/* ================                                           OPA1                                            ================ */
/* =========================================================================================================================== */


/**
  * @brief desc OPA1 (OPA1)
  */

typedef struct {                                /*!< (@ 0x400000B0) OPA1 Structure                                             */
  
  union {
    __IOM uint32_t CR;                          /*!< (@ 0x00000000) Control register0                                          */
    
    struct {
      __IOM uint32_t EN         : 1;            /*!< [0..0] desc EN                                                            */
      __IOM uint32_t MODE       : 2;            /*!< [2..1] desc MODE                                                          */
      __IM  uint32_t            : 1;
      __IOM uint32_t INP1EN     : 1;            /*!< [4..4] desc PCH1EN                                                        */
      __IOM uint32_t INP2EN     : 1;            /*!< [5..5] desc PCH2EN                                                        */
      __IOM uint32_t INP3EN     : 1;            /*!< [6..6] desc PCH3EN                                                        */
      __IOM uint32_t INP4EN     : 1;            /*!< [7..7] desc PCH4EN                                                        */
      __IOM uint32_t INN1EN     : 1;            /*!< [8..8] desc NCH1EN                                                        */
      __IOM uint32_t INN2EN     : 1;            /*!< [9..9] desc NCH2EN                                                        */
      __IOM uint32_t AMP       : 3;            /*!< [12..10] desc GAIN                                                        */
      __IOM uint32_t BIAS       : 3;            /*!< [15..13] desc BIAS                                                        */
    } CR_f;
  } ;
  
  union {
    __IOM uint32_t CAL;                         /*!< (@ 0x00000004) Control register1                                          */
    
    struct {
      __IOM uint32_t CALEN      : 1;            /*!< [0..0] desc AZEN                                                          */
      __IOM uint32_t CALMODE    : 1;            /*!< [1..1] desc MODE                                                          */
      __IOM uint32_t START      : 1;            /*!< [2..2] desc START                                                         */
      __IOM uint32_t SOFTTRIG   : 1;            /*!< [3..3] desc SOFTTRIG                                                      */
      __IOM uint32_t CALPERIOD  : 4;            /*!< [7..4] desc PERIOD                                                        */
      __IOM uint32_t ADCSTART   : 1;            /*!< desc ADCSTART                                                             */
            uint32_t            : 1;
      __IM  uint32_t AZRUN      : 1;            /*!< [10..10] desc AZRUN                                                       */
      __IOM uint32_t CLKDIV     : 3;            /*!< [13..11] desc CLKDIV                                                      */
      __IOM uint32_t ADC1START1 : 1;            /*!< [14..14] desc ADC1START1                                                  */
      __IOM uint32_t ADC2START1 : 1;            /*!< [15..15] desc ADC2START1                                                  */
      __IOM uint32_t ATIM1TRGO  : 1;            /*!< [16..16] desc ATIM1TRGO                                                   */
      __IOM uint32_t ATIM1OC4   : 1;          /*!< [17..17] desc ATIM1OC4REFC                                                */
      __IOM uint32_t ATIM1OC5   : 1;          /*!< [18..18] desc ATIM1OC5REFC                                                */
      __IOM uint32_t ATIM1OC6   : 1;          /*!< [19..19] desc ATIM1OC6REFC                                                */
      __IOM uint32_t GTIM1TRGO  : 1;            /*!< [20..20] desc GTIM1TRGO                                                   */
      __IOM uint32_t GTIM1OC1   : 1;          /*!< [21..21] desc GTIM1OC1REFC                                                */
      __IOM uint32_t GTIM1OC2   : 1;          /*!< [22..22] desc GTIM1OC2REFC                                                */
      __IOM uint32_t GTIM2TRGO  : 1;            /*!< [23..23] desc GTIM2TRGO                                                   */
      __IOM uint32_t GTIM2OC1   : 1;          /*!< [24..24] desc GTIM2OC1REFC                                                */
      __IOM uint32_t GTIM2OC2   : 1;          /*!< [25..25] desc GTIM2OC2REFC                                                */
      __IOM uint32_t GTIM3TRGO  : 1;            /*!< [26..26] desc GTIM3TRGO                                                   */
      __IOM uint32_t GTIM3OC1   : 1;          /*!< [27..27] desc GTIM3OC1REFC                                                */
      __IOM uint32_t GTIM3OC2   : 1;          /*!< [28..28] desc GTIM3OC2REFC                                                */
      __IOM uint32_t GTIM4TRGO  : 1;            /*!< [29..29] desc GTIM4TRGO                                                   */
      __IOM uint32_t GTIM4OC1   : 1;          /*!< [30..30] desc GTIM4OC1REFC                                                */
      __IOM uint32_t GTIM4OC2   : 1;          /*!< [31..31] desc GTIM4OC2REFC                                                */
    } CAL_f;
  } ;
} OPA_TypeDef;                                     /*!< Size = 8 (0x8)                                                            */


/* =========================================================================================================================== */
/* ================                                            RAM                                            ================ */
/* =========================================================================================================================== */


/**
  * @brief desc RAM (RAM)
  */

typedef struct {                                /*!< (@ 0x40022400) RAM Structure                                              */
  
  union {
    __IOM uint32_t IER;                         /*!< (@ 0x00000000) Interrupt enable register                                  */
    
    struct {
      __IOM uint32_t PARITY     : 1;            /*!< [0..0] desc PARITY                                                        */
    } IER_f;
  } ;
  
  union {
    __IM  uint32_t ADDR;                        /*!< (@ 0x00000004) Error address register                                     */
    
    struct {
      __IM  uint32_t ADDR       : 32;           /*!< [31..0] desc ADDR                                                         */
    } ADDR_f;
  } ;
  
  union {
    __IM  uint32_t ISR;                         /*!< (@ 0x00000008) Interrupt status register                                  */
    
    struct {
      __IM  uint32_t PARITY     : 1;            /*!< [0..0] desc PARITY                                                        */
    } ISR_f;
  } ;
  
  union {
    __IOM uint32_t ICR;                         /*!< (@ 0x0000000C) Interrupt flag clear register                              */
    
    struct {
      __IOM uint32_t PARITY     : 1;            /*!< [0..0] desc PARITY                                                        */
    } ICR_f;
  } ;
} RAM_TypeDef;                                     /*!< Size = 16 (0x10)                                                          */



/* =========================================================================================================================== */
/* ================                                            RTC                                            ================ */
/* =========================================================================================================================== */


/**
  * @brief desc RTC (RTC)
  */

typedef struct {                                /*!< (@ 0x40004400) RTC Structure                                              */
  
  union {
    __OM  uint32_t KEY;                         /*!< (@ 0x00000000) desc KEY                                                   */
    
    struct {
      __OM  uint32_t KEY        : 8;            /*!< [7..0] desc KEY                                                           */
    } KEY_f;
  } ;
  
  union {
    __IOM uint32_t CR0;                         /*!< (@ 0x00000004) desc CR0                                                   */
    
    struct {
      __IOM uint32_t INTERVAL   : 3;            /*!< [2..0] desc INTERVAL                                                      */
      __IOM uint32_t H24        : 1;            /*!< [3..3] desc H24                                                           */
      __IM  uint32_t            : 1;
      __IOM uint32_t RTC1HZ     : 2;            /*!< [6..5] desc RTC1HZ                                                        */
      __IOM uint32_t START      : 1;            /*!< [7..7] desc START                                                         */
    } CR0_f;
  } ;
  
  union {
    __IOM uint32_t CR1;                         /*!< (@ 0x00000008) desc CR1                                                   */
    
    struct {
      __IM  uint32_t            : 2;
      __IM  uint32_t WAIT       : 1;            /*!< [2..2] desc WAIT                                                          */
      __IM  uint32_t            : 5;
      __IOM uint32_t SOURCE     : 3;            /*!< [10..8] desc SOURCE                                                       */
    } CR1_f;
  } ;
  
  union {
    __IOM uint32_t CR2;                         /*!< (@ 0x0000000C) desc CR2                                                   */
    
    struct {
      __IOM uint32_t AWTPRS     : 2;            /*!< [1..0] desc AWTPRS                                                        */
      __IOM uint32_t AWTSRC     : 1;            /*!< [2..2] desc AWTSRC                                                        */
      __IOM uint32_t TAMPEDGE   : 1;            /*!< [3..3] desc TAMPEDGE                                                      */
      __IOM uint32_t RTCOUT     : 2;            /*!< [5..4] desc RTCOUT                                                        */
      __IOM uint32_t TAMPEN     : 1;            /*!< [6..6] desc TAMPEN                                                        */
      __IOM uint32_t AWTEN      : 1;            /*!< [7..7] desc AWTEN                                                         */
      __IM  uint32_t            : 1;
      __IOM uint32_t ALARMAEN   : 1;            /*!< [9..9] desc ALARMAEN                                                      */
      __IOM uint32_t ALARMBEN   : 1;            /*!< [10..10] desc ALARMBEN                                                    */
    } CR2_f;
  } ;
  
  union {
    __IOM uint32_t COMPCFR1;                    /*!< (@ 0x00000010) desc COMPCFR1                                              */
    
    struct {
      __IOM uint32_t COMP       : 12;           /*!< [11..0] desc COMP                                                         */
      __IOM uint32_t PERIOD     : 2;            /*!< [13..12] desc PERIOD                                                      */
      __IOM uint32_t SIGN       : 1;            /*!< [14..14] desc SIGN                                                        */
      __IOM uint32_t EN         : 1;            /*!< [15..15] desc EN                                                          */
    } COMPCFR1_f;
  } ;
  
  union {
    __IOM uint32_t DATE;                        /*!< (@ 0x00000014) desc DATE                                                  */
    
    struct {
      __IOM uint32_t DAY        : 6;            /*!< [7..0] desc DAY                                                           */
            uint32_t            : 2;
      __IOM uint32_t MONTH      : 5;            /*!< [15..8] desc MONTH                                                        */
            uint32_t            : 3;
      __IOM uint32_t YEAR       : 8;            /*!< [23..16] desc YEAR                                                        */
      __IOM uint32_t WEEK       : 3;            /*!< [26..24] desc WEEK                                                        */
    } DATE_f;
  } ;
  
  union {
    __IOM uint32_t TIME;                        /*!< (@ 0x00000018) desc TIME                                                  */
    
    struct {
      __IOM uint32_t SECOND     : 7;            /*!< [6..0] desc SECOND                                                        */
      __IM  uint32_t            : 1;
      __IOM uint32_t MINUTE     : 7;            /*!< [14..8] desc MINUTE                                                       */
      __IM  uint32_t            : 1;
      __IOM uint32_t HOUR       : 6;            /*!< [21..16] desc HOUR                                                        */
    } TIME_f;
  } ;
  
  union {
    __IOM uint32_t ALARMA;                      /*!< (@ 0x0000001C) desc ALARMA                                                */
    
    struct {
      __IOM uint32_t SECOND     : 7;            /*!< [6..0] desc SECOND                                                        */
      __IOM uint32_t SECONDEN   : 1;            /*!< [7..7] desc SECONDEN                                                      */
      __IOM uint32_t MINUTE     : 7;            /*!< [14..8] desc MINUTE                                                       */
      __IOM uint32_t MINUTEEN   : 1;            /*!< [15..15] desc MINUTEEN                                                    */
      __IOM uint32_t HOUR       : 6;            /*!< [21..16] desc HOUR                                                        */
      __IM  uint32_t            : 1;
      __IOM uint32_t HOUREN     : 1;            /*!< [23..23] desc HOUREN                                                      */
      __IOM uint32_t WEEKMASK   : 7;            /*!< [30..24] desc WEEKMASK                                                    */
    } ALARMA_f;
  } ;
  
  union {
    __IOM uint32_t ALARMB;                      /*!< (@ 0x00000020) desc ALARMB                                                */
    
    struct {
      __IOM uint32_t SECOND     : 7;            /*!< [6..0] desc SECOND                                                        */
      __IOM uint32_t SECONDEN   : 1;            /*!< [7..7] desc SECONDEN                                                      */
      __IOM uint32_t MINUTE     : 7;            /*!< [14..8] desc MINUTE                                                       */
      __IOM uint32_t MINUTEEN   : 1;            /*!< [15..15] desc MINUTEEN                                                    */
      __IOM uint32_t HOUR       : 6;            /*!< [21..16] desc HOUR                                                        */
      __IM  uint32_t            : 1;
      __IOM uint32_t HOUREN     : 1;            /*!< [23..23] desc HOUREN                                                      */
      __IOM uint32_t WEEKMASK   : 7;            /*!< [30..24] desc WEEKMASK                                                    */
    } ALARMB_f;
  } ;
  
  union {
    __IM  uint32_t TAMPDATE;                    /*!< (@ 0x00000024) desc TAMPDATE                                              */
    
    struct {
      __IM  uint32_t DAY        : 6;            /*!< [5..0] desc DAY                                                           */
      __IM  uint32_t            : 2;
      __IM  uint32_t MONTH      : 5;            /*!< [12..8] desc MONTH                                                        */
      __IM  uint32_t WEEK       : 3;            /*!< [15..13] desc WEEK                                                        */
    } TAMPDATE_f;
  } ;
  
  union {
    __IM  uint32_t TAMPTIME;                    /*!< (@ 0x00000028) desc TAMPTIME                                              */
    
    struct {
      __IM  uint32_t SECOND     : 7;            /*!< [6..0] desc SECOND                                                        */
      __IM  uint32_t            : 1;
      __IM  uint32_t MINUTE     : 7;            /*!< [14..8] desc MINUTE                                                       */
      __IM  uint32_t            : 1;
      __IM  uint32_t HOUR       : 6;            /*!< [21..16] desc HOUR                                                        */
    } TAMPTIME_f;
  } ;
  
  union {
    __IOM uint32_t AWTARR;                      /*!< (@ 0x0000002C) desc AWTARR                                                */
    
    struct {
      __IOM uint32_t ARR        : 16;           /*!< [15..0] desc ARR                                                          */
    } AWTARR_f;
  } ;
  
  union {
    __IOM uint32_t IER;                         /*!< (@ 0x00000030) desc IER                                                   */
    
    struct {
      __IOM uint32_t ALARMA     : 1;            /*!< [0..0] desc ALARMA                                                        */
      __IOM uint32_t ALARMB     : 1;            /*!< [1..1] desc ALARMB                                                        */
      __IOM uint32_t AWTIMER    : 1;            /*!< [2..2] desc AWTIMER                                                       */
      __IOM uint32_t TAMP       : 1;            /*!< [3..3] desc TAMP                                                          */
      __IOM uint32_t TAMPOV     : 1;            /*!< [4..4] desc TAMPOV                                                        */
      __IM  uint32_t            : 1;
      __IOM uint32_t INTERVAL   : 1;            /*!< [6..6] desc INTERVAL                                                      */
    } IER_f;
  } ;
  
  union {
    __IM  uint32_t ISR;                         /*!< (@ 0x00000034) desc ISR                                                   */
    
    struct {
      __IM  uint32_t ALARMA     : 1;            /*!< [0..0] desc ALARMA                                                        */
      __IM  uint32_t ALARMB     : 1;            /*!< [1..1] desc ALARMB                                                        */
      __IM  uint32_t AWTIMER    : 1;            /*!< [2..2] desc AWTIMER                                                       */
      __IM  uint32_t TAMP       : 1;            /*!< [3..3] desc TAMP                                                          */
      __IM  uint32_t TAMPOV     : 1;            /*!< [4..4] desc TAMPOV                                                        */
      __IM  uint32_t            : 1;
      __IM  uint32_t INTERVAL   : 1;            /*!< [6..6] desc INTERVAL                                                      */
    } ISR_f;
  } ;
  
  union {
    __IOM uint32_t ICR;                         /*!< (@ 0x00000038) desc ICR                                                   */
    
    struct {
      __IOM uint32_t ALARMA     : 1;            /*!< [0..0] desc ALARMA                                                        */
      __IOM uint32_t ALARMB     : 1;            /*!< [1..1] desc ALARMB                                                        */
      __IOM uint32_t AWTIMER    : 1;            /*!< [2..2] desc AWTIMER                                                       */
      __IOM uint32_t TAMP       : 1;            /*!< [3..3] desc TAMP                                                          */
      __IOM uint32_t TAMPOV     : 1;            /*!< [4..4] desc TAMPOV                                                        */
      __IM  uint32_t            : 1;
      __IOM uint32_t INTERVAL   : 1;            /*!< [6..6] desc INTERVAL                                                      */
    } ICR_f;
  } ;
  
  union {
    __IM  uint32_t AWTCNT;                      /*!< (@ 0x0000003C) desc AWTCNT                                                */
    
    struct {
      __IM  uint32_t CNT        : 16;           /*!< [15..0] desc CNT                                                          */
    } AWTCNT_f;
  } ;
  
  union {
    __IOM uint32_t PSC;                         /*!< (@ 0x00000040) desc PSC                                                   */
    
    struct {
      __IOM uint32_t PSC2       : 20;           /*!< [19..0] desc PSC2                                                         */
      __IOM uint32_t PSC1       : 8;            /*!< [27..20] desc PSC1                                                        */
    } PSC_f;
  } ;
  
  union {
    __IM  uint32_t SSCNT;                       /*!< (@ 0x00000044) desc SSCNT                                                 */
    
    struct {
      __IM  uint32_t SSCNT0     : 20;           /*!< [19..0] desc SSCNT0                                                       */
      __IM  uint32_t SSCNT1     : 1;            /*!< [20..20] desc SSCNT1                                                      */
    } SSCNT_f;
  } ;
} RTC_TypeDef;                                  /*!< Size = 92 (0x5c)                                                          */



/* =========================================================================================================================== */
/* ================                                           SPI1                                            ================ */
/* =========================================================================================================================== */


/**
  * @brief desc SPI1 (SPI1)
  */

typedef struct {                                /*!< (@ 0x40000800) SPI1 Structure                                             */
  
  union {
    __IOM uint32_t CR1;                         /*!< (@ 0x00000000) Control register1                                          */
    
    struct {
      __IOM uint32_t MSTR       : 1;            /*!< [0..0] desc MSTR                                                          */
      __IOM uint32_t SSM        : 1;            /*!< [1..1] desc SSM                                                           */
      __IOM uint32_t CPHA       : 1;            /*!< [2..2] desc CPHA                                                          */
      __IOM uint32_t CPOL       : 1;            /*!< [3..3] desc CPOL                                                          */
      __IM  uint32_t            : 3;
      __IOM uint32_t LSBF       : 1;            /*!< [7..7] desc LSBF                                                          */
      __IOM uint32_t WIDTH      : 4;            /*!< [11..8] desc WIDTH                                                        */
      __IOM uint32_t GAP        : 4;            /*!< [15..12] desc GAP                                                         */
      __IOM uint32_t MODE       : 2;            /*!< [17..16] desc MODE                                                        */
      __IOM uint32_t FLTEN      : 1;            /*!< [18..18] desc FLTEN                                                       */
      __IOM uint32_t MISOHD     : 1;            /*!< [19..19] desc MISOHD                                                      */
      __IOM uint32_t SMP        : 1;            /*!< [20..20] desc SMP                                                         */
      __IM  uint32_t            : 3;
      __IOM uint32_t BR         : 7;            /*!< [30..24] desc BR                                                          */
    } CR1_f;
  } ;
  
  union {
    __IOM uint32_t CR2;                         /*!< (@ 0x00000004) Control register2                                          */
    
    struct {
      __IOM uint32_t EN         : 1;            /*!< [0..0] desc EN                                                            */
      __IOM uint32_t DMARX      : 1;            /*!< [1..1] desc DMARX                                                         */
      __IOM uint32_t DMATX      : 1;            /*!< [2..2] desc DMATX                                                         */
    } CR2_f;
  } ;
  
  union {
    __IOM uint32_t CR3;                         /*!< (@ 0x00000008) desc CR3                                                   */
    
    struct {
      __IOM uint32_t HDOE       : 1;            /*!< [0..0] desc HDOE                                                          */
    } CR3_f;
  } ;
  
  union {
    __IOM uint32_t SSI;                         /*!< (@ 0x0000000C) Slave slect register                                       */
    
    struct {
      __IOM uint32_t SSI        : 1;            /*!< [0..0] desc SSI                                                           */
    } SSI_f;
  } ;
  
  union {
    __IOM uint32_t IER;                         /*!< (@ 0x00000010) Interrupt enable register                                  */
    
    struct {
      __IOM uint32_t TXE        : 1;            /*!< [0..0] desc TXE                                                           */
      __IOM uint32_t RXNE       : 1;            /*!< [1..1] desc RXNE                                                          */
      __IOM uint32_t SSF        : 1;            /*!< [2..2] desc SSF                                                           */
      __IOM uint32_t SSR        : 1;            /*!< [3..3] desc SSR                                                           */
      __IOM uint32_t UD         : 1;            /*!< [4..4] desc UD                                                            */
      __IOM uint32_t OV         : 1;            /*!< [5..5] desc OV                                                            */
      __IOM uint32_t SSERR      : 1;            /*!< [6..6] desc SSERR                                                         */
      __IOM uint32_t MODF       : 1;            /*!< [7..7] desc MODF                                                          */
    } IER_f;
  } ;
  
  union {
    __IM  uint32_t ISR;                         /*!< (@ 0x00000014) Interrupt status register                                  */
    
    struct {
      __IM  uint32_t TXE        : 1;            /*!< [0..0] desc TXE                                                           */
      __IM  uint32_t RXNE       : 1;            /*!< [1..1] desc RXNE                                                          */
      __IM  uint32_t SSF        : 1;            /*!< [2..2] desc SSF                                                           */
      __IM  uint32_t SSR        : 1;            /*!< [3..3] desc SSR                                                           */
      __IM  uint32_t UD         : 1;            /*!< [4..4] desc UD                                                            */
      __IM  uint32_t OV         : 1;            /*!< [5..5] desc OV                                                            */
      __IM  uint32_t SSERR      : 1;            /*!< [6..6] desc SSERR                                                         */
      __IM  uint32_t MODF       : 1;            /*!< [7..7] desc MODF                                                          */
      __IM  uint32_t BUSY       : 1;            /*!< [8..8] desc BUSY                                                          */
      __IM  uint32_t SSLVL      : 1;            /*!< [9..9] desc SSLVL                                                         */
    } ISR_f;
  } ;
  
  union {
    __IOM uint32_t ICR;                         /*!< (@ 0x00000018) Interrupt flag clear register                              */
    
    struct {
      __IOM uint32_t FLUSH      : 1;            /*!< [0..0] desc FLUSH                                                         */
      __IOM uint32_t RXNE       : 1;            /*!< [1..1] desc RXNE                                                          */
      __IOM uint32_t SSF        : 1;            /*!< [2..2] desc SSF                                                           */
      __IOM uint32_t SSR        : 1;            /*!< [3..3] desc SSR                                                           */
      __IOM uint32_t UD         : 1;            /*!< [4..4] desc UD                                                            */
      __IOM uint32_t OV         : 1;            /*!< [5..5] desc OV                                                            */
      __IOM uint32_t SSERR      : 1;            /*!< [6..6] desc SSERR                                                         */
      __IOM uint32_t MODF       : 1;            /*!< [7..7] desc MODF                                                          */
    } ICR_f;
  } ;
  
  union {
    __IOM uint32_t DR;                          /*!< (@ 0x0000001C) Data register                                              */
    
    struct {
      __IOM uint32_t DR         : 16;           /*!< [15..0] desc DR                                                           */
    } DR_f;
  } ;
} SPI_TypeDef;                                     /*!< Size = 32 (0x20)                                                          */



/* =========================================================================================================================== */
/* ================                                          SYSCTRL                                          ================ */
/* =========================================================================================================================== */


/**
  * @brief System Ctrl (SYSCTRL)
  */

typedef struct {                                /*!< (@ 0x40004000) SYSCTRL Structure                                          */
  
  union {
    __IOM uint32_t CR0;                         /*!< (@ 0x00000000) Control Reg0                                               */
    
    struct {
      __IOM uint32_t SYSCLK     : 3;            /*!< [2..0] desc SYSCLK                                                        */
      __IOM uint32_t PCLKPRS    : 2;            /*!< [4..3] desc PCLKPRS                                                       */
      __IOM uint32_t HCLKPRS    : 3;            /*!< [7..5] desc HCLKPRS                                                       */
      __IM  uint32_t            : 8;
      __OM  uint32_t KEY        : 16;           /*!< [31..16] desc KEY                                                         */
    } CR0_f;
  } ;
  
  union {
    __IOM uint32_t CR1;                         /*!< (@ 0x00000004) Control Reg1                                               */
    
    struct {
      __IOM uint32_t HSIEN      : 1;            /*!< [0..0] desc HSIEN                                                         */
      __IOM uint32_t HSEEN      : 1;            /*!< [1..1] desc HSEEN                                                         */
      __IOM uint32_t PLLEN      : 1;            /*!< [2..2] desc PLLEN                                                         */
      __IOM uint32_t LSIEN      : 1;            /*!< [3..3] desc LSIEN                                                         */
      __IOM uint32_t LSEEN      : 1;            /*!< [4..4] desc LSEEN                                                         */
      __IOM uint32_t LSELOCK    : 1;            /*!< [5..5] desc LSELOCK                                                       */
      __IOM uint32_t LSECCS     : 1;            /*!< [6..6] desc LSECCS                                                        */
      __IOM uint32_t HSECCS     : 1;            /*!< [7..7] desc HSECCS                                                        */
      __IOM uint32_t CLKCCS     : 1;            /*!< [8..8] desc CLKCCS                                                        */
      __IM  uint32_t            : 7;
      __OM  uint32_t KEY        : 16;           /*!< [31..16] desc KEY                                                         */
    } CR1_f;
  } ;
  
  union {
    __IOM uint32_t CR2;                         /*!< (@ 0x00000008) Control Reg2                                               */
    
    struct {
      __IM  uint32_t            : 1;
      __IOM uint32_t SWDIO      : 1;            /*!< [1..1] desc SWDIO                                                         */
      __IOM uint32_t LOCKUP     : 1;            /*!< [2..2] desc LOCKUP                                                        */
      __IOM uint32_t WAKEUPCLK  : 1;            /*!< [3..3] desc WAKEUPCLK                                                     */
      __IOM uint32_t FLASHWAIT  : 3;            /*!< [6..4] desc FLASHWAIT                                                     */
      __IM  uint32_t            : 3;
      __IOM uint32_t HSEBRKEN   : 1;            /*!< [10..10] desc HSEBRKEN                                                    */
      __IOM uint32_t LSEBRKEN   : 1;            /*!< [11..11] desc LSEBRKEN                                                    */
      __IOM uint32_t CLLBRKEN   : 1;            /*!< [12..12] desc CLLBRKEN                                                    */
      __IOM uint32_t DSBRKEN    : 1;            /*!< [13..13] desc DSBRKEN                                                     */
      __IOM uint32_t LVDBRKEN   : 1;            /*!< [14..14] desc LVDBRKEN                                                    */
      __IOM uint32_t RAMBRKEN   : 1;            /*!< [15..15] desc RAMBRKEN                                                    */
      __OM  uint32_t KEY        : 16;           /*!< [31..16] desc KEY                                                         */
    } CR2_f;
  } ;
  
  union {
    __IOM uint32_t IER;                         /*!< (@ 0x0000000C) Interupt Enable Reg                                        */
    
    struct {
      __IOM uint32_t HSIRDY     : 1;            /*!< [0..0] desc HSIRDY                                                        */
      __IOM uint32_t HSERDY     : 1;            /*!< [1..1] desc HSERDY                                                        */
      __IOM uint32_t PLLRDY     : 1;            /*!< [2..2] desc PLLRDY                                                        */
      __IOM uint32_t LSIRDY     : 1;            /*!< [3..3] desc LSIRDY                                                        */
      __IOM uint32_t LSERDY     : 1;            /*!< [4..4] desc LSERDY                                                        */
      __IOM uint32_t LSEFAIL    : 1;            /*!< [5..5] desc LSEFAIL                                                       */
      __IOM uint32_t HSEFAIL    : 1;            /*!< [6..6] desc HSEFAIL                                                       */
      __IOM uint32_t LSEFAULT   : 1;            /*!< [7..7] desc LSEFAULT                                                      */
      __IOM uint32_t HSEFAULT   : 1;            /*!< [8..8] desc HSEFAULT                                                      */
      __IM  uint32_t            : 7;
      __OM  uint32_t KEY        : 16;           /*!< [31..16] desc KEY                                                         */
    } IER_f;
  } ;
  
  union {
    __IM  uint32_t ISR;                         /*!< (@ 0x00000010) Interupt Status Reg                                        */
    
    struct {
      __IM  uint32_t HSIRDY     : 1;            /*!< [0..0] desc HSIRDY                                                        */
      __IM  uint32_t HSERDY     : 1;            /*!< [1..1] desc HSERDY                                                        */
      __IM  uint32_t PLLRDY     : 1;            /*!< [2..2] desc PLLRDY                                                        */
      __IM  uint32_t LSIRDY     : 1;            /*!< [3..3] desc LSIRDY                                                        */
      __IM  uint32_t LSERDY     : 1;            /*!< [4..4] desc LSERDY                                                        */
      __IM  uint32_t LSEFAIL    : 1;            /*!< [5..5] desc LSEFAIL                                                       */
      __IM  uint32_t HSEFAIL    : 1;            /*!< [6..6] desc HSEFAIL                                                       */
      __IM  uint32_t LSEFAULT   : 1;            /*!< [7..7] desc LSEFAULT                                                      */
      __IM  uint32_t HSEFAULT   : 1;            /*!< [8..8] desc HSEFAULT                                                      */
      __IM  uint32_t            : 2;
      __IM  uint32_t HSISTABLE  : 1;            /*!< [11..11] desc HSISTABLE                                                   */
      __IM  uint32_t HSESTABLE  : 1;            /*!< [12..12] desc HSESTABLE                                                   */
      __IM  uint32_t PLLSTABLE  : 1;            /*!< [13..13] desc PLLSTABLE                                                   */
      __IM  uint32_t LSISTABLE  : 1;            /*!< [14..14] desc LSISTABLE                                                   */
      __IM  uint32_t LSESTABLE  : 1;            /*!< [15..15] desc LSESTABLE                                                   */
    } ISR_f;
  } ;
  
  union {
    __IOM uint32_t ICR;                         /*!< (@ 0x00000014) Interupt Clear Reg                                         */
    
    struct {
      __IOM uint32_t HSIRDY     : 1;            /*!< [0..0] desc HSIRDY                                                        */
      __IOM uint32_t HSERDY     : 1;            /*!< [1..1] desc HSERDY                                                        */
      __IOM uint32_t PLLRDY     : 1;            /*!< [2..2] desc PLLRDY                                                        */
      __IOM uint32_t LSIRDY     : 1;            /*!< [3..3] desc LSIRDY                                                        */
      __IOM uint32_t LSERDY     : 1;            /*!< [4..4] desc LSERDY                                                        */
      __IOM uint32_t LSEFAIL    : 1;            /*!< [5..5] desc LSEFAIL                                                       */
      __IOM uint32_t HSEFAIL    : 1;            /*!< [6..6] desc HSEFAIL                                                       */
      __IOM uint32_t LSEFAULT   : 1;            /*!< [7..7] desc LSEFAULT                                                      */
      __IOM uint32_t HSEFAULT   : 1;            /*!< [8..8] desc HSEFAULT                                                      */
    } ICR_f;
  } ;
  
  union {
    __IOM uint32_t HSI;                         /*!< (@ 0x00000018) HSI Control Reg                                            */
    
    struct {
      __IOM uint32_t TRIM       : 11;           /*!< [10..0] desc TRIM                                                         */
      __IOM uint32_t DIV        : 4;            /*!< [14..11] desc DIV                                                         */
      __IM  uint32_t STABLE     : 1;            /*!< [15..15] desc STABLE                                                      */
    } HSI_f;
  } ;
  
  union {
    __IOM uint32_t HSE;                         /*!< (@ 0x0000001C) HEX Control Reg                                            */
    
    struct {
      __IOM uint32_t DRIVER     : 4;            /*!< [3..0] desc DRIVER                                                        */
      __IOM uint32_t WAITCYCLE  : 2;            /*!< [5..4] desc WAITCYCLE                                                     */
      __IOM uint32_t MODE       : 1;            /*!< [6..6] desc MODE                                                          */
      __IOM uint32_t HEXENPOL   : 1;            /*!< [7..7] desc HEXENPOL                                                      */
      __IOM uint32_t DETCNT     : 11;           /*!< [18..8] desc DETCNT                                                       */
      __IM  uint32_t STABLE     : 1;            /*!< [19..19] desc STABLE                                                      */
      __IOM uint32_t PDRIVER    : 4;            /*!< [23..20] desc PDRIVER                                                     */
      __IOM uint32_t DIGFLT     : 1;            /*!< [24..24] desc DIGFLT                                                      */
    } HSE_f;
  } ;
  
  union {
    __IOM uint32_t LSI;                         /*!< (@ 0x00000020) LSI Control Reg                                            */
    
    struct {
      __IOM uint32_t TRIM       : 9;            /*!< [8..0] desc TRIM                                                          */
      __IM  uint32_t            : 1;
      __IOM uint32_t WAITCYCLE  : 2;            /*!< [11..10] desc WAITCYCLE                                                   */
      __IM  uint32_t            : 3;
      __IM  uint32_t STABLE     : 1;            /*!< [15..15] desc STABLE                                                      */
    } LSI_f;
  } ;
  
  union {
    __IOM uint32_t LSE;                         /*!< (@ 0x00000024) LSE Control Reg                                            */
    
    struct {
      __IOM uint32_t DRIVER     : 4;            /*!< [3..0] desc DRIVER                                                        */
      __IOM uint32_t WAITCYCLE  : 2;            /*!< [5..4] desc WAITCYCLE                                                     */
      __IOM uint32_t MODE       : 1;            /*!< [6..6] desc MODE                                                          */
      __IM  uint32_t            : 1;
      __IOM uint32_t PDRIVER    : 4;            /*!< [11..8] desc PDRIVER                                                      */
      __IM  uint32_t            : 5;
      __IOM uint32_t PINLOCK    : 1;            /*!< [17..17] desc PINLOCK                                                     */
      __IM  uint32_t STABLE     : 1;            /*!< [18..18] desc STABLE                                                      */
    } LSE_f;
  } ;
  
  union {
    __IOM uint32_t PLL;                         /*!< (@ 0x00000028) PLL Control Reg                                            */
    
    struct {
      __IOM uint32_t SOURCE     : 1;            /*!< [0..0] desc SOURCE                                                        */
      __IOM uint32_t DIV        : 4;            /*!< [4..1] desc DIV                                                           */
      __IOM uint32_t WAITCYCLE  : 3;            /*!< [7..5] desc WAITCYCLE                                                     */
      __IOM uint32_t MUL        : 8;            /*!< [15..8] desc MUL                                                          */
      __IM  uint32_t STABLE     : 1;            /*!< [16..16] desc STABLE                                                      */
    } PLL_f;
  } ;
  
  union {
    __IOM uint32_t DEBUG;                       /*!< (@ 0x0000002C) Debug Control Reg                                          */
    
    struct {
      __IOM uint32_t ATIM       : 1;            /*!< [0..0] desc ATIM                                                          */
      __IOM uint32_t GTIM1      : 1;            /*!< [1..1] desc GTIM1                                                         */
      __IOM uint32_t GTIM2      : 1;            /*!< [2..2] desc GTIM2                                                         */
      __IOM uint32_t GTIM3      : 1;            /*!< [3..3] desc GTIM3                                                         */
      __IOM uint32_t GTIM4      : 1;            /*!< [4..4] desc GTIM4                                                         */
      __IOM uint32_t BTIM123    : 1;            /*!< [5..5] desc BTIM123                                                       */
      __IOM uint32_t LPTIM      : 1;            /*!< [6..6] desc LPTIM                                                         */
      __IM  uint32_t            : 1;
      __IOM uint32_t RTC        : 1;            /*!< [8..8] desc RTC                                                           */
      __IOM uint32_t IWDT       : 1;            /*!< [9..9] desc IWDT                                                          */
      __IOM uint32_t WWDT       : 1;            /*!< [10..10] desc WWDT                                                        */
      __IOM uint32_t HALLTIM    : 1;            /*!< [11..11] desc HALLTIM                                                     */
    } DEBUG_f;
  } ;
  
  union {
    __IOM uint32_t AHBEN;                       /*!< (@ 0x00000030) AHB Clock Control Reg                                      */
    
    struct {
      __IOM uint32_t DMA        : 1;            /*!< [0..0] desc DMA                                                           */
      __IOM uint32_t FLASH      : 1;            /*!< [1..1] desc FLASH                                                         */
      __IOM uint32_t CRC        : 1;            /*!< [2..2] desc CRC                                                           */
      __IOM uint32_t EAU        : 1;            /*!< [3..3] desc EAU                                                           */
      __IOM uint32_t GPIOA      : 1;            /*!< [4..4] desc GPIOA                                                         */
      __IOM uint32_t GPIOB      : 1;            /*!< [5..5] desc GPIOB                                                         */
      __IOM uint32_t GPIOC      : 1;            /*!< [6..6] desc GPIOC                                                         */
      __IOM uint32_t GPIOF      : 1;            /*!< [7..7] desc GPIOF                                                         */
      __IOM uint32_t CORDIC     : 1;            /*!< [8..8] desc CORDIC                                                        */
      __IM  uint32_t            : 7;
      __OM  uint32_t KEY        : 16;           /*!< [31..16] desc KEY                                                         */
    } AHBEN_f;
  } ;
  
  union {
    __IOM uint32_t APBEN2;                      /*!< (@ 0x00000034) APB Clock Control Reg2                                     */
    
    struct {
      __IM  uint32_t            : 1;
      __IOM uint32_t RTC        : 1;            /*!< [1..1] desc RTC                                                           */
      __IOM uint32_t BTIM123    : 1;            /*!< [2..2] desc BTIM123                                                       */
      __IM  uint32_t            : 1;
      __IOM uint32_t IWDT       : 1;            /*!< [4..4] desc IWDT                                                          */
      __IOM uint32_t WWDT       : 1;            /*!< [5..5] desc WWDT                                                          */
      __IOM uint32_t I2C1       : 1;            /*!< [6..6] desc I2C1                                                          */
      __IOM uint32_t LPTIM      : 1;            /*!< [7..7] desc LPTIM                                                         */
      __IM  uint32_t            : 1;
      __IOM uint32_t OPA        : 1;            /*!< [9..9] desc OPA                                                           */
      __IOM uint32_t DAC        : 1;            /*!< [10..10] desc DAC                                                         */
      __IOM uint32_t I2C2       : 1;            /*!< [11..11] desc I2C2                                                        */
      __IOM uint32_t HALLTIM    : 1;            /*!< [12..12] desc HALLTIM                                                     */
      __IM  uint32_t            : 3;
      __OM  uint32_t KEY        : 16;           /*!< [31..16] desc KEY                                                         */
    } APBEN2_f;
  } ;
  
  union {
    __IOM uint32_t APBEN1;                      /*!< (@ 0x00000038) APB Clock Control Reg1                                     */
    
    struct {
      __IOM uint32_t ADC        : 1;            /*!< [0..0] desc ADC                                                           */
      __IOM uint32_t VC         : 1;            /*!< [1..1] desc VC                                                            */
      __IOM uint32_t SPI1       : 1;            /*!< [2..2] desc SPI1                                                          */
      __IOM uint32_t UART1      : 1;            /*!< [3..3] desc UART1                                                         */
      __IOM uint32_t UART2      : 1;            /*!< [4..4] desc UART2                                                         */
      __IOM uint32_t ATIM       : 1;            /*!< [5..5] desc ATIM                                                          */
      __IOM uint32_t GTIM1      : 1;            /*!< [6..6] desc GTIM1                                                         */
      __IOM uint32_t GTIM2      : 1;            /*!< [7..7] desc GTIM2                                                         */
      __IOM uint32_t UART3      : 1;            /*!< [8..8] desc UART3                                                         */
      __IM  uint32_t            : 2;
      __IOM uint32_t GTIM3      : 1;            /*!< [11..11] desc GTIM3                                                       */
      __IOM uint32_t GTIM4      : 1;            /*!< [12..12] desc GTIM4                                                       */
      __IOM uint32_t SPI2       : 1;            /*!< [13..13] desc SPI2                                                        */
      __IOM uint32_t SPI3       : 1;            /*!< [14..14] desc SPI3                                                        */
      __IM  uint32_t            : 1;
      __OM  uint32_t KEY        : 16;           /*!< [31..16] desc KEY                                                         */
    } APBEN1_f;
  } ;
  __IM  uint32_t  RESERVED;
  
  union {
    __IOM uint32_t AHBRST;                      /*!< (@ 0x00000040) AHB Reset Control Reg                                      */
    
    struct {
      __IOM uint32_t DMA        : 1;            /*!< [0..0] desc DMA                                                           */
      __IOM uint32_t FLASH      : 1;            /*!< [1..1] desc FLASH                                                         */
      __IOM uint32_t CRC        : 1;            /*!< [2..2] desc CRC                                                           */
      __IOM uint32_t EAU        : 1;            /*!< [3..3] desc EAU                                                           */
      __IOM uint32_t GPIOA      : 1;            /*!< [4..4] desc GPIOA                                                         */
      __IOM uint32_t GPIOB      : 1;            /*!< [5..5] desc GPIOB                                                         */
      __IOM uint32_t GPIOC      : 1;            /*!< [6..6] desc GPIOC                                                         */
      __IOM uint32_t GPIOF      : 1;            /*!< [7..7] desc GPIOF                                                         */
      __IOM uint32_t CORDIC     : 1;            /*!< [8..8] desc CORDIC                                                        */
    } AHBRST_f;
  } ;
  
  union {
    __IOM uint32_t APBRST2;                     /*!< (@ 0x00000044) APB Reset Control Reg2                                     */
    
    struct {
      __IM  uint32_t            : 1;
      __IOM uint32_t RTC        : 1;            /*!< [1..1] desc RTC                                                           */
      __IOM uint32_t BTIM123    : 1;            /*!< [2..2] desc BTIM123                                                       */
      __IM  uint32_t            : 1;
      __IOM uint32_t IWDT       : 1;            /*!< [4..4] desc IWDT                                                          */
      __IOM uint32_t WWDT       : 1;            /*!< [5..5] desc WWDT                                                          */
      __IOM uint32_t I2C1       : 1;            /*!< [6..6] desc I2C1                                                          */
      __IOM uint32_t LPTIM      : 1;            /*!< [7..7] desc LPTIM                                                         */
      __IM  uint32_t            : 1;
      __IOM uint32_t OPA        : 1;            /*!< [9..9] desc OPA                                                           */
      __IOM uint32_t DAC        : 1;            /*!< [10..10] desc DAC                                                         */
      __IOM uint32_t I2C2       : 1;            /*!< [11..11] desc I2C2                                                        */
      __IOM uint32_t HALLTIM    : 1;            /*!< [12..12] desc HALLTIM                                                     */      
    } APBRST2_f;
  } ;
  
  union {
    __IOM uint32_t APBRST1;                     /*!< (@ 0x00000048) APB Reset Control Reg1                                     */
    
    struct {
      __IOM uint32_t ADC        : 1;            /*!< [0..0] desc ADC                                                           */
      __IOM uint32_t VC         : 1;            /*!< [1..1] desc VC                                                            */
      __IOM uint32_t SPI1       : 1;            /*!< [2..2] desc SPI1                                                          */
      __IOM uint32_t UART1      : 1;            /*!< [3..3] desc UART1                                                         */
      __IOM uint32_t UART2      : 1;            /*!< [4..4] desc UART2                                                         */
      __IOM uint32_t ATIM       : 1;            /*!< [5..5] desc ATIM                                                          */
      __IOM uint32_t GTIM1      : 1;            /*!< [6..6] desc GTIM1                                                         */
      __IOM uint32_t GTIM2      : 1;            /*!< [7..7] desc GTIM2                                                         */
      __IOM uint32_t UART3      : 1;            /*!< [8..8] desc UART3                                                         */
      __IM  uint32_t            : 2;
      __IOM uint32_t GTIM3      : 1;            /*!< [11..11] desc GTIM3                                                       */
      __IOM uint32_t GTIM4      : 1;            /*!< [12..12] desc GTIM4                                                       */
      __IOM uint32_t SPI2       : 1;            /*!< [13..13] desc SPI2                                                        */
      __IOM uint32_t SPI3       : 1;            /*!< [14..14] desc SPI3                                                        */
    } APBRST1_f;
  } ;
  
  union {
    __IOM uint32_t RESETFLAG;                   /*!< (@ 0x0000004C) Reset Status Reg                                           */
    
    struct {
      __IOM uint32_t POR        : 1;            /*!< [0..0] desc POR                                                           */
      __IM  uint32_t            : 2;
      __IOM uint32_t LVD        : 1;            /*!< [3..3] desc LVD                                                           */
      __IOM uint32_t IWDT       : 1;            /*!< [4..4] desc IWDT                                                          */
      __IOM uint32_t WWDT       : 1;            /*!< [5..5] desc WWDT                                                          */
      __IOM uint32_t RSTB       : 1;            /*!< [6..6] desc RSTB                                                          */
      __IM  uint32_t            : 1;
      __IOM uint32_t LOCKUP     : 1;            /*!< [8..8] desc LOCKUP                                                        */
      __IOM uint32_t SYSRESETREQ : 1;           /*!< [9..9] desc SYSRESETREQ                                                   */
    } RESETFLAG_f;
  } ;
  __IM  uint32_t  RESERVED1[8];
  
  union {
    __IOM uint32_t MCO;                         /*!< (@ 0x00000070) Master Clock Output Control Reg                            */
    
    struct {
      __IOM uint32_t SOURCE     : 4;            /*!< [3..0] desc SOURCE                                                        */
      __IOM uint32_t DIV        : 4;            /*!< [7..4] desc DIV                                                           */
    } MCO_f;
  } ;
} SYSCTRL_TypeDef;                                 /*!< Size = 116 (0x74)                                                         */



/* =========================================================================================================================== */
/* ================                                            VC1                                            ================ */
/* =========================================================================================================================== */


/**
  * @brief desc VC1 (VC1)
  */

typedef struct {                                /*!< (@ 0x40000084) VC1 Structure                                              */
  
  union {
    __IOM uint32_t CR0;                         /*!< (@ 0x00000000) Control register0                                          */
    
    struct {
      __IOM uint32_t EN         : 1;            /*!< [0..0] desc EN                                                            */
      __IOM uint32_t RESP       : 1;            /*!< [1..1] desc RESP                                                          */
      __IM  uint32_t            : 1;
      __IOM uint32_t HYS        : 1;            /*!< [3..3] desc HYS                                                           */
      __IM  uint32_t            : 1;
      __IOM uint32_t IE         : 1;            /*!< [5..5] desc IE                                                            */
      __IOM uint32_t POL        : 1;            /*!< [6..6] desc POL                                                           */
      __IOM uint32_t WINDOW     : 1;            /*!< [7..7] desc WINDOW                                                        */
      __IOM uint32_t INN        : 2;            /*!< [9..8] desc INN                                                           */
      __IM  uint32_t            : 2;
      __IOM uint32_t INP        : 2;            /*!< [13..12] desc INP                                                         */
    } CR0_f;
  } ;
  
  union {
    __IOM uint32_t CR1;                         /*!< (@ 0x00000004) Control register1                                          */
    
    struct {
      __IOM uint32_t FLTTIME    : 4;            /*!< [3..0] desc FLTTIME                                                       */
      __IOM uint32_t FLTCLK     : 1;            /*!< [4..4] desc FLTCLK                                                        */
      __IOM uint32_t FALLIE     : 1;            /*!< [5..5] desc FALLIE                                                        */
      __IOM uint32_t RISEIE     : 1;            /*!< [6..6] desc RISEIE                                                        */
      __IOM uint32_t HIGHIE     : 1;            /*!< [7..7] desc HIGHIE                                                        */
      __IOM uint32_t BLANKTIME  : 3;            /*!< [10..8] desc BLANKTIME                                                    */
      __IOM uint32_t BLANKLVL   : 1;            /*!< [11..11] desc BLANKLVL                                                    */
    } CR1_f;
  } ;
  
  union {
    __IOM uint32_t CR2;                         /*!< (@ 0x00000008) Control register1                                          */
    
    struct {
      __IOM uint32_t ATIMTRGO     : 1;          /*!< [0..0] desc ATIM1TRGO                                                     */
      __IOM uint32_t ATIMTRGO2    : 1;          /*!< [1..1] desc ATIM1TRGO2                                                    */
      __IOM uint32_t ATIMOC1REFC  : 1;          /*!< [2..2] desc ATIM1OC1REFC                                                  */
      __IOM uint32_t ATIMOC2REFC  : 1;          /*!< [3..3] desc ATIM1OC2REFC                                                  */
      __IOM uint32_t ATIMOC3REFC  : 1;          /*!< [4..4] desc ATIM1OC3REFC                                                  */
      __IOM uint32_t ATIMOC4REFC  : 1;          /*!< [5..5] desc ATIM1OC4REFC                                                  */
      __IOM uint32_t ATIMOC5REFC  : 1;          /*!< [6..6] desc ATIM1OC5REFC                                                  */
      __IOM uint32_t ATIMOC6REFC  : 1;          /*!< [7..7] desc ATIM1OC6REFC                                                  */
      __IOM uint32_t GTIM1TRGO    : 1;          /*!< [8..8] desc GTIM1TRGO                                                     */
      __IOM uint32_t GTIM1OC1REFC : 1;          /*!< [9..9] desc GTIM1OC1REFC                                                  */
      __IOM uint32_t GTIM1OC2REFC : 1;          /*!< [10..10] desc GTIM1OC2REFC                                                */
      __IOM uint32_t GTIM1OC3REFC : 1;          /*!< [11..11] desc GTIM1OC3REFC                                                */
      __IOM uint32_t GTIM1OC4REFC : 1;          /*!< [12..12] desc GTIM1OC4REFC                                                */
      __IOM uint32_t GTIM2TRGO    : 1;          /*!< [13..13] desc GTIM2TRGO                                                   */
      __IOM uint32_t GTIM2OC1REFC : 1;          /*!< [14..14] desc GTIM2OC1REFC                                                */
      __IOM uint32_t GTIM2OC2REFC : 1;          /*!< [15..15] desc GTIM2OC2REFC                                                */
      __IOM uint32_t GTIM2OC3REFC : 1;          /*!< [16..16] desc GTIM2OC3REFC                                                */
      __IOM uint32_t GTIM2OC4REFC : 1;          /*!< [17..17] desc GTIM2OC4REFC                                                */
      __IOM uint32_t GTIM3TRGO    : 1;          /*!< [18..18] desc GTIM3TRGO                                                   */
      __IOM uint32_t GTIM3OC1REFC : 1;          /*!< [19..19] desc GTIM3OC1REFC                                                */
      __IOM uint32_t GTIM3OC2REFC : 1;          /*!< [20..20] desc GTIM3OC2REFC                                                */
      __IOM uint32_t GTIM3OC3REFC : 1;          /*!< [21..21] desc GTIM3OC3REFC                                                */
      __IOM uint32_t GTIM3OC4REFC : 1;          /*!< [22..22] desc GTIM3OC4REFC                                                */
      __IOM uint32_t GTIM4TRGO    : 1;          /*!< [23..23] desc GTIM4TRGO                                                   */
      __IOM uint32_t GTIM4OC1REFC : 1;          /*!< [24..24] desc GTIM4OC1REFC                                                */
      __IOM uint32_t GTIM4OC2REFC : 1;          /*!< [25..25] desc GTIM4OC2REFC                                                */
      __IOM uint32_t GTIM4OC3REFC : 1;          /*!< [26..26] desc GTIM4OC3REFC                                                */
      __IOM uint32_t GTIM4OC4REFC : 1;          /*!< [27..27] desc GTIM4OC4REFC                                                */
      __IOM uint32_t BTIM1TRGO    : 1;          /*!< [28..28] desc BTIM1TRGO                                                   */
      __IOM uint32_t BTIM2TRGO    : 1;          /*!< [29..29] desc BTIM2TRGO                                                   */
      __IOM uint32_t BTIM3TRGO    : 1;          /*!< [30..30] desc BTIM3TRGO                                                   */
      __IOM uint32_t HALLTIM1TRGO : 1;          /*!< [31..31] desc HALLTIM1TRGO                                                */
    } CR2_f;
  } ;
  
  union {
    __IOM uint32_t SR;                          /*!< (@ 0x0000000C) Status register                                            */
    
    struct {
      __IOM uint32_t INTF       : 1;            /*!< [0..0] desc INTF                                                          */
      __IM  uint32_t FLTV       : 1;            /*!< [1..1] desc FLTV                                                          */
    } SR_f;
  } ;
} VC_TypeDef;                                      /*!< Size = 16 (0x10)                                                          */



/* =========================================================================================================================== */
/* ================                                          VC12REF                                          ================ */
/* =========================================================================================================================== */


/**
  * @brief desc VC12REF (VC12REF)
  */

typedef struct {                                /*!< (@ 0x40000080) VC12REF Structure                                          */
  
  union {
    __IOM uint32_t REF;                         /*!< (@ 0x00000000) VCREF Control register                                     */
    
    struct {
      __IOM uint32_t DIV        : 3;            /*!< [2..0] desc DIV                                                           */
      __IM  uint32_t            : 1;
      __IOM uint32_t EN         : 1;            /*!< [4..4] desc EN                                                            */
      __IOM uint32_t VIN        : 1;            /*!< [5..5] desc VIN                                                           */
    } REF_f;
  } ;
} VCREF_TypeDef;                                  /*!< Size = 4 (0x4)                                                            */



/* =========================================================================================================================== */
/* ================                                           WWDT                                            ================ */
/* =========================================================================================================================== */


/**
  * @brief desc WWDT (WWDT)
  */

typedef struct {                                /*!< WWDT Structure                                                            */
  
  union {
    __IOM uint32_t CR0;                         /*!< Control register0                                                         */
    
    struct {
      __IOM uint32_t WCNT       : 7;            /*!< desc WCNT                                                                 */
      __IOM uint32_t EN         : 1;            /*!< desc EN                                                                   */
    } CR0_f;
  } ;
  
  union {
    __IOM uint32_t CR1;                         /*!< Control register1                                                         */
    
    struct {
      __IOM uint32_t WINR       : 7;            /*!< desc WINR                                                                 */
      __IOM uint32_t PRS        : 3;            /*!< desc PRESCALE                                                             */
      __IOM uint32_t IE         : 1;            /*!< desc IE                                                                   */
    } CR1_f;
  } ;
  
  union {
    __IOM uint32_t SR;                          /*!< status register                                                           */
    
    struct {
      __IOM uint32_t POV        : 1;            /*!< desc POV                                                                  */
    } SR_f;
  } ;
} WWDT_TypeDef;                                  /*!< Size = 12 (0xc)                                                           */


/** @} */ /* End of group Device_Peripheral_peripherals */


/* =========================================================================================================================== */
/* ================                          Device Specific Peripheral Address Map                           ================ */
/* =========================================================================================================================== */


/** @addtogroup Device_Peripheral_peripheralAddr
  * @{
  */

#define ADC1_BASE                   0x40000000UL
#define ADC2_BASE                   0x40000100UL
#define ATIM_BASE                   0x40001400UL
#define BGR_BASE                    0x400000FCUL
#define BTIM1_BASE                  0x40004800UL
#define BTIM2_BASE                  0x40004840UL
#define BTIM3_BASE                  0x40004880UL
#define CORDIC_BASE                 0x40023400UL
#define CRC_BASE                    0x40023000UL
#define DAC_BASE                    0x400000C0UL
#define DMA_BASE                    0x40020000UL
#define DMACHANNEL1_BASE            0x40020020UL
#define DMACHANNEL2_BASE            0x40020040UL
#define DMACHANNEL3_BASE            0x40020060UL
#define DMACHANNEL4_BASE            0x40020080UL
#define EAU_BASE                    0x40023200UL
#define FLASH_BASE                  0x40022000UL
#define GPIOA_BASE                  0x48000000UL
#define GPIOB_BASE                  0x48000100UL
#define GPIOC_BASE                  0x48000200UL
#define GPIOF_BASE                  0x48000300UL
#define GTIM1_BASE                  0x40001800UL
#define GTIM2_BASE                  0x40001C00UL
#define GTIM3_BASE                  0x40002400UL
#define GTIM4_BASE                  0x40002800UL
#define HALLTIM_BASE                0x40006400UL
#define I2C1_BASE                   0x40005800UL
#define I2C2_BASE                   0x40005C00UL
#define IRMOD_BASE                  0x40004080UL
#define IWDT_BASE                   0x40005000UL
#define LPTIM_BASE                  0x40006000UL
#define UART1_BASE                  0x40000C00UL
#define UART2_BASE                  0x40001000UL
#define UART3_BASE                  0x40002000UL
#define LVD_BASE                    0x400000A4UL
#define OPA1_BASE                   0x400000B0UL
#define OPA2_BASE                   0x400000B8UL
#define RAM_BASE                    0x40022400UL
#define RTC_BASE                    0x40004400UL
#define SPI1_BASE                   0x40000800UL
#define SPI2_BASE                   0x40000400UL
#define SPI3_BASE                   0x40003400UL
#define SYSCTRL_BASE                0x40004000UL
#define VC1_BASE                    0x40000084UL
#define VC12REF_BASE                0x40000080UL
#define VC2_BASE                    0x40000094UL
#define VC3_BASE                    0x40000184UL
#define VC34REF_BASE                0x40000180UL
#define VC4_BASE                    0x40000194UL
#define WWDT_BASE                   0x40005400UL

/** @} */ /* End of group Device_Peripheral_peripheralAddr */


/* =========================================================================================================================== */
/* ================                                  Peripheral declaration                                   ================ */
/* =========================================================================================================================== */


/** @addtogroup Device_Peripheral_declaration
  * @{
  */

#define CW_ADC1                        ((ADC_TypeDef*)               ADC1_BASE)
#define CW_ADC2                        ((ADC_TypeDef*)               ADC2_BASE)
#define CW_ATIM                        ((ATIM_TypeDef*)              ATIM_BASE)
#define CW_BGR                         ((BGR_TypeDef*)               BGR_BASE)
#define CW_BTIM1                       ((BTIM_TypeDef*)              BTIM1_BASE)
#define CW_BTIM2                       ((BTIM_TypeDef*)              BTIM2_BASE)
#define CW_BTIM3                       ((BTIM_TypeDef*)              BTIM3_BASE)
#define CW_CORDIC                      ((CORDIC_TypeDef*)            CORDIC_BASE)
#define CW_CRC                         ((CRC_TypeDef*)               CRC_BASE)
#define CW_DAC                         ((DAC_TypeDef*)               DAC_BASE)
#define CW_DMA                         ((DMA_TypeDef*)               DMA_BASE)
#define CW_DMACHANNEL1                 ((DMACHANNEL_TypeDef*)        DMACHANNEL1_BASE)
#define CW_DMACHANNEL2                 ((DMACHANNEL_TypeDef*)        DMACHANNEL2_BASE)
#define CW_DMACHANNEL3                 ((DMACHANNEL_TypeDef*)        DMACHANNEL3_BASE)
#define CW_DMACHANNEL4                 ((DMACHANNEL_TypeDef*)        DMACHANNEL4_BASE)
#define CW_EAU                         ((EAU_TypeDef*)               EAU_BASE)
#define CW_FLASH                       ((FLASH_TypeDef*)             FLASH_BASE)
#define CW_GPIOA                       ((GPIO_TypeDef*)              GPIOA_BASE)
#define CW_GPIOB                       ((GPIO_TypeDef*)              GPIOB_BASE)
#define CW_GPIOC                       ((GPIO_TypeDef*)              GPIOC_BASE)
#define CW_GPIOF                       ((GPIO_TypeDef*)              GPIOF_BASE)
#define CW_GTIM1                       ((GTIM_TypeDef*)              GTIM1_BASE)
#define CW_GTIM2                       ((GTIM_TypeDef*)              GTIM2_BASE)
#define CW_GTIM3                       ((GTIM_TypeDef*)              GTIM3_BASE)
#define CW_GTIM4                       ((GTIM_TypeDef*)              GTIM4_BASE)
#define CW_HALLTIM                     ((HALLTIM_TypeDef*)           HALLTIM_BASE)
#define CW_I2C1                        ((I2C_TypeDef*)               I2C1_BASE)
#define CW_I2C2                        ((I2C_TypeDef*)               I2C2_BASE)
#define CW_IRMOD                       ((IRMOD_TypeDef*)             IRMOD_BASE)
#define CW_IWDT                        ((IWDT_TypeDef*)              IWDT_BASE)
#define CW_LPTIM                       ((LPTIM_TypeDef*)             LPTIM_BASE)
#define CW_UART1                       ((UART_TypeDef*)              UART1_BASE)
#define CW_UART2                       ((UART_TypeDef*)              UART2_BASE)
#define CW_UART3                       ((UART_TypeDef*)              UART3_BASE)
#define CW_LVD                         ((LVD_TypeDef*)               LVD_BASE)
#define CW_OPA1                        ((OPA_TypeDef*)               OPA1_BASE)
#define CW_OPA2                        ((OPA_TypeDef*)               OPA2_BASE)
#define CW_RAM                         ((RAM_TypeDef*)               RAM_BASE)
#define CW_RTC                         ((RTC_TypeDef*)               RTC_BASE)
#define CW_SPI1                        ((SPI_TypeDef*)               SPI1_BASE)
#define CW_SPI2                        ((SPI_TypeDef*)               SPI2_BASE)
#define CW_SPI3                        ((SPI_TypeDef*)               SPI3_BASE)
#define CW_SYSCTRL                     ((SYSCTRL_TypeDef*)           SYSCTRL_BASE)
#define CW_VC1                         ((VC_TypeDef*)                VC1_BASE)
#define CW_VC12REF                     ((VCREF_TypeDef*)            VC12REF_BASE)
#define CW_VC2                         ((VC_TypeDef*)                VC2_BASE)
#define CW_VC3                         ((VC_TypeDef*)                VC3_BASE)
#define CW_VC34REF                     ((VCREF_TypeDef*)            VC34REF_BASE)
#define CW_VC4                         ((VC_TypeDef*)                VC4_BASE)
#define CW_WWDT                        ((WWDT_TypeDef*)              WWDT_BASE)

/** @} */ /* End of group Device_Peripheral_declaration */


/* =========================================  End of section using anonymous unions  ========================================= */
#if defined (__CC_ARM)
  #pragma pop
#elif defined (__ICCARM__)
  /* leave anonymous unions enabled */
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
  #pragma clang diagnostic pop
#elif defined (__GNUC__)
  /* anonymous unions are enabled by default */
#elif defined (__TMS470__)
  /* anonymous unions are enabled by default */
#elif defined (__TASKING__)
  #pragma warning restore
#elif defined (__CSMC__)
  /* anonymous unions are enabled by default */
#endif


/* =========================================================================================================================== */
/* ================                                Pos/Mask Peripheral Section                                ================ */
/* =========================================================================================================================== */


/** @addtogroup PosMask_peripherals
  * @{
  */



/* =========================================================================================================================== */
/* ================                                            ADC                                            ================ */
/* =========================================================================================================================== */

/* ==========================================================  CR  =========================================================== */
#define ADCx_CR_SLAVE_Pos                 (7UL)                     /*!< SLAVE (Bit 7)                                         */
#define ADCx_CR_SLAVE_Msk                 (0x80UL)                  /*!< SLAVE (Bitfield-Mask: 0x01)                           */
#define ADCx_CR_ENS_Pos                   (4UL)                     /*!< ENS (Bit 4)                                           */
#define ADCx_CR_ENS_Msk                   (0x70UL)                  /*!< ENS (Bitfield-Mask: 0x07)                             */
#define ADCx_CR_CLK_Pos                   (2UL)                     /*!< CLKSRC (Bit 2)                                        */
#define ADCx_CR_CLK_Msk                   (0xcUL)                   /*!< CLKSRC (Bitfield-Mask: 0x03)                          */
#define ADCx_CR_CONT_Pos                  (1UL)                     /*!< CONT (Bit 1)                                          */
#define ADCx_CR_CONT_Msk                  (0x2UL)                   /*!< CONT (Bitfield-Mask: 0x01)                            */
#define ADCx_CR_EN_Pos                    (0UL)                     /*!< EN (Bit 0)                                            */
#define ADCx_CR_EN_Msk                    (0x1UL)                   /*!< EN (Bitfield-Mask: 0x01)                              */
/* =========================================================  START  ========================================================= */
#define ADCx_START_START_Pos              (0UL)                     /*!< START (Bit 0)                                         */
#define ADCx_START_START_Msk              (0x1UL)                   /*!< START (Bitfield-Mask: 0x01)                           */
/* =========================================================  AWDTR  ========================================================= */
#define ADCx_AWDTR_VTH_Pos                (16UL)                    /*!< VTH (Bit 16)                                          */
#define ADCx_AWDTR_VTH_Msk                (0xfff0000UL)             /*!< VTH (Bitfield-Mask: 0xfff)                            */
#define ADCx_AWDTR_VTL_Pos                (0UL)                     /*!< VTL (Bit 0)                                           */
#define ADCx_AWDTR_VTL_Msk                (0xfffUL)                 /*!< VTL (Bitfield-Mask: 0xfff)                            */
/* =========================================================  AWDCR  ========================================================= */
#define ADCx_AWDCR_IN15_Pos               (15UL)                    /*!< IN15 (Bit 15)                                         */
#define ADCx_AWDCR_IN15_Msk               (0x8000UL)                /*!< IN15 (Bitfield-Mask: 0x01)                            */
#define ADCx_AWDCR_IN14_Pos               (14UL)                    /*!< IN14 (Bit 14)                                         */
#define ADCx_AWDCR_IN14_Msk               (0x4000UL)                /*!< IN14 (Bitfield-Mask: 0x01)                            */
#define ADCx_AWDCR_IN13_Pos               (13UL)                    /*!< IN13 (Bit 13)                                         */
#define ADCx_AWDCR_IN13_Msk               (0x2000UL)                /*!< IN13 (Bitfield-Mask: 0x01)                            */
#define ADCx_AWDCR_IN12_Pos               (12UL)                    /*!< IN12 (Bit 12)                                         */
#define ADCx_AWDCR_IN12_Msk               (0x1000UL)                /*!< IN12 (Bitfield-Mask: 0x01)                            */
#define ADCx_AWDCR_IN11_Pos               (11UL)                    /*!< IN11 (Bit 11)                                         */
#define ADCx_AWDCR_IN11_Msk               (0x800UL)                 /*!< IN11 (Bitfield-Mask: 0x01)                            */
#define ADCx_AWDCR_IN10_Pos               (10UL)                    /*!< IN10 (Bit 10)                                         */
#define ADCx_AWDCR_IN10_Msk               (0x400UL)                 /*!< IN10 (Bitfield-Mask: 0x01)                            */
#define ADCx_AWDCR_IN9_Pos                (9UL)                     /*!< IN9 (Bit 9)                                           */
#define ADCx_AWDCR_IN9_Msk                (0x200UL)                 /*!< IN9 (Bitfield-Mask: 0x01)                             */
#define ADCx_AWDCR_IN8_Pos                (8UL)                     /*!< IN8 (Bit 8)                                           */
#define ADCx_AWDCR_IN8_Msk                (0x100UL)                 /*!< IN8 (Bitfield-Mask: 0x01)                             */
#define ADCx_AWDCR_IN7_Pos                (7UL)                     /*!< IN7 (Bit 7)                                           */
#define ADCx_AWDCR_IN7_Msk                (0x80UL)                  /*!< IN7 (Bitfield-Mask: 0x01)                             */
#define ADCx_AWDCR_IN6_Pos                (6UL)                     /*!< IN6 (Bit 6)                                           */
#define ADCx_AWDCR_IN6_Msk                (0x40UL)                  /*!< IN6 (Bitfield-Mask: 0x01)                             */
#define ADCx_AWDCR_IN5_Pos                (5UL)                     /*!< IN5 (Bit 5)                                           */
#define ADCx_AWDCR_IN5_Msk                (0x20UL)                  /*!< IN5 (Bitfield-Mask: 0x01)                             */
#define ADCx_AWDCR_IN4_Pos                (4UL)                     /*!< IN4 (Bit 4)                                           */
#define ADCx_AWDCR_IN4_Msk                (0x10UL)                  /*!< IN4 (Bitfield-Mask: 0x01)                             */
#define ADCx_AWDCR_IN3_Pos                (3UL)                     /*!< IN3 (Bit 3)                                           */
#define ADCx_AWDCR_IN3_Msk                (0x8UL)                   /*!< IN3 (Bitfield-Mask: 0x01)                             */
#define ADCx_AWDCR_IN2_Pos                (2UL)                     /*!< IN2 (Bit 2)                                           */
#define ADCx_AWDCR_IN2_Msk                (0x4UL)                   /*!< IN2 (Bitfield-Mask: 0x01)                             */
#define ADCx_AWDCR_IN1_Pos                (1UL)                     /*!< IN1 (Bit 1)                                           */
#define ADCx_AWDCR_IN1_Msk                (0x2UL)                   /*!< IN1 (Bitfield-Mask: 0x01)                             */
#define ADCx_AWDCR_IN0_Pos                (0UL)                     /*!< IN0 (Bit 0)                                           */
#define ADCx_AWDCR_IN0_Msk                (0x1UL)                   /*!< IN0 (Bitfield-Mask: 0x01)                             */
/* ========================================================  TRIGGER  ======================================================== */
#define ADCx_TRIGGER_HALLTIMTRGO_Pos      (31UL)                    /*!< HALLTIMTRGO (Bit 31)                                  */
#define ADCx_TRIGGER_HALLTIMTRGO_Msk      (0x80000000UL)            /*!< HALLTIMTRGO (Bitfield-Mask: 0x01)                     */
#define ADCx_TRIGGER_BTIM3TRGO_Pos        (30UL)                    /*!< BTIM3TRGO (Bit 30)                                    */
#define ADCx_TRIGGER_BTIM3TRGO_Msk        (0x40000000UL)            /*!< BTIM3TRGO (Bitfield-Mask: 0x01)                       */
#define ADCx_TRIGGER_BTIM2TRGO_Pos        (29UL)                    /*!< BTIM2TRGO (Bit 29)                                    */
#define ADCx_TRIGGER_BTIM2TRGO_Msk        (0x20000000UL)            /*!< BTIM2TRGO (Bitfield-Mask: 0x01)                       */
#define ADCx_TRIGGER_BTIM1TRGO_Pos        (28UL)                    /*!< BTIM1TRGO (Bit 28)                                    */
#define ADCx_TRIGGER_BTIM1TRGO_Msk        (0x10000000UL)            /*!< BTIM1TRGO (Bitfield-Mask: 0x01)                       */
#define ADCx_TRIGGER_GTIM4OC4REFC_Pos     (27UL)                    /*!< GTIM4OC4REFC (Bit 27)                                 */
#define ADCx_TRIGGER_GTIM4OC4REFC_Msk     (0x8000000UL)             /*!< GTIM4OC4REFC (Bitfield-Mask: 0x01)                    */
#define ADCx_TRIGGER_GTIM4OC3REFC_Pos     (26UL)                    /*!< GTIM4OC3REFC (Bit 26)                                 */
#define ADCx_TRIGGER_GTIM4OC3REFC_Msk     (0x4000000UL)             /*!< GTIM4OC3REFC (Bitfield-Mask: 0x01)                    */
#define ADCx_TRIGGER_GTIM4OC2REFC_Pos     (25UL)                    /*!< GTIM4OC2REFC (Bit 25)                                 */
#define ADCx_TRIGGER_GTIM4OC2REFC_Msk     (0x2000000UL)             /*!< GTIM4OC2REFC (Bitfield-Mask: 0x01)                    */
#define ADCx_TRIGGER_GTIM4OC1REFC_Pos     (24UL)                    /*!< GTIM4OC1REFC (Bit 24)                                 */
#define ADCx_TRIGGER_GTIM4OC1REFC_Msk     (0x1000000UL)             /*!< GTIM4OC1REFC (Bitfield-Mask: 0x01)                    */
#define ADCx_TRIGGER_GTIM4TRGO_Pos        (23UL)                    /*!< GTIM4TRGO (Bit 23)                                    */
#define ADCx_TRIGGER_GTIM4TRGO_Msk        (0x800000UL)              /*!< GTIM4TRGO (Bitfield-Mask: 0x01)                       */
#define ADCx_TRIGGER_GTIM3OC4REFC_Pos     (22UL)                    /*!< GTIM3OC4REFC (Bit 22)                                 */
#define ADCx_TRIGGER_GTIM3OC4REFC_Msk     (0x400000UL)              /*!< GTIM3OC4REFC (Bitfield-Mask: 0x01)                    */
#define ADCx_TRIGGER_GTIM3OC3REFC_Pos     (21UL)                    /*!< GTIM3OC3REFC (Bit 21)                                 */
#define ADCx_TRIGGER_GTIM3OC3REFC_Msk     (0x200000UL)              /*!< GTIM3OC3REFC (Bitfield-Mask: 0x01)                    */
#define ADCx_TRIGGER_GTIM3OC2REFC_Pos     (20UL)                    /*!< GTIM3OC2REFC (Bit 20)                                 */
#define ADCx_TRIGGER_GTIM3OC2REFC_Msk     (0x100000UL)              /*!< GTIM3OC2REFC (Bitfield-Mask: 0x01)                    */
#define ADCx_TRIGGER_GTIM3OC1REFC_Pos     (19UL)                    /*!< GTIM3OC1REFC (Bit 19)                                 */
#define ADCx_TRIGGER_GTIM3OC1REFC_Msk     (0x80000UL)               /*!< GTIM3OC1REFC (Bitfield-Mask: 0x01)                    */
#define ADCx_TRIGGER_GTIM3TRGO_Pos        (18UL)                    /*!< GTIM3TRGO (Bit 18)                                    */
#define ADCx_TRIGGER_GTIM3TRGO_Msk        (0x40000UL)               /*!< GTIM3TRGO (Bitfield-Mask: 0x01)                       */
#define ADCx_TRIGGER_GTIM2OC4REFC_Pos     (17UL)                    /*!< GTIM2OC4REFC (Bit 17)                                 */
#define ADCx_TRIGGER_GTIM2OC4REFC_Msk     (0x20000UL)               /*!< GTIM2OC4REFC (Bitfield-Mask: 0x01)                    */
#define ADCx_TRIGGER_GTIM2OC3REFC_Pos     (16UL)                    /*!< GTIM2OC3REFC (Bit 16)                                 */
#define ADCx_TRIGGER_GTIM2OC3REFC_Msk     (0x10000UL)               /*!< GTIM2OC3REFC (Bitfield-Mask: 0x01)                    */
#define ADCx_TRIGGER_GTIM2OC2REFC_Pos     (15UL)                    /*!< GTIM2OC2REFC (Bit 15)                                 */
#define ADCx_TRIGGER_GTIM2OC2REFC_Msk     (0x8000UL)                /*!< GTIM2OC2REFC (Bitfield-Mask: 0x01)                    */
#define ADCx_TRIGGER_GTIM2OC1REFC_Pos     (14UL)                    /*!< GTIM2OC1REFC (Bit 14)                                 */
#define ADCx_TRIGGER_GTIM2OC1REFC_Msk     (0x4000UL)                /*!< GTIM2OC1REFC (Bitfield-Mask: 0x01)                    */
#define ADCx_TRIGGER_GTIM2TRGO_Pos        (13UL)                    /*!< GTIM2TRGO (Bit 13)                                    */
#define ADCx_TRIGGER_GTIM2TRGO_Msk        (0x2000UL)                /*!< GTIM2TRGO (Bitfield-Mask: 0x01)                       */
#define ADCx_TRIGGER_GTIM1OC4REFC_Pos     (12UL)                    /*!< GTIM1OC4REFC (Bit 12)                                 */
#define ADCx_TRIGGER_GTIM1OC4REFC_Msk     (0x1000UL)                /*!< GTIM1OC4REFC (Bitfield-Mask: 0x01)                    */
#define ADCx_TRIGGER_GTIM1OC3REFC_Pos     (11UL)                    /*!< GTIM1OC3REFC (Bit 11)                                 */
#define ADCx_TRIGGER_GTIM1OC3REFC_Msk     (0x800UL)                 /*!< GTIM1OC3REFC (Bitfield-Mask: 0x01)                    */
#define ADCx_TRIGGER_GTIM1OC2REFC_Pos     (10UL)                    /*!< GTIM1OC2REFC (Bit 10)                                 */
#define ADCx_TRIGGER_GTIM1OC2REFC_Msk     (0x400UL)                 /*!< GTIM1OC2REFC (Bitfield-Mask: 0x01)                    */
#define ADCx_TRIGGER_GTIM1OC1REFC_Pos     (9UL)                     /*!< GTIM1OC1REFC (Bit 9)                                  */
#define ADCx_TRIGGER_GTIM1OC1REFC_Msk     (0x200UL)                 /*!< GTIM1OC1REFC (Bitfield-Mask: 0x01)                    */
#define ADCx_TRIGGER_GTIM1TRGO_Pos        (8UL)                     /*!< GTIM1TRGO (Bit 8)                                     */
#define ADCx_TRIGGER_GTIM1TRGO_Msk        (0x100UL)                 /*!< GTIM1TRGO (Bitfield-Mask: 0x01)                       */
#define ADCx_TRIGGER_ATIMOC6REFC_Pos      (7UL)                     /*!< ATIMOC6REFC (Bit 7)                                   */
#define ADCx_TRIGGER_ATIMOC6REFC_Msk      (0x80UL)                  /*!< ATIMOC6REFC (Bitfield-Mask: 0x01)                     */
#define ADCx_TRIGGER_ATIMOC5REFC_Pos      (6UL)                     /*!< ATIMOC5REFC (Bit 6)                                   */
#define ADCx_TRIGGER_ATIMOC5REFC_Msk      (0x40UL)                  /*!< ATIMOC5REFC (Bitfield-Mask: 0x01)                     */
#define ADCx_TRIGGER_ATIMOC4REFC_Pos      (5UL)                     /*!< ATIMOC4REFC (Bit 5)                                   */
#define ADCx_TRIGGER_ATIMOC4REFC_Msk      (0x20UL)                  /*!< ATIMOC4REFC (Bitfield-Mask: 0x01)                     */
#define ADCx_TRIGGER_ATIMOC3REFC_Pos      (4UL)                     /*!< ATIMOC3REFC (Bit 4)                                   */
#define ADCx_TRIGGER_ATIMOC3REFC_Msk      (0x10UL)                  /*!< ATIMOC3REFC (Bitfield-Mask: 0x01)                     */
#define ADCx_TRIGGER_ATIMOC2REFC_Pos      (3UL)                     /*!< ATIMOC2REFC (Bit 3)                                   */
#define ADCx_TRIGGER_ATIMOC2REFC_Msk      (0x8UL)                   /*!< ATIMOC2REFC (Bitfield-Mask: 0x01)                     */
#define ADCx_TRIGGER_ATIMOC1REFC_Pos      (2UL)                     /*!< ATIMOC1REFC (Bit 2)                                   */
#define ADCx_TRIGGER_ATIMOC1REFC_Msk      (0x4UL)                   /*!< ATIMOC1REFC (Bitfield-Mask: 0x01)                     */
#define ADCx_TRIGGER_ATIMTRGO2_Pos        (1UL)                     /*!< ATIMTRGO2 (Bit 1)                                     */
#define ADCx_TRIGGER_ATIMTRGO2_Msk        (0x2UL)                   /*!< ATIMTRGO2 (Bitfield-Mask: 0x01)                       */
#define ADCx_TRIGGER_ATIMTRGO_Pos         (0UL)                     /*!< ATIMTRGO (Bit 0)                                      */
#define ADCx_TRIGGER_ATIMTRGO_Msk         (0x1UL)                   /*!< ATIMTRGO (Bitfield-Mask: 0x01)                        */
/* ========================================================  SAMPLE  ========================================================= */
#define ADCx_SAMPLE_SQRCH7_Pos            (28UL)                    /*!< SQRCH7 (Bit 28)                                       */
#define ADCx_SAMPLE_SQRCH7_Msk            (0xf0000000UL)            /*!< SQRCH7 (Bitfield-Mask: 0x0f)                          */
#define ADCx_SAMPLE_SQRCH6_Pos            (24UL)                    /*!< SQRCH6 (Bit 24)                                       */
#define ADCx_SAMPLE_SQRCH6_Msk            (0xf000000UL)             /*!< SQRCH6 (Bitfield-Mask: 0x0f)                          */
#define ADCx_SAMPLE_SQRCH5_Pos            (20UL)                    /*!< SQRCH5 (Bit 20)                                       */
#define ADCx_SAMPLE_SQRCH5_Msk            (0xf00000UL)              /*!< SQRCH5 (Bitfield-Mask: 0x0f)                          */
#define ADCx_SAMPLE_SQRCH4_Pos            (16UL)                    /*!< SQRCH4 (Bit 16)                                       */
#define ADCx_SAMPLE_SQRCH4_Msk            (0xf0000UL)               /*!< SQRCH4 (Bitfield-Mask: 0x0f)                          */
#define ADCx_SAMPLE_SQRCH3_Pos            (12UL)                    /*!< SQRCH3 (Bit 12)                                       */
#define ADCx_SAMPLE_SQRCH3_Msk            (0xf000UL)                /*!< SQRCH3 (Bitfield-Mask: 0x0f)                          */
#define ADCx_SAMPLE_SQRCH2_Pos            (8UL)                     /*!< SQRCH2 (Bit 8)                                        */
#define ADCx_SAMPLE_SQRCH2_Msk            (0xf00UL)                 /*!< SQRCH2 (Bitfield-Mask: 0x0f)                          */
#define ADCx_SAMPLE_SQRCH1_Pos            (4UL)                     /*!< SQRCH1 (Bit 4)                                        */
#define ADCx_SAMPLE_SQRCH1_Msk            (0xf0UL)                  /*!< SQRCH1 (Bitfield-Mask: 0x0f)                          */
#define ADCx_SAMPLE_SQRCH0_Pos            (0UL)                     /*!< SQRCH0 (Bit 0)                                        */
#define ADCx_SAMPLE_SQRCH0_Msk            (0xfUL)                   /*!< SQRCH0 (Bitfield-Mask: 0x0f)                          */
/* ========================================================  SQRCFR  ========================================================= */
#define ADCx_SQRCFR_SQRCH7_Pos            (28UL)                    /*!< SQRCH7 (Bit 28)                                       */
#define ADCx_SQRCFR_SQRCH7_Msk            (0xf0000000UL)            /*!< SQRCH7 (Bitfield-Mask: 0x0f)                          */
#define ADCx_SQRCFR_SQRCH6_Pos            (24UL)                    /*!< SQRCH6 (Bit 24)                                       */
#define ADCx_SQRCFR_SQRCH6_Msk            (0xf000000UL)             /*!< SQRCH6 (Bitfield-Mask: 0x0f)                          */
#define ADCx_SQRCFR_SQRCH5_Pos            (20UL)                    /*!< SQRCH5 (Bit 20)                                       */
#define ADCx_SQRCFR_SQRCH5_Msk            (0xf00000UL)              /*!< SQRCH5 (Bitfield-Mask: 0x0f)                          */
#define ADCx_SQRCFR_SQRCH4_Pos            (16UL)                    /*!< SQRCH4 (Bit 16)                                       */
#define ADCx_SQRCFR_SQRCH4_Msk            (0xf0000UL)               /*!< SQRCH4 (Bitfield-Mask: 0x0f)                          */
#define ADCx_SQRCFR_SQRCH3_Pos            (12UL)                    /*!< SQRCH3 (Bit 12)                                       */
#define ADCx_SQRCFR_SQRCH3_Msk            (0xf000UL)                /*!< SQRCH3 (Bitfield-Mask: 0x0f)                          */
#define ADCx_SQRCFR_SQRCH2_Pos            (8UL)                     /*!< SQRCH2 (Bit 8)                                        */
#define ADCx_SQRCFR_SQRCH2_Msk            (0xf00UL)                 /*!< SQRCH2 (Bitfield-Mask: 0x0f)                          */
#define ADCx_SQRCFR_SQRCH1_Pos            (4UL)                     /*!< SQRCH1 (Bit 4)                                        */
#define ADCx_SQRCFR_SQRCH1_Msk            (0xf0UL)                  /*!< SQRCH1 (Bitfield-Mask: 0x0f)                          */
#define ADCx_SQRCFR_SQRCH0_Pos            (0UL)                     /*!< SQRCH0 (Bit 0)                                        */
#define ADCx_SQRCFR_SQRCH0_Msk            (0xfUL)                   /*!< SQRCH0 (Bitfield-Mask: 0x0f)                          */
/* ==========================================================  IER  ========================================================== */
#define ADCx_IER_DMAEOS_Pos               (6UL)                     /*!< DMAEOS (Bit 6)                                        */
#define ADCx_IER_DMAEOS_Msk               (0x40UL)                  /*!< DMAEOS (Bitfield-Mask: 0x01)                          */
#define ADCx_IER_DMAEOC_Pos               (5UL)                     /*!< DMAEOC (Bit 5)                                        */
#define ADCx_IER_DMAEOC_Msk               (0x20UL)                  /*!< DMAEOC (Bitfield-Mask: 0x01)                          */
#define ADCx_IER_AWDH_Pos                 (4UL)                     /*!< AWDH (Bit 4)                                          */
#define ADCx_IER_AWDH_Msk                 (0x10UL)                  /*!< AWDH (Bitfield-Mask: 0x01)                            */
#define ADCx_IER_AWDL_Pos                 (3UL)                     /*!< AWDL (Bit 3)                                          */
#define ADCx_IER_AWDL_Msk                 (0x8UL)                   /*!< AWDL (Bitfield-Mask: 0x01)                            */
#define ADCx_IER_EOS_Pos                  (1UL)                     /*!< EOS (Bit 1)                                           */
#define ADCx_IER_EOS_Msk                  (0x2UL)                   /*!< EOS (Bitfield-Mask: 0x01)                             */
#define ADCx_IER_EOC_Pos                  (0UL)                     /*!< EOC (Bit 0)                                           */
#define ADCx_IER_EOC_Msk                  (0x1UL)                   /*!< EOC (Bitfield-Mask: 0x01)                             */
/* ==========================================================  ISR  ========================================================== */
#define ADCx_ISR_AWDH_Pos                 (4UL)                     /*!< AWDH (Bit 4)                                          */
#define ADCx_ISR_AWDH_Msk                 (0x10UL)                  /*!< AWDH (Bitfield-Mask: 0x01)                            */
#define ADCx_ISR_AWDL_Pos                 (3UL)                     /*!< AWDL (Bit 3)                                          */
#define ADCx_ISR_AWDL_Msk                 (0x8UL)                   /*!< AWDL (Bitfield-Mask: 0x01)                            */
#define ADCx_ISR_EOS_Pos                  (1UL)                     /*!< EOS (Bit 1)                                           */
#define ADCx_ISR_EOS_Msk                  (0x2UL)                   /*!< EOS (Bitfield-Mask: 0x01)                             */
#define ADCx_ISR_EOC_Pos                  (0UL)                     /*!< EOC (Bit 0)                                           */
#define ADCx_ISR_EOC_Msk                  (0x1UL)                   /*!< EOC (Bitfield-Mask: 0x01)                             */
/* ==========================================================  ICR  ========================================================== */
#define ADCx_ICR_AWDH_Pos                 (4UL)                     /*!< AWDH (Bit 4)                                          */
#define ADCx_ICR_AWDH_Msk                 (0x10UL)                  /*!< AWDH (Bitfield-Mask: 0x01)                            */
#define ADCx_ICR_AWDL_Pos                 (3UL)                     /*!< AWDL (Bit 3)                                          */
#define ADCx_ICR_AWDL_Msk                 (0x8UL)                   /*!< AWDL (Bitfield-Mask: 0x01)                            */
#define ADCx_ICR_EOS_Pos                  (1UL)                     /*!< EOS (Bit 1)                                           */
#define ADCx_ICR_EOS_Msk                  (0x2UL)                   /*!< EOS (Bitfield-Mask: 0x01)                             */
#define ADCx_ICR_EOC_Pos                  (0UL)                     /*!< EOC (Bit 0)                                           */
#define ADCx_ICR_EOC_Msk                  (0x1UL)                   /*!< EOC (Bitfield-Mask: 0x01)                             */
/* ========================================================  RESULT0  ======================================================== */
#define ADCx_RESULT0_RESULT_Pos           (0UL)                     /*!< RESULT (Bit 0)                                        */
#define ADCx_RESULT0_RESULT_Msk           (0xfffUL)                 /*!< RESULT (Bitfield-Mask: 0xffff)                        */
/* ========================================================  RESULT1  ======================================================== */
#define ADCx_RESULT1_RESULT_Pos           (0UL)                     /*!< RESULT (Bit 0)                                        */
#define ADCx_RESULT1_RESULT_Msk           (0xfffUL)                 /*!< RESULT (Bitfield-Mask: 0xffff)                        */
/* ========================================================  RESULT2  ======================================================== */
#define ADCx_RESULT2_RESULT_Pos           (0UL)                     /*!< RESULT (Bit 0)                                        */
#define ADCx_RESULT2_RESULT_Msk           (0xfffUL)                 /*!< RESULT (Bitfield-Mask: 0xffff)                        */
/* ========================================================  RESULT3  ======================================================== */
#define ADCx_RESULT3_RESULT_Pos           (0UL)                     /*!< RESULT (Bit 0)                                        */
#define ADCx_RESULT3_RESULT_Msk           (0xfffUL)                 /*!< RESULT (Bitfield-Mask: 0xffff)                        */
/* ========================================================  RESULT4  ======================================================== */
#define ADCx_RESULT4_RESULT_Pos           (0UL)                     /*!< RESULT (Bit 0)                                        */
#define ADCx_RESULT4_RESULT_Msk           (0xfffUL)                 /*!< RESULT (Bitfield-Mask: 0xffff)                        */
/* ========================================================  RESULT5  ======================================================== */
#define ADCx_RESULT5_RESULT_Pos           (0UL)                     /*!< RESULT (Bit 0)                                        */
#define ADCx_RESULT5_RESULT_Msk           (0xfffUL)                 /*!< RESULT (Bitfield-Mask: 0xffff)                        */
/* ========================================================  RESULT6  ======================================================== */
#define ADCx_RESULT6_RESULT_Pos           (0UL)                     /*!< RESULT (Bit 0)                                        */
#define ADCx_RESULT6_RESULT_Msk           (0xfffUL)                 /*!< RESULT (Bitfield-Mask: 0xffff)                        */
/* ========================================================  RESULT7  ======================================================== */
#define ADCx_RESULT7_RESULT_Pos           (0UL)                     /*!< RESULT (Bit 0)                                        */
#define ADCx_RESULT7_RESULT_Msk           (0xfffUL)                 /*!< RESULT (Bitfield-Mask: 0xffff)                        */


/* =========================================================================================================================== */
/* ================                                           ATIM                                            ================ */
/* =========================================================================================================================== */

/* ==========================================================  CR1  ========================================================== */
#define ATIM_CR1_UIFREMAP_Pos             (11UL)                    /*!< UIFREMAP (Bit 11)                                     */
#define ATIM_CR1_UIFREMAP_Msk             (0x800UL)                 /*!< UIFREMAP (Bitfield-Mask: 0x01)                        */
#define ATIM_CR1_CKD_Pos                  (8UL)                     /*!< CKD (Bit 8)                                           */
#define ATIM_CR1_CKD_Msk                  (0x300UL)                 /*!< CKD (Bitfield-Mask: 0x03)                             */
#define ATIM_CR1_ARPE_Pos                 (7UL)                     /*!< ARPE (Bit 7)                                          */
#define ATIM_CR1_ARPE_Msk                 (0x80UL)                  /*!< ARPE (Bitfield-Mask: 0x01)                            */
#define ATIM_CR1_CMS_Pos                  (5UL)                     /*!< CMS (Bit 5)                                           */
#define ATIM_CR1_CMS_Msk                  (0x60UL)                  /*!< CMS (Bitfield-Mask: 0x03)                             */
#define ATIM_CR1_DIR_Pos                  (4UL)                     /*!< DIR (Bit 4)                                           */
#define ATIM_CR1_DIR_Msk                  (0x10UL)                  /*!< DIR (Bitfield-Mask: 0x01)                             */
#define ATIM_CR1_OPM_Pos                  (3UL)                     /*!< OPM (Bit 3)                                           */
#define ATIM_CR1_OPM_Msk                  (0x8UL)                   /*!< OPM (Bitfield-Mask: 0x01)                             */
#define ATIM_CR1_URS_Pos                  (2UL)                     /*!< URS (Bit 2)                                           */
#define ATIM_CR1_URS_Msk                  (0x4UL)                   /*!< URS (Bitfield-Mask: 0x01)                             */
#define ATIM_CR1_UDIS_Pos                 (1UL)                     /*!< UDIS (Bit 1)                                          */
#define ATIM_CR1_UDIS_Msk                 (0x2UL)                   /*!< UDIS (Bitfield-Mask: 0x01)                            */
#define ATIM_CR1_CEN_Pos                  (0UL)                     /*!< CEN (Bit 0)                                           */
#define ATIM_CR1_CEN_Msk                  (0x1UL)                   /*!< CEN (Bitfield-Mask: 0x01)                             */
/* ==========================================================  CR2  ========================================================== */
#define ATIM_CR2_MMSH_Pos                 (25UL)                    /*!< MMSH (Bit 25)                                         */
#define ATIM_CR2_MMSH_Msk                 (0x6000000UL)             /*!< MMSH (Bitfield-Mask: 0x03)                            */
#define ATIM_CR2_MMS2_Pos                 (20UL)                    /*!< MMS2 (Bit 20)                                         */
#define ATIM_CR2_MMS2_Msk                 (0x1f00000UL)             /*!< MMS2 (Bitfield-Mask: 0x1f)                            */
#define ATIM_CR2_OIS6N_Pos                (19UL)                    /*!< OIS6N (Bit 19)                                        */
#define ATIM_CR2_OIS6N_Msk                (0x80000UL)               /*!< OIS6N (Bitfield-Mask: 0x01)                           */
#define ATIM_CR2_OIS6_Pos                 (18UL)                    /*!< OIS6 (Bit 18)                                         */
#define ATIM_CR2_OIS6_Msk                 (0x40000UL)               /*!< OIS6 (Bitfield-Mask: 0x01)                            */
#define ATIM_CR2_OIS5N_Pos                (17UL)                    /*!< OIS5N (Bit 17)                                        */
#define ATIM_CR2_OIS5N_Msk                (0x20000UL)               /*!< OIS5N (Bitfield-Mask: 0x01)                           */
#define ATIM_CR2_OIS5_Pos                 (16UL)                    /*!< OIS5 (Bit 16)                                         */
#define ATIM_CR2_OIS5_Msk                 (0x10000UL)               /*!< OIS5 (Bitfield-Mask: 0x01)                            */
#define ATIM_CR2_OIS4N_Pos                (15UL)                    /*!< OIS4N (Bit 15)                                        */
#define ATIM_CR2_OIS4N_Msk                (0x8000UL)                /*!< OIS4N (Bitfield-Mask: 0x01)                           */
#define ATIM_CR2_OIS4_Pos                 (14UL)                    /*!< OIS4 (Bit 14)                                         */
#define ATIM_CR2_OIS4_Msk                 (0x4000UL)                /*!< OIS4 (Bitfield-Mask: 0x01)                            */
#define ATIM_CR2_OIS3N_Pos                (13UL)                    /*!< OIS3N (Bit 13)                                        */
#define ATIM_CR2_OIS3N_Msk                (0x2000UL)                /*!< OIS3N (Bitfield-Mask: 0x01)                           */
#define ATIM_CR2_OIS3_Pos                 (12UL)                    /*!< OIS3 (Bit 12)                                         */
#define ATIM_CR2_OIS3_Msk                 (0x1000UL)                /*!< OIS3 (Bitfield-Mask: 0x01)                            */
#define ATIM_CR2_OIS2N_Pos                (11UL)                    /*!< OIS2N (Bit 11)                                        */
#define ATIM_CR2_OIS2N_Msk                (0x800UL)                 /*!< OIS2N (Bitfield-Mask: 0x01)                           */
#define ATIM_CR2_OIS2_Pos                 (10UL)                    /*!< OIS2 (Bit 10)                                         */
#define ATIM_CR2_OIS2_Msk                 (0x400UL)                 /*!< OIS2 (Bitfield-Mask: 0x01)                            */
#define ATIM_CR2_OIS1N_Pos                (9UL)                     /*!< OIS1N (Bit 9)                                         */
#define ATIM_CR2_OIS1N_Msk                (0x200UL)                 /*!< OIS1N (Bitfield-Mask: 0x01)                           */
#define ATIM_CR2_OIS1_Pos                 (8UL)                     /*!< OIS1 (Bit 8)                                          */
#define ATIM_CR2_OIS1_Msk                 (0x100UL)                 /*!< OIS1 (Bitfield-Mask: 0x01)                            */
#define ATIM_CR2_TI1S_Pos                 (7UL)                     /*!< TI1S (Bit 7)                                          */
#define ATIM_CR2_TI1S_Msk                 (0x80UL)                  /*!< TI1S (Bitfield-Mask: 0x01)                            */
#define ATIM_CR2_MMS_Pos                  (4UL)                     /*!< MMS (Bit 4)                                           */
#define ATIM_CR2_MMS_Msk                  (0x70UL)                  /*!< MMS (Bitfield-Mask: 0x07)                             */
#define ATIM_CR2_CCDS_Pos                 (3UL)                     /*!< CCDS (Bit 3)                                          */
#define ATIM_CR2_CCDS_Msk                 (0x8UL)                   /*!< CCDS (Bitfield-Mask: 0x01)                            */
#define ATIM_CR2_CCUS_Pos                 (2UL)                     /*!< CCUS (Bit 2)                                          */
#define ATIM_CR2_CCUS_Msk                 (0x4UL)                   /*!< CCUS (Bitfield-Mask: 0x01)                            */
#define ATIM_CR2_CCPC_Pos                 (0UL)                     /*!< CCPC (Bit 0)                                          */
#define ATIM_CR2_CCPC_Msk                 (0x1UL)                   /*!< CCPC (Bitfield-Mask: 0x01)                            */
/* =========================================================  SMCR  ========================================================== */
#define ATIM_SMCR_SMSPS_Pos               (25UL)                    /*!< SMSPS (Bit 25)                                        */
#define ATIM_SMCR_SMSPS_Msk               (0x2000000UL)             /*!< SMSPS (Bitfield-Mask: 0x01)                           */
#define ATIM_SMCR_SMSPE_Pos               (24UL)                    /*!< SMSPE (Bit 24)                                        */
#define ATIM_SMCR_SMSPE_Msk               (0x1000000UL)             /*!< SMSPE (Bitfield-Mask: 0x01)                           */
#define ATIM_SMCR_TSH_Pos                 (20UL)                    /*!< TSH (Bit 20)                                          */
#define ATIM_SMCR_TSH_Msk                 (0x300000UL)              /*!< TSH (Bitfield-Mask: 0x03)                             */
#define ATIM_SMCR_SMSH_Pos                (16UL)                    /*!< SMSH (Bit 16)                                         */
#define ATIM_SMCR_SMSH_Msk                (0x10000UL)               /*!< SMSH (Bitfield-Mask: 0x01)                            */
#define ATIM_SMCR_ETP_Pos                 (15UL)                    /*!< ETP (Bit 15)                                          */
#define ATIM_SMCR_ETP_Msk                 (0x8000UL)                /*!< ETP (Bitfield-Mask: 0x01)                             */
#define ATIM_SMCR_ECE_Pos                 (14UL)                    /*!< ECE (Bit 14)                                          */
#define ATIM_SMCR_ECE_Msk                 (0x4000UL)                /*!< ECE (Bitfield-Mask: 0x01)                             */
#define ATIM_SMCR_ETPS_Pos                (12UL)                    /*!< ETPS (Bit 12)                                         */
#define ATIM_SMCR_ETPS_Msk                (0x3000UL)                /*!< ETPS (Bitfield-Mask: 0x03)                            */
#define ATIM_SMCR_ETF_Pos                 (8UL)                     /*!< ETF (Bit 8)                                           */
#define ATIM_SMCR_ETF_Msk                 (0xf00UL)                 /*!< ETF (Bitfield-Mask: 0x0f)                             */
#define ATIM_SMCR_MSM_Pos                 (7UL)                     /*!< MSM (Bit 7)                                           */
#define ATIM_SMCR_MSM_Msk                 (0x80UL)                  /*!< MSM (Bitfield-Mask: 0x01)                             */
#define ATIM_SMCR_TS_Pos                  (4UL)                     /*!< TS (Bit 4)                                            */
#define ATIM_SMCR_TS_Msk                  (0x70UL)                  /*!< TS (Bitfield-Mask: 0x07)                              */
#define ATIM_SMCR_OCCS_Pos                (3UL)                     /*!< OCCS (Bit 3)                                          */
#define ATIM_SMCR_OCCS_Msk                (0x8UL)                   /*!< OCCS (Bitfield-Mask: 0x01)                            */
#define ATIM_SMCR_SMS_Pos                 (0UL)                     /*!< SMS (Bit 0)                                           */
#define ATIM_SMCR_SMS_Msk                 (0x7UL)                   /*!< SMS (Bitfield-Mask: 0x07)                             */
/* ==========================================================  IER  ========================================================== */
#define ATIM_IER_TERRIE_Pos               (23UL)                    /*!< TERRIE (Bit 23)                                       */
#define ATIM_IER_TERRIE_Msk               (0x800000UL)              /*!< TERRIE (Bitfield-Mask: 0x01)                          */
#define ATIM_IER_IERRIE_Pos               (22UL)                    /*!< IERRIE (Bit 22)                                       */
#define ATIM_IER_IERRIE_Msk               (0x400000UL)              /*!< IERRIE (Bitfield-Mask: 0x01)                          */
#define ATIM_IER_DIRIE_Pos                (21UL)                    /*!< DIRIE (Bit 21)                                        */
#define ATIM_IER_DIRIE_Msk                (0x200000UL)              /*!< DIRIE (Bitfield-Mask: 0x01)                           */
#define ATIM_IER_IDXIE_Pos                (20UL)                    /*!< IDXIE (Bit 20)                                        */
#define ATIM_IER_IDXIE_Msk                (0x100000UL)              /*!< IDXIE (Bitfield-Mask: 0x01)                           */
#define ATIM_IER_CC6DE_Pos                (19UL)                    /*!< CC6DE (Bit 19)                                        */
#define ATIM_IER_CC6DE_Msk                (0x80000UL)               /*!< CC6DE (Bitfield-Mask: 0x01)                           */
#define ATIM_IER_CC5DE_Pos                (18UL)                    /*!< CC5DE (Bit 18)                                        */
#define ATIM_IER_CC5DE_Msk                (0x40000UL)               /*!< CC5DE (Bitfield-Mask: 0x01)                           */
#define ATIM_IER_CC6IE_Pos                (17UL)                    /*!< CC6IE (Bit 17)                                        */
#define ATIM_IER_CC6IE_Msk                (0x20000UL)               /*!< CC6IE (Bitfield-Mask: 0x01)                           */
#define ATIM_IER_CC5IE_Pos                (16UL)                    /*!< CC5IE (Bit 16)                                        */
#define ATIM_IER_CC5IE_Msk                (0x10000UL)               /*!< CC5IE (Bitfield-Mask: 0x01)                           */
#define ATIM_IER_TDE_Pos                  (14UL)                    /*!< TDE (Bit 14)                                          */
#define ATIM_IER_TDE_Msk                  (0x4000UL)                /*!< TDE (Bitfield-Mask: 0x01)                             */
#define ATIM_IER_COMDE_Pos                (13UL)                    /*!< COMDE (Bit 13)                                        */
#define ATIM_IER_COMDE_Msk                (0x2000UL)                /*!< COMDE (Bitfield-Mask: 0x01)                           */
#define ATIM_IER_CC4DE_Pos                (12UL)                    /*!< CC4DE (Bit 12)                                        */
#define ATIM_IER_CC4DE_Msk                (0x1000UL)                /*!< CC4DE (Bitfield-Mask: 0x01)                           */
#define ATIM_IER_CC3DE_Pos                (11UL)                    /*!< CC3DE (Bit 11)                                        */
#define ATIM_IER_CC3DE_Msk                (0x800UL)                 /*!< CC3DE (Bitfield-Mask: 0x01)                           */
#define ATIM_IER_CC2DE_Pos                (10UL)                    /*!< CC2DE (Bit 10)                                        */
#define ATIM_IER_CC2DE_Msk                (0x400UL)                 /*!< CC2DE (Bitfield-Mask: 0x01)                           */
#define ATIM_IER_CC1DE_Pos                (9UL)                     /*!< CC1DE (Bit 9)                                         */
#define ATIM_IER_CC1DE_Msk                (0x200UL)                 /*!< CC1DE (Bitfield-Mask: 0x01)                           */
#define ATIM_IER_UDE_Pos                  (8UL)                     /*!< UDE (Bit 8)                                           */
#define ATIM_IER_UDE_Msk                  (0x100UL)                 /*!< UDE (Bitfield-Mask: 0x01)                             */
#define ATIM_IER_BIE_Pos                  (7UL)                     /*!< BIE (Bit 7)                                           */
#define ATIM_IER_BIE_Msk                  (0x80UL)                  /*!< BIE (Bitfield-Mask: 0x01)                             */
#define ATIM_IER_TIE_Pos                  (6UL)                     /*!< TIE (Bit 6)                                           */
#define ATIM_IER_TIE_Msk                  (0x40UL)                  /*!< TIE (Bitfield-Mask: 0x01)                             */
#define ATIM_IER_COMIE_Pos                (5UL)                     /*!< COMIE (Bit 5)                                         */
#define ATIM_IER_COMIE_Msk                (0x20UL)                  /*!< COMIE (Bitfield-Mask: 0x01)                           */
#define ATIM_IER_CC4IE_Pos                (4UL)                     /*!< CC4IE (Bit 4)                                         */
#define ATIM_IER_CC4IE_Msk                (0x10UL)                  /*!< CC4IE (Bitfield-Mask: 0x01)                           */
#define ATIM_IER_CC3IE_Pos                (3UL)                     /*!< CC3IE (Bit 3)                                         */
#define ATIM_IER_CC3IE_Msk                (0x8UL)                   /*!< CC3IE (Bitfield-Mask: 0x01)                           */
#define ATIM_IER_CC2IE_Pos                (2UL)                     /*!< CC2IE (Bit 2)                                         */
#define ATIM_IER_CC2IE_Msk                (0x4UL)                   /*!< CC2IE (Bitfield-Mask: 0x01)                           */
#define ATIM_IER_CC1IE_Pos                (1UL)                     /*!< CC1IE (Bit 1)                                         */
#define ATIM_IER_CC1IE_Msk                (0x2UL)                   /*!< CC1IE (Bitfield-Mask: 0x01)                           */
#define ATIM_IER_UIE_Pos                  (0UL)                     /*!< UIE (Bit 0)                                           */
#define ATIM_IER_UIE_Msk                  (0x1UL)                   /*!< UIE (Bitfield-Mask: 0x01)                             */
/* ==========================================================  ISR  ========================================================== */
#define ATIM_ISR_TERRF_Pos                (23UL)                    /*!< TERRF (Bit 23)                                        */
#define ATIM_ISR_TERRF_Msk                (0x800000UL)              /*!< TERRF (Bitfield-Mask: 0x01)                           */
#define ATIM_ISR_IERRF_Pos                (22UL)                    /*!< IERRF (Bit 22)                                        */
#define ATIM_ISR_IERRF_Msk                (0x400000UL)              /*!< IERRF (Bitfield-Mask: 0x01)                           */
#define ATIM_ISR_DIRF_Pos                 (21UL)                    /*!< DIRF (Bit 21)                                         */
#define ATIM_ISR_DIRF_Msk                 (0x200000UL)              /*!< DIRF (Bitfield-Mask: 0x01)                            */
#define ATIM_ISR_IDXF_Pos                 (20UL)                    /*!< IDXF (Bit 20)                                         */
#define ATIM_ISR_IDXF_Msk                 (0x100000UL)              /*!< IDXF (Bitfield-Mask: 0x01)                            */
#define ATIM_ISR_CC6OF_Pos                (19UL)                    /*!< CC6OF (Bit 19)                                        */
#define ATIM_ISR_CC6OF_Msk                (0x80000UL)               /*!< CC6OF (Bitfield-Mask: 0x01)                           */
#define ATIM_ISR_CC5OF_Pos                (18UL)                    /*!< CC5OF (Bit 18)                                        */
#define ATIM_ISR_CC5OF_Msk                (0x40000UL)               /*!< CC5OF (Bitfield-Mask: 0x01)                           */
#define ATIM_ISR_CC6IF_Pos                (17UL)                    /*!< CC6IF (Bit 17)                                        */
#define ATIM_ISR_CC6IF_Msk                (0x20000UL)               /*!< CC6IF (Bitfield-Mask: 0x01)                           */
#define ATIM_ISR_CC5IF_Pos                (16UL)                    /*!< CC5IF (Bit 16)                                        */
#define ATIM_ISR_CC5IF_Msk                (0x10000UL)               /*!< CC5IF (Bitfield-Mask: 0x01)                           */
#define ATIM_ISR_SBIF_Pos                 (13UL)                    /*!< SBIF (Bit 13)                                         */
#define ATIM_ISR_SBIF_Msk                 (0x2000UL)                /*!< SBIF (Bitfield-Mask: 0x01)                            */
#define ATIM_ISR_CC4OF_Pos                (12UL)                    /*!< CC4OF (Bit 12)                                        */
#define ATIM_ISR_CC4OF_Msk                (0x1000UL)                /*!< CC4OF (Bitfield-Mask: 0x01)                           */
#define ATIM_ISR_CC3OF_Pos                (11UL)                    /*!< CC3OF (Bit 11)                                        */
#define ATIM_ISR_CC3OF_Msk                (0x800UL)                 /*!< CC3OF (Bitfield-Mask: 0x01)                           */
#define ATIM_ISR_CC2OF_Pos                (10UL)                    /*!< CC2OF (Bit 10)                                        */
#define ATIM_ISR_CC2OF_Msk                (0x400UL)                 /*!< CC2OF (Bitfield-Mask: 0x01)                           */
#define ATIM_ISR_CC1OF_Pos                (9UL)                     /*!< CC1OF (Bit 9)                                         */
#define ATIM_ISR_CC1OF_Msk                (0x200UL)                 /*!< CC1OF (Bitfield-Mask: 0x01)                           */
#define ATIM_ISR_B2IF_Pos                 (8UL)                     /*!< B2IF (Bit 8)                                          */
#define ATIM_ISR_B2IF_Msk                 (0x100UL)                 /*!< B2IF (Bitfield-Mask: 0x01)                            */
#define ATIM_ISR_BIF_Pos                  (7UL)                     /*!< BIF (Bit 7)                                           */
#define ATIM_ISR_BIF_Msk                  (0x80UL)                  /*!< BIF (Bitfield-Mask: 0x01)                             */
#define ATIM_ISR_TIF_Pos                  (6UL)                     /*!< TIF (Bit 6)                                           */
#define ATIM_ISR_TIF_Msk                  (0x40UL)                  /*!< TIF (Bitfield-Mask: 0x01)                             */
#define ATIM_ISR_COMIF_Pos                (5UL)                     /*!< COMIF (Bit 5)                                         */
#define ATIM_ISR_COMIF_Msk                (0x20UL)                  /*!< COMIF (Bitfield-Mask: 0x01)                           */
#define ATIM_ISR_CC4IF_Pos                (4UL)                     /*!< CC4IF (Bit 4)                                         */
#define ATIM_ISR_CC4IF_Msk                (0x10UL)                  /*!< CC4IF (Bitfield-Mask: 0x01)                           */
#define ATIM_ISR_CC3IF_Pos                (3UL)                     /*!< CC3IF (Bit 3)                                         */
#define ATIM_ISR_CC3IF_Msk                (0x8UL)                   /*!< CC3IF (Bitfield-Mask: 0x01)                           */
#define ATIM_ISR_CC2IF_Pos                (2UL)                     /*!< CC2IF (Bit 2)                                         */
#define ATIM_ISR_CC2IF_Msk                (0x4UL)                   /*!< CC2IF (Bitfield-Mask: 0x01)                           */
#define ATIM_ISR_CC1IF_Pos                (1UL)                     /*!< CC1IF (Bit 1)                                         */
#define ATIM_ISR_CC1IF_Msk                (0x2UL)                   /*!< CC1IF (Bitfield-Mask: 0x01)                           */
#define ATIM_ISR_UIF_Pos                  (0UL)                     /*!< UIF (Bit 0)                                           */
#define ATIM_ISR_UIF_Msk                  (0x1UL)                   /*!< UIF (Bitfield-Mask: 0x01)                             */
/* ==========================================================  EGR  ========================================================== */
#define ATIM_EGR_CC6G_Pos                 (17UL)                    /*!< CC6G (Bit 17)                                         */
#define ATIM_EGR_CC6G_Msk                 (0x20000UL)               /*!< CC6G (Bitfield-Mask: 0x01)                            */
#define ATIM_EGR_CC5G_Pos                 (16UL)                    /*!< CC5G (Bit 16)                                         */
#define ATIM_EGR_CC5G_Msk                 (0x10000UL)               /*!< CC5G (Bitfield-Mask: 0x01)                            */
#define ATIM_EGR_B2G_Pos                  (8UL)                     /*!< B2G (Bit 8)                                           */
#define ATIM_EGR_B2G_Msk                  (0x100UL)                 /*!< B2G (Bitfield-Mask: 0x01)                             */
#define ATIM_EGR_BG_Pos                   (7UL)                     /*!< BG (Bit 7)                                            */
#define ATIM_EGR_BG_Msk                   (0x80UL)                  /*!< BG (Bitfield-Mask: 0x01)                              */
#define ATIM_EGR_TG_Pos                   (6UL)                     /*!< TG (Bit 6)                                            */
#define ATIM_EGR_TG_Msk                   (0x40UL)                  /*!< TG (Bitfield-Mask: 0x01)                              */
#define ATIM_EGR_COMG_Pos                 (5UL)                     /*!< COMG (Bit 5)                                          */
#define ATIM_EGR_COMG_Msk                 (0x20UL)                  /*!< COMG (Bitfield-Mask: 0x01)                            */
#define ATIM_EGR_CC4G_Pos                 (4UL)                     /*!< CC4G (Bit 4)                                          */
#define ATIM_EGR_CC4G_Msk                 (0x10UL)                  /*!< CC4G (Bitfield-Mask: 0x01)                            */
#define ATIM_EGR_CC3G_Pos                 (3UL)                     /*!< CC3G (Bit 3)                                          */
#define ATIM_EGR_CC3G_Msk                 (0x8UL)                   /*!< CC3G (Bitfield-Mask: 0x01)                            */
#define ATIM_EGR_CC2G_Pos                 (2UL)                     /*!< CC2G (Bit 2)                                          */
#define ATIM_EGR_CC2G_Msk                 (0x4UL)                   /*!< CC2G (Bitfield-Mask: 0x01)                            */
#define ATIM_EGR_CC1G_Pos                 (1UL)                     /*!< CC1G (Bit 1)                                          */
#define ATIM_EGR_CC1G_Msk                 (0x2UL)                   /*!< CC1G (Bitfield-Mask: 0x01)                            */
#define ATIM_EGR_UG_Pos                   (0UL)                     /*!< UG (Bit 0)                                            */
#define ATIM_EGR_UG_Msk                   (0x1UL)                   /*!< UG (Bitfield-Mask: 0x01)                              */
/* =======================================================  CCMR1CAP  ======================================================== */
#define ATIM_CCMR1CAP_IC2F_Pos            (12UL)                    /*!< IC2F (Bit 12)                                         */
#define ATIM_CCMR1CAP_IC2F_Msk            (0xf000UL)                /*!< IC2F (Bitfield-Mask: 0x0f)                            */
#define ATIM_CCMR1CAP_IC2PSC_Pos          (10UL)                    /*!< IC2PSC (Bit 10)                                       */
#define ATIM_CCMR1CAP_IC2PSC_Msk          (0xc00UL)                 /*!< IC2PSC (Bitfield-Mask: 0x03)                          */
#define ATIM_CCMR1CAP_CC2S_Pos            (8UL)                     /*!< CC2S (Bit 8)                                          */
#define ATIM_CCMR1CAP_CC2S_Msk            (0x300UL)                 /*!< CC2S (Bitfield-Mask: 0x03)                            */
#define ATIM_CCMR1CAP_IC1F_Pos            (4UL)                     /*!< IC1F (Bit 4)                                          */
#define ATIM_CCMR1CAP_IC1F_Msk            (0xf0UL)                  /*!< IC1F (Bitfield-Mask: 0x0f)                            */
#define ATIM_CCMR1CAP_IC1PSC_Pos          (2UL)                     /*!< IC1PSC (Bit 2)                                        */
#define ATIM_CCMR1CAP_IC1PSC_Msk          (0xcUL)                   /*!< IC1PSC (Bitfield-Mask: 0x03)                          */
#define ATIM_CCMR1CAP_CC1S_Pos            (0UL)                     /*!< CC1S (Bit 0)                                          */
#define ATIM_CCMR1CAP_CC1S_Msk            (0x3UL)                   /*!< CC1S (Bitfield-Mask: 0x03)                            */
/* =======================================================  CCMR1CMP  ======================================================== */
#define ATIM_CCMR1CMP_OC2MH_Pos           (24UL)                    /*!< OC2MH (Bit 24)                                        */
#define ATIM_CCMR1CMP_OC2MH_Msk           (0x1000000UL)             /*!< OC2MH (Bitfield-Mask: 0x01)                           */
#define ATIM_CCMR1CMP_OC1MH_Pos           (16UL)                    /*!< OC1MH (Bit 16)                                        */
#define ATIM_CCMR1CMP_OC1MH_Msk           (0x10000UL)               /*!< OC1MH (Bitfield-Mask: 0x01)                           */
#define ATIM_CCMR1CMP_OC2CE_Pos           (15UL)                    /*!< OC2CE (Bit 15)                                        */
#define ATIM_CCMR1CMP_OC2CE_Msk           (0x8000UL)                /*!< OC2CE (Bitfield-Mask: 0x01)                           */
#define ATIM_CCMR1CMP_OC2M_Pos            (12UL)                    /*!< OC2M (Bit 12)                                         */
#define ATIM_CCMR1CMP_OC2M_Msk            (0x7000UL)                /*!< OC2M (Bitfield-Mask: 0x07)                            */
#define ATIM_CCMR1CMP_OC2PE_Pos           (11UL)                    /*!< OC2PE (Bit 11)                                        */
#define ATIM_CCMR1CMP_OC2PE_Msk           (0x800UL)                 /*!< OC2PE (Bitfield-Mask: 0x01)                           */
#define ATIM_CCMR1CMP_OC2FE_Pos           (10UL)                    /*!< OC2FE (Bit 10)                                        */
#define ATIM_CCMR1CMP_OC2FE_Msk           (0x400UL)                 /*!< OC2FE (Bitfield-Mask: 0x01)                           */
#define ATIM_CCMR1CMP_CC2S_Pos            (8UL)                     /*!< CC2S (Bit 8)                                          */
#define ATIM_CCMR1CMP_CC2S_Msk            (0x300UL)                 /*!< CC2S (Bitfield-Mask: 0x03)                            */
#define ATIM_CCMR1CMP_OC1CE_Pos           (7UL)                     /*!< OC1CE (Bit 7)                                         */
#define ATIM_CCMR1CMP_OC1CE_Msk           (0x80UL)                  /*!< OC1CE (Bitfield-Mask: 0x01)                           */
#define ATIM_CCMR1CMP_OC1M_Pos            (4UL)                     /*!< OC1M (Bit 4)                                          */
#define ATIM_CCMR1CMP_OC1M_Msk            (0x70UL)                  /*!< OC1M (Bitfield-Mask: 0x07)                            */
#define ATIM_CCMR1CMP_OC1PE_Pos           (3UL)                     /*!< OC1PE (Bit 3)                                         */
#define ATIM_CCMR1CMP_OC1PE_Msk           (0x8UL)                   /*!< OC1PE (Bitfield-Mask: 0x01)                           */
#define ATIM_CCMR1CMP_OC1FE_Pos           (2UL)                     /*!< OC1FE (Bit 2)                                         */
#define ATIM_CCMR1CMP_OC1FE_Msk           (0x4UL)                   /*!< OC1FE (Bitfield-Mask: 0x01)                           */
#define ATIM_CCMR1CMP_CC1S_Pos            (0UL)                     /*!< CC1S (Bit 0)                                          */
#define ATIM_CCMR1CMP_CC1S_Msk            (0x3UL)                   /*!< CC1S (Bitfield-Mask: 0x03)                            */
/* =======================================================  CCMR2CAP  ======================================================== */
#define ATIM_CCMR2CAP_IC4F_Pos            (12UL)                    /*!< IC4F (Bit 12)                                         */
#define ATIM_CCMR2CAP_IC4F_Msk            (0xf000UL)                /*!< IC4F (Bitfield-Mask: 0x0f)                            */
#define ATIM_CCMR2CAP_IC4PSC_Pos          (10UL)                    /*!< IC4PSC (Bit 10)                                       */
#define ATIM_CCMR2CAP_IC4PSC_Msk          (0xc00UL)                 /*!< IC4PSC (Bitfield-Mask: 0x03)                          */
#define ATIM_CCMR2CAP_CC4S_Pos            (8UL)                     /*!< CC4S (Bit 8)                                          */
#define ATIM_CCMR2CAP_CC4S_Msk            (0x300UL)                 /*!< CC4S (Bitfield-Mask: 0x03)                            */
#define ATIM_CCMR2CAP_IC3F_Pos            (4UL)                     /*!< IC3F (Bit 4)                                          */
#define ATIM_CCMR2CAP_IC3F_Msk            (0xf0UL)                  /*!< IC3F (Bitfield-Mask: 0x0f)                            */
#define ATIM_CCMR2CAP_IC3PSC_Pos          (2UL)                     /*!< IC3PSC (Bit 2)                                        */
#define ATIM_CCMR2CAP_IC3PSC_Msk          (0xcUL)                   /*!< IC3PSC (Bitfield-Mask: 0x03)                          */
#define ATIM_CCMR2CAP_CC3S_Pos            (0UL)                     /*!< CC3S (Bit 0)                                          */
#define ATIM_CCMR2CAP_CC3S_Msk            (0x3UL)                   /*!< CC3S (Bitfield-Mask: 0x03)                            */
/* =======================================================  CCMR2CMP  ======================================================== */
#define ATIM_CCMR2CMP_OC4MH_Pos           (24UL)                    /*!< OC4MH (Bit 24)                                        */
#define ATIM_CCMR2CMP_OC4MH_Msk           (0x1000000UL)             /*!< OC4MH (Bitfield-Mask: 0x01)                           */
#define ATIM_CCMR2CMP_OC3MH_Pos           (16UL)                    /*!< OC3MH (Bit 16)                                        */
#define ATIM_CCMR2CMP_OC3MH_Msk           (0x10000UL)               /*!< OC3MH (Bitfield-Mask: 0x01)                           */
#define ATIM_CCMR2CMP_OC4CE_Pos           (15UL)                    /*!< OC4CE (Bit 15)                                        */
#define ATIM_CCMR2CMP_OC4CE_Msk           (0x8000UL)                /*!< OC4CE (Bitfield-Mask: 0x01)                           */
#define ATIM_CCMR2CMP_OC4M_Pos            (12UL)                    /*!< OC4M (Bit 12)                                         */
#define ATIM_CCMR2CMP_OC4M_Msk            (0x7000UL)                /*!< OC4M (Bitfield-Mask: 0x07)                            */
#define ATIM_CCMR2CMP_OC4PE_Pos           (11UL)                    /*!< OC4PE (Bit 11)                                        */
#define ATIM_CCMR2CMP_OC4PE_Msk           (0x800UL)                 /*!< OC4PE (Bitfield-Mask: 0x01)                           */
#define ATIM_CCMR2CMP_OC4FE_Pos           (10UL)                    /*!< OC4FE (Bit 10)                                        */
#define ATIM_CCMR2CMP_OC4FE_Msk           (0x400UL)                 /*!< OC4FE (Bitfield-Mask: 0x01)                           */
#define ATIM_CCMR2CMP_CC4S_Pos            (8UL)                     /*!< CC4S (Bit 8)                                          */
#define ATIM_CCMR2CMP_CC4S_Msk            (0x300UL)                 /*!< CC4S (Bitfield-Mask: 0x03)                            */
#define ATIM_CCMR2CMP_OC3CE_Pos           (7UL)                     /*!< OC3CE (Bit 7)                                         */
#define ATIM_CCMR2CMP_OC3CE_Msk           (0x80UL)                  /*!< OC3CE (Bitfield-Mask: 0x01)                           */
#define ATIM_CCMR2CMP_OC3M_Pos            (4UL)                     /*!< OC3M (Bit 4)                                          */
#define ATIM_CCMR2CMP_OC3M_Msk            (0x70UL)                  /*!< OC3M (Bitfield-Mask: 0x07)                            */
#define ATIM_CCMR2CMP_OC3PE_Pos           (3UL)                     /*!< OC3PE (Bit 3)                                         */
#define ATIM_CCMR2CMP_OC3PE_Msk           (0x8UL)                   /*!< OC3PE (Bitfield-Mask: 0x01)                           */
#define ATIM_CCMR2CMP_OC3FE_Pos           (2UL)                     /*!< OC3FE (Bit 2)                                         */
#define ATIM_CCMR2CMP_OC3FE_Msk           (0x4UL)                   /*!< OC3FE (Bitfield-Mask: 0x01)                           */
#define ATIM_CCMR2CMP_CC3S_Pos            (0UL)                     /*!< CC3S (Bit 0)                                          */
#define ATIM_CCMR2CMP_CC3S_Msk            (0x3UL)                   /*!< CC3S (Bitfield-Mask: 0x03)                            */
/* =======================================================  CCMR3CAP  ======================================================== */
#define ATIM_CCMR3CAP_IC6F_Pos            (12UL)                    /*!< IC6F (Bit 12)                                         */
#define ATIM_CCMR3CAP_IC6F_Msk            (0xf000UL)                /*!< IC6F (Bitfield-Mask: 0x0f)                            */
#define ATIM_CCMR3CAP_IC6PSC_Pos          (10UL)                    /*!< IC6PSC (Bit 10)                                       */
#define ATIM_CCMR3CAP_IC6PSC_Msk          (0xc00UL)                 /*!< IC6PSC (Bitfield-Mask: 0x03)                          */
#define ATIM_CCMR3CAP_CC6S_Pos            (8UL)                     /*!< CC6S (Bit 8)                                          */
#define ATIM_CCMR3CAP_CC6S_Msk            (0x300UL)                 /*!< CC6S (Bitfield-Mask: 0x03)                            */
#define ATIM_CCMR3CAP_IC5F_Pos            (4UL)                     /*!< IC5F (Bit 4)                                          */
#define ATIM_CCMR3CAP_IC5F_Msk            (0xf0UL)                  /*!< IC5F (Bitfield-Mask: 0x0f)                            */
#define ATIM_CCMR3CAP_IC5PSC_Pos          (2UL)                     /*!< IC5PSC (Bit 2)                                        */
#define ATIM_CCMR3CAP_IC5PSC_Msk          (0xcUL)                   /*!< IC5PSC (Bitfield-Mask: 0x03)                          */
#define ATIM_CCMR3CAP_CC5S_Pos            (0UL)                     /*!< CC5S (Bit 0)                                          */
#define ATIM_CCMR3CAP_CC5S_Msk            (0x3UL)                   /*!< CC5S (Bitfield-Mask: 0x03)                            */
/* =======================================================  CCMR3CMP  ======================================================== */
#define ATIM_CCMR3CMP_OC6MH_Pos           (24UL)                    /*!< OC6MH (Bit 24)                                        */
#define ATIM_CCMR3CMP_OC6MH_Msk           (0x1000000UL)             /*!< OC6MH (Bitfield-Mask: 0x01)                           */
#define ATIM_CCMR3CMP_OC5MH_Pos           (16UL)                    /*!< OC5MH (Bit 16)                                        */
#define ATIM_CCMR3CMP_OC5MH_Msk           (0x10000UL)               /*!< OC5MH (Bitfield-Mask: 0x01)                           */
#define ATIM_CCMR3CMP_OC6CE_Pos           (15UL)                    /*!< OC6CE (Bit 15)                                        */
#define ATIM_CCMR3CMP_OC6CE_Msk           (0x8000UL)                /*!< OC6CE (Bitfield-Mask: 0x01)                           */
#define ATIM_CCMR3CMP_OC6M_Pos            (12UL)                    /*!< OC6M (Bit 12)                                         */
#define ATIM_CCMR3CMP_OC6M_Msk            (0x7000UL)                /*!< OC6M (Bitfield-Mask: 0x07)                            */
#define ATIM_CCMR3CMP_OC6PE_Pos           (11UL)                    /*!< OC6PE (Bit 11)                                        */
#define ATIM_CCMR3CMP_OC6PE_Msk           (0x800UL)                 /*!< OC6PE (Bitfield-Mask: 0x01)                           */
#define ATIM_CCMR3CMP_OC6FE_Pos           (10UL)                    /*!< OC6FE (Bit 10)                                        */
#define ATIM_CCMR3CMP_OC6FE_Msk           (0x400UL)                 /*!< OC6FE (Bitfield-Mask: 0x01)                           */
#define ATIM_CCMR3CMP_CC6S_Pos            (8UL)                     /*!< CC6S (Bit 8)                                          */
#define ATIM_CCMR3CMP_CC6S_Msk            (0x300UL)                 /*!< CC6S (Bitfield-Mask: 0x03)                            */
#define ATIM_CCMR3CMP_OC5CE_Pos           (7UL)                     /*!< OC5CE (Bit 7)                                         */
#define ATIM_CCMR3CMP_OC5CE_Msk           (0x80UL)                  /*!< OC5CE (Bitfield-Mask: 0x01)                           */
#define ATIM_CCMR3CMP_OC5M_Pos            (4UL)                     /*!< OC5M (Bit 4)                                          */
#define ATIM_CCMR3CMP_OC5M_Msk            (0x70UL)                  /*!< OC5M (Bitfield-Mask: 0x07)                            */
#define ATIM_CCMR3CMP_OC5PE_Pos           (3UL)                     /*!< OC5PE (Bit 3)                                         */
#define ATIM_CCMR3CMP_OC5PE_Msk           (0x8UL)                   /*!< OC5PE (Bitfield-Mask: 0x01)                           */
#define ATIM_CCMR3CMP_OC5FE_Pos           (2UL)                     /*!< OC5FE (Bit 2)                                         */
#define ATIM_CCMR3CMP_OC5FE_Msk           (0x4UL)                   /*!< OC5FE (Bitfield-Mask: 0x01)                           */
#define ATIM_CCMR3CMP_CC5S_Pos            (0UL)                     /*!< CC5S (Bit 0)                                          */
#define ATIM_CCMR3CMP_CC5S_Msk            (0x3UL)                   /*!< CC5S (Bitfield-Mask: 0x03)                            */
/* =========================================================  CCER  ========================================================== */
#define ATIM_CCER_CC6NP_Pos               (23UL)                    /*!< CC6NP (Bit 23)                                        */
#define ATIM_CCER_CC6NP_Msk               (0x800000UL)              /*!< CC6NP (Bitfield-Mask: 0x01)                           */
#define ATIM_CCER_CC6NE_Pos               (22UL)                    /*!< CC6NE (Bit 22)                                        */
#define ATIM_CCER_CC6NE_Msk               (0x400000UL)              /*!< CC6NE (Bitfield-Mask: 0x01)                           */
#define ATIM_CCER_CC6P_Pos                (21UL)                    /*!< CC6P (Bit 21)                                         */
#define ATIM_CCER_CC6P_Msk                (0x200000UL)              /*!< CC6P (Bitfield-Mask: 0x01)                            */
#define ATIM_CCER_CC6E_Pos                (20UL)                    /*!< CC6E (Bit 20)                                         */
#define ATIM_CCER_CC6E_Msk                (0x100000UL)              /*!< CC6E (Bitfield-Mask: 0x01)                            */
#define ATIM_CCER_CC5NP_Pos               (19UL)                    /*!< CC5NP (Bit 19)                                        */
#define ATIM_CCER_CC5NP_Msk               (0x80000UL)               /*!< CC5NP (Bitfield-Mask: 0x01)                           */
#define ATIM_CCER_CC5NE_Pos               (18UL)                    /*!< CC5NE (Bit 18)                                        */
#define ATIM_CCER_CC5NE_Msk               (0x40000UL)               /*!< CC5NE (Bitfield-Mask: 0x01)                           */
#define ATIM_CCER_CC5P_Pos                (17UL)                    /*!< CC5P (Bit 17)                                         */
#define ATIM_CCER_CC5P_Msk                (0x20000UL)               /*!< CC5P (Bitfield-Mask: 0x01)                            */
#define ATIM_CCER_CC5E_Pos                (16UL)                    /*!< CC5E (Bit 16)                                         */
#define ATIM_CCER_CC5E_Msk                (0x10000UL)               /*!< CC5E (Bitfield-Mask: 0x01)                            */
#define ATIM_CCER_CC4NP_Pos               (15UL)                    /*!< CC4NP (Bit 15)                                        */
#define ATIM_CCER_CC4NP_Msk               (0x8000UL)                /*!< CC4NP (Bitfield-Mask: 0x01)                           */
#define ATIM_CCER_CC4NE_Pos               (14UL)                    /*!< CC4NE (Bit 14)                                        */
#define ATIM_CCER_CC4NE_Msk               (0x4000UL)                /*!< CC4NE (Bitfield-Mask: 0x01)                           */
#define ATIM_CCER_CC4P_Pos                (13UL)                    /*!< CC4P (Bit 13)                                         */
#define ATIM_CCER_CC4P_Msk                (0x2000UL)                /*!< CC4P (Bitfield-Mask: 0x01)                            */
#define ATIM_CCER_CC4E_Pos                (12UL)                    /*!< CC4E (Bit 12)                                         */
#define ATIM_CCER_CC4E_Msk                (0x1000UL)                /*!< CC4E (Bitfield-Mask: 0x01)                            */
#define ATIM_CCER_CC3NP_Pos               (11UL)                    /*!< CC3NP (Bit 11)                                        */
#define ATIM_CCER_CC3NP_Msk               (0x800UL)                 /*!< CC3NP (Bitfield-Mask: 0x01)                           */
#define ATIM_CCER_CC3NE_Pos               (10UL)                    /*!< CC3NE (Bit 10)                                        */
#define ATIM_CCER_CC3NE_Msk               (0x400UL)                 /*!< CC3NE (Bitfield-Mask: 0x01)                           */
#define ATIM_CCER_CC3P_Pos                (9UL)                     /*!< CC3P (Bit 9)                                          */
#define ATIM_CCER_CC3P_Msk                (0x200UL)                 /*!< CC3P (Bitfield-Mask: 0x01)                            */
#define ATIM_CCER_CC3E_Pos                (8UL)                     /*!< CC3E (Bit 8)                                          */
#define ATIM_CCER_CC3E_Msk                (0x100UL)                 /*!< CC3E (Bitfield-Mask: 0x01)                            */
#define ATIM_CCER_CC2NP_Pos               (7UL)                     /*!< CC2NP (Bit 7)                                         */
#define ATIM_CCER_CC2NP_Msk               (0x80UL)                  /*!< CC2NP (Bitfield-Mask: 0x01)                           */
#define ATIM_CCER_CC2NE_Pos               (6UL)                     /*!< CC2NE (Bit 6)                                         */
#define ATIM_CCER_CC2NE_Msk               (0x40UL)                  /*!< CC2NE (Bitfield-Mask: 0x01)                           */
#define ATIM_CCER_CC2P_Pos                (5UL)                     /*!< CC2P (Bit 5)                                          */
#define ATIM_CCER_CC2P_Msk                (0x20UL)                  /*!< CC2P (Bitfield-Mask: 0x01)                            */
#define ATIM_CCER_CC2E_Pos                (4UL)                     /*!< CC2E (Bit 4)                                          */
#define ATIM_CCER_CC2E_Msk                (0x10UL)                  /*!< CC2E (Bitfield-Mask: 0x01)                            */
#define ATIM_CCER_CC1NP_Pos               (3UL)                     /*!< CC1NP (Bit 3)                                         */
#define ATIM_CCER_CC1NP_Msk               (0x8UL)                   /*!< CC1NP (Bitfield-Mask: 0x01)                           */
#define ATIM_CCER_CC1NE_Pos               (2UL)                     /*!< CC1NE (Bit 2)                                         */
#define ATIM_CCER_CC1NE_Msk               (0x4UL)                   /*!< CC1NE (Bitfield-Mask: 0x01)                           */
#define ATIM_CCER_CC1P_Pos                (1UL)                     /*!< CC1P (Bit 1)                                          */
#define ATIM_CCER_CC1P_Msk                (0x2UL)                   /*!< CC1P (Bitfield-Mask: 0x01)                            */
#define ATIM_CCER_CC1E_Pos                (0UL)                     /*!< CC1E (Bit 0)                                          */
#define ATIM_CCER_CC1E_Msk                (0x1UL)                   /*!< CC1E (Bitfield-Mask: 0x01)                            */
/* ==========================================================  CNT  ========================================================== */
#define ATIM_CNT_UIFCPY_Pos               (31UL)                    /*!< UIFCPY (Bit 31)                                       */
#define ATIM_CNT_UIFCPY_Msk               (0x80000000UL)            /*!< UIFCPY (Bitfield-Mask: 0x01)                          */
#define ATIM_CNT_CNT_Pos                  (0UL)                     /*!< CNT (Bit 0)                                           */
#define ATIM_CNT_CNT_Msk                  (0xffffUL)                /*!< CNT (Bitfield-Mask: 0xffff)                           */
/* ==========================================================  PSC  ========================================================== */
#define ATIM_PSC_PSC_Pos                  (0UL)                     /*!< PSC (Bit 0)                                           */
#define ATIM_PSC_PSC_Msk                  (0xffffUL)                /*!< PSC (Bitfield-Mask: 0xffff)                           */
/* ==========================================================  ARR  ========================================================== */
#define ATIM_ARR_ARR_Pos                  (0UL)                     /*!< ARR (Bit 0)                                           */
#define ATIM_ARR_ARR_Msk                  (0xffffUL)                /*!< ARR (Bitfield-Mask: 0xffff)                           */
/* ==========================================================  RCR  ========================================================== */
#define ATIM_RCR_REP_Pos                  (0UL)                     /*!< REP (Bit 0)                                           */
#define ATIM_RCR_REP_Msk                  (0xffffUL)                /*!< REP (Bitfield-Mask: 0xffff)                           */
/* =========================================================  CCR1  ========================================================== */
#define ATIM_CCR1_CCR1_Pos                (0UL)                     /*!< CCR1 (Bit 0)                                          */
#define ATIM_CCR1_CCR1_Msk                (0xffffUL)                /*!< CCR1 (Bitfield-Mask: 0xffff)                          */
/* =========================================================  CCR2  ========================================================== */
#define ATIM_CCR2_CCR2_Pos                (0UL)                     /*!< CCR2 (Bit 0)                                          */
#define ATIM_CCR2_CCR2_Msk                (0xffffUL)                /*!< CCR2 (Bitfield-Mask: 0xffff)                          */
/* =========================================================  CCR3  ========================================================== */
#define ATIM_CCR3_CCR3_Pos                (0UL)                     /*!< CCR3 (Bit 0)                                          */
#define ATIM_CCR3_CCR3_Msk                (0xffffUL)                /*!< CCR3 (Bitfield-Mask: 0xffff)                          */
/* =========================================================  CCR4  ========================================================== */
#define ATIM_CCR4_CCR4_Pos                (0UL)                     /*!< CCR4 (Bit 0)                                          */
#define ATIM_CCR4_CCR4_Msk                (0xffffUL)                /*!< CCR4 (Bitfield-Mask: 0xffff)                          */
/* =========================================================  CCR5  ========================================================== */
#define ATIM_CCR5_GC5C6_Pos               (31UL)                    /*!< GC5C6 (Bit 31)                                        */
#define ATIM_CCR5_GC5C6_Msk               (0x80000000UL)            /*!< GC5C6 (Bitfield-Mask: 0x01)                           */
#define ATIM_CCR5_GC5C5_Pos               (30UL)                    /*!< GC5C5 (Bit 30)                                        */
#define ATIM_CCR5_GC5C5_Msk               (0x40000000UL)            /*!< GC5C5 (Bitfield-Mask: 0x01)                           */
#define ATIM_CCR5_GC5C4_Pos               (29UL)                    /*!< GC5C4 (Bit 29)                                        */
#define ATIM_CCR5_GC5C4_Msk               (0x20000000UL)            /*!< GC5C4 (Bitfield-Mask: 0x01)                           */
#define ATIM_CCR5_GC5C3_Pos               (28UL)                    /*!< GC5C3 (Bit 28)                                        */
#define ATIM_CCR5_GC5C3_Msk               (0x10000000UL)            /*!< GC5C3 (Bitfield-Mask: 0x01)                           */
#define ATIM_CCR5_GC5C2_Pos               (27UL)                    /*!< GC5C2 (Bit 27)                                        */
#define ATIM_CCR5_GC5C2_Msk               (0x8000000UL)             /*!< GC5C2 (Bitfield-Mask: 0x01)                           */
#define ATIM_CCR5_GC5C1_Pos               (26UL)                    /*!< GC5C1 (Bit 26)                                        */
#define ATIM_CCR5_GC5C1_Msk               (0x4000000UL)             /*!< GC5C1 (Bitfield-Mask: 0x01)                           */
#define ATIM_CCR5_CCR5_Pos                (0UL)                     /*!< CCR5 (Bit 0)                                          */
#define ATIM_CCR5_CCR5_Msk                (0xffffUL)                /*!< CCR5 (Bitfield-Mask: 0xffff)                          */
/* =========================================================  CCR6  ========================================================== */
#define ATIM_CCR6_GC6C6_Pos               (31UL)                    /*!< GC6C6 (Bit 31)                                        */
#define ATIM_CCR6_GC6C6_Msk               (0x80000000UL)            /*!< GC6C6 (Bitfield-Mask: 0x01)                           */
#define ATIM_CCR6_GC6C5_Pos               (30UL)                    /*!< GC6C5 (Bit 30)                                        */
#define ATIM_CCR6_GC6C5_Msk               (0x40000000UL)            /*!< GC6C5 (Bitfield-Mask: 0x01)                           */
#define ATIM_CCR6_GC6C4_Pos               (29UL)                    /*!< GC6C4 (Bit 29)                                        */
#define ATIM_CCR6_GC6C4_Msk               (0x20000000UL)            /*!< GC6C4 (Bitfield-Mask: 0x01)                           */
#define ATIM_CCR6_GC6C3_Pos               (28UL)                    /*!< GC6C3 (Bit 28)                                        */
#define ATIM_CCR6_GC6C3_Msk               (0x10000000UL)            /*!< GC6C3 (Bitfield-Mask: 0x01)                           */
#define ATIM_CCR6_GC6C2_Pos               (27UL)                    /*!< GC6C2 (Bit 27)                                        */
#define ATIM_CCR6_GC6C2_Msk               (0x8000000UL)             /*!< GC6C2 (Bitfield-Mask: 0x01)                           */
#define ATIM_CCR6_GC6C1_Pos               (26UL)                    /*!< GC6C1 (Bit 26)                                        */
#define ATIM_CCR6_GC6C1_Msk               (0x4000000UL)             /*!< GC6C1 (Bitfield-Mask: 0x01)                           */
#define ATIM_CCR6_CCR6_Pos                (0UL)                     /*!< CCR6 (Bit 0)                                          */
#define ATIM_CCR6_CCR6_Msk                (0xffffUL)                /*!< CCR6 (Bitfield-Mask: 0xffff)                          */
/* =========================================================  BDTR  ========================================================== */
#define ATIM_BDTR_BK2P_Pos                (25UL)                    /*!< BK2P (Bit 25)                                         */
#define ATIM_BDTR_BK2P_Msk                (0x2000000UL)             /*!< BK2P (Bitfield-Mask: 0x01)                            */
#define ATIM_BDTR_BK2E_Pos                (24UL)                    /*!< BK2E (Bit 24)                                         */
#define ATIM_BDTR_BK2E_Msk                (0x1000000UL)             /*!< BK2E (Bitfield-Mask: 0x01)                            */
#define ATIM_BDTR_BK2F_Pos                (20UL)                    /*!< BK2F (Bit 20)                                         */
#define ATIM_BDTR_BK2F_Msk                (0xf00000UL)              /*!< BK2F (Bitfield-Mask: 0x0f)                            */
#define ATIM_BDTR_BKF_Pos                 (16UL)                    /*!< BKF (Bit 16)                                          */
#define ATIM_BDTR_BKF_Msk                 (0xf0000UL)               /*!< BKF (Bitfield-Mask: 0x0f)                             */
#define ATIM_BDTR_MOE_Pos                 (15UL)                    /*!< MOE (Bit 15)                                          */
#define ATIM_BDTR_MOE_Msk                 (0x8000UL)                /*!< MOE (Bitfield-Mask: 0x01)                             */
#define ATIM_BDTR_AOE_Pos                 (14UL)                    /*!< AOE (Bit 14)                                          */
#define ATIM_BDTR_AOE_Msk                 (0x4000UL)                /*!< AOE (Bitfield-Mask: 0x01)                             */
#define ATIM_BDTR_BKP_Pos                 (13UL)                    /*!< BKP (Bit 13)                                          */
#define ATIM_BDTR_BKP_Msk                 (0x2000UL)                /*!< BKP (Bitfield-Mask: 0x01)                             */
#define ATIM_BDTR_BKE_Pos                 (12UL)                    /*!< BKE (Bit 12)                                          */
#define ATIM_BDTR_BKE_Msk                 (0x1000UL)                /*!< BKE (Bitfield-Mask: 0x01)                             */
#define ATIM_BDTR_OSSR_Pos                (11UL)                    /*!< OSSR (Bit 11)                                         */
#define ATIM_BDTR_OSSR_Msk                (0x800UL)                 /*!< OSSR (Bitfield-Mask: 0x01)                            */
#define ATIM_BDTR_OSSI_Pos                (10UL)                    /*!< OSSI (Bit 10)                                         */
#define ATIM_BDTR_OSSI_Msk                (0x400UL)                 /*!< OSSI (Bitfield-Mask: 0x01)                            */
#define ATIM_BDTR_LOCK_Pos                (8UL)                     /*!< LOCK (Bit 8)                                          */
#define ATIM_BDTR_LOCK_Msk                (0x300UL)                 /*!< LOCK (Bitfield-Mask: 0x03)                            */
#define ATIM_BDTR_DTG_Pos                 (0UL)                     /*!< DTG (Bit 0)                                           */
#define ATIM_BDTR_DTG_Msk                 (0xffUL)                  /*!< DTG (Bitfield-Mask: 0xff)                             */
/* =========================================================  DTR2  ========================================================== */
#define ATIM_DTR2_DTPE_Pos                (17UL)                    /*!< DTPE (Bit 17)                                         */
#define ATIM_DTR2_DTPE_Msk                (0x20000UL)               /*!< DTPE (Bitfield-Mask: 0x01)                            */
#define ATIM_DTR2_DTAE_Pos                (16UL)                    /*!< DTAE (Bit 16)                                         */
#define ATIM_DTR2_DTAE_Msk                (0x10000UL)               /*!< DTAE (Bitfield-Mask: 0x01)                            */
#define ATIM_DTR2_DTGF_Pos                (0UL)                     /*!< DTGF (Bit 0)                                          */
#define ATIM_DTR2_DTGF_Msk                (0xffUL)                  /*!< DTGF (Bitfield-Mask: 0xff)                            */
/* ==========================================================  ECR  ========================================================== */
#define ATIM_ECR_IPOS_Pos                 (6UL)                     /*!< IPOS (Bit 6)                                          */
#define ATIM_ECR_IPOS_Msk                 (0xc0UL)                  /*!< IPOS (Bitfield-Mask: 0x03)                            */
#define ATIM_ECR_FIDX_Pos                 (5UL)                     /*!< FIDX (Bit 5)                                          */
#define ATIM_ECR_FIDX_Msk                 (0x20UL)                  /*!< FIDX (Bitfield-Mask: 0x01)                            */
#define ATIM_ECR_IDIR_Pos                 (1UL)                     /*!< IDIR (Bit 1)                                          */
#define ATIM_ECR_IDIR_Msk                 (0x6UL)                   /*!< IDIR (Bitfield-Mask: 0x03)                            */
#define ATIM_ECR_IE_Pos                   (0UL)                     /*!< IE (Bit 0)                                            */
#define ATIM_ECR_IE_Msk                   (0x1UL)                   /*!< IE (Bitfield-Mask: 0x01)                              */
/* ========================================================  TISEL1  ========================================================= */
#define ATIM_TISEL1_TI4SEL_Pos            (24UL)                    /*!< TI4SEL (Bit 24)                                       */
#define ATIM_TISEL1_TI4SEL_Msk            (0xf000000UL)             /*!< TI4SEL (Bitfield-Mask: 0x0f)                          */
#define ATIM_TISEL1_TI3SEL_Pos            (16UL)                    /*!< TI3SEL (Bit 16)                                       */
#define ATIM_TISEL1_TI3SEL_Msk            (0xf0000UL)               /*!< TI3SEL (Bitfield-Mask: 0x0f)                          */
#define ATIM_TISEL1_TI2SEL_Pos            (8UL)                     /*!< TI2SEL (Bit 8)                                        */
#define ATIM_TISEL1_TI2SEL_Msk            (0xf00UL)                 /*!< TI2SEL (Bitfield-Mask: 0x0f)                          */
#define ATIM_TISEL1_TI1SEL_Pos            (0UL)                     /*!< TI1SEL (Bit 0)                                        */
#define ATIM_TISEL1_TI1SEL_Msk            (0xfUL)                   /*!< TI1SEL (Bitfield-Mask: 0x0f)                          */
/* ========================================================  TISEL2  ========================================================= */
#define ATIM_TISEL2_TI6SEL_Pos            (8UL)                     /*!< TI6SEL (Bit 8)                                        */
#define ATIM_TISEL2_TI6SEL_Msk            (0xf00UL)                 /*!< TI6SEL (Bitfield-Mask: 0x0f)                          */
#define ATIM_TISEL2_TI5SEL_Pos            (0UL)                     /*!< TI5SEL (Bit 0)                                        */
#define ATIM_TISEL2_TI5SEL_Msk            (0xfUL)                   /*!< TI5SEL (Bitfield-Mask: 0x0f)                          */
/* ==========================================================  AF1  ========================================================== */
#define ATIM_AF1_ETRSEL_Pos               (16UL)                    /*!< ETRSEL (Bit 16)                                       */
#define ATIM_AF1_ETRSEL_Msk               (0xf0000UL)               /*!< ETRSEL (Bitfield-Mask: 0x0f)                          */
#define ATIM_AF1_BKVC4P_Pos               (13UL)                    /*!< BKVC4P (Bit 13)                                       */
#define ATIM_AF1_BKVC4P_Msk               (0x2000UL)                /*!< BKVC4P (Bitfield-Mask: 0x01)                          */
#define ATIM_AF1_BKVC3P_Pos               (12UL)                    /*!< BKVC3P (Bit 12)                                       */
#define ATIM_AF1_BKVC3P_Msk               (0x1000UL)                /*!< BKVC3P (Bitfield-Mask: 0x01)                          */
#define ATIM_AF1_BKVC2P_Pos               (11UL)                    /*!< BKVC2P (Bit 11)                                       */
#define ATIM_AF1_BKVC2P_Msk               (0x800UL)                 /*!< BKVC2P (Bitfield-Mask: 0x01)                          */
#define ATIM_AF1_BKVC1P_Pos               (10UL)                    /*!< BKVC1P (Bit 10)                                       */
#define ATIM_AF1_BKVC1P_Msk               (0x400UL)                 /*!< BKVC1P (Bitfield-Mask: 0x01)                          */
#define ATIM_AF1_BKINP_Pos                (9UL)                     /*!< BKINP (Bit 9)                                         */
#define ATIM_AF1_BKINP_Msk                (0x200UL)                 /*!< BKINP (Bitfield-Mask: 0x01)                           */
#define ATIM_AF1_BKVC4E_Pos               (4UL)                     /*!< BKVC4E (Bit 4)                                        */
#define ATIM_AF1_BKVC4E_Msk               (0x10UL)                  /*!< BKVC4E (Bitfield-Mask: 0x01)                          */
#define ATIM_AF1_BKVC3E_Pos               (3UL)                     /*!< BKVC3E (Bit 3)                                        */
#define ATIM_AF1_BKVC3E_Msk               (0x8UL)                   /*!< BKVC3E (Bitfield-Mask: 0x01)                          */
#define ATIM_AF1_BKVC2E_Pos               (2UL)                     /*!< BKVC2E (Bit 2)                                        */
#define ATIM_AF1_BKVC2E_Msk               (0x4UL)                   /*!< BKVC2E (Bitfield-Mask: 0x01)                          */
#define ATIM_AF1_BKVC1E_Pos               (1UL)                     /*!< BKVC1E (Bit 1)                                        */
#define ATIM_AF1_BKVC1E_Msk               (0x2UL)                   /*!< BKVC1E (Bitfield-Mask: 0x01)                          */
#define ATIM_AF1_BKINE_Pos                (0UL)                     /*!< BKINE (Bit 0)                                         */
#define ATIM_AF1_BKINE_Msk                (0x1UL)                   /*!< BKINE (Bitfield-Mask: 0x01)                           */
/* ==========================================================  AF2  ========================================================== */
#define ATIM_AF2_OCRSEL_Pos               (16UL)                    /*!< OCRSEL (Bit 16)                                       */
#define ATIM_AF2_OCRSEL_Msk               (0xf0000UL)               /*!< OCRSEL (Bitfield-Mask: 0x0f)                          */
#define ATIM_AF2_BK2VC4P_Pos              (13UL)                    /*!< BK2VC4P (Bit 13)                                      */
#define ATIM_AF2_BK2VC4P_Msk              (0x2000UL)                /*!< BK2VC4P (Bitfield-Mask: 0x01)                         */
#define ATIM_AF2_BK2VC3P_Pos              (12UL)                    /*!< BK2VC3P (Bit 12)                                      */
#define ATIM_AF2_BK2VC3P_Msk              (0x1000UL)                /*!< BK2VC3P (Bitfield-Mask: 0x01)                         */
#define ATIM_AF2_BK2VC2P_Pos              (11UL)                    /*!< BK2VC2P (Bit 11)                                      */
#define ATIM_AF2_BK2VC2P_Msk              (0x800UL)                 /*!< BK2VC2P (Bitfield-Mask: 0x01)                         */
#define ATIM_AF2_BK2VC1P_Pos              (10UL)                    /*!< BK2VC1P (Bit 10)                                      */
#define ATIM_AF2_BK2VC1P_Msk              (0x400UL)                 /*!< BK2VC1P (Bitfield-Mask: 0x01)                         */
#define ATIM_AF2_BK2INP_Pos               (9UL)                     /*!< BK2INP (Bit 9)                                        */
#define ATIM_AF2_BK2INP_Msk               (0x200UL)                 /*!< BK2INP (Bitfield-Mask: 0x01)                          */
#define ATIM_AF2_BK2VC4E_Pos              (4UL)                     /*!< BK2VC4E (Bit 4)                                       */
#define ATIM_AF2_BK2VC4E_Msk              (0x10UL)                  /*!< BK2VC4E (Bitfield-Mask: 0x01)                         */
#define ATIM_AF2_BK2VC3E_Pos              (3UL)                     /*!< BK2VC3E (Bit 3)                                       */
#define ATIM_AF2_BK2VC3E_Msk              (0x8UL)                   /*!< BK2VC3E (Bitfield-Mask: 0x01)                         */
#define ATIM_AF2_BK2VC2E_Pos              (2UL)                     /*!< BK2VC2E (Bit 2)                                       */
#define ATIM_AF2_BK2VC2E_Msk              (0x4UL)                   /*!< BK2VC2E (Bitfield-Mask: 0x01)                         */
#define ATIM_AF2_BK2VC1E_Pos              (1UL)                     /*!< BK2VC1E (Bit 1)                                       */
#define ATIM_AF2_BK2VC1E_Msk              (0x2UL)                   /*!< BK2VC1E (Bitfield-Mask: 0x01)                         */
#define ATIM_AF2_BK2INE_Pos               (0UL)                     /*!< BK2INE (Bit 0)                                        */
#define ATIM_AF2_BK2INE_Msk               (0x1UL)                   /*!< BK2INE (Bitfield-Mask: 0x01)                          */
/* ==========================================================  ICR  ========================================================== */
#define ATIM_ICR_TERRF_Pos                (23UL)                    /*!< TERRF (Bit 23)                                        */
#define ATIM_ICR_TERRF_Msk                (0x800000UL)              /*!< TERRF (Bitfield-Mask: 0x01)                           */
#define ATIM_ICR_IERRF_Pos                (22UL)                    /*!< IERRF (Bit 22)                                        */
#define ATIM_ICR_IERRF_Msk                (0x400000UL)              /*!< IERRF (Bitfield-Mask: 0x01)                           */
#define ATIM_ICR_DIRF_Pos                 (21UL)                    /*!< DIRF (Bit 21)                                         */
#define ATIM_ICR_DIRF_Msk                 (0x200000UL)              /*!< DIRF (Bitfield-Mask: 0x01)                            */
#define ATIM_ICR_IDXF_Pos                 (20UL)                    /*!< IDXF (Bit 20)                                         */
#define ATIM_ICR_IDXF_Msk                 (0x100000UL)              /*!< IDXF (Bitfield-Mask: 0x01)                            */
#define ATIM_ICR_CC6OF_Pos                (19UL)                    /*!< CC6OF (Bit 19)                                        */
#define ATIM_ICR_CC6OF_Msk                (0x80000UL)               /*!< CC6OF (Bitfield-Mask: 0x01)                           */
#define ATIM_ICR_CC5OF_Pos                (18UL)                    /*!< CC5OF (Bit 18)                                        */
#define ATIM_ICR_CC5OF_Msk                (0x40000UL)               /*!< CC5OF (Bitfield-Mask: 0x01)                           */
#define ATIM_ICR_CC6IF_Pos                (17UL)                    /*!< CC6IF (Bit 17)                                        */
#define ATIM_ICR_CC6IF_Msk                (0x20000UL)               /*!< CC6IF (Bitfield-Mask: 0x01)                           */
#define ATIM_ICR_CC5IF_Pos                (16UL)                    /*!< CC5IF (Bit 16)                                        */
#define ATIM_ICR_CC5IF_Msk                (0x10000UL)               /*!< CC5IF (Bitfield-Mask: 0x01)                           */
#define ATIM_ICR_SBIF_Pos                 (13UL)                    /*!< SBIF (Bit 13)                                         */
#define ATIM_ICR_SBIF_Msk                 (0x2000UL)                /*!< SBIF (Bitfield-Mask: 0x01)                            */
#define ATIM_ICR_CC4OF_Pos                (12UL)                    /*!< CC4OF (Bit 12)                                        */
#define ATIM_ICR_CC4OF_Msk                (0x1000UL)                /*!< CC4OF (Bitfield-Mask: 0x01)                           */
#define ATIM_ICR_CC3OF_Pos                (11UL)                    /*!< CC3OF (Bit 11)                                        */
#define ATIM_ICR_CC3OF_Msk                (0x800UL)                 /*!< CC3OF (Bitfield-Mask: 0x01)                           */
#define ATIM_ICR_CC2OF_Pos                (10UL)                    /*!< CC2OF (Bit 10)                                        */
#define ATIM_ICR_CC2OF_Msk                (0x400UL)                 /*!< CC2OF (Bitfield-Mask: 0x01)                           */
#define ATIM_ICR_CC1OF_Pos                (9UL)                     /*!< CC1OF (Bit 9)                                         */
#define ATIM_ICR_CC1OF_Msk                (0x200UL)                 /*!< CC1OF (Bitfield-Mask: 0x01)                           */
#define ATIM_ICR_B2IF_Pos                 (8UL)                     /*!< B2IF (Bit 8)                                          */
#define ATIM_ICR_B2IF_Msk                 (0x100UL)                 /*!< B2IF (Bitfield-Mask: 0x01)                            */
#define ATIM_ICR_BIF_Pos                  (7UL)                     /*!< BIF (Bit 7)                                           */
#define ATIM_ICR_BIF_Msk                  (0x80UL)                  /*!< BIF (Bitfield-Mask: 0x01)                             */
#define ATIM_ICR_TIF_Pos                  (6UL)                     /*!< TIF (Bit 6)                                           */
#define ATIM_ICR_TIF_Msk                  (0x40UL)                  /*!< TIF (Bitfield-Mask: 0x01)                             */
#define ATIM_ICR_COMIF_Pos                (5UL)                     /*!< COMIF (Bit 5)                                         */
#define ATIM_ICR_COMIF_Msk                (0x20UL)                  /*!< COMIF (Bitfield-Mask: 0x01)                           */
#define ATIM_ICR_CC4IF_Pos                (4UL)                     /*!< CC4IF (Bit 4)                                         */
#define ATIM_ICR_CC4IF_Msk                (0x10UL)                  /*!< CC4IF (Bitfield-Mask: 0x01)                           */
#define ATIM_ICR_CC3IF_Pos                (3UL)                     /*!< CC3IF (Bit 3)                                         */
#define ATIM_ICR_CC3IF_Msk                (0x8UL)                   /*!< CC3IF (Bitfield-Mask: 0x01)                           */
#define ATIM_ICR_CC2IF_Pos                (2UL)                     /*!< CC2IF (Bit 2)                                         */
#define ATIM_ICR_CC2IF_Msk                (0x4UL)                   /*!< CC2IF (Bitfield-Mask: 0x01)                           */
#define ATIM_ICR_CC1IF_Pos                (1UL)                     /*!< CC1IF (Bit 1)                                         */
#define ATIM_ICR_CC1IF_Msk                (0x2UL)                   /*!< CC1IF (Bitfield-Mask: 0x01)                           */
#define ATIM_ICR_UIF_Pos                  (0UL)                     /*!< UIF (Bit 0)                                           */
#define ATIM_ICR_UIF_Msk                  (0x1UL)                   /*!< UIF (Bitfield-Mask: 0x01)                             */


/* =========================================================================================================================== */
/* ================                                            BGR                                            ================ */
/* =========================================================================================================================== */

/* ==========================================================  CR  =========================================================== */
#define BGR_CR_TSEN_Pos                   (1UL)                     /*!< TSEN (Bit 1)                                          */
#define BGR_CR_TSEN_Msk                   (0x2UL)                   /*!< TSEN (Bitfield-Mask: 0x01)                            */
#define BGR_CR_BGREN_Pos                  (0UL)                     /*!< BGREN (Bit 0)                                         */
#define BGR_CR_BGREN_Msk                  (0x1UL)                   /*!< BGREN (Bitfield-Mask: 0x01)                           */


/* =========================================================================================================================== */
/* ================                                           BTIM                                            ================ */
/* =========================================================================================================================== */

/* ==========================================================  CR1  ========================================================== */
#define BTIMx_CR1_TOGEN_Pos               (15UL)                    /*!< TOGEN (Bit 15)                                        */
#define BTIMx_CR1_TOGEN_Msk               (0x8000UL)                /*!< TOGEN (Bitfield-Mask: 0x01)                           */
#define BTIMx_CR1_UIFREMAP_Pos            (11UL)                    /*!< UIFREMAP (Bit 11)                                     */
#define BTIMx_CR1_UIFREMAP_Msk            (0x800UL)                 /*!< UIFREMAP (Bitfield-Mask: 0x01)                        */
#define BTIMx_CR1_ONESHOT_Pos             (3UL)                     /*!< ONESHOT (Bit 3)                                       */
#define BTIMx_CR1_ONESHOT_Msk             (0x8UL)                   /*!< ONESHOT (Bitfield-Mask: 0x01)                         */
#define BTIMx_CR1_URS_Pos                 (2UL)                     /*!< URS (Bit 2)                                           */
#define BTIMx_CR1_URS_Msk                 (0x4UL)                   /*!< URS (Bitfield-Mask: 0x01)                             */
#define BTIMx_CR1_UDIS_Pos                (1UL)                     /*!< UDIS (Bit 1)                                          */
#define BTIMx_CR1_UDIS_Msk                (0x2UL)                   /*!< UDIS (Bitfield-Mask: 0x01)                            */
#define BTIMx_CR1_EN_Pos                  (0UL)                     /*!< EN (Bit 0)                                            */
#define BTIMx_CR1_EN_Msk                  (0x1UL)                   /*!< EN (Bitfield-Mask: 0x01)                              */
/* ==========================================================  CR2  ========================================================== */
#define BTIMx_CR2_MMS_Pos                 (4UL)                     /*!< MMS (Bit 4)                                           */
#define BTIMx_CR2_MMS_Msk                 (0x70UL)                  /*!< MMS (Bitfield-Mask: 0x07)                             */
/* =========================================================  SMCR  ========================================================== */
#define BTIMx_SMCR_TRGIPOL_Pos            (17UL)                    /*!< TRGIPOL (Bit 17)                                      */
#define BTIMx_SMCR_TRGIPOL_Msk            (0x20000UL)               /*!< TRGIPOL (Bitfield-Mask: 0x01)                         */
#define BTIMx_SMCR_RSTIPOL_Pos            (16UL)                    /*!< RSTIPOL (Bit 16)                                      */
#define BTIMx_SMCR_RSTIPOL_Msk            (0x10000UL)               /*!< RSTIPOL (Bitfield-Mask: 0x01)                         */
#define BTIMx_SMCR_TRGIFLT_Pos            (12UL)                    /*!< TRGIFLT (Bit 12)                                      */
#define BTIMx_SMCR_TRGIFLT_Msk            (0x7000UL)                /*!< TRGIFLT (Bitfield-Mask: 0x07)                         */
#define BTIMx_SMCR_MSM_Pos                (11UL)                    /*!< MSM (Bit 11)                                          */
#define BTIMx_SMCR_MSM_Msk                (0x800UL)                 /*!< MSM (Bitfield-Mask: 0x01)                             */
#define BTIMx_SMCR_TRGISRC_Pos            (7UL)                     /*!< TRGISRC (Bit 7)                                       */
#define BTIMx_SMCR_TRGISRC_Msk            (0x780UL)                 /*!< TRGISRC (Bitfield-Mask: 0x0f)                         */
#define BTIMx_SMCR_RSTISRC_Pos            (3UL)                     /*!< RSTISRC (Bit 3)                                       */
#define BTIMx_SMCR_RSTISRC_Msk            (0x78UL)                  /*!< RSTISRC (Bitfield-Mask: 0x0f)                         */
#define BTIMx_SMCR_SMS_Pos                (0UL)                     /*!< SMS (Bit 0)                                           */
#define BTIMx_SMCR_SMS_Msk                (0x7UL)                   /*!< SMS (Bitfield-Mask: 0x07)                             */
/* =========================================================  DIER  ========================================================== */
#define BTIMx_DIER_TDE_Pos                 (14UL)                   /*!< TDE (Bit 14)                                          */
#define BTIMx_DIER_TDE_Msk                 (0x4000UL)               /*!< TDE (Bitfield-Mask: 0x01)                             */
#define BTIMx_DIER_UDE_Pos                 (8UL)                    /*!< UDE (Bit 8)                                           */
#define BTIMx_DIER_UDE_Msk                 (0x100UL)                /*!< UDE (Bitfield-Mask: 0x01)                             */
#define BTIMx_DIER_TIE_Pos                 (6UL)                    /*!< TIE (Bit 6)                                           */
#define BTIMx_DIER_TIE_Msk                 (0x40UL)                 /*!< TIE (Bitfield-Mask: 0x01)                             */
#define BTIMx_DIER_UIE_Pos                 (0UL)                    /*!< UIE (Bit 0)                                           */
#define BTIMx_DIER_UIE_Msk                 (0x1UL)                  /*!< UIE (Bitfield-Mask: 0x01)                             */
/* ==========================================================  ISR  ========================================================== */
#define BTIMx_ISR_TIF_Pos                 (6UL)                     /*!< TIF (Bit 6)                                           */
#define BTIMx_ISR_TIF_Msk                 (0x40UL)                  /*!< TIF (Bitfield-Mask: 0x01)                             */
#define BTIMx_ISR_UIF_Pos                 (0UL)                     /*!< UIF (Bit 0)                                           */
#define BTIMx_ISR_UIF_Msk                 (0x1UL)                   /*!< UIF (Bitfield-Mask: 0x01)                             */
/* ==========================================================  ICR  ========================================================== */
#define BTIMx_ICR_TIF_Pos                 (6UL)                     /*!< TIF (Bit 6)                                           */
#define BTIMx_ICR_TIF_Msk                 (0x40UL)                  /*!< TIF (Bitfield-Mask: 0x01)                             */
#define BTIMx_ICR_UIF_Pos                 (0UL)                     /*!< UIF (Bit 0)                                           */
#define BTIMx_ICR_UIF_Msk                 (0x1UL)                   /*!< UIF (Bitfield-Mask: 0x01)                             */
/* ==========================================================  EGR  ========================================================== */
#define BTIMx_EGR_TG_Pos                  (6UL)                     /*!< TG (Bit 6)                                            */
#define BTIMx_EGR_TG_Msk                  (0x40UL)                  /*!< TG (Bitfield-Mask: 0x01)                              */
#define BTIMx_EGR_UG_Pos                  (0UL)                     /*!< UG (Bit 0)                                            */
#define BTIMx_EGR_UG_Msk                  (0x1UL)                   /*!< UG (Bitfield-Mask: 0x01)                              */
/* ==========================================================  CNT  ========================================================== */
#define BTIMx_CNT_UIFCPY_Pos              (31UL)                    /*!< UIFCPY (Bit 31)                                       */
#define BTIMx_CNT_UIFCPY_Msk              (0x80000000UL)            /*!< UIFCPY (Bitfield-Mask: 0x01)                          */
#define BTIMx_CNT_CNT_Pos                 (0UL)                     /*!< CNT (Bit 0)                                           */
#define BTIMx_CNT_CNT_Msk                 (0xffffUL)                /*!< CNT (Bitfield-Mask: 0xffff)                           */
/* ==========================================================  PSC  ========================================================== */
#define BTIMx_PSC_PSC_Pos                 (0UL)                     /*!< PSC (Bit 0)                                           */
#define BTIMx_PSC_PSC_Msk                 (0xffffUL)                /*!< PSC (Bitfield-Mask: 0xffff)                           */
/* ==========================================================  ARR  ========================================================== */
#define BTIMx_ARR_ARR_Pos                 (0UL)                     /*!< ARR (Bit 0)                                           */
#define BTIMx_ARR_ARR_Msk                 (0xffffUL)                /*!< ARR (Bitfield-Mask: 0xffff)                           */


/* =========================================================================================================================== */
/* ================                                          CORDIC                                           ================ */
/* =========================================================================================================================== */

/* ==========================================================  CSR  ========================================================== */
#define CORDIC_CSR_BUSY_Pos               (17UL)                    /*!< BUSY (Bit 17)                                         */
#define CORDIC_CSR_BUSY_Msk               (0x20000UL)               /*!< BUSY (Bitfield-Mask: 0x01)                            */
#define CORDIC_CSR_EOC_Pos                (16UL)                    /*!< EOC (Bit 16)                                          */
#define CORDIC_CSR_EOC_Msk                (0x10000UL)               /*!< EOC (Bitfield-Mask: 0x01)                             */
#define CORDIC_CSR_DMAIDLE_Pos            (15UL)                    /*!< DMAIDLE (Bit 15)                                      */
#define CORDIC_CSR_DMAIDLE_Msk            (0x8000UL)                /*!< DMAIDLE (Bitfield-Mask: 0x01)                         */
#define CORDIC_CSR_DMAEOC_Pos             (14UL)                    /*!< DMAEOC (Bit 14)                                       */
#define CORDIC_CSR_DMAEOC_Msk             (0x4000UL)                /*!< DMAEOC (Bitfield-Mask: 0x01)                          */
#define CORDIC_CSR_IE_Pos                 (13UL)                    /*!< IE (Bit 13)                                           */
#define CORDIC_CSR_IE_Msk                 (0x2000UL)                /*!< IE (Bitfield-Mask: 0x01)                              */
#define CORDIC_CSR_COMP_Pos               (12UL)                    /*!< COMP (Bit 12)                                         */
#define CORDIC_CSR_COMP_Msk               (0x1000UL)                /*!< COMP (Bitfield-Mask: 0x01)                            */
#define CORDIC_CSR_ITER_Pos               (8UL)                     /*!< ITER (Bit 8)                                          */
#define CORDIC_CSR_ITER_Msk               (0xf00UL)                 /*!< ITER (Bitfield-Mask: 0x0f)                            */
#define CORDIC_CSR_FORMAT_Pos             (7UL)                     /*!< SIZE (Bit 7)                                          */
#define CORDIC_CSR_FORMAT_Msk             (0x80UL)                  /*!< SIZE (Bitfield-Mask: 0x01)                            */
#define CORDIC_CSR_SCALE_Pos              (4UL)                     /*!< SCALE (Bit 4)                                         */
#define CORDIC_CSR_SCALE_Msk              (0x70UL)                  /*!< SCALE (Bitfield-Mask: 0x07)                           */
#define CORDIC_CSR_FUNC_Pos               (0UL)                     /*!< FUNC (Bit 0)                                          */
#define CORDIC_CSR_FUNC_Msk               (0xfUL)                   /*!< FUNC (Bitfield-Mask: 0x0f)                            */
/* ==========================================================  DRX  ========================================================== */
#define CORDIC_X_X_Pos                    (0UL)                     /*!< DATA (Bit 0)                                          */
#define CORDIC_X_X_Msk                    (0xffffffffUL)            /*!< DATA (Bitfield-Mask: 0xffffffff)                      */
/* ==========================================================  DRY  ========================================================== */
#define CORDIC_Y_Y_Pos                    (0UL)                     /*!< DATA (Bit 0)                                          */
#define CORDIC_Y_Y_Msk                    (0xffffffffUL)            /*!< DATA (Bitfield-Mask: 0xffffffff)                      */
/* ==========================================================  DRZ  ========================================================== */
#define CORDIC_Z_Z_Pos                    (0UL)                     /*!< DATA (Bit 0)                                          */
#define CORDIC_Z_Z_Msk                    (0xffffffffUL)            /*!< DATA (Bitfield-Mask: 0xffffffff)                      */


/* =========================================================================================================================== */
/* ================                                            CRC                                            ================ */
/* =========================================================================================================================== */

/* ==========================================================  CR  =========================================================== */
#define CRC_CR_MODE_Pos                   (0UL)                     /*!< MODE (Bit 0)                                          */
#define CRC_CR_MODE_Msk                   (0xfUL)                   /*!< MODE (Bitfield-Mask: 0x0f)                            */
/* ==========================================================  DR  =========================================================== */
#define CRC_DR_DR_Pos                     (0UL)                     /*!< DR (Bit 0)                                            */
#define CRC_DR_DR_Msk                     (0xffUL)                  /*!< DR (Bitfield-Mask: 0xff)                              */
/* ========================================================  RESULT  ========================================================= */
#define CRC_RESULT_RESULT_Pos             (0UL)                     /*!< RESULT (Bit 0)                                        */
#define CRC_RESULT_RESULT_Msk             (0xffffUL)                /*!< RESULT (Bitfield-Mask: 0xffff)                        */


/* =========================================================================================================================== */
/* ================                                            DAC                                            ================ */
/* =========================================================================================================================== */

/* ==========================================================  CR0  ========================================================== */
#define DAC_CR0_DMAUDRIE2_Pos             (29UL)                    /*!< DMAUDRIE2 (Bit 29)                                    */
#define DAC_CR0_DMAUDRIE2_Msk             (0x20000000UL)            /*!< DMAUDRIE2 (Bitfield-Mask: 0x01)                       */
#define DAC_CR0_DMAEN2_Pos                (28UL)                    /*!< DMAEN2 (Bit 28)                                       */
#define DAC_CR0_DMAEN2_Msk                (0x10000000UL)            /*!< DMAEN2 (Bitfield-Mask: 0x01)                          */
#define DAC_CR0_MAMP2_Pos                 (24UL)                    /*!< MAMP2 (Bit 24)                                        */
#define DAC_CR0_MAMP2_Msk                 (0xf000000UL)             /*!< MAMP2 (Bitfield-Mask: 0x0f)                           */
#define DAC_CR0_WAVE2_Pos                 (22UL)                    /*!< WAVE2 (Bit 22)                                        */
#define DAC_CR0_WAVE2_Msk                 (0xc00000UL)              /*!< WAVE2 (Bitfield-Mask: 0x03)                           */
#define DAC_CR0_TSEL2_Pos                 (18UL)                    /*!< TSEL2 (Bit 18)                                        */
#define DAC_CR0_TSEL2_Msk                 (0x3c0000UL)              /*!< TSEL2 (Bitfield-Mask: 0x0f)                           */
#define DAC_CR0_TEN2_Pos                  (17UL)                    /*!< TEN2 (Bit 17)                                         */
#define DAC_CR0_TEN2_Msk                  (0x20000UL)               /*!< TEN2 (Bitfield-Mask: 0x01)                            */
#define DAC_CR0_EN2_Pos                   (16UL)                    /*!< EN2 (Bit 16)                                          */
#define DAC_CR0_EN2_Msk                   (0x10000UL)               /*!< EN2 (Bitfield-Mask: 0x01)                             */
#define DAC_CR0_DMAUDRIE1_Pos             (13UL)                    /*!< DMAUDRIE1 (Bit 13)                                    */
#define DAC_CR0_DMAUDRIE1_Msk             (0x2000UL)                /*!< DMAUDRIE1 (Bitfield-Mask: 0x01)                       */
#define DAC_CR0_DMAEN1_Pos                (12UL)                    /*!< DMAEN1 (Bit 12)                                       */
#define DAC_CR0_DMAEN1_Msk                (0x1000UL)                /*!< DMAEN1 (Bitfield-Mask: 0x01)                          */
#define DAC_CR0_MAMP1_Pos                 (8UL)                     /*!< MAMP1 (Bit 8)                                         */
#define DAC_CR0_MAMP1_Msk                 (0xf00UL)                 /*!< MAMP1 (Bitfield-Mask: 0x0f)                           */
#define DAC_CR0_WAVE1_Pos                 (6UL)                     /*!< WAVE1 (Bit 6)                                         */
#define DAC_CR0_WAVE1_Msk                 (0xc0UL)                  /*!< WAVE1 (Bitfield-Mask: 0x03)                           */
#define DAC_CR0_TSEL1_Pos                 (2UL)                     /*!< TSEL1 (Bit 2)                                         */
#define DAC_CR0_TSEL1_Msk                 (0x3cUL)                  /*!< TSEL1 (Bitfield-Mask: 0x0f)                           */
#define DAC_CR0_TEN1_Pos                  (1UL)                     /*!< TEN1 (Bit 1)                                          */
#define DAC_CR0_TEN1_Msk                  (0x2UL)                   /*!< TEN1 (Bitfield-Mask: 0x01)                            */
#define DAC_CR0_EN1_Pos                   (0UL)                     /*!< EN1 (Bit 0)                                           */
#define DAC_CR0_EN1_Msk                   (0x1UL)                   /*!< EN1 (Bitfield-Mask: 0x01)                             */
/* ========================================================  SWTRGR  ========================================================= */
#define DAC_SWTRGR_SWTRIG2_Pos            (1UL)                     /*!< SWTRIG2 (Bit 1)                                       */
#define DAC_SWTRGR_SWTRIG2_Msk            (0x2UL)                   /*!< SWTRIG2 (Bitfield-Mask: 0x01)                         */
#define DAC_SWTRGR_SWTRIG1_Pos            (0UL)                     /*!< SWTRIG1 (Bit 0)                                       */
#define DAC_SWTRGR_SWTRIG1_Msk            (0x1UL)                   /*!< SWTRIG1 (Bitfield-Mask: 0x01)                         */
/* ========================================================  DHR12R1  ======================================================== */
#define DAC_DHR12R1_DATA_Pos              (0UL)                     /*!< DATA (Bit 0)                                          */
#define DAC_DHR12R1_DATA_Msk              (0xfffUL)                 /*!< DATA (Bitfield-Mask: 0xfff)                           */
/* ========================================================  DHR12L1  ======================================================== */
#define DAC_DHR12L1_DATA_Pos              (4UL)                     /*!< DATA (Bit 4)                                          */
#define DAC_DHR12L1_DATA_Msk              (0xfff0UL)                /*!< DATA (Bitfield-Mask: 0xfff)                           */
/* ========================================================  DHR8R1  ========================================================= */
#define DAC_DHR8R1_DATA_Pos               (4UL)                     /*!< DATA (Bit 4)                                          */
#define DAC_DHR8R1_DATA_Msk               (0xf0UL)                  /*!< DATA (Bitfield-Mask: 0x0f)                            */
/* ========================================================  DHR12R2  ======================================================== */
#define DAC_DHR12R2_DATA_Pos              (0UL)                     /*!< DATA (Bit 0)                                          */
#define DAC_DHR12R2_DATA_Msk              (0xfffUL)                 /*!< DATA (Bitfield-Mask: 0xfff)                           */
/* ========================================================  DHR12L2  ======================================================== */
#define DAC_DHR12L2_DATA_Pos              (4UL)                     /*!< DATA (Bit 4)                                          */
#define DAC_DHR12L2_DATA_Msk              (0xfff0UL)                /*!< DATA (Bitfield-Mask: 0xfff)                           */
/* ========================================================  DHR8R2  ========================================================= */
#define DAC_DHR8R2_DATA_Pos               (4UL)                     /*!< DATA (Bit 4)                                          */
#define DAC_DHR8R2_DATA_Msk               (0xf0UL)                  /*!< DATA (Bitfield-Mask: 0x0f)                            */
/* ========================================================  DHR12RD  ======================================================== */
#define DAC_DHR12RD_C2DATA_Pos            (16UL)                    /*!< C2DATA (Bit 16)                                       */
#define DAC_DHR12RD_C2DATA_Msk            (0xfff0000UL)             /*!< C2DATA (Bitfield-Mask: 0xfff)                         */
#define DAC_DHR12RD_C1DATA_Pos            (0UL)                     /*!< C1DATA (Bit 0)                                        */
#define DAC_DHR12RD_C1DATA_Msk            (0xfffUL)                 /*!< C1DATA (Bitfield-Mask: 0xfff)                         */
/* ========================================================  DHR12LD  ======================================================== */
#define DAC_DHR12LD_C2DATA_Pos            (20UL)                    /*!< C2DATA (Bit 20)                                       */
#define DAC_DHR12LD_C2DATA_Msk            (0xfff00000UL)            /*!< C2DATA (Bitfield-Mask: 0xfff)                         */
#define DAC_DHR12LD_C1DATA_Pos            (4UL)                     /*!< C1DATA (Bit 4)                                        */
#define DAC_DHR12LD_C1DATA_Msk            (0xfff0UL)                /*!< C1DATA (Bitfield-Mask: 0xfff)                         */
/* ========================================================  DHR8RD  ========================================================= */
#define DAC_DHR8RD_C2DATA_Pos             (8UL)                     /*!< C2DATA (Bit 8)                                        */
#define DAC_DHR8RD_C2DATA_Msk             (0xff00UL)                /*!< C2DATA (Bitfield-Mask: 0xff)                          */
#define DAC_DHR8RD_C1DATA_Pos             (0UL)                     /*!< C1DATA (Bit 0)                                        */
#define DAC_DHR8RD_C1DATA_Msk             (0xffUL)                  /*!< C1DATA (Bitfield-Mask: 0xff)                          */
/* =========================================================  DOR1  ========================================================== */
#define DAC_DOR1_DMAUDR_Pos               (15UL)                    /*!< DMAUDR (Bit 15)                                       */
#define DAC_DOR1_DMAUDR_Msk               (0x8000UL)                /*!< DMAUDR (Bitfield-Mask: 0x01)                          */
#define DAC_DOR1_DATA_Pos                 (0UL)                     /*!< DATA (Bit 0)                                          */
#define DAC_DOR1_DATA_Msk                 (0xfffUL)                 /*!< DATA (Bitfield-Mask: 0xfff)                           */
/* =========================================================  DOR2  ========================================================== */
#define DAC_DOR2_DMAUDR_Pos               (15UL)                    /*!< DMAUDR (Bit 15)                                       */
#define DAC_DOR2_DMAUDR_Msk               (0x8000UL)                /*!< DMAUDR (Bitfield-Mask: 0x01)                          */
#define DAC_DOR2_DATA_Pos                 (0UL)                     /*!< DATA (Bit 0)                                          */
#define DAC_DOR2_DATA_Msk                 (0xfffUL)                 /*!< DATA (Bitfield-Mask: 0xfff)                           */
/* ==========================================================  CR1  ========================================================== */
#define DAC_CR1_C2OUT_Pos                 (1UL)                     /*!< C2OUT (Bit 1)                                         */
#define DAC_CR1_C2OUT_Msk                 (0x2UL)                   /*!< C2OUT (Bitfield-Mask: 0x01)                           */
#define DAC_CR1_C1OUT_Pos                 (0UL)                     /*!< C1OUT (Bit 0)                                         */
#define DAC_CR1_C1OUT_Msk                 (0x1UL)                   /*!< C1OUT (Bitfield-Mask: 0x01)                           */


/* =========================================================================================================================== */
/* ================                                            DMA                                            ================ */
/* =========================================================================================================================== */

/* ==========================================================  ISR  ========================================================== */
#define DMA_ISR_TE4_Pos                   (13UL)                    /*!< TE4 (Bit 13)                                          */
#define DMA_ISR_TE4_Msk                   (0x2000UL)                /*!< TE4 (Bitfield-Mask: 0x01)                             */
#define DMA_ISR_TC4_Pos                   (12UL)                    /*!< TC4 (Bit 12)                                          */
#define DMA_ISR_TC4_Msk                   (0x1000UL)                /*!< TC4 (Bitfield-Mask: 0x01)                             */
#define DMA_ISR_TE3_Pos                   (9UL)                     /*!< TE3 (Bit 9)                                           */
#define DMA_ISR_TE3_Msk                   (0x200UL)                 /*!< TE3 (Bitfield-Mask: 0x01)                             */
#define DMA_ISR_TC3_Pos                   (8UL)                     /*!< TC3 (Bit 8)                                           */
#define DMA_ISR_TC3_Msk                   (0x100UL)                 /*!< TC3 (Bitfield-Mask: 0x01)                             */
#define DMA_ISR_TE2_Pos                   (5UL)                     /*!< TE2 (Bit 5)                                           */
#define DMA_ISR_TE2_Msk                   (0x20UL)                  /*!< TE2 (Bitfield-Mask: 0x01)                             */
#define DMA_ISR_TC2_Pos                   (4UL)                     /*!< TC2 (Bit 4)                                           */
#define DMA_ISR_TC2_Msk                   (0x10UL)                  /*!< TC2 (Bitfield-Mask: 0x01)                             */
#define DMA_ISR_TE1_Pos                   (1UL)                     /*!< TE1 (Bit 1)                                           */
#define DMA_ISR_TE1_Msk                   (0x2UL)                   /*!< TE1 (Bitfield-Mask: 0x01)                             */
#define DMA_ISR_TC1_Pos                   (0UL)                     /*!< TC1 (Bit 0)                                           */
#define DMA_ISR_TC1_Msk                   (0x1UL)                   /*!< TC1 (Bitfield-Mask: 0x01)                             */
/* ==========================================================  ICR  ========================================================== */
#define DMA_ICR_TE4_Pos                   (13UL)                    /*!< TE4 (Bit 13)                                          */
#define DMA_ICR_TE4_Msk                   (0x2000UL)                /*!< TE4 (Bitfield-Mask: 0x01)                             */
#define DMA_ICR_TC4_Pos                   (12UL)                    /*!< TC4 (Bit 12)                                          */
#define DMA_ICR_TC4_Msk                   (0x1000UL)                /*!< TC4 (Bitfield-Mask: 0x01)                             */
#define DMA_ICR_TE3_Pos                   (9UL)                     /*!< TE3 (Bit 9)                                           */
#define DMA_ICR_TE3_Msk                   (0x200UL)                 /*!< TE3 (Bitfield-Mask: 0x01)                             */
#define DMA_ICR_TC3_Pos                   (8UL)                     /*!< TC3 (Bit 8)                                           */
#define DMA_ICR_TC3_Msk                   (0x100UL)                 /*!< TC3 (Bitfield-Mask: 0x01)                             */
#define DMA_ICR_TE2_Pos                   (5UL)                     /*!< TE2 (Bit 5)                                           */
#define DMA_ICR_TE2_Msk                   (0x20UL)                  /*!< TE2 (Bitfield-Mask: 0x01)                             */
#define DMA_ICR_TC2_Pos                   (4UL)                     /*!< TC2 (Bit 4)                                           */
#define DMA_ICR_TC2_Msk                   (0x10UL)                  /*!< TC2 (Bitfield-Mask: 0x01)                             */
#define DMA_ICR_TE1_Pos                   (1UL)                     /*!< TE1 (Bit 1)                                           */
#define DMA_ICR_TE1_Msk                   (0x2UL)                   /*!< TE1 (Bitfield-Mask: 0x01)                             */
#define DMA_ICR_TC1_Pos                   (0UL)                     /*!< TC1 (Bit 0)                                           */
#define DMA_ICR_TC1_Msk                   (0x1UL)                   /*!< TC1 (Bitfield-Mask: 0x01)                             */
/* =========================================================  CSR1  ========================================================== */
#define DMA_CSR1_DSTLOAD_Pos              (15UL)                    /*!< DSTLOAD (Bit 15)                                      */
#define DMA_CSR1_DSTLOAD_Msk              (0x8000UL)                /*!< DSTLOAD (Bitfield-Mask: 0x01)                         */
#define DMA_CSR1_SRCLOAD_Pos              (14UL)                    /*!< SRCLOAD (Bit 14)                                      */
#define DMA_CSR1_SRCLOAD_Msk              (0x4000UL)                /*!< SRCLOAD (Bitfield-Mask: 0x01)                         */
#define DMA_CSR1_TE_Pos                   (13UL)                    /*!< TE (Bit 13)                                           */
#define DMA_CSR1_TE_Msk                   (0x2000UL)                /*!< TE (Bitfield-Mask: 0x01)                              */
#define DMA_CSR1_TC_Pos                   (12UL)                    /*!< TC (Bit 12)                                           */
#define DMA_CSR1_TC_Msk                   (0x1000UL)                /*!< TC (Bitfield-Mask: 0x01)                              */
#define DMA_CSR1_RESTART_Pos              (11UL)                    /*!< RESTART (Bit 11)                                      */
#define DMA_CSR1_RESTART_Msk              (0x800UL)                 /*!< RESTART (Bitfield-Mask: 0x01)                         */
#define DMA_CSR1_STATUS_Pos               (8UL)                     /*!< STATUS (Bit 8)                                        */
#define DMA_CSR1_STATUS_Msk               (0x700UL)                 /*!< STATUS (Bitfield-Mask: 0x07)                          */
#define DMA_CSR1_SIZE_Pos                 (6UL)                     /*!< SIZE (Bit 6)                                          */
#define DMA_CSR1_SIZE_Msk                 (0xc0UL)                  /*!< SIZE (Bitfield-Mask: 0x03)                            */
#define DMA_CSR1_DSTINC_Pos               (5UL)                     /*!< DSTINC (Bit 5)                                        */
#define DMA_CSR1_DSTINC_Msk               (0x20UL)                  /*!< DSTINC (Bitfield-Mask: 0x01)                          */
#define DMA_CSR1_SRCINC_Pos               (4UL)                     /*!< SRCINC (Bit 4)                                        */
#define DMA_CSR1_SRCINC_Msk               (0x10UL)                  /*!< SRCINC (Bitfield-Mask: 0x01)                          */
#define DMA_CSR1_TRANS_Pos                (3UL)                     /*!< TRANS (Bit 3)                                         */
#define DMA_CSR1_TRANS_Msk                (0x8UL)                   /*!< TRANS (Bitfield-Mask: 0x01)                           */
#define DMA_CSR1_TEIE_Pos                 (2UL)                     /*!< TEIE (Bit 2)                                          */
#define DMA_CSR1_TEIE_Msk                 (0x4UL)                   /*!< TEIE (Bitfield-Mask: 0x01)                            */
#define DMA_CSR1_TCIE_Pos                 (1UL)                     /*!< TCIE (Bit 1)                                          */
#define DMA_CSR1_TCIE_Msk                 (0x2UL)                   /*!< TCIE (Bitfield-Mask: 0x01)                            */
#define DMA_CSR1_EN_Pos                   (0UL)                     /*!< EN (Bit 0)                                            */
#define DMA_CSR1_EN_Msk                   (0x1UL)                   /*!< EN (Bitfield-Mask: 0x01)                              */
/* =========================================================  TRIG1  ========================================================= */
#define DMA_TRIG1_HARDSRC_Pos             (2UL)                     /*!< HARDSRC (Bit 2)                                       */
#define DMA_TRIG1_HARDSRC_Msk             (0xfcUL)                  /*!< HARDSRC (Bitfield-Mask: 0x3f)                         */
#define DMA_TRIG1_SOFTSRC_Pos             (1UL)                     /*!< SOFTSRC (Bit 1)                                       */
#define DMA_TRIG1_SOFTSRC_Msk             (0x2UL)                   /*!< SOFTSRC (Bitfield-Mask: 0x01)                         */
#define DMA_TRIG1_TYPE_Pos                (0UL)                     /*!< TYPE (Bit 0)                                          */
#define DMA_TRIG1_TYPE_Msk                (0x1UL)                   /*!< TYPE (Bitfield-Mask: 0x01)                            */
/* =========================================================  CNT1  ========================================================== */
#define DMA_CNT1_REPEAT_Pos               (16UL)                    /*!< REPEAT (Bit 16)                                       */
#define DMA_CNT1_REPEAT_Msk               (0xf0000UL)               /*!< REPEAT (Bitfield-Mask: 0x0f)                          */
#define DMA_CNT1_CNT_Pos                  (0UL)                     /*!< CNT (Bit 0)                                           */
#define DMA_CNT1_CNT_Msk                  (0xffffUL)                /*!< CNT (Bitfield-Mask: 0xffff)                           */
/* =======================================================  SRCADDR1  ======================================================== */
#define DMA_SRCADDR1_SRCADDR_Pos          (0UL)                     /*!< SRCADDR (Bit 0)                                       */
#define DMA_SRCADDR1_SRCADDR_Msk          (0xffffffffUL)            /*!< SRCADDR (Bitfield-Mask: 0xffffffff)                   */
/* =======================================================  DSTADDR1  ======================================================== */
#define DMA_DSTADDR1_DSTADDR_Pos          (0UL)                     /*!< DSTADDR (Bit 0)                                       */
#define DMA_DSTADDR1_DSTADDR_Msk          (0xffffffffUL)            /*!< DSTADDR (Bitfield-Mask: 0xffffffff)                   */
/* =========================================================  CCNT1  ========================================================= */
#define DMA_CCNT1_CREPEAT_Pos             (16UL)                    /*!< CREPEAT (Bit 16)                                      */
#define DMA_CCNT1_CREPEAT_Msk             (0xf0000UL)               /*!< CREPEAT (Bitfield-Mask: 0x0f)                         */
#define DMA_CCNT1_CCNT_Pos                (0UL)                     /*!< CCNT (Bit 0)                                          */
#define DMA_CCNT1_CCNT_Msk                (0xffffUL)                /*!< CCNT (Bitfield-Mask: 0xffff)                          */
/* =======================================================  CSRCADDR1  ======================================================= */
#define DMA_CSRCADDR1_CSRCADDR_Pos        (0UL)                     /*!< CSRCADDR (Bit 0)                                      */
#define DMA_CSRCADDR1_CSRCADDR_Msk        (0xffffffffUL)            /*!< CSRCADDR (Bitfield-Mask: 0xffffffff)                  */
/* =======================================================  CDSTADDR1  ======================================================= */
#define DMA_CDSTADDR1_CDSTADDR_Pos        (0UL)                     /*!< CDSTADDR (Bit 0)                                      */
#define DMA_CDSTADDR1_CDSTADDR_Msk        (0xffffffffUL)            /*!< CDSTADDR (Bitfield-Mask: 0xffffffff)                  */
/* =========================================================  CSR2  ========================================================== */
#define DMA_CSR2_DSTLOAD_Pos              (15UL)                    /*!< DSTLOAD (Bit 15)                                      */
#define DMA_CSR2_DSTLOAD_Msk              (0x8000UL)                /*!< DSTLOAD (Bitfield-Mask: 0x01)                         */
#define DMA_CSR2_SRCLOAD_Pos              (14UL)                    /*!< SRCLOAD (Bit 14)                                      */
#define DMA_CSR2_SRCLOAD_Msk              (0x4000UL)                /*!< SRCLOAD (Bitfield-Mask: 0x01)                         */
#define DMA_CSR2_TE_Pos                   (13UL)                    /*!< TE (Bit 13)                                           */
#define DMA_CSR2_TE_Msk                   (0x2000UL)                /*!< TE (Bitfield-Mask: 0x01)                              */
#define DMA_CSR2_TC_Pos                   (12UL)                    /*!< TC (Bit 12)                                           */
#define DMA_CSR2_TC_Msk                   (0x1000UL)                /*!< TC (Bitfield-Mask: 0x01)                              */
#define DMA_CSR2_RESTART_Pos              (11UL)                    /*!< RESTART (Bit 11)                                      */
#define DMA_CSR2_RESTART_Msk              (0x800UL)                 /*!< RESTART (Bitfield-Mask: 0x01)                         */
#define DMA_CSR2_STATUS_Pos               (8UL)                     /*!< STATUS (Bit 8)                                        */
#define DMA_CSR2_STATUS_Msk               (0x700UL)                 /*!< STATUS (Bitfield-Mask: 0x07)                          */
#define DMA_CSR2_SIZE_Pos                 (6UL)                     /*!< SIZE (Bit 6)                                          */
#define DMA_CSR2_SIZE_Msk                 (0xc0UL)                  /*!< SIZE (Bitfield-Mask: 0x03)                            */
#define DMA_CSR2_DSTINC_Pos               (5UL)                     /*!< DSTINC (Bit 5)                                        */
#define DMA_CSR2_DSTINC_Msk               (0x20UL)                  /*!< DSTINC (Bitfield-Mask: 0x01)                          */
#define DMA_CSR2_SRCINC_Pos               (4UL)                     /*!< SRCINC (Bit 4)                                        */
#define DMA_CSR2_SRCINC_Msk               (0x10UL)                  /*!< SRCINC (Bitfield-Mask: 0x01)                          */
#define DMA_CSR2_TRANS_Pos                (3UL)                     /*!< TRANS (Bit 3)                                         */
#define DMA_CSR2_TRANS_Msk                (0x8UL)                   /*!< TRANS (Bitfield-Mask: 0x01)                           */
#define DMA_CSR2_TEIE_Pos                 (2UL)                     /*!< TEIE (Bit 2)                                          */
#define DMA_CSR2_TEIE_Msk                 (0x4UL)                   /*!< TEIE (Bitfield-Mask: 0x01)                            */
#define DMA_CSR2_TCIE_Pos                 (1UL)                     /*!< TCIE (Bit 1)                                          */
#define DMA_CSR2_TCIE_Msk                 (0x2UL)                   /*!< TCIE (Bitfield-Mask: 0x01)                            */
#define DMA_CSR2_EN_Pos                   (0UL)                     /*!< EN (Bit 0)                                            */
#define DMA_CSR2_EN_Msk                   (0x1UL)                   /*!< EN (Bitfield-Mask: 0x01)                              */
/* =========================================================  CNT2  ========================================================== */
#define DMA_CNT2_REPEAT_Pos               (16UL)                    /*!< REPEAT (Bit 16)                                       */
#define DMA_CNT2_REPEAT_Msk               (0xf0000UL)               /*!< REPEAT (Bitfield-Mask: 0x0f)                          */
#define DMA_CNT2_CNT_Pos                  (0UL)                     /*!< CNT (Bit 0)                                           */
#define DMA_CNT2_CNT_Msk                  (0xffffUL)                /*!< CNT (Bitfield-Mask: 0xffff)                           */
/* =======================================================  SRCADDR2  ======================================================== */
#define DMA_SRCADDR2_SRCADDR_Pos          (0UL)                     /*!< SRCADDR (Bit 0)                                       */
#define DMA_SRCADDR2_SRCADDR_Msk          (0xffffffffUL)            /*!< SRCADDR (Bitfield-Mask: 0xffffffff)                   */
/* =======================================================  DSTADDR2  ======================================================== */
#define DMA_DSTADDR2_DSTADDR_Pos          (0UL)                     /*!< DSTADDR (Bit 0)                                       */
#define DMA_DSTADDR2_DSTADDR_Msk          (0xffffffffUL)            /*!< DSTADDR (Bitfield-Mask: 0xffffffff)                   */
/* =========================================================  TRIG2  ========================================================= */
#define DMA_TRIG2_HARDSRC_Pos             (2UL)                     /*!< HARDSRC (Bit 2)                                       */
#define DMA_TRIG2_HARDSRC_Msk             (0xfcUL)                  /*!< HARDSRC (Bitfield-Mask: 0x3f)                         */
#define DMA_TRIG2_SOFTSRC_Pos             (1UL)                     /*!< SOFTSRC (Bit 1)                                       */
#define DMA_TRIG2_SOFTSRC_Msk             (0x2UL)                   /*!< SOFTSRC (Bitfield-Mask: 0x01)                         */
#define DMA_TRIG2_TYPE_Pos                (0UL)                     /*!< TYPE (Bit 0)                                          */
#define DMA_TRIG2_TYPE_Msk                (0x1UL)                   /*!< TYPE (Bitfield-Mask: 0x01)                            */
/* =========================================================  CCNT2  ========================================================= */
#define DMA_CCNT2_CREPEAT_Pos             (16UL)                    /*!< CREPEAT (Bit 16)                                      */
#define DMA_CCNT2_CREPEAT_Msk             (0xf0000UL)               /*!< CREPEAT (Bitfield-Mask: 0x0f)                         */
#define DMA_CCNT2_CCNT_Pos                (0UL)                     /*!< CCNT (Bit 0)                                          */
#define DMA_CCNT2_CCNT_Msk                (0xffffUL)                /*!< CCNT (Bitfield-Mask: 0xffff)                          */
/* =======================================================  CSRCADDR2  ======================================================= */
#define DMA_CSRCADDR2_CSRCADDR_Pos        (0UL)                     /*!< CSRCADDR (Bit 0)                                      */
#define DMA_CSRCADDR2_CSRCADDR_Msk        (0xffffffffUL)            /*!< CSRCADDR (Bitfield-Mask: 0xffffffff)                  */
/* =======================================================  CDSTADDR2  ======================================================= */
#define DMA_CDSTADDR2_CDSTADDR_Pos        (0UL)                     /*!< CDSTADDR (Bit 0)                                      */
#define DMA_CDSTADDR2_CDSTADDR_Msk        (0xffffffffUL)            /*!< CDSTADDR (Bitfield-Mask: 0xffffffff)                  */
/* =========================================================  CSR3  ========================================================== */
#define DMA_CSR3_DSTLOAD_Pos              (15UL)                    /*!< DSTLOAD (Bit 15)                                      */
#define DMA_CSR3_DSTLOAD_Msk              (0x8000UL)                /*!< DSTLOAD (Bitfield-Mask: 0x01)                         */
#define DMA_CSR3_SRCLOAD_Pos              (14UL)                    /*!< SRCLOAD (Bit 14)                                      */
#define DMA_CSR3_SRCLOAD_Msk              (0x4000UL)                /*!< SRCLOAD (Bitfield-Mask: 0x01)                         */
#define DMA_CSR3_TE_Pos                   (13UL)                    /*!< TE (Bit 13)                                           */
#define DMA_CSR3_TE_Msk                   (0x2000UL)                /*!< TE (Bitfield-Mask: 0x01)                              */
#define DMA_CSR3_TC_Pos                   (12UL)                    /*!< TC (Bit 12)                                           */
#define DMA_CSR3_TC_Msk                   (0x1000UL)                /*!< TC (Bitfield-Mask: 0x01)                              */
#define DMA_CSR3_RESTART_Pos              (11UL)                    /*!< RESTART (Bit 11)                                      */
#define DMA_CSR3_RESTART_Msk              (0x800UL)                 /*!< RESTART (Bitfield-Mask: 0x01)                         */
#define DMA_CSR3_STATUS_Pos               (8UL)                     /*!< STATUS (Bit 8)                                        */
#define DMA_CSR3_STATUS_Msk               (0x700UL)                 /*!< STATUS (Bitfield-Mask: 0x07)                          */
#define DMA_CSR3_SIZE_Pos                 (6UL)                     /*!< SIZE (Bit 6)                                          */
#define DMA_CSR3_SIZE_Msk                 (0xc0UL)                  /*!< SIZE (Bitfield-Mask: 0x03)                            */
#define DMA_CSR3_DSTINC_Pos               (5UL)                     /*!< DSTINC (Bit 5)                                        */
#define DMA_CSR3_DSTINC_Msk               (0x20UL)                  /*!< DSTINC (Bitfield-Mask: 0x01)                          */
#define DMA_CSR3_SRCINC_Pos               (4UL)                     /*!< SRCINC (Bit 4)                                        */
#define DMA_CSR3_SRCINC_Msk               (0x10UL)                  /*!< SRCINC (Bitfield-Mask: 0x01)                          */
#define DMA_CSR3_TRANS_Pos                (3UL)                     /*!< TRANS (Bit 3)                                         */
#define DMA_CSR3_TRANS_Msk                (0x8UL)                   /*!< TRANS (Bitfield-Mask: 0x01)                           */
#define DMA_CSR3_TEIE_Pos                 (2UL)                     /*!< TEIE (Bit 2)                                          */
#define DMA_CSR3_TEIE_Msk                 (0x4UL)                   /*!< TEIE (Bitfield-Mask: 0x01)                            */
#define DMA_CSR3_TCIE_Pos                 (1UL)                     /*!< TCIE (Bit 1)                                          */
#define DMA_CSR3_TCIE_Msk                 (0x2UL)                   /*!< TCIE (Bitfield-Mask: 0x01)                            */
#define DMA_CSR3_EN_Pos                   (0UL)                     /*!< EN (Bit 0)                                            */
#define DMA_CSR3_EN_Msk                   (0x1UL)                   /*!< EN (Bitfield-Mask: 0x01)                              */
/* =========================================================  CNT3  ========================================================== */
#define DMA_CNT3_REPEAT_Pos               (16UL)                    /*!< REPEAT (Bit 16)                                       */
#define DMA_CNT3_REPEAT_Msk               (0xf0000UL)               /*!< REPEAT (Bitfield-Mask: 0x0f)                          */
#define DMA_CNT3_CNT_Pos                  (0UL)                     /*!< CNT (Bit 0)                                           */
#define DMA_CNT3_CNT_Msk                  (0xffffUL)                /*!< CNT (Bitfield-Mask: 0xffff)                           */
/* =======================================================  SRCADDR3  ======================================================== */
#define DMA_SRCADDR3_SRCADDR_Pos          (0UL)                     /*!< SRCADDR (Bit 0)                                       */
#define DMA_SRCADDR3_SRCADDR_Msk          (0xffffffffUL)            /*!< SRCADDR (Bitfield-Mask: 0xffffffff)                   */
/* =======================================================  DSTADDR3  ======================================================== */
#define DMA_DSTADDR3_DSTADDR_Pos          (0UL)                     /*!< DSTADDR (Bit 0)                                       */
#define DMA_DSTADDR3_DSTADDR_Msk          (0xffffffffUL)            /*!< DSTADDR (Bitfield-Mask: 0xffffffff)                   */
/* =========================================================  TRIG3  ========================================================= */
#define DMA_TRIG3_HARDSRC_Pos             (2UL)                     /*!< HARDSRC (Bit 2)                                       */
#define DMA_TRIG3_HARDSRC_Msk             (0xfcUL)                  /*!< HARDSRC (Bitfield-Mask: 0x3f)                         */
#define DMA_TRIG3_SOFTSRC_Pos             (1UL)                     /*!< SOFTSRC (Bit 1)                                       */
#define DMA_TRIG3_SOFTSRC_Msk             (0x2UL)                   /*!< SOFTSRC (Bitfield-Mask: 0x01)                         */
#define DMA_TRIG3_TYPE_Pos                (0UL)                     /*!< TYPE (Bit 0)                                          */
#define DMA_TRIG3_TYPE_Msk                (0x1UL)                   /*!< TYPE (Bitfield-Mask: 0x01)                            */
/* =========================================================  CCNT3  ========================================================= */
#define DMA_CCNT3_CREPEAT_Pos             (16UL)                    /*!< CREPEAT (Bit 16)                                      */
#define DMA_CCNT3_CREPEAT_Msk             (0xf0000UL)               /*!< CREPEAT (Bitfield-Mask: 0x0f)                         */
#define DMA_CCNT3_CCNT_Pos                (0UL)                     /*!< CCNT (Bit 0)                                          */
#define DMA_CCNT3_CCNT_Msk                (0xffffUL)                /*!< CCNT (Bitfield-Mask: 0xffff)                          */
/* =======================================================  CSRCADDR3  ======================================================= */
#define DMA_CSRCADDR3_CSRCADDR_Pos        (0UL)                     /*!< CSRCADDR (Bit 0)                                      */
#define DMA_CSRCADDR3_CSRCADDR_Msk        (0xffffffffUL)            /*!< CSRCADDR (Bitfield-Mask: 0xffffffff)                  */
/* =======================================================  CDSTADDR3  ======================================================= */
#define DMA_CDSTADDR3_CDSTADDR_Pos        (0UL)                     /*!< CDSTADDR (Bit 0)                                      */
#define DMA_CDSTADDR3_CDSTADDR_Msk        (0xffffffffUL)            /*!< CDSTADDR (Bitfield-Mask: 0xffffffff)                  */
/* =========================================================  CSR4  ========================================================== */
#define DMA_CSR4_DSTLOAD_Pos              (15UL)                    /*!< DSTLOAD (Bit 15)                                      */
#define DMA_CSR4_DSTLOAD_Msk              (0x8000UL)                /*!< DSTLOAD (Bitfield-Mask: 0x01)                         */
#define DMA_CSR4_SRCLOAD_Pos              (14UL)                    /*!< SRCLOAD (Bit 14)                                      */
#define DMA_CSR4_SRCLOAD_Msk              (0x4000UL)                /*!< SRCLOAD (Bitfield-Mask: 0x01)                         */
#define DMA_CSR4_TE_Pos                   (13UL)                    /*!< TE (Bit 13)                                           */
#define DMA_CSR4_TE_Msk                   (0x2000UL)                /*!< TE (Bitfield-Mask: 0x01)                              */
#define DMA_CSR4_TC_Pos                   (12UL)                    /*!< TC (Bit 12)                                           */
#define DMA_CSR4_TC_Msk                   (0x1000UL)                /*!< TC (Bitfield-Mask: 0x01)                              */
#define DMA_CSR4_RESTART_Pos              (11UL)                    /*!< RESTART (Bit 11)                                      */
#define DMA_CSR4_RESTART_Msk              (0x800UL)                 /*!< RESTART (Bitfield-Mask: 0x01)                         */
#define DMA_CSR4_STATUS_Pos               (8UL)                     /*!< STATUS (Bit 8)                                        */
#define DMA_CSR4_STATUS_Msk               (0x700UL)                 /*!< STATUS (Bitfield-Mask: 0x07)                          */
#define DMA_CSR4_SIZE_Pos                 (6UL)                     /*!< SIZE (Bit 6)                                          */
#define DMA_CSR4_SIZE_Msk                 (0xc0UL)                  /*!< SIZE (Bitfield-Mask: 0x03)                            */
#define DMA_CSR4_DSTINC_Pos               (5UL)                     /*!< DSTINC (Bit 5)                                        */
#define DMA_CSR4_DSTINC_Msk               (0x20UL)                  /*!< DSTINC (Bitfield-Mask: 0x01)                          */
#define DMA_CSR4_SRCINC_Pos               (4UL)                     /*!< SRCINC (Bit 4)                                        */
#define DMA_CSR4_SRCINC_Msk               (0x10UL)                  /*!< SRCINC (Bitfield-Mask: 0x01)                          */
#define DMA_CSR4_TRANS_Pos                (3UL)                     /*!< TRANS (Bit 3)                                         */
#define DMA_CSR4_TRANS_Msk                (0x8UL)                   /*!< TRANS (Bitfield-Mask: 0x01)                           */
#define DMA_CSR4_TEIE_Pos                 (2UL)                     /*!< TEIE (Bit 2)                                          */
#define DMA_CSR4_TEIE_Msk                 (0x4UL)                   /*!< TEIE (Bitfield-Mask: 0x01)                            */
#define DMA_CSR4_TCIE_Pos                 (1UL)                     /*!< TCIE (Bit 1)                                          */
#define DMA_CSR4_TCIE_Msk                 (0x2UL)                   /*!< TCIE (Bitfield-Mask: 0x01)                            */
#define DMA_CSR4_EN_Pos                   (0UL)                     /*!< EN (Bit 0)                                            */
#define DMA_CSR4_EN_Msk                   (0x1UL)                   /*!< EN (Bitfield-Mask: 0x01)                              */
/* =========================================================  CNT4  ========================================================== */
#define DMA_CNT4_REPEAT_Pos               (16UL)                    /*!< REPEAT (Bit 16)                                       */
#define DMA_CNT4_REPEAT_Msk               (0xf0000UL)               /*!< REPEAT (Bitfield-Mask: 0x0f)                          */
#define DMA_CNT4_CNT_Pos                  (0UL)                     /*!< CNT (Bit 0)                                           */
#define DMA_CNT4_CNT_Msk                  (0xffffUL)                /*!< CNT (Bitfield-Mask: 0xffff)                           */
/* =======================================================  SRCADDR4  ======================================================== */
#define DMA_SRCADDR4_SRCADDR_Pos          (0UL)                     /*!< SRCADDR (Bit 0)                                       */
#define DMA_SRCADDR4_SRCADDR_Msk          (0xffffffffUL)            /*!< SRCADDR (Bitfield-Mask: 0xffffffff)                   */
/* =======================================================  DSTADDR4  ======================================================== */
#define DMA_DSTADDR4_DSTADDR_Pos          (0UL)                     /*!< DSTADDR (Bit 0)                                       */
#define DMA_DSTADDR4_DSTADDR_Msk          (0xffffffffUL)            /*!< DSTADDR (Bitfield-Mask: 0xffffffff)                   */
/* =========================================================  TRIG4  ========================================================= */
#define DMA_TRIG4_HARDSRC_Pos             (2UL)                     /*!< HARDSRC (Bit 2)                                       */
#define DMA_TRIG4_HARDSRC_Msk             (0xfcUL)                  /*!< HARDSRC (Bitfield-Mask: 0x3f)                         */
#define DMA_TRIG4_SOFTSRC_Pos             (1UL)                     /*!< SOFTSRC (Bit 1)                                       */
#define DMA_TRIG4_SOFTSRC_Msk             (0x2UL)                   /*!< SOFTSRC (Bitfield-Mask: 0x01)                         */
#define DMA_TRIG4_TYPE_Pos                (0UL)                     /*!< TYPE (Bit 0)                                          */
#define DMA_TRIG4_TYPE_Msk                (0x1UL)                   /*!< TYPE (Bitfield-Mask: 0x01)                            */
/* =========================================================  CCNT4  ========================================================= */
#define DMA_CCNT4_CREPEAT_Pos             (16UL)                    /*!< CREPEAT (Bit 16)                                      */
#define DMA_CCNT4_CREPEAT_Msk             (0xf0000UL)               /*!< CREPEAT (Bitfield-Mask: 0x0f)                         */
#define DMA_CCNT4_CCNT_Pos                (0UL)                     /*!< CCNT (Bit 0)                                          */
#define DMA_CCNT4_CCNT_Msk                (0xffffUL)                /*!< CCNT (Bitfield-Mask: 0xffff)                          */
/* =======================================================  CSRCADDR4  ======================================================= */
#define DMA_CSRCADDR4_CSRCADDR_Pos        (0UL)                     /*!< CSRCADDR (Bit 0)                                      */
#define DMA_CSRCADDR4_CSRCADDR_Msk        (0xffffffffUL)            /*!< CSRCADDR (Bitfield-Mask: 0xffffffff)                  */
/* =======================================================  CDSTADDR4  ======================================================= */
#define DMA_CDSTADDR4_CDSTADDR_Pos        (0UL)                     /*!< CDSTADDR (Bit 0)                                      */
#define DMA_CDSTADDR4_CDSTADDR_Msk        (0xffffffffUL)            /*!< CDSTADDR (Bitfield-Mask: 0xffffffff)                  */


/* =========================================================================================================================== */
/* ================                                        DMACHANNEL                                         ================ */
/* =========================================================================================================================== */

/* ==========================================================  CSR  ========================================================== */
#define DMACHx_CSR_DSTLOAD_Pos       (15UL)                    /*!< DSTLOAD (Bit 15)                                      */
#define DMACHx_CSR_DSTLOAD_Msk       (0x8000UL)                /*!< DSTLOAD (Bitfield-Mask: 0x01)                         */
#define DMACHx_CSR_SRCLOAD_Pos       (14UL)                    /*!< SRCLOAD (Bit 14)                                      */
#define DMACHx_CSR_SRCLOAD_Msk       (0x4000UL)                /*!< SRCLOAD (Bitfield-Mask: 0x01)                         */
#define DMACHx_CSR_TE_Pos            (13UL)                    /*!< TE (Bit 13)                                           */
#define DMACHx_CSR_TE_Msk            (0x2000UL)                /*!< TE (Bitfield-Mask: 0x01)                              */
#define DMACHx_CSR_TC_Pos            (12UL)                    /*!< TC (Bit 12)                                           */
#define DMACHx_CSR_TC_Msk            (0x1000UL)                /*!< TC (Bitfield-Mask: 0x01)                              */
#define DMACHx_CSR_RESTART_Pos       (11UL)                    /*!< RESTART (Bit 11)                                      */
#define DMACHx_CSR_RESTART_Msk       (0x800UL)                 /*!< RESTART (Bitfield-Mask: 0x01)                         */
#define DMACHx_CSR_STATUS_Pos        (8UL)                     /*!< STATUS (Bit 8)                                        */
#define DMACHx_CSR_STATUS_Msk        (0x700UL)                 /*!< STATUS (Bitfield-Mask: 0x07)                          */
#define DMACHx_CSR_SIZE_Pos          (6UL)                     /*!< SIZE (Bit 6)                                          */
#define DMACHx_CSR_SIZE_Msk          (0xc0UL)                  /*!< SIZE (Bitfield-Mask: 0x03)                            */
#define DMACHx_CSR_DSTINC_Pos        (5UL)                     /*!< DSTINC (Bit 5)                                        */
#define DMACHx_CSR_DSTINC_Msk        (0x20UL)                  /*!< DSTINC (Bitfield-Mask: 0x01)                          */
#define DMACHx_CSR_SRCINC_Pos        (4UL)                     /*!< SRCINC (Bit 4)                                        */
#define DMACHx_CSR_SRCINC_Msk        (0x10UL)                  /*!< SRCINC (Bitfield-Mask: 0x01)                          */
#define DMACHx_CSR_TRANS_Pos         (3UL)                     /*!< TRANS (Bit 3)                                         */
#define DMACHx_CSR_TRANS_Msk         (0x8UL)                   /*!< TRANS (Bitfield-Mask: 0x01)                           */
#define DMACHx_CSR_TEIE_Pos          (2UL)                     /*!< TEIE (Bit 2)                                          */
#define DMACHx_CSR_TEIE_Msk          (0x4UL)                   /*!< TEIE (Bitfield-Mask: 0x01)                            */
#define DMACHx_CSR_TCIE_Pos          (1UL)                     /*!< TCIE (Bit 1)                                          */
#define DMACHx_CSR_TCIE_Msk          (0x2UL)                   /*!< TCIE (Bitfield-Mask: 0x01)                            */
#define DMACHx_CSR_EN_Pos            (0UL)                     /*!< EN (Bit 0)                                            */
#define DMACHx_CSR_EN_Msk            (0x1UL)                   /*!< EN (Bitfield-Mask: 0x01)                              */
/* ==========================================================  CNT  ========================================================== */
#define DMACHx_CNT_REPEAT_Pos        (16UL)                    /*!< REPEAT (Bit 16)                                       */
#define DMACHx_CNT_REPEAT_Msk        (0xf0000UL)               /*!< REPEAT (Bitfield-Mask: 0x0f)                          */
#define DMACHx_CNT_CNT_Pos           (0UL)                     /*!< CNT (Bit 0)                                           */
#define DMACHx_CNT_CNT_Msk           (0xffffUL)                /*!< CNT (Bitfield-Mask: 0xffff)                           */
/* ========================================================  SRCADDR  ======================================================== */
#define DMACHx_SRCADDR_SRCADDR_Pos   (0UL)                     /*!< SRCADDR (Bit 0)                                       */
#define DMACHx_SRCADDR_SRCADDR_Msk   (0xffffffffUL)            /*!< SRCADDR (Bitfield-Mask: 0xffffffff)                   */
/* ========================================================  DSTADDR  ======================================================== */
#define DMACHx_DSTADDR_DSTADDR_Pos   (0UL)                     /*!< DSTADDR (Bit 0)                                       */
#define DMACHx_DSTADDR_DSTADDR_Msk   (0xffffffffUL)            /*!< DSTADDR (Bitfield-Mask: 0xffffffff)                   */
/* =========================================================  TRIG  ========================================================== */
#define DMACHx_TRIG_HARDSRC_Pos      (2UL)                     /*!< HARDSRC (Bit 2)                                       */
#define DMACHx_TRIG_HARDSRC_Msk      (0xfcUL)                  /*!< HARDSRC (Bitfield-Mask: 0x3f)                         */
#define DMACHx_TRIG_SOFTSRC_Pos      (1UL)                     /*!< SOFTSRC (Bit 1)                                       */
#define DMACHx_TRIG_SOFTSRC_Msk      (0x2UL)                   /*!< SOFTSRC (Bitfield-Mask: 0x01)                         */
#define DMACHx_TRIG_TYPE_Pos         (0UL)                     /*!< TYPE (Bit 0)                                          */
#define DMACHx_TRIG_TYPE_Msk         (0x1UL)                   /*!< TYPE (Bitfield-Mask: 0x01)                            */
/* =========================================================  CCNT  ========================================================== */
#define DMACHx_CCNT_CREPEAT_Pos      (16UL)                    /*!< CREPEAT (Bit 16)                                      */
#define DMACHx_CCNT_CREPEAT_Msk      (0xf0000UL)               /*!< CREPEAT (Bitfield-Mask: 0x0f)                         */
#define DMACHx_CCNT_CCNT_Pos         (0UL)                     /*!< CCNT (Bit 0)                                          */
#define DMACHx_CCNT_CCNT_Msk         (0xffffUL)                /*!< CCNT (Bitfield-Mask: 0xffff)                          */
/* =======================================================  CSRCADDR  ======================================================== */
#define DMACHx_CSRCADDR_CSRCADDR_Pos (0UL)                     /*!< CSRCADDR (Bit 0)                                      */
#define DMACHx_CSRCADDR_CSRCADDR_Msk (0xffffffffUL)            /*!< CSRCADDR (Bitfield-Mask: 0xffffffff)                  */
/* =======================================================  CDSTADDR  ======================================================== */
#define DMACHx_CDSTADDR_CDSTADDR_Pos (0UL)                     /*!< CDSTADDR (Bit 0)                                      */
#define DMACHx_CDSTADDR_CDSTADDR_Msk (0xffffffffUL)            /*!< CDSTADDR (Bitfield-Mask: 0xffffffff)                  */


/* =========================================================================================================================== */
/* ================                                            EAU                                            ================ */
/* =========================================================================================================================== */

/* ==========================================================  CSR  ========================================================== */
#define EAU_CSR_BUSY_Pos                  (4UL)                     /*!< BUSY (Bit 4)                                          */
#define EAU_CSR_BUSY_Msk                  (0x10UL)                  /*!< BUSY (Bitfield-Mask: 0x01)                            */
#define EAU_CSR_ZERO_Pos                  (3UL)                     /*!< ZERO (Bit 3)                                          */
#define EAU_CSR_ZERO_Msk                  (0x8UL)                   /*!< ZERO (Bitfield-Mask: 0x01)                            */
#define EAU_CSR_OVR_Pos                   (2UL)                     /*!< OVR (Bit 2)                                           */
#define EAU_CSR_OVR_Msk                   (0x4UL)                   /*!< OVR (Bitfield-Mask: 0x01)                             */
#define EAU_CSR_MODE_Pos                  (0UL)                     /*!< MODE (Bit 0)                                          */
#define EAU_CSR_MODE_Msk                  (0x3UL)                   /*!< MODE (Bitfield-Mask: 0x03)                            */
/* =======================================================  DIVIDEND  ======================================================== */
#define EAU_DIVIDEND_DIVIDEND_Pos         (0UL)                     /*!< DIVIDEND (Bit 0)                                      */
#define EAU_DIVIDEND_DIVIDEND_Msk         (0xffffffffUL)            /*!< DIVIDEND (Bitfield-Mask: 0xffffffff)                  */
/* ========================================================  DIVISOR  ======================================================== */
#define EAU_DIVISOR_DIVISOR_Pos           (0UL)                     /*!< DIVISOR (Bit 0)                                       */
#define EAU_DIVISOR_DIVISOR_Msk           (0xffffffffUL)            /*!< DIVISOR (Bitfield-Mask: 0xffffffff)                   */
/* =======================================================  QUOTIENT  ======================================================== */
#define EAU_QUOTIENT_QUOTIENT_Pos         (0UL)                     /*!< QUOTIENT (Bit 0)                                      */
#define EAU_QUOTIENT_QUOTIENT_Msk         (0xffffffffUL)            /*!< QUOTIENT (Bitfield-Mask: 0xffffffff)                  */
/* =======================================================  REMAINDER  ======================================================= */
#define EAU_REMAINDER_REMAINDER_Pos       (0UL)                     /*!< REMAINDER (Bit 0)                                     */
#define EAU_REMAINDER_REMAINDER_Msk       (0xffffffffUL)            /*!< REMAINDER (Bitfield-Mask: 0xffffffff)                 */


/* =========================================================================================================================== */
/* ================                                           FLASH                                           ================ */
/* =========================================================================================================================== */

/* ==========================================================  CR1  ========================================================== */
#define FLASH_CR1_KEY_Pos                 (16UL)                    /*!< KEY (Bit 16)                                          */
#define FLASH_CR1_KEY_Msk                 (0xffff0000UL)            /*!< KEY (Bitfield-Mask: 0xffff)                           */
#define FLASH_CR1_SECURITY_Pos            (5UL)                     /*!< SECURITY (Bit 5)                                      */
#define FLASH_CR1_SECURITY_Msk            (0x60UL)                  /*!< SECURITY (Bitfield-Mask: 0x03)                        */
#define FLASH_CR1_MODE_Pos                (0UL)                     /*!< MODE (Bit 0)                                          */
#define FLASH_CR1_MODE_Msk                (0x3UL)                   /*!< MODE (Bitfield-Mask: 0x03)                            */
/* ==========================================================  CR2  ========================================================== */
#define FLASH_CR2_KEY_Pos                 (16UL)                    /*!< KEY (Bit 16)                                          */
#define FLASH_CR2_KEY_Msk                 (0xffff0000UL)            /*!< KEY (Bitfield-Mask: 0xffff)                           */
#define FLASH_CR2_CACHEINVALID_Pos        (5UL)                     /*!< CACHEINVALID (Bit 5)                                  */
#define FLASH_CR2_CACHEINVALID_Msk        (0x20UL)                  /*!< CACHEINVALID (Bitfield-Mask: 0x01)                    */
#define FLASH_CR2_CACHE_Pos               (4UL)                     /*!< CACHE (Bit 4)                                         */
#define FLASH_CR2_CACHE_Msk               (0x10UL)                  /*!< CACHE (Bitfield-Mask: 0x01)                           */
#define FLASH_CR2_FETCH_Pos               (3UL)                     /*!< FETCH (Bit 3)                                         */
#define FLASH_CR2_FETCH_Msk               (0x8UL)                   /*!< FETCH (Bitfield-Mask: 0x01)                           */
#define FLASH_CR2_WAIT_Pos                (0UL)                     /*!< WAIT (Bit 0)                                          */
#define FLASH_CR2_WAIT_Msk                (0x7UL)                   /*!< WAIT (Bitfield-Mask: 0x07)                            */
/* =======================================================  PAGELOCK  ======================================================== */
#define FLASH_PAGELOCK_KEY_Pos            (16UL)                    /*!< KEY (Bit 16)                                          */
#define FLASH_PAGELOCK_KEY_Msk            (0xffff0000UL)            /*!< KEY (Bitfield-Mask: 0xffff)                           */
#define FLASH_PAGELOCK_LOCK15_Pos         (15UL)                    /*!< LOCK15 (Bit 15)                                       */
#define FLASH_PAGELOCK_LOCK15_Msk         (0x8000UL)                /*!< LOCK15 (Bitfield-Mask: 0x01)                          */
#define FLASH_PAGELOCK_LOCK14_Pos         (14UL)                    /*!< LOCK14 (Bit 14)                                       */
#define FLASH_PAGELOCK_LOCK14_Msk         (0x4000UL)                /*!< LOCK14 (Bitfield-Mask: 0x01)                          */
#define FLASH_PAGELOCK_LOCK13_Pos         (13UL)                    /*!< LOCK13 (Bit 13)                                       */
#define FLASH_PAGELOCK_LOCK13_Msk         (0x2000UL)                /*!< LOCK13 (Bitfield-Mask: 0x01)                          */
#define FLASH_PAGELOCK_LOCK12_Pos         (12UL)                    /*!< LOCK12 (Bit 12)                                       */
#define FLASH_PAGELOCK_LOCK12_Msk         (0x1000UL)                /*!< LOCK12 (Bitfield-Mask: 0x01)                          */
#define FLASH_PAGELOCK_LOCK11_Pos         (11UL)                    /*!< LOCK11 (Bit 11)                                       */
#define FLASH_PAGELOCK_LOCK11_Msk         (0x800UL)                 /*!< LOCK11 (Bitfield-Mask: 0x01)                          */
#define FLASH_PAGELOCK_LOCK10_Pos         (10UL)                    /*!< LOCK10 (Bit 10)                                       */
#define FLASH_PAGELOCK_LOCK10_Msk         (0x400UL)                 /*!< LOCK10 (Bitfield-Mask: 0x01)                          */
#define FLASH_PAGELOCK_LOCK9_Pos          (9UL)                     /*!< LOCK9 (Bit 9)                                         */
#define FLASH_PAGELOCK_LOCK9_Msk          (0x200UL)                 /*!< LOCK9 (Bitfield-Mask: 0x01)                           */
#define FLASH_PAGELOCK_LOCK8_Pos          (8UL)                     /*!< LOCK8 (Bit 8)                                         */
#define FLASH_PAGELOCK_LOCK8_Msk          (0x100UL)                 /*!< LOCK8 (Bitfield-Mask: 0x01)                           */
#define FLASH_PAGELOCK_LOCK7_Pos          (7UL)                     /*!< LOCK7 (Bit 7)                                         */
#define FLASH_PAGELOCK_LOCK7_Msk          (0x80UL)                  /*!< LOCK7 (Bitfield-Mask: 0x01)                           */
#define FLASH_PAGELOCK_LOCK6_Pos          (6UL)                     /*!< LOCK6 (Bit 6)                                         */
#define FLASH_PAGELOCK_LOCK6_Msk          (0x40UL)                  /*!< LOCK6 (Bitfield-Mask: 0x01)                           */
#define FLASH_PAGELOCK_LOCK5_Pos          (5UL)                     /*!< LOCK5 (Bit 5)                                         */
#define FLASH_PAGELOCK_LOCK5_Msk          (0x20UL)                  /*!< LOCK5 (Bitfield-Mask: 0x01)                           */
#define FLASH_PAGELOCK_LOCK4_Pos          (4UL)                     /*!< LOCK4 (Bit 4)                                         */
#define FLASH_PAGELOCK_LOCK4_Msk          (0x10UL)                  /*!< LOCK4 (Bitfield-Mask: 0x01)                           */
#define FLASH_PAGELOCK_LOCK3_Pos          (3UL)                     /*!< LOCK3 (Bit 3)                                         */
#define FLASH_PAGELOCK_LOCK3_Msk          (0x8UL)                   /*!< LOCK3 (Bitfield-Mask: 0x01)                           */
#define FLASH_PAGELOCK_LOCK2_Pos          (2UL)                     /*!< LOCK2 (Bit 2)                                         */
#define FLASH_PAGELOCK_LOCK2_Msk          (0x4UL)                   /*!< LOCK2 (Bitfield-Mask: 0x01)                           */
#define FLASH_PAGELOCK_LOCK1_Pos          (1UL)                     /*!< LOCK1 (Bit 1)                                         */
#define FLASH_PAGELOCK_LOCK1_Msk          (0x2UL)                   /*!< LOCK1 (Bitfield-Mask: 0x01)                           */
#define FLASH_PAGELOCK_LOCK0_Pos          (0UL)                     /*!< LOCK0 (Bit 0)                                         */
#define FLASH_PAGELOCK_LOCK0_Msk          (0x1UL)                   /*!< LOCK0 (Bitfield-Mask: 0x01)                           */
/* ==========================================================  IER  ========================================================== */
#define FLASH_IER_PROG_Pos                (4UL)                     /*!< PROG (Bit 4)                                          */
#define FLASH_IER_PROG_Msk                (0x10UL)                  /*!< PROG (Bitfield-Mask: 0x01)                            */
#define FLASH_IER_CACHEON_Pos             (3UL)                     /*!< CACHEON (Bit 3)                                       */
#define FLASH_IER_CACHEON_Msk             (0x8UL)                   /*!< CACHEON (Bitfield-Mask: 0x01)                         */
#define FLASH_IER_SDKERR_Pos              (2UL)                     /*!< SDKERR (Bit 2)                                        */
#define FLASH_IER_SDKERR_Msk              (0x4UL)                   /*!< SDKERR (Bitfield-Mask: 0x01)                          */
#define FLASH_IER_PAGELOCK_Pos            (1UL)                     /*!< PAGELOCK (Bit 1)                                      */
#define FLASH_IER_PAGELOCK_Msk            (0x2UL)                   /*!< PAGELOCK (Bitfield-Mask: 0x01)                        */
#define FLASH_IER_PC_Pos                  (0UL)                     /*!< PC (Bit 0)                                            */
#define FLASH_IER_PC_Msk                  (0x1UL)                   /*!< PC (Bitfield-Mask: 0x01)                              */
/* ==========================================================  ISR  ========================================================== */
#define FLASH_ISR_BUSY_Pos                (5UL)                     /*!< BUSY (Bit 5)                                          */
#define FLASH_ISR_BUSY_Msk                (0x20UL)                  /*!< BUSY (Bitfield-Mask: 0x01)                            */
#define FLASH_ISR_PROG_Pos                (4UL)                     /*!< PROG (Bit 4)                                          */
#define FLASH_ISR_PROG_Msk                (0x10UL)                  /*!< PROG (Bitfield-Mask: 0x01)                            */
#define FLASH_ISR_CACHEON_Pos             (3UL)                     /*!< CACHEON (Bit 3)                                       */
#define FLASH_ISR_CACHEON_Msk             (0x8UL)                   /*!< CACHEON (Bitfield-Mask: 0x01)                         */
#define FLASH_ISR_SDKERR_Pos              (2UL)                     /*!< SDKERR (Bit 2)                                        */
#define FLASH_ISR_SDKERR_Msk              (0x4UL)                   /*!< SDKERR (Bitfield-Mask: 0x01)                          */
#define FLASH_ISR_PAGELOCK_Pos            (1UL)                     /*!< PAGELOCK (Bit 1)                                      */
#define FLASH_ISR_PAGELOCK_Msk            (0x2UL)                   /*!< PAGELOCK (Bitfield-Mask: 0x01)                        */
#define FLASH_ISR_PC_Pos                  (0UL)                     /*!< PC (Bit 0)                                            */
#define FLASH_ISR_PC_Msk                  (0x1UL)                   /*!< PC (Bitfield-Mask: 0x01)                              */
/* ==========================================================  ICR  ========================================================== */
#define FLASH_ICR_PROG_Pos                (4UL)                     /*!< PROG (Bit 4)                                          */
#define FLASH_ICR_PROG_Msk                (0x10UL)                  /*!< PROG (Bitfield-Mask: 0x01)                            */
#define FLASH_ICR_CACHEON_Pos             (3UL)                     /*!< CACHEON (Bit 3)                                       */
#define FLASH_ICR_CACHEON_Msk             (0x8UL)                   /*!< CACHEON (Bitfield-Mask: 0x01)                         */
#define FLASH_ICR_SDKERR_Pos              (2UL)                     /*!< SDKERR (Bit 2)                                        */
#define FLASH_ICR_SDKERR_Msk              (0x4UL)                   /*!< SDKERR (Bitfield-Mask: 0x01)                          */
#define FLASH_ICR_PAGELOCK_Pos            (1UL)                     /*!< PAGELOCK (Bit 1)                                      */
#define FLASH_ICR_PAGELOCK_Msk            (0x2UL)                   /*!< PAGELOCK (Bitfield-Mask: 0x01)                        */
#define FLASH_ICR_PC_Pos                  (0UL)                     /*!< PC (Bit 0)                                            */
#define FLASH_ICR_PC_Msk                  (0x1UL)                   /*!< PC (Bitfield-Mask: 0x01)                              */
/* ========================================================  SDKCFR  ========================================================= */
#define FLASH_SDKCFR_END_Pos              (8UL)                     /*!< END (Bit 8)                                           */
#define FLASH_SDKCFR_END_Msk              (0x7f00UL)                /*!< END (Bitfield-Mask: 0x7f)                             */
#define FLASH_SDKCFR_START_Pos            (0UL)                     /*!< START (Bit 0)                                         */
#define FLASH_SDKCFR_START_Msk            (0x7fUL)                  /*!< START (Bitfield-Mask: 0x7f)                           */


/* =========================================================================================================================== */
/* ================                                           GPIO                                            ================ */
/* =========================================================================================================================== */

/* ==========================================================  DIR  ========================================================== */
#define GPIOx_DIR_PIN15_Pos               (15UL)                    /*!< PIN15 (Bit 15)                                        */
#define GPIOx_DIR_PIN15_Msk               (0x8000UL)                /*!< PIN15 (Bitfield-Mask: 0x01)                           */
#define GPIOx_DIR_PIN14_Pos               (14UL)                    /*!< PIN14 (Bit 14)                                        */
#define GPIOx_DIR_PIN14_Msk               (0x4000UL)                /*!< PIN14 (Bitfield-Mask: 0x01)                           */
#define GPIOx_DIR_PIN13_Pos               (13UL)                    /*!< PIN13 (Bit 13)                                        */
#define GPIOx_DIR_PIN13_Msk               (0x2000UL)                /*!< PIN13 (Bitfield-Mask: 0x01)                           */
#define GPIOx_DIR_PIN12_Pos               (12UL)                    /*!< PIN12 (Bit 12)                                        */
#define GPIOx_DIR_PIN12_Msk               (0x1000UL)                /*!< PIN12 (Bitfield-Mask: 0x01)                           */
#define GPIOx_DIR_PIN11_Pos               (11UL)                    /*!< PIN11 (Bit 11)                                        */
#define GPIOx_DIR_PIN11_Msk               (0x800UL)                 /*!< PIN11 (Bitfield-Mask: 0x01)                           */
#define GPIOx_DIR_PIN10_Pos               (10UL)                    /*!< PIN10 (Bit 10)                                        */
#define GPIOx_DIR_PIN10_Msk               (0x400UL)                 /*!< PIN10 (Bitfield-Mask: 0x01)                           */
#define GPIOx_DIR_PIN9_Pos                (9UL)                     /*!< PIN9 (Bit 9)                                          */
#define GPIOx_DIR_PIN9_Msk                (0x200UL)                 /*!< PIN9 (Bitfield-Mask: 0x01)                            */
#define GPIOx_DIR_PIN8_Pos                (8UL)                     /*!< PIN8 (Bit 8)                                          */
#define GPIOx_DIR_PIN8_Msk                (0x100UL)                 /*!< PIN8 (Bitfield-Mask: 0x01)                            */
#define GPIOx_DIR_PIN7_Pos                (7UL)                     /*!< PIN7 (Bit 7)                                          */
#define GPIOx_DIR_PIN7_Msk                (0x80UL)                  /*!< PIN7 (Bitfield-Mask: 0x01)                            */
#define GPIOx_DIR_PIN6_Pos                (6UL)                     /*!< PIN6 (Bit 6)                                          */
#define GPIOx_DIR_PIN6_Msk                (0x40UL)                  /*!< PIN6 (Bitfield-Mask: 0x01)                            */
#define GPIOx_DIR_PIN5_Pos                (5UL)                     /*!< PIN5 (Bit 5)                                          */
#define GPIOx_DIR_PIN5_Msk                (0x20UL)                  /*!< PIN5 (Bitfield-Mask: 0x01)                            */
#define GPIOx_DIR_PIN4_Pos                (4UL)                     /*!< PIN4 (Bit 4)                                          */
#define GPIOx_DIR_PIN4_Msk                (0x10UL)                  /*!< PIN4 (Bitfield-Mask: 0x01)                            */
#define GPIOx_DIR_PIN3_Pos                (3UL)                     /*!< PIN3 (Bit 3)                                          */
#define GPIOx_DIR_PIN3_Msk                (0x8UL)                   /*!< PIN3 (Bitfield-Mask: 0x01)                            */
#define GPIOx_DIR_PIN2_Pos                (2UL)                     /*!< PIN2 (Bit 2)                                          */
#define GPIOx_DIR_PIN2_Msk                (0x4UL)                   /*!< PIN2 (Bitfield-Mask: 0x01)                            */
#define GPIOx_DIR_PIN1_Pos                (1UL)                     /*!< PIN1 (Bit 1)                                          */
#define GPIOx_DIR_PIN1_Msk                (0x2UL)                   /*!< PIN1 (Bitfield-Mask: 0x01)                            */
#define GPIOx_DIR_PIN0_Pos                (0UL)                     /*!< PIN0 (Bit 0)                                          */
#define GPIOx_DIR_PIN0_Msk                (0x1UL)                   /*!< PIN0 (Bitfield-Mask: 0x01)                            */
/* =======================================================  OPENDRAIN  ======================================================= */
#define GPIOx_OPENDRAIN_PIN15_Pos         (15UL)                    /*!< PIN15 (Bit 15)                                        */
#define GPIOx_OPENDRAIN_PIN15_Msk         (0x8000UL)                /*!< PIN15 (Bitfield-Mask: 0x01)                           */
#define GPIOx_OPENDRAIN_PIN14_Pos         (14UL)                    /*!< PIN14 (Bit 14)                                        */
#define GPIOx_OPENDRAIN_PIN14_Msk         (0x4000UL)                /*!< PIN14 (Bitfield-Mask: 0x01)                           */
#define GPIOx_OPENDRAIN_PIN13_Pos         (13UL)                    /*!< PIN13 (Bit 13)                                        */
#define GPIOx_OPENDRAIN_PIN13_Msk         (0x2000UL)                /*!< PIN13 (Bitfield-Mask: 0x01)                           */
#define GPIOx_OPENDRAIN_PIN12_Pos         (12UL)                    /*!< PIN12 (Bit 12)                                        */
#define GPIOx_OPENDRAIN_PIN12_Msk         (0x1000UL)                /*!< PIN12 (Bitfield-Mask: 0x01)                           */
#define GPIOx_OPENDRAIN_PIN11_Pos         (11UL)                    /*!< PIN11 (Bit 11)                                        */
#define GPIOx_OPENDRAIN_PIN11_Msk         (0x800UL)                 /*!< PIN11 (Bitfield-Mask: 0x01)                           */
#define GPIOx_OPENDRAIN_PIN10_Pos         (10UL)                    /*!< PIN10 (Bit 10)                                        */
#define GPIOx_OPENDRAIN_PIN10_Msk         (0x400UL)                 /*!< PIN10 (Bitfield-Mask: 0x01)                           */
#define GPIOx_OPENDRAIN_PIN9_Pos          (9UL)                     /*!< PIN9 (Bit 9)                                          */
#define GPIOx_OPENDRAIN_PIN9_Msk          (0x200UL)                 /*!< PIN9 (Bitfield-Mask: 0x01)                            */
#define GPIOx_OPENDRAIN_PIN8_Pos          (8UL)                     /*!< PIN8 (Bit 8)                                          */
#define GPIOx_OPENDRAIN_PIN8_Msk          (0x100UL)                 /*!< PIN8 (Bitfield-Mask: 0x01)                            */
#define GPIOx_OPENDRAIN_PIN7_Pos          (7UL)                     /*!< PIN7 (Bit 7)                                          */
#define GPIOx_OPENDRAIN_PIN7_Msk          (0x80UL)                  /*!< PIN7 (Bitfield-Mask: 0x01)                            */
#define GPIOx_OPENDRAIN_PIN6_Pos          (6UL)                     /*!< PIN6 (Bit 6)                                          */
#define GPIOx_OPENDRAIN_PIN6_Msk          (0x40UL)                  /*!< PIN6 (Bitfield-Mask: 0x01)                            */
#define GPIOx_OPENDRAIN_PIN5_Pos          (5UL)                     /*!< PIN5 (Bit 5)                                          */
#define GPIOx_OPENDRAIN_PIN5_Msk          (0x20UL)                  /*!< PIN5 (Bitfield-Mask: 0x01)                            */
#define GPIOx_OPENDRAIN_PIN4_Pos          (4UL)                     /*!< PIN4 (Bit 4)                                          */
#define GPIOx_OPENDRAIN_PIN4_Msk          (0x10UL)                  /*!< PIN4 (Bitfield-Mask: 0x01)                            */
#define GPIOx_OPENDRAIN_PIN3_Pos          (3UL)                     /*!< PIN3 (Bit 3)                                          */
#define GPIOx_OPENDRAIN_PIN3_Msk          (0x8UL)                   /*!< PIN3 (Bitfield-Mask: 0x01)                            */
#define GPIOx_OPENDRAIN_PIN2_Pos          (2UL)                     /*!< PIN2 (Bit 2)                                          */
#define GPIOx_OPENDRAIN_PIN2_Msk          (0x4UL)                   /*!< PIN2 (Bitfield-Mask: 0x01)                            */
#define GPIOx_OPENDRAIN_PIN1_Pos          (1UL)                     /*!< PIN1 (Bit 1)                                          */
#define GPIOx_OPENDRAIN_PIN1_Msk          (0x2UL)                   /*!< PIN1 (Bitfield-Mask: 0x01)                            */
#define GPIOx_OPENDRAIN_PIN0_Pos          (0UL)                     /*!< PIN0 (Bit 0)                                          */
#define GPIOx_OPENDRAIN_PIN0_Msk          (0x1UL)                   /*!< PIN0 (Bitfield-Mask: 0x01)                            */
/* ==========================================================  PUR  ========================================================== */
#define GPIOx_PUR_PIN15_Pos               (15UL)                    /*!< PIN15 (Bit 15)                                        */
#define GPIOx_PUR_PIN15_Msk               (0x8000UL)                /*!< PIN15 (Bitfield-Mask: 0x01)                           */
#define GPIOx_PUR_PIN14_Pos               (14UL)                    /*!< PIN14 (Bit 14)                                        */
#define GPIOx_PUR_PIN14_Msk               (0x4000UL)                /*!< PIN14 (Bitfield-Mask: 0x01)                           */
#define GPIOx_PUR_PIN13_Pos               (13UL)                    /*!< PIN13 (Bit 13)                                        */
#define GPIOx_PUR_PIN13_Msk               (0x2000UL)                /*!< PIN13 (Bitfield-Mask: 0x01)                           */
#define GPIOx_PUR_PIN12_Pos               (12UL)                    /*!< PIN12 (Bit 12)                                        */
#define GPIOx_PUR_PIN12_Msk               (0x1000UL)                /*!< PIN12 (Bitfield-Mask: 0x01)                           */
#define GPIOx_PUR_PIN11_Pos               (11UL)                    /*!< PIN11 (Bit 11)                                        */
#define GPIOx_PUR_PIN11_Msk               (0x800UL)                 /*!< PIN11 (Bitfield-Mask: 0x01)                           */
#define GPIOx_PUR_PIN10_Pos               (10UL)                    /*!< PIN10 (Bit 10)                                        */
#define GPIOx_PUR_PIN10_Msk               (0x400UL)                 /*!< PIN10 (Bitfield-Mask: 0x01)                           */
#define GPIOx_PUR_PIN9_Pos                (9UL)                     /*!< PIN9 (Bit 9)                                          */
#define GPIOx_PUR_PIN9_Msk                (0x200UL)                 /*!< PIN9 (Bitfield-Mask: 0x01)                            */
#define GPIOx_PUR_PIN8_Pos                (8UL)                     /*!< PIN8 (Bit 8)                                          */
#define GPIOx_PUR_PIN8_Msk                (0x100UL)                 /*!< PIN8 (Bitfield-Mask: 0x01)                            */
#define GPIOx_PUR_PIN7_Pos                (7UL)                     /*!< PIN7 (Bit 7)                                          */
#define GPIOx_PUR_PIN7_Msk                (0x80UL)                  /*!< PIN7 (Bitfield-Mask: 0x01)                            */
#define GPIOx_PUR_PIN6_Pos                (6UL)                     /*!< PIN6 (Bit 6)                                          */
#define GPIOx_PUR_PIN6_Msk                (0x40UL)                  /*!< PIN6 (Bitfield-Mask: 0x01)                            */
#define GPIOx_PUR_PIN5_Pos                (5UL)                     /*!< PIN5 (Bit 5)                                          */
#define GPIOx_PUR_PIN5_Msk                (0x20UL)                  /*!< PIN5 (Bitfield-Mask: 0x01)                            */
#define GPIOx_PUR_PIN4_Pos                (4UL)                     /*!< PIN4 (Bit 4)                                          */
#define GPIOx_PUR_PIN4_Msk                (0x10UL)                  /*!< PIN4 (Bitfield-Mask: 0x01)                            */
#define GPIOx_PUR_PIN3_Pos                (3UL)                     /*!< PIN3 (Bit 3)                                          */
#define GPIOx_PUR_PIN3_Msk                (0x8UL)                   /*!< PIN3 (Bitfield-Mask: 0x01)                            */
#define GPIOx_PUR_PIN2_Pos                (2UL)                     /*!< PIN2 (Bit 2)                                          */
#define GPIOx_PUR_PIN2_Msk                (0x4UL)                   /*!< PIN2 (Bitfield-Mask: 0x01)                            */
#define GPIOx_PUR_PIN1_Pos                (1UL)                     /*!< PIN1 (Bit 1)                                          */
#define GPIOx_PUR_PIN1_Msk                (0x2UL)                   /*!< PIN1 (Bitfield-Mask: 0x01)                            */
#define GPIOx_PUR_PIN0_Pos                (0UL)                     /*!< PIN0 (Bit 0)                                          */
#define GPIOx_PUR_PIN0_Msk                (0x1UL)                   /*!< PIN0 (Bitfield-Mask: 0x01)                            */
/* =========================================================  AFRH  ========================================================== */
#define GPIOx_AFRH_PIN15_Pos              (28UL)                    /*!< PIN15 (Bit 28)                                        */
#define GPIOx_AFRH_PIN15_Msk              (0xf0000000UL)            /*!< PIN15 (Bitfield-Mask: 0x0f)                           */
#define GPIOx_AFRH_PIN14_Pos              (24UL)                    /*!< PIN14 (Bit 24)                                        */
#define GPIOx_AFRH_PIN14_Msk              (0xf000000UL)             /*!< PIN14 (Bitfield-Mask: 0x0f)                           */
#define GPIOx_AFRH_PIN13_Pos              (20UL)                    /*!< PIN13 (Bit 20)                                        */
#define GPIOx_AFRH_PIN13_Msk              (0xf00000UL)              /*!< PIN13 (Bitfield-Mask: 0x0f)                           */
#define GPIOx_AFRH_PIN12_Pos              (16UL)                    /*!< PIN12 (Bit 16)                                        */
#define GPIOx_AFRH_PIN12_Msk              (0xf0000UL)               /*!< PIN12 (Bitfield-Mask: 0x0f)                           */
#define GPIOx_AFRH_PIN11_Pos              (12UL)                    /*!< PIN11 (Bit 12)                                        */
#define GPIOx_AFRH_PIN11_Msk              (0xf000UL)                /*!< PIN11 (Bitfield-Mask: 0x0f)                           */
#define GPIOx_AFRH_PIN10_Pos              (8UL)                     /*!< PIN10 (Bit 8)                                         */
#define GPIOx_AFRH_PIN10_Msk              (0xf00UL)                 /*!< PIN10 (Bitfield-Mask: 0x0f)                           */
#define GPIOx_AFRH_PIN9_Pos               (4UL)                     /*!< PIN9 (Bit 4)                                          */
#define GPIOx_AFRH_PIN9_Msk               (0xf0UL)                  /*!< PIN9 (Bitfield-Mask: 0x0f)                            */
#define GPIOx_AFRH_PIN8_Pos               (0UL)                     /*!< PIN8 (Bit 0)                                          */
#define GPIOx_AFRH_PIN8_Msk               (0xfUL)                   /*!< PIN8 (Bitfield-Mask: 0x0f)                            */
/* =========================================================  AFRL  ========================================================== */
#define GPIOx_AFRL_PIN7_Pos               (28UL)                    /*!< PIN7 (Bit 28)                                         */
#define GPIOx_AFRL_PIN7_Msk               (0xf0000000UL)            /*!< PIN7 (Bitfield-Mask: 0x0f)                            */
#define GPIOx_AFRL_PIN6_Pos               (24UL)                    /*!< PIN6 (Bit 24)                                         */
#define GPIOx_AFRL_PIN6_Msk               (0xf000000UL)             /*!< PIN6 (Bitfield-Mask: 0x0f)                            */
#define GPIOx_AFRL_PIN5_Pos               (20UL)                    /*!< PIN5 (Bit 20)                                         */
#define GPIOx_AFRL_PIN5_Msk               (0xf00000UL)              /*!< PIN5 (Bitfield-Mask: 0x0f)                            */
#define GPIOx_AFRL_PIN4_Pos               (16UL)                    /*!< PIN4 (Bit 16)                                         */
#define GPIOx_AFRL_PIN4_Msk               (0xf0000UL)               /*!< PIN4 (Bitfield-Mask: 0x0f)                            */
#define GPIOx_AFRL_PIN3_Pos               (12UL)                    /*!< PIN3 (Bit 12)                                         */
#define GPIOx_AFRL_PIN3_Msk               (0xf000UL)                /*!< PIN3 (Bitfield-Mask: 0x0f)                            */
#define GPIOx_AFRL_PIN2_Pos               (8UL)                     /*!< PIN2 (Bit 8)                                          */
#define GPIOx_AFRL_PIN2_Msk               (0xf00UL)                 /*!< PIN2 (Bitfield-Mask: 0x0f)                            */
#define GPIOx_AFRL_PIN1_Pos               (4UL)                     /*!< PIN1 (Bit 4)                                          */
#define GPIOx_AFRL_PIN1_Msk               (0xf0UL)                  /*!< PIN1 (Bitfield-Mask: 0x0f)                            */
#define GPIOx_AFRL_PIN0_Pos               (0UL)                     /*!< PIN0 (Bit 0)                                          */
#define GPIOx_AFRL_PIN0_Msk               (0xfUL)                   /*!< PIN0 (Bitfield-Mask: 0x0f)                            */
/* ========================================================  ANALOG  ========================================================= */
#define GPIOx_ANALOG_PIN15_Pos            (15UL)                    /*!< PIN15 (Bit 15)                                        */
#define GPIOx_ANALOG_PIN15_Msk            (0x8000UL)                /*!< PIN15 (Bitfield-Mask: 0x01)                           */
#define GPIOx_ANALOG_PIN14_Pos            (14UL)                    /*!< PIN14 (Bit 14)                                        */
#define GPIOx_ANALOG_PIN14_Msk            (0x4000UL)                /*!< PIN14 (Bitfield-Mask: 0x01)                           */
#define GPIOx_ANALOG_PIN13_Pos            (13UL)                    /*!< PIN13 (Bit 13)                                        */
#define GPIOx_ANALOG_PIN13_Msk            (0x2000UL)                /*!< PIN13 (Bitfield-Mask: 0x01)                           */
#define GPIOx_ANALOG_PIN12_Pos            (12UL)                    /*!< PIN12 (Bit 12)                                        */
#define GPIOx_ANALOG_PIN12_Msk            (0x1000UL)                /*!< PIN12 (Bitfield-Mask: 0x01)                           */
#define GPIOx_ANALOG_PIN11_Pos            (11UL)                    /*!< PIN11 (Bit 11)                                        */
#define GPIOx_ANALOG_PIN11_Msk            (0x800UL)                 /*!< PIN11 (Bitfield-Mask: 0x01)                           */
#define GPIOx_ANALOG_PIN10_Pos            (10UL)                    /*!< PIN10 (Bit 10)                                        */
#define GPIOx_ANALOG_PIN10_Msk            (0x400UL)                 /*!< PIN10 (Bitfield-Mask: 0x01)                           */
#define GPIOx_ANALOG_PIN9_Pos             (9UL)                     /*!< PIN9 (Bit 9)                                          */
#define GPIOx_ANALOG_PIN9_Msk             (0x200UL)                 /*!< PIN9 (Bitfield-Mask: 0x01)                            */
#define GPIOx_ANALOG_PIN8_Pos             (8UL)                     /*!< PIN8 (Bit 8)                                          */
#define GPIOx_ANALOG_PIN8_Msk             (0x100UL)                 /*!< PIN8 (Bitfield-Mask: 0x01)                            */
#define GPIOx_ANALOG_PIN7_Pos             (7UL)                     /*!< PIN7 (Bit 7)                                          */
#define GPIOx_ANALOG_PIN7_Msk             (0x80UL)                  /*!< PIN7 (Bitfield-Mask: 0x01)                            */
#define GPIOx_ANALOG_PIN6_Pos             (6UL)                     /*!< PIN6 (Bit 6)                                          */
#define GPIOx_ANALOG_PIN6_Msk             (0x40UL)                  /*!< PIN6 (Bitfield-Mask: 0x01)                            */
#define GPIOx_ANALOG_PIN5_Pos             (5UL)                     /*!< PIN5 (Bit 5)                                          */
#define GPIOx_ANALOG_PIN5_Msk             (0x20UL)                  /*!< PIN5 (Bitfield-Mask: 0x01)                            */
#define GPIOx_ANALOG_PIN4_Pos             (4UL)                     /*!< PIN4 (Bit 4)                                          */
#define GPIOx_ANALOG_PIN4_Msk             (0x10UL)                  /*!< PIN4 (Bitfield-Mask: 0x01)                            */
#define GPIOx_ANALOG_PIN3_Pos             (3UL)                     /*!< PIN3 (Bit 3)                                          */
#define GPIOx_ANALOG_PIN3_Msk             (0x8UL)                   /*!< PIN3 (Bitfield-Mask: 0x01)                            */
#define GPIOx_ANALOG_PIN2_Pos             (2UL)                     /*!< PIN2 (Bit 2)                                          */
#define GPIOx_ANALOG_PIN2_Msk             (0x4UL)                   /*!< PIN2 (Bitfield-Mask: 0x01)                            */
#define GPIOx_ANALOG_PIN1_Pos             (1UL)                     /*!< PIN1 (Bit 1)                                          */
#define GPIOx_ANALOG_PIN1_Msk             (0x2UL)                   /*!< PIN1 (Bitfield-Mask: 0x01)                            */
#define GPIOx_ANALOG_PIN0_Pos             (0UL)                     /*!< PIN0 (Bit 0)                                          */
#define GPIOx_ANALOG_PIN0_Msk             (0x1UL)                   /*!< PIN0 (Bitfield-Mask: 0x01)                            */
/* ========================================================  RISEIE  ========================================================= */
#define GPIOx_RISEIE_PIN15_Pos            (15UL)                    /*!< PIN15 (Bit 15)                                        */
#define GPIOx_RISEIE_PIN15_Msk            (0x8000UL)                /*!< PIN15 (Bitfield-Mask: 0x01)                           */
#define GPIOx_RISEIE_PIN14_Pos            (14UL)                    /*!< PIN14 (Bit 14)                                        */
#define GPIOx_RISEIE_PIN14_Msk            (0x4000UL)                /*!< PIN14 (Bitfield-Mask: 0x01)                           */
#define GPIOx_RISEIE_PIN13_Pos            (13UL)                    /*!< PIN13 (Bit 13)                                        */
#define GPIOx_RISEIE_PIN13_Msk            (0x2000UL)                /*!< PIN13 (Bitfield-Mask: 0x01)                           */
#define GPIOx_RISEIE_PIN12_Pos            (12UL)                    /*!< PIN12 (Bit 12)                                        */
#define GPIOx_RISEIE_PIN12_Msk            (0x1000UL)                /*!< PIN12 (Bitfield-Mask: 0x01)                           */
#define GPIOx_RISEIE_PIN11_Pos            (11UL)                    /*!< PIN11 (Bit 11)                                        */
#define GPIOx_RISEIE_PIN11_Msk            (0x800UL)                 /*!< PIN11 (Bitfield-Mask: 0x01)                           */
#define GPIOx_RISEIE_PIN10_Pos            (10UL)                    /*!< PIN10 (Bit 10)                                        */
#define GPIOx_RISEIE_PIN10_Msk            (0x400UL)                 /*!< PIN10 (Bitfield-Mask: 0x01)                           */
#define GPIOx_RISEIE_PIN9_Pos             (9UL)                     /*!< PIN9 (Bit 9)                                          */
#define GPIOx_RISEIE_PIN9_Msk             (0x200UL)                 /*!< PIN9 (Bitfield-Mask: 0x01)                            */
#define GPIOx_RISEIE_PIN8_Pos             (8UL)                     /*!< PIN8 (Bit 8)                                          */
#define GPIOx_RISEIE_PIN8_Msk             (0x100UL)                 /*!< PIN8 (Bitfield-Mask: 0x01)                            */
#define GPIOx_RISEIE_PIN7_Pos             (7UL)                     /*!< PIN7 (Bit 7)                                          */
#define GPIOx_RISEIE_PIN7_Msk             (0x80UL)                  /*!< PIN7 (Bitfield-Mask: 0x01)                            */
#define GPIOx_RISEIE_PIN6_Pos             (6UL)                     /*!< PIN6 (Bit 6)                                          */
#define GPIOx_RISEIE_PIN6_Msk             (0x40UL)                  /*!< PIN6 (Bitfield-Mask: 0x01)                            */
#define GPIOx_RISEIE_PIN5_Pos             (5UL)                     /*!< PIN5 (Bit 5)                                          */
#define GPIOx_RISEIE_PIN5_Msk             (0x20UL)                  /*!< PIN5 (Bitfield-Mask: 0x01)                            */
#define GPIOx_RISEIE_PIN4_Pos             (4UL)                     /*!< PIN4 (Bit 4)                                          */
#define GPIOx_RISEIE_PIN4_Msk             (0x10UL)                  /*!< PIN4 (Bitfield-Mask: 0x01)                            */
#define GPIOx_RISEIE_PIN3_Pos             (3UL)                     /*!< PIN3 (Bit 3)                                          */
#define GPIOx_RISEIE_PIN3_Msk             (0x8UL)                   /*!< PIN3 (Bitfield-Mask: 0x01)                            */
#define GPIOx_RISEIE_PIN2_Pos             (2UL)                     /*!< PIN2 (Bit 2)                                          */
#define GPIOx_RISEIE_PIN2_Msk             (0x4UL)                   /*!< PIN2 (Bitfield-Mask: 0x01)                            */
#define GPIOx_RISEIE_PIN1_Pos             (1UL)                     /*!< PIN1 (Bit 1)                                          */
#define GPIOx_RISEIE_PIN1_Msk             (0x2UL)                   /*!< PIN1 (Bitfield-Mask: 0x01)                            */
#define GPIOx_RISEIE_PIN0_Pos             (0UL)                     /*!< PIN0 (Bit 0)                                          */
#define GPIOx_RISEIE_PIN0_Msk             (0x1UL)                   /*!< PIN0 (Bitfield-Mask: 0x01)                            */
/* ========================================================  FALLIE  ========================================================= */
#define GPIOx_FALLIE_PIN15_Pos            (15UL)                    /*!< PIN15 (Bit 15)                                        */
#define GPIOx_FALLIE_PIN15_Msk            (0x8000UL)                /*!< PIN15 (Bitfield-Mask: 0x01)                           */
#define GPIOx_FALLIE_PIN14_Pos            (14UL)                    /*!< PIN14 (Bit 14)                                        */
#define GPIOx_FALLIE_PIN14_Msk            (0x4000UL)                /*!< PIN14 (Bitfield-Mask: 0x01)                           */
#define GPIOx_FALLIE_PIN13_Pos            (13UL)                    /*!< PIN13 (Bit 13)                                        */
#define GPIOx_FALLIE_PIN13_Msk            (0x2000UL)                /*!< PIN13 (Bitfield-Mask: 0x01)                           */
#define GPIOx_FALLIE_PIN12_Pos            (12UL)                    /*!< PIN12 (Bit 12)                                        */
#define GPIOx_FALLIE_PIN12_Msk            (0x1000UL)                /*!< PIN12 (Bitfield-Mask: 0x01)                           */
#define GPIOx_FALLIE_PIN11_Pos            (11UL)                    /*!< PIN11 (Bit 11)                                        */
#define GPIOx_FALLIE_PIN11_Msk            (0x800UL)                 /*!< PIN11 (Bitfield-Mask: 0x01)                           */
#define GPIOx_FALLIE_PIN10_Pos            (10UL)                    /*!< PIN10 (Bit 10)                                        */
#define GPIOx_FALLIE_PIN10_Msk            (0x400UL)                 /*!< PIN10 (Bitfield-Mask: 0x01)                           */
#define GPIOx_FALLIE_PIN9_Pos             (9UL)                     /*!< PIN9 (Bit 9)                                          */
#define GPIOx_FALLIE_PIN9_Msk             (0x200UL)                 /*!< PIN9 (Bitfield-Mask: 0x01)                            */
#define GPIOx_FALLIE_PIN8_Pos             (8UL)                     /*!< PIN8 (Bit 8)                                          */
#define GPIOx_FALLIE_PIN8_Msk             (0x100UL)                 /*!< PIN8 (Bitfield-Mask: 0x01)                            */
#define GPIOx_FALLIE_PIN7_Pos             (7UL)                     /*!< PIN7 (Bit 7)                                          */
#define GPIOx_FALLIE_PIN7_Msk             (0x80UL)                  /*!< PIN7 (Bitfield-Mask: 0x01)                            */
#define GPIOx_FALLIE_PIN6_Pos             (6UL)                     /*!< PIN6 (Bit 6)                                          */
#define GPIOx_FALLIE_PIN6_Msk             (0x40UL)                  /*!< PIN6 (Bitfield-Mask: 0x01)                            */
#define GPIOx_FALLIE_PIN5_Pos             (5UL)                     /*!< PIN5 (Bit 5)                                          */
#define GPIOx_FALLIE_PIN5_Msk             (0x20UL)                  /*!< PIN5 (Bitfield-Mask: 0x01)                            */
#define GPIOx_FALLIE_PIN4_Pos             (4UL)                     /*!< PIN4 (Bit 4)                                          */
#define GPIOx_FALLIE_PIN4_Msk             (0x10UL)                  /*!< PIN4 (Bitfield-Mask: 0x01)                            */
#define GPIOx_FALLIE_PIN3_Pos             (3UL)                     /*!< PIN3 (Bit 3)                                          */
#define GPIOx_FALLIE_PIN3_Msk             (0x8UL)                   /*!< PIN3 (Bitfield-Mask: 0x01)                            */
#define GPIOx_FALLIE_PIN2_Pos             (2UL)                     /*!< PIN2 (Bit 2)                                          */
#define GPIOx_FALLIE_PIN2_Msk             (0x4UL)                   /*!< PIN2 (Bitfield-Mask: 0x01)                            */
#define GPIOx_FALLIE_PIN1_Pos             (1UL)                     /*!< PIN1 (Bit 1)                                          */
#define GPIOx_FALLIE_PIN1_Msk             (0x2UL)                   /*!< PIN1 (Bitfield-Mask: 0x01)                            */
#define GPIOx_FALLIE_PIN0_Pos             (0UL)                     /*!< PIN0 (Bit 0)                                          */
#define GPIOx_FALLIE_PIN0_Msk             (0x1UL)                   /*!< PIN0 (Bitfield-Mask: 0x01)                            */
/* ==========================================================  ISR  ========================================================== */
#define GPIOx_ISR_PIN15_Pos               (15UL)                    /*!< PIN15 (Bit 15)                                        */
#define GPIOx_ISR_PIN15_Msk               (0x8000UL)                /*!< PIN15 (Bitfield-Mask: 0x01)                           */
#define GPIOx_ISR_PIN14_Pos               (14UL)                    /*!< PIN14 (Bit 14)                                        */
#define GPIOx_ISR_PIN14_Msk               (0x4000UL)                /*!< PIN14 (Bitfield-Mask: 0x01)                           */
#define GPIOx_ISR_PIN13_Pos               (13UL)                    /*!< PIN13 (Bit 13)                                        */
#define GPIOx_ISR_PIN13_Msk               (0x2000UL)                /*!< PIN13 (Bitfield-Mask: 0x01)                           */
#define GPIOx_ISR_PIN12_Pos               (12UL)                    /*!< PIN12 (Bit 12)                                        */
#define GPIOx_ISR_PIN12_Msk               (0x1000UL)                /*!< PIN12 (Bitfield-Mask: 0x01)                           */
#define GPIOx_ISR_PIN11_Pos               (11UL)                    /*!< PIN11 (Bit 11)                                        */
#define GPIOx_ISR_PIN11_Msk               (0x800UL)                 /*!< PIN11 (Bitfield-Mask: 0x01)                           */
#define GPIOx_ISR_PIN10_Pos               (10UL)                    /*!< PIN10 (Bit 10)                                        */
#define GPIOx_ISR_PIN10_Msk               (0x400UL)                 /*!< PIN10 (Bitfield-Mask: 0x01)                           */
#define GPIOx_ISR_PIN9_Pos                (9UL)                     /*!< PIN9 (Bit 9)                                          */
#define GPIOx_ISR_PIN9_Msk                (0x200UL)                 /*!< PIN9 (Bitfield-Mask: 0x01)                            */
#define GPIOx_ISR_PIN8_Pos                (8UL)                     /*!< PIN8 (Bit 8)                                          */
#define GPIOx_ISR_PIN8_Msk                (0x100UL)                 /*!< PIN8 (Bitfield-Mask: 0x01)                            */
#define GPIOx_ISR_PIN7_Pos                (7UL)                     /*!< PIN7 (Bit 7)                                          */
#define GPIOx_ISR_PIN7_Msk                (0x80UL)                  /*!< PIN7 (Bitfield-Mask: 0x01)                            */
#define GPIOx_ISR_PIN6_Pos                (6UL)                     /*!< PIN6 (Bit 6)                                          */
#define GPIOx_ISR_PIN6_Msk                (0x40UL)                  /*!< PIN6 (Bitfield-Mask: 0x01)                            */
#define GPIOx_ISR_PIN5_Pos                (5UL)                     /*!< PIN5 (Bit 5)                                          */
#define GPIOx_ISR_PIN5_Msk                (0x20UL)                  /*!< PIN5 (Bitfield-Mask: 0x01)                            */
#define GPIOx_ISR_PIN4_Pos                (4UL)                     /*!< PIN4 (Bit 4)                                          */
#define GPIOx_ISR_PIN4_Msk                (0x10UL)                  /*!< PIN4 (Bitfield-Mask: 0x01)                            */
#define GPIOx_ISR_PIN3_Pos                (3UL)                     /*!< PIN3 (Bit 3)                                          */
#define GPIOx_ISR_PIN3_Msk                (0x8UL)                   /*!< PIN3 (Bitfield-Mask: 0x01)                            */
#define GPIOx_ISR_PIN2_Pos                (2UL)                     /*!< PIN2 (Bit 2)                                          */
#define GPIOx_ISR_PIN2_Msk                (0x4UL)                   /*!< PIN2 (Bitfield-Mask: 0x01)                            */
#define GPIOx_ISR_PIN1_Pos                (1UL)                     /*!< PIN1 (Bit 1)                                          */
#define GPIOx_ISR_PIN1_Msk                (0x2UL)                   /*!< PIN1 (Bitfield-Mask: 0x01)                            */
#define GPIOx_ISR_PIN0_Pos                (0UL)                     /*!< PIN0 (Bit 0)                                          */
#define GPIOx_ISR_PIN0_Msk                (0x1UL)                   /*!< PIN0 (Bitfield-Mask: 0x01)                            */
/* ==========================================================  ICR  ========================================================== */
#define GPIOx_ICR_PIN15_Pos               (15UL)                    /*!< PIN15 (Bit 15)                                        */
#define GPIOx_ICR_PIN15_Msk               (0x8000UL)                /*!< PIN15 (Bitfield-Mask: 0x01)                           */
#define GPIOx_ICR_PIN14_Pos               (14UL)                    /*!< PIN14 (Bit 14)                                        */
#define GPIOx_ICR_PIN14_Msk               (0x4000UL)                /*!< PIN14 (Bitfield-Mask: 0x01)                           */
#define GPIOx_ICR_PIN13_Pos               (13UL)                    /*!< PIN13 (Bit 13)                                        */
#define GPIOx_ICR_PIN13_Msk               (0x2000UL)                /*!< PIN13 (Bitfield-Mask: 0x01)                           */
#define GPIOx_ICR_PIN12_Pos               (12UL)                    /*!< PIN12 (Bit 12)                                        */
#define GPIOx_ICR_PIN12_Msk               (0x1000UL)                /*!< PIN12 (Bitfield-Mask: 0x01)                           */
#define GPIOx_ICR_PIN11_Pos               (11UL)                    /*!< PIN11 (Bit 11)                                        */
#define GPIOx_ICR_PIN11_Msk               (0x800UL)                 /*!< PIN11 (Bitfield-Mask: 0x01)                           */
#define GPIOx_ICR_PIN10_Pos               (10UL)                    /*!< PIN10 (Bit 10)                                        */
#define GPIOx_ICR_PIN10_Msk               (0x400UL)                 /*!< PIN10 (Bitfield-Mask: 0x01)                           */
#define GPIOx_ICR_PIN9_Pos                (9UL)                     /*!< PIN9 (Bit 9)                                          */
#define GPIOx_ICR_PIN9_Msk                (0x200UL)                 /*!< PIN9 (Bitfield-Mask: 0x01)                            */
#define GPIOx_ICR_PIN8_Pos                (8UL)                     /*!< PIN8 (Bit 8)                                          */
#define GPIOx_ICR_PIN8_Msk                (0x100UL)                 /*!< PIN8 (Bitfield-Mask: 0x01)                            */
#define GPIOx_ICR_PIN7_Pos                (7UL)                     /*!< PIN7 (Bit 7)                                          */
#define GPIOx_ICR_PIN7_Msk                (0x80UL)                  /*!< PIN7 (Bitfield-Mask: 0x01)                            */
#define GPIOx_ICR_PIN6_Pos                (6UL)                     /*!< PIN6 (Bit 6)                                          */
#define GPIOx_ICR_PIN6_Msk                (0x40UL)                  /*!< PIN6 (Bitfield-Mask: 0x01)                            */
#define GPIOx_ICR_PIN5_Pos                (5UL)                     /*!< PIN5 (Bit 5)                                          */
#define GPIOx_ICR_PIN5_Msk                (0x20UL)                  /*!< PIN5 (Bitfield-Mask: 0x01)                            */
#define GPIOx_ICR_PIN4_Pos                (4UL)                     /*!< PIN4 (Bit 4)                                          */
#define GPIOx_ICR_PIN4_Msk                (0x10UL)                  /*!< PIN4 (Bitfield-Mask: 0x01)                            */
#define GPIOx_ICR_PIN3_Pos                (3UL)                     /*!< PIN3 (Bit 3)                                          */
#define GPIOx_ICR_PIN3_Msk                (0x8UL)                   /*!< PIN3 (Bitfield-Mask: 0x01)                            */
#define GPIOx_ICR_PIN2_Pos                (2UL)                     /*!< PIN2 (Bit 2)                                          */
#define GPIOx_ICR_PIN2_Msk                (0x4UL)                   /*!< PIN2 (Bitfield-Mask: 0x01)                            */
#define GPIOx_ICR_PIN1_Pos                (1UL)                     /*!< PIN1 (Bit 1)                                          */
#define GPIOx_ICR_PIN1_Msk                (0x2UL)                   /*!< PIN1 (Bitfield-Mask: 0x01)                            */
#define GPIOx_ICR_PIN0_Pos                (0UL)                     /*!< PIN0 (Bit 0)                                          */
#define GPIOx_ICR_PIN0_Msk                (0x1UL)                   /*!< PIN0 (Bitfield-Mask: 0x01)                            */
/* ========================================================  FILTER  ========================================================= */
#define GPIOx_FILTER_FLTCLK_Pos           (16UL)                    /*!< FLTCLK (Bit 16)                                       */
#define GPIOx_FILTER_FLTCLK_Msk           (0x70000UL)               /*!< FLTCLK (Bitfield-Mask: 0x07)                          */
#define GPIOx_FILTER_PIN15_Pos            (15UL)                    /*!< PIN15 (Bit 15)                                        */
#define GPIOx_FILTER_PIN15_Msk            (0x8000UL)                /*!< PIN15 (Bitfield-Mask: 0x01)                           */
#define GPIOx_FILTER_PIN14_Pos            (14UL)                    /*!< PIN14 (Bit 14)                                        */
#define GPIOx_FILTER_PIN14_Msk            (0x4000UL)                /*!< PIN14 (Bitfield-Mask: 0x01)                           */
#define GPIOx_FILTER_PIN13_Pos            (13UL)                    /*!< PIN13 (Bit 13)                                        */
#define GPIOx_FILTER_PIN13_Msk            (0x2000UL)                /*!< PIN13 (Bitfield-Mask: 0x01)                           */
#define GPIOx_FILTER_PIN12_Pos            (12UL)                    /*!< PIN12 (Bit 12)                                        */
#define GPIOx_FILTER_PIN12_Msk            (0x1000UL)                /*!< PIN12 (Bitfield-Mask: 0x01)                           */
#define GPIOx_FILTER_PIN11_Pos            (11UL)                    /*!< PIN11 (Bit 11)                                        */
#define GPIOx_FILTER_PIN11_Msk            (0x800UL)                 /*!< PIN11 (Bitfield-Mask: 0x01)                           */
#define GPIOx_FILTER_PIN10_Pos            (10UL)                    /*!< PIN10 (Bit 10)                                        */
#define GPIOx_FILTER_PIN10_Msk            (0x400UL)                 /*!< PIN10 (Bitfield-Mask: 0x01)                           */
#define GPIOx_FILTER_PIN9_Pos             (9UL)                     /*!< PIN9 (Bit 9)                                          */
#define GPIOx_FILTER_PIN9_Msk             (0x200UL)                 /*!< PIN9 (Bitfield-Mask: 0x01)                            */
#define GPIOx_FILTER_PIN8_Pos             (8UL)                     /*!< PIN8 (Bit 8)                                          */
#define GPIOx_FILTER_PIN8_Msk             (0x100UL)                 /*!< PIN8 (Bitfield-Mask: 0x01)                            */
#define GPIOx_FILTER_PIN7_Pos             (7UL)                     /*!< PIN7 (Bit 7)                                          */
#define GPIOx_FILTER_PIN7_Msk             (0x80UL)                  /*!< PIN7 (Bitfield-Mask: 0x01)                            */
#define GPIOx_FILTER_PIN6_Pos             (6UL)                     /*!< PIN6 (Bit 6)                                          */
#define GPIOx_FILTER_PIN6_Msk             (0x40UL)                  /*!< PIN6 (Bitfield-Mask: 0x01)                            */
#define GPIOx_FILTER_PIN5_Pos             (5UL)                     /*!< PIN5 (Bit 5)                                          */
#define GPIOx_FILTER_PIN5_Msk             (0x20UL)                  /*!< PIN5 (Bitfield-Mask: 0x01)                            */
#define GPIOx_FILTER_PIN4_Pos             (4UL)                     /*!< PIN4 (Bit 4)                                          */
#define GPIOx_FILTER_PIN4_Msk             (0x10UL)                  /*!< PIN4 (Bitfield-Mask: 0x01)                            */
#define GPIOx_FILTER_PIN3_Pos             (3UL)                     /*!< PIN3 (Bit 3)                                          */
#define GPIOx_FILTER_PIN3_Msk             (0x8UL)                   /*!< PIN3 (Bitfield-Mask: 0x01)                            */
#define GPIOx_FILTER_PIN2_Pos             (2UL)                     /*!< PIN2 (Bit 2)                                          */
#define GPIOx_FILTER_PIN2_Msk             (0x4UL)                   /*!< PIN2 (Bitfield-Mask: 0x01)                            */
#define GPIOx_FILTER_PIN1_Pos             (1UL)                     /*!< PIN1 (Bit 1)                                          */
#define GPIOx_FILTER_PIN1_Msk             (0x2UL)                   /*!< PIN1 (Bitfield-Mask: 0x01)                            */
#define GPIOx_FILTER_PIN0_Pos             (0UL)                     /*!< PIN0 (Bit 0)                                          */
#define GPIOx_FILTER_PIN0_Msk             (0x1UL)                   /*!< PIN0 (Bitfield-Mask: 0x01)                            */
/* ==========================================================  IDR  ========================================================== */
#define GPIOx_IDR_PIN15_Pos               (15UL)                    /*!< PIN15 (Bit 15)                                        */
#define GPIOx_IDR_PIN15_Msk               (0x8000UL)                /*!< PIN15 (Bitfield-Mask: 0x01)                           */
#define GPIOx_IDR_PIN14_Pos               (14UL)                    /*!< PIN14 (Bit 14)                                        */
#define GPIOx_IDR_PIN14_Msk               (0x4000UL)                /*!< PIN14 (Bitfield-Mask: 0x01)                           */
#define GPIOx_IDR_PIN13_Pos               (13UL)                    /*!< PIN13 (Bit 13)                                        */
#define GPIOx_IDR_PIN13_Msk               (0x2000UL)                /*!< PIN13 (Bitfield-Mask: 0x01)                           */
#define GPIOx_IDR_PIN12_Pos               (12UL)                    /*!< PIN12 (Bit 12)                                        */
#define GPIOx_IDR_PIN12_Msk               (0x1000UL)                /*!< PIN12 (Bitfield-Mask: 0x01)                           */
#define GPIOx_IDR_PIN11_Pos               (11UL)                    /*!< PIN11 (Bit 11)                                        */
#define GPIOx_IDR_PIN11_Msk               (0x800UL)                 /*!< PIN11 (Bitfield-Mask: 0x01)                           */
#define GPIOx_IDR_PIN10_Pos               (10UL)                    /*!< PIN10 (Bit 10)                                        */
#define GPIOx_IDR_PIN10_Msk               (0x400UL)                 /*!< PIN10 (Bitfield-Mask: 0x01)                           */
#define GPIOx_IDR_PIN9_Pos                (9UL)                     /*!< PIN9 (Bit 9)                                          */
#define GPIOx_IDR_PIN9_Msk                (0x200UL)                 /*!< PIN9 (Bitfield-Mask: 0x01)                            */
#define GPIOx_IDR_PIN8_Pos                (8UL)                     /*!< PIN8 (Bit 8)                                          */
#define GPIOx_IDR_PIN8_Msk                (0x100UL)                 /*!< PIN8 (Bitfield-Mask: 0x01)                            */
#define GPIOx_IDR_PIN7_Pos                (7UL)                     /*!< PIN7 (Bit 7)                                          */
#define GPIOx_IDR_PIN7_Msk                (0x80UL)                  /*!< PIN7 (Bitfield-Mask: 0x01)                            */
#define GPIOx_IDR_PIN6_Pos                (6UL)                     /*!< PIN6 (Bit 6)                                          */
#define GPIOx_IDR_PIN6_Msk                (0x40UL)                  /*!< PIN6 (Bitfield-Mask: 0x01)                            */
#define GPIOx_IDR_PIN5_Pos                (5UL)                     /*!< PIN5 (Bit 5)                                          */
#define GPIOx_IDR_PIN5_Msk                (0x20UL)                  /*!< PIN5 (Bitfield-Mask: 0x01)                            */
#define GPIOx_IDR_PIN4_Pos                (4UL)                     /*!< PIN4 (Bit 4)                                          */
#define GPIOx_IDR_PIN4_Msk                (0x10UL)                  /*!< PIN4 (Bitfield-Mask: 0x01)                            */
#define GPIOx_IDR_PIN3_Pos                (3UL)                     /*!< PIN3 (Bit 3)                                          */
#define GPIOx_IDR_PIN3_Msk                (0x8UL)                   /*!< PIN3 (Bitfield-Mask: 0x01)                            */
#define GPIOx_IDR_PIN2_Pos                (2UL)                     /*!< PIN2 (Bit 2)                                          */
#define GPIOx_IDR_PIN2_Msk                (0x4UL)                   /*!< PIN2 (Bitfield-Mask: 0x01)                            */
#define GPIOx_IDR_PIN1_Pos                (1UL)                     /*!< PIN1 (Bit 1)                                          */
#define GPIOx_IDR_PIN1_Msk                (0x2UL)                   /*!< PIN1 (Bitfield-Mask: 0x01)                            */
#define GPIOx_IDR_PIN0_Pos                (0UL)                     /*!< PIN0 (Bit 0)                                          */
#define GPIOx_IDR_PIN0_Msk                (0x1UL)                   /*!< PIN0 (Bitfield-Mask: 0x01)                            */
/* ==========================================================  ODR  ========================================================== */
#define GPIOx_ODR_PIN15_Pos               (15UL)                    /*!< PIN15 (Bit 15)                                        */
#define GPIOx_ODR_PIN15_Msk               (0x8000UL)                /*!< PIN15 (Bitfield-Mask: 0x01)                           */
#define GPIOx_ODR_PIN14_Pos               (14UL)                    /*!< PIN14 (Bit 14)                                        */
#define GPIOx_ODR_PIN14_Msk               (0x4000UL)                /*!< PIN14 (Bitfield-Mask: 0x01)                           */
#define GPIOx_ODR_PIN13_Pos               (13UL)                    /*!< PIN13 (Bit 13)                                        */
#define GPIOx_ODR_PIN13_Msk               (0x2000UL)                /*!< PIN13 (Bitfield-Mask: 0x01)                           */
#define GPIOx_ODR_PIN12_Pos               (12UL)                    /*!< PIN12 (Bit 12)                                        */
#define GPIOx_ODR_PIN12_Msk               (0x1000UL)                /*!< PIN12 (Bitfield-Mask: 0x01)                           */
#define GPIOx_ODR_PIN11_Pos               (11UL)                    /*!< PIN11 (Bit 11)                                        */
#define GPIOx_ODR_PIN11_Msk               (0x800UL)                 /*!< PIN11 (Bitfield-Mask: 0x01)                           */
#define GPIOx_ODR_PIN10_Pos               (10UL)                    /*!< PIN10 (Bit 10)                                        */
#define GPIOx_ODR_PIN10_Msk               (0x400UL)                 /*!< PIN10 (Bitfield-Mask: 0x01)                           */
#define GPIOx_ODR_PIN9_Pos                (9UL)                     /*!< PIN9 (Bit 9)                                          */
#define GPIOx_ODR_PIN9_Msk                (0x200UL)                 /*!< PIN9 (Bitfield-Mask: 0x01)                            */
#define GPIOx_ODR_PIN8_Pos                (8UL)                     /*!< PIN8 (Bit 8)                                          */
#define GPIOx_ODR_PIN8_Msk                (0x100UL)                 /*!< PIN8 (Bitfield-Mask: 0x01)                            */
#define GPIOx_ODR_PIN7_Pos                (7UL)                     /*!< PIN7 (Bit 7)                                          */
#define GPIOx_ODR_PIN7_Msk                (0x80UL)                  /*!< PIN7 (Bitfield-Mask: 0x01)                            */
#define GPIOx_ODR_PIN6_Pos                (6UL)                     /*!< PIN6 (Bit 6)                                          */
#define GPIOx_ODR_PIN6_Msk                (0x40UL)                  /*!< PIN6 (Bitfield-Mask: 0x01)                            */
#define GPIOx_ODR_PIN5_Pos                (5UL)                     /*!< PIN5 (Bit 5)                                          */
#define GPIOx_ODR_PIN5_Msk                (0x20UL)                  /*!< PIN5 (Bitfield-Mask: 0x01)                            */
#define GPIOx_ODR_PIN4_Pos                (4UL)                     /*!< PIN4 (Bit 4)                                          */
#define GPIOx_ODR_PIN4_Msk                (0x10UL)                  /*!< PIN4 (Bitfield-Mask: 0x01)                            */
#define GPIOx_ODR_PIN3_Pos                (3UL)                     /*!< PIN3 (Bit 3)                                          */
#define GPIOx_ODR_PIN3_Msk                (0x8UL)                   /*!< PIN3 (Bitfield-Mask: 0x01)                            */
#define GPIOx_ODR_PIN2_Pos                (2UL)                     /*!< PIN2 (Bit 2)                                          */
#define GPIOx_ODR_PIN2_Msk                (0x4UL)                   /*!< PIN2 (Bitfield-Mask: 0x01)                            */
#define GPIOx_ODR_PIN1_Pos                (1UL)                     /*!< PIN1 (Bit 1)                                          */
#define GPIOx_ODR_PIN1_Msk                (0x2UL)                   /*!< PIN1 (Bitfield-Mask: 0x01)                            */
#define GPIOx_ODR_PIN0_Pos                (0UL)                     /*!< PIN0 (Bit 0)                                          */
#define GPIOx_ODR_PIN0_Msk                (0x1UL)                   /*!< PIN0 (Bitfield-Mask: 0x01)                            */
/* ==========================================================  BRR  ========================================================== */
#define GPIOx_BRR_BRR15_Pos               (15UL)                    /*!< BRR15 (Bit 15)                                        */
#define GPIOx_BRR_BRR15_Msk               (0x8000UL)                /*!< BRR15 (Bitfield-Mask: 0x01)                           */
#define GPIOx_BRR_BRR14_Pos               (14UL)                    /*!< BRR14 (Bit 14)                                        */
#define GPIOx_BRR_BRR14_Msk               (0x4000UL)                /*!< BRR14 (Bitfield-Mask: 0x01)                           */
#define GPIOx_BRR_BRR13_Pos               (13UL)                    /*!< BRR13 (Bit 13)                                        */
#define GPIOx_BRR_BRR13_Msk               (0x2000UL)                /*!< BRR13 (Bitfield-Mask: 0x01)                           */
#define GPIOx_BRR_BRR12_Pos               (12UL)                    /*!< BRR12 (Bit 12)                                        */
#define GPIOx_BRR_BRR12_Msk               (0x1000UL)                /*!< BRR12 (Bitfield-Mask: 0x01)                           */
#define GPIOx_BRR_BRR11_Pos               (11UL)                    /*!< BRR11 (Bit 11)                                        */
#define GPIOx_BRR_BRR11_Msk               (0x800UL)                 /*!< BRR11 (Bitfield-Mask: 0x01)                           */
#define GPIOx_BRR_BRR10_Pos               (10UL)                    /*!< BRR10 (Bit 10)                                        */
#define GPIOx_BRR_BRR10_Msk               (0x400UL)                 /*!< BRR10 (Bitfield-Mask: 0x01)                           */
#define GPIOx_BRR_BRR9_Pos                (9UL)                     /*!< BRR9 (Bit 9)                                          */
#define GPIOx_BRR_BRR9_Msk                (0x200UL)                 /*!< BRR9 (Bitfield-Mask: 0x01)                            */
#define GPIOx_BRR_BRR8_Pos                (8UL)                     /*!< BRR8 (Bit 8)                                          */
#define GPIOx_BRR_BRR8_Msk                (0x100UL)                 /*!< BRR8 (Bitfield-Mask: 0x01)                            */
#define GPIOx_BRR_BRR7_Pos                (7UL)                     /*!< BRR7 (Bit 7)                                          */
#define GPIOx_BRR_BRR7_Msk                (0x80UL)                  /*!< BRR7 (Bitfield-Mask: 0x01)                            */
#define GPIOx_BRR_BRR6_Pos                (6UL)                     /*!< BRR6 (Bit 6)                                          */
#define GPIOx_BRR_BRR6_Msk                (0x40UL)                  /*!< BRR6 (Bitfield-Mask: 0x01)                            */
#define GPIOx_BRR_BRR5_Pos                (5UL)                     /*!< BRR5 (Bit 5)                                          */
#define GPIOx_BRR_BRR5_Msk                (0x20UL)                  /*!< BRR5 (Bitfield-Mask: 0x01)                            */
#define GPIOx_BRR_BRR4_Pos                (4UL)                     /*!< BRR4 (Bit 4)                                          */
#define GPIOx_BRR_BRR4_Msk                (0x10UL)                  /*!< BRR4 (Bitfield-Mask: 0x01)                            */
#define GPIOx_BRR_BRR3_Pos                (3UL)                     /*!< BRR3 (Bit 3)                                          */
#define GPIOx_BRR_BRR3_Msk                (0x8UL)                   /*!< BRR3 (Bitfield-Mask: 0x01)                            */
#define GPIOx_BRR_BRR2_Pos                (2UL)                     /*!< BRR2 (Bit 2)                                          */
#define GPIOx_BRR_BRR2_Msk                (0x4UL)                   /*!< BRR2 (Bitfield-Mask: 0x01)                            */
#define GPIOx_BRR_BRR1_Pos                (1UL)                     /*!< BRR1 (Bit 1)                                          */
#define GPIOx_BRR_BRR1_Msk                (0x2UL)                   /*!< BRR1 (Bitfield-Mask: 0x01)                            */
#define GPIOx_BRR_BRR0_Pos                (0UL)                     /*!< BRR0 (Bit 0)                                          */
#define GPIOx_BRR_BRR0_Msk                (0x1UL)                   /*!< BRR0 (Bitfield-Mask: 0x01)                            */
/* =========================================================  BSRR  ========================================================== */
#define GPIOx_BSRR_BRR15_Pos              (31UL)                    /*!< BRR15 (Bit 31)                                        */
#define GPIOx_BSRR_BRR15_Msk              (0x80000000UL)            /*!< BRR15 (Bitfield-Mask: 0x01)                           */
#define GPIOx_BSRR_BRR14_Pos              (30UL)                    /*!< BRR14 (Bit 30)                                        */
#define GPIOx_BSRR_BRR14_Msk              (0x40000000UL)            /*!< BRR14 (Bitfield-Mask: 0x01)                           */
#define GPIOx_BSRR_BRR13_Pos              (29UL)                    /*!< BRR13 (Bit 29)                                        */
#define GPIOx_BSRR_BRR13_Msk              (0x20000000UL)            /*!< BRR13 (Bitfield-Mask: 0x01)                           */
#define GPIOx_BSRR_BRR12_Pos              (28UL)                    /*!< BRR12 (Bit 28)                                        */
#define GPIOx_BSRR_BRR12_Msk              (0x10000000UL)            /*!< BRR12 (Bitfield-Mask: 0x01)                           */
#define GPIOx_BSRR_BRR11_Pos              (27UL)                    /*!< BRR11 (Bit 27)                                        */
#define GPIOx_BSRR_BRR11_Msk              (0x8000000UL)             /*!< BRR11 (Bitfield-Mask: 0x01)                           */
#define GPIOx_BSRR_BRR10_Pos              (26UL)                    /*!< BRR10 (Bit 26)                                        */
#define GPIOx_BSRR_BRR10_Msk              (0x4000000UL)             /*!< BRR10 (Bitfield-Mask: 0x01)                           */
#define GPIOx_BSRR_BRR9_Pos               (25UL)                    /*!< BRR9 (Bit 25)                                         */
#define GPIOx_BSRR_BRR9_Msk               (0x2000000UL)             /*!< BRR9 (Bitfield-Mask: 0x01)                            */
#define GPIOx_BSRR_BRR8_Pos               (24UL)                    /*!< BRR8 (Bit 24)                                         */
#define GPIOx_BSRR_BRR8_Msk               (0x1000000UL)             /*!< BRR8 (Bitfield-Mask: 0x01)                            */
#define GPIOx_BSRR_BRR7_Pos               (23UL)                    /*!< BRR7 (Bit 23)                                         */
#define GPIOx_BSRR_BRR7_Msk               (0x800000UL)              /*!< BRR7 (Bitfield-Mask: 0x01)                            */
#define GPIOx_BSRR_BRR6_Pos               (22UL)                    /*!< BRR6 (Bit 22)                                         */
#define GPIOx_BSRR_BRR6_Msk               (0x400000UL)              /*!< BRR6 (Bitfield-Mask: 0x01)                            */
#define GPIOx_BSRR_BRR5_Pos               (21UL)                    /*!< BRR5 (Bit 21)                                         */
#define GPIOx_BSRR_BRR5_Msk               (0x200000UL)              /*!< BRR5 (Bitfield-Mask: 0x01)                            */
#define GPIOx_BSRR_BRR4_Pos               (20UL)                    /*!< BRR4 (Bit 20)                                         */
#define GPIOx_BSRR_BRR4_Msk               (0x100000UL)              /*!< BRR4 (Bitfield-Mask: 0x01)                            */
#define GPIOx_BSRR_BRR3_Pos               (19UL)                    /*!< BRR3 (Bit 19)                                         */
#define GPIOx_BSRR_BRR3_Msk               (0x80000UL)               /*!< BRR3 (Bitfield-Mask: 0x01)                            */
#define GPIOx_BSRR_BRR2_Pos               (18UL)                    /*!< BRR2 (Bit 18)                                         */
#define GPIOx_BSRR_BRR2_Msk               (0x40000UL)               /*!< BRR2 (Bitfield-Mask: 0x01)                            */
#define GPIOx_BSRR_BRR1_Pos               (17UL)                    /*!< BRR1 (Bit 17)                                         */
#define GPIOx_BSRR_BRR1_Msk               (0x20000UL)               /*!< BRR1 (Bitfield-Mask: 0x01)                            */
#define GPIOx_BSRR_BRR0_Pos               (16UL)                    /*!< BRR0 (Bit 16)                                         */
#define GPIOx_BSRR_BRR0_Msk               (0x10000UL)               /*!< BRR0 (Bitfield-Mask: 0x01)                            */
#define GPIOx_BSRR_BSS15_Pos              (15UL)                    /*!< BSS15 (Bit 15)                                        */
#define GPIOx_BSRR_BSS15_Msk              (0x8000UL)                /*!< BSS15 (Bitfield-Mask: 0x01)                           */
#define GPIOx_BSRR_BSS14_Pos              (14UL)                    /*!< BSS14 (Bit 14)                                        */
#define GPIOx_BSRR_BSS14_Msk              (0x4000UL)                /*!< BSS14 (Bitfield-Mask: 0x01)                           */
#define GPIOx_BSRR_BSS13_Pos              (13UL)                    /*!< BSS13 (Bit 13)                                        */
#define GPIOx_BSRR_BSS13_Msk              (0x2000UL)                /*!< BSS13 (Bitfield-Mask: 0x01)                           */
#define GPIOx_BSRR_BSS12_Pos              (12UL)                    /*!< BSS12 (Bit 12)                                        */
#define GPIOx_BSRR_BSS12_Msk              (0x1000UL)                /*!< BSS12 (Bitfield-Mask: 0x01)                           */
#define GPIOx_BSRR_BSS11_Pos              (11UL)                    /*!< BSS11 (Bit 11)                                        */
#define GPIOx_BSRR_BSS11_Msk              (0x800UL)                 /*!< BSS11 (Bitfield-Mask: 0x01)                           */
#define GPIOx_BSRR_BSS10_Pos              (10UL)                    /*!< BSS10 (Bit 10)                                        */
#define GPIOx_BSRR_BSS10_Msk              (0x400UL)                 /*!< BSS10 (Bitfield-Mask: 0x01)                           */
#define GPIOx_BSRR_BSS9_Pos               (9UL)                     /*!< BSS9 (Bit 9)                                          */
#define GPIOx_BSRR_BSS9_Msk               (0x200UL)                 /*!< BSS9 (Bitfield-Mask: 0x01)                            */
#define GPIOx_BSRR_BSS8_Pos               (8UL)                     /*!< BSS8 (Bit 8)                                          */
#define GPIOx_BSRR_BSS8_Msk               (0x100UL)                 /*!< BSS8 (Bitfield-Mask: 0x01)                            */
#define GPIOx_BSRR_BSS7_Pos               (7UL)                     /*!< BSS7 (Bit 7)                                          */
#define GPIOx_BSRR_BSS7_Msk               (0x80UL)                  /*!< BSS7 (Bitfield-Mask: 0x01)                            */
#define GPIOx_BSRR_BSS6_Pos               (6UL)                     /*!< BSS6 (Bit 6)                                          */
#define GPIOx_BSRR_BSS6_Msk               (0x40UL)                  /*!< BSS6 (Bitfield-Mask: 0x01)                            */
#define GPIOx_BSRR_BSS5_Pos               (5UL)                     /*!< BSS5 (Bit 5)                                          */
#define GPIOx_BSRR_BSS5_Msk               (0x20UL)                  /*!< BSS5 (Bitfield-Mask: 0x01)                            */
#define GPIOx_BSRR_BSS4_Pos               (4UL)                     /*!< BSS4 (Bit 4)                                          */
#define GPIOx_BSRR_BSS4_Msk               (0x10UL)                  /*!< BSS4 (Bitfield-Mask: 0x01)                            */
#define GPIOx_BSRR_BSS3_Pos               (3UL)                     /*!< BSS3 (Bit 3)                                          */
#define GPIOx_BSRR_BSS3_Msk               (0x8UL)                   /*!< BSS3 (Bitfield-Mask: 0x01)                            */
#define GPIOx_BSRR_BSS2_Pos               (2UL)                     /*!< BSS2 (Bit 2)                                          */
#define GPIOx_BSRR_BSS2_Msk               (0x4UL)                   /*!< BSS2 (Bitfield-Mask: 0x01)                            */
#define GPIOx_BSRR_BSS1_Pos               (1UL)                     /*!< BSS1 (Bit 1)                                          */
#define GPIOx_BSRR_BSS1_Msk               (0x2UL)                   /*!< BSS1 (Bitfield-Mask: 0x01)                            */
#define GPIOx_BSRR_BSS0_Pos               (0UL)                     /*!< BSS0 (Bit 0)                                          */
#define GPIOx_BSRR_BSS0_Msk               (0x1UL)                   /*!< BSS0 (Bitfield-Mask: 0x01)                            */
/* ==========================================================  TOG  ========================================================== */
#define GPIOx_TOG_PIN15_Pos               (15UL)                    /*!< PIN15 (Bit 15)                                        */
#define GPIOx_TOG_PIN15_Msk               (0x8000UL)                /*!< PIN15 (Bitfield-Mask: 0x01)                           */
#define GPIOx_TOG_PIN14_Pos               (14UL)                    /*!< PIN14 (Bit 14)                                        */
#define GPIOx_TOG_PIN14_Msk               (0x4000UL)                /*!< PIN14 (Bitfield-Mask: 0x01)                           */
#define GPIOx_TOG_PIN13_Pos               (13UL)                    /*!< PIN13 (Bit 13)                                        */
#define GPIOx_TOG_PIN13_Msk               (0x2000UL)                /*!< PIN13 (Bitfield-Mask: 0x01)                           */
#define GPIOx_TOG_PIN12_Pos               (12UL)                    /*!< PIN12 (Bit 12)                                        */
#define GPIOx_TOG_PIN12_Msk               (0x1000UL)                /*!< PIN12 (Bitfield-Mask: 0x01)                           */
#define GPIOx_TOG_PIN11_Pos               (11UL)                    /*!< PIN11 (Bit 11)                                        */
#define GPIOx_TOG_PIN11_Msk               (0x800UL)                 /*!< PIN11 (Bitfield-Mask: 0x01)                           */
#define GPIOx_TOG_PIN10_Pos               (10UL)                    /*!< PIN10 (Bit 10)                                        */
#define GPIOx_TOG_PIN10_Msk               (0x400UL)                 /*!< PIN10 (Bitfield-Mask: 0x01)                           */
#define GPIOx_TOG_PIN9_Pos                (9UL)                     /*!< PIN9 (Bit 9)                                          */
#define GPIOx_TOG_PIN9_Msk                (0x200UL)                 /*!< PIN9 (Bitfield-Mask: 0x01)                            */
#define GPIOx_TOG_PIN8_Pos                (8UL)                     /*!< PIN8 (Bit 8)                                          */
#define GPIOx_TOG_PIN8_Msk                (0x100UL)                 /*!< PIN8 (Bitfield-Mask: 0x01)                            */
#define GPIOx_TOG_PIN7_Pos                (7UL)                     /*!< PIN7 (Bit 7)                                          */
#define GPIOx_TOG_PIN7_Msk                (0x80UL)                  /*!< PIN7 (Bitfield-Mask: 0x01)                            */
#define GPIOx_TOG_PIN6_Pos                (6UL)                     /*!< PIN6 (Bit 6)                                          */
#define GPIOx_TOG_PIN6_Msk                (0x40UL)                  /*!< PIN6 (Bitfield-Mask: 0x01)                            */
#define GPIOx_TOG_PIN5_Pos                (5UL)                     /*!< PIN5 (Bit 5)                                          */
#define GPIOx_TOG_PIN5_Msk                (0x20UL)                  /*!< PIN5 (Bitfield-Mask: 0x01)                            */
#define GPIOx_TOG_PIN4_Pos                (4UL)                     /*!< PIN4 (Bit 4)                                          */
#define GPIOx_TOG_PIN4_Msk                (0x10UL)                  /*!< PIN4 (Bitfield-Mask: 0x01)                            */
#define GPIOx_TOG_PIN3_Pos                (3UL)                     /*!< PIN3 (Bit 3)                                          */
#define GPIOx_TOG_PIN3_Msk                (0x8UL)                   /*!< PIN3 (Bitfield-Mask: 0x01)                            */
#define GPIOx_TOG_PIN2_Pos                (2UL)                     /*!< PIN2 (Bit 2)                                          */
#define GPIOx_TOG_PIN2_Msk                (0x4UL)                   /*!< PIN2 (Bitfield-Mask: 0x01)                            */
#define GPIOx_TOG_PIN1_Pos                (1UL)                     /*!< PIN1 (Bit 1)                                          */
#define GPIOx_TOG_PIN1_Msk                (0x2UL)                   /*!< PIN1 (Bitfield-Mask: 0x01)                            */
#define GPIOx_TOG_PIN0_Pos                (0UL)                     /*!< PIN0 (Bit 0)                                          */
#define GPIOx_TOG_PIN0_Msk                (0x1UL)                   /*!< PIN0 (Bitfield-Mask: 0x01)                            */


/* =========================================================================================================================== */
/* ================                                           GTIM                                            ================ */
/* =========================================================================================================================== */

/* ==========================================================  CR1  ========================================================== */
#define GTIMx_CR1_UIFREMAP_Pos            (11UL)                    /*!< UIFREMAP (Bit 11)                                     */
#define GTIMx_CR1_UIFREMAP_Msk            (0x800UL)                 /*!< UIFREMAP (Bitfield-Mask: 0x01)                        */
#define GTIMx_CR1_CKD_Pos                 (8UL)                     /*!< CKD (Bit 8)                                           */
#define GTIMx_CR1_CKD_Msk                 (0x300UL)                 /*!< CKD (Bitfield-Mask: 0x03)                             */
#define GTIMx_CR1_ARPE_Pos                (7UL)                     /*!< ARPE (Bit 7)                                          */
#define GTIMx_CR1_ARPE_Msk                (0x80UL)                  /*!< ARPE (Bitfield-Mask: 0x01)                            */
#define GTIMx_CR1_CMS_Pos                 (5UL)                     /*!< CMS (Bit 5)                                           */
#define GTIMx_CR1_CMS_Msk                 (0x60UL)                  /*!< CMS (Bitfield-Mask: 0x03)                             */
#define GTIMx_CR1_DIR_Pos                 (4UL)                     /*!< DIR (Bit 4)                                           */
#define GTIMx_CR1_DIR_Msk                 (0x10UL)                  /*!< DIR (Bitfield-Mask: 0x01)                             */
#define GTIMx_CR1_OPM_Pos                 (3UL)                     /*!< OPM (Bit 3)                                           */
#define GTIMx_CR1_OPM_Msk                 (0x8UL)                   /*!< OPM (Bitfield-Mask: 0x01)                             */
#define GTIMx_CR1_URS_Pos                 (2UL)                     /*!< URS (Bit 2)                                           */
#define GTIMx_CR1_URS_Msk                 (0x4UL)                   /*!< URS (Bitfield-Mask: 0x01)                             */
#define GTIMx_CR1_UDIS_Pos                (1UL)                     /*!< UDIS (Bit 1)                                          */
#define GTIMx_CR1_UDIS_Msk                (0x2UL)                   /*!< UDIS (Bitfield-Mask: 0x01)                            */
#define GTIMx_CR1_CEN_Pos                 (0UL)                     /*!< CEN (Bit 0)                                           */
#define GTIMx_CR1_CEN_Msk                 (0x1UL)                   /*!< CEN (Bitfield-Mask: 0x01)                             */
/* ==========================================================  CR2  ========================================================== */
#define GTIMx_CR2_MMSH_Pos                (25UL)                    /*!< MMSH (Bit 25)                                         */
#define GTIMx_CR2_MMSH_Msk                (0x6000000UL)             /*!< MMSH (Bitfield-Mask: 0x03)                            */
#define GTIMx_CR2_TI1S_Pos                (7UL)                     /*!< TI1S (Bit 7)                                          */
#define GTIMx_CR2_TI1S_Msk                (0x80UL)                  /*!< TI1S (Bitfield-Mask: 0x01)                            */
#define GTIMx_CR2_MMS_Pos                 (4UL)                     /*!< MMS (Bit 4)                                           */
#define GTIMx_CR2_MMS_Msk                 (0x70UL)                  /*!< MMS (Bitfield-Mask: 0x07)                             */
#define GTIMx_CR2_CCDS_Pos                (3UL)                     /*!< CCDS (Bit 3)                                          */
#define GTIMx_CR2_CCDS_Msk                (0x8UL)                   /*!< CCDS (Bitfield-Mask: 0x01)                            */
/* =========================================================  SMCR  ========================================================== */
#define GTIMx_SMCR_SMSPS_Pos              (25UL)                    /*!< SMSPS (Bit 25)                                        */
#define GTIMx_SMCR_SMSPS_Msk              (0x2000000UL)             /*!< SMSPS (Bitfield-Mask: 0x01)                           */
#define GTIMx_SMCR_SMSPE_Pos              (24UL)                    /*!< SMSPE (Bit 24)                                        */
#define GTIMx_SMCR_SMSPE_Msk              (0x1000000UL)             /*!< SMSPE (Bitfield-Mask: 0x01)                           */
#define GTIMx_SMCR_TSH_Pos                (20UL)                    /*!< TSH (Bit 20)                                          */
#define GTIMx_SMCR_TSH_Msk                (0x300000UL)              /*!< TSH (Bitfield-Mask: 0x03)                             */
#define GTIMx_SMCR_SMSH_Pos               (16UL)                    /*!< SMSH (Bit 16)                                         */
#define GTIMx_SMCR_SMSH_Msk               (0x10000UL)               /*!< SMSH (Bitfield-Mask: 0x01)                            */
#define GTIMx_SMCR_ETP_Pos                (15UL)                    /*!< ETP (Bit 15)                                          */
#define GTIMx_SMCR_ETP_Msk                (0x8000UL)                /*!< ETP (Bitfield-Mask: 0x01)                             */
#define GTIMx_SMCR_ECE_Pos                (14UL)                    /*!< ECE (Bit 14)                                          */
#define GTIMx_SMCR_ECE_Msk                (0x4000UL)                /*!< ECE (Bitfield-Mask: 0x01)                             */
#define GTIMx_SMCR_ETPS_Pos               (12UL)                    /*!< ETPS (Bit 12)                                         */
#define GTIMx_SMCR_ETPS_Msk               (0x3000UL)                /*!< ETPS (Bitfield-Mask: 0x03)                            */
#define GTIMx_SMCR_ETF_Pos                (8UL)                     /*!< ETF (Bit 8)                                           */
#define GTIMx_SMCR_ETF_Msk                (0xf00UL)                 /*!< ETF (Bitfield-Mask: 0x0f)                             */
#define GTIMx_SMCR_MSM_Pos                (7UL)                     /*!< MSM (Bit 7)                                           */
#define GTIMx_SMCR_MSM_Msk                (0x80UL)                  /*!< MSM (Bitfield-Mask: 0x01)                             */
#define GTIMx_SMCR_TS_Pos                 (4UL)                     /*!< TS (Bit 4)                                            */
#define GTIMx_SMCR_TS_Msk                 (0x70UL)                  /*!< TS (Bitfield-Mask: 0x07)                              */
#define GTIMx_SMCR_OCCS_Pos               (3UL)                     /*!< OCCS (Bit 3)                                          */
#define GTIMx_SMCR_OCCS_Msk               (0x8UL)                   /*!< OCCS (Bitfield-Mask: 0x01)                            */
#define GTIMx_SMCR_SMS_Pos                (0UL)                     /*!< SMS (Bit 0)                                           */
#define GTIMx_SMCR_SMS_Msk                (0x7UL)                   /*!< SMS (Bitfield-Mask: 0x07)                             */
/* ==========================================================  IER  ========================================================== */
#define GTIMx_IER_TERRIE_Pos              (23UL)                    /*!< TERRIE (Bit 23)                                       */
#define GTIMx_IER_TERRIE_Msk              (0x800000UL)              /*!< TERRIE (Bitfield-Mask: 0x01)                          */
#define GTIMx_IER_IERRIE_Pos              (22UL)                    /*!< IERRIE (Bit 22)                                       */
#define GTIMx_IER_IERRIE_Msk              (0x400000UL)              /*!< IERRIE (Bitfield-Mask: 0x01)                          */
#define GTIMx_IER_DIRIE_Pos               (21UL)                    /*!< DIRIE (Bit 21)                                        */
#define GTIMx_IER_DIRIE_Msk               (0x200000UL)              /*!< DIRIE (Bitfield-Mask: 0x01)                           */
#define GTIMx_IER_IDXIE_Pos               (20UL)                    /*!< IDXIE (Bit 20)                                        */
#define GTIMx_IER_IDXIE_Msk               (0x100000UL)              /*!< IDXIE (Bitfield-Mask: 0x01)                           */
#define GTIMx_IER_TDE_Pos                 (14UL)                    /*!< TDE (Bit 14)                                          */
#define GTIMx_IER_TDE_Msk                 (0x4000UL)                /*!< TDE (Bitfield-Mask: 0x01)                             */
#define GTIMx_IER_CC4DE_Pos               (12UL)                    /*!< CC4DE (Bit 12)                                        */
#define GTIMx_IER_CC4DE_Msk               (0x1000UL)                /*!< CC4DE (Bitfield-Mask: 0x01)                           */
#define GTIMx_IER_CC3DE_Pos               (11UL)                    /*!< CC3DE (Bit 11)                                        */
#define GTIMx_IER_CC3DE_Msk               (0x800UL)                 /*!< CC3DE (Bitfield-Mask: 0x01)                           */
#define GTIMx_IER_CC2DE_Pos               (10UL)                    /*!< CC2DE (Bit 10)                                        */
#define GTIMx_IER_CC2DE_Msk               (0x400UL)                 /*!< CC2DE (Bitfield-Mask: 0x01)                           */
#define GTIMx_IER_CC1DE_Pos               (9UL)                     /*!< CC1DE (Bit 9)                                         */
#define GTIMx_IER_CC1DE_Msk               (0x200UL)                 /*!< CC1DE (Bitfield-Mask: 0x01)                           */
#define GTIMx_IER_UDE_Pos                 (8UL)                     /*!< UDE (Bit 8)                                           */
#define GTIMx_IER_UDE_Msk                 (0x100UL)                 /*!< UDE (Bitfield-Mask: 0x01)                             */
#define GTIMx_IER_TIE_Pos                 (6UL)                     /*!< TIE (Bit 6)                                           */
#define GTIMx_IER_TIE_Msk                 (0x40UL)                  /*!< TIE (Bitfield-Mask: 0x01)                             */
#define GTIMx_IER_CC4IE_Pos               (4UL)                     /*!< CC4IE (Bit 4)                                         */
#define GTIMx_IER_CC4IE_Msk               (0x10UL)                  /*!< CC4IE (Bitfield-Mask: 0x01)                           */
#define GTIMx_IER_CC3IE_Pos               (3UL)                     /*!< CC3IE (Bit 3)                                         */
#define GTIMx_IER_CC3IE_Msk               (0x8UL)                   /*!< CC3IE (Bitfield-Mask: 0x01)                           */
#define GTIMx_IER_CC2IE_Pos               (2UL)                     /*!< CC2IE (Bit 2)                                         */
#define GTIMx_IER_CC2IE_Msk               (0x4UL)                   /*!< CC2IE (Bitfield-Mask: 0x01)                           */
#define GTIMx_IER_CC1IE_Pos               (1UL)                     /*!< CC1IE (Bit 1)                                         */
#define GTIMx_IER_CC1IE_Msk               (0x2UL)                   /*!< CC1IE (Bitfield-Mask: 0x01)                           */
#define GTIMx_IER_UIE_Pos                 (0UL)                     /*!< UIE (Bit 0)                                           */
#define GTIMx_IER_UIE_Msk                 (0x1UL)                   /*!< UIE (Bitfield-Mask: 0x01)                             */
/* ==========================================================  ISR  ========================================================== */
#define GTIMx_ISR_TERRF_Pos               (23UL)                    /*!< TERRF (Bit 23)                                        */
#define GTIMx_ISR_TERRF_Msk               (0x800000UL)              /*!< TERRF (Bitfield-Mask: 0x01)                           */
#define GTIMx_ISR_IERRF_Pos               (22UL)                    /*!< IERRF (Bit 22)                                        */
#define GTIMx_ISR_IERRF_Msk               (0x400000UL)              /*!< IERRF (Bitfield-Mask: 0x01)                           */
#define GTIMx_ISR_DIRF_Pos                (21UL)                    /*!< DIRF (Bit 21)                                         */
#define GTIMx_ISR_DIRF_Msk                (0x200000UL)              /*!< DIRF (Bitfield-Mask: 0x01)                            */
#define GTIMx_ISR_IDXF_Pos                (20UL)                    /*!< IDXF (Bit 20)                                         */
#define GTIMx_ISR_IDXF_Msk                (0x100000UL)              /*!< IDXF (Bitfield-Mask: 0x01)                            */
#define GTIMx_ISR_CC4OF_Pos               (12UL)                    /*!< CC4OF (Bit 12)                                        */
#define GTIMx_ISR_CC4OF_Msk               (0x1000UL)                /*!< CC4OF (Bitfield-Mask: 0x01)                           */
#define GTIMx_ISR_CC3OF_Pos               (11UL)                    /*!< CC3OF (Bit 11)                                        */
#define GTIMx_ISR_CC3OF_Msk               (0x800UL)                 /*!< CC3OF (Bitfield-Mask: 0x01)                           */
#define GTIMx_ISR_CC2OF_Pos               (10UL)                    /*!< CC2OF (Bit 10)                                        */
#define GTIMx_ISR_CC2OF_Msk               (0x400UL)                 /*!< CC2OF (Bitfield-Mask: 0x01)                           */
#define GTIMx_ISR_CC1OF_Pos               (9UL)                     /*!< CC1OF (Bit 9)                                         */
#define GTIMx_ISR_CC1OF_Msk               (0x200UL)                 /*!< CC1OF (Bitfield-Mask: 0x01)                           */
#define GTIMx_ISR_TIF_Pos                 (6UL)                     /*!< TIF (Bit 6)                                           */
#define GTIMx_ISR_TIF_Msk                 (0x40UL)                  /*!< TIF (Bitfield-Mask: 0x01)                             */
#define GTIMx_ISR_CC4IF_Pos               (4UL)                     /*!< CC4IF (Bit 4)                                         */
#define GTIMx_ISR_CC4IF_Msk               (0x10UL)                  /*!< CC4IF (Bitfield-Mask: 0x01)                           */
#define GTIMx_ISR_CC3IF_Pos               (3UL)                     /*!< CC3IF (Bit 3)                                         */
#define GTIMx_ISR_CC3IF_Msk               (0x8UL)                   /*!< CC3IF (Bitfield-Mask: 0x01)                           */
#define GTIMx_ISR_CC2IF_Pos               (2UL)                     /*!< CC2IF (Bit 2)                                         */
#define GTIMx_ISR_CC2IF_Msk               (0x4UL)                   /*!< CC2IF (Bitfield-Mask: 0x01)                           */
#define GTIMx_ISR_CC1IF_Pos               (1UL)                     /*!< CC1IF (Bit 1)                                         */
#define GTIMx_ISR_CC1IF_Msk               (0x2UL)                   /*!< CC1IF (Bitfield-Mask: 0x01)                           */
#define GTIMx_ISR_UIF_Pos                 (0UL)                     /*!< UIF (Bit 0)                                           */
#define GTIMx_ISR_UIF_Msk                 (0x1UL)                   /*!< UIF (Bitfield-Mask: 0x01)                             */
/* ==========================================================  ICR  ========================================================== */
#define GTIMx_ICR_TERRF_Pos               (23UL)                    /*!< TERRF (Bit 23)                                        */
#define GTIMx_ICR_TERRF_Msk               (0x800000UL)              /*!< TERRF (Bitfield-Mask: 0x01)                           */
#define GTIMx_ICR_IERRF_Pos               (22UL)                    /*!< IERRF (Bit 22)                                        */
#define GTIMx_ICR_IERRF_Msk               (0x400000UL)              /*!< IERRF (Bitfield-Mask: 0x01)                           */
#define GTIMx_ICR_DIRF_Pos                (21UL)                    /*!< DIRF (Bit 21)                                         */
#define GTIMx_ICR_DIRF_Msk                (0x200000UL)              /*!< DIRF (Bitfield-Mask: 0x01)                            */
#define GTIMx_ICR_IDXF_Pos                (20UL)                    /*!< IDXF (Bit 20)                                         */
#define GTIMx_ICR_IDXF_Msk                (0x100000UL)              /*!< IDXF (Bitfield-Mask: 0x01)                            */
#define GTIMx_ICR_CC4OF_Pos               (12UL)                    /*!< CC4OF (Bit 12)                                        */
#define GTIMx_ICR_CC4OF_Msk               (0x1000UL)                /*!< CC4OF (Bitfield-Mask: 0x01)                           */
#define GTIMx_ICR_CC3OF_Pos               (11UL)                    /*!< CC3OF (Bit 11)                                        */
#define GTIMx_ICR_CC3OF_Msk               (0x800UL)                 /*!< CC3OF (Bitfield-Mask: 0x01)                           */
#define GTIMx_ICR_CC2OF_Pos               (10UL)                    /*!< CC2OF (Bit 10)                                        */
#define GTIMx_ICR_CC2OF_Msk               (0x400UL)                 /*!< CC2OF (Bitfield-Mask: 0x01)                           */
#define GTIMx_ICR_CC1OF_Pos               (9UL)                     /*!< CC1OF (Bit 9)                                         */
#define GTIMx_ICR_CC1OF_Msk               (0x200UL)                 /*!< CC1OF (Bitfield-Mask: 0x01)                           */
#define GTIMx_ICR_TIF_Pos                 (6UL)                     /*!< TIF (Bit 6)                                           */
#define GTIMx_ICR_TIF_Msk                 (0x40UL)                  /*!< TIF (Bitfield-Mask: 0x01)                             */
#define GTIMx_ICR_CC4IF_Pos               (4UL)                     /*!< CC4IF (Bit 4)                                         */
#define GTIMx_ICR_CC4IF_Msk               (0x10UL)                  /*!< CC4IF (Bitfield-Mask: 0x01)                           */
#define GTIMx_ICR_CC3IF_Pos               (3UL)                     /*!< CC3IF (Bit 3)                                         */
#define GTIMx_ICR_CC3IF_Msk               (0x8UL)                   /*!< CC3IF (Bitfield-Mask: 0x01)                           */
#define GTIMx_ICR_CC2IF_Pos               (2UL)                     /*!< CC2IF (Bit 2)                                         */
#define GTIMx_ICR_CC2IF_Msk               (0x4UL)                   /*!< CC2IF (Bitfield-Mask: 0x01)                           */
#define GTIMx_ICR_CC1IF_Pos               (1UL)                     /*!< CC1IF (Bit 1)                                         */
#define GTIMx_ICR_CC1IF_Msk               (0x2UL)                   /*!< CC1IF (Bitfield-Mask: 0x01)                           */
#define GTIMx_ICR_UIF_Pos                 (0UL)                     /*!< UIF (Bit 0)                                           */
#define GTIMx_ICR_UIF_Msk                 (0x1UL)                   /*!< UIF (Bitfield-Mask: 0x01)                             */
/* ==========================================================  EGR  ========================================================== */
#define GTIMx_EGR_TG_Pos                  (6UL)                     /*!< TG (Bit 6)                                            */
#define GTIMx_EGR_TG_Msk                  (0x40UL)                  /*!< TG (Bitfield-Mask: 0x01)                              */
#define GTIMx_EGR_CC4G_Pos                (4UL)                     /*!< CC4G (Bit 4)                                          */
#define GTIMx_EGR_CC4G_Msk                (0x10UL)                  /*!< CC4G (Bitfield-Mask: 0x01)                            */
#define GTIMx_EGR_CC3G_Pos                (3UL)                     /*!< CC3G (Bit 3)                                          */
#define GTIMx_EGR_CC3G_Msk                (0x8UL)                   /*!< CC3G (Bitfield-Mask: 0x01)                            */
#define GTIMx_EGR_CC2G_Pos                (2UL)                     /*!< CC2G (Bit 2)                                          */
#define GTIMx_EGR_CC2G_Msk                (0x4UL)                   /*!< CC2G (Bitfield-Mask: 0x01)                            */
#define GTIMx_EGR_CC1G_Pos                (1UL)                     /*!< CC1G (Bit 1)                                          */
#define GTIMx_EGR_CC1G_Msk                (0x2UL)                   /*!< CC1G (Bitfield-Mask: 0x01)                            */
#define GTIMx_EGR_UG_Pos                  (0UL)                     /*!< UG (Bit 0)                                            */
#define GTIMx_EGR_UG_Msk                  (0x1UL)                   /*!< UG (Bitfield-Mask: 0x01)                              */
/* =======================================================  CCMR1CAP  ======================================================== */
#define GTIMx_CCMR1CAP_IC2F_Pos           (12UL)                    /*!< IC2F (Bit 12)                                         */
#define GTIMx_CCMR1CAP_IC2F_Msk           (0xf000UL)                /*!< IC2F (Bitfield-Mask: 0x0f)                            */
#define GTIMx_CCMR1CAP_IC2PSC_Pos         (10UL)                    /*!< IC2PSC (Bit 10)                                       */
#define GTIMx_CCMR1CAP_IC2PSC_Msk         (0xc00UL)                 /*!< IC2PSC (Bitfield-Mask: 0x03)                          */
#define GTIMx_CCMR1CAP_CC2S_Pos           (8UL)                     /*!< CC2S (Bit 8)                                          */
#define GTIMx_CCMR1CAP_CC2S_Msk           (0x300UL)                 /*!< CC2S (Bitfield-Mask: 0x03)                            */
#define GTIMx_CCMR1CAP_IC1F_Pos           (4UL)                     /*!< IC1F (Bit 4)                                          */
#define GTIMx_CCMR1CAP_IC1F_Msk           (0xf0UL)                  /*!< IC1F (Bitfield-Mask: 0x0f)                            */
#define GTIMx_CCMR1CAP_IC1PSC_Pos         (2UL)                     /*!< IC1PSC (Bit 2)                                        */
#define GTIMx_CCMR1CAP_IC1PSC_Msk         (0xcUL)                   /*!< IC1PSC (Bitfield-Mask: 0x03)                          */
#define GTIMx_CCMR1CAP_CC1S_Pos           (0UL)                     /*!< CC1S (Bit 0)                                          */
#define GTIMx_CCMR1CAP_CC1S_Msk           (0x3UL)                   /*!< CC1S (Bitfield-Mask: 0x03)                            */
/* =======================================================  CCMR1CMP  ======================================================== */
#define GTIMx_CCMR1CMP_OC2MH_Pos          (24UL)                    /*!< OC2MH (Bit 24)                                        */
#define GTIMx_CCMR1CMP_OC2MH_Msk          (0x1000000UL)             /*!< OC2MH (Bitfield-Mask: 0x01)                           */
#define GTIMx_CCMR1CMP_OC1MH_Pos          (16UL)                    /*!< OC1MH (Bit 16)                                        */
#define GTIMx_CCMR1CMP_OC1MH_Msk          (0x10000UL)               /*!< OC1MH (Bitfield-Mask: 0x01)                           */
#define GTIMx_CCMR1CMP_OC2CE_Pos          (15UL)                    /*!< OC2CE (Bit 15)                                        */
#define GTIMx_CCMR1CMP_OC2CE_Msk          (0x8000UL)                /*!< OC2CE (Bitfield-Mask: 0x01)                           */
#define GTIMx_CCMR1CMP_OC2M_Pos           (12UL)                    /*!< OC2M (Bit 12)                                         */
#define GTIMx_CCMR1CMP_OC2M_Msk           (0x7000UL)                /*!< OC2M (Bitfield-Mask: 0x07)                            */
#define GTIMx_CCMR1CMP_OC2PE_Pos          (11UL)                    /*!< OC2PE (Bit 11)                                        */
#define GTIMx_CCMR1CMP_OC2PE_Msk          (0x800UL)                 /*!< OC2PE (Bitfield-Mask: 0x01)                           */
#define GTIMx_CCMR1CMP_OC2FE_Pos          (10UL)                    /*!< OC2FE (Bit 10)                                        */
#define GTIMx_CCMR1CMP_OC2FE_Msk          (0x400UL)                 /*!< OC2FE (Bitfield-Mask: 0x01)                           */
#define GTIMx_CCMR1CMP_CC2S_Pos           (8UL)                     /*!< CC2S (Bit 8)                                          */
#define GTIMx_CCMR1CMP_CC2S_Msk           (0x300UL)                 /*!< CC2S (Bitfield-Mask: 0x03)                            */
#define GTIMx_CCMR1CMP_OC1CE_Pos          (7UL)                     /*!< OC1CE (Bit 7)                                         */
#define GTIMx_CCMR1CMP_OC1CE_Msk          (0x80UL)                  /*!< OC1CE (Bitfield-Mask: 0x01)                           */
#define GTIMx_CCMR1CMP_OC1M_Pos           (4UL)                     /*!< OC1M (Bit 4)                                          */
#define GTIMx_CCMR1CMP_OC1M_Msk           (0x70UL)                  /*!< OC1M (Bitfield-Mask: 0x07)                            */
#define GTIMx_CCMR1CMP_OC1PE_Pos          (3UL)                     /*!< OC1PE (Bit 3)                                         */
#define GTIMx_CCMR1CMP_OC1PE_Msk          (0x8UL)                   /*!< OC1PE (Bitfield-Mask: 0x01)                           */
#define GTIMx_CCMR1CMP_OC1FE_Pos          (2UL)                     /*!< OC1FE (Bit 2)                                         */
#define GTIMx_CCMR1CMP_OC1FE_Msk          (0x4UL)                   /*!< OC1FE (Bitfield-Mask: 0x01)                           */
#define GTIMx_CCMR1CMP_CC1S_Pos           (0UL)                     /*!< CC1S (Bit 0)                                          */
#define GTIMx_CCMR1CMP_CC1S_Msk           (0x3UL)                   /*!< CC1S (Bitfield-Mask: 0x03)                            */
/* =======================================================  CCMR2CAP  ======================================================== */
#define GTIMx_CCMR2CAP_IC4F_Pos           (12UL)                    /*!< IC4F (Bit 12)                                         */
#define GTIMx_CCMR2CAP_IC4F_Msk           (0xf000UL)                /*!< IC4F (Bitfield-Mask: 0x0f)                            */
#define GTIMx_CCMR2CAP_IC4PSC_Pos         (10UL)                    /*!< IC4PSC (Bit 10)                                       */
#define GTIMx_CCMR2CAP_IC4PSC_Msk         (0xc00UL)                 /*!< IC4PSC (Bitfield-Mask: 0x03)                          */
#define GTIMx_CCMR2CAP_CC4S_Pos           (8UL)                     /*!< CC4S (Bit 8)                                          */
#define GTIMx_CCMR2CAP_CC4S_Msk           (0x300UL)                 /*!< CC4S (Bitfield-Mask: 0x03)                            */
#define GTIMx_CCMR2CAP_IC3F_Pos           (4UL)                     /*!< IC3F (Bit 4)                                          */
#define GTIMx_CCMR2CAP_IC3F_Msk           (0xf0UL)                  /*!< IC3F (Bitfield-Mask: 0x0f)                            */
#define GTIMx_CCMR2CAP_IC3PSC_Pos         (2UL)                     /*!< IC3PSC (Bit 2)                                        */
#define GTIMx_CCMR2CAP_IC3PSC_Msk         (0xcUL)                   /*!< IC3PSC (Bitfield-Mask: 0x03)                          */
#define GTIMx_CCMR2CAP_CC3S_Pos           (0UL)                     /*!< CC3S (Bit 0)                                          */
#define GTIMx_CCMR2CAP_CC3S_Msk           (0x3UL)                   /*!< CC3S (Bitfield-Mask: 0x03)                            */
/* =======================================================  CCMR2CMP  ======================================================== */
#define GTIMx_CCMR2CMP_OC4MH_Pos          (24UL)                    /*!< OC4MH (Bit 24)                                        */
#define GTIMx_CCMR2CMP_OC4MH_Msk          (0x1000000UL)             /*!< OC4MH (Bitfield-Mask: 0x01)                           */
#define GTIMx_CCMR2CMP_OC3MH_Pos          (16UL)                    /*!< OC3MH (Bit 16)                                        */
#define GTIMx_CCMR2CMP_OC3MH_Msk          (0x10000UL)               /*!< OC3MH (Bitfield-Mask: 0x01)                           */
#define GTIMx_CCMR2CMP_OC4CE_Pos          (15UL)                    /*!< OC4CE (Bit 15)                                        */
#define GTIMx_CCMR2CMP_OC4CE_Msk          (0x8000UL)                /*!< OC4CE (Bitfield-Mask: 0x01)                           */
#define GTIMx_CCMR2CMP_OC4M_Pos           (12UL)                    /*!< OC4M (Bit 12)                                         */
#define GTIMx_CCMR2CMP_OC4M_Msk           (0x7000UL)                /*!< OC4M (Bitfield-Mask: 0x07)                            */
#define GTIMx_CCMR2CMP_OC4PE_Pos          (11UL)                    /*!< OC4PE (Bit 11)                                        */
#define GTIMx_CCMR2CMP_OC4PE_Msk          (0x800UL)                 /*!< OC4PE (Bitfield-Mask: 0x01)                           */
#define GTIMx_CCMR2CMP_OC4FE_Pos          (10UL)                    /*!< OC4FE (Bit 10)                                        */
#define GTIMx_CCMR2CMP_OC4FE_Msk          (0x400UL)                 /*!< OC4FE (Bitfield-Mask: 0x01)                           */
#define GTIMx_CCMR2CMP_CC4S_Pos           (8UL)                     /*!< CC4S (Bit 8)                                          */
#define GTIMx_CCMR2CMP_CC4S_Msk           (0x300UL)                 /*!< CC4S (Bitfield-Mask: 0x03)                            */
#define GTIMx_CCMR2CMP_OC3CE_Pos          (7UL)                     /*!< OC3CE (Bit 7)                                         */
#define GTIMx_CCMR2CMP_OC3CE_Msk          (0x80UL)                  /*!< OC3CE (Bitfield-Mask: 0x01)                           */
#define GTIMx_CCMR2CMP_OC3M_Pos           (4UL)                     /*!< OC3M (Bit 4)                                          */
#define GTIMx_CCMR2CMP_OC3M_Msk           (0x70UL)                  /*!< OC3M (Bitfield-Mask: 0x07)                            */
#define GTIMx_CCMR2CMP_OC3PE_Pos          (3UL)                     /*!< OC3PE (Bit 3)                                         */
#define GTIMx_CCMR2CMP_OC3PE_Msk          (0x8UL)                   /*!< OC3PE (Bitfield-Mask: 0x01)                           */
#define GTIMx_CCMR2CMP_OC3FE_Pos          (2UL)                     /*!< OC3FE (Bit 2)                                         */
#define GTIMx_CCMR2CMP_OC3FE_Msk          (0x4UL)                   /*!< OC3FE (Bitfield-Mask: 0x01)                           */
#define GTIMx_CCMR2CMP_CC3S_Pos           (0UL)                     /*!< CC3S (Bit 0)                                          */
#define GTIMx_CCMR2CMP_CC3S_Msk           (0x3UL)                   /*!< CC3S (Bitfield-Mask: 0x03)                            */
/* =========================================================  CCER  ========================================================== */
#define GTIMx_CCER_CC4NP_Pos              (15UL)                    /*!< CC4NP (Bit 15)                                        */
#define GTIMx_CCER_CC4NP_Msk              (0x8000UL)                /*!< CC4NP (Bitfield-Mask: 0x01)                           */
#define GTIMx_CCER_CC4P_Pos               (13UL)                    /*!< CC4P (Bit 13)                                         */
#define GTIMx_CCER_CC4P_Msk               (0x2000UL)                /*!< CC4P (Bitfield-Mask: 0x01)                            */
#define GTIMx_CCER_CC4E_Pos               (12UL)                    /*!< CC4E (Bit 12)                                         */
#define GTIMx_CCER_CC4E_Msk               (0x1000UL)                /*!< CC4E (Bitfield-Mask: 0x01)                            */
#define GTIMx_CCER_CC3NP_Pos              (11UL)                    /*!< CC3NP (Bit 11)                                        */
#define GTIMx_CCER_CC3NP_Msk              (0x800UL)                 /*!< CC3NP (Bitfield-Mask: 0x01)                           */
#define GTIMx_CCER_CC3P_Pos               (9UL)                     /*!< CC3P (Bit 9)                                          */
#define GTIMx_CCER_CC3P_Msk               (0x200UL)                 /*!< CC3P (Bitfield-Mask: 0x01)                            */
#define GTIMx_CCER_CC3E_Pos               (8UL)                     /*!< CC3E (Bit 8)                                          */
#define GTIMx_CCER_CC3E_Msk               (0x100UL)                 /*!< CC3E (Bitfield-Mask: 0x01)                            */
#define GTIMx_CCER_CC2NP_Pos              (7UL)                     /*!< CC2NP (Bit 7)                                         */
#define GTIMx_CCER_CC2NP_Msk              (0x80UL)                  /*!< CC2NP (Bitfield-Mask: 0x01)                           */
#define GTIMx_CCER_CC2P_Pos               (5UL)                     /*!< CC2P (Bit 5)                                          */
#define GTIMx_CCER_CC2P_Msk               (0x20UL)                  /*!< CC2P (Bitfield-Mask: 0x01)                            */
#define GTIMx_CCER_CC2E_Pos               (4UL)                     /*!< CC2E (Bit 4)                                          */
#define GTIMx_CCER_CC2E_Msk               (0x10UL)                  /*!< CC2E (Bitfield-Mask: 0x01)                            */
#define GTIMx_CCER_CC1NP_Pos              (3UL)                     /*!< CC1NP (Bit 3)                                         */
#define GTIMx_CCER_CC1NP_Msk              (0x8UL)                   /*!< CC1NP (Bitfield-Mask: 0x01)                           */
#define GTIMx_CCER_CC1P_Pos               (1UL)                     /*!< CC1P (Bit 1)                                          */
#define GTIMx_CCER_CC1P_Msk               (0x2UL)                   /*!< CC1P (Bitfield-Mask: 0x01)                            */
#define GTIMx_CCER_CC1E_Pos               (0UL)                     /*!< CC1E (Bit 0)                                          */
#define GTIMx_CCER_CC1E_Msk               (0x1UL)                   /*!< CC1E (Bitfield-Mask: 0x01)                            */
/* ==========================================================  CNT  ========================================================== */
#define GTIMx_CNT_UIFCPY_Pos              (31UL)                    /*!< UIFCPY (Bit 31)                                       */
#define GTIMx_CNT_UIFCPY_Msk              (0x80000000UL)            /*!< UIFCPY (Bitfield-Mask: 0x01)                          */
#define GTIMx_CNT_CNT_Pos                 (0UL)                     /*!< CNT (Bit 0)                                           */
#define GTIMx_CNT_CNT_Msk                 (0xffffUL)                /*!< CNT (Bitfield-Mask: 0xffff)                           */
/* ==========================================================  PSC  ========================================================== */
#define GTIMx_PSC_PSC_Pos                 (0UL)                     /*!< PSC (Bit 0)                                           */
#define GTIMx_PSC_PSC_Msk                 (0xffffUL)                /*!< PSC (Bitfield-Mask: 0xffff)                           */
/* ==========================================================  ARR  ========================================================== */
#define GTIMx_ARR_ARR_Pos                 (0UL)                     /*!< ARR (Bit 0)                                           */
#define GTIMx_ARR_ARR_Msk                 (0xffffUL)                /*!< ARR (Bitfield-Mask: 0xffff)                           */
/* =========================================================  CCR1  ========================================================== */
#define GTIMx_CCR1_CCR1_Pos               (0UL)                     /*!< CCR1 (Bit 0)                                          */
#define GTIMx_CCR1_CCR1_Msk               (0xffffUL)                /*!< CCR1 (Bitfield-Mask: 0xffff)                          */
/* =========================================================  CCR2  ========================================================== */
#define GTIMx_CCR2_CCR2_Pos               (0UL)                     /*!< CCR2 (Bit 0)                                          */
#define GTIMx_CCR2_CCR2_Msk               (0xffffUL)                /*!< CCR2 (Bitfield-Mask: 0xffff)                          */
/* =========================================================  CCR3  ========================================================== */
#define GTIMx_CCR3_CCR3_Pos               (0UL)                     /*!< CCR3 (Bit 0)                                          */
#define GTIMx_CCR3_CCR3_Msk               (0xffffUL)                /*!< CCR3 (Bitfield-Mask: 0xffff)                          */
/* =========================================================  CCR4  ========================================================== */
#define GTIMx_CCR4_CCR4_Pos               (0UL)                     /*!< CCR4 (Bit 0)                                          */
#define GTIMx_CCR4_CCR4_Msk               (0xffffUL)                /*!< CCR4 (Bitfield-Mask: 0xffff)                          */
/* ==========================================================  ECR  ========================================================== */
#define GTIMx_ECR_IPOS_Pos                (6UL)                     /*!< IPOS (Bit 6)                                          */
#define GTIMx_ECR_IPOS_Msk                (0xc0UL)                  /*!< IPOS (Bitfield-Mask: 0x03)                            */
#define GTIMx_ECR_FIDX_Pos                (5UL)                     /*!< FIDX (Bit 5)                                          */
#define GTIMx_ECR_FIDX_Msk                (0x20UL)                  /*!< FIDX (Bitfield-Mask: 0x01)                            */
#define GTIMx_ECR_IDIR_Pos                (1UL)                     /*!< IDIR (Bit 1)                                          */
#define GTIMx_ECR_IDIR_Msk                (0x6UL)                   /*!< IDIR (Bitfield-Mask: 0x03)                            */
#define GTIMx_ECR_IE_Pos                  (0UL)                     /*!< IE (Bit 0)                                            */
#define GTIMx_ECR_IE_Msk                  (0x1UL)                   /*!< IE (Bitfield-Mask: 0x01)                              */
/* =========================================================  TISEL  ========================================================= */
#define GTIMx_TISEL_TI4SEL_Pos            (24UL)                    /*!< TI4SEL (Bit 24)                                       */
#define GTIMx_TISEL_TI4SEL_Msk            (0xf000000UL)             /*!< TI4SEL (Bitfield-Mask: 0x0f)                          */
#define GTIMx_TISEL_TI3SEL_Pos            (16UL)                    /*!< TI3SEL (Bit 16)                                       */
#define GTIMx_TISEL_TI3SEL_Msk            (0xf0000UL)               /*!< TI3SEL (Bitfield-Mask: 0x0f)                          */
#define GTIMx_TISEL_TI2SEL_Pos            (8UL)                     /*!< TI2SEL (Bit 8)                                        */
#define GTIMx_TISEL_TI2SEL_Msk            (0xf00UL)                 /*!< TI2SEL (Bitfield-Mask: 0x0f)                          */
#define GTIMx_TISEL_TI1SEL_Pos            (0UL)                     /*!< TI1SEL (Bit 0)                                        */
#define GTIMx_TISEL_TI1SEL_Msk            (0xfUL)                   /*!< TI1SEL (Bitfield-Mask: 0x0f)                          */
/* ==========================================================  AF1  ========================================================== */
#define GTIMx_AF1_ETRSEL_Pos              (14UL)                    /*!< ETRSEL (Bit 14)                                       */
#define GTIMx_AF1_ETRSEL_Msk              (0x3c000UL)               /*!< ETRSEL (Bitfield-Mask: 0x0f)                          */
/* ==========================================================  AF2  ========================================================== */
#define GTIMx_AF2_OCRSEL_Pos              (16UL)                    /*!< OCRSEL (Bit 16)                                       */
#define GTIMx_AF2_OCRSEL_Msk              (0x70000UL)               /*!< OCRSEL (Bitfield-Mask: 0x07)                          */


/* =========================================================================================================================== */
/* ================                                          HALLTIM                                          ================ */
/* =========================================================================================================================== */

/* ==========================================================  CR  =========================================================== */
#define HALLTIM_CR_SOFTCAP_Pos            (23UL)                    /*!< SOFTCAP (Bit 23)                                      */
#define HALLTIM_CR_SOFTCAP_Msk            (0x800000UL)              /*!< SOFTCAP (Bitfield-Mask: 0x01)                         */
#define HALLTIM_CR_FLT2LEN_Pos            (8UL)                     /*!< FLT2LEN (Bit 8)                                       */
#define HALLTIM_CR_FLT2LEN_Msk            (0x7fff00UL)              /*!< FLT2LEN (Bitfield-Mask: 0x7fff)                       */
#define HALLTIM_CR_MMS_Pos                (4UL)                     /*!< MMS (Bit 4)                                           */
#define HALLTIM_CR_MMS_Msk                (0x70UL)                  /*!< MMS (Bitfield-Mask: 0x07)                             */
#define HALLTIM_CR_DIV_Pos                (2UL)                     /*!< DIV (Bit 2)                                           */
#define HALLTIM_CR_DIV_Msk                (0xcUL)                   /*!< DIV (Bitfield-Mask: 0x03)                             */
#define HALLTIM_CR_FLT1EN_Pos             (1UL)                     /*!< FLT1EN (Bit 1)                                        */
#define HALLTIM_CR_FLT1EN_Msk             (0x2UL)                   /*!< FLT1EN (Bitfield-Mask: 0x01)                          */
#define HALLTIM_CR_EN_Pos                 (0UL)                     /*!< EN (Bit 0)                                            */
#define HALLTIM_CR_EN_Msk                 (0x1UL)                   /*!< EN (Bitfield-Mask: 0x01)                              */
/* =========================================================  DIER  ========================================================== */
#define HALLTIM_DIER_SOFTDMA_Pos          (7UL)                     /*!< SOFTDMA (Bit 7)                                       */
#define HALLTIM_DIER_SOFTDMA_Msk          (0x80UL)                  /*!< SOFTDMA (Bitfield-Mask: 0x01)                         */
#define HALLTIM_DIER_MATCHDMA_Pos         (6UL)                     /*!< MATCHDMA (Bit 6)                                      */
#define HALLTIM_DIER_MATCHDMA_Msk         (0x40UL)                  /*!< MATCHDMA (Bitfield-Mask: 0x01)                        */
#define HALLTIM_DIER_OVDMA_Pos            (5UL)                     /*!< OVDMA (Bit 5)                                         */
#define HALLTIM_DIER_OVDMA_Msk            (0x20UL)                  /*!< OVDMA (Bitfield-Mask: 0x01)                           */
#define HALLTIM_DIER_CAPDMA_Pos           (4UL)                     /*!< CAPDMA (Bit 4)                                        */
#define HALLTIM_DIER_CAPDMA_Msk           (0x10UL)                  /*!< CAPDMA (Bitfield-Mask: 0x01)                          */
#define HALLTIM_DIER_MATCHIE_Pos          (2UL)                     /*!< MATCHIE (Bit 2)                                       */
#define HALLTIM_DIER_MATCHIE_Msk          (0x4UL)                   /*!< MATCHIE (Bitfield-Mask: 0x01)                         */
#define HALLTIM_DIER_OVIE_Pos             (1UL)                     /*!< OVIE (Bit 1)                                          */
#define HALLTIM_DIER_OVIE_Msk             (0x2UL)                   /*!< OVIE (Bitfield-Mask: 0x01)                            */
#define HALLTIM_DIER_CAPIE_Pos            (0UL)                     /*!< CAPIE (Bit 0)                                         */
#define HALLTIM_DIER_CAPIE_Msk            (0x1UL)                   /*!< CAPIE (Bitfield-Mask: 0x01)                           */
/* ==========================================================  CNT  ========================================================== */
#define HALLTIM_CNT_DATA_Pos              (0UL)                     /*!< DATA (Bit 0)                                          */
#define HALLTIM_CNT_DATA_Msk              (0xffffffUL)              /*!< DATA (Bitfield-Mask: 0xffffff)                        */
/* ==========================================================  ARR  ========================================================== */
#define HALLTIM_ARR_DATA_Pos              (0UL)                     /*!< DATA (Bit 0)                                          */
#define HALLTIM_ARR_DATA_Msk              (0xffffffUL)              /*!< DATA (Bitfield-Mask: 0xffffff)                        */
/* =========================================================  WIDTH  ========================================================= */
#define HALLTIM_WIDTH_DATA_Pos            (0UL)                     /*!< DATA (Bit 0)                                          */
#define HALLTIM_WIDTH_DATA_Msk            (0xffffffUL)              /*!< DATA (Bitfield-Mask: 0xffffff)                        */
/* ==========================================================  CCR  ========================================================== */
#define HALLTIM_CCR_DATA_Pos              (0UL)                     /*!< DATA (Bit 0)                                          */
#define HALLTIM_CCR_DATA_Msk              (0xffffffUL)              /*!< DATA (Bitfield-Mask: 0xffffff)                        */
/* ==========================================================  ISR  ========================================================== */
#define HALLTIM_ISR_MATCH_Pos             (2UL)                     /*!< MATCH (Bit 2)                                         */
#define HALLTIM_ISR_MATCH_Msk             (0x4UL)                   /*!< MATCH (Bitfield-Mask: 0x01)                           */
#define HALLTIM_ISR_OV_Pos                (1UL)                     /*!< OV (Bit 1)                                            */
#define HALLTIM_ISR_OV_Msk                (0x2UL)                   /*!< OV (Bitfield-Mask: 0x01)                              */
#define HALLTIM_ISR_CAPF_Pos              (0UL)                     /*!< CAPF (Bit 0)                                          */
#define HALLTIM_ISR_CAPF_Msk              (0x1UL)                   /*!< CAPF (Bitfield-Mask: 0x01)                            */
/* ==========================================================  ICR  ========================================================== */
#define HALLTIM_ICR_MATCHF_Pos            (2UL)                     /*!< MATCHF (Bit 2)                                        */
#define HALLTIM_ICR_MATCHF_Msk            (0x4UL)                   /*!< MATCHF (Bitfield-Mask: 0x01)                          */
#define HALLTIM_ICR_OVF_Pos               (1UL)                     /*!< OVF (Bit 1)                                           */
#define HALLTIM_ICR_OVF_Msk               (0x2UL)                   /*!< OVF (Bitfield-Mask: 0x01)                             */
#define HALLTIM_ICR_CAPF_Pos              (0UL)                     /*!< CAPF (Bit 0)                                          */
#define HALLTIM_ICR_CAPF_Msk              (0x1UL)                   /*!< CAPF (Bitfield-Mask: 0x01)                            */
/* =========================================================  STATE  ========================================================= */
#define HALLTIM_STATE_CH3S_Pos            (6UL)                     /*!< CH3S (Bit 6)                                          */
#define HALLTIM_STATE_CH3S_Msk            (0x40UL)                  /*!< CH3S (Bitfield-Mask: 0x01)                            */
#define HALLTIM_STATE_CH2S_Pos            (5UL)                     /*!< CH2S (Bit 5)                                          */
#define HALLTIM_STATE_CH2S_Msk            (0x20UL)                  /*!< CH2S (Bitfield-Mask: 0x01)                            */
#define HALLTIM_STATE_CH1S_Pos            (4UL)                     /*!< CH1S (Bit 4)                                          */
#define HALLTIM_STATE_CH1S_Msk            (0x10UL)                  /*!< CH1S (Bitfield-Mask: 0x01)                            */
#define HALLTIM_STATE_CH3F_Pos            (2UL)                     /*!< CH3F (Bit 2)                                          */
#define HALLTIM_STATE_CH3F_Msk            (0x4UL)                   /*!< CH3F (Bitfield-Mask: 0x01)                            */
#define HALLTIM_STATE_CH2F_Pos            (1UL)                     /*!< CH2F (Bit 1)                                          */
#define HALLTIM_STATE_CH2F_Msk            (0x2UL)                   /*!< CH2F (Bitfield-Mask: 0x01)                            */
#define HALLTIM_STATE_CH1F_Pos            (0UL)                     /*!< CH1F (Bit 0)                                          */
#define HALLTIM_STATE_CH1F_Msk            (0x1UL)                   /*!< CH1F (Bitfield-Mask: 0x01)                            */


/* =========================================================================================================================== */
/* ================                                            I2C                                            ================ */
/* =========================================================================================================================== */

/* =========================================================  INSEL  ========================================================= */
#define I2Cx_INSEL_SDAINSEL_Pos           (3UL)                     /*!< SDAINSEL (Bit 3)                                      */
#define I2Cx_INSEL_SDAINSEL_Msk           (0x38UL)                  /*!< SDAINSEL (Bitfield-Mask: 0x07)                        */
#define I2Cx_INSEL_SCLINSEL_Pos           (0UL)                     /*!< SCLINSEL (Bit 0)                                      */
#define I2Cx_INSEL_SCLINSEL_Msk           (0x7UL)                   /*!< SCLINSEL (Bitfield-Mask: 0x07)                        */
/* =========================================================  MCR0  ========================================================== */
#define I2Cx_MCR0_RXFIFORST_Pos           (9UL)                     /*!< RXFIFORST (Bit 9)                                     */
#define I2Cx_MCR0_RXFIFORST_Msk           (0x200UL)                 /*!< RXFIFORST (Bitfield-Mask: 0x01)                       */
#define I2Cx_MCR0_TXFIFORST_Pos           (8UL)                     /*!< TXFIFORST (Bit 8)                                     */
#define I2Cx_MCR0_TXFIFORST_Msk           (0x100UL)                 /*!< TXFIFORST (Bitfield-Mask: 0x01)                       */
#define I2Cx_MCR0_CLKSRC_Pos              (6UL)                     /*!< CLKSRC (Bit 6)                                        */
#define I2Cx_MCR0_CLKSRC_Msk              (0xc0UL)                  /*!< CLKSRC (Bitfield-Mask: 0x03)                          */
#define I2Cx_MCR0_DBGEN_Pos               (3UL)                     /*!< DBGEN (Bit 3)                                         */
#define I2Cx_MCR0_DBGEN_Msk               (0x8UL)                   /*!< DBGEN (Bitfield-Mask: 0x01)                           */
#define I2Cx_MCR0_SLEEPEN_Pos             (2UL)                     /*!< SLEEPEN (Bit 2)                                       */
#define I2Cx_MCR0_SLEEPEN_Msk             (0x4UL)                   /*!< SLEEPEN (Bitfield-Mask: 0x01)                         */
#define I2Cx_MCR0_RESET_Pos               (1UL)                     /*!< RESET (Bit 1)                                         */
#define I2Cx_MCR0_RESET_Msk               (0x2UL)                   /*!< RESET (Bitfield-Mask: 0x01)                           */
#define I2Cx_MCR0_MEN_Pos                 (0UL)                     /*!< MEN (Bit 0)                                           */
#define I2Cx_MCR0_MEN_Msk                 (0x1UL)                   /*!< MEN (Bitfield-Mask: 0x01)                             */
/* =========================================================  MCR1  ========================================================== */
#define I2Cx_MCR1_RDMO_Pos                (9UL)                     /*!< RDMO (Bit 9)                                          */
#define I2Cx_MCR1_RDMO_Msk                (0x200UL)                 /*!< RDMO (Bitfield-Mask: 0x01)                            */
#define I2Cx_MCR1_CIRFIFO_Pos             (8UL)                     /*!< CIRFIFO (Bit 8)                                       */
#define I2Cx_MCR1_CIRFIFO_Msk             (0x100UL)                 /*!< CIRFIFO (Bitfield-Mask: 0x01)                         */
/* =========================================================  MCR2  ========================================================== */
#define I2Cx_MCR2_PINCFG_Pos              (24UL)                    /*!< PINCFG (Bit 24)                                       */
#define I2Cx_MCR2_PINCFG_Msk              (0x7000000UL)             /*!< PINCFG (Bitfield-Mask: 0x07)                          */
#define I2Cx_MCR2_MATCFG_Pos              (16UL)                    /*!< MATCFG (Bit 16)                                       */
#define I2Cx_MCR2_MATCFG_Msk              (0x70000UL)               /*!< MATCFG (Bitfield-Mask: 0x07)                          */
#define I2Cx_MCR2_TRGSEL_Pos              (15UL)                    /*!< TRGSEL (Bit 15)                                       */
#define I2Cx_MCR2_TRGSEL_Msk              (0x8000UL)                /*!< TRGSEL (Bitfield-Mask: 0x01)                          */
#define I2Cx_MCR2_TIMECFG_Pos             (10UL)                    /*!< TIMECFG (Bit 10)                                      */
#define I2Cx_MCR2_TIMECFG_Msk             (0x400UL)                 /*!< TIMECFG (Bitfield-Mask: 0x01)                         */
#define I2Cx_MCR2_IGNACK_Pos              (9UL)                     /*!< IGNACK (Bit 9)                                        */
#define I2Cx_MCR2_IGNACK_Msk              (0x200UL)                 /*!< IGNACK (Bitfield-Mask: 0x01)                          */
#define I2Cx_MCR2_AUTOSTOP_Pos            (8UL)                     /*!< AUTOSTOP (Bit 8)                                      */
#define I2Cx_MCR2_AUTOSTOP_Msk            (0x100UL)                 /*!< AUTOSTOP (Bitfield-Mask: 0x01)                        */
#define I2Cx_MCR2_PRESCALE_Pos            (0UL)                     /*!< PRESCALE (Bit 0)                                      */
#define I2Cx_MCR2_PRESCALE_Msk            (0x7UL)                   /*!< PRESCALE (Bitfield-Mask: 0x07)                        */
/* =========================================================  MCR3  ========================================================== */
#define I2Cx_MCR3_FLTSDA_Pos              (24UL)                    /*!< FLTSDA (Bit 24)                                       */
#define I2Cx_MCR3_FLTSDA_Msk              (0xf000000UL)             /*!< FLTSDA (Bitfield-Mask: 0x0f)                          */
#define I2Cx_MCR3_FLTSCL_Pos              (16UL)                    /*!< FLTSCL (Bit 16)                                       */
#define I2Cx_MCR3_FLTSCL_Msk              (0xf0000UL)               /*!< FLTSCL (Bitfield-Mask: 0x0f)                          */
#define I2Cx_MCR3_BUSIDLE_Pos             (0UL)                     /*!< BUSIDLE (Bit 0)                                       */
#define I2Cx_MCR3_BUSIDLE_Msk             (0xfffUL)                 /*!< BUSIDLE (Bitfield-Mask: 0xfff)                        */
/* =========================================================  MCR4  ========================================================== */
#define I2Cx_MCR4_PINLOW_Pos              (8UL)                     /*!< PINLOW (Bit 8)                                        */
#define I2Cx_MCR4_PINLOW_Msk              (0xfff00UL)               /*!< PINLOW (Bitfield-Mask: 0xfff)                         */
/* =========================================================  MCCR  ========================================================= */
#define I2Cx_MCCR_DATAVD_Pos             (24UL)                    /*!< DATAVD (Bit 24)                                       */
#define I2Cx_MCCR_DATAVD_Msk             (0x3f000000UL)            /*!< DATAVD (Bitfield-Mask: 0x3f)                          */
#define I2Cx_MCCR_SETHOLD_Pos            (16UL)                    /*!< SETHOLD (Bit 16)                                      */
#define I2Cx_MCCR_SETHOLD_Msk            (0x3f0000UL)              /*!< SETHOLD (Bitfield-Mask: 0x3f)                         */
#define I2Cx_MCCR_CLKHI_Pos              (8UL)                     /*!< CLKHI (Bit 8)                                         */
#define I2Cx_MCCR_CLKHI_Msk              (0x3f00UL)                /*!< CLKHI (Bitfield-Mask: 0x3f)                           */
#define I2Cx_MCCR_CLKLO_Pos              (0UL)                     /*!< CLKLO (Bit 0)                                         */
#define I2Cx_MCCR_CLKLO_Msk              (0x3fUL)                  /*!< CLKLO (Bitfield-Mask: 0x3f)                           */
/* ========================================================  MMATCH  ========================================================= */
#define I2Cx_MMATCH_MATCH1_Pos            (16UL)                    /*!< MATCH1 (Bit 16)                                       */
#define I2Cx_MMATCH_MATCH1_Msk            (0xff0000UL)              /*!< MATCH1 (Bitfield-Mask: 0xff)                          */
#define I2Cx_MMATCH_MATCH0_Pos            (0UL)                     /*!< MATCH0 (Bit 0)                                        */
#define I2Cx_MMATCH_MATCH0_Msk            (0xffUL)                  /*!< MATCH0 (Bitfield-Mask: 0xff)                          */
/* ========================================================  MFIFOCR  ======================================================== */
#define I2Cx_MFIFOCR_RXWATER_Pos          (16UL)                    /*!< RXWATER (Bit 16)                                      */
#define I2Cx_MFIFOCR_RXWATER_Msk          (0x10000UL)               /*!< RXWATER (Bitfield-Mask: 0x01)                         */
#define I2Cx_MFIFOCR_TXWATER_Pos          (0UL)                     /*!< TXWATER (Bit 0)                                       */
#define I2Cx_MFIFOCR_TXWATER_Msk          (0x1UL)                   /*!< TXWATER (Bitfield-Mask: 0x01)                         */
/* ========================================================  MFIFOSR  ======================================================== */
#define I2Cx_MFIFOSR_RXCNT_Pos            (16UL)                    /*!< RXCNT (Bit 16)                                        */
#define I2Cx_MFIFOSR_RXCNT_Msk            (0x10000UL)               /*!< RXCNT (Bitfield-Mask: 0x01)                           */
#define I2Cx_MFIFOSR_TXCNT_Pos            (0UL)                     /*!< TXCNT (Bit 0)                                         */
#define I2Cx_MFIFOSR_TXCNT_Msk            (0x1UL)                   /*!< TXCNT (Bitfield-Mask: 0x01)                           */
/* =========================================================  MTDR  ========================================================== */
#define I2Cx_MTDR_CMD_Pos                 (8UL)                     /*!< CMD (Bit 8)                                           */
#define I2Cx_MTDR_CMD_Msk                 (0x700UL)                 /*!< CMD (Bitfield-Mask: 0x07)                             */
#define I2Cx_MTDR_DATA_Pos                (0UL)                     /*!< DATA (Bit 0)                                          */
#define I2Cx_MTDR_DATA_Msk                (0xffUL)                  /*!< DATA (Bitfield-Mask: 0xff)                            */
/* =========================================================  MRDR  ========================================================== */
#define I2Cx_MRDR_EMPTY_Pos               (14UL)                    /*!< EMPTY (Bit 14)                                        */
#define I2Cx_MRDR_EMPTY_Msk               (0x4000UL)                /*!< EMPTY (Bitfield-Mask: 0x01)                           */
#define I2Cx_MRDR_DATA_Pos                (0UL)                     /*!< DATA (Bit 0)                                          */
#define I2Cx_MRDR_DATA_Msk                (0xffUL)                  /*!< DATA (Bitfield-Mask: 0xff)                            */
/* =========================================================  MDER  ========================================================== */
#define I2Cx_MDER_RXNE_Pos                (1UL)                     /*!< RXNE (Bit 1)                                          */
#define I2Cx_MDER_RXNE_Msk                (0x2UL)                   /*!< RXNE (Bitfield-Mask: 0x01)                            */
#define I2Cx_MDER_TXE_Pos                 (0UL)                     /*!< TXE (Bit 0)                                           */
#define I2Cx_MDER_TXE_Msk                 (0x1UL)                   /*!< TXE (Bitfield-Mask: 0x01)                             */
/* =========================================================  MIER  ========================================================== */
#define I2Cx_MIER_MATCH_Pos               (14UL)                    /*!< MATCH (Bit 14)                                        */
#define I2Cx_MIER_MATCH_Msk               (0x4000UL)                /*!< MATCH (Bitfield-Mask: 0x01)                           */
#define I2Cx_MIER_PINLOW_Pos              (13UL)                    /*!< PINLOW (Bit 13)                                       */
#define I2Cx_MIER_PINLOW_Msk              (0x2000UL)                /*!< PINLOW (Bitfield-Mask: 0x01)                          */
#define I2Cx_MIER_FIFO_Pos                (12UL)                    /*!< FIFO (Bit 12)                                         */
#define I2Cx_MIER_FIFO_Msk                (0x1000UL)                /*!< FIFO (Bitfield-Mask: 0x01)                            */
#define I2Cx_MIER_ARBI_Pos                (11UL)                    /*!< ARBI (Bit 11)                                         */
#define I2Cx_MIER_ARBI_Msk                (0x800UL)                 /*!< ARBI (Bitfield-Mask: 0x01)                            */
#define I2Cx_MIER_NACK_Pos                (10UL)                    /*!< NACK (Bit 10)                                         */
#define I2Cx_MIER_NACK_Msk                (0x400UL)                 /*!< NACK (Bitfield-Mask: 0x01)                            */
#define I2Cx_MIER_STOP_Pos                (9UL)                     /*!< STOP (Bit 9)                                          */
#define I2Cx_MIER_STOP_Msk                (0x200UL)                 /*!< STOP (Bitfield-Mask: 0x01)                            */
#define I2Cx_MIER_PACKET_Pos              (8UL)                     /*!< PACKET (Bit 8)                                        */
#define I2Cx_MIER_PACKET_Msk              (0x100UL)                 /*!< PACKET (Bitfield-Mask: 0x01)                          */
#define I2Cx_MIER_RXNE_Pos                (1UL)                     /*!< RXNE (Bit 1)                                          */
#define I2Cx_MIER_RXNE_Msk                (0x2UL)                   /*!< RXNE (Bitfield-Mask: 0x01)                            */
#define I2Cx_MIER_TXE_Pos                 (0UL)                     /*!< TXE (Bit 0)                                           */
#define I2Cx_MIER_TXE_Msk                 (0x1UL)                   /*!< TXE (Bitfield-Mask: 0x01)                             */
/* =========================================================  MISR  ========================================================== */
#define I2Cx_MISR_BUSBUSY_Pos             (25UL)                    /*!< BUSBUSY (Bit 25)                                      */
#define I2Cx_MISR_BUSBUSY_Msk             (0x2000000UL)             /*!< BUSBUSY (Bitfield-Mask: 0x01)                         */
#define I2Cx_MISR_MSTBUSY_Pos             (24UL)                    /*!< MSTBUSY (Bit 24)                                      */
#define I2Cx_MISR_MSTBUSY_Msk             (0x1000000UL)             /*!< MSTBUSY (Bitfield-Mask: 0x01)                         */
#define I2Cx_MISR_MATCH_Pos               (14UL)                    /*!< MATCH (Bit 14)                                        */
#define I2Cx_MISR_MATCH_Msk               (0x4000UL)                /*!< MATCH (Bitfield-Mask: 0x01)                           */
#define I2Cx_MISR_PINLOW_Pos              (13UL)                    /*!< PINLOW (Bit 13)                                       */
#define I2Cx_MISR_PINLOW_Msk              (0x2000UL)                /*!< PINLOW (Bitfield-Mask: 0x01)                          */
#define I2Cx_MISR_FIFO_Pos                (12UL)                    /*!< FIFO (Bit 12)                                         */
#define I2Cx_MISR_FIFO_Msk                (0x1000UL)                /*!< FIFO (Bitfield-Mask: 0x01)                            */
#define I2Cx_MISR_ARBI_Pos                (11UL)                    /*!< ARBI (Bit 11)                                         */
#define I2Cx_MISR_ARBI_Msk                (0x800UL)                 /*!< ARBI (Bitfield-Mask: 0x01)                            */
#define I2Cx_MISR_NACK_Pos                (10UL)                    /*!< NACK (Bit 10)                                         */
#define I2Cx_MISR_NACK_Msk                (0x400UL)                 /*!< NACK (Bitfield-Mask: 0x01)                            */
#define I2Cx_MISR_STOP_Pos                (9UL)                     /*!< STOP (Bit 9)                                          */
#define I2Cx_MISR_STOP_Msk                (0x200UL)                 /*!< STOP (Bitfield-Mask: 0x01)                            */
#define I2Cx_MISR_PACKET_Pos              (8UL)                     /*!< PACKET (Bit 8)                                        */
#define I2Cx_MISR_PACKET_Msk              (0x100UL)                 /*!< PACKET (Bitfield-Mask: 0x01)                          */
#define I2Cx_MISR_RXNE_Pos                (1UL)                     /*!< RXNE (Bit 1)                                          */
#define I2Cx_MISR_RXNE_Msk                (0x2UL)                   /*!< RXNE (Bitfield-Mask: 0x01)                            */
#define I2Cx_MISR_TXE_Pos                 (0UL)                     /*!< TXE (Bit 0)                                           */
#define I2Cx_MISR_TXE_Msk                 (0x1UL)                   /*!< TXE (Bitfield-Mask: 0x01)                             */
/* =========================================================  MICR  ========================================================== */
#define I2Cx_MICR_MATCH_Pos               (14UL)                    /*!< MATCH (Bit 14)                                        */
#define I2Cx_MICR_MATCH_Msk               (0x4000UL)                /*!< MATCH (Bitfield-Mask: 0x01)                           */
#define I2Cx_MICR_PINLOW_Pos              (13UL)                    /*!< PINLOW (Bit 13)                                       */
#define I2Cx_MICR_PINLOW_Msk              (0x2000UL)                /*!< PINLOW (Bitfield-Mask: 0x01)                          */
#define I2Cx_MICR_FIFO_Pos                (12UL)                    /*!< FIFO (Bit 12)                                         */
#define I2Cx_MICR_FIFO_Msk                (0x1000UL)                /*!< FIFO (Bitfield-Mask: 0x01)                            */
#define I2Cx_MICR_ARBI_Pos                (11UL)                    /*!< ARBI (Bit 11)                                         */
#define I2Cx_MICR_ARBI_Msk                (0x800UL)                 /*!< ARBI (Bitfield-Mask: 0x01)                            */
#define I2Cx_MICR_NACK_Pos                (10UL)                    /*!< NACK (Bit 10)                                         */
#define I2Cx_MICR_NACK_Msk                (0x400UL)                 /*!< NACK (Bitfield-Mask: 0x01)                            */
#define I2Cx_MICR_STOP_Pos                (9UL)                     /*!< STOP (Bit 9)                                          */
#define I2Cx_MICR_STOP_Msk                (0x200UL)                 /*!< STOP (Bitfield-Mask: 0x01)                            */
#define I2Cx_MICR_PACKET_Pos              (8UL)                     /*!< PACKET (Bit 8)                                        */
#define I2Cx_MICR_PACKET_Msk              (0x100UL)                 /*!< PACKET (Bitfield-Mask: 0x01)                          */
/* =========================================================  SCR0  ========================================================== */
#define I2Cx_SCR0_RXFIFORST_Pos           (9UL)                     /*!< RXFIFORST (Bit 9)                                     */
#define I2Cx_SCR0_RXFIFORST_Msk           (0x200UL)                 /*!< RXFIFORST (Bitfield-Mask: 0x01)                       */
#define I2Cx_SCR0_TXFIFORST_Pos           (8UL)                     /*!< TXFIFORST (Bit 8)                                     */
#define I2Cx_SCR0_TXFIFORST_Msk           (0x100UL)                 /*!< TXFIFORST (Bitfield-Mask: 0x01)                       */
#define I2Cx_SCR0_CLKSRC_Pos              (6UL)                     /*!< CLKSRC (Bit 6)                                        */
#define I2Cx_SCR0_CLKSRC_Msk              (0xc0UL)                  /*!< CLKSRC (Bitfield-Mask: 0x03)                          */
#define I2Cx_SCR0_FLTEN_Pos               (4UL)                     /*!< FLTEN (Bit 4)                                         */
#define I2Cx_SCR0_FLTEN_Msk               (0x10UL)                  /*!< FLTEN (Bitfield-Mask: 0x01)                           */
#define I2Cx_SCR0_RESET_Pos               (1UL)                     /*!< RESET (Bit 1)                                         */
#define I2Cx_SCR0_RESET_Msk               (0x2UL)                   /*!< RESET (Bitfield-Mask: 0x01)                           */
#define I2Cx_SCR0_SEN_Pos                 (0UL)                     /*!< SEN (Bit 0)                                           */
#define I2Cx_SCR0_SEN_Msk                 (0x1UL)                   /*!< SEN (Bitfield-Mask: 0x01)                             */
/* =========================================================  SCR1  ========================================================== */
#define I2Cx_SCR1_ADDRCFG_Pos             (16UL)                    /*!< ADDRCFG (Bit 16)                                      */
#define I2Cx_SCR1_ADDRCFG_Msk             (0x70000UL)               /*!< ADDRCFG (Bitfield-Mask: 0x07)                         */
#define I2Cx_SCR1_TRGSEL_Pos              (15UL)                    /*!< TRGSEL (Bit 15)                                       */
#define I2Cx_SCR1_TRGSEL_Msk              (0x8000UL)                /*!< TRGSEL (Bitfield-Mask: 0x01)                          */
#define I2Cx_SCR1_IGNACK_Pos              (12UL)                    /*!< IGNACK (Bit 12)                                       */
#define I2Cx_SCR1_IGNACK_Msk              (0x1000UL)                /*!< IGNACK (Bitfield-Mask: 0x01)                          */
#define I2Cx_SCR1_RXCFG_Pos               (11UL)                    /*!< RXCFG (Bit 11)                                        */
#define I2Cx_SCR1_RXCFG_Msk               (0x800UL)                 /*!< RXCFG (Bitfield-Mask: 0x01)                           */
#define I2Cx_SCR1_TXCFG_Pos               (10UL)                    /*!< TXCFG (Bit 10)                                        */
#define I2Cx_SCR1_TXCFG_Msk               (0x400UL)                 /*!< TXCFG (Bitfield-Mask: 0x01)                           */
#define I2Cx_SCR1_ALERTEN_Pos             (9UL)                     /*!< ALERTEN (Bit 9)                                       */
#define I2Cx_SCR1_ALERTEN_Msk             (0x200UL)                 /*!< ALERTEN (Bitfield-Mask: 0x01)                         */
#define I2Cx_SCR1_GCEN_Pos                (8UL)                     /*!< GCEN (Bit 8)                                          */
#define I2Cx_SCR1_GCEN_Msk                (0x100UL)                 /*!< GCEN (Bitfield-Mask: 0x01)                            */
#define I2Cx_SCR1_ACKSTALL_Pos            (3UL)                     /*!< ACKSTALL (Bit 3)                                      */
#define I2Cx_SCR1_ACKSTALL_Msk            (0x8UL)                   /*!< ACKSTALL (Bitfield-Mask: 0x01)                        */
#define I2Cx_SCR1_TXSTALL_Pos             (2UL)                     /*!< TXSTALL (Bit 2)                                       */
#define I2Cx_SCR1_TXSTALL_Msk             (0x4UL)                   /*!< TXSTALL (Bitfield-Mask: 0x01)                         */
#define I2Cx_SCR1_RXSTALL_Pos             (1UL)                     /*!< RXSTALL (Bit 1)                                       */
#define I2Cx_SCR1_RXSTALL_Msk             (0x2UL)                   /*!< RXSTALL (Bitfield-Mask: 0x01)                         */
#define I2Cx_SCR1_ADRSTALL_Pos            (0UL)                     /*!< ADRSTALL (Bit 0)                                      */
#define I2Cx_SCR1_ADRSTALL_Msk            (0x1UL)                   /*!< ADRSTALL (Bitfield-Mask: 0x01)                        */
/* =========================================================  SCR2  ========================================================== */
#define I2Cx_SCR2_PINCFG_Pos              (24UL)                    /*!< PINCFG (Bit 24)                                       */
#define I2Cx_SCR2_PINCFG_Msk              (0x7000000UL)             /*!< PINCFG (Bitfield-Mask: 0x07)                          */
/* =========================================================  SCR3  ========================================================== */
#define I2Cx_SCR3_FLTSDA_Pos              (24UL)                    /*!< FLTSDA (Bit 24)                                       */
#define I2Cx_SCR3_FLTSDA_Msk              (0xf000000UL)             /*!< FLTSDA (Bitfield-Mask: 0x0f)                          */
#define I2Cx_SCR3_FLTSCL_Pos              (16UL)                    /*!< FLTSCL (Bit 16)                                       */
#define I2Cx_SCR3_FLTSCL_Msk              (0xf0000UL)               /*!< FLTSCL (Bitfield-Mask: 0x0f)                          */
#define I2Cx_SCR3_DATAVD_Pos              (8UL)                     /*!< DATAVD (Bit 8)                                        */
#define I2Cx_SCR3_DATAVD_Msk              (0x3f00UL)                /*!< DATAVD (Bitfield-Mask: 0x3f)                          */
#define I2Cx_SCR3_CLKHOLD_Pos             (0UL)                     /*!< CLKHOLD (Bit 0)                                       */
#define I2Cx_SCR3_CLKHOLD_Msk             (0xfUL)                   /*!< CLKHOLD (Bitfield-Mask: 0x0f)                         */
/* =========================================================  SAMR  ========================================================== */
#define I2Cx_SAMR_ADDR1_Pos               (17UL)                    /*!< ADDR1 (Bit 17)                                        */
#define I2Cx_SAMR_ADDR1_Msk               (0x7fe0000UL)             /*!< ADDR1 (Bitfield-Mask: 0x3ff)                          */
#define I2Cx_SAMR_ADDR0_Pos               (1UL)                     /*!< ADDR0 (Bit 1)                                         */
#define I2Cx_SAMR_ADDR0_Msk               (0x7feUL)                 /*!< ADDR0 (Bitfield-Mask: 0x3ff)                          */
/* =========================================================  STAR  ========================================================== */
#define I2Cx_STAR_TXNACK_Pos              (0UL)                     /*!< TXNACK (Bit 0)                                        */
#define I2Cx_STAR_TXNACK_Msk              (0x1UL)                   /*!< TXNACK (Bitfield-Mask: 0x01)                          */
/* =========================================================  STDR  ========================================================== */
#define I2Cx_STDR_DATA_Pos                (0UL)                     /*!< DATA (Bit 0)                                          */
#define I2Cx_STDR_DATA_Msk                (0xffUL)                  /*!< DATA (Bitfield-Mask: 0xff)                            */
/* =========================================================  SRDR  ========================================================== */
#define I2Cx_SRDR_SOF_Pos                 (15UL)                    /*!< SOF (Bit 15)                                          */
#define I2Cx_SRDR_SOF_Msk                 (0x8000UL)                /*!< SOF (Bitfield-Mask: 0x01)                             */
#define I2Cx_SRDR_RXEMPTY_Pos             (14UL)                    /*!< RXEMPTY (Bit 14)                                      */
#define I2Cx_SRDR_RXEMPTY_Msk             (0x4000UL)                /*!< RXEMPTY (Bitfield-Mask: 0x01)                         */
#define I2Cx_SRDR_DATA_Pos                (0UL)                     /*!< DATA (Bit 0)                                          */
#define I2Cx_SRDR_DATA_Msk                (0xffUL)                  /*!< DATA (Bitfield-Mask: 0xff)                            */
/* =========================================================  SASR  ========================================================== */
#define I2Cx_SASR_ANV_Pos                 (14UL)                    /*!< ANV (Bit 14)                                          */
#define I2Cx_SASR_ANV_Msk                 (0x4000UL)                /*!< ANV (Bitfield-Mask: 0x01)                             */
#define I2Cx_SASR_RADDR_Pos               (0UL)                     /*!< RADDR (Bit 0)                                         */
#define I2Cx_SASR_RADDR_Msk               (0x7ffUL)                 /*!< RADDR (Bitfield-Mask: 0x7ff)                          */
/* =========================================================  SDER  ========================================================== */
#define I2Cx_SDER_ADDR_Pos                (2UL)                     /*!< ADDR (Bit 2)                                          */
#define I2Cx_SDER_ADDR_Msk                (0x4UL)                   /*!< ADDR (Bitfield-Mask: 0x01)                            */
#define I2Cx_SDER_RXNE_Pos                (1UL)                     /*!< RXNE (Bit 1)                                          */
#define I2Cx_SDER_RXNE_Msk                (0x2UL)                   /*!< RXNE (Bitfield-Mask: 0x01)                            */
#define I2Cx_SDER_TXE_Pos                 (0UL)                     /*!< TXE (Bit 0)                                           */
#define I2Cx_SDER_TXE_Msk                 (0x1UL)                   /*!< TXE (Bitfield-Mask: 0x01)                             */
/* =========================================================  SIER  ========================================================== */
#define I2Cx_SIER_ALERT_Pos               (15UL)                    /*!< ALERT (Bit 15)                                        */
#define I2Cx_SIER_ALERT_Msk               (0x8000UL)                /*!< ALERT (Bitfield-Mask: 0x01)                           */
#define I2Cx_SIER_GC_Pos                  (14UL)                    /*!< GC (Bit 14)                                           */
#define I2Cx_SIER_GC_Msk                  (0x4000UL)                /*!< GC (Bitfield-Mask: 0x01)                              */
#define I2Cx_SIER_AM1_Pos                 (13UL)                    /*!< AM1 (Bit 13)                                          */
#define I2Cx_SIER_AM1_Msk                 (0x2000UL)                /*!< AM1 (Bitfield-Mask: 0x01)                             */
#define I2Cx_SIER_AM0_Pos                 (12UL)                    /*!< AM0 (Bit 12)                                          */
#define I2Cx_SIER_AM0_Msk                 (0x1000UL)                /*!< AM0 (Bitfield-Mask: 0x01)                             */
#define I2Cx_SIER_FIFO_Pos                (11UL)                    /*!< FIFO (Bit 11)                                         */
#define I2Cx_SIER_FIFO_Msk                (0x800UL)                 /*!< FIFO (Bitfield-Mask: 0x01)                            */
#define I2Cx_SIER_BIT_Pos                 (10UL)                    /*!< BIT (Bit 10)                                          */
#define I2Cx_SIER_BIT_Msk                 (0x400UL)                 /*!< BIT (Bitfield-Mask: 0x01)                             */
#define I2Cx_SIER_STOP_Pos                (9UL)                     /*!< STOP (Bit 9)                                          */
#define I2Cx_SIER_STOP_Msk                (0x200UL)                 /*!< STOP (Bitfield-Mask: 0x01)                            */
#define I2Cx_SIER_RESTART_Pos             (8UL)                     /*!< RESTART (Bit 8)                                       */
#define I2Cx_SIER_RESTART_Msk             (0x100UL)                 /*!< RESTART (Bitfield-Mask: 0x01)                         */
#define I2Cx_SIER_TACK_Pos                (3UL)                     /*!< TACK (Bit 3)                                          */
#define I2Cx_SIER_TACK_Msk                (0x8UL)                   /*!< TACK (Bitfield-Mask: 0x01)                            */
#define I2Cx_SIER_ADDR_Pos                (2UL)                     /*!< ADDR (Bit 2)                                          */
#define I2Cx_SIER_ADDR_Msk                (0x4UL)                   /*!< ADDR (Bitfield-Mask: 0x01)                            */
#define I2Cx_SIER_RXNE_Pos                (1UL)                     /*!< RXNE (Bit 1)                                          */
#define I2Cx_SIER_RXNE_Msk                (0x2UL)                   /*!< RXNE (Bitfield-Mask: 0x01)                            */
#define I2Cx_SIER_TXE_Pos                 (0UL)                     /*!< TXE (Bit 0)                                           */
#define I2Cx_SIER_TXE_Msk                 (0x1UL)                   /*!< TXE (Bitfield-Mask: 0x01)                             */
/* =========================================================  SISR  ========================================================== */
#define I2Cx_SISR_BUSBUSY_Pos             (25UL)                    /*!< BUSBUSY (Bit 25)                                      */
#define I2Cx_SISR_BUSBUSY_Msk             (0x2000000UL)             /*!< BUSBUSY (Bitfield-Mask: 0x01)                         */
#define I2Cx_SISR_SLVBUSY_Pos             (24UL)                    /*!< SLVBUSY (Bit 24)                                      */
#define I2Cx_SISR_SLVBUSY_Msk             (0x1000000UL)             /*!< SLVBUSY (Bitfield-Mask: 0x01)                         */
#define I2Cx_SISR_ALERT_Pos               (15UL)                    /*!< ALERT (Bit 15)                                        */
#define I2Cx_SISR_ALERT_Msk               (0x8000UL)                /*!< ALERT (Bitfield-Mask: 0x01)                           */
#define I2Cx_SISR_GC_Pos                  (14UL)                    /*!< GC (Bit 14)                                           */
#define I2Cx_SISR_GC_Msk                  (0x4000UL)                /*!< GC (Bitfield-Mask: 0x01)                              */
#define I2Cx_SISR_AM1_Pos                 (13UL)                    /*!< AM1 (Bit 13)                                          */
#define I2Cx_SISR_AM1_Msk                 (0x2000UL)                /*!< AM1 (Bitfield-Mask: 0x01)                             */
#define I2Cx_SISR_AM0_Pos                 (12UL)                    /*!< AM0 (Bit 12)                                          */
#define I2Cx_SISR_AM0_Msk                 (0x1000UL)                /*!< AM0 (Bitfield-Mask: 0x01)                             */
#define I2Cx_SISR_FIFO_Pos                (11UL)                    /*!< FIFO (Bit 11)                                         */
#define I2Cx_SISR_FIFO_Msk                (0x800UL)                 /*!< FIFO (Bitfield-Mask: 0x01)                            */
#define I2Cx_SISR_BIT_Pos                 (10UL)                    /*!< BIT (Bit 10)                                          */
#define I2Cx_SISR_BIT_Msk                 (0x400UL)                 /*!< BIT (Bitfield-Mask: 0x01)                             */
#define I2Cx_SISR_STOP_Pos                (9UL)                     /*!< STOP (Bit 9)                                          */
#define I2Cx_SISR_STOP_Msk                (0x200UL)                 /*!< STOP (Bitfield-Mask: 0x01)                            */
#define I2Cx_SISR_RESTART_Pos             (8UL)                     /*!< RESTART (Bit 8)                                       */
#define I2Cx_SISR_RESTART_Msk             (0x100UL)                 /*!< RESTART (Bitfield-Mask: 0x01)                         */
#define I2Cx_SISR_TACK_Pos                (3UL)                     /*!< TACK (Bit 3)                                          */
#define I2Cx_SISR_TACK_Msk                (0x8UL)                   /*!< TACK (Bitfield-Mask: 0x01)                            */
#define I2Cx_SISR_ADDR_Pos                (2UL)                     /*!< ADDR (Bit 2)                                          */
#define I2Cx_SISR_ADDR_Msk                (0x4UL)                   /*!< ADDR (Bitfield-Mask: 0x01)                            */
#define I2Cx_SISR_RXNE_Pos                (1UL)                     /*!< RXNE (Bit 1)                                          */
#define I2Cx_SISR_RXNE_Msk                (0x2UL)                   /*!< RXNE (Bitfield-Mask: 0x01)                            */
#define I2Cx_SISR_TXE_Pos                 (0UL)                     /*!< TXE (Bit 0)                                           */
#define I2Cx_SISR_TXE_Msk                 (0x1UL)                   /*!< TXE (Bitfield-Mask: 0x01)                             */
/* =========================================================  SICR  ========================================================== */
#define I2Cx_SICR_FIFO_Pos                (11UL)                    /*!< FIFO (Bit 11)                                         */
#define I2Cx_SICR_FIFO_Msk                (0x800UL)                 /*!< FIFO (Bitfield-Mask: 0x01)                            */
#define I2Cx_SICR_BIT_Pos                 (10UL)                    /*!< BIT (Bit 10)                                          */
#define I2Cx_SICR_BIT_Msk                 (0x400UL)                 /*!< BIT (Bitfield-Mask: 0x01)                             */
#define I2Cx_SICR_STOP_Pos                (9UL)                     /*!< STOP (Bit 9)                                          */
#define I2Cx_SICR_STOP_Msk                (0x200UL)                 /*!< STOP (Bitfield-Mask: 0x01)                            */
#define I2Cx_SICR_RESTART_Pos             (8UL)                     /*!< RESTART (Bit 8)                                       */
#define I2Cx_SICR_RESTART_Msk             (0x100UL)                 /*!< RESTART (Bitfield-Mask: 0x01)                         */


/* =========================================================================================================================== */
/* ================                                           IRMOD                                           ================ */
/* =========================================================================================================================== */

/* ==========================================================  CR  =========================================================== */
#define IRMOD_CR_INV_Pos                  (5UL)                     /*!< INV (Bit 5)                                           */
#define IRMOD_CR_INV_Msk                  (0x20UL)                  /*!< INV (Bitfield-Mask: 0x01)                             */
#define IRMOD_CR_IRSW_Pos                 (4UL)                     /*!< IRSW (Bit 4)                                          */
#define IRMOD_CR_IRSW_Msk                 (0x10UL)                  /*!< IRSW (Bitfield-Mask: 0x01)                            */
#define IRMOD_CR_MOD_Pos                  (0UL)                     /*!< MOD (Bit 0)                                           */
#define IRMOD_CR_MOD_Msk                  (0xfUL)                   /*!< MOD (Bitfield-Mask: 0x0f)                             */


/* =========================================================================================================================== */
/* ================                                           IWDT                                            ================ */
/* =========================================================================================================================== */

/* ==========================================================  KR  =========================================================== */
#define IWDT_KR_KR_Pos                    (0UL)                     /*!< KR (Bit 0)                                            */
#define IWDT_KR_KR_Msk                    (0xffffUL)                /*!< KR (Bitfield-Mask: 0xffff)                            */
/* ==========================================================  CR  =========================================================== */
#define IWDT_CR_PAUSE_Pos                 (5UL)                     /*!< PAUSE (Bit 5)                                         */
#define IWDT_CR_PAUSE_Msk                 (0x20UL)                  /*!< PAUSE (Bitfield-Mask: 0x01)                           */
#define IWDT_CR_IE_Pos                    (4UL)                     /*!< IE (Bit 4)                                            */
#define IWDT_CR_IE_Msk                    (0x10UL)                  /*!< IE (Bitfield-Mask: 0x01)                              */
#define IWDT_CR_ACTION_Pos                (3UL)                     /*!< ACTION (Bit 3)                                        */
#define IWDT_CR_ACTION_Msk                (0x8UL)                   /*!< ACTION (Bitfield-Mask: 0x01)                          */
#define IWDT_CR_PRS_Pos                   (0UL)                     /*!< PRS (Bit 0)                                           */
#define IWDT_CR_PRS_Msk                   (0x7UL)                   /*!< PRS (Bitfield-Mask: 0x07)                             */
/* ==========================================================  ARR  ========================================================== */
#define IWDT_ARR_ARR_Pos                  (0UL)                     /*!< ARR (Bit 0)                                           */
#define IWDT_ARR_ARR_Msk                  (0xfffUL)                 /*!< ARR (Bitfield-Mask: 0xfff)                            */
/* ==========================================================  CNT  ========================================================== */
#define IWDT_CNT_CNT_Pos                  (0UL)                     /*!< CNT (Bit 0)                                           */
#define IWDT_CNT_CNT_Msk                  (0xfffUL)                 /*!< CNT (Bitfield-Mask: 0xfff)                            */
/* =========================================================  WINR  ========================================================== */
#define IWDT_WINR_WINR_Pos                (0UL)                     /*!< WINR (Bit 0)                                          */
#define IWDT_WINR_WINR_Msk                (0xfffUL)                 /*!< WINR (Bitfield-Mask: 0xfff)                           */
/* ==========================================================  SR  =========================================================== */
#define IWDT_SR_RELOAD_Pos                (5UL)                     /*!< RELOAD (Bit 5)                                        */
#define IWDT_SR_RELOAD_Msk                (0x20UL)                  /*!< RELOAD (Bitfield-Mask: 0x01)                          */
#define IWDT_SR_RUN_Pos                   (4UL)                     /*!< RUN (Bit 4)                                           */
#define IWDT_SR_RUN_Msk                   (0x10UL)                  /*!< RUN (Bitfield-Mask: 0x01)                             */
#define IWDT_SR_OV_Pos                    (3UL)                     /*!< OV (Bit 3)                                            */
#define IWDT_SR_OV_Msk                    (0x8UL)                   /*!< OV (Bitfield-Mask: 0x01)                              */
#define IWDT_SR_WINRF_Pos                 (2UL)                     /*!< WINRF (Bit 2)                                         */
#define IWDT_SR_WINRF_Msk                 (0x4UL)                   /*!< WINRF (Bitfield-Mask: 0x01)                           */
#define IWDT_SR_ARRF_Pos                  (1UL)                     /*!< ARRF (Bit 1)                                          */
#define IWDT_SR_ARRF_Msk                  (0x2UL)                   /*!< ARRF (Bitfield-Mask: 0x01)                            */
#define IWDT_SR_CRF_Pos                   (0UL)                     /*!< CRF (Bit 0)                                           */
#define IWDT_SR_CRF_Msk                   (0x1UL)                   /*!< CRF (Bitfield-Mask: 0x01)                             */


/* =========================================================================================================================== */
/* ================                                           LPTIM                                           ================ */
/* =========================================================================================================================== */

/* =========================================================  CFGR  ========================================================== */
#define LPTIM_CFGR_ICLKSRC_Pos            (25UL)                    /*!< ICLKSRC (Bit 25)                                      */
#define LPTIM_CFGR_ICLKSRC_Msk            (0x6000000UL)             /*!< ICLKSRC (Bitfield-Mask: 0x03)                         */
#define LPTIM_CFGR_ENC_Pos                (24UL)                    /*!< ENC (Bit 24)                                          */
#define LPTIM_CFGR_ENC_Msk                (0x1000000UL)             /*!< ENC (Bitfield-Mask: 0x01)                             */
#define LPTIM_CFGR_COUNTMD_Pos            (23UL)                    /*!< COUNTMD (Bit 23)                                      */
#define LPTIM_CFGR_COUNTMD_Msk            (0x800000UL)              /*!< COUNTMD (Bitfield-Mask: 0x01)                         */
#define LPTIM_CFGR_PRELOAD_Pos            (22UL)                    /*!< PRELOAD (Bit 22)                                      */
#define LPTIM_CFGR_PRELOAD_Msk            (0x400000UL)              /*!< PRELOAD (Bitfield-Mask: 0x01)                         */
#define LPTIM_CFGR_WAVPOL_Pos             (21UL)                    /*!< WAVPOL (Bit 21)                                       */
#define LPTIM_CFGR_WAVPOL_Msk             (0x200000UL)              /*!< WAVPOL (Bitfield-Mask: 0x01)                          */
#define LPTIM_CFGR_WAVE_Pos               (20UL)                    /*!< WAVE (Bit 20)                                         */
#define LPTIM_CFGR_WAVE_Msk               (0x100000UL)              /*!< WAVE (Bitfield-Mask: 0x01)                            */
#define LPTIM_CFGR_TIMOUT_Pos             (19UL)                    /*!< TIMOUT (Bit 19)                                       */
#define LPTIM_CFGR_TIMOUT_Msk             (0x80000UL)               /*!< TIMOUT (Bitfield-Mask: 0x01)                          */
#define LPTIM_CFGR_TRIGEN_Pos             (17UL)                    /*!< TRIGEN (Bit 17)                                       */
#define LPTIM_CFGR_TRIGEN_Msk             (0x60000UL)               /*!< TRIGEN (Bitfield-Mask: 0x03)                          */
#define LPTIM_CFGR_TRIGSEL_Pos            (12UL)                    /*!< TRIGSEL (Bit 12)                                      */
#define LPTIM_CFGR_TRIGSEL_Msk            (0xf000UL)                /*!< TRIGSEL (Bitfield-Mask: 0x0f)                         */
#define LPTIM_CFGR_PRS_Pos                (9UL)                     /*!< PRS (Bit 9)                                           */
#define LPTIM_CFGR_PRS_Msk                (0xe00UL)                 /*!< PRS (Bitfield-Mask: 0x07)                             */
#define LPTIM_CFGR_TRIGFLT_Pos            (6UL)                     /*!< TRIGFLT (Bit 6)                                       */
#define LPTIM_CFGR_TRIGFLT_Msk            (0xc0UL)                  /*!< TRIGFLT (Bitfield-Mask: 0x03)                         */
#define LPTIM_CFGR_CHFLT_Pos              (3UL)                     /*!< CHFLT (Bit 3)                                         */
#define LPTIM_CFGR_CHFLT_Msk              (0x18UL)                  /*!< CHFLT (Bitfield-Mask: 0x03)                           */
#define LPTIM_CFGR_ENCMD_CKPOL_Pos        (1UL)                     /*!< ENCMD_CKPOL (Bit 1)                                   */
#define LPTIM_CFGR_ENCMD_CKPOL_Msk        (0x6UL)                   /*!< ENCMD_CKPOL (Bitfield-Mask: 0x03)                     */
#define LPTIM_CFGR_CKSEL_Pos              (0UL)                     /*!< CKSEL (Bit 0)                                         */
#define LPTIM_CFGR_CKSEL_Msk              (0x1UL)                   /*!< CKSEL (Bitfield-Mask: 0x01)                           */
/* ==========================================================  CR0  ========================================================== */
#define LPTIM_CR0_ARST_Pos                (4UL)                     /*!< ARST (Bit 4)                                          */
#define LPTIM_CR0_ARST_Msk                (0x10UL)                  /*!< ARST (Bitfield-Mask: 0x01)                            */
#define LPTIM_CR0_SRST_Pos                (3UL)                     /*!< SRST (Bit 3)                                          */
#define LPTIM_CR0_SRST_Msk                (0x8UL)                   /*!< SRST (Bitfield-Mask: 0x01)                            */
#define LPTIM_CR0_CNTSTART_Pos            (2UL)                     /*!< CNTSTART (Bit 2)                                      */
#define LPTIM_CR0_CNTSTART_Msk            (0x4UL)                   /*!< CNTSTART (Bitfield-Mask: 0x01)                        */
#define LPTIM_CR0_SNGSTART_Pos            (1UL)                     /*!< SNGSTART (Bit 1)                                      */
#define LPTIM_CR0_SNGSTART_Msk            (0x2UL)                   /*!< SNGSTART (Bitfield-Mask: 0x01)                        */
#define LPTIM_CR0_EN_Pos                  (0UL)                     /*!< EN (Bit 0)                                            */
#define LPTIM_CR0_EN_Msk                  (0x1UL)                   /*!< EN (Bitfield-Mask: 0x01)                              */
/* ==========================================================  ARR  ========================================================== */
#define LPTIM_ARR_ARR_Pos                 (0UL)                     /*!< ARR (Bit 0)                                           */
#define LPTIM_ARR_ARR_Msk                 (0xffffUL)                /*!< ARR (Bitfield-Mask: 0xffff)                           */
/* ==========================================================  CNT  ========================================================== */
#define LPTIM_CNT_CNT_Pos                 (0UL)                     /*!< CNT (Bit 0)                                           */
#define LPTIM_CNT_CNT_Msk                 (0xffffUL)                /*!< CNT (Bitfield-Mask: 0xffff)                           */
/* ==========================================================  CMP  ========================================================== */
#define LPTIM_CMP_CMP_Pos                 (0UL)                     /*!< CMP (Bit 0)                                           */
#define LPTIM_CMP_CMP_Msk                 (0xffffUL)                /*!< CMP (Bitfield-Mask: 0xffff)                           */
/* ==========================================================  IER  ========================================================== */
#define LPTIM_IER_DOWN_Pos                (6UL)                     /*!< DOWN (Bit 6)                                          */
#define LPTIM_IER_DOWN_Msk                (0x40UL)                  /*!< DOWN (Bitfield-Mask: 0x01)                            */
#define LPTIM_IER_UP_Pos                  (5UL)                     /*!< UP (Bit 5)                                            */
#define LPTIM_IER_UP_Msk                  (0x20UL)                  /*!< UP (Bitfield-Mask: 0x01)                              */
#define LPTIM_IER_ARROK_Pos               (4UL)                     /*!< ARROK (Bit 4)                                         */
#define LPTIM_IER_ARROK_Msk               (0x10UL)                  /*!< ARROK (Bitfield-Mask: 0x01)                           */
#define LPTIM_IER_CMPOK_Pos               (3UL)                     /*!< CMPOK (Bit 3)                                         */
#define LPTIM_IER_CMPOK_Msk               (0x8UL)                   /*!< CMPOK (Bitfield-Mask: 0x01)                           */
#define LPTIM_IER_EXTTRIG_Pos             (2UL)                     /*!< EXTTRIG (Bit 2)                                       */
#define LPTIM_IER_EXTTRIG_Msk             (0x4UL)                   /*!< EXTTRIG (Bitfield-Mask: 0x01)                         */
#define LPTIM_IER_ARRM_Pos                (1UL)                     /*!< ARRM (Bit 1)                                          */
#define LPTIM_IER_ARRM_Msk                (0x2UL)                   /*!< ARRM (Bitfield-Mask: 0x01)                            */
#define LPTIM_IER_CMPM_Pos                (0UL)                     /*!< CMPM (Bit 0)                                          */
#define LPTIM_IER_CMPM_Msk                (0x1UL)                   /*!< CMPM (Bitfield-Mask: 0x01)                            */
/* ==========================================================  ISR  ========================================================== */
#define LPTIM_ISR_DIR_Pos                 (7UL)                     /*!< DIR (Bit 7)                                           */
#define LPTIM_ISR_DIR_Msk                 (0x180UL)                 /*!< DIR (Bitfield-Mask: 0x03)                             */
#define LPTIM_ISR_DOWN_Pos                (6UL)                     /*!< DOWN (Bit 6)                                          */
#define LPTIM_ISR_DOWN_Msk                (0x40UL)                  /*!< DOWN (Bitfield-Mask: 0x01)                            */
#define LPTIM_ISR_UP_Pos                  (5UL)                     /*!< UP (Bit 5)                                            */
#define LPTIM_ISR_UP_Msk                  (0x20UL)                  /*!< UP (Bitfield-Mask: 0x01)                              */
#define LPTIM_ISR_ARROK_Pos               (4UL)                     /*!< ARROK (Bit 4)                                         */
#define LPTIM_ISR_ARROK_Msk               (0x10UL)                  /*!< ARROK (Bitfield-Mask: 0x01)                           */
#define LPTIM_ISR_CMPOK_Pos               (3UL)                     /*!< CMPOK (Bit 3)                                         */
#define LPTIM_ISR_CMPOK_Msk               (0x8UL)                   /*!< CMPOK (Bitfield-Mask: 0x01)                           */
#define LPTIM_ISR_EXTTRIG_Pos             (2UL)                     /*!< EXTTRIG (Bit 2)                                       */
#define LPTIM_ISR_EXTTRIG_Msk             (0x4UL)                   /*!< EXTTRIG (Bitfield-Mask: 0x01)                         */
#define LPTIM_ISR_ARRM_Pos                (1UL)                     /*!< ARRM (Bit 1)                                          */
#define LPTIM_ISR_ARRM_Msk                (0x2UL)                   /*!< ARRM (Bitfield-Mask: 0x01)                            */
#define LPTIM_ISR_CMPM_Pos                (0UL)                     /*!< CMPM (Bit 0)                                          */
#define LPTIM_ISR_CMPM_Msk                (0x1UL)                   /*!< CMPM (Bitfield-Mask: 0x01)                            */
/* ==========================================================  ICR  ========================================================== */
#define LPTIM_ICR_DOWN_Pos                (6UL)                     /*!< DOWN (Bit 6)                                          */
#define LPTIM_ICR_DOWN_Msk                (0x40UL)                  /*!< DOWN (Bitfield-Mask: 0x01)                            */
#define LPTIM_ICR_UP_Pos                  (5UL)                     /*!< UP (Bit 5)                                            */
#define LPTIM_ICR_UP_Msk                  (0x20UL)                  /*!< UP (Bitfield-Mask: 0x01)                              */
#define LPTIM_ICR_ARROK_Pos               (4UL)                     /*!< ARROK (Bit 4)                                         */
#define LPTIM_ICR_ARROK_Msk               (0x10UL)                  /*!< ARROK (Bitfield-Mask: 0x01)                           */
#define LPTIM_ICR_CMPOK_Pos               (3UL)                     /*!< CMPOK (Bit 3)                                         */
#define LPTIM_ICR_CMPOK_Msk               (0x8UL)                   /*!< CMPOK (Bitfield-Mask: 0x01)                           */
#define LPTIM_ICR_EXTTRIG_Pos             (2UL)                     /*!< EXTTRIG (Bit 2)                                       */
#define LPTIM_ICR_EXTTRIG_Msk             (0x4UL)                   /*!< EXTTRIG (Bitfield-Mask: 0x01)                         */
#define LPTIM_ICR_ARRM_Pos                (1UL)                     /*!< ARRM (Bit 1)                                          */
#define LPTIM_ICR_ARRM_Msk                (0x2UL)                   /*!< ARRM (Bitfield-Mask: 0x01)                            */
#define LPTIM_ICR_CMPM_Pos                (0UL)                     /*!< CMPM (Bit 0)                                          */
#define LPTIM_ICR_CMPM_Msk                (0x1UL)                   /*!< CMPM (Bitfield-Mask: 0x01)                            */
/* ==========================================================  CR1  ========================================================== */
#define LPTIM_CR1_CH2SRC_Pos              (3UL)                     /*!< CH2SRC (Bit 3)                                        */
#define LPTIM_CR1_CH2SRC_Msk              (0x38UL)                  /*!< CH2SRC (Bitfield-Mask: 0x07)                          */
#define LPTIM_CR1_CH1SRC_Pos              (0UL)                     /*!< CH1SRC (Bit 0)                                        */
#define LPTIM_CR1_CH1SRC_Msk              (0x7UL)                   /*!< CH1SRC (Bitfield-Mask: 0x07)                          */


/* =========================================================================================================================== */
/* ================                                           UART                                            ================ */
/* =========================================================================================================================== */

/* ==========================================================  CR1  ========================================================== */
#define UARTx_CR1_SYNC_Pos                (14UL)                    /*!< SYNC (Bit 14)                                         */
#define UARTx_CR1_SYNC_Msk                (0x4000UL)                /*!< SYNC (Bitfield-Mask: 0x01)                            */
#define UARTx_CR1_SOURCE_Pos              (12UL)                    /*!< SOURCE (Bit 12)                                       */
#define UARTx_CR1_SOURCE_Msk              (0x3000UL)                /*!< SOURCE (Bitfield-Mask: 0x03)                          */
#define UARTx_CR1_SIGNAL_Pos              (11UL)                    /*!< SIGNAL (Bit 11)                                       */
#define UARTx_CR1_SIGNAL_Msk              (0x800UL)                 /*!< SIGNAL (Bitfield-Mask: 0x01)                          */
#define UARTx_CR1_OVER_Pos                (9UL)                     /*!< OVER (Bit 9)                                          */
#define UARTx_CR1_OVER_Msk                (0x600UL)                 /*!< OVER (Bitfield-Mask: 0x03)                            */
#define UARTx_CR1_START_Pos               (8UL)                     /*!< START (Bit 8)                                         */
#define UARTx_CR1_START_Msk               (0x100UL)                 /*!< START (Bitfield-Mask: 0x01)                           */
#define UARTx_CR1_MSBF_Pos                (7UL)                     /*!< MSBF (Bit 7)                                          */
#define UARTx_CR1_MSBF_Msk                (0x80UL)                  /*!< MSBF (Bitfield-Mask: 0x01)                            */
#define UARTx_CR1_CHLEN_Pos               (6UL)                     /*!< CHLEN (Bit 6)                                         */
#define UARTx_CR1_CHLEN_Msk               (0x40UL)                  /*!< CHLEN (Bitfield-Mask: 0x01)                           */
#define UARTx_CR1_STOP_Pos                (4UL)                     /*!< STOP (Bit 4)                                          */
#define UARTx_CR1_STOP_Msk                (0x30UL)                  /*!< STOP (Bitfield-Mask: 0x03)                            */
#define UARTx_CR1_PARITYEN_Pos            (3UL)                     /*!< PARITYEN (Bit 3)                                      */
#define UARTx_CR1_PARITYEN_Msk            (0x8UL)                   /*!< PARITYEN (Bitfield-Mask: 0x01)                        */
#define UARTx_CR1_PARITY_Pos              (2UL)                     /*!< PARITY (Bit 2)                                        */
#define UARTx_CR1_PARITY_Msk              (0x4UL)                   /*!< PARITY (Bitfield-Mask: 0x01)                          */
#define UARTx_CR1_RXEN_Pos                (1UL)                     /*!< RXEN (Bit 1)                                          */
#define UARTx_CR1_RXEN_Msk                (0x2UL)                   /*!< RXEN (Bitfield-Mask: 0x01)                            */
#define UARTx_CR1_TXEN_Pos                (0UL)                     /*!< TXEN (Bit 0)                                          */
#define UARTx_CR1_TXEN_Msk                (0x1UL)                   /*!< TXEN (Bitfield-Mask: 0x01)                            */
/* ==========================================================  CR2  ========================================================== */
#define UARTx_CR2_RXSRC_Pos               (15UL)                    /*!< RXSRC (Bit 15)                                        */
#define UARTx_CR2_RXSRC_Msk               (0x38000UL)               /*!< RXSRC (Bitfield-Mask: 0x07)                           */
#define UARTx_CR2_LOOP_Pos                (14UL)                    /*!< LOOP (Bit 14)                                         */
#define UARTx_CR2_LOOP_Msk                (0x4000UL)                /*!< LOOP (Bitfield-Mask: 0x01)                            */
#define UARTx_CR2_ADCTX_Pos               (13UL)                    /*!< ADCTX (Bit 13)                                        */
#define UARTx_CR2_ADCTX_Msk               (0x2000UL)                /*!< ADCTX (Bitfield-Mask: 0x01)                           */
#define UARTx_CR2_ADCRX_Pos               (12UL)                    /*!< ADCRX (Bit 12)                                        */
#define UARTx_CR2_ADCRX_Msk               (0x1000UL)                /*!< ADCRX (Bitfield-Mask: 0x01)                           */
#define UARTx_CR2_SWAP_Pos                (11UL)                    /*!< SWAP (Bit 11)                                         */
#define UARTx_CR2_SWAP_Msk                (0x800UL)                 /*!< SWAP (Bitfield-Mask: 0x01)                            */
#define UARTx_CR2_TIMCR_Pos               (8UL)                     /*!< TIMCR (Bit 8)                                         */
#define UARTx_CR2_TIMCR_Msk               (0x700UL)                 /*!< TIMCR (Bitfield-Mask: 0x07)                           */
#define UARTx_CR2_DMATX_Pos               (7UL)                     /*!< DMATX (Bit 7)                                         */
#define UARTx_CR2_DMATX_Msk               (0x80UL)                  /*!< DMATX (Bitfield-Mask: 0x01)                           */
#define UARTx_CR2_DMARX_Pos               (6UL)                     /*!< DMARX (Bit 6)                                         */
#define UARTx_CR2_DMARX_Msk               (0x40UL)                  /*!< DMARX (Bitfield-Mask: 0x01)                           */
#define UARTx_CR2_TXINV_Pos               (5UL)                     /*!< TXINV (Bit 5)                                         */
#define UARTx_CR2_TXINV_Msk               (0x20UL)                  /*!< TXINV (Bitfield-Mask: 0x01)                           */
#define UARTx_CR2_RXINV_Pos               (4UL)                     /*!< RXINV (Bit 4)                                         */
#define UARTx_CR2_RXINV_Msk               (0x10UL)                  /*!< RXINV (Bitfield-Mask: 0x01)                           */
#define UARTx_CR2_RTSEN_Pos               (3UL)                     /*!< RTSEN (Bit 3)                                         */
#define UARTx_CR2_RTSEN_Msk               (0x8UL)                   /*!< RTSEN (Bitfield-Mask: 0x01)                           */
#define UARTx_CR2_CTSEN_Pos               (2UL)                     /*!< CTSEN (Bit 2)                                         */
#define UARTx_CR2_CTSEN_Msk               (0x4UL)                   /*!< CTSEN (Bitfield-Mask: 0x01)                           */
#define UARTx_CR2_RXMATCHEN_Pos           (1UL)                     /*!< RXMATCHEN (Bit 1)                                     */
#define UARTx_CR2_RXMATCHEN_Msk           (0x2UL)                   /*!< RXMATCHEN (Bitfield-Mask: 0x01)                       */
#define UARTx_CR2_ADDREN_Pos              (0UL)                     /*!< ADDREN (Bit 0)                                        */
#define UARTx_CR2_ADDREN_Msk              (0x1UL)                   /*!< ADDREN (Bitfield-Mask: 0x01)                          */
/* ==========================================================  CR3  ========================================================== */
#define UARTx_CR3_BRKL_Pos                (8UL)                     /*!< BRKL (Bit 8)                                          */
#define UARTx_CR3_BRKL_Msk                (0x100UL)                 /*!< BRKL (Bitfield-Mask: 0x01)                            */
#define UARTx_CR3_LIN_Pos                 (7UL)                     /*!< LIN (Bit 7)                                           */
#define UARTx_CR3_LIN_Msk                 (0x80UL)                  /*!< LIN (Bitfield-Mask: 0x01)                             */
#define UARTx_CR3_DETIME_Pos              (2UL)                     /*!< DETIME (Bit 2)                                        */
#define UARTx_CR3_DETIME_Msk              (0x7cUL)                  /*!< DETIME (Bitfield-Mask: 0x1f)                          */
#define UARTx_CR3_DEP_Pos                  (1UL)                     /*!< DEP (Bit 1)                                           */
#define UARTx_CR3_DEP_Msk                  (0x2UL)                   /*!< DEP (Bitfield-Mask: 0x01)                             */
#define UARTx_CR3_DEM_Pos                 (0UL)                     /*!< DEM (Bit 0)                                           */
#define UARTx_CR3_DEM_Msk                 (0x1UL)                   /*!< DEM (Bitfield-Mask: 0x01)                             */
/* =========================================================  BRRI  ========================================================== */
#define UARTx_BRRI_BRRI_Pos               (0UL)                     /*!< BRRI (Bit 0)                                          */
#define UARTx_BRRI_BRRI_Msk               (0xffffUL)                /*!< BRRI (Bitfield-Mask: 0xffff)                          */
/* =========================================================  BRRF  ========================================================== */
#define UARTx_BRRF_BRRF_Pos               (0UL)                     /*!< BRRF (Bit 0)                                          */
#define UARTx_BRRF_BRRF_Msk               (0xfUL)                   /*!< BRRF (Bitfield-Mask: 0x0f)                            */
/* ========================================================  TIMARR  ========================================================= */
#define UARTx_TIMARR_TIMARR_Pos           (0UL)                     /*!< TIMARR (Bit 0)                                        */
#define UARTx_TIMARR_TIMARR_Msk           (0xffffffUL)              /*!< TIMARR (Bitfield-Mask: 0xffffff)                      */
/* ========================================================  TIMCNT  ========================================================= */
#define UARTx_TIMCNT_TIMCNT_Pos           (0UL)                     /*!< TIMCNT (Bit 0)                                        */
#define UARTx_TIMCNT_TIMCNT_Msk           (0xffffffUL)              /*!< TIMCNT (Bitfield-Mask: 0xffffff)                      */
/* ==========================================================  TDR  ========================================================== */
#define UARTx_TDR_BREAK_Pos               (10UL)                    /*!< BREAK (Bit 10)                                        */
#define UARTx_TDR_BREAK_Msk               (0x400UL)                 /*!< BREAK (Bitfield-Mask: 0x01)                           */
#define UARTx_TDR_IDLE_Pos                (9UL)                     /*!< IDLE (Bit 9)                                          */
#define UARTx_TDR_IDLE_Msk                (0x200UL)                 /*!< IDLE (Bitfield-Mask: 0x01)                            */
#define UARTx_TDR_TDR_Pos                 (0UL)                     /*!< TDR (Bit 0)                                           */
#define UARTx_TDR_TDR_Msk                 (0x1ffUL)                 /*!< TDR (Bitfield-Mask: 0x1ff)                            */
/* ==========================================================  RDR  ========================================================== */
#define UARTx_RDR_RDR_Pos                 (0UL)                     /*!< RDR (Bit 0)                                           */
#define UARTx_RDR_RDR_Msk                 (0x1ffUL)                 /*!< RDR (Bitfield-Mask: 0x1ff)                            */
/* ==========================================================  IER  ========================================================== */
#define UARTx_IER_RXMATCH_Pos             (12UL)                    /*!< RXMATCH (Bit 12)                                      */
#define UARTx_IER_RXMATCH_Msk             (0x1000UL)                /*!< RXMATCH (Bitfield-Mask: 0x01)                         */
#define UARTx_IER_ORE_Pos                 (11UL)                    /*!< ORE (Bit 11)                                          */
#define UARTx_IER_ORE_Msk                 (0x800UL)                 /*!< ORE (Bitfield-Mask: 0x01)                             */
#define UARTx_IER_NE_Pos                  (10UL)                    /*!< NE (Bit 10)                                           */
#define UARTx_IER_NE_Msk                  (0x400UL)                 /*!< NE (Bitfield-Mask: 0x01)                              */
#define UARTx_IER_PE_Pos                  (9UL)                     /*!< PE (Bit 9)                                            */
#define UARTx_IER_PE_Msk                  (0x200UL)                 /*!< PE (Bitfield-Mask: 0x01)                              */
#define UARTx_IER_FE_Pos                  (8UL)                     /*!< FE (Bit 8)                                            */
#define UARTx_IER_FE_Msk                  (0x100UL)                 /*!< FE (Bitfield-Mask: 0x01)                              */
#define UARTx_IER_CTS_Pos                 (7UL)                     /*!< CTS (Bit 7)                                           */
#define UARTx_IER_CTS_Msk                 (0x80UL)                  /*!< CTS (Bitfield-Mask: 0x01)                             */
#define UARTx_IER_TIMOV_Pos               (6UL)                     /*!< TIMOV (Bit 6)                                         */
#define UARTx_IER_TIMOV_Msk               (0x40UL)                  /*!< TIMOV (Bitfield-Mask: 0x01)                           */
#define UARTx_IER_BAUD_Pos                (5UL)                     /*!< BAUD (Bit 5)                                          */
#define UARTx_IER_BAUD_Msk                (0x20UL)                  /*!< BAUD (Bitfield-Mask: 0x01)                            */
#define UARTx_IER_RXBRK_Pos               (4UL)                     /*!< RXBRK (Bit 4)                                         */
#define UARTx_IER_RXBRK_Msk               (0x10UL)                  /*!< RXBRK (Bitfield-Mask: 0x01)                           */
#define UARTx_IER_RXIDLE_Pos              (3UL)                     /*!< RXIDLE (Bit 3)                                        */
#define UARTx_IER_RXIDLE_Msk              (0x8UL)                   /*!< RXIDLE (Bitfield-Mask: 0x01)                          */
#define UARTx_IER_RC_Pos                  (2UL)                     /*!< RC (Bit 2)                                            */
#define UARTx_IER_RC_Msk                  (0x4UL)                   /*!< RC (Bitfield-Mask: 0x01)                              */
#define UARTx_IER_TC_Pos                  (1UL)                     /*!< TC (Bit 1)                                            */
#define UARTx_IER_TC_Msk                  (0x2UL)                   /*!< TC (Bitfield-Mask: 0x01)                              */
#define UARTx_IER_TXE_Pos                 (0UL)                     /*!< TXE (Bit 0)                                           */
#define UARTx_IER_TXE_Msk                 (0x1UL)                   /*!< TXE (Bitfield-Mask: 0x01)                             */
/* ==========================================================  ISR  ========================================================== */
#define UARTx_ISR_CTSLV_Pos               (15UL)                    /*!< CTSLV (Bit 15)                                        */
#define UARTx_ISR_CTSLV_Msk               (0x8000UL)                /*!< CTSLV (Bitfield-Mask: 0x01)                           */
#define UARTx_ISR_TXBUSY_Pos              (14UL)                    /*!< TXBUSY (Bit 14)                                       */
#define UARTx_ISR_TXBUSY_Msk              (0x4000UL)                /*!< TXBUSY (Bitfield-Mask: 0x01)                          */
#define UARTx_ISR_SLVMATCH_Pos            (13UL)                    /*!< SLVMATCH (Bit 13)                                     */
#define UARTx_ISR_SLVMATCH_Msk            (0x2000UL)                /*!< SLVMATCH (Bitfield-Mask: 0x01)                        */
#define UARTx_ISR_RXMATCH_Pos             (12UL)                    /*!< RXMATCH (Bit 12)                                      */
#define UARTx_ISR_RXMATCH_Msk             (0x1000UL)                /*!< RXMATCH (Bitfield-Mask: 0x01)                         */
#define UARTx_ISR_ORE_Pos                 (11UL)                    /*!< ORE (Bit 11)                                          */
#define UARTx_ISR_ORE_Msk                 (0x800UL)                 /*!< ORE (Bitfield-Mask: 0x01)                             */
#define UARTx_ISR_NE_Pos                  (10UL)                    /*!< NE (Bit 10)                                           */
#define UARTx_ISR_NE_Msk                  (0x400UL)                 /*!< NE (Bitfield-Mask: 0x01)                              */
#define UARTx_ISR_PE_Pos                  (9UL)                     /*!< PE (Bit 9)                                            */
#define UARTx_ISR_PE_Msk                  (0x200UL)                 /*!< PE (Bitfield-Mask: 0x01)                              */
#define UARTx_ISR_FE_Pos                  (8UL)                     /*!< FE (Bit 8)                                            */
#define UARTx_ISR_FE_Msk                  (0x100UL)                 /*!< FE (Bitfield-Mask: 0x01)                              */
#define UARTx_ISR_CTS_Pos                 (7UL)                     /*!< CTS (Bit 7)                                           */
#define UARTx_ISR_CTS_Msk                 (0x80UL)                  /*!< CTS (Bitfield-Mask: 0x01)                             */
#define UARTx_ISR_TIMOV_Pos               (6UL)                     /*!< TIMOV (Bit 6)                                         */
#define UARTx_ISR_TIMOV_Msk               (0x40UL)                  /*!< TIMOV (Bitfield-Mask: 0x01)                           */
#define UARTx_ISR_BAUD_Pos                (5UL)                     /*!< BAUD (Bit 5)                                          */
#define UARTx_ISR_BAUD_Msk                (0x20UL)                  /*!< BAUD (Bitfield-Mask: 0x01)                            */
#define UARTx_ISR_RXBRK_Pos               (4UL)                     /*!< RXBRK (Bit 4)                                         */
#define UARTx_ISR_RXBRK_Msk               (0x10UL)                  /*!< RXBRK (Bitfield-Mask: 0x01)                           */
#define UARTx_ISR_RXIDLE_Pos              (3UL)                     /*!< RXIDLE (Bit 3)                                        */
#define UARTx_ISR_RXIDLE_Msk              (0x8UL)                   /*!< RXIDLE (Bitfield-Mask: 0x01)                          */
#define UARTx_ISR_RC_Pos                  (2UL)                     /*!< RC (Bit 2)                                            */
#define UARTx_ISR_RC_Msk                  (0x4UL)                   /*!< RC (Bitfield-Mask: 0x01)                              */
#define UARTx_ISR_TC_Pos                  (1UL)                     /*!< TC (Bit 1)                                            */
#define UARTx_ISR_TC_Msk                  (0x2UL)                   /*!< TC (Bitfield-Mask: 0x01)                              */
#define UARTx_ISR_TXE_Pos                 (0UL)                     /*!< TXE (Bit 0)                                           */
#define UARTx_ISR_TXE_Msk                 (0x1UL)                   /*!< TXE (Bitfield-Mask: 0x01)                             */
/* ==========================================================  ICR  ========================================================== */
#define UARTx_ICR_RXMATCH_Pos             (12UL)                    /*!< RXMATCH (Bit 12)                                      */
#define UARTx_ICR_RXMATCH_Msk             (0x1000UL)                /*!< RXMATCH (Bitfield-Mask: 0x01)                         */
#define UARTx_ICR_ORE_Pos                 (11UL)                    /*!< ORE (Bit 11)                                          */
#define UARTx_ICR_ORE_Msk                 (0x800UL)                 /*!< ORE (Bitfield-Mask: 0x01)                             */
#define UARTx_ICR_NE_Pos                  (10UL)                    /*!< NE (Bit 10)                                           */
#define UARTx_ICR_NE_Msk                  (0x400UL)                 /*!< NE (Bitfield-Mask: 0x01)                              */
#define UARTx_ICR_PE_Pos                  (9UL)                     /*!< PE (Bit 9)                                            */
#define UARTx_ICR_PE_Msk                  (0x200UL)                 /*!< PE (Bitfield-Mask: 0x01)                              */
#define UARTx_ICR_FE_Pos                  (8UL)                     /*!< FE (Bit 8)                                            */
#define UARTx_ICR_FE_Msk                  (0x100UL)                 /*!< FE (Bitfield-Mask: 0x01)                              */
#define UARTx_ICR_CTS_Pos                 (7UL)                     /*!< CTS (Bit 7)                                           */
#define UARTx_ICR_CTS_Msk                 (0x80UL)                  /*!< CTS (Bitfield-Mask: 0x01)                             */
#define UARTx_ICR_TIMOV_Pos               (6UL)                     /*!< TIMOV (Bit 6)                                         */
#define UARTx_ICR_TIMOV_Msk               (0x40UL)                  /*!< TIMOV (Bitfield-Mask: 0x01)                           */
#define UARTx_ICR_BAUD_Pos                (5UL)                     /*!< BAUD (Bit 5)                                          */
#define UARTx_ICR_BAUD_Msk                (0x20UL)                  /*!< BAUD (Bitfield-Mask: 0x01)                            */
#define UARTx_ICR_RXBRK_Pos               (4UL)                     /*!< RXBRK (Bit 4)                                         */
#define UARTx_ICR_RXBRK_Msk               (0x10UL)                  /*!< RXBRK (Bitfield-Mask: 0x01)                           */
#define UARTx_ICR_RXIDLE_Pos              (3UL)                     /*!< RXIDLE (Bit 3)                                        */
#define UARTx_ICR_RXIDLE_Msk              (0x8UL)                   /*!< RXIDLE (Bitfield-Mask: 0x01)                          */
#define UARTx_ICR_RC_Pos                  (2UL)                     /*!< RC (Bit 2)                                            */
#define UARTx_ICR_RC_Msk                  (0x4UL)                   /*!< RC (Bitfield-Mask: 0x01)                              */
#define UARTx_ICR_TC_Pos                  (1UL)                     /*!< TC (Bit 1)                                            */
#define UARTx_ICR_TC_Msk                  (0x2UL)                   /*!< TC (Bitfield-Mask: 0x01)                              */
/* =========================================================  ADDR  ========================================================== */
#define UARTx_ADDR_ADDR_Pos               (0UL)                     /*!< ADDR (Bit 0)                                          */
#define UARTx_ADDR_ADDR_Msk               (0xffUL)                  /*!< ADDR (Bitfield-Mask: 0xff)                            */
/* =========================================================  MASK  ========================================================== */
#define UARTx_MASK_MASK_Pos               (0UL)                     /*!< MASK (Bit 0)                                          */
#define UARTx_MASK_MASK_Msk               (0xffUL)                  /*!< MASK (Bitfield-Mask: 0xff)                            */
/* ========================================================  RXMATCH  ======================================================== */
#define UARTx_RXMATCH_RXMATCH_Pos         (0UL)                     /*!< RXMATCH (Bit 0)                                       */
#define UARTx_RXMATCH_RXMATCH_Msk         (0x1ffUL)                 /*!< RXMATCH (Bitfield-Mask: 0x1ff)                        */


/* =========================================================================================================================== */
/* ================                                            LVD                                            ================ */
/* =========================================================================================================================== */

/* ==========================================================  CR0  ========================================================== */
#define LVD_CR0_FLTCLK_Pos                (8UL)                     /*!< FLTCLK (Bit 8)                                        */
#define LVD_CR0_FLTCLK_Msk                (0x100UL)                 /*!< FLTCLK (Bitfield-Mask: 0x01)                          */
#define LVD_CR0_VTH_Pos                   (4UL)                     /*!< VTH (Bit 4)                                           */
#define LVD_CR0_VTH_Msk                   (0x70UL)                  /*!< VTH (Bitfield-Mask: 0x07)                             */
#define LVD_CR0_SOURCE_Pos                (2UL)                     /*!< SOURCE (Bit 2)                                        */
#define LVD_CR0_SOURCE_Msk                (0x4UL)                   /*!< SOURCE (Bitfield-Mask: 0x01)                          */
#define LVD_CR0_ACTION_Pos                (1UL)                     /*!< ACTION (Bit 1)                                        */
#define LVD_CR0_ACTION_Msk                (0x2UL)                   /*!< ACTION (Bitfield-Mask: 0x01)                          */
#define LVD_CR0_EN_Pos                    (0UL)                     /*!< EN (Bit 0)                                            */
#define LVD_CR0_EN_Msk                    (0x1UL)                   /*!< EN (Bitfield-Mask: 0x01)                              */
/* ==========================================================  CR1  ========================================================== */
#define LVD_CR1_FLTTIME_Pos               (4UL)                     /*!< FLTTIME (Bit 4)                                       */
#define LVD_CR1_FLTTIME_Msk               (0xf0UL)                  /*!< FLTTIME (Bitfield-Mask: 0x0f)                         */
#define LVD_CR1_FALL_Pos                  (3UL)                     /*!< FALL (Bit 3)                                          */
#define LVD_CR1_FALL_Msk                  (0x8UL)                   /*!< FALL (Bitfield-Mask: 0x01)                            */
#define LVD_CR1_RISE_Pos                  (2UL)                     /*!< RISE (Bit 2)                                          */
#define LVD_CR1_RISE_Msk                  (0x4UL)                   /*!< RISE (Bitfield-Mask: 0x01)                            */
#define LVD_CR1_LEVEL_Pos                 (1UL)                     /*!< LEVEL (Bit 1)                                         */
#define LVD_CR1_LEVEL_Msk                 (0x2UL)                   /*!< LEVEL (Bitfield-Mask: 0x01)                           */
#define LVD_CR1_IE_Pos                    (0UL)                     /*!< IE (Bit 0)                                            */
#define LVD_CR1_IE_Msk                    (0x1UL)                   /*!< IE (Bitfield-Mask: 0x01)                              */
/* ==========================================================  SR  =========================================================== */
#define LVD_SR_FLTV_Pos                   (1UL)                     /*!< FLTV (Bit 1)                                          */
#define LVD_SR_FLTV_Msk                   (0x2UL)                   /*!< FLTV (Bitfield-Mask: 0x01)                            */
#define LVD_SR_INTF_Pos                   (0UL)                     /*!< INTF (Bit 0)                                          */
#define LVD_SR_INTF_Msk                   (0x1UL)                   /*!< INTF (Bitfield-Mask: 0x01)                            */


/* =========================================================================================================================== */
/* ================                                            OPA                                            ================ */
/* =========================================================================================================================== */

/* ==========================================================  CR  =========================================================== */
#define OPAx_CR_BIAS_Pos                   (13UL)                    /*!< BIAS (Bit 13)                                         */
#define OPAx_CR_BIAS_Msk                   (0xe000UL)                /*!< BIAS (Bitfield-Mask: 0x07)                            */
#define OPAx_CR_AMP_Pos                    (10UL)                    /*!< AMP (Bit 10)                                          */
#define OPAx_CR_AMP_Msk                    (0x1c00UL)                /*!< AMP (Bitfield-Mask: 0x07)                             */
#define OPAx_CR_INN2EN_Pos                 (9UL)                     /*!< INN2EN (Bit 9)                                        */
#define OPAx_CR_INN2EN_Msk                 (0x200UL)                 /*!< INN2EN (Bitfield-Mask: 0x01)                          */
#define OPAx_CR_INN1EN_Pos                 (8UL)                     /*!< INN1EN (Bit 8)                                        */
#define OPAx_CR_INN1EN_Msk                 (0x100UL)                 /*!< INN1EN (Bitfield-Mask: 0x01)                          */
#define OPAx_CR_INP4EN_Pos                 (7UL)                     /*!< INP4EN (Bit 7)                                        */
#define OPAx_CR_INP4EN_Msk                 (0x80UL)                  /*!< INP4EN (Bitfield-Mask: 0x01)                          */
#define OPAx_CR_INP3EN_Pos                 (6UL)                     /*!< INP3EN (Bit 6)                                        */
#define OPAx_CR_INP3EN_Msk                 (0x40UL)                  /*!< INP3EN (Bitfield-Mask: 0x01)                          */
#define OPAx_CR_INP2EN_Pos                 (5UL)                     /*!< INP2EN (Bit 5)                                        */
#define OPAx_CR_INP2EN_Msk                 (0x20UL)                  /*!< INP2EN (Bitfield-Mask: 0x01)                          */
#define OPAx_CR_INP1EN_Pos                 (4UL)                     /*!< INP1EN (Bit 4)                                        */
#define OPAx_CR_INP1EN_Msk                 (0x10UL)                  /*!< INP1EN (Bitfield-Mask: 0x01)                          */
#define OPAx_CR_MODE_Pos                   (1UL)                     /*!< MODE (Bit 1)                                          */
#define OPAx_CR_MODE_Msk                   (0x6UL)                   /*!< MODE (Bitfield-Mask: 0x03)                            */
#define OPAx_CR_EN_Pos                     (0UL)                     /*!< EN (Bit 0)                                            */
#define OPAx_CR_EN_Msk                     (0x1UL)                   /*!< EN (Bitfield-Mask: 0x01)                              */
/* ==========================================================  CAL  ========================================================== */
#define OPAx_CAL_GTIM4OC2_Pos              (31UL)                    /*!< GTIM4OC2 (Bit 31)                                     */
#define OPAx_CAL_GTIM4OC2_Msk              (0x80000000UL)            /*!< GTIM4OC2 (Bitfield-Mask: 0x01)                        */
#define OPAx_CAL_GTIM4OC1_Pos              (30UL)                    /*!< GTIM4OC1 (Bit 30)                                     */
#define OPAx_CAL_GTIM4OC1_Msk              (0x40000000UL)            /*!< GTIM4OC1 (Bitfield-Mask: 0x01)                        */
#define OPAx_CAL_GTIM4TRGO_Pos             (29UL)                    /*!< GTIM4TRGO (Bit 29)                                    */
#define OPAx_CAL_GTIM4TRGO_Msk             (0x20000000UL)            /*!< GTIM4TRGO (Bitfield-Mask: 0x01)                       */
#define OPAx_CAL_GTIM3OC2_Pos              (28UL)                    /*!< GTIM3OC2 (Bit 28)                                     */
#define OPAx_CAL_GTIM3OC2_Msk              (0x10000000UL)            /*!< GTIM3OC2 (Bitfield-Mask: 0x01)                        */
#define OPAx_CAL_GTIM3OC1_Pos              (27UL)                    /*!< GTIM3OC1 (Bit 27)                                     */
#define OPAx_CAL_GTIM3OC1_Msk              (0x8000000UL)             /*!< GTIM3OC1 (Bitfield-Mask: 0x01)                        */
#define OPAx_CAL_GTIM3TRGO_Pos             (26UL)                    /*!< GTIM3TRGO (Bit 26)                                    */
#define OPAx_CAL_GTIM3TRGO_Msk             (0x4000000UL)             /*!< GTIM3TRGO (Bitfield-Mask: 0x01)                       */
#define OPAx_CAL_GTIM2OC2_Pos              (25UL)                    /*!< GTIM2OC2 (Bit 25)                                     */
#define OPAx_CAL_GTIM2OC2_Msk              (0x2000000UL)             /*!< GTIM2OC2 (Bitfield-Mask: 0x01)                        */
#define OPAx_CAL_GTIM2OC1_Pos              (24UL)                    /*!< GTIM2OC1 (Bit 24)                                     */
#define OPAx_CAL_GTIM2OC1_Msk              (0x1000000UL)             /*!< GTIM2OC1 (Bitfield-Mask: 0x01)                        */
#define OPAx_CAL_GTIM2TRGO_Pos             (23UL)                    /*!< GTIM2TRGO (Bit 23)                                    */
#define OPAx_CAL_GTIM2TRGO_Msk             (0x800000UL)              /*!< GTIM2TRGO (Bitfield-Mask: 0x01)                       */
#define OPAx_CAL_GTIM1OC2_Pos              (22UL)                    /*!< GTIM1OC2 (Bit 22)                                     */
#define OPAx_CAL_GTIM1OC2_Msk              (0x400000UL)              /*!< GTIM1OC2 (Bitfield-Mask: 0x01)                        */
#define OPAx_CAL_GTIM1OC1_Pos              (21UL)                    /*!< GTIM1OC1 (Bit 21)                                     */
#define OPAx_CAL_GTIM1OC1_Msk              (0x200000UL)              /*!< GTIM1OC1 (Bitfield-Mask: 0x01)                        */
#define OPAx_CAL_GTIM1TRGO_Pos             (20UL)                    /*!< GTIM1TRGO (Bit 20)                                    */
#define OPAx_CAL_GTIM1TRGO_Msk             (0x100000UL)              /*!< GTIM1TRGO (Bitfield-Mask: 0x01)                       */
#define OPAx_CAL_ATIM1OC6_Pos              (19UL)                    /*!< ATIM1OC6 (Bit 19)                                     */
#define OPAx_CAL_ATIM1OC6_Msk              (0x80000UL)               /*!< ATIM1OC6 (Bitfield-Mask: 0x01)                        */
#define OPAx_CAL_ATIM1OC5_Pos              (18UL)                    /*!< ATIM1OC5 (Bit 18)                                     */
#define OPAx_CAL_ATIM1OC5_Msk              (0x40000UL)               /*!< ATIM1OC5 (Bitfield-Mask: 0x01)                        */
#define OPAx_CAL_ATIM1OC4_Pos              (17UL)                    /*!< ATIM1OC4 (Bit 17)                                     */
#define OPAx_CAL_ATIM1OC4_Msk              (0x20000UL)               /*!< ATIM1OC4 (Bitfield-Mask: 0x01)                        */
#define OPAx_CAL_ATIM1TRGO_Pos             (16UL)                    /*!< ATIM1TRGO (Bit 16)                                    */
#define OPAx_CAL_ATIM1TRGO_Msk             (0x10000UL)               /*!< ATIM1TRGO (Bitfield-Mask: 0x01)                       */
#define OPAx_CAL_ADC2START1_Pos            (15UL)                    /*!< ADC2START1 (Bit 15)                                   */
#define OPAx_CAL_ADC2START1_Msk            (0x8000UL)                /*!< ADC2START1 (Bitfield-Mask: 0x01)                      */
#define OPAx_CAL_ADC1START1_Pos            (14UL)                    /*!< ADC1START1 (Bit 14)                                   */
#define OPAx_CAL_ADC1START1_Msk            (0x4000UL)                /*!< ADC1START1 (Bitfield-Mask: 0x01)                      */
#define OPAx_CAL_CLKDIV_Pos                (11UL)                    /*!< CLKDIV (Bit 11)                                       */
#define OPAx_CAL_CLKDIV_Msk                (0x3800UL)                /*!< CLKDIV (Bitfield-Mask: 0x07)                          */
#define OPAx_CAL_AZRUN_Pos                 (10UL)                    /*!< AZRUN (Bit 10)                                        */
#define OPAx_CAL_AZRUN_Msk                 (0x400UL)                 /*!< AZRUN (Bitfield-Mask: 0x01)                           */
#define OPAx_CAL_ADCSTART_Pos              (8UL)                     /*!< ADCSTART (Bit 8)                                      */
#define OPAx_CAL_ADCSTART_Msk              (0x100UL)                 /*!< ADCSTART (Bitfield-Mask: 0x01)                        */
#define OPAx_CAL_CALPERIOD_Pos             (4UL)                     /*!< CALPERIOD (Bit 4)                                     */
#define OPAx_CAL_CALPERIOD_Msk             (0xf0UL)                  /*!< CALPERIOD (Bitfield-Mask: 0x0f)                       */
#define OPAx_CAL_SOFTTRIG_Pos              (3UL)                     /*!< SOFTTRIG (Bit 3)                                      */
#define OPAx_CAL_SOFTTRIG_Msk              (0x8UL)                   /*!< SOFTTRIG (Bitfield-Mask: 0x01)                        */
#define OPAx_CAL_START_Pos                 (2UL)                     /*!< START (Bit 2)                                         */
#define OPAx_CAL_START_Msk                 (0x4UL)                   /*!< START (Bitfield-Mask: 0x01)                           */
#define OPAx_CAL_CALMODE_Pos               (1UL)                     /*!< CALMODE (Bit 1)                                       */
#define OPAx_CAL_CALMODE_Msk               (0x2UL)                   /*!< CALMODE (Bitfield-Mask: 0x01)                         */
#define OPAx_CAL_CALEN_Pos                 (0UL)                     /*!< CALEN (Bit 0)                                         */
#define OPAx_CAL_CALEN_Msk                 (0x1UL)                   /*!< CALEN (Bitfield-Mask: 0x01)                           */


/* =========================================================================================================================== */
/* ================                                            RAM                                            ================ */
/* =========================================================================================================================== */

/* ==========================================================  IER  ========================================================== */
#define RAM_IER_PARITY_Pos                (0UL)                     /*!< PARITY (Bit 0)                                        */
#define RAM_IER_PARITY_Msk                (0x1UL)                   /*!< PARITY (Bitfield-Mask: 0x01)                          */
/* =========================================================  ADDR  ========================================================== */
#define RAM_ADDR_ADDR_Pos                 (0UL)                     /*!< ADDR (Bit 0)                                          */
#define RAM_ADDR_ADDR_Msk                 (0xffffffffUL)            /*!< ADDR (Bitfield-Mask: 0xffffffff)                      */
/* ==========================================================  ISR  ========================================================== */
#define RAM_ISR_PARITY_Pos                (0UL)                     /*!< PARITY (Bit 0)                                        */
#define RAM_ISR_PARITY_Msk                (0x1UL)                   /*!< PARITY (Bitfield-Mask: 0x01)                          */
/* ==========================================================  ICR  ========================================================== */
#define RAM_ICR_PARITY_Pos                (0UL)                     /*!< PARITY (Bit 0)                                        */
#define RAM_ICR_PARITY_Msk                (0x1UL)                   /*!< PARITY (Bitfield-Mask: 0x01)                          */


/* =========================================================================================================================== */
/* ================                                            RTC                                            ================ */
/* =========================================================================================================================== */

/* ==========================================================  KEY  ========================================================== */
#define RTC_KEY_KEY_Pos                   (0UL)                     /*!< KEY (Bit 0)                                           */
#define RTC_KEY_KEY_Msk                   (0xffUL)                  /*!< KEY (Bitfield-Mask: 0xff)                             */
/* ==========================================================  CR0  ========================================================== */
#define RTC_CR0_START_Pos                 (7UL)                     /*!< START (Bit 7)                                         */
#define RTC_CR0_START_Msk                 (0x80UL)                  /*!< START (Bitfield-Mask: 0x01)                           */
#define RTC_CR0_RTC1HZ_Pos                (5UL)                     /*!< RTC1HZ (Bit 5)                                        */
#define RTC_CR0_RTC1HZ_Msk                (0x60UL)                  /*!< RTC1HZ (Bitfield-Mask: 0x03)                          */
#define RTC_CR0_H24_Pos                   (3UL)                     /*!< H24 (Bit 3)                                           */
#define RTC_CR0_H24_Msk                   (0x8UL)                   /*!< H24 (Bitfield-Mask: 0x01)                             */
#define RTC_CR0_INTERVAL_Pos              (0UL)                     /*!< INTERVAL (Bit 0)                                      */
#define RTC_CR0_INTERVAL_Msk              (0x7UL)                   /*!< INTERVAL (Bitfield-Mask: 0x07)                        */
/* ==========================================================  CR1  ========================================================== */
#define RTC_CR1_SOURCE_Pos                (8UL)                     /*!< SOURCE (Bit 8)                                        */
#define RTC_CR1_SOURCE_Msk                (0x700UL)                 /*!< SOURCE (Bitfield-Mask: 0x07)                          */
#define RTC_CR1_WAIT_Pos                  (2UL)                     /*!< WAIT (Bit 2)                                          */
#define RTC_CR1_WAIT_Msk                  (0x4UL)                   /*!< WAIT (Bitfield-Mask: 0x01)                            */
/* ==========================================================  CR2  ========================================================== */
#define RTC_CR2_ALARMBEN_Pos              (10UL)                    /*!< ALARMBEN (Bit 10)                                     */
#define RTC_CR2_ALARMBEN_Msk              (0x400UL)                 /*!< ALARMBEN (Bitfield-Mask: 0x01)                        */
#define RTC_CR2_ALARMAEN_Pos              (9UL)                     /*!< ALARMAEN (Bit 9)                                      */
#define RTC_CR2_ALARMAEN_Msk              (0x200UL)                 /*!< ALARMAEN (Bitfield-Mask: 0x01)                        */
#define RTC_CR2_AWTEN_Pos                 (7UL)                     /*!< AWTEN (Bit 7)                                         */
#define RTC_CR2_AWTEN_Msk                 (0x80UL)                  /*!< AWTEN (Bitfield-Mask: 0x01)                           */
#define RTC_CR2_TAMPEN_Pos                (6UL)                     /*!< TAMPEN (Bit 6)                                        */
#define RTC_CR2_TAMPEN_Msk                (0x40UL)                  /*!< TAMPEN (Bitfield-Mask: 0x01)                          */
#define RTC_CR2_RTCOUT_Pos                (4UL)                     /*!< RTCOUT (Bit 4)                                        */
#define RTC_CR2_RTCOUT_Msk                (0x30UL)                  /*!< RTCOUT (Bitfield-Mask: 0x03)                          */
#define RTC_CR2_TAMPEDGE_Pos              (3UL)                     /*!< TAMPEDGE (Bit 3)                                      */
#define RTC_CR2_TAMPEDGE_Msk              (0x8UL)                   /*!< TAMPEDGE (Bitfield-Mask: 0x01)                        */
#define RTC_CR2_AWTSRC_Pos                (2UL)                     /*!< AWTSRC (Bit 2)                                        */
#define RTC_CR2_AWTSRC_Msk                (0x4UL)                   /*!< AWTSRC (Bitfield-Mask: 0x01)                          */
#define RTC_CR2_AWTPRS_Pos                (0UL)                     /*!< AWTPRS (Bit 0)                                        */
#define RTC_CR2_AWTPRS_Msk                (0x3UL)                   /*!< AWTPRS (Bitfield-Mask: 0x03)                          */
/* ==========================================================  PSC  ========================================================== */
#define RTC_PSC_PSC1_Pos                  (20UL)                    /*!< PSC1 (Bit 20)                                         */
#define RTC_PSC_PSC1_Msk                  (0xff00000UL)             /*!< PSC1 (Bitfield-Mask: 0xff)                            */
#define RTC_PSC_PSC2_Pos                  (0UL)                     /*!< PSC2 (Bit 0)                                          */
#define RTC_PSC_PSC2_Msk                  (0xfffffUL)               /*!< PSC2 (Bitfield-Mask: 0xfffff)                         */
/* =========================================================  DATE  ========================================================== */
#define RTC_DATE_WEEK_Pos                 (24UL)                    /*!< WEEK (Bit 24)                                         */
#define RTC_DATE_WEEK_Msk                 (0x7000000UL)             /*!< WEEK (Bitfield-Mask: 0x07)                            */
#define RTC_DATE_YEAR_Pos                 (16UL)                    /*!< YEAR (Bit 16)                                         */
#define RTC_DATE_YEAR_Msk                 (0xff0000UL)              /*!< YEAR (Bitfield-Mask: 0xff)                            */
#define RTC_DATE_MONTH_Pos                (8UL)                     /*!< MONTH (Bit 8)                                         */
#define RTC_DATE_MONTH_Msk                (0x1f00UL)                /*!< MONTH (Bitfield-Mask: 0x1f)                           */
#define RTC_DATE_DAY_Pos                  (0UL)                     /*!< DAY (Bit 0)                                           */
#define RTC_DATE_DAY_Msk                  (0x3fUL)                  /*!< DAY (Bitfield-Mask: 0x3f)                             */
/* =========================================================  TIME  ========================================================== */
#define RTC_TIME_HOUR_Pos                 (16UL)                    /*!< HOUR (Bit 16)                                         */
#define RTC_TIME_HOUR_Msk                 (0x3f0000UL)              /*!< HOUR (Bitfield-Mask: 0x3f)                            */
#define RTC_TIME_MINUTE_Pos               (8UL)                     /*!< MINUTE (Bit 8)                                        */
#define RTC_TIME_MINUTE_Msk               (0x7f00UL)                /*!< MINUTE (Bitfield-Mask: 0x7f)                          */
#define RTC_TIME_SECOND_Pos               (0UL)                     /*!< SECOND (Bit 0)                                        */
#define RTC_TIME_SECOND_Msk               (0x7fUL)                  /*!< SECOND (Bitfield-Mask: 0x7f)                          */
/* =========================================================  SSCNT  ========================================================= */
#define RTC_SSCNT_SSCNT1_Pos              (20UL)                    /*!< SSCNT1 (Bit 20)                                       */
#define RTC_SSCNT_SSCNT1_Msk              (0x100000UL)              /*!< SSCNT1 (Bitfield-Mask: 0x01)                          */
#define RTC_SSCNT_SSCNT0_Pos              (0UL)                     /*!< SSCNT0 (Bit 0)                                        */
#define RTC_SSCNT_SSCNT0_Msk              (0xfffffUL)               /*!< SSCNT0 (Bitfield-Mask: 0xfffff)                       */
/* ========================================================  ALARMA  ========================================================= */
#define RTC_ALARMA_WEEKMASK_Pos           (24UL)                    /*!< WEEKMASK (Bit 24)                                     */
#define RTC_ALARMA_WEEKMASK_Msk           (0x7f000000UL)            /*!< WEEKMASK (Bitfield-Mask: 0x7f)                        */
#define RTC_ALARMA_HOUREN_Pos             (23UL)                    /*!< HOUREN (Bit 23)                                       */
#define RTC_ALARMA_HOUREN_Msk             (0x800000UL)              /*!< HOUREN (Bitfield-Mask: 0x01)                          */
#define RTC_ALARMA_HOUR_Pos               (16UL)                    /*!< HOUR (Bit 16)                                         */
#define RTC_ALARMA_HOUR_Msk               (0x3f0000UL)              /*!< HOUR (Bitfield-Mask: 0x3f)                            */
#define RTC_ALARMA_MINUTEEN_Pos           (15UL)                    /*!< MINUTEEN (Bit 15)                                     */
#define RTC_ALARMA_MINUTEEN_Msk           (0x8000UL)                /*!< MINUTEEN (Bitfield-Mask: 0x01)                        */
#define RTC_ALARMA_MINUTE_Pos             (8UL)                     /*!< MINUTE (Bit 8)                                        */
#define RTC_ALARMA_MINUTE_Msk             (0x7f00UL)                /*!< MINUTE (Bitfield-Mask: 0x7f)                          */
#define RTC_ALARMA_SECONDEN_Pos           (7UL)                     /*!< SECONDEN (Bit 7)                                      */
#define RTC_ALARMA_SECONDEN_Msk           (0x80UL)                  /*!< SECONDEN (Bitfield-Mask: 0x01)                        */
#define RTC_ALARMA_SECOND_Pos             (0UL)                     /*!< SECOND (Bit 0)                                        */
#define RTC_ALARMA_SECOND_Msk             (0x7fUL)                  /*!< SECOND (Bitfield-Mask: 0x7f)                          */
/* ========================================================  ALARMB  ========================================================= */
#define RTC_ALARMB_WEEKMASK_Pos           (24UL)                    /*!< WEEKMASK (Bit 24)                                     */
#define RTC_ALARMB_WEEKMASK_Msk           (0x7f000000UL)            /*!< WEEKMASK (Bitfield-Mask: 0x7f)                        */
#define RTC_ALARMB_HOUREN_Pos             (23UL)                    /*!< HOUREN (Bit 23)                                       */
#define RTC_ALARMB_HOUREN_Msk             (0x800000UL)              /*!< HOUREN (Bitfield-Mask: 0x01)                          */
#define RTC_ALARMB_HOUR_Pos               (16UL)                    /*!< HOUR (Bit 16)                                         */
#define RTC_ALARMB_HOUR_Msk               (0x3f0000UL)              /*!< HOUR (Bitfield-Mask: 0x3f)                            */
#define RTC_ALARMB_MINUTEEN_Pos           (15UL)                    /*!< MINUTEEN (Bit 15)                                     */
#define RTC_ALARMB_MINUTEEN_Msk           (0x8000UL)                /*!< MINUTEEN (Bitfield-Mask: 0x01)                        */
#define RTC_ALARMB_MINUTE_Pos             (8UL)                     /*!< MINUTE (Bit 8)                                        */
#define RTC_ALARMB_MINUTE_Msk             (0x7f00UL)                /*!< MINUTE (Bitfield-Mask: 0x7f)                          */
#define RTC_ALARMB_SECONDEN_Pos           (7UL)                     /*!< SECONDEN (Bit 7)                                      */
#define RTC_ALARMB_SECONDEN_Msk           (0x80UL)                  /*!< SECONDEN (Bitfield-Mask: 0x01)                        */
#define RTC_ALARMB_SECOND_Pos             (0UL)                     /*!< SECOND (Bit 0)                                        */
#define RTC_ALARMB_SECOND_Msk             (0x7fUL)                  /*!< SECOND (Bitfield-Mask: 0x7f)                          */
/* =======================================================  TAMPDATE  ======================================================== */
#define RTC_TAMPDATE_WEEK_Pos             (13UL)                    /*!< WEEK (Bit 13)                                         */
#define RTC_TAMPDATE_WEEK_Msk             (0xe000UL)                /*!< WEEK (Bitfield-Mask: 0x07)                            */
#define RTC_TAMPDATE_MONTH_Pos            (8UL)                     /*!< MONTH (Bit 8)                                         */
#define RTC_TAMPDATE_MONTH_Msk            (0x1f00UL)                /*!< MONTH (Bitfield-Mask: 0x1f)                           */
#define RTC_TAMPDATE_DAY_Pos              (0UL)                     /*!< DAY (Bit 0)                                           */
#define RTC_TAMPDATE_DAY_Msk              (0x3fUL)                  /*!< DAY (Bitfield-Mask: 0x3f)                             */
/* =======================================================  TAMPTIME  ======================================================== */
#define RTC_TAMPTIME_HOUR_Pos             (16UL)                    /*!< HOUR (Bit 16)                                         */
#define RTC_TAMPTIME_HOUR_Msk             (0x3f0000UL)              /*!< HOUR (Bitfield-Mask: 0x3f)                            */
#define RTC_TAMPTIME_MINUTE_Pos           (8UL)                     /*!< MINUTE (Bit 8)                                        */
#define RTC_TAMPTIME_MINUTE_Msk           (0x7f00UL)                /*!< MINUTE (Bitfield-Mask: 0x7f)                          */
#define RTC_TAMPTIME_SECOND_Pos           (0UL)                     /*!< SECOND (Bit 0)                                        */
#define RTC_TAMPTIME_SECOND_Msk           (0x7fUL)                  /*!< SECOND (Bitfield-Mask: 0x7f)                          */
/* ==========================================================  IER  ========================================================== */
#define RTC_IER_INTERVAL_Pos              (6UL)                     /*!< INTERVAL (Bit 6)                                      */
#define RTC_IER_INTERVAL_Msk              (0x40UL)                  /*!< INTERVAL (Bitfield-Mask: 0x01)                        */
#define RTC_IER_TAMPOV_Pos                (4UL)                     /*!< TAMPOV (Bit 4)                                        */
#define RTC_IER_TAMPOV_Msk                (0x10UL)                  /*!< TAMPOV (Bitfield-Mask: 0x01)                          */
#define RTC_IER_TAMP_Pos                  (3UL)                     /*!< TAMP (Bit 3)                                          */
#define RTC_IER_TAMP_Msk                  (0x8UL)                   /*!< TAMP (Bitfield-Mask: 0x01)                            */
#define RTC_IER_AWTIMER_Pos               (2UL)                     /*!< AWTIMER (Bit 2)                                       */
#define RTC_IER_AWTIMER_Msk               (0x4UL)                   /*!< AWTIMER (Bitfield-Mask: 0x01)                         */
#define RTC_IER_ALARMB_Pos                (1UL)                     /*!< ALARMB (Bit 1)                                        */
#define RTC_IER_ALARMB_Msk                (0x2UL)                   /*!< ALARMB (Bitfield-Mask: 0x01)                          */
#define RTC_IER_ALARMA_Pos                (0UL)                     /*!< ALARMA (Bit 0)                                        */
#define RTC_IER_ALARMA_Msk                (0x1UL)                   /*!< ALARMA (Bitfield-Mask: 0x01)                          */
/* ==========================================================  ISR  ========================================================== */
#define RTC_ISR_INTERVAL_Pos              (6UL)                     /*!< INTERVAL (Bit 6)                                      */
#define RTC_ISR_INTERVAL_Msk              (0x40UL)                  /*!< INTERVAL (Bitfield-Mask: 0x01)                        */
#define RTC_ISR_TAMPOV_Pos                (4UL)                     /*!< TAMPOV (Bit 4)                                        */
#define RTC_ISR_TAMPOV_Msk                (0x10UL)                  /*!< TAMPOV (Bitfield-Mask: 0x01)                          */
#define RTC_ISR_TAMP_Pos                  (3UL)                     /*!< TAMP (Bit 3)                                          */
#define RTC_ISR_TAMP_Msk                  (0x8UL)                   /*!< TAMP (Bitfield-Mask: 0x01)                            */
#define RTC_ISR_AWTIMER_Pos               (2UL)                     /*!< AWTIMER (Bit 2)                                       */
#define RTC_ISR_AWTIMER_Msk               (0x4UL)                   /*!< AWTIMER (Bitfield-Mask: 0x01)                         */
#define RTC_ISR_ALARMB_Pos                (1UL)                     /*!< ALARMB (Bit 1)                                        */
#define RTC_ISR_ALARMB_Msk                (0x2UL)                   /*!< ALARMB (Bitfield-Mask: 0x01)                          */
#define RTC_ISR_ALARMA_Pos                (0UL)                     /*!< ALARMA (Bit 0)                                        */
#define RTC_ISR_ALARMA_Msk                (0x1UL)                   /*!< ALARMA (Bitfield-Mask: 0x01)                          */
/* ==========================================================  ICR  ========================================================== */
#define RTC_ICR_INTERVAL_Pos              (6UL)                     /*!< INTERVAL (Bit 6)                                      */
#define RTC_ICR_INTERVAL_Msk              (0x40UL)                  /*!< INTERVAL (Bitfield-Mask: 0x01)                        */
#define RTC_ICR_TAMPOV_Pos                (4UL)                     /*!< TAMPOV (Bit 4)                                        */
#define RTC_ICR_TAMPOV_Msk                (0x10UL)                  /*!< TAMPOV (Bitfield-Mask: 0x01)                          */
#define RTC_ICR_TAMP_Pos                  (3UL)                     /*!< TAMP (Bit 3)                                          */
#define RTC_ICR_TAMP_Msk                  (0x8UL)                   /*!< TAMP (Bitfield-Mask: 0x01)                            */
#define RTC_ICR_AWTIMER_Pos               (2UL)                     /*!< AWTIMER (Bit 2)                                       */
#define RTC_ICR_AWTIMER_Msk               (0x4UL)                   /*!< AWTIMER (Bitfield-Mask: 0x01)                         */
#define RTC_ICR_ALARMB_Pos                (1UL)                     /*!< ALARMB (Bit 1)                                        */
#define RTC_ICR_ALARMB_Msk                (0x2UL)                   /*!< ALARMB (Bitfield-Mask: 0x01)                          */
#define RTC_ICR_ALARMA_Pos                (0UL)                     /*!< ALARMA (Bit 0)                                        */
#define RTC_ICR_ALARMA_Msk                (0x1UL)                   /*!< ALARMA (Bitfield-Mask: 0x01)                          */
/* ========================================================  AWTARR  ========================================================= */
#define RTC_AWTARR_ARR_Pos                (0UL)                     /*!< ARR (Bit 0)                                           */
#define RTC_AWTARR_ARR_Msk                (0xffffUL)                /*!< ARR (Bitfield-Mask: 0xffff)                           */
/* ========================================================  AWTCNT  ========================================================= */
#define RTC_AWTCNT_CNT_Pos                (0UL)                     /*!< CNT (Bit 0)                                           */
#define RTC_AWTCNT_CNT_Msk                (0xffffUL)                /*!< CNT (Bitfield-Mask: 0xffff)                           */
/* =======================================================  COMPCFR1  ======================================================== */
#define RTC_COMPCFR1_EN_Pos               (15UL)                    /*!< EN (Bit 15)                                           */
#define RTC_COMPCFR1_EN_Msk               (0x8000UL)                /*!< EN (Bitfield-Mask: 0x01)                              */
#define RTC_COMPCFR1_SIGN_Pos             (14UL)                    /*!< SIGN (Bit 14)                                         */
#define RTC_COMPCFR1_SIGN_Msk             (0x4000UL)                /*!< SIGN (Bitfield-Mask: 0x01)                            */
#define RTC_COMPCFR1_PERIOD_Pos           (12UL)                    /*!< PERIOD (Bit 12)                                       */
#define RTC_COMPCFR1_PERIOD_Msk           (0x3000UL)                /*!< PERIOD (Bitfield-Mask: 0x03)                          */
#define RTC_COMPCFR1_COMP_Pos             (0UL)                     /*!< COMP (Bit 0)                                          */
#define RTC_COMPCFR1_COMP_Msk             (0xfffUL)                 /*!< COMP (Bitfield-Mask: 0xfff)                           */


/* =========================================================================================================================== */
/* ================                                            SPI                                            ================ */
/* =========================================================================================================================== */

/* ==========================================================  CR1  ========================================================== */
#define SPIx_CR1_BR_Pos                   (24UL)                    /*!< BR (Bit 24)                                           */
#define SPIx_CR1_BR_Msk                   (0x7f000000UL)            /*!< BR (Bitfield-Mask: 0x7f)                              */
#define SPIx_CR1_SMP_Pos                  (20UL)                    /*!< SMP (Bit 20)                                          */
#define SPIx_CR1_SMP_Msk                  (0x100000UL)              /*!< SMP (Bitfield-Mask: 0x01)                             */
#define SPIx_CR1_MISOHD_Pos               (19UL)                    /*!< MISOHD (Bit 19)                                       */
#define SPIx_CR1_MISOHD_Msk               (0x80000UL)               /*!< MISOHD (Bitfield-Mask: 0x01)                          */
#define SPIx_CR1_FLTEN_Pos                (18UL)                    /*!< FLTEN (Bit 18)                                        */
#define SPIx_CR1_FLTEN_Msk                (0x40000UL)               /*!< FLTEN (Bitfield-Mask: 0x01)                           */
#define SPIx_CR1_MODE_Pos                 (16UL)                    /*!< MODE (Bit 16)                                         */
#define SPIx_CR1_MODE_Msk                 (0x30000UL)               /*!< MODE (Bitfield-Mask: 0x03)                            */
#define SPIx_CR1_GAP_Pos                  (12UL)                    /*!< GAP (Bit 12)                                          */
#define SPIx_CR1_GAP_Msk                  (0xf000UL)                /*!< GAP (Bitfield-Mask: 0x0f)                             */
#define SPIx_CR1_WIDTH_Pos                (8UL)                     /*!< WIDTH (Bit 8)                                         */
#define SPIx_CR1_WIDTH_Msk                (0xf00UL)                 /*!< WIDTH (Bitfield-Mask: 0x0f)                           */
#define SPIx_CR1_LSBF_Pos                 (7UL)                     /*!< LSBF (Bit 7)                                          */
#define SPIx_CR1_LSBF_Msk                 (0x80UL)                  /*!< LSBF (Bitfield-Mask: 0x01)                            */
#define SPIx_CR1_CPOL_Pos                 (3UL)                     /*!< CPOL (Bit 3)                                          */
#define SPIx_CR1_CPOL_Msk                 (0x8UL)                   /*!< CPOL (Bitfield-Mask: 0x01)                            */
#define SPIx_CR1_CPHA_Pos                 (2UL)                     /*!< CPHA (Bit 2)                                          */
#define SPIx_CR1_CPHA_Msk                 (0x4UL)                   /*!< CPHA (Bitfield-Mask: 0x01)                            */
#define SPIx_CR1_SSM_Pos                  (1UL)                     /*!< SSM (Bit 1)                                           */
#define SPIx_CR1_SSM_Msk                  (0x2UL)                   /*!< SSM (Bitfield-Mask: 0x01)                             */
#define SPIx_CR1_MSTR_Pos                 (0UL)                     /*!< MSTR (Bit 0)                                          */
#define SPIx_CR1_MSTR_Msk                 (0x1UL)                   /*!< MSTR (Bitfield-Mask: 0x01)                            */
/* ==========================================================  CR2  ========================================================== */
#define SPIx_CR2_DMATX_Pos                (2UL)                     /*!< DMATX (Bit 2)                                         */
#define SPIx_CR2_DMATX_Msk                (0x4UL)                   /*!< DMATX (Bitfield-Mask: 0x01)                           */
#define SPIx_CR2_DMARX_Pos                (1UL)                     /*!< DMARX (Bit 1)                                         */
#define SPIx_CR2_DMARX_Msk                (0x2UL)                   /*!< DMARX (Bitfield-Mask: 0x01)                           */
#define SPIx_CR2_EN_Pos                   (0UL)                     /*!< EN (Bit 0)                                            */
#define SPIx_CR2_EN_Msk                   (0x1UL)                   /*!< EN (Bitfield-Mask: 0x01)                              */
/* ==========================================================  CR3  ========================================================== */
#define SPIx_CR3_HDOE_Pos                 (0UL)                     /*!< HDOE (Bit 0)                                          */
#define SPIx_CR3_HDOE_Msk                 (0x1UL)                   /*!< HDOE (Bitfield-Mask: 0x01)                            */
/* ==========================================================  SSI  ========================================================== */
#define SPIx_SSI_SSI_Pos                  (0UL)                     /*!< SSI (Bit 0)                                           */
#define SPIx_SSI_SSI_Msk                  (0x1UL)                   /*!< SSI (Bitfield-Mask: 0x01)                             */
/* ==========================================================  IER  ========================================================== */
#define SPIx_IER_MODF_Pos                 (7UL)                     /*!< MODF (Bit 7)                                          */
#define SPIx_IER_MODF_Msk                 (0x80UL)                  /*!< MODF (Bitfield-Mask: 0x01)                            */
#define SPIx_IER_SSERR_Pos                (6UL)                     /*!< SSERR (Bit 6)                                         */
#define SPIx_IER_SSERR_Msk                (0x40UL)                  /*!< SSERR (Bitfield-Mask: 0x01)                           */
#define SPIx_IER_OV_Pos                   (5UL)                     /*!< OV (Bit 5)                                            */
#define SPIx_IER_OV_Msk                   (0x20UL)                  /*!< OV (Bitfield-Mask: 0x01)                              */
#define SPIx_IER_UD_Pos                   (4UL)                     /*!< UD (Bit 4)                                            */
#define SPIx_IER_UD_Msk                   (0x10UL)                  /*!< UD (Bitfield-Mask: 0x01)                              */
#define SPIx_IER_SSR_Pos                  (3UL)                     /*!< SSR (Bit 3)                                           */
#define SPIx_IER_SSR_Msk                  (0x8UL)                   /*!< SSR (Bitfield-Mask: 0x01)                             */
#define SPIx_IER_SSF_Pos                  (2UL)                     /*!< SSF (Bit 2)                                           */
#define SPIx_IER_SSF_Msk                  (0x4UL)                   /*!< SSF (Bitfield-Mask: 0x01)                             */
#define SPIx_IER_RXNE_Pos                 (1UL)                     /*!< RXNE (Bit 1)                                          */
#define SPIx_IER_RXNE_Msk                 (0x2UL)                   /*!< RXNE (Bitfield-Mask: 0x01)                            */
#define SPIx_IER_TXE_Pos                  (0UL)                     /*!< TXE (Bit 0)                                           */
#define SPIx_IER_TXE_Msk                  (0x1UL)                   /*!< TXE (Bitfield-Mask: 0x01)                             */
/* ==========================================================  ISR  ========================================================== */
#define SPIx_ISR_SSLVL_Pos                (9UL)                     /*!< SSLVL (Bit 9)                                         */
#define SPIx_ISR_SSLVL_Msk                (0x200UL)                 /*!< SSLVL (Bitfield-Mask: 0x01)                           */
#define SPIx_ISR_BUSY_Pos                 (8UL)                     /*!< BUSY (Bit 8)                                          */
#define SPIx_ISR_BUSY_Msk                 (0x100UL)                 /*!< BUSY (Bitfield-Mask: 0x01)                            */
#define SPIx_ISR_MODF_Pos                 (7UL)                     /*!< MODF (Bit 7)                                          */
#define SPIx_ISR_MODF_Msk                 (0x80UL)                  /*!< MODF (Bitfield-Mask: 0x01)                            */
#define SPIx_ISR_SSERR_Pos                (6UL)                     /*!< SSERR (Bit 6)                                         */
#define SPIx_ISR_SSERR_Msk                (0x40UL)                  /*!< SSERR (Bitfield-Mask: 0x01)                           */
#define SPIx_ISR_OV_Pos                   (5UL)                     /*!< OV (Bit 5)                                            */
#define SPIx_ISR_OV_Msk                   (0x20UL)                  /*!< OV (Bitfield-Mask: 0x01)                              */
#define SPIx_ISR_UD_Pos                   (4UL)                     /*!< UD (Bit 4)                                            */
#define SPIx_ISR_UD_Msk                   (0x10UL)                  /*!< UD (Bitfield-Mask: 0x01)                              */
#define SPIx_ISR_SSR_Pos                  (3UL)                     /*!< SSR (Bit 3)                                           */
#define SPIx_ISR_SSR_Msk                  (0x8UL)                   /*!< SSR (Bitfield-Mask: 0x01)                             */
#define SPIx_ISR_SSF_Pos                  (2UL)                     /*!< SSF (Bit 2)                                           */
#define SPIx_ISR_SSF_Msk                  (0x4UL)                   /*!< SSF (Bitfield-Mask: 0x01)                             */
#define SPIx_ISR_RXNE_Pos                 (1UL)                     /*!< RXNE (Bit 1)                                          */
#define SPIx_ISR_RXNE_Msk                 (0x2UL)                   /*!< RXNE (Bitfield-Mask: 0x01)                            */
#define SPIx_ISR_TXE_Pos                  (0UL)                     /*!< TXE (Bit 0)                                           */
#define SPIx_ISR_TXE_Msk                  (0x1UL)                   /*!< TXE (Bitfield-Mask: 0x01)                             */
/* ==========================================================  ICR  ========================================================== */
#define SPIx_ICR_MODF_Pos                 (7UL)                     /*!< MODF (Bit 7)                                          */
#define SPIx_ICR_MODF_Msk                 (0x80UL)                  /*!< MODF (Bitfield-Mask: 0x01)                            */
#define SPIx_ICR_SSERR_Pos                (6UL)                     /*!< SSERR (Bit 6)                                         */
#define SPIx_ICR_SSERR_Msk                (0x40UL)                  /*!< SSERR (Bitfield-Mask: 0x01)                           */
#define SPIx_ICR_OV_Pos                   (5UL)                     /*!< OV (Bit 5)                                            */
#define SPIx_ICR_OV_Msk                   (0x20UL)                  /*!< OV (Bitfield-Mask: 0x01)                              */
#define SPIx_ICR_UD_Pos                   (4UL)                     /*!< UD (Bit 4)                                            */
#define SPIx_ICR_UD_Msk                   (0x10UL)                  /*!< UD (Bitfield-Mask: 0x01)                              */
#define SPIx_ICR_SSR_Pos                  (3UL)                     /*!< SSR (Bit 3)                                           */
#define SPIx_ICR_SSR_Msk                  (0x8UL)                   /*!< SSR (Bitfield-Mask: 0x01)                             */
#define SPIx_ICR_SSF_Pos                  (2UL)                     /*!< SSF (Bit 2)                                           */
#define SPIx_ICR_SSF_Msk                  (0x4UL)                   /*!< SSF (Bitfield-Mask: 0x01)                             */
#define SPIx_ICR_RXNE_Pos                 (1UL)                     /*!< RXNE (Bit 1)                                          */
#define SPIx_ICR_RXNE_Msk                 (0x2UL)                   /*!< RXNE (Bitfield-Mask: 0x01)                            */
#define SPIx_ICR_FLUSH_Pos                (0UL)                     /*!< FLUSH (Bit 0)                                         */
#define SPIx_ICR_FLUSH_Msk                (0x1UL)                   /*!< FLUSH (Bitfield-Mask: 0x01)                           */
/* ==========================================================  DR  =========================================================== */
#define SPIx_DR_DR_Pos                    (0UL)                     /*!< DR (Bit 0)                                            */
#define SPIx_DR_DR_Msk                    (0xffffUL)                /*!< DR (Bitfield-Mask: 0xffff)                            */


/* =========================================================================================================================== */
/* ================                                          SYSCTRL                                          ================ */
/* =========================================================================================================================== */

/* ==========================================================  CR0  ========================================================== */
#define SYSCTRL_CR0_KEY_Pos               (16UL)                    /*!< KEY (Bit 16)                                          */
#define SYSCTRL_CR0_KEY_Msk               (0xffff0000UL)            /*!< KEY (Bitfield-Mask: 0xffff)                           */
#define SYSCTRL_CR0_HCLKPRS_Pos           (5UL)                     /*!< HCLKPRS (Bit 5)                                       */
#define SYSCTRL_CR0_HCLKPRS_Msk           (0xe0UL)                  /*!< HCLKPRS (Bitfield-Mask: 0x07)                         */
#define SYSCTRL_CR0_PCLKPRS_Pos           (3UL)                     /*!< PCLKPRS (Bit 3)                                       */
#define SYSCTRL_CR0_PCLKPRS_Msk           (0x18UL)                  /*!< PCLKPRS (Bitfield-Mask: 0x03)                         */
#define SYSCTRL_CR0_SYSCLK_Pos            (0UL)                     /*!< SYSCLK (Bit 0)                                        */
#define SYSCTRL_CR0_SYSCLK_Msk            (0x7UL)                   /*!< SYSCLK (Bitfield-Mask: 0x07)                          */
/* ==========================================================  CR1  ========================================================== */
#define SYSCTRL_CR1_KEY_Pos               (16UL)                    /*!< KEY (Bit 16)                                          */
#define SYSCTRL_CR1_KEY_Msk               (0xffff0000UL)            /*!< KEY (Bitfield-Mask: 0xffff)                           */
#define SYSCTRL_CR1_CLKCCS_Pos            (8UL)                     /*!< CLKCCS (Bit 8)                                        */
#define SYSCTRL_CR1_CLKCCS_Msk            (0x100UL)                 /*!< CLKCCS (Bitfield-Mask: 0x01)                          */
#define SYSCTRL_CR1_HSECCS_Pos            (7UL)                     /*!< HSECCS (Bit 7)                                        */
#define SYSCTRL_CR1_HSECCS_Msk            (0x80UL)                  /*!< HSECCS (Bitfield-Mask: 0x01)                          */
#define SYSCTRL_CR1_LSECCS_Pos            (6UL)                     /*!< LSECCS (Bit 6)                                        */
#define SYSCTRL_CR1_LSECCS_Msk            (0x40UL)                  /*!< LSECCS (Bitfield-Mask: 0x01)                          */
#define SYSCTRL_CR1_LSELOCK_Pos           (5UL)                     /*!< LSELOCK (Bit 5)                                       */
#define SYSCTRL_CR1_LSELOCK_Msk           (0x20UL)                  /*!< LSELOCK (Bitfield-Mask: 0x01)                         */
#define SYSCTRL_CR1_LSEEN_Pos             (4UL)                     /*!< LSEEN (Bit 4)                                         */
#define SYSCTRL_CR1_LSEEN_Msk             (0x10UL)                  /*!< LSEEN (Bitfield-Mask: 0x01)                           */
#define SYSCTRL_CR1_LSIEN_Pos             (3UL)                     /*!< LSIEN (Bit 3)                                         */
#define SYSCTRL_CR1_LSIEN_Msk             (0x8UL)                   /*!< LSIEN (Bitfield-Mask: 0x01)                           */
#define SYSCTRL_CR1_PLLEN_Pos             (2UL)                     /*!< PLLEN (Bit 2)                                         */
#define SYSCTRL_CR1_PLLEN_Msk             (0x4UL)                   /*!< PLLEN (Bitfield-Mask: 0x01)                           */
#define SYSCTRL_CR1_HSEEN_Pos             (1UL)                     /*!< HSEEN (Bit 1)                                         */
#define SYSCTRL_CR1_HSEEN_Msk             (0x2UL)                   /*!< HSEEN (Bitfield-Mask: 0x01)                           */
#define SYSCTRL_CR1_HSIEN_Pos             (0UL)                     /*!< HSIEN (Bit 0)                                         */
#define SYSCTRL_CR1_HSIEN_Msk             (0x1UL)                   /*!< HSIEN (Bitfield-Mask: 0x01)                           */
/* ==========================================================  CR2  ========================================================== */
#define SYSCTRL_CR2_KEY_Pos               (16UL)                    /*!< KEY (Bit 16)                                          */
#define SYSCTRL_CR2_KEY_Msk               (0xffff0000UL)            /*!< KEY (Bitfield-Mask: 0xffff)                           */
#define SYSCTRL_CR2_RAMBRKEN_Pos          (15UL)                    /*!< RAMBRKEN (Bit 15)                                     */
#define SYSCTRL_CR2_RAMBRKEN_Msk          (0x8000UL)                /*!< RAMBRKEN (Bitfield-Mask: 0x01)                        */
#define SYSCTRL_CR2_LVDBRKEN_Pos          (14UL)                    /*!< LVDBRKEN (Bit 14)                                     */
#define SYSCTRL_CR2_LVDBRKEN_Msk          (0x4000UL)                /*!< LVDBRKEN (Bitfield-Mask: 0x01)                        */
#define SYSCTRL_CR2_DSBRKEN_Pos           (13UL)                    /*!< DSBRKEN (Bit 13)                                      */
#define SYSCTRL_CR2_DSBRKEN_Msk           (0x2000UL)                /*!< DSBRKEN (Bitfield-Mask: 0x01)                         */
#define SYSCTRL_CR2_CLLBRKEN_Pos          (12UL)                    /*!< CLLBRKEN (Bit 12)                                     */
#define SYSCTRL_CR2_CLLBRKEN_Msk          (0x1000UL)                /*!< CLLBRKEN (Bitfield-Mask: 0x01)                        */
#define SYSCTRL_CR2_LSEBRKEN_Pos          (11UL)                    /*!< LSEBRKEN (Bit 11)                                     */
#define SYSCTRL_CR2_LSEBRKEN_Msk          (0x800UL)                 /*!< LSEBRKEN (Bitfield-Mask: 0x01)                        */
#define SYSCTRL_CR2_HSEBRKEN_Pos          (10UL)                    /*!< HSEBRKEN (Bit 10)                                     */
#define SYSCTRL_CR2_HSEBRKEN_Msk          (0x400UL)                 /*!< HSEBRKEN (Bitfield-Mask: 0x01)                        */
#define SYSCTRL_CR2_FLASHWAIT_Pos         (4UL)                     /*!< FLASHWAIT (Bit 4)                                     */
#define SYSCTRL_CR2_FLASHWAIT_Msk         (0x70UL)                  /*!< FLASHWAIT (Bitfield-Mask: 0x07)                       */
#define SYSCTRL_CR2_WAKEUPCLK_Pos         (3UL)                     /*!< WAKEUPCLK (Bit 3)                                     */
#define SYSCTRL_CR2_WAKEUPCLK_Msk         (0x8UL)                   /*!< WAKEUPCLK (Bitfield-Mask: 0x01)                       */
#define SYSCTRL_CR2_LOCKUP_Pos            (2UL)                     /*!< LOCKUP (Bit 2)                                        */
#define SYSCTRL_CR2_LOCKUP_Msk            (0x4UL)                   /*!< LOCKUP (Bitfield-Mask: 0x01)                          */
#define SYSCTRL_CR2_SWDIO_Pos             (1UL)                     /*!< SWDIO (Bit 1)                                         */
#define SYSCTRL_CR2_SWDIO_Msk             (0x2UL)                   /*!< SWDIO (Bitfield-Mask: 0x01)                           */
/* ==========================================================  HSI  ========================================================== */
#define SYSCTRL_HSI_STABLE_Pos            (15UL)                    /*!< STABLE (Bit 15)                                       */
#define SYSCTRL_HSI_STABLE_Msk            (0x8000UL)                /*!< STABLE (Bitfield-Mask: 0x01)                          */
#define SYSCTRL_HSI_DIV_Pos               (11UL)                    /*!< DIV (Bit 11)                                          */
#define SYSCTRL_HSI_DIV_Msk               (0x7800UL)                /*!< DIV (Bitfield-Mask: 0x0f)                             */
#define SYSCTRL_HSI_TRIM_Pos              (0UL)                     /*!< TRIM (Bit 0)                                          */
#define SYSCTRL_HSI_TRIM_Msk              (0x7ffUL)                 /*!< TRIM (Bitfield-Mask: 0x7ff)                           */
/* ==========================================================  LSI  ========================================================== */
#define SYSCTRL_LSI_STABLE_Pos            (15UL)                    /*!< STABLE (Bit 15)                                       */
#define SYSCTRL_LSI_STABLE_Msk            (0x8000UL)                /*!< STABLE (Bitfield-Mask: 0x01)                          */
#define SYSCTRL_LSI_WAITCYCLE_Pos         (10UL)                    /*!< WAITCYCLE (Bit 10)                                    */
#define SYSCTRL_LSI_WAITCYCLE_Msk         (0xc00UL)                 /*!< WAITCYCLE (Bitfield-Mask: 0x03)                       */
#define SYSCTRL_LSI_TRIM_Pos              (0UL)                     /*!< TRIM (Bit 0)                                          */
#define SYSCTRL_LSI_TRIM_Msk              (0x1ffUL)                 /*!< TRIM (Bitfield-Mask: 0x1ff)                           */
/* ==========================================================  HSE  ========================================================== */
#define SYSCTRL_HSE_DIGFLT_Pos            (24UL)                    /*!< DIGFLT (Bit 24)                                       */
#define SYSCTRL_HSE_DIGFLT_Msk            (0x1000000UL)             /*!< DIGFLT (Bitfield-Mask: 0x01)                          */
#define SYSCTRL_HSE_PDRIVER_Pos           (20UL)                    /*!< PDRIVER (Bit 20)                                      */
#define SYSCTRL_HSE_PDRIVER_Msk           (0xf00000UL)              /*!< PDRIVER (Bitfield-Mask: 0x0f)                         */
#define SYSCTRL_HSE_STABLE_Pos            (19UL)                    /*!< STABLE (Bit 19)                                       */
#define SYSCTRL_HSE_STABLE_Msk            (0x80000UL)               /*!< STABLE (Bitfield-Mask: 0x01)                          */
#define SYSCTRL_HSE_DETCNT_Pos            (8UL)                     /*!< DETCNT (Bit 8)                                        */
#define SYSCTRL_HSE_DETCNT_Msk            (0x7ff00UL)               /*!< DETCNT (Bitfield-Mask: 0x7ff)                         */
#define SYSCTRL_HSE_HEXENPOL_Pos          (7UL)                     /*!< HEXENPOL (Bit 7)                                      */
#define SYSCTRL_HSE_HEXENPOL_Msk          (0x80UL)                  /*!< HEXENPOL (Bitfield-Mask: 0x01)                        */
#define SYSCTRL_HSE_MODE_Pos              (6UL)                     /*!< MODE (Bit 6)                                          */
#define SYSCTRL_HSE_MODE_Msk              (0x40UL)                  /*!< MODE (Bitfield-Mask: 0x01)                            */
#define SYSCTRL_HSE_WAITCYCLE_Pos         (4UL)                     /*!< WAITCYCLE (Bit 4)                                     */
#define SYSCTRL_HSE_WAITCYCLE_Msk         (0x30UL)                  /*!< WAITCYCLE (Bitfield-Mask: 0x03)                       */
#define SYSCTRL_HSE_DRIVER_Pos            (0UL)                     /*!< DRIVER (Bit 0)                                        */
#define SYSCTRL_HSE_DRIVER_Msk            (0xfUL)                   /*!< DRIVER (Bitfield-Mask: 0x0f)                          */
/* ==========================================================  LSE  ========================================================== */
#define SYSCTRL_LSE_STABLE_Pos            (18UL)                    /*!< STABLE (Bit 18)                                       */
#define SYSCTRL_LSE_STABLE_Msk            (0x40000UL)               /*!< STABLE (Bitfield-Mask: 0x01)                          */
#define SYSCTRL_LSE_PINLOCK_Pos           (17UL)                    /*!< PINLOCK (Bit 17)                                      */
#define SYSCTRL_LSE_PINLOCK_Msk           (0x20000UL)               /*!< PINLOCK (Bitfield-Mask: 0x01)                         */
#define SYSCTRL_LSE_PDRIVER_Pos           (8UL)                     /*!< PDRIVER (Bit 8)                                       */
#define SYSCTRL_LSE_PDRIVER_Msk           (0xf00UL)                 /*!< PDRIVER (Bitfield-Mask: 0x0f)                         */
#define SYSCTRL_LSE_MODE_Pos              (6UL)                     /*!< MODE (Bit 6)                                          */
#define SYSCTRL_LSE_MODE_Msk              (0x40UL)                  /*!< MODE (Bitfield-Mask: 0x01)                            */
#define SYSCTRL_LSE_WAITCYCLE_Pos         (4UL)                     /*!< WAITCYCLE (Bit 4)                                     */
#define SYSCTRL_LSE_WAITCYCLE_Msk         (0x30UL)                  /*!< WAITCYCLE (Bitfield-Mask: 0x03)                       */
#define SYSCTRL_LSE_DRIVER_Pos            (0UL)                     /*!< DRIVER (Bit 0)                                        */
#define SYSCTRL_LSE_DRIVER_Msk            (0xfUL)                   /*!< DRIVER (Bitfield-Mask: 0x0f)                          */
/* ==========================================================  IER  ========================================================== */
#define SYSCTRL_IER_KEY_Pos               (16UL)                    /*!< KEY (Bit 16)                                          */
#define SYSCTRL_IER_KEY_Msk               (0xffff0000UL)            /*!< KEY (Bitfield-Mask: 0xffff)                           */
#define SYSCTRL_IER_HSEFAULT_Pos          (8UL)                     /*!< HSEFAULT (Bit 8)                                      */
#define SYSCTRL_IER_HSEFAULT_Msk          (0x100UL)                 /*!< HSEFAULT (Bitfield-Mask: 0x01)                        */
#define SYSCTRL_IER_LSEFAULT_Pos          (7UL)                     /*!< LSEFAULT (Bit 7)                                      */
#define SYSCTRL_IER_LSEFAULT_Msk          (0x80UL)                  /*!< LSEFAULT (Bitfield-Mask: 0x01)                        */
#define SYSCTRL_IER_HSEFAIL_Pos           (6UL)                     /*!< HSEFAIL (Bit 6)                                       */
#define SYSCTRL_IER_HSEFAIL_Msk           (0x40UL)                  /*!< HSEFAIL (Bitfield-Mask: 0x01)                         */
#define SYSCTRL_IER_LSEFAIL_Pos           (5UL)                     /*!< LSEFAIL (Bit 5)                                       */
#define SYSCTRL_IER_LSEFAIL_Msk           (0x20UL)                  /*!< LSEFAIL (Bitfield-Mask: 0x01)                         */
#define SYSCTRL_IER_LSERDY_Pos            (4UL)                     /*!< LSERDY (Bit 4)                                        */
#define SYSCTRL_IER_LSERDY_Msk            (0x10UL)                  /*!< LSERDY (Bitfield-Mask: 0x01)                          */
#define SYSCTRL_IER_LSIRDY_Pos            (3UL)                     /*!< LSIRDY (Bit 3)                                        */
#define SYSCTRL_IER_LSIRDY_Msk            (0x8UL)                   /*!< LSIRDY (Bitfield-Mask: 0x01)                          */
#define SYSCTRL_IER_PLLRDY_Pos            (2UL)                     /*!< PLLRDY (Bit 2)                                        */
#define SYSCTRL_IER_PLLRDY_Msk            (0x4UL)                   /*!< PLLRDY (Bitfield-Mask: 0x01)                          */
#define SYSCTRL_IER_HSERDY_Pos            (1UL)                     /*!< HSERDY (Bit 1)                                        */
#define SYSCTRL_IER_HSERDY_Msk            (0x2UL)                   /*!< HSERDY (Bitfield-Mask: 0x01)                          */
#define SYSCTRL_IER_HSIRDY_Pos            (0UL)                     /*!< HSIRDY (Bit 0)                                        */
#define SYSCTRL_IER_HSIRDY_Msk            (0x1UL)                   /*!< HSIRDY (Bitfield-Mask: 0x01)                          */
/* ==========================================================  ISR  ========================================================== */
#define SYSCTRL_ISR_LSESTABLE_Pos         (15UL)                    /*!< LSESTABLE (Bit 15)                                    */
#define SYSCTRL_ISR_LSESTABLE_Msk         (0x8000UL)                /*!< LSESTABLE (Bitfield-Mask: 0x01)                       */
#define SYSCTRL_ISR_LSISTABLE_Pos         (14UL)                    /*!< LSISTABLE (Bit 14)                                    */
#define SYSCTRL_ISR_LSISTABLE_Msk         (0x4000UL)                /*!< LSISTABLE (Bitfield-Mask: 0x01)                       */
#define SYSCTRL_ISR_PLLSTABLE_Pos         (13UL)                    /*!< PLLSTABLE (Bit 13)                                    */
#define SYSCTRL_ISR_PLLSTABLE_Msk         (0x2000UL)                /*!< PLLSTABLE (Bitfield-Mask: 0x01)                       */
#define SYSCTRL_ISR_HSESTABLE_Pos         (12UL)                    /*!< HSESTABLE (Bit 12)                                    */
#define SYSCTRL_ISR_HSESTABLE_Msk         (0x1000UL)                /*!< HSESTABLE (Bitfield-Mask: 0x01)                       */
#define SYSCTRL_ISR_HSISTABLE_Pos         (11UL)                    /*!< HSISTABLE (Bit 11)                                    */
#define SYSCTRL_ISR_HSISTABLE_Msk         (0x800UL)                 /*!< HSISTABLE (Bitfield-Mask: 0x01)                       */
#define SYSCTRL_ISR_HSEFAULT_Pos          (8UL)                     /*!< HSEFAULT (Bit 8)                                      */
#define SYSCTRL_ISR_HSEFAULT_Msk          (0x100UL)                 /*!< HSEFAULT (Bitfield-Mask: 0x01)                        */
#define SYSCTRL_ISR_LSEFAULT_Pos          (7UL)                     /*!< LSEFAULT (Bit 7)                                      */
#define SYSCTRL_ISR_LSEFAULT_Msk          (0x80UL)                  /*!< LSEFAULT (Bitfield-Mask: 0x01)                        */
#define SYSCTRL_ISR_HSEFAIL_Pos           (6UL)                     /*!< HSEFAIL (Bit 6)                                       */
#define SYSCTRL_ISR_HSEFAIL_Msk           (0x40UL)                  /*!< HSEFAIL (Bitfield-Mask: 0x01)                         */
#define SYSCTRL_ISR_LSEFAIL_Pos           (5UL)                     /*!< LSEFAIL (Bit 5)                                       */
#define SYSCTRL_ISR_LSEFAIL_Msk           (0x20UL)                  /*!< LSEFAIL (Bitfield-Mask: 0x01)                         */
#define SYSCTRL_ISR_LSERDY_Pos            (4UL)                     /*!< LSERDY (Bit 4)                                        */
#define SYSCTRL_ISR_LSERDY_Msk            (0x10UL)                  /*!< LSERDY (Bitfield-Mask: 0x01)                          */
#define SYSCTRL_ISR_LSIRDY_Pos            (3UL)                     /*!< LSIRDY (Bit 3)                                        */
#define SYSCTRL_ISR_LSIRDY_Msk            (0x8UL)                   /*!< LSIRDY (Bitfield-Mask: 0x01)                          */
#define SYSCTRL_ISR_PLLRDY_Pos            (2UL)                     /*!< PLLRDY (Bit 2)                                        */
#define SYSCTRL_ISR_PLLRDY_Msk            (0x4UL)                   /*!< PLLRDY (Bitfield-Mask: 0x01)                          */
#define SYSCTRL_ISR_HSERDY_Pos            (1UL)                     /*!< HSERDY (Bit 1)                                        */
#define SYSCTRL_ISR_HSERDY_Msk            (0x2UL)                   /*!< HSERDY (Bitfield-Mask: 0x01)                          */
#define SYSCTRL_ISR_HSIRDY_Pos            (0UL)                     /*!< HSIRDY (Bit 0)                                        */
#define SYSCTRL_ISR_HSIRDY_Msk            (0x1UL)                   /*!< HSIRDY (Bitfield-Mask: 0x01)                          */
/* ==========================================================  ICR  ========================================================== */
#define SYSCTRL_ICR_HSEFAULT_Pos          (8UL)                     /*!< HSEFAULT (Bit 8)                                      */
#define SYSCTRL_ICR_HSEFAULT_Msk          (0x100UL)                 /*!< HSEFAULT (Bitfield-Mask: 0x01)                        */
#define SYSCTRL_ICR_LSEFAULT_Pos          (7UL)                     /*!< LSEFAULT (Bit 7)                                      */
#define SYSCTRL_ICR_LSEFAULT_Msk          (0x80UL)                  /*!< LSEFAULT (Bitfield-Mask: 0x01)                        */
#define SYSCTRL_ICR_HSEFAIL_Pos           (6UL)                     /*!< HSEFAIL (Bit 6)                                       */
#define SYSCTRL_ICR_HSEFAIL_Msk           (0x40UL)                  /*!< HSEFAIL (Bitfield-Mask: 0x01)                         */
#define SYSCTRL_ICR_LSEFAIL_Pos           (5UL)                     /*!< LSEFAIL (Bit 5)                                       */
#define SYSCTRL_ICR_LSEFAIL_Msk           (0x20UL)                  /*!< LSEFAIL (Bitfield-Mask: 0x01)                         */
#define SYSCTRL_ICR_LSERDY_Pos            (4UL)                     /*!< LSERDY (Bit 4)                                        */
#define SYSCTRL_ICR_LSERDY_Msk            (0x10UL)                  /*!< LSERDY (Bitfield-Mask: 0x01)                          */
#define SYSCTRL_ICR_LSIRDY_Pos            (3UL)                     /*!< LSIRDY (Bit 3)                                        */
#define SYSCTRL_ICR_LSIRDY_Msk            (0x8UL)                   /*!< LSIRDY (Bitfield-Mask: 0x01)                          */
#define SYSCTRL_ICR_PLLRDY_Pos            (2UL)                     /*!< PLLRDY (Bit 2)                                        */
#define SYSCTRL_ICR_PLLRDY_Msk            (0x4UL)                   /*!< PLLRDY (Bitfield-Mask: 0x01)                          */
#define SYSCTRL_ICR_HSERDY_Pos            (1UL)                     /*!< HSERDY (Bit 1)                                        */
#define SYSCTRL_ICR_HSERDY_Msk            (0x2UL)                   /*!< HSERDY (Bitfield-Mask: 0x01)                          */
#define SYSCTRL_ICR_HSIRDY_Pos            (0UL)                     /*!< HSIRDY (Bit 0)                                        */
#define SYSCTRL_ICR_HSIRDY_Msk            (0x1UL)                   /*!< HSIRDY (Bitfield-Mask: 0x01)                          */
/* =========================================================  AHBEN  ========================================================= */
#define SYSCTRL_AHBEN_KEY_Pos             (16UL)                    /*!< KEY (Bit 16)                                          */
#define SYSCTRL_AHBEN_KEY_Msk             (0xffff0000UL)            /*!< KEY (Bitfield-Mask: 0xffff)                           */
#define SYSCTRL_AHBEN_CORDIC_Pos          (8UL)                     /*!< CORDIC (Bit 8)                                        */
#define SYSCTRL_AHBEN_CORDIC_Msk          (0x100UL)                 /*!< CORDIC (Bitfield-Mask: 0x01)                          */
#define SYSCTRL_AHBEN_GPIOF_Pos           (7UL)                     /*!< GPIOF (Bit 7)                                         */
#define SYSCTRL_AHBEN_GPIOF_Msk           (0x80UL)                  /*!< GPIOF (Bitfield-Mask: 0x01)                           */
#define SYSCTRL_AHBEN_GPIOC_Pos           (6UL)                     /*!< GPIOC (Bit 6)                                         */
#define SYSCTRL_AHBEN_GPIOC_Msk           (0x40UL)                  /*!< GPIOC (Bitfield-Mask: 0x01)                           */
#define SYSCTRL_AHBEN_GPIOB_Pos           (5UL)                     /*!< GPIOB (Bit 5)                                         */
#define SYSCTRL_AHBEN_GPIOB_Msk           (0x20UL)                  /*!< GPIOB (Bitfield-Mask: 0x01)                           */
#define SYSCTRL_AHBEN_GPIOA_Pos           (4UL)                     /*!< GPIOA (Bit 4)                                         */
#define SYSCTRL_AHBEN_GPIOA_Msk           (0x10UL)                  /*!< GPIOA (Bitfield-Mask: 0x01)                           */
#define SYSCTRL_AHBEN_EAU_Pos             (3UL)                     /*!< EAU (Bit 3)                                           */
#define SYSCTRL_AHBEN_EAU_Msk             (0x8UL)                   /*!< EAU (Bitfield-Mask: 0x01)                             */
#define SYSCTRL_AHBEN_CRC_Pos             (2UL)                     /*!< CRC (Bit 2)                                           */
#define SYSCTRL_AHBEN_CRC_Msk             (0x4UL)                   /*!< CRC (Bitfield-Mask: 0x01)                             */
#define SYSCTRL_AHBEN_FLASH_Pos           (1UL)                     /*!< FLASH (Bit 1)                                         */
#define SYSCTRL_AHBEN_FLASH_Msk           (0x2UL)                   /*!< FLASH (Bitfield-Mask: 0x01)                           */
#define SYSCTRL_AHBEN_DMA_Pos             (0UL)                     /*!< DMA (Bit 0)                                           */
#define SYSCTRL_AHBEN_DMA_Msk             (0x1UL)                   /*!< DMA (Bitfield-Mask: 0x01)                             */
/* ========================================================  APBEN1  ========================================================= */
#define SYSCTRL_APBEN1_KEY_Pos            (16UL)                    /*!< KEY (Bit 16)                                          */
#define SYSCTRL_APBEN1_KEY_Msk            (0xffff0000UL)            /*!< KEY (Bitfield-Mask: 0xffff)                           */
#define SYSCTRL_APBEN1_SPI3_Pos           (14UL)                    /*!< SPI3 (Bit 14)                                         */
#define SYSCTRL_APBEN1_SPI3_Msk           (0x4000UL)                /*!< SPI3 (Bitfield-Mask: 0x01)                            */
#define SYSCTRL_APBEN1_SPI2_Pos           (13UL)                    /*!< SPI2 (Bit 13)                                         */
#define SYSCTRL_APBEN1_SPI2_Msk           (0x2000UL)                /*!< SPI2 (Bitfield-Mask: 0x01)                            */
#define SYSCTRL_APBEN1_GTIM4_Pos          (12UL)                    /*!< GTIM4 (Bit 12)                                        */
#define SYSCTRL_APBEN1_GTIM4_Msk          (0x1000UL)                /*!< GTIM4 (Bitfield-Mask: 0x01)                           */
#define SYSCTRL_APBEN1_GTIM3_Pos          (11UL)                    /*!< GTIM3 (Bit 11)                                        */
#define SYSCTRL_APBEN1_GTIM3_Msk          (0x800UL)                 /*!< GTIM3 (Bitfield-Mask: 0x01)                           */
#define SYSCTRL_APBEN1_UART3_Pos          (8UL)                     /*!< UART3 (Bit 8)                                         */
#define SYSCTRL_APBEN1_UART3_Msk          (0x100UL)                 /*!< UART3 (Bitfield-Mask: 0x01)                           */
#define SYSCTRL_APBEN1_GTIM2_Pos          (7UL)                     /*!< GTIM2 (Bit 7)                                         */
#define SYSCTRL_APBEN1_GTIM2_Msk          (0x80UL)                  /*!< GTIM2 (Bitfield-Mask: 0x01)                           */
#define SYSCTRL_APBEN1_GTIM1_Pos          (6UL)                     /*!< GTIM1 (Bit 6)                                         */
#define SYSCTRL_APBEN1_GTIM1_Msk          (0x40UL)                  /*!< GTIM1 (Bitfield-Mask: 0x01)                           */
#define SYSCTRL_APBEN1_ATIM_Pos           (5UL)                     /*!< ATIM (Bit 5)                                          */
#define SYSCTRL_APBEN1_ATIM_Msk           (0x20UL)                  /*!< ATIM (Bitfield-Mask: 0x01)                            */
#define SYSCTRL_APBEN1_UART2_Pos          (4UL)                     /*!< UART2 (Bit 4)                                         */
#define SYSCTRL_APBEN1_UART2_Msk          (0x10UL)                  /*!< UART2 (Bitfield-Mask: 0x01)                           */
#define SYSCTRL_APBEN1_UART1_Pos          (3UL)                     /*!< UART1 (Bit 3)                                         */
#define SYSCTRL_APBEN1_UART1_Msk          (0x8UL)                   /*!< UART1 (Bitfield-Mask: 0x01)                           */
#define SYSCTRL_APBEN1_SPI1_Pos           (2UL)                     /*!< SPI1 (Bit 2)                                          */
#define SYSCTRL_APBEN1_SPI1_Msk           (0x4UL)                   /*!< SPI1 (Bitfield-Mask: 0x01)                            */
#define SYSCTRL_APBEN1_VC_Pos             (1UL)                     /*!< VC (Bit 1)                                            */
#define SYSCTRL_APBEN1_VC_Msk             (0x2UL)                   /*!< VC (Bitfield-Mask: 0x01)                              */
#define SYSCTRL_APBEN1_ADC_Pos            (0UL)                     /*!< ADC (Bit 0)                                           */
#define SYSCTRL_APBEN1_ADC_Msk            (0x1UL)                   /*!< ADC (Bitfield-Mask: 0x01)                             */
/* ========================================================  APBEN2  ========================================================= */
#define SYSCTRL_APBEN2_KEY_Pos            (16UL)                    /*!< KEY (Bit 16)                                          */
#define SYSCTRL_APBEN2_KEY_Msk            (0xffff0000UL)            /*!< KEY (Bitfield-Mask: 0xffff)                           */
#define SYSCTRL_APBEN2_HALLTIM_Pos        (12UL)                    /*!< HALLTIM (Bit 12)                                      */
#define SYSCTRL_APBEN2_HALLTIM_Msk        (0x1000UL)                /*!< HALLTIM (Bitfield-Mask: 0x01)                         */
#define SYSCTRL_APBEN2_I2C2_Pos           (11UL)                    /*!< I2C2 (Bit 11)                                         */
#define SYSCTRL_APBEN2_I2C2_Msk           (0x800UL)                 /*!< I2C2 (Bitfield-Mask: 0x01)                            */
#define SYSCTRL_APBEN2_DAC_Pos            (10UL)                    /*!< DAC (Bit 10)                                          */
#define SYSCTRL_APBEN2_DAC_Msk            (0x400UL)                 /*!< DAC (Bitfield-Mask: 0x01)                             */
#define SYSCTRL_APBEN2_OPA_Pos            (9UL)                     /*!< OPA (Bit 9)                                           */
#define SYSCTRL_APBEN2_OPA_Msk            (0x200UL)                 /*!< OPA (Bitfield-Mask: 0x01)                             */
#define SYSCTRL_APBEN2_LPTIM_Pos          (7UL)                     /*!< LPTIM (Bit 7)                                         */
#define SYSCTRL_APBEN2_LPTIM_Msk          (0x80UL)                  /*!< LPTIM (Bitfield-Mask: 0x01)                           */
#define SYSCTRL_APBEN2_I2C1_Pos           (6UL)                     /*!< I2C1 (Bit 6)                                          */
#define SYSCTRL_APBEN2_I2C1_Msk           (0x40UL)                  /*!< I2C1 (Bitfield-Mask: 0x01)                            */
#define SYSCTRL_APBEN2_WWDT_Pos           (5UL)                     /*!< WWDT (Bit 5)                                          */
#define SYSCTRL_APBEN2_WWDT_Msk           (0x20UL)                  /*!< WWDT (Bitfield-Mask: 0x01)                            */
#define SYSCTRL_APBEN2_IWDT_Pos           (4UL)                     /*!< IWDT (Bit 4)                                          */
#define SYSCTRL_APBEN2_IWDT_Msk           (0x10UL)                  /*!< IWDT (Bitfield-Mask: 0x01)                            */
#define SYSCTRL_APBEN2_BTIM123_Pos        (2UL)                     /*!< BTIM123 (Bit 2)                                       */
#define SYSCTRL_APBEN2_BTIM123_Msk        (0x4UL)                   /*!< BTIM123 (Bitfield-Mask: 0x01)                         */
#define SYSCTRL_APBEN2_RTC_Pos            (1UL)                     /*!< RTC (Bit 1)                                           */
#define SYSCTRL_APBEN2_RTC_Msk            (0x2UL)                   /*!< RTC (Bitfield-Mask: 0x01)                             */
/* ========================================================  AHBRST  ========================================================= */
#define SYSCTRL_AHBRST_CORDIC_Pos         (8UL)                     /*!< CORDIC (Bit 8)                                        */
#define SYSCTRL_AHBRST_CORDIC_Msk         (0x100UL)                 /*!< CORDIC (Bitfield-Mask: 0x01)                          */
#define SYSCTRL_AHBRST_GPIOF_Pos          (7UL)                     /*!< GPIOF (Bit 7)                                         */
#define SYSCTRL_AHBRST_GPIOF_Msk          (0x80UL)                  /*!< GPIOF (Bitfield-Mask: 0x01)                           */
#define SYSCTRL_AHBRST_GPIOC_Pos          (6UL)                     /*!< GPIOC (Bit 6)                                         */
#define SYSCTRL_AHBRST_GPIOC_Msk          (0x40UL)                  /*!< GPIOC (Bitfield-Mask: 0x01)                           */
#define SYSCTRL_AHBRST_GPIOB_Pos          (5UL)                     /*!< GPIOB (Bit 5)                                         */
#define SYSCTRL_AHBRST_GPIOB_Msk          (0x20UL)                  /*!< GPIOB (Bitfield-Mask: 0x01)                           */
#define SYSCTRL_AHBRST_GPIOA_Pos          (4UL)                     /*!< GPIOA (Bit 4)                                         */
#define SYSCTRL_AHBRST_GPIOA_Msk          (0x10UL)                  /*!< GPIOA (Bitfield-Mask: 0x01)                           */
#define SYSCTRL_AHBRST_EAU_Pos            (3UL)                     /*!< EAU (Bit 3)                                           */
#define SYSCTRL_AHBRST_EAU_Msk            (0x8UL)                   /*!< EAU (Bitfield-Mask: 0x01)                             */
#define SYSCTRL_AHBRST_CRC_Pos            (2UL)                     /*!< CRC (Bit 2)                                           */
#define SYSCTRL_AHBRST_CRC_Msk            (0x4UL)                   /*!< CRC (Bitfield-Mask: 0x01)                             */
#define SYSCTRL_AHBRST_FLASH_Pos          (1UL)                     /*!< FLASH (Bit 1)                                         */
#define SYSCTRL_AHBRST_FLASH_Msk          (0x2UL)                   /*!< FLASH (Bitfield-Mask: 0x01)                           */
#define SYSCTRL_AHBRST_DMA_Pos            (0UL)                     /*!< DMA (Bit 0)                                           */
#define SYSCTRL_AHBRST_DMA_Msk            (0x1UL)                   /*!< DMA (Bitfield-Mask: 0x01)                             */
/* ========================================================  APBRST1  ======================================================== */
#define SYSCTRL_APBRST1_SPI3_Pos          (14UL)                    /*!< SPI3 (Bit 14)                                         */
#define SYSCTRL_APBRST1_SPI3_Msk          (0x4000UL)                /*!< SPI3 (Bitfield-Mask: 0x01)                            */
#define SYSCTRL_APBRST1_SPI2_Pos          (13UL)                    /*!< SPI2 (Bit 13)                                         */
#define SYSCTRL_APBRST1_SPI2_Msk          (0x2000UL)                /*!< SPI2 (Bitfield-Mask: 0x01)                            */
#define SYSCTRL_APBRST1_GTIM4_Pos         (12UL)                    /*!< GTIM4 (Bit 12)                                        */
#define SYSCTRL_APBRST1_GTIM4_Msk         (0x1000UL)                /*!< GTIM4 (Bitfield-Mask: 0x01)                           */
#define SYSCTRL_APBRST1_GTIM3_Pos         (11UL)                    /*!< GTIM3 (Bit 11)                                        */
#define SYSCTRL_APBRST1_GTIM3_Msk         (0x800UL)                 /*!< GTIM3 (Bitfield-Mask: 0x01)                           */
#define SYSCTRL_APBRST1_UART3_Pos         (8UL)                     /*!< UART3 (Bit 8)                                         */
#define SYSCTRL_APBRST1_UART3_Msk         (0x100UL)                 /*!< UART3 (Bitfield-Mask: 0x01)                           */
#define SYSCTRL_APBRST1_GTIM2_Pos         (7UL)                     /*!< GTIM2 (Bit 7)                                         */
#define SYSCTRL_APBRST1_GTIM2_Msk         (0x80UL)                  /*!< GTIM2 (Bitfield-Mask: 0x01)                           */
#define SYSCTRL_APBRST1_GTIM1_Pos         (6UL)                     /*!< GTIM1 (Bit 6)                                         */
#define SYSCTRL_APBRST1_GTIM1_Msk         (0x40UL)                  /*!< GTIM1 (Bitfield-Mask: 0x01)                           */
#define SYSCTRL_APBRST1_ATIM_Pos          (5UL)                     /*!< ATIM (Bit 5)                                          */
#define SYSCTRL_APBRST1_ATIM_Msk          (0x20UL)                  /*!< ATIM (Bitfield-Mask: 0x01)                            */
#define SYSCTRL_APBRST1_UART2_Pos         (4UL)                     /*!< UART2 (Bit 4)                                         */
#define SYSCTRL_APBRST1_UART2_Msk         (0x10UL)                  /*!< UART2 (Bitfield-Mask: 0x01)                           */
#define SYSCTRL_APBRST1_UART1_Pos         (3UL)                     /*!< UART1 (Bit 3)                                         */
#define SYSCTRL_APBRST1_UART1_Msk         (0x8UL)                   /*!< UART1 (Bitfield-Mask: 0x01)                           */
#define SYSCTRL_APBRST1_SPI1_Pos          (2UL)                     /*!< SPI1 (Bit 2)                                          */
#define SYSCTRL_APBRST1_SPI1_Msk          (0x4UL)                   /*!< SPI1 (Bitfield-Mask: 0x01)                            */
#define SYSCTRL_APBRST1_VC_Pos            (1UL)                     /*!< VC (Bit 1)                                            */
#define SYSCTRL_APBRST1_VC_Msk            (0x2UL)                   /*!< VC (Bitfield-Mask: 0x01)                              */
#define SYSCTRL_APBRST1_ADC_Pos           (0UL)                     /*!< ADC (Bit 0)                                           */
#define SYSCTRL_APBRST1_ADC_Msk           (0x1UL)                   /*!< ADC (Bitfield-Mask: 0x01)                             */
/* ========================================================  APBRST2  ======================================================== */
#define SYSCTRL_APBRST2_HALLTIM_Pos       (12UL)                    /*!< HALLTIM (Bit 12)                                      */
#define SYSCTRL_APBRST2_HALLTIM_Msk       (0x1000UL)                /*!< HALLTIM (Bitfield-Mask: 0x01)                         */
#define SYSCTRL_APBRST2_I2C2_Pos          (11UL)                    /*!< I2C2 (Bit 11)                                         */
#define SYSCTRL_APBRST2_I2C2_Msk          (0x800UL)                 /*!< I2C2 (Bitfield-Mask: 0x01)                            */
#define SYSCTRL_APBRST2_DAC_Pos           (10UL)                    /*!< DAC (Bit 10)                                          */
#define SYSCTRL_APBRST2_DAC_Msk           (0x400UL)                 /*!< DAC (Bitfield-Mask: 0x01)                             */
#define SYSCTRL_APBRST2_OPA_Pos           (9UL)                     /*!< OPA (Bit 9)                                           */
#define SYSCTRL_APBRST2_OPA_Msk           (0x200UL)                 /*!< OPA (Bitfield-Mask: 0x01)                             */
#define SYSCTRL_APBRST2_LPTIM_Pos         (7UL)                     /*!< LPTIM (Bit 7)                                         */
#define SYSCTRL_APBRST2_LPTIM_Msk         (0x80UL)                  /*!< LPTIM (Bitfield-Mask: 0x01)                           */
#define SYSCTRL_APBRST2_I2C1_Pos          (6UL)                     /*!< I2C1 (Bit 6)                                          */
#define SYSCTRL_APBRST2_I2C1_Msk          (0x40UL)                  /*!< I2C1 (Bitfield-Mask: 0x01)                            */
#define SYSCTRL_APBRST2_WWDT_Pos          (5UL)                     /*!< WWDT (Bit 5)                                          */
#define SYSCTRL_APBRST2_WWDT_Msk          (0x20UL)                  /*!< WWDT (Bitfield-Mask: 0x01)                            */
#define SYSCTRL_APBRST2_IWDT_Pos          (4UL)                     /*!< IWDT (Bit 4)                                          */
#define SYSCTRL_APBRST2_IWDT_Msk          (0x10UL)                  /*!< IWDT (Bitfield-Mask: 0x01)                            */
#define SYSCTRL_APBRST2_BTIM123_Pos       (2UL)                     /*!< BTIM123 (Bit 2)                                       */
#define SYSCTRL_APBRST2_BTIM123_Msk       (0x4UL)                   /*!< BTIM123 (Bitfield-Mask: 0x01)                         */
#define SYSCTRL_APBRST2_RTC_Pos           (1UL)                     /*!< RTC (Bit 1)                                           */
#define SYSCTRL_APBRST2_RTC_Msk           (0x2UL)                   /*!< RTC (Bitfield-Mask: 0x01)                             */
/* =======================================================  RESETFLAG  ======================================================= */
#define SYSCTRL_RESETFLAG_SYSRESETREQ_Pos (9UL)                     /*!< SYSRESETREQ (Bit 9)                                   */
#define SYSCTRL_RESETFLAG_SYSRESETREQ_Msk (0x200UL)                 /*!< SYSRESETREQ (Bitfield-Mask: 0x01)                     */
#define SYSCTRL_RESETFLAG_LOCKUP_Pos      (8UL)                     /*!< LOCKUP (Bit 8)                                        */
#define SYSCTRL_RESETFLAG_LOCKUP_Msk      (0x100UL)                 /*!< LOCKUP (Bitfield-Mask: 0x01)                          */
#define SYSCTRL_RESETFLAG_RSTB_Pos        (6UL)                     /*!< RSTB (Bit 6)                                          */
#define SYSCTRL_RESETFLAG_RSTB_Msk        (0x40UL)                  /*!< RSTB (Bitfield-Mask: 0x01)                            */
#define SYSCTRL_RESETFLAG_WWDT_Pos        (5UL)                     /*!< WWDT (Bit 5)                                          */
#define SYSCTRL_RESETFLAG_WWDT_Msk        (0x20UL)                  /*!< WWDT (Bitfield-Mask: 0x01)                            */
#define SYSCTRL_RESETFLAG_IWDT_Pos        (4UL)                     /*!< IWDT (Bit 4)                                          */
#define SYSCTRL_RESETFLAG_IWDT_Msk        (0x10UL)                  /*!< IWDT (Bitfield-Mask: 0x01)                            */
#define SYSCTRL_RESETFLAG_LVD_Pos         (3UL)                     /*!< LVD (Bit 3)                                           */
#define SYSCTRL_RESETFLAG_LVD_Msk         (0x8UL)                   /*!< LVD (Bitfield-Mask: 0x01)                             */
#define SYSCTRL_RESETFLAG_POR_Pos         (0UL)                     /*!< POR (Bit 0)                                           */
#define SYSCTRL_RESETFLAG_POR_Msk         (0x1UL)                   /*!< POR (Bitfield-Mask: 0x01)                             */
/* =========================================================  DEBUG  ========================================================= */
#define SYSCTRL_DEBUG_HALLTIM_Pos         (11UL)                    /*!< HALLTIM (Bit 11)                                      */
#define SYSCTRL_DEBUG_HALLTIM_Msk         (0x800UL)                 /*!< HALLTIM (Bitfield-Mask: 0x01)                         */
#define SYSCTRL_DEBUG_WWDT_Pos            (10UL)                    /*!< WWDT (Bit 10)                                         */
#define SYSCTRL_DEBUG_WWDT_Msk            (0x400UL)                 /*!< WWDT (Bitfield-Mask: 0x01)                            */
#define SYSCTRL_DEBUG_IWDT_Pos            (9UL)                     /*!< IWDT (Bit 9)                                          */
#define SYSCTRL_DEBUG_IWDT_Msk            (0x200UL)                 /*!< IWDT (Bitfield-Mask: 0x01)                            */
#define SYSCTRL_DEBUG_RTC_Pos             (8UL)                     /*!< RTC (Bit 8)                                           */
#define SYSCTRL_DEBUG_RTC_Msk             (0x100UL)                 /*!< RTC (Bitfield-Mask: 0x01)                             */
#define SYSCTRL_DEBUG_LPTIM_Pos           (6UL)                     /*!< LPTIM (Bit 6)                                         */
#define SYSCTRL_DEBUG_LPTIM_Msk           (0x40UL)                  /*!< LPTIM (Bitfield-Mask: 0x01)                           */
#define SYSCTRL_DEBUG_BTIM123_Pos         (5UL)                     /*!< BTIM123 (Bit 5)                                       */
#define SYSCTRL_DEBUG_BTIM123_Msk         (0x20UL)                  /*!< BTIM123 (Bitfield-Mask: 0x01)                         */
#define SYSCTRL_DEBUG_GTIM4_Pos           (4UL)                     /*!< GTIM4 (Bit 4)                                         */
#define SYSCTRL_DEBUG_GTIM4_Msk           (0x10UL)                  /*!< GTIM4 (Bitfield-Mask: 0x01)                           */
#define SYSCTRL_DEBUG_GTIM3_Pos           (3UL)                     /*!< GTIM3 (Bit 3)                                         */
#define SYSCTRL_DEBUG_GTIM3_Msk           (0x8UL)                   /*!< GTIM3 (Bitfield-Mask: 0x01)                           */
#define SYSCTRL_DEBUG_GTIM2_Pos           (2UL)                     /*!< GTIM2 (Bit 2)                                         */
#define SYSCTRL_DEBUG_GTIM2_Msk           (0x4UL)                   /*!< GTIM2 (Bitfield-Mask: 0x01)                           */
#define SYSCTRL_DEBUG_GTIM1_Pos           (1UL)                     /*!< GTIM1 (Bit 1)                                         */
#define SYSCTRL_DEBUG_GTIM1_Msk           (0x2UL)                   /*!< GTIM1 (Bitfield-Mask: 0x01)                           */
#define SYSCTRL_DEBUG_ATIM_Pos            (0UL)                     /*!< ATIM (Bit 0)                                          */
#define SYSCTRL_DEBUG_ATIM_Msk            (0x1UL)                   /*!< ATIM (Bitfield-Mask: 0x01)                            */
/* ==========================================================  MCO  ========================================================== */
#define SYSCTRL_MCO_DIV_Pos               (4UL)                     /*!< DIV (Bit 4)                                           */
#define SYSCTRL_MCO_DIV_Msk               (0xf0UL)                  /*!< DIV (Bitfield-Mask: 0x0f)                             */
#define SYSCTRL_MCO_SOURCE_Pos            (0UL)                     /*!< SOURCE (Bit 0)                                        */
#define SYSCTRL_MCO_SOURCE_Msk            (0xfUL)                   /*!< SOURCE (Bitfield-Mask: 0x0f)                          */
/* ==========================================================  PLL  ========================================================== */
#define SYSCTRL_PLL_STABLE_Pos            (16UL)                    /*!< STABLE (Bit 16)                                       */
#define SYSCTRL_PLL_STABLE_Msk            (0x10000UL)               /*!< STABLE (Bitfield-Mask: 0x01)                          */
#define SYSCTRL_PLL_MUL_Pos               (8UL)                     /*!< MUL (Bit 8)                                           */
#define SYSCTRL_PLL_MUL_Msk               (0xff00UL)                /*!< MUL (Bitfield-Mask: 0xff)                             */
#define SYSCTRL_PLL_WAITCYCLE_Pos         (5UL)                     /*!< WAITCYCLE (Bit 5)                                     */
#define SYSCTRL_PLL_WAITCYCLE_Msk         (0xe0UL)                  /*!< WAITCYCLE (Bitfield-Mask: 0x07)                       */
#define SYSCTRL_PLL_DIV_Pos               (1UL)                     /*!< DIV (Bit 1)                                           */
#define SYSCTRL_PLL_DIV_Msk               (0x1eUL)                  /*!< DIV (Bitfield-Mask: 0x0f)                             */
#define SYSCTRL_PLL_SOURCE_Pos            (0UL)                     /*!< SOURCE (Bit 0)                                        */
#define SYSCTRL_PLL_SOURCE_Msk            (0x1UL)                   /*!< SOURCE (Bitfield-Mask: 0x01)                          */


/* =========================================================================================================================== */
/* ================                                            VC                                             ================ */
/* =========================================================================================================================== */

/* ==========================================================  CR0  ========================================================== */
#define VCx_CR0_INP_Pos                   (12UL)                    /*!< INP (Bit 12)                                          */
#define VCx_CR0_INP_Msk                   (0x3000UL)                /*!< INP (Bitfield-Mask: 0x03)                             */
#define VCx_CR0_INN_Pos                   (8UL)                     /*!< INN (Bit 8)                                           */
#define VCx_CR0_INN_Msk                   (0x300UL)                 /*!< INN (Bitfield-Mask: 0x03)                             */
#define VCx_CR0_WINDOW_Pos                (7UL)                     /*!< WINDOW (Bit 7)                                        */
#define VCx_CR0_WINDOW_Msk                (0x80UL)                  /*!< WINDOW (Bitfield-Mask: 0x01)                          */
#define VCx_CR0_POL_Pos                   (6UL)                     /*!< POL (Bit 6)                                           */
#define VCx_CR0_POL_Msk                   (0x40UL)                  /*!< POL (Bitfield-Mask: 0x01)                             */
#define VCx_CR0_IE_Pos                    (5UL)                     /*!< IE (Bit 5)                                            */
#define VCx_CR0_IE_Msk                    (0x20UL)                  /*!< IE (Bitfield-Mask: 0x01)                              */
#define VCx_CR0_HYS_Pos                   (3UL)                     /*!< HYS (Bit 3)                                           */
#define VCx_CR0_HYS_Msk                   (0x8UL)                   /*!< HYS (Bitfield-Mask: 0x01)                             */
#define VCx_CR0_RESP_Pos                  (1UL)                     /*!< RESP (Bit 1)                                          */
#define VCx_CR0_RESP_Msk                  (0x2UL)                   /*!< RESP (Bitfield-Mask: 0x01)                            */
#define VCx_CR0_EN_Pos                    (0UL)                     /*!< EN (Bit 0)                                            */
#define VCx_CR0_EN_Msk                    (0x1UL)                   /*!< EN (Bitfield-Mask: 0x01)                              */
/* ==========================================================  CR1  ========================================================== */
#define VCx_CR1_BLANKLVL_Pos              (11UL)                    /*!< BLANKLVL (Bit 11)                                     */
#define VCx_CR1_BLANKLVL_Msk              (0x800UL)                 /*!< BLANKLVL (Bitfield-Mask: 0x01)                        */
#define VCx_CR1_BLANKTIME_Pos             (8UL)                     /*!< BLANKTIME (Bit 8)                                     */
#define VCx_CR1_BLANKTIME_Msk             (0x700UL)                 /*!< BLANKTIME (Bitfield-Mask: 0x07)                       */
#define VCx_CR1_HIGHIE_Pos                (7UL)                     /*!< HIGHIE (Bit 7)                                        */
#define VCx_CR1_HIGHIE_Msk                (0x80UL)                  /*!< HIGHIE (Bitfield-Mask: 0x01)                          */
#define VCx_CR1_RISEIE_Pos                (6UL)                     /*!< RISEIE (Bit 6)                                        */
#define VCx_CR1_RISEIE_Msk                (0x40UL)                  /*!< RISEIE (Bitfield-Mask: 0x01)                          */
#define VCx_CR1_FALLIE_Pos                (5UL)                     /*!< FALLIE (Bit 5)                                        */
#define VCx_CR1_FALLIE_Msk                (0x20UL)                  /*!< FALLIE (Bitfield-Mask: 0x01)                          */
#define VCx_CR1_FLTCLK_Pos                (4UL)                     /*!< FLTCLK (Bit 4)                                        */
#define VCx_CR1_FLTCLK_Msk                (0x10UL)                  /*!< FLTCLK (Bitfield-Mask: 0x01)                          */
#define VCx_CR1_FLTTIME_Pos               (0UL)                     /*!< FLTTIME (Bit 0)                                       */
#define VCx_CR1_FLTTIME_Msk               (0xfUL)                   /*!< FLTTIME (Bitfield-Mask: 0x0f)                         */
/* ==========================================================  CR2  ========================================================== */
#define VCx_CR2_HALLTIM1TRGO_Pos          (31UL)                    /*!< HALLTIM1TRGO (Bit 31)                                 */
#define VCx_CR2_HALLTIM1TRGO_Msk          (0x80000000UL)            /*!< HALLTIM1TRGO (Bitfield-Mask: 0x01)                    */
#define VCx_CR2_BTIM3TRGO_Pos             (30UL)                    /*!< BTIM3TRGO (Bit 30)                                    */
#define VCx_CR2_BTIM3TRGO_Msk             (0x40000000UL)            /*!< BTIM3TRGO (Bitfield-Mask: 0x01)                       */
#define VCx_CR2_BTIM2TRGO_Pos             (29UL)                    /*!< BTIM2TRGO (Bit 29)                                    */
#define VCx_CR2_BTIM2TRGO_Msk             (0x20000000UL)            /*!< BTIM2TRGO (Bitfield-Mask: 0x01)                       */
#define VCx_CR2_BTIM1TRGO_Pos             (28UL)                    /*!< BTIM1TRGO (Bit 28)                                    */
#define VCx_CR2_BTIM1TRGO_Msk             (0x10000000UL)            /*!< BTIM1TRGO (Bitfield-Mask: 0x01)                       */
#define VCx_CR2_GTIM4OC4REFC_Pos          (27UL)                    /*!< GTIM4OC4REFC (Bit 27)                                 */
#define VCx_CR2_GTIM4OC4REFC_Msk          (0x8000000UL)             /*!< GTIM4OC4REFC (Bitfield-Mask: 0x01)                    */
#define VCx_CR2_GTIM4OC3REFC_Pos          (26UL)                    /*!< GTIM4OC3REFC (Bit 26)                                 */
#define VCx_CR2_GTIM4OC3REFC_Msk          (0x4000000UL)             /*!< GTIM4OC3REFC (Bitfield-Mask: 0x01)                    */
#define VCx_CR2_GTIM4OC2REFC_Pos          (25UL)                    /*!< GTIM4OC2REFC (Bit 25)                                 */
#define VCx_CR2_GTIM4OC2REFC_Msk          (0x2000000UL)             /*!< GTIM4OC2REFC (Bitfield-Mask: 0x01)                    */
#define VCx_CR2_GTIM4OC1REFC_Pos          (24UL)                    /*!< GTIM4OC1REFC (Bit 24)                                 */
#define VCx_CR2_GTIM4OC1REFC_Msk          (0x1000000UL)             /*!< GTIM4OC1REFC (Bitfield-Mask: 0x01)                    */
#define VCx_CR2_GTIM4TRGO_Pos             (23UL)                    /*!< GTIM4TRGO (Bit 23)                                    */
#define VCx_CR2_GTIM4TRGO_Msk             (0x800000UL)              /*!< GTIM4TRGO (Bitfield-Mask: 0x01)                       */
#define VCx_CR2_GTIM3OC4REFC_Pos          (22UL)                    /*!< GTIM3OC4REFC (Bit 22)                                 */
#define VCx_CR2_GTIM3OC4REFC_Msk          (0x400000UL)              /*!< GTIM3OC4REFC (Bitfield-Mask: 0x01)                    */
#define VCx_CR2_GTIM3OC3REFC_Pos          (21UL)                    /*!< GTIM3OC3REFC (Bit 21)                                 */
#define VCx_CR2_GTIM3OC3REFC_Msk          (0x200000UL)              /*!< GTIM3OC3REFC (Bitfield-Mask: 0x01)                    */
#define VCx_CR2_GTIM3OC2REFC_Pos          (20UL)                    /*!< GTIM3OC2REFC (Bit 20)                                 */
#define VCx_CR2_GTIM3OC2REFC_Msk          (0x100000UL)              /*!< GTIM3OC2REFC (Bitfield-Mask: 0x01)                    */
#define VCx_CR2_GTIM3OC1REFC_Pos          (19UL)                    /*!< GTIM3OC1REFC (Bit 19)                                 */
#define VCx_CR2_GTIM3OC1REFC_Msk          (0x80000UL)               /*!< GTIM3OC1REFC (Bitfield-Mask: 0x01)                    */
#define VCx_CR2_GTIM3TRGO_Pos             (18UL)                    /*!< GTIM3TRGO (Bit 18)                                    */
#define VCx_CR2_GTIM3TRGO_Msk             (0x40000UL)               /*!< GTIM3TRGO (Bitfield-Mask: 0x01)                       */
#define VCx_CR2_GTIM2OC4REFC_Pos          (17UL)                    /*!< GTIM2OC4REFC (Bit 17)                                 */
#define VCx_CR2_GTIM2OC4REFC_Msk          (0x20000UL)               /*!< GTIM2OC4REFC (Bitfield-Mask: 0x01)                    */
#define VCx_CR2_GTIM2OC3REFC_Pos          (16UL)                    /*!< GTIM2OC3REFC (Bit 16)                                 */
#define VCx_CR2_GTIM2OC3REFC_Msk          (0x10000UL)               /*!< GTIM2OC3REFC (Bitfield-Mask: 0x01)                    */
#define VCx_CR2_GTIM2OC2REFC_Pos          (15UL)                    /*!< GTIM2OC2REFC (Bit 15)                                 */
#define VCx_CR2_GTIM2OC2REFC_Msk          (0x8000UL)                /*!< GTIM2OC2REFC (Bitfield-Mask: 0x01)                    */
#define VCx_CR2_GTIM2OC1REFC_Pos          (14UL)                    /*!< GTIM2OC1REFC (Bit 14)                                 */
#define VCx_CR2_GTIM2OC1REFC_Msk          (0x4000UL)                /*!< GTIM2OC1REFC (Bitfield-Mask: 0x01)                    */
#define VCx_CR2_GTIM2TRGO_Pos             (13UL)                    /*!< GTIM2TRGO (Bit 13)                                    */
#define VCx_CR2_GTIM2TRGO_Msk             (0x2000UL)                /*!< GTIM2TRGO (Bitfield-Mask: 0x01)                       */
#define VCx_CR2_GTIM1OC4REFC_Pos          (12UL)                    /*!< GTIM1OC4REFC (Bit 12)                                 */
#define VCx_CR2_GTIM1OC4REFC_Msk          (0x1000UL)                /*!< GTIM1OC4REFC (Bitfield-Mask: 0x01)                    */
#define VCx_CR2_GTIM1OC3REFC_Pos          (11UL)                    /*!< GTIM1OC3REFC (Bit 11)                                 */
#define VCx_CR2_GTIM1OC3REFC_Msk          (0x800UL)                 /*!< GTIM1OC3REFC (Bitfield-Mask: 0x01)                    */
#define VCx_CR2_GTIM1OC2REFC_Pos          (10UL)                    /*!< GTIM1OC2REFC (Bit 10)                                 */
#define VCx_CR2_GTIM1OC2REFC_Msk          (0x400UL)                 /*!< GTIM1OC2REFC (Bitfield-Mask: 0x01)                    */
#define VCx_CR2_GTIM1OC1REFC_Pos          (9UL)                     /*!< GTIM1OC1REFC (Bit 9)                                  */
#define VCx_CR2_GTIM1OC1REFC_Msk          (0x200UL)                 /*!< GTIM1OC1REFC (Bitfield-Mask: 0x01)                    */
#define VCx_CR2_GTIM1TRGO_Pos             (8UL)                     /*!< GTIM1TRGO (Bit 8)                                     */
#define VCx_CR2_GTIM1TRGO_Msk             (0x100UL)                 /*!< GTIM1TRGO (Bitfield-Mask: 0x01)                       */
#define VCx_CR2_ATIMOC6REFC_Pos           (7UL)                     /*!< ATIM1OC6REFC (Bit 7)                                  */
#define VCx_CR2_ATIMOC6REFC_Msk           (0x80UL)                  /*!< ATIM1OC6REFC (Bitfield-Mask: 0x01)                    */
#define VCx_CR2_ATIMOC5REFC_Pos           (6UL)                     /*!< ATIM1OC5REFC (Bit 6)                                  */
#define VCx_CR2_ATIMOC5REFC_Msk           (0x40UL)                  /*!< ATIM1OC5REFC (Bitfield-Mask: 0x01)                    */
#define VCx_CR2_ATIMOC4REFC_Pos           (5UL)                     /*!< ATIM1OC4REFC (Bit 5)                                  */
#define VCx_CR2_ATIMOC4REFC_Msk           (0x20UL)                  /*!< ATIM1OC4REFC (Bitfield-Mask: 0x01)                    */
#define VCx_CR2_ATIMOC3REFC_Pos           (4UL)                     /*!< ATIM1OC3REFC (Bit 4)                                  */
#define VCx_CR2_ATIMOC3REFC_Msk           (0x10UL)                  /*!< ATIM1OC3REFC (Bitfield-Mask: 0x01)                    */
#define VCx_CR2_ATIMOC2REFC_Pos           (3UL)                     /*!< ATIM1OC2REFC (Bit 3)                                  */
#define VCx_CR2_ATIMOC2REFC_Msk           (0x8UL)                   /*!< ATIM1OC2REFC (Bitfield-Mask: 0x01)                    */
#define VCx_CR2_ATIMOC1REFC_Pos           (2UL)                     /*!< ATIM1OC1REFC (Bit 2)                                  */
#define VCx_CR2_ATIMOC1REFC_Msk           (0x4UL)                   /*!< ATIM1OC1REFC (Bitfield-Mask: 0x01)                    */
#define VCx_CR2_ATIMTRGO2_Pos             (1UL)                     /*!< ATIM1TRGO2 (Bit 1)                                    */
#define VCx_CR2_ATIMTRGO2_Msk             (0x2UL)                   /*!< ATIM1TRGO2 (Bitfield-Mask: 0x01)                      */
#define VCx_CR2_ATIMTRGO_Pos              (0UL)                     /*!< ATIM1TRGO (Bit 0)                                     */
#define VCx_CR2_ATIMTRGO_Msk              (0x1UL)                   /*!< ATIM1TRGO (Bitfield-Mask: 0x01)                       */
/* ==========================================================  SR  =========================================================== */
#define VCx_SR_FLTV_Pos                   (1UL)                     /*!< FLTV (Bit 1)                                          */
#define VCx_SR_FLTV_Msk                   (0x2UL)                   /*!< FLTV (Bitfield-Mask: 0x01)                            */
#define VCx_SR_INTF_Pos                   (0UL)                     /*!< INTF (Bit 0)                                          */
#define VCx_SR_INTF_Msk                   (0x1UL)                   /*!< INTF (Bitfield-Mask: 0x01)                            */


/* =========================================================================================================================== */
/* ================                                          VCREF                                           ================ */
/* =========================================================================================================================== */

/* ==========================================================  DIV  ========================================================== */
#define VC12REF_DIV_VIN_Pos               (5UL)                     /*!< VIN (Bit 5)                                           */
#define VC12REF_DIV_VIN_Msk               (0x20UL)                  /*!< VIN (Bitfield-Mask: 0x01)                             */
#define VC12REF_DIV_EN_Pos                (4UL)                     /*!< EN (Bit 4)                                            */
#define VC12REF_DIV_EN_Msk                (0x10UL)                  /*!< EN (Bitfield-Mask: 0x01)                              */
#define VC12REF_DIV_DIV_Pos               (0UL)                     /*!< DIV (Bit 0)                                           */
#define VC12REF_DIV_DIV_Msk               (0x7UL)                   /*!< DIV (Bitfield-Mask: 0x07)                             */


/* =========================================================================================================================== */
/* ================                                           WWDT                                            ================ */
/* =========================================================================================================================== */

/* ==========================================================  CR0  ========================================================== */
#define WWDT_CR0_EN_Pos                   (7UL)                     /*!< EN (Bit 7)                                            */
#define WWDT_CR0_EN_Msk                   (0x80UL)                  /*!< EN (Bitfield-Mask: 0x01)                              */
#define WWDT_CR0_WCNT_Pos                 (0UL)                     /*!< WCNT (Bit 0)                                          */
#define WWDT_CR0_WCNT_Msk                 (0x7fUL)                  /*!< WCNT (Bitfield-Mask: 0x7f)                            */
/* ==========================================================  CR1  ========================================================== */
#define WWDT_CR1_IE_Pos                   (10UL)                    /*!< IE (Bit 10)                                           */
#define WWDT_CR1_IE_Msk                   (0x400UL)                 /*!< IE (Bitfield-Mask: 0x01)                              */
#define WWDT_CR1_PRS_Pos                  (7UL)                     /*!< PRS (Bit 7)                                           */
#define WWDT_CR1_PRS_Msk                  (0x380UL)                 /*!< PRS (Bitfield-Mask: 0x07)                             */
#define WWDT_CR1_WINR_Pos                 (0UL)                     /*!< WINR (Bit 0)                                          */
#define WWDT_CR1_WINR_Msk                 (0x7fUL)                  /*!< WINR (Bitfield-Mask: 0x7f)                            */
/* ==========================================================  SR  =========================================================== */
#define WWDT_SR_POV_Pos                   (0UL)                     /*!< POV (Bit 0)                                           */
#define WWDT_SR_POV_Msk                   (0x1UL)                   /*!< POV (Bitfield-Mask: 0x01)                             */

/** @} */ /* End of group PosMask_peripherals */


#ifdef __cplusplus
}
#endif

#endif /* __CW32L012_H */


/** @} */ /* End of group cw32l012 */

